RISC-V: Fix `test' operand error with soft-float ABI being configured

[thirdparty/glibc.git] / ChangeLog

diff --git a/ChangeLog b/ChangeLog
index 60f76450e5feaf823ad126662674a95c168a3f7e..bef50d40f60f8d8f57cba46aa4429ffaa7071a8d 100644 (file)
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+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2019-03-30  Maciej W. Rozycki  <macro@wdc.com>
+
+       * sysdeps/unix/sysv/linux/riscv/configure.ac: Quote
+       $libc_cv_riscv_float_abi in `test' invocation.
+       * sysdeps/unix/sysv/linux/riscv/configure: Regenerate.
+
 2019-03-29  Paul A. Clarke  <pc@us.ibm.com>
 
        * sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_register): Replace inline