arch/arm/mach-iop13xx/include/mach/irqs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _IOP13XX_IRQS_H_
   3 #define _IOP13XX_IRQS_H_
   4
   5 #ifndef __ASSEMBLER__
   6 #include <linux/types.h>
   7
   8 /* INTPND0 CP6 R0 Page 3
   9  */
  10 static inline u32 read_intpnd_0(void)
  11 {
  12         u32 val;
  13         asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
  14         return val;
  15 }
  16
  17 /* INTPND1 CP6 R1 Page 3
  18  */
  19 static inline u32 read_intpnd_1(void)
  20 {
  21         u32 val;
  22         asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
  23         return val;
  24 }
  25
  26 /* INTPND2 CP6 R2 Page 3
  27  */
  28 static inline u32 read_intpnd_2(void)
  29 {
  30         u32 val;
  31         asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
  32         return val;
  33 }
  34
  35 /* INTPND3 CP6 R3 Page 3
  36  */
  37 static inline u32 read_intpnd_3(void)
  38 {
  39         u32 val;
  40         asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
  41         return val;
  42 }
  43 #endif
  44
  45 #define INTBASE 0
  46 #define INTSIZE_4 1
  47
  48 /*
  49  * iop34x chipset interrupts
  50  */
  51 #define IOP13XX_IRQ(x)          (IOP13XX_IRQ_OFS + (x))
  52
  53 /*
  54  * On IRQ or FIQ register
  55  */
  56 #define IRQ_IOP13XX_ADMA0_EOT   (0)
  57 #define IRQ_IOP13XX_ADMA0_EOC   (1)
  58 #define IRQ_IOP13XX_ADMA1_EOT   (2)
  59 #define IRQ_IOP13XX_ADMA1_EOC   (3)
  60 #define IRQ_IOP13XX_ADMA2_EOT   (4)
  61 #define IRQ_IOP13XX_ADMA2_EOC   (5)
  62 #define IRQ_IOP134_WATCHDOG     (6)
  63 #define IRQ_IOP13XX_RSVD_7      (7)
  64 #define IRQ_IOP13XX_TIMER0      (8)
  65 #define IRQ_IOP13XX_TIMER1      (9)
  66 #define IRQ_IOP13XX_I2C_0       (10)
  67 #define IRQ_IOP13XX_I2C_1       (11)
  68 #define IRQ_IOP13XX_MSG (12)
  69 #define IRQ_IOP13XX_MSGIBQ      (13)
  70 #define IRQ_IOP13XX_ATU_IM      (14)
  71 #define IRQ_IOP13XX_ATU_BIST    (15)
  72 #define IRQ_IOP13XX_PPMU        (16)
  73 #define IRQ_IOP13XX_COREPMU     (17)
  74 #define IRQ_IOP13XX_CORECACHE   (18)
  75 #define IRQ_IOP13XX_RSVD_19     (19)
  76 #define IRQ_IOP13XX_RSVD_20     (20)
  77 #define IRQ_IOP13XX_RSVD_21     (21)
  78 #define IRQ_IOP13XX_RSVD_22     (22)
  79 #define IRQ_IOP13XX_RSVD_23     (23)
  80 #define IRQ_IOP13XX_XINT0       (24)
  81 #define IRQ_IOP13XX_XINT1       (25)
  82 #define IRQ_IOP13XX_XINT2       (26)
  83 #define IRQ_IOP13XX_XINT3       (27)
  84 #define IRQ_IOP13XX_XINT4       (28)
  85 #define IRQ_IOP13XX_XINT5       (29)
  86 #define IRQ_IOP13XX_XINT6       (30)
  87 #define IRQ_IOP13XX_XINT7       (31)
  88                                       /* IINTSRC1 bit */
  89 #define IRQ_IOP13XX_XINT8       (32)  /* 0  */
  90 #define IRQ_IOP13XX_XINT9       (33)  /* 1  */
  91 #define IRQ_IOP13XX_XINT10      (34)  /* 2  */
  92 #define IRQ_IOP13XX_XINT11      (35)  /* 3  */
  93 #define IRQ_IOP13XX_XINT12      (36)  /* 4  */
  94 #define IRQ_IOP13XX_XINT13      (37)  /* 5  */
  95 #define IRQ_IOP13XX_XINT14      (38)  /* 6  */
  96 #define IRQ_IOP13XX_XINT15      (39)  /* 7  */
  97 #define IRQ_IOP13XX_RSVD_40     (40)  /* 8  */
  98 #define IRQ_IOP13XX_RSVD_41     (41)  /* 9  */
  99 #define IRQ_IOP13XX_RSVD_42     (42)  /* 10 */
 100 #define IRQ_IOP13XX_RSVD_43     (43)  /* 11 */
 101 #define IRQ_IOP13XX_RSVD_44     (44)  /* 12 */
 102 #define IRQ_IOP13XX_RSVD_45     (45)  /* 13 */
 103 #define IRQ_IOP13XX_RSVD_46     (46)  /* 14 */
 104 #define IRQ_IOP13XX_RSVD_47     (47)  /* 15 */
 105 #define IRQ_IOP13XX_RSVD_48     (48)  /* 16 */
 106 #define IRQ_IOP13XX_RSVD_49     (49)  /* 17 */
 107 #define IRQ_IOP13XX_RSVD_50     (50)  /* 18 */
 108 #define IRQ_IOP13XX_UART0       (51)  /* 19 */
 109 #define IRQ_IOP13XX_UART1       (52)  /* 20 */
 110 #define IRQ_IOP13XX_PBIE        (53)  /* 21 */
 111 #define IRQ_IOP13XX_ATU_CRW     (54)  /* 22 */
 112 #define IRQ_IOP13XX_ATU_ERR     (55)  /* 23 */
 113 #define IRQ_IOP13XX_MCU_ERR     (56)  /* 24 */
 114 #define IRQ_IOP13XX_ADMA0_ERR   (57)  /* 25 */
 115 #define IRQ_IOP13XX_ADMA1_ERR   (58)  /* 26 */
 116 #define IRQ_IOP13XX_ADMA2_ERR   (59)  /* 27 */
 117 #define IRQ_IOP13XX_RSVD_60     (60)  /* 28 */
 118 #define IRQ_IOP13XX_RSVD_61     (61)  /* 29 */
 119 #define IRQ_IOP13XX_MSG_ERR     (62)  /* 30 */
 120 #define IRQ_IOP13XX_RSVD_63     (63)  /* 31 */
 121                                       /* IINTSRC2 bit */
 122 #define IRQ_IOP13XX_INTERPROC   (64)  /* 0  */
 123 #define IRQ_IOP13XX_RSVD_65     (65)  /* 1  */
 124 #define IRQ_IOP13XX_RSVD_66     (66)  /* 2  */
 125 #define IRQ_IOP13XX_RSVD_67     (67)  /* 3  */
 126 #define IRQ_IOP13XX_RSVD_68     (68)  /* 4  */
 127 #define IRQ_IOP13XX_RSVD_69     (69)  /* 5  */
 128 #define IRQ_IOP13XX_RSVD_70     (70)  /* 6  */
 129 #define IRQ_IOP13XX_RSVD_71     (71)  /* 7  */
 130 #define IRQ_IOP13XX_RSVD_72     (72)  /* 8  */
 131 #define IRQ_IOP13XX_RSVD_73     (73)  /* 9  */
 132 #define IRQ_IOP13XX_RSVD_74     (74)  /* 10 */
 133 #define IRQ_IOP13XX_RSVD_75     (75)  /* 11 */
 134 #define IRQ_IOP13XX_RSVD_76     (76)  /* 12 */
 135 #define IRQ_IOP13XX_RSVD_77     (77)  /* 13 */
 136 #define IRQ_IOP13XX_RSVD_78     (78)  /* 14 */
 137 #define IRQ_IOP13XX_RSVD_79     (79)  /* 15 */
 138 #define IRQ_IOP13XX_RSVD_80     (80)  /* 16 */
 139 #define IRQ_IOP13XX_RSVD_81     (81)  /* 17 */
 140 #define IRQ_IOP13XX_RSVD_82     (82)  /* 18 */
 141 #define IRQ_IOP13XX_RSVD_83     (83)  /* 19 */
 142 #define IRQ_IOP13XX_RSVD_84     (84)  /* 20 */
 143 #define IRQ_IOP13XX_RSVD_85     (85)  /* 21 */
 144 #define IRQ_IOP13XX_RSVD_86     (86)  /* 22 */
 145 #define IRQ_IOP13XX_RSVD_87     (87)  /* 23 */
 146 #define IRQ_IOP13XX_RSVD_88     (88)  /* 24 */
 147 #define IRQ_IOP13XX_RSVD_89     (89)  /* 25 */
 148 #define IRQ_IOP13XX_RSVD_90     (90)  /* 26 */
 149 #define IRQ_IOP13XX_RSVD_91     (91)  /* 27 */
 150 #define IRQ_IOP13XX_RSVD_92     (92)  /* 28 */
 151 #define IRQ_IOP13XX_RSVD_93     (93)  /* 29 */
 152 #define IRQ_IOP13XX_SIB_ERR     (94)  /* 30 */
 153 #define IRQ_IOP13XX_SRAM_ERR    (95)  /* 31 */
 154                                       /* IINTSRC3 bit */
 155 #define IRQ_IOP13XX_I2C_2       (96)  /* 0  */
 156 #define IRQ_IOP13XX_ATUE_BIST   (97)  /* 1  */
 157 #define IRQ_IOP13XX_ATUE_CRW    (98)  /* 2  */
 158 #define IRQ_IOP13XX_ATUE_ERR    (99)  /* 3  */
 159 #define IRQ_IOP13XX_IMU (100) /* 4  */
 160 #define IRQ_IOP13XX_RSVD_101    (101) /* 5  */
 161 #define IRQ_IOP13XX_RSVD_102    (102) /* 6  */
 162 #define IRQ_IOP13XX_TPMI0_OUT   (103) /* 7  */
 163 #define IRQ_IOP13XX_TPMI1_OUT   (104) /* 8  */
 164 #define IRQ_IOP13XX_TPMI2_OUT   (105) /* 9  */
 165 #define IRQ_IOP13XX_TPMI3_OUT   (106) /* 10 */
 166 #define IRQ_IOP13XX_ATUE_IMA    (107) /* 11 */
 167 #define IRQ_IOP13XX_ATUE_IMB    (108) /* 12 */
 168 #define IRQ_IOP13XX_ATUE_IMC    (109) /* 13 */
 169 #define IRQ_IOP13XX_ATUE_IMD    (110) /* 14 */
 170 #define IRQ_IOP13XX_MU_MSI_TB   (111) /* 15 */
 171 #define IRQ_IOP13XX_RSVD_112    (112) /* 16 */
 172 #define IRQ_IOP13XX_INBD_MSI    (113) /* 17 */
 173 #define IRQ_IOP13XX_RSVD_114    (114) /* 18 */
 174 #define IRQ_IOP13XX_RSVD_115    (115) /* 19 */
 175 #define IRQ_IOP13XX_RSVD_116    (116) /* 20 */
 176 #define IRQ_IOP13XX_RSVD_117    (117) /* 21 */
 177 #define IRQ_IOP13XX_RSVD_118    (118) /* 22 */
 178 #define IRQ_IOP13XX_RSVD_119    (119) /* 23 */
 179 #define IRQ_IOP13XX_RSVD_120    (120) /* 24 */
 180 #define IRQ_IOP13XX_RSVD_121    (121) /* 25 */
 181 #define IRQ_IOP13XX_RSVD_122    (122) /* 26 */
 182 #define IRQ_IOP13XX_RSVD_123    (123) /* 27 */
 183 #define IRQ_IOP13XX_RSVD_124    (124) /* 28 */
 184 #define IRQ_IOP13XX_RSVD_125    (125) /* 29 */
 185 #define IRQ_IOP13XX_RSVD_126    (126) /* 30 */
 186 #define IRQ_IOP13XX_HPI (127) /* 31 */
 187
 188 #ifdef CONFIG_PCI_MSI
 189 #define IRQ_IOP13XX_MSI_0       (IRQ_IOP13XX_HPI + 1)
 190 #define NR_IOP13XX_IRQS         (IRQ_IOP13XX_MSI_0 + 128)
 191 #else
 192 #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
 193 #endif
 194
 195 #endif /* _IOP13XX_IRQ_H_ */