drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.h

   1 /*
   2  * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __NVKM_SECBOOT_ACR_R361_H__
  24 #define __NVKM_SECBOOT_ACR_R361_H__
  25
  26 #include "acr_r352.h"
  27
  28 /**
  29  * struct acr_r361_flcn_bl_desc - DMEM bootloader descriptor
  30  * @signature:          16B signature for secure code. 0s if no secure code
  31  * @ctx_dma:            DMA context to be used by BL while loading code/data
  32  * @code_dma_base:      256B-aligned Physical FB Address where code is located
  33  *                      (falcon's $xcbase register)
  34  * @non_sec_code_off:   offset from code_dma_base where the non-secure code is
  35  *                      located. The offset must be multiple of 256 to help perf
  36  * @non_sec_code_size:  the size of the nonSecure code part.
  37  * @sec_code_off:       offset from code_dma_base where the secure code is
  38  *                      located. The offset must be multiple of 256 to help perf
  39  * @sec_code_size:      offset from code_dma_base where the secure code is
  40  *                      located. The offset must be multiple of 256 to help perf
  41  * @code_entry_point:   code entry point which will be invoked by BL after
  42  *                      code is loaded.
  43  * @data_dma_base:      256B aligned Physical FB Address where data is located.
  44  *                      (falcon's $xdbase register)
  45  * @data_size:          size of data block. Should be multiple of 256B
  46  *
  47  * Structure used by the bootloader to load the rest of the code. This has
  48  * to be filled by host and copied into DMEM at offset provided in the
  49  * hsflcn_bl_desc.bl_desc_dmem_load_off.
  50  */
  51 struct acr_r361_flcn_bl_desc {
  52         u32 reserved[4];
  53         u32 signature[4];
  54         u32 ctx_dma;
  55         struct flcn_u64 code_dma_base;
  56         u32 non_sec_code_off;
  57         u32 non_sec_code_size;
  58         u32 sec_code_off;
  59         u32 sec_code_size;
  60         u32 code_entry_point;
  61         struct flcn_u64 data_dma_base;
  62         u32 data_size;
  63 };
  64
  65 void acr_r361_generate_hs_bl_desc(const struct hsf_load_header *, void *, u64);
  66
  67 extern const struct acr_r352_ls_func acr_r361_ls_fecs_func;
  68 extern const struct acr_r352_ls_func acr_r361_ls_gpccs_func;
  69 extern const struct acr_r352_ls_func acr_r361_ls_pmu_func;
  70 extern const struct acr_r352_lsf_func acr_r361_ls_sec2_func_0;
  71 #endif