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[thirdparty/kernel/linux.git] / drivers / net / ethernet / atheros / atlx / atl2.c
1 /*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23 #include <linux/atomic.h>
24 #include <linux/crc32.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/hardirq.h>
29 #include <linux/if_vlan.h>
30 #include <linux/in.h>
31 #include <linux/interrupt.h>
32 #include <linux/ip.h>
33 #include <linux/irqflags.h>
34 #include <linux/irqreturn.h>
35 #include <linux/mii.h>
36 #include <linux/net.h>
37 #include <linux/netdevice.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/pm.h>
41 #include <linux/skbuff.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44 #include <linux/string.h>
45 #include <linux/tcp.h>
46 #include <linux/timer.h>
47 #include <linux/types.h>
48 #include <linux/workqueue.h>
49
50 #include "atl2.h"
51
52 #define ATL2_DRV_VERSION "2.2.3"
53
54 static const char atl2_driver_name[] = "atl2";
55 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
56 static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
57 static const char atl2_driver_version[] = ATL2_DRV_VERSION;
58 static const struct ethtool_ops atl2_ethtool_ops;
59
60 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
61 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(ATL2_DRV_VERSION);
64
65 /*
66 * atl2_pci_tbl - PCI Device ID Table
67 */
68 static const struct pci_device_id atl2_pci_tbl[] = {
69 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
70 /* required last entry */
71 {0,}
72 };
73 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
74
75 static void atl2_check_options(struct atl2_adapter *adapter);
76
77 /**
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
85 static int atl2_sw_init(struct atl2_adapter *adapter)
86 {
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95 hw->revision_id = pdev->revision;
96
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
119
120 set_bit(__ATL2_DOWN, &adapter->flags);
121
122 return 0;
123 }
124
125 /**
126 * atl2_set_multi - Multicast and Promiscuous mode set
127 * @netdev: network interface device structure
128 *
129 * The set_multi entry point is called whenever the multicast address
130 * list or the network interface flags are updated. This routine is
131 * responsible for configuring the hardware for proper multicast,
132 * promiscuous mode, and all-multi behavior.
133 */
134 static void atl2_set_multi(struct net_device *netdev)
135 {
136 struct atl2_adapter *adapter = netdev_priv(netdev);
137 struct atl2_hw *hw = &adapter->hw;
138 struct netdev_hw_addr *ha;
139 u32 rctl;
140 u32 hash_value;
141
142 /* Check for Promiscuous and All Multicast modes */
143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
144
145 if (netdev->flags & IFF_PROMISC) {
146 rctl |= MAC_CTRL_PROMIS_EN;
147 } else if (netdev->flags & IFF_ALLMULTI) {
148 rctl |= MAC_CTRL_MC_ALL_EN;
149 rctl &= ~MAC_CTRL_PROMIS_EN;
150 } else
151 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
152
153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
154
155 /* clear the old settings from the multicast hash table */
156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
158
159 /* comoute mc addresses' hash value ,and put it into hash table */
160 netdev_for_each_mc_addr(ha, netdev) {
161 hash_value = atl2_hash_mc_addr(hw, ha->addr);
162 atl2_hash_set(hw, hash_value);
163 }
164 }
165
166 static void init_ring_ptrs(struct atl2_adapter *adapter)
167 {
168 /* Read / Write Ptr Initialize: */
169 adapter->txd_write_ptr = 0;
170 atomic_set(&adapter->txd_read_ptr, 0);
171
172 adapter->rxd_read_ptr = 0;
173 adapter->rxd_write_ptr = 0;
174
175 atomic_set(&adapter->txs_write_ptr, 0);
176 adapter->txs_next_clear = 0;
177 }
178
179 /**
180 * atl2_configure - Configure Transmit&Receive Unit after Reset
181 * @adapter: board private structure
182 *
183 * Configure the Tx /Rx unit of the MAC after a reset.
184 */
185 static int atl2_configure(struct atl2_adapter *adapter)
186 {
187 struct atl2_hw *hw = &adapter->hw;
188 u32 value;
189
190 /* clear interrupt status */
191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
192
193 /* set MAC Address */
194 value = (((u32)hw->mac_addr[2]) << 24) |
195 (((u32)hw->mac_addr[3]) << 16) |
196 (((u32)hw->mac_addr[4]) << 8) |
197 (((u32)hw->mac_addr[5]));
198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
199 value = (((u32)hw->mac_addr[0]) << 8) |
200 (((u32)hw->mac_addr[1]));
201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
202
203 /* HI base address */
204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
205 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
206
207 /* LO base address */
208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
209 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
211 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
213 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
214
215 /* element count */
216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
219
220 /* config Internal SRAM */
221 /*
222 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
224 */
225
226 /* config IPG/IFG */
227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
228 MAC_IPG_IFG_IPGT_SHIFT) |
229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
230 MAC_IPG_IFG_MIFG_SHIFT) |
231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
232 MAC_IPG_IFG_IPGR1_SHIFT)|
233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
234 MAC_IPG_IFG_IPGR2_SHIFT);
235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
236
237 /* config Half-Duplex Control */
238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
240 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
241 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
242 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
244 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
246
247 /* set Interrupt Moderator Timer */
248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
250
251 /* set Interrupt Clear Timer */
252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
253
254 /* set MTU */
255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
256 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
257
258 /* 1590 */
259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
260
261 /* flow control */
262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
264
265 /* Init mailbox */
266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
268
269 /* enable DMA read/write */
270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
272
273 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
274 if ((value & ISR_PHY_LINKDOWN) != 0)
275 value = 1; /* config failed */
276 else
277 value = 0;
278
279 /* clear all interrupt status */
280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
282 return value;
283 }
284
285 /**
286 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
287 * @adapter: board private structure
288 *
289 * Return 0 on success, negative on failure
290 */
291 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
292 {
293 struct pci_dev *pdev = adapter->pdev;
294 int size;
295 u8 offset = 0;
296
297 /* real ring DMA buffer */
298 adapter->ring_size = size =
299 adapter->txd_ring_size * 1 + 7 + /* dword align */
300 adapter->txs_ring_size * 4 + 7 + /* dword align */
301 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
302
303 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
304 &adapter->ring_dma);
305 if (!adapter->ring_vir_addr)
306 return -ENOMEM;
307 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
308
309 /* Init TXD Ring */
310 adapter->txd_dma = adapter->ring_dma ;
311 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
312 adapter->txd_dma += offset;
313 adapter->txd_ring = adapter->ring_vir_addr + offset;
314
315 /* Init TXS Ring */
316 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
317 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
318 adapter->txs_dma += offset;
319 adapter->txs_ring = (struct tx_pkt_status *)
320 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
321
322 /* Init RXD Ring */
323 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
324 offset = (adapter->rxd_dma & 127) ?
325 (128 - (adapter->rxd_dma & 127)) : 0;
326 if (offset > 7)
327 offset -= 8;
328 else
329 offset += (128 - 8);
330
331 adapter->rxd_dma += offset;
332 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
333 (adapter->txs_ring_size * 4 + offset));
334
335 /*
336 * Read / Write Ptr Initialize:
337 * init_ring_ptrs(adapter);
338 */
339 return 0;
340 }
341
342 /**
343 * atl2_irq_enable - Enable default interrupt generation settings
344 * @adapter: board private structure
345 */
346 static inline void atl2_irq_enable(struct atl2_adapter *adapter)
347 {
348 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
349 ATL2_WRITE_FLUSH(&adapter->hw);
350 }
351
352 /**
353 * atl2_irq_disable - Mask off interrupt generation on the NIC
354 * @adapter: board private structure
355 */
356 static inline void atl2_irq_disable(struct atl2_adapter *adapter)
357 {
358 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
359 ATL2_WRITE_FLUSH(&adapter->hw);
360 synchronize_irq(adapter->pdev->irq);
361 }
362
363 static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl)
364 {
365 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
366 /* enable VLAN tag insert/strip */
367 *ctrl |= MAC_CTRL_RMV_VLAN;
368 } else {
369 /* disable VLAN tag insert/strip */
370 *ctrl &= ~MAC_CTRL_RMV_VLAN;
371 }
372 }
373
374 static void atl2_vlan_mode(struct net_device *netdev,
375 netdev_features_t features)
376 {
377 struct atl2_adapter *adapter = netdev_priv(netdev);
378 u32 ctrl;
379
380 atl2_irq_disable(adapter);
381
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
383 __atl2_vlan_mode(features, &ctrl);
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
385
386 atl2_irq_enable(adapter);
387 }
388
389 static void atl2_restore_vlan(struct atl2_adapter *adapter)
390 {
391 atl2_vlan_mode(adapter->netdev, adapter->netdev->features);
392 }
393
394 static netdev_features_t atl2_fix_features(struct net_device *netdev,
395 netdev_features_t features)
396 {
397 /*
398 * Since there is no support for separate rx/tx vlan accel
399 * enable/disable make sure tx flag is always in same state as rx.
400 */
401 if (features & NETIF_F_HW_VLAN_CTAG_RX)
402 features |= NETIF_F_HW_VLAN_CTAG_TX;
403 else
404 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
405
406 return features;
407 }
408
409 static int atl2_set_features(struct net_device *netdev,
410 netdev_features_t features)
411 {
412 netdev_features_t changed = netdev->features ^ features;
413
414 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
415 atl2_vlan_mode(netdev, features);
416
417 return 0;
418 }
419
420 static void atl2_intr_rx(struct atl2_adapter *adapter)
421 {
422 struct net_device *netdev = adapter->netdev;
423 struct rx_desc *rxd;
424 struct sk_buff *skb;
425
426 do {
427 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
428 if (!rxd->status.update)
429 break; /* end of tx */
430
431 /* clear this flag at once */
432 rxd->status.update = 0;
433
434 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
435 int rx_size = (int)(rxd->status.pkt_size - 4);
436 /* alloc new buffer */
437 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
438 if (NULL == skb) {
439 /*
440 * Check that some rx space is free. If not,
441 * free one and mark stats->rx_dropped++.
442 */
443 netdev->stats.rx_dropped++;
444 break;
445 }
446 memcpy(skb->data, rxd->packet, rx_size);
447 skb_put(skb, rx_size);
448 skb->protocol = eth_type_trans(skb, netdev);
449 if (rxd->status.vlan) {
450 u16 vlan_tag = (rxd->status.vtag>>4) |
451 ((rxd->status.vtag&7) << 13) |
452 ((rxd->status.vtag&8) << 9);
453
454 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
455 }
456 netif_rx(skb);
457 netdev->stats.rx_bytes += rx_size;
458 netdev->stats.rx_packets++;
459 } else {
460 netdev->stats.rx_errors++;
461
462 if (rxd->status.ok && rxd->status.pkt_size <= 60)
463 netdev->stats.rx_length_errors++;
464 if (rxd->status.mcast)
465 netdev->stats.multicast++;
466 if (rxd->status.crc)
467 netdev->stats.rx_crc_errors++;
468 if (rxd->status.align)
469 netdev->stats.rx_frame_errors++;
470 }
471
472 /* advance write ptr */
473 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
474 adapter->rxd_write_ptr = 0;
475 } while (1);
476
477 /* update mailbox? */
478 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
479 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
480 }
481
482 static void atl2_intr_tx(struct atl2_adapter *adapter)
483 {
484 struct net_device *netdev = adapter->netdev;
485 u32 txd_read_ptr;
486 u32 txs_write_ptr;
487 struct tx_pkt_status *txs;
488 struct tx_pkt_header *txph;
489 int free_hole = 0;
490
491 do {
492 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
493 txs = adapter->txs_ring + txs_write_ptr;
494 if (!txs->update)
495 break; /* tx stop here */
496
497 free_hole = 1;
498 txs->update = 0;
499
500 if (++txs_write_ptr == adapter->txs_ring_size)
501 txs_write_ptr = 0;
502 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
503
504 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
505 txph = (struct tx_pkt_header *)
506 (((u8 *)adapter->txd_ring) + txd_read_ptr);
507
508 if (txph->pkt_size != txs->pkt_size) {
509 struct tx_pkt_status *old_txs = txs;
510 printk(KERN_WARNING
511 "%s: txs packet size not consistent with txd"
512 " txd_:0x%08x, txs_:0x%08x!\n",
513 adapter->netdev->name,
514 *(u32 *)txph, *(u32 *)txs);
515 printk(KERN_WARNING
516 "txd read ptr: 0x%x\n",
517 txd_read_ptr);
518 txs = adapter->txs_ring + txs_write_ptr;
519 printk(KERN_WARNING
520 "txs-behind:0x%08x\n",
521 *(u32 *)txs);
522 if (txs_write_ptr < 2) {
523 txs = adapter->txs_ring +
524 (adapter->txs_ring_size +
525 txs_write_ptr - 2);
526 } else {
527 txs = adapter->txs_ring + (txs_write_ptr - 2);
528 }
529 printk(KERN_WARNING
530 "txs-before:0x%08x\n",
531 *(u32 *)txs);
532 txs = old_txs;
533 }
534
535 /* 4for TPH */
536 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
537 if (txd_read_ptr >= adapter->txd_ring_size)
538 txd_read_ptr -= adapter->txd_ring_size;
539
540 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
541
542 /* tx statistics: */
543 if (txs->ok) {
544 netdev->stats.tx_bytes += txs->pkt_size;
545 netdev->stats.tx_packets++;
546 }
547 else
548 netdev->stats.tx_errors++;
549
550 if (txs->defer)
551 netdev->stats.collisions++;
552 if (txs->abort_col)
553 netdev->stats.tx_aborted_errors++;
554 if (txs->late_col)
555 netdev->stats.tx_window_errors++;
556 if (txs->underun)
557 netdev->stats.tx_fifo_errors++;
558 } while (1);
559
560 if (free_hole) {
561 if (netif_queue_stopped(adapter->netdev) &&
562 netif_carrier_ok(adapter->netdev))
563 netif_wake_queue(adapter->netdev);
564 }
565 }
566
567 static void atl2_check_for_link(struct atl2_adapter *adapter)
568 {
569 struct net_device *netdev = adapter->netdev;
570 u16 phy_data = 0;
571
572 spin_lock(&adapter->stats_lock);
573 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
574 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
575 spin_unlock(&adapter->stats_lock);
576
577 /* notify upper layer link down ASAP */
578 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
579 if (netif_carrier_ok(netdev)) { /* old link state: Up */
580 printk(KERN_INFO "%s: %s NIC Link is Down\n",
581 atl2_driver_name, netdev->name);
582 adapter->link_speed = SPEED_0;
583 netif_carrier_off(netdev);
584 netif_stop_queue(netdev);
585 }
586 }
587 schedule_work(&adapter->link_chg_task);
588 }
589
590 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
591 {
592 u16 phy_data;
593 spin_lock(&adapter->stats_lock);
594 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
595 spin_unlock(&adapter->stats_lock);
596 }
597
598 /**
599 * atl2_intr - Interrupt Handler
600 * @irq: interrupt number
601 * @data: pointer to a network interface device structure
602 */
603 static irqreturn_t atl2_intr(int irq, void *data)
604 {
605 struct atl2_adapter *adapter = netdev_priv(data);
606 struct atl2_hw *hw = &adapter->hw;
607 u32 status;
608
609 status = ATL2_READ_REG(hw, REG_ISR);
610 if (0 == status)
611 return IRQ_NONE;
612
613 /* link event */
614 if (status & ISR_PHY)
615 atl2_clear_phy_int(adapter);
616
617 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
618 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
619
620 /* check if PCIE PHY Link down */
621 if (status & ISR_PHY_LINKDOWN) {
622 if (netif_running(adapter->netdev)) { /* reset MAC */
623 ATL2_WRITE_REG(hw, REG_ISR, 0);
624 ATL2_WRITE_REG(hw, REG_IMR, 0);
625 ATL2_WRITE_FLUSH(hw);
626 schedule_work(&adapter->reset_task);
627 return IRQ_HANDLED;
628 }
629 }
630
631 /* check if DMA read/write error? */
632 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
633 ATL2_WRITE_REG(hw, REG_ISR, 0);
634 ATL2_WRITE_REG(hw, REG_IMR, 0);
635 ATL2_WRITE_FLUSH(hw);
636 schedule_work(&adapter->reset_task);
637 return IRQ_HANDLED;
638 }
639
640 /* link event */
641 if (status & (ISR_PHY | ISR_MANUAL)) {
642 adapter->netdev->stats.tx_carrier_errors++;
643 atl2_check_for_link(adapter);
644 }
645
646 /* transmit event */
647 if (status & ISR_TX_EVENT)
648 atl2_intr_tx(adapter);
649
650 /* rx exception */
651 if (status & ISR_RX_EVENT)
652 atl2_intr_rx(adapter);
653
654 /* re-enable Interrupt */
655 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
656 return IRQ_HANDLED;
657 }
658
659 static int atl2_request_irq(struct atl2_adapter *adapter)
660 {
661 struct net_device *netdev = adapter->netdev;
662 int flags, err = 0;
663
664 flags = IRQF_SHARED;
665 adapter->have_msi = true;
666 err = pci_enable_msi(adapter->pdev);
667 if (err)
668 adapter->have_msi = false;
669
670 if (adapter->have_msi)
671 flags &= ~IRQF_SHARED;
672
673 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
674 netdev);
675 }
676
677 /**
678 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
679 * @adapter: board private structure
680 *
681 * Free all transmit software resources
682 */
683 static void atl2_free_ring_resources(struct atl2_adapter *adapter)
684 {
685 struct pci_dev *pdev = adapter->pdev;
686 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
687 adapter->ring_dma);
688 }
689
690 /**
691 * atl2_open - Called when a network interface is made active
692 * @netdev: network interface device structure
693 *
694 * Returns 0 on success, negative value on failure
695 *
696 * The open entry point is called when a network interface is made
697 * active by the system (IFF_UP). At this point all resources needed
698 * for transmit and receive operations are allocated, the interrupt
699 * handler is registered with the OS, the watchdog timer is started,
700 * and the stack is notified that the interface is ready.
701 */
702 static int atl2_open(struct net_device *netdev)
703 {
704 struct atl2_adapter *adapter = netdev_priv(netdev);
705 int err;
706 u32 val;
707
708 /* disallow open during test */
709 if (test_bit(__ATL2_TESTING, &adapter->flags))
710 return -EBUSY;
711
712 /* allocate transmit descriptors */
713 err = atl2_setup_ring_resources(adapter);
714 if (err)
715 return err;
716
717 err = atl2_init_hw(&adapter->hw);
718 if (err) {
719 err = -EIO;
720 goto err_init_hw;
721 }
722
723 /* hardware has been reset, we need to reload some things */
724 atl2_set_multi(netdev);
725 init_ring_ptrs(adapter);
726
727 atl2_restore_vlan(adapter);
728
729 if (atl2_configure(adapter)) {
730 err = -EIO;
731 goto err_config;
732 }
733
734 err = atl2_request_irq(adapter);
735 if (err)
736 goto err_req_irq;
737
738 clear_bit(__ATL2_DOWN, &adapter->flags);
739
740 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
741
742 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
743 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
744 val | MASTER_CTRL_MANUAL_INT);
745
746 atl2_irq_enable(adapter);
747
748 return 0;
749
750 err_init_hw:
751 err_req_irq:
752 err_config:
753 atl2_free_ring_resources(adapter);
754 atl2_reset_hw(&adapter->hw);
755
756 return err;
757 }
758
759 static void atl2_down(struct atl2_adapter *adapter)
760 {
761 struct net_device *netdev = adapter->netdev;
762
763 /* signal that we're down so the interrupt handler does not
764 * reschedule our watchdog timer */
765 set_bit(__ATL2_DOWN, &adapter->flags);
766
767 netif_tx_disable(netdev);
768
769 /* reset MAC to disable all RX/TX */
770 atl2_reset_hw(&adapter->hw);
771 msleep(1);
772
773 atl2_irq_disable(adapter);
774
775 del_timer_sync(&adapter->watchdog_timer);
776 del_timer_sync(&adapter->phy_config_timer);
777 clear_bit(0, &adapter->cfg_phy);
778
779 netif_carrier_off(netdev);
780 adapter->link_speed = SPEED_0;
781 adapter->link_duplex = -1;
782 }
783
784 static void atl2_free_irq(struct atl2_adapter *adapter)
785 {
786 struct net_device *netdev = adapter->netdev;
787
788 free_irq(adapter->pdev->irq, netdev);
789
790 #ifdef CONFIG_PCI_MSI
791 if (adapter->have_msi)
792 pci_disable_msi(adapter->pdev);
793 #endif
794 }
795
796 /**
797 * atl2_close - Disables a network interface
798 * @netdev: network interface device structure
799 *
800 * Returns 0, this is not allowed to fail
801 *
802 * The close entry point is called when an interface is de-activated
803 * by the OS. The hardware is still under the drivers control, but
804 * needs to be disabled. A global MAC reset is issued to stop the
805 * hardware, and all transmit and receive resources are freed.
806 */
807 static int atl2_close(struct net_device *netdev)
808 {
809 struct atl2_adapter *adapter = netdev_priv(netdev);
810
811 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
812
813 atl2_down(adapter);
814 atl2_free_irq(adapter);
815 atl2_free_ring_resources(adapter);
816
817 return 0;
818 }
819
820 static inline int TxsFreeUnit(struct atl2_adapter *adapter)
821 {
822 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
823
824 return (adapter->txs_next_clear >= txs_write_ptr) ?
825 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
826 txs_write_ptr - 1) :
827 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
828 }
829
830 static inline int TxdFreeBytes(struct atl2_adapter *adapter)
831 {
832 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
833
834 return (adapter->txd_write_ptr >= txd_read_ptr) ?
835 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
836 txd_read_ptr - 1) :
837 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
838 }
839
840 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
841 struct net_device *netdev)
842 {
843 struct atl2_adapter *adapter = netdev_priv(netdev);
844 struct tx_pkt_header *txph;
845 u32 offset, copy_len;
846 int txs_unused;
847 int txbuf_unused;
848
849 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
850 dev_kfree_skb_any(skb);
851 return NETDEV_TX_OK;
852 }
853
854 if (unlikely(skb->len <= 0)) {
855 dev_kfree_skb_any(skb);
856 return NETDEV_TX_OK;
857 }
858
859 txs_unused = TxsFreeUnit(adapter);
860 txbuf_unused = TxdFreeBytes(adapter);
861
862 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
863 txs_unused < 1) {
864 /* not enough resources */
865 netif_stop_queue(netdev);
866 return NETDEV_TX_BUSY;
867 }
868
869 offset = adapter->txd_write_ptr;
870
871 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
872
873 *(u32 *)txph = 0;
874 txph->pkt_size = skb->len;
875
876 offset += 4;
877 if (offset >= adapter->txd_ring_size)
878 offset -= adapter->txd_ring_size;
879 copy_len = adapter->txd_ring_size - offset;
880 if (copy_len >= skb->len) {
881 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
882 offset += ((u32)(skb->len + 3) & ~3);
883 } else {
884 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
885 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
886 skb->len-copy_len);
887 offset = ((u32)(skb->len-copy_len + 3) & ~3);
888 }
889 #ifdef NETIF_F_HW_VLAN_CTAG_TX
890 if (skb_vlan_tag_present(skb)) {
891 u16 vlan_tag = skb_vlan_tag_get(skb);
892 vlan_tag = (vlan_tag << 4) |
893 (vlan_tag >> 13) |
894 ((vlan_tag >> 9) & 0x8);
895 txph->ins_vlan = 1;
896 txph->vlan = vlan_tag;
897 }
898 #endif
899 if (offset >= adapter->txd_ring_size)
900 offset -= adapter->txd_ring_size;
901 adapter->txd_write_ptr = offset;
902
903 /* clear txs before send */
904 adapter->txs_ring[adapter->txs_next_clear].update = 0;
905 if (++adapter->txs_next_clear == adapter->txs_ring_size)
906 adapter->txs_next_clear = 0;
907
908 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
909 (adapter->txd_write_ptr >> 2));
910
911 mmiowb();
912 dev_kfree_skb_any(skb);
913 return NETDEV_TX_OK;
914 }
915
916 /**
917 * atl2_change_mtu - Change the Maximum Transfer Unit
918 * @netdev: network interface device structure
919 * @new_mtu: new value for maximum frame size
920 *
921 * Returns 0 on success, negative on failure
922 */
923 static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
924 {
925 struct atl2_adapter *adapter = netdev_priv(netdev);
926 struct atl2_hw *hw = &adapter->hw;
927
928 /* set MTU */
929 netdev->mtu = new_mtu;
930 hw->max_frame_size = new_mtu;
931 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ETH_HLEN +
932 VLAN_HLEN + ETH_FCS_LEN);
933
934 return 0;
935 }
936
937 /**
938 * atl2_set_mac - Change the Ethernet Address of the NIC
939 * @netdev: network interface device structure
940 * @p: pointer to an address structure
941 *
942 * Returns 0 on success, negative on failure
943 */
944 static int atl2_set_mac(struct net_device *netdev, void *p)
945 {
946 struct atl2_adapter *adapter = netdev_priv(netdev);
947 struct sockaddr *addr = p;
948
949 if (!is_valid_ether_addr(addr->sa_data))
950 return -EADDRNOTAVAIL;
951
952 if (netif_running(netdev))
953 return -EBUSY;
954
955 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
956 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
957
958 atl2_set_mac_addr(&adapter->hw);
959
960 return 0;
961 }
962
963 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
964 {
965 struct atl2_adapter *adapter = netdev_priv(netdev);
966 struct mii_ioctl_data *data = if_mii(ifr);
967 unsigned long flags;
968
969 switch (cmd) {
970 case SIOCGMIIPHY:
971 data->phy_id = 0;
972 break;
973 case SIOCGMIIREG:
974 spin_lock_irqsave(&adapter->stats_lock, flags);
975 if (atl2_read_phy_reg(&adapter->hw,
976 data->reg_num & 0x1F, &data->val_out)) {
977 spin_unlock_irqrestore(&adapter->stats_lock, flags);
978 return -EIO;
979 }
980 spin_unlock_irqrestore(&adapter->stats_lock, flags);
981 break;
982 case SIOCSMIIREG:
983 if (data->reg_num & ~(0x1F))
984 return -EFAULT;
985 spin_lock_irqsave(&adapter->stats_lock, flags);
986 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
987 data->val_in)) {
988 spin_unlock_irqrestore(&adapter->stats_lock, flags);
989 return -EIO;
990 }
991 spin_unlock_irqrestore(&adapter->stats_lock, flags);
992 break;
993 default:
994 return -EOPNOTSUPP;
995 }
996 return 0;
997 }
998
999 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1000 {
1001 switch (cmd) {
1002 case SIOCGMIIPHY:
1003 case SIOCGMIIREG:
1004 case SIOCSMIIREG:
1005 return atl2_mii_ioctl(netdev, ifr, cmd);
1006 #ifdef ETHTOOL_OPS_COMPAT
1007 case SIOCETHTOOL:
1008 return ethtool_ioctl(ifr);
1009 #endif
1010 default:
1011 return -EOPNOTSUPP;
1012 }
1013 }
1014
1015 /**
1016 * atl2_tx_timeout - Respond to a Tx Hang
1017 * @netdev: network interface device structure
1018 */
1019 static void atl2_tx_timeout(struct net_device *netdev)
1020 {
1021 struct atl2_adapter *adapter = netdev_priv(netdev);
1022
1023 /* Do the reset outside of interrupt context */
1024 schedule_work(&adapter->reset_task);
1025 }
1026
1027 /**
1028 * atl2_watchdog - Timer Call-back
1029 * @data: pointer to netdev cast into an unsigned long
1030 */
1031 static void atl2_watchdog(struct timer_list *t)
1032 {
1033 struct atl2_adapter *adapter = from_timer(adapter, t, watchdog_timer);
1034
1035 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1036 u32 drop_rxd, drop_rxs;
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&adapter->stats_lock, flags);
1040 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1041 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1042 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1043
1044 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1045
1046 /* Reset the timer */
1047 mod_timer(&adapter->watchdog_timer,
1048 round_jiffies(jiffies + 4 * HZ));
1049 }
1050 }
1051
1052 /**
1053 * atl2_phy_config - Timer Call-back
1054 * @data: pointer to netdev cast into an unsigned long
1055 */
1056 static void atl2_phy_config(struct timer_list *t)
1057 {
1058 struct atl2_adapter *adapter = from_timer(adapter, t,
1059 phy_config_timer);
1060 struct atl2_hw *hw = &adapter->hw;
1061 unsigned long flags;
1062
1063 spin_lock_irqsave(&adapter->stats_lock, flags);
1064 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1065 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1066 MII_CR_RESTART_AUTO_NEG);
1067 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1068 clear_bit(0, &adapter->cfg_phy);
1069 }
1070
1071 static int atl2_up(struct atl2_adapter *adapter)
1072 {
1073 struct net_device *netdev = adapter->netdev;
1074 int err = 0;
1075 u32 val;
1076
1077 /* hardware has been reset, we need to reload some things */
1078
1079 err = atl2_init_hw(&adapter->hw);
1080 if (err) {
1081 err = -EIO;
1082 return err;
1083 }
1084
1085 atl2_set_multi(netdev);
1086 init_ring_ptrs(adapter);
1087
1088 atl2_restore_vlan(adapter);
1089
1090 if (atl2_configure(adapter)) {
1091 err = -EIO;
1092 goto err_up;
1093 }
1094
1095 clear_bit(__ATL2_DOWN, &adapter->flags);
1096
1097 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1098 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1099 MASTER_CTRL_MANUAL_INT);
1100
1101 atl2_irq_enable(adapter);
1102
1103 err_up:
1104 return err;
1105 }
1106
1107 static void atl2_reinit_locked(struct atl2_adapter *adapter)
1108 {
1109 WARN_ON(in_interrupt());
1110 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1111 msleep(1);
1112 atl2_down(adapter);
1113 atl2_up(adapter);
1114 clear_bit(__ATL2_RESETTING, &adapter->flags);
1115 }
1116
1117 static void atl2_reset_task(struct work_struct *work)
1118 {
1119 struct atl2_adapter *adapter;
1120 adapter = container_of(work, struct atl2_adapter, reset_task);
1121
1122 atl2_reinit_locked(adapter);
1123 }
1124
1125 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1126 {
1127 u32 value;
1128 struct atl2_hw *hw = &adapter->hw;
1129 struct net_device *netdev = adapter->netdev;
1130
1131 /* Config MAC CTRL Register */
1132 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1133
1134 /* duplex */
1135 if (FULL_DUPLEX == adapter->link_duplex)
1136 value |= MAC_CTRL_DUPLX;
1137
1138 /* flow control */
1139 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1140
1141 /* PAD & CRC */
1142 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1143
1144 /* preamble length */
1145 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1146 MAC_CTRL_PRMLEN_SHIFT);
1147
1148 /* vlan */
1149 __atl2_vlan_mode(netdev->features, &value);
1150
1151 /* filter mode */
1152 value |= MAC_CTRL_BC_EN;
1153 if (netdev->flags & IFF_PROMISC)
1154 value |= MAC_CTRL_PROMIS_EN;
1155 else if (netdev->flags & IFF_ALLMULTI)
1156 value |= MAC_CTRL_MC_ALL_EN;
1157
1158 /* half retry buffer */
1159 value |= (((u32)(adapter->hw.retry_buf &
1160 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1161
1162 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1163 }
1164
1165 static int atl2_check_link(struct atl2_adapter *adapter)
1166 {
1167 struct atl2_hw *hw = &adapter->hw;
1168 struct net_device *netdev = adapter->netdev;
1169 int ret_val;
1170 u16 speed, duplex, phy_data;
1171 int reconfig = 0;
1172
1173 /* MII_BMSR must read twise */
1174 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1175 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1176 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1177 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1178 u32 value;
1179 /* disable rx */
1180 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1181 value &= ~MAC_CTRL_RX_EN;
1182 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1183 adapter->link_speed = SPEED_0;
1184 netif_carrier_off(netdev);
1185 netif_stop_queue(netdev);
1186 }
1187 return 0;
1188 }
1189
1190 /* Link Up */
1191 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1192 if (ret_val)
1193 return ret_val;
1194 switch (hw->MediaType) {
1195 case MEDIA_TYPE_100M_FULL:
1196 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1197 reconfig = 1;
1198 break;
1199 case MEDIA_TYPE_100M_HALF:
1200 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1201 reconfig = 1;
1202 break;
1203 case MEDIA_TYPE_10M_FULL:
1204 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1205 reconfig = 1;
1206 break;
1207 case MEDIA_TYPE_10M_HALF:
1208 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1209 reconfig = 1;
1210 break;
1211 }
1212 /* link result is our setting */
1213 if (reconfig == 0) {
1214 if (adapter->link_speed != speed ||
1215 adapter->link_duplex != duplex) {
1216 adapter->link_speed = speed;
1217 adapter->link_duplex = duplex;
1218 atl2_setup_mac_ctrl(adapter);
1219 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1220 atl2_driver_name, netdev->name,
1221 adapter->link_speed,
1222 adapter->link_duplex == FULL_DUPLEX ?
1223 "Full Duplex" : "Half Duplex");
1224 }
1225
1226 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1227 netif_carrier_on(netdev);
1228 netif_wake_queue(netdev);
1229 }
1230 return 0;
1231 }
1232
1233 /* change original link status */
1234 if (netif_carrier_ok(netdev)) {
1235 u32 value;
1236 /* disable rx */
1237 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1238 value &= ~MAC_CTRL_RX_EN;
1239 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1240
1241 adapter->link_speed = SPEED_0;
1242 netif_carrier_off(netdev);
1243 netif_stop_queue(netdev);
1244 }
1245
1246 /* auto-neg, insert timer to re-config phy
1247 * (if interval smaller than 5 seconds, something strange) */
1248 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1249 if (!test_and_set_bit(0, &adapter->cfg_phy))
1250 mod_timer(&adapter->phy_config_timer,
1251 round_jiffies(jiffies + 5 * HZ));
1252 }
1253
1254 return 0;
1255 }
1256
1257 /**
1258 * atl2_link_chg_task - deal with link change event Out of interrupt context
1259 */
1260 static void atl2_link_chg_task(struct work_struct *work)
1261 {
1262 struct atl2_adapter *adapter;
1263 unsigned long flags;
1264
1265 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1266
1267 spin_lock_irqsave(&adapter->stats_lock, flags);
1268 atl2_check_link(adapter);
1269 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1270 }
1271
1272 static void atl2_setup_pcicmd(struct pci_dev *pdev)
1273 {
1274 u16 cmd;
1275
1276 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1277
1278 if (cmd & PCI_COMMAND_INTX_DISABLE)
1279 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1280 if (cmd & PCI_COMMAND_IO)
1281 cmd &= ~PCI_COMMAND_IO;
1282 if (0 == (cmd & PCI_COMMAND_MEMORY))
1283 cmd |= PCI_COMMAND_MEMORY;
1284 if (0 == (cmd & PCI_COMMAND_MASTER))
1285 cmd |= PCI_COMMAND_MASTER;
1286 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1287
1288 /*
1289 * some motherboards BIOS(PXE/EFI) driver may set PME
1290 * while they transfer control to OS (Windows/Linux)
1291 * so we should clear this bit before NIC work normally
1292 */
1293 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1294 }
1295
1296 #ifdef CONFIG_NET_POLL_CONTROLLER
1297 static void atl2_poll_controller(struct net_device *netdev)
1298 {
1299 disable_irq(netdev->irq);
1300 atl2_intr(netdev->irq, netdev);
1301 enable_irq(netdev->irq);
1302 }
1303 #endif
1304
1305
1306 static const struct net_device_ops atl2_netdev_ops = {
1307 .ndo_open = atl2_open,
1308 .ndo_stop = atl2_close,
1309 .ndo_start_xmit = atl2_xmit_frame,
1310 .ndo_set_rx_mode = atl2_set_multi,
1311 .ndo_validate_addr = eth_validate_addr,
1312 .ndo_set_mac_address = atl2_set_mac,
1313 .ndo_change_mtu = atl2_change_mtu,
1314 .ndo_fix_features = atl2_fix_features,
1315 .ndo_set_features = atl2_set_features,
1316 .ndo_do_ioctl = atl2_ioctl,
1317 .ndo_tx_timeout = atl2_tx_timeout,
1318 #ifdef CONFIG_NET_POLL_CONTROLLER
1319 .ndo_poll_controller = atl2_poll_controller,
1320 #endif
1321 };
1322
1323 /**
1324 * atl2_probe - Device Initialization Routine
1325 * @pdev: PCI device information struct
1326 * @ent: entry in atl2_pci_tbl
1327 *
1328 * Returns 0 on success, negative on failure
1329 *
1330 * atl2_probe initializes an adapter identified by a pci_dev structure.
1331 * The OS initialization, configuring of the adapter private structure,
1332 * and a hardware reset occur.
1333 */
1334 static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1335 {
1336 struct net_device *netdev;
1337 struct atl2_adapter *adapter;
1338 static int cards_found = 0;
1339 unsigned long mmio_start;
1340 int mmio_len;
1341 int err;
1342
1343 err = pci_enable_device(pdev);
1344 if (err)
1345 return err;
1346
1347 /*
1348 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1349 * until the kernel has the proper infrastructure to support 64-bit DMA
1350 * on these devices.
1351 */
1352 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1353 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1354 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1355 err = -EIO;
1356 goto err_dma;
1357 }
1358
1359 /* Mark all PCI regions associated with PCI device
1360 * pdev as being reserved by owner atl2_driver_name */
1361 err = pci_request_regions(pdev, atl2_driver_name);
1362 if (err)
1363 goto err_pci_reg;
1364
1365 /* Enables bus-mastering on the device and calls
1366 * pcibios_set_master to do the needed arch specific settings */
1367 pci_set_master(pdev);
1368
1369 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1370 if (!netdev) {
1371 err = -ENOMEM;
1372 goto err_alloc_etherdev;
1373 }
1374
1375 SET_NETDEV_DEV(netdev, &pdev->dev);
1376
1377 pci_set_drvdata(pdev, netdev);
1378 adapter = netdev_priv(netdev);
1379 adapter->netdev = netdev;
1380 adapter->pdev = pdev;
1381 adapter->hw.back = adapter;
1382
1383 mmio_start = pci_resource_start(pdev, 0x0);
1384 mmio_len = pci_resource_len(pdev, 0x0);
1385
1386 adapter->hw.mem_rang = (u32)mmio_len;
1387 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1388 if (!adapter->hw.hw_addr) {
1389 err = -EIO;
1390 goto err_ioremap;
1391 }
1392
1393 atl2_setup_pcicmd(pdev);
1394
1395 netdev->netdev_ops = &atl2_netdev_ops;
1396 netdev->ethtool_ops = &atl2_ethtool_ops;
1397 netdev->watchdog_timeo = 5 * HZ;
1398 netdev->min_mtu = 40;
1399 netdev->max_mtu = ETH_DATA_LEN + VLAN_HLEN;
1400 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1401
1402 netdev->mem_start = mmio_start;
1403 netdev->mem_end = mmio_start + mmio_len;
1404 adapter->bd_number = cards_found;
1405 adapter->pci_using_64 = false;
1406
1407 /* setup the private structure */
1408 err = atl2_sw_init(adapter);
1409 if (err)
1410 goto err_sw_init;
1411
1412 netdev->hw_features = NETIF_F_HW_VLAN_CTAG_RX;
1413 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1414
1415 /* Init PHY as early as possible due to power saving issue */
1416 atl2_phy_init(&adapter->hw);
1417
1418 /* reset the controller to
1419 * put the device in a known good starting state */
1420
1421 if (atl2_reset_hw(&adapter->hw)) {
1422 err = -EIO;
1423 goto err_reset;
1424 }
1425
1426 /* copy the MAC address out of the EEPROM */
1427 atl2_read_mac_addr(&adapter->hw);
1428 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1429 if (!is_valid_ether_addr(netdev->dev_addr)) {
1430 err = -EIO;
1431 goto err_eeprom;
1432 }
1433
1434 atl2_check_options(adapter);
1435
1436 timer_setup(&adapter->watchdog_timer, atl2_watchdog, 0);
1437
1438 timer_setup(&adapter->phy_config_timer, atl2_phy_config, 0);
1439
1440 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1441 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1442
1443 strcpy(netdev->name, "eth%d"); /* ?? */
1444 err = register_netdev(netdev);
1445 if (err)
1446 goto err_register;
1447
1448 /* assume we have no link for now */
1449 netif_carrier_off(netdev);
1450 netif_stop_queue(netdev);
1451
1452 cards_found++;
1453
1454 return 0;
1455
1456 err_reset:
1457 err_register:
1458 err_sw_init:
1459 err_eeprom:
1460 iounmap(adapter->hw.hw_addr);
1461 err_ioremap:
1462 free_netdev(netdev);
1463 err_alloc_etherdev:
1464 pci_release_regions(pdev);
1465 err_pci_reg:
1466 err_dma:
1467 pci_disable_device(pdev);
1468 return err;
1469 }
1470
1471 /**
1472 * atl2_remove - Device Removal Routine
1473 * @pdev: PCI device information struct
1474 *
1475 * atl2_remove is called by the PCI subsystem to alert the driver
1476 * that it should release a PCI device. The could be caused by a
1477 * Hot-Plug event, or because the driver is going to be removed from
1478 * memory.
1479 */
1480 /* FIXME: write the original MAC address back in case it was changed from a
1481 * BIOS-set value, as in atl1 -- CHS */
1482 static void atl2_remove(struct pci_dev *pdev)
1483 {
1484 struct net_device *netdev = pci_get_drvdata(pdev);
1485 struct atl2_adapter *adapter = netdev_priv(netdev);
1486
1487 /* flush_scheduled work may reschedule our watchdog task, so
1488 * explicitly disable watchdog tasks from being rescheduled */
1489 set_bit(__ATL2_DOWN, &adapter->flags);
1490
1491 del_timer_sync(&adapter->watchdog_timer);
1492 del_timer_sync(&adapter->phy_config_timer);
1493 cancel_work_sync(&adapter->reset_task);
1494 cancel_work_sync(&adapter->link_chg_task);
1495
1496 unregister_netdev(netdev);
1497
1498 atl2_force_ps(&adapter->hw);
1499
1500 iounmap(adapter->hw.hw_addr);
1501 pci_release_regions(pdev);
1502
1503 free_netdev(netdev);
1504
1505 pci_disable_device(pdev);
1506 }
1507
1508 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1509 {
1510 struct net_device *netdev = pci_get_drvdata(pdev);
1511 struct atl2_adapter *adapter = netdev_priv(netdev);
1512 struct atl2_hw *hw = &adapter->hw;
1513 u16 speed, duplex;
1514 u32 ctrl = 0;
1515 u32 wufc = adapter->wol;
1516
1517 #ifdef CONFIG_PM
1518 int retval = 0;
1519 #endif
1520
1521 netif_device_detach(netdev);
1522
1523 if (netif_running(netdev)) {
1524 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1525 atl2_down(adapter);
1526 }
1527
1528 #ifdef CONFIG_PM
1529 retval = pci_save_state(pdev);
1530 if (retval)
1531 return retval;
1532 #endif
1533
1534 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1535 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1536 if (ctrl & BMSR_LSTATUS)
1537 wufc &= ~ATLX_WUFC_LNKC;
1538
1539 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1540 u32 ret_val;
1541 /* get current link speed & duplex */
1542 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1543 if (ret_val) {
1544 printk(KERN_DEBUG
1545 "%s: get speed&duplex error while suspend\n",
1546 atl2_driver_name);
1547 goto wol_dis;
1548 }
1549
1550 ctrl = 0;
1551
1552 /* turn on magic packet wol */
1553 if (wufc & ATLX_WUFC_MAG)
1554 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1555
1556 /* ignore Link Chg event when Link is up */
1557 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1558
1559 /* Config MAC CTRL Register */
1560 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1561 if (FULL_DUPLEX == adapter->link_duplex)
1562 ctrl |= MAC_CTRL_DUPLX;
1563 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1564 ctrl |= (((u32)adapter->hw.preamble_len &
1565 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1566 ctrl |= (((u32)(adapter->hw.retry_buf &
1567 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1568 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1569 if (wufc & ATLX_WUFC_MAG) {
1570 /* magic packet maybe Broadcast&multicast&Unicast */
1571 ctrl |= MAC_CTRL_BC_EN;
1572 }
1573
1574 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1575
1576 /* pcie patch */
1577 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1578 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1579 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1580 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1581 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1582 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1583
1584 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1585 goto suspend_exit;
1586 }
1587
1588 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1589 /* link is down, so only LINK CHG WOL event enable */
1590 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1591 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1592 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1593
1594 /* pcie patch */
1595 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1596 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1597 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1598 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1599 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1600 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1601
1602 hw->phy_configured = false; /* re-init PHY when resume */
1603
1604 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1605
1606 goto suspend_exit;
1607 }
1608
1609 wol_dis:
1610 /* WOL disabled */
1611 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1612
1613 /* pcie patch */
1614 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1615 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1616 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1617 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1618 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1619 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1620
1621 atl2_force_ps(hw);
1622 hw->phy_configured = false; /* re-init PHY when resume */
1623
1624 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1625
1626 suspend_exit:
1627 if (netif_running(netdev))
1628 atl2_free_irq(adapter);
1629
1630 pci_disable_device(pdev);
1631
1632 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1633
1634 return 0;
1635 }
1636
1637 #ifdef CONFIG_PM
1638 static int atl2_resume(struct pci_dev *pdev)
1639 {
1640 struct net_device *netdev = pci_get_drvdata(pdev);
1641 struct atl2_adapter *adapter = netdev_priv(netdev);
1642 u32 err;
1643
1644 pci_set_power_state(pdev, PCI_D0);
1645 pci_restore_state(pdev);
1646
1647 err = pci_enable_device(pdev);
1648 if (err) {
1649 printk(KERN_ERR
1650 "atl2: Cannot enable PCI device from suspend\n");
1651 return err;
1652 }
1653
1654 pci_set_master(pdev);
1655
1656 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1657
1658 pci_enable_wake(pdev, PCI_D3hot, 0);
1659 pci_enable_wake(pdev, PCI_D3cold, 0);
1660
1661 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1662
1663 if (netif_running(netdev)) {
1664 err = atl2_request_irq(adapter);
1665 if (err)
1666 return err;
1667 }
1668
1669 atl2_reset_hw(&adapter->hw);
1670
1671 if (netif_running(netdev))
1672 atl2_up(adapter);
1673
1674 netif_device_attach(netdev);
1675
1676 return 0;
1677 }
1678 #endif
1679
1680 static void atl2_shutdown(struct pci_dev *pdev)
1681 {
1682 atl2_suspend(pdev, PMSG_SUSPEND);
1683 }
1684
1685 static struct pci_driver atl2_driver = {
1686 .name = atl2_driver_name,
1687 .id_table = atl2_pci_tbl,
1688 .probe = atl2_probe,
1689 .remove = atl2_remove,
1690 /* Power Management Hooks */
1691 .suspend = atl2_suspend,
1692 #ifdef CONFIG_PM
1693 .resume = atl2_resume,
1694 #endif
1695 .shutdown = atl2_shutdown,
1696 };
1697
1698 /**
1699 * atl2_init_module - Driver Registration Routine
1700 *
1701 * atl2_init_module is the first routine called when the driver is
1702 * loaded. All it does is register with the PCI subsystem.
1703 */
1704 static int __init atl2_init_module(void)
1705 {
1706 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1707 atl2_driver_version);
1708 printk(KERN_INFO "%s\n", atl2_copyright);
1709 return pci_register_driver(&atl2_driver);
1710 }
1711 module_init(atl2_init_module);
1712
1713 /**
1714 * atl2_exit_module - Driver Exit Cleanup Routine
1715 *
1716 * atl2_exit_module is called just before the driver is removed
1717 * from memory.
1718 */
1719 static void __exit atl2_exit_module(void)
1720 {
1721 pci_unregister_driver(&atl2_driver);
1722 }
1723 module_exit(atl2_exit_module);
1724
1725 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1726 {
1727 struct atl2_adapter *adapter = hw->back;
1728 pci_read_config_word(adapter->pdev, reg, value);
1729 }
1730
1731 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1732 {
1733 struct atl2_adapter *adapter = hw->back;
1734 pci_write_config_word(adapter->pdev, reg, *value);
1735 }
1736
1737 static int atl2_get_link_ksettings(struct net_device *netdev,
1738 struct ethtool_link_ksettings *cmd)
1739 {
1740 struct atl2_adapter *adapter = netdev_priv(netdev);
1741 struct atl2_hw *hw = &adapter->hw;
1742 u32 supported, advertising;
1743
1744 supported = (SUPPORTED_10baseT_Half |
1745 SUPPORTED_10baseT_Full |
1746 SUPPORTED_100baseT_Half |
1747 SUPPORTED_100baseT_Full |
1748 SUPPORTED_Autoneg |
1749 SUPPORTED_TP);
1750 advertising = ADVERTISED_TP;
1751
1752 advertising |= ADVERTISED_Autoneg;
1753 advertising |= hw->autoneg_advertised;
1754
1755 cmd->base.port = PORT_TP;
1756 cmd->base.phy_address = 0;
1757
1758 if (adapter->link_speed != SPEED_0) {
1759 cmd->base.speed = adapter->link_speed;
1760 if (adapter->link_duplex == FULL_DUPLEX)
1761 cmd->base.duplex = DUPLEX_FULL;
1762 else
1763 cmd->base.duplex = DUPLEX_HALF;
1764 } else {
1765 cmd->base.speed = SPEED_UNKNOWN;
1766 cmd->base.duplex = DUPLEX_UNKNOWN;
1767 }
1768
1769 cmd->base.autoneg = AUTONEG_ENABLE;
1770
1771 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1772 supported);
1773 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1774 advertising);
1775
1776 return 0;
1777 }
1778
1779 static int atl2_set_link_ksettings(struct net_device *netdev,
1780 const struct ethtool_link_ksettings *cmd)
1781 {
1782 struct atl2_adapter *adapter = netdev_priv(netdev);
1783 struct atl2_hw *hw = &adapter->hw;
1784 u32 advertising;
1785
1786 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1787 cmd->link_modes.advertising);
1788
1789 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1790 msleep(1);
1791
1792 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1793 #define MY_ADV_MASK (ADVERTISE_10_HALF | \
1794 ADVERTISE_10_FULL | \
1795 ADVERTISE_100_HALF| \
1796 ADVERTISE_100_FULL)
1797
1798 if ((advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1799 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1800 hw->autoneg_advertised = MY_ADV_MASK;
1801 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_FULL) {
1802 hw->MediaType = MEDIA_TYPE_100M_FULL;
1803 hw->autoneg_advertised = ADVERTISE_100_FULL;
1804 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_HALF) {
1805 hw->MediaType = MEDIA_TYPE_100M_HALF;
1806 hw->autoneg_advertised = ADVERTISE_100_HALF;
1807 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_FULL) {
1808 hw->MediaType = MEDIA_TYPE_10M_FULL;
1809 hw->autoneg_advertised = ADVERTISE_10_FULL;
1810 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_HALF) {
1811 hw->MediaType = MEDIA_TYPE_10M_HALF;
1812 hw->autoneg_advertised = ADVERTISE_10_HALF;
1813 } else {
1814 clear_bit(__ATL2_RESETTING, &adapter->flags);
1815 return -EINVAL;
1816 }
1817 advertising = hw->autoneg_advertised |
1818 ADVERTISED_TP | ADVERTISED_Autoneg;
1819 } else {
1820 clear_bit(__ATL2_RESETTING, &adapter->flags);
1821 return -EINVAL;
1822 }
1823
1824 /* reset the link */
1825 if (netif_running(adapter->netdev)) {
1826 atl2_down(adapter);
1827 atl2_up(adapter);
1828 } else
1829 atl2_reset_hw(&adapter->hw);
1830
1831 clear_bit(__ATL2_RESETTING, &adapter->flags);
1832 return 0;
1833 }
1834
1835 static u32 atl2_get_msglevel(struct net_device *netdev)
1836 {
1837 return 0;
1838 }
1839
1840 /*
1841 * It's sane for this to be empty, but we might want to take advantage of this.
1842 */
1843 static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1844 {
1845 }
1846
1847 static int atl2_get_regs_len(struct net_device *netdev)
1848 {
1849 #define ATL2_REGS_LEN 42
1850 return sizeof(u32) * ATL2_REGS_LEN;
1851 }
1852
1853 static void atl2_get_regs(struct net_device *netdev,
1854 struct ethtool_regs *regs, void *p)
1855 {
1856 struct atl2_adapter *adapter = netdev_priv(netdev);
1857 struct atl2_hw *hw = &adapter->hw;
1858 u32 *regs_buff = p;
1859 u16 phy_data;
1860
1861 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1862
1863 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1864
1865 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1866 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1867 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1868 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1869 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1870 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1871 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1872 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1873 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1874 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1875 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1876 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1877 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1878 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1879 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1880 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1881 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1882 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1883 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1884 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1885 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1886 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1887 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1888 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1889 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1890 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1891 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1892 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1893 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1894 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1895 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1896 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1897 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1898 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1899 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1900 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1901 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1902 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1903 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1904
1905 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1906 regs_buff[40] = (u32)phy_data;
1907 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1908 regs_buff[41] = (u32)phy_data;
1909 }
1910
1911 static int atl2_get_eeprom_len(struct net_device *netdev)
1912 {
1913 struct atl2_adapter *adapter = netdev_priv(netdev);
1914
1915 if (!atl2_check_eeprom_exist(&adapter->hw))
1916 return 512;
1917 else
1918 return 0;
1919 }
1920
1921 static int atl2_get_eeprom(struct net_device *netdev,
1922 struct ethtool_eeprom *eeprom, u8 *bytes)
1923 {
1924 struct atl2_adapter *adapter = netdev_priv(netdev);
1925 struct atl2_hw *hw = &adapter->hw;
1926 u32 *eeprom_buff;
1927 int first_dword, last_dword;
1928 int ret_val = 0;
1929 int i;
1930
1931 if (eeprom->len == 0)
1932 return -EINVAL;
1933
1934 if (atl2_check_eeprom_exist(hw))
1935 return -EINVAL;
1936
1937 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1938
1939 first_dword = eeprom->offset >> 2;
1940 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1941
1942 eeprom_buff = kmalloc_array(last_dword - first_dword + 1, sizeof(u32),
1943 GFP_KERNEL);
1944 if (!eeprom_buff)
1945 return -ENOMEM;
1946
1947 for (i = first_dword; i < last_dword; i++) {
1948 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) {
1949 ret_val = -EIO;
1950 goto free;
1951 }
1952 }
1953
1954 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1955 eeprom->len);
1956 free:
1957 kfree(eeprom_buff);
1958
1959 return ret_val;
1960 }
1961
1962 static int atl2_set_eeprom(struct net_device *netdev,
1963 struct ethtool_eeprom *eeprom, u8 *bytes)
1964 {
1965 struct atl2_adapter *adapter = netdev_priv(netdev);
1966 struct atl2_hw *hw = &adapter->hw;
1967 u32 *eeprom_buff;
1968 u32 *ptr;
1969 int max_len, first_dword, last_dword, ret_val = 0;
1970 int i;
1971
1972 if (eeprom->len == 0)
1973 return -EOPNOTSUPP;
1974
1975 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1976 return -EFAULT;
1977
1978 max_len = 512;
1979
1980 first_dword = eeprom->offset >> 2;
1981 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1982 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1983 if (!eeprom_buff)
1984 return -ENOMEM;
1985
1986 ptr = eeprom_buff;
1987
1988 if (eeprom->offset & 3) {
1989 /* need read/modify/write of first changed EEPROM word */
1990 /* only the second byte of the word is being modified */
1991 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) {
1992 ret_val = -EIO;
1993 goto out;
1994 }
1995 ptr++;
1996 }
1997 if (((eeprom->offset + eeprom->len) & 3)) {
1998 /*
1999 * need read/modify/write of last changed EEPROM word
2000 * only the first byte of the word is being modified
2001 */
2002 if (!atl2_read_eeprom(hw, last_dword * 4,
2003 &(eeprom_buff[last_dword - first_dword]))) {
2004 ret_val = -EIO;
2005 goto out;
2006 }
2007 }
2008
2009 /* Device's eeprom is always little-endian, word addressable */
2010 memcpy(ptr, bytes, eeprom->len);
2011
2012 for (i = 0; i < last_dword - first_dword + 1; i++) {
2013 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) {
2014 ret_val = -EIO;
2015 goto out;
2016 }
2017 }
2018 out:
2019 kfree(eeprom_buff);
2020 return ret_val;
2021 }
2022
2023 static void atl2_get_drvinfo(struct net_device *netdev,
2024 struct ethtool_drvinfo *drvinfo)
2025 {
2026 struct atl2_adapter *adapter = netdev_priv(netdev);
2027
2028 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver));
2029 strlcpy(drvinfo->version, atl2_driver_version,
2030 sizeof(drvinfo->version));
2031 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version));
2032 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
2033 sizeof(drvinfo->bus_info));
2034 }
2035
2036 static void atl2_get_wol(struct net_device *netdev,
2037 struct ethtool_wolinfo *wol)
2038 {
2039 struct atl2_adapter *adapter = netdev_priv(netdev);
2040
2041 wol->supported = WAKE_MAGIC;
2042 wol->wolopts = 0;
2043
2044 if (adapter->wol & ATLX_WUFC_EX)
2045 wol->wolopts |= WAKE_UCAST;
2046 if (adapter->wol & ATLX_WUFC_MC)
2047 wol->wolopts |= WAKE_MCAST;
2048 if (adapter->wol & ATLX_WUFC_BC)
2049 wol->wolopts |= WAKE_BCAST;
2050 if (adapter->wol & ATLX_WUFC_MAG)
2051 wol->wolopts |= WAKE_MAGIC;
2052 if (adapter->wol & ATLX_WUFC_LNKC)
2053 wol->wolopts |= WAKE_PHY;
2054 }
2055
2056 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2057 {
2058 struct atl2_adapter *adapter = netdev_priv(netdev);
2059
2060 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2061 return -EOPNOTSUPP;
2062
2063 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
2064 return -EOPNOTSUPP;
2065
2066 /* these settings will always override what we currently have */
2067 adapter->wol = 0;
2068
2069 if (wol->wolopts & WAKE_MAGIC)
2070 adapter->wol |= ATLX_WUFC_MAG;
2071 if (wol->wolopts & WAKE_PHY)
2072 adapter->wol |= ATLX_WUFC_LNKC;
2073
2074 return 0;
2075 }
2076
2077 static int atl2_nway_reset(struct net_device *netdev)
2078 {
2079 struct atl2_adapter *adapter = netdev_priv(netdev);
2080 if (netif_running(netdev))
2081 atl2_reinit_locked(adapter);
2082 return 0;
2083 }
2084
2085 static const struct ethtool_ops atl2_ethtool_ops = {
2086 .get_drvinfo = atl2_get_drvinfo,
2087 .get_regs_len = atl2_get_regs_len,
2088 .get_regs = atl2_get_regs,
2089 .get_wol = atl2_get_wol,
2090 .set_wol = atl2_set_wol,
2091 .get_msglevel = atl2_get_msglevel,
2092 .set_msglevel = atl2_set_msglevel,
2093 .nway_reset = atl2_nway_reset,
2094 .get_link = ethtool_op_get_link,
2095 .get_eeprom_len = atl2_get_eeprom_len,
2096 .get_eeprom = atl2_get_eeprom,
2097 .set_eeprom = atl2_set_eeprom,
2098 .get_link_ksettings = atl2_get_link_ksettings,
2099 .set_link_ksettings = atl2_set_link_ksettings,
2100 };
2101
2102 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2103 (((a) & 0xff00ff00) >> 8))
2104 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2105 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2106
2107 /*
2108 * Reset the transmit and receive units; mask and clear all interrupts.
2109 *
2110 * hw - Struct containing variables accessed by shared code
2111 * return : 0 or idle status (if error)
2112 */
2113 static s32 atl2_reset_hw(struct atl2_hw *hw)
2114 {
2115 u32 icr;
2116 u16 pci_cfg_cmd_word;
2117 int i;
2118
2119 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2120 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2121 if ((pci_cfg_cmd_word &
2122 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2123 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2124 pci_cfg_cmd_word |=
2125 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2126 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2127 }
2128
2129 /* Clear Interrupt mask to stop board from generating
2130 * interrupts & Clear any pending interrupt events
2131 */
2132 /* FIXME */
2133 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2134 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2135
2136 /* Issue Soft Reset to the MAC. This will reset the chip's
2137 * transmit, receive, DMA. It will not effect
2138 * the current PCI configuration. The global reset bit is self-
2139 * clearing, and should clear within a microsecond.
2140 */
2141 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2142 wmb();
2143 msleep(1); /* delay about 1ms */
2144
2145 /* Wait at least 10ms for All module to be Idle */
2146 for (i = 0; i < 10; i++) {
2147 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2148 if (!icr)
2149 break;
2150 msleep(1); /* delay 1 ms */
2151 cpu_relax();
2152 }
2153
2154 if (icr)
2155 return icr;
2156
2157 return 0;
2158 }
2159
2160 #define CUSTOM_SPI_CS_SETUP 2
2161 #define CUSTOM_SPI_CLK_HI 2
2162 #define CUSTOM_SPI_CLK_LO 2
2163 #define CUSTOM_SPI_CS_HOLD 2
2164 #define CUSTOM_SPI_CS_HI 3
2165
2166 static struct atl2_spi_flash_dev flash_table[] =
2167 {
2168 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2169 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2170 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2171 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2172 };
2173
2174 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2175 {
2176 int i;
2177 u32 value;
2178
2179 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2180 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2181
2182 value = SPI_FLASH_CTRL_WAIT_READY |
2183 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2184 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2185 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2186 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2187 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2188 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2189 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2190 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2191 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2192 SPI_FLASH_CTRL_CS_HI_SHIFT |
2193 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2194
2195 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2196
2197 value |= SPI_FLASH_CTRL_START;
2198
2199 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2200
2201 for (i = 0; i < 10; i++) {
2202 msleep(1);
2203 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2204 if (!(value & SPI_FLASH_CTRL_START))
2205 break;
2206 }
2207
2208 if (value & SPI_FLASH_CTRL_START)
2209 return false;
2210
2211 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2212
2213 return true;
2214 }
2215
2216 /*
2217 * get_permanent_address
2218 * return 0 if get valid mac address,
2219 */
2220 static int get_permanent_address(struct atl2_hw *hw)
2221 {
2222 u32 Addr[2];
2223 u32 i, Control;
2224 u16 Register;
2225 u8 EthAddr[ETH_ALEN];
2226 bool KeyValid;
2227
2228 if (is_valid_ether_addr(hw->perm_mac_addr))
2229 return 0;
2230
2231 Addr[0] = 0;
2232 Addr[1] = 0;
2233
2234 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2235 Register = 0;
2236 KeyValid = false;
2237
2238 /* Read out all EEPROM content */
2239 i = 0;
2240 while (1) {
2241 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2242 if (KeyValid) {
2243 if (Register == REG_MAC_STA_ADDR)
2244 Addr[0] = Control;
2245 else if (Register ==
2246 (REG_MAC_STA_ADDR + 4))
2247 Addr[1] = Control;
2248 KeyValid = false;
2249 } else if ((Control & 0xff) == 0x5A) {
2250 KeyValid = true;
2251 Register = (u16) (Control >> 16);
2252 } else {
2253 /* assume data end while encount an invalid KEYWORD */
2254 break;
2255 }
2256 } else {
2257 break; /* read error */
2258 }
2259 i += 4;
2260 }
2261
2262 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2263 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2264
2265 if (is_valid_ether_addr(EthAddr)) {
2266 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
2267 return 0;
2268 }
2269 return 1;
2270 }
2271
2272 /* see if SPI flash exists? */
2273 Addr[0] = 0;
2274 Addr[1] = 0;
2275 Register = 0;
2276 KeyValid = false;
2277 i = 0;
2278 while (1) {
2279 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2280 if (KeyValid) {
2281 if (Register == REG_MAC_STA_ADDR)
2282 Addr[0] = Control;
2283 else if (Register == (REG_MAC_STA_ADDR + 4))
2284 Addr[1] = Control;
2285 KeyValid = false;
2286 } else if ((Control & 0xff) == 0x5A) {
2287 KeyValid = true;
2288 Register = (u16) (Control >> 16);
2289 } else {
2290 break; /* data end */
2291 }
2292 } else {
2293 break; /* read error */
2294 }
2295 i += 4;
2296 }
2297
2298 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2299 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2300 if (is_valid_ether_addr(EthAddr)) {
2301 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
2302 return 0;
2303 }
2304 /* maybe MAC-address is from BIOS */
2305 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2306 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2307 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2308 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2309
2310 if (is_valid_ether_addr(EthAddr)) {
2311 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
2312 return 0;
2313 }
2314
2315 return 1;
2316 }
2317
2318 /*
2319 * Reads the adapter's MAC address from the EEPROM
2320 *
2321 * hw - Struct containing variables accessed by shared code
2322 */
2323 static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2324 {
2325 if (get_permanent_address(hw)) {
2326 /* for test */
2327 /* FIXME: shouldn't we use eth_random_addr() here? */
2328 hw->perm_mac_addr[0] = 0x00;
2329 hw->perm_mac_addr[1] = 0x13;
2330 hw->perm_mac_addr[2] = 0x74;
2331 hw->perm_mac_addr[3] = 0x00;
2332 hw->perm_mac_addr[4] = 0x5c;
2333 hw->perm_mac_addr[5] = 0x38;
2334 }
2335
2336 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN);
2337
2338 return 0;
2339 }
2340
2341 /*
2342 * Hashes an address to determine its location in the multicast table
2343 *
2344 * hw - Struct containing variables accessed by shared code
2345 * mc_addr - the multicast address to hash
2346 *
2347 * atl2_hash_mc_addr
2348 * purpose
2349 * set hash value for a multicast address
2350 * hash calcu processing :
2351 * 1. calcu 32bit CRC for multicast address
2352 * 2. reverse crc with MSB to LSB
2353 */
2354 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2355 {
2356 u32 crc32, value;
2357 int i;
2358
2359 value = 0;
2360 crc32 = ether_crc_le(6, mc_addr);
2361
2362 for (i = 0; i < 32; i++)
2363 value |= (((crc32 >> i) & 1) << (31 - i));
2364
2365 return value;
2366 }
2367
2368 /*
2369 * Sets the bit in the multicast table corresponding to the hash value.
2370 *
2371 * hw - Struct containing variables accessed by shared code
2372 * hash_value - Multicast address hash value
2373 */
2374 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2375 {
2376 u32 hash_bit, hash_reg;
2377 u32 mta;
2378
2379 /* The HASH Table is a register array of 2 32-bit registers.
2380 * It is treated like an array of 64 bits. We want to set
2381 * bit BitArray[hash_value]. So we figure out what register
2382 * the bit is in, read it, OR in the new bit, then write
2383 * back the new value. The register is determined by the
2384 * upper 7 bits of the hash value and the bit within that
2385 * register are determined by the lower 5 bits of the value.
2386 */
2387 hash_reg = (hash_value >> 31) & 0x1;
2388 hash_bit = (hash_value >> 26) & 0x1F;
2389
2390 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2391
2392 mta |= (1 << hash_bit);
2393
2394 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2395 }
2396
2397 /*
2398 * atl2_init_pcie - init PCIE module
2399 */
2400 static void atl2_init_pcie(struct atl2_hw *hw)
2401 {
2402 u32 value;
2403 value = LTSSM_TEST_MODE_DEF;
2404 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2405
2406 value = PCIE_DLL_TX_CTRL1_DEF;
2407 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2408 }
2409
2410 static void atl2_init_flash_opcode(struct atl2_hw *hw)
2411 {
2412 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2413 hw->flash_vendor = 0; /* ATMEL */
2414
2415 /* Init OP table */
2416 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2417 flash_table[hw->flash_vendor].cmdPROGRAM);
2418 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2419 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2420 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2421 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2422 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2423 flash_table[hw->flash_vendor].cmdRDID);
2424 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2425 flash_table[hw->flash_vendor].cmdWREN);
2426 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2427 flash_table[hw->flash_vendor].cmdRDSR);
2428 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2429 flash_table[hw->flash_vendor].cmdWRSR);
2430 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2431 flash_table[hw->flash_vendor].cmdREAD);
2432 }
2433
2434 /********************************************************************
2435 * Performs basic configuration of the adapter.
2436 *
2437 * hw - Struct containing variables accessed by shared code
2438 * Assumes that the controller has previously been reset and is in a
2439 * post-reset uninitialized state. Initializes multicast table,
2440 * and Calls routines to setup link
2441 * Leaves the transmit and receive units disabled and uninitialized.
2442 ********************************************************************/
2443 static s32 atl2_init_hw(struct atl2_hw *hw)
2444 {
2445 u32 ret_val = 0;
2446
2447 atl2_init_pcie(hw);
2448
2449 /* Zero out the Multicast HASH table */
2450 /* clear the old settings from the multicast hash table */
2451 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2452 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2453
2454 atl2_init_flash_opcode(hw);
2455
2456 ret_val = atl2_phy_init(hw);
2457
2458 return ret_val;
2459 }
2460
2461 /*
2462 * Detects the current speed and duplex settings of the hardware.
2463 *
2464 * hw - Struct containing variables accessed by shared code
2465 * speed - Speed of the connection
2466 * duplex - Duplex setting of the connection
2467 */
2468 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2469 u16 *duplex)
2470 {
2471 s32 ret_val;
2472 u16 phy_data;
2473
2474 /* Read PHY Specific Status Register (17) */
2475 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2476 if (ret_val)
2477 return ret_val;
2478
2479 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2480 return ATLX_ERR_PHY_RES;
2481
2482 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2483 case MII_ATLX_PSSR_100MBS:
2484 *speed = SPEED_100;
2485 break;
2486 case MII_ATLX_PSSR_10MBS:
2487 *speed = SPEED_10;
2488 break;
2489 default:
2490 return ATLX_ERR_PHY_SPEED;
2491 }
2492
2493 if (phy_data & MII_ATLX_PSSR_DPLX)
2494 *duplex = FULL_DUPLEX;
2495 else
2496 *duplex = HALF_DUPLEX;
2497
2498 return 0;
2499 }
2500
2501 /*
2502 * Reads the value from a PHY register
2503 * hw - Struct containing variables accessed by shared code
2504 * reg_addr - address of the PHY register to read
2505 */
2506 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2507 {
2508 u32 val;
2509 int i;
2510
2511 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2512 MDIO_START |
2513 MDIO_SUP_PREAMBLE |
2514 MDIO_RW |
2515 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2516 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2517
2518 wmb();
2519
2520 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2521 udelay(2);
2522 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2523 if (!(val & (MDIO_START | MDIO_BUSY)))
2524 break;
2525 wmb();
2526 }
2527 if (!(val & (MDIO_START | MDIO_BUSY))) {
2528 *phy_data = (u16)val;
2529 return 0;
2530 }
2531
2532 return ATLX_ERR_PHY;
2533 }
2534
2535 /*
2536 * Writes a value to a PHY register
2537 * hw - Struct containing variables accessed by shared code
2538 * reg_addr - address of the PHY register to write
2539 * data - data to write to the PHY
2540 */
2541 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2542 {
2543 int i;
2544 u32 val;
2545
2546 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2547 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2548 MDIO_SUP_PREAMBLE |
2549 MDIO_START |
2550 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2551 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2552
2553 wmb();
2554
2555 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2556 udelay(2);
2557 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2558 if (!(val & (MDIO_START | MDIO_BUSY)))
2559 break;
2560
2561 wmb();
2562 }
2563
2564 if (!(val & (MDIO_START | MDIO_BUSY)))
2565 return 0;
2566
2567 return ATLX_ERR_PHY;
2568 }
2569
2570 /*
2571 * Configures PHY autoneg and flow control advertisement settings
2572 *
2573 * hw - Struct containing variables accessed by shared code
2574 */
2575 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2576 {
2577 s32 ret_val;
2578 s16 mii_autoneg_adv_reg;
2579
2580 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2581 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2582
2583 /* Need to parse autoneg_advertised and set up
2584 * the appropriate PHY registers. First we will parse for
2585 * autoneg_advertised software override. Since we can advertise
2586 * a plethora of combinations, we need to check each bit
2587 * individually.
2588 */
2589
2590 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2591 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2592 * the 1000Base-T Control Register (Address 9). */
2593 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2594
2595 /* Need to parse MediaType and setup the
2596 * appropriate PHY registers. */
2597 switch (hw->MediaType) {
2598 case MEDIA_TYPE_AUTO_SENSOR:
2599 mii_autoneg_adv_reg |=
2600 (MII_AR_10T_HD_CAPS |
2601 MII_AR_10T_FD_CAPS |
2602 MII_AR_100TX_HD_CAPS|
2603 MII_AR_100TX_FD_CAPS);
2604 hw->autoneg_advertised =
2605 ADVERTISE_10_HALF |
2606 ADVERTISE_10_FULL |
2607 ADVERTISE_100_HALF|
2608 ADVERTISE_100_FULL;
2609 break;
2610 case MEDIA_TYPE_100M_FULL:
2611 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2612 hw->autoneg_advertised = ADVERTISE_100_FULL;
2613 break;
2614 case MEDIA_TYPE_100M_HALF:
2615 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2616 hw->autoneg_advertised = ADVERTISE_100_HALF;
2617 break;
2618 case MEDIA_TYPE_10M_FULL:
2619 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2620 hw->autoneg_advertised = ADVERTISE_10_FULL;
2621 break;
2622 default:
2623 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2624 hw->autoneg_advertised = ADVERTISE_10_HALF;
2625 break;
2626 }
2627
2628 /* flow control fixed to enable all */
2629 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2630
2631 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2632
2633 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2634
2635 if (ret_val)
2636 return ret_val;
2637
2638 return 0;
2639 }
2640
2641 /*
2642 * Resets the PHY and make all config validate
2643 *
2644 * hw - Struct containing variables accessed by shared code
2645 *
2646 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2647 */
2648 static s32 atl2_phy_commit(struct atl2_hw *hw)
2649 {
2650 s32 ret_val;
2651 u16 phy_data;
2652
2653 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2654 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2655 if (ret_val) {
2656 u32 val;
2657 int i;
2658 /* pcie serdes link may be down ! */
2659 for (i = 0; i < 25; i++) {
2660 msleep(1);
2661 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2662 if (!(val & (MDIO_START | MDIO_BUSY)))
2663 break;
2664 }
2665
2666 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2667 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2668 return ret_val;
2669 }
2670 }
2671 return 0;
2672 }
2673
2674 static s32 atl2_phy_init(struct atl2_hw *hw)
2675 {
2676 s32 ret_val;
2677 u16 phy_val;
2678
2679 if (hw->phy_configured)
2680 return 0;
2681
2682 /* Enable PHY */
2683 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2684 ATL2_WRITE_FLUSH(hw);
2685 msleep(1);
2686
2687 /* check if the PHY is in powersaving mode */
2688 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2689 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2690
2691 /* 024E / 124E 0r 0274 / 1274 ? */
2692 if (phy_val & 0x1000) {
2693 phy_val &= ~0x1000;
2694 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2695 }
2696
2697 msleep(1);
2698
2699 /*Enable PHY LinkChange Interrupt */
2700 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2701 if (ret_val)
2702 return ret_val;
2703
2704 /* setup AutoNeg parameters */
2705 ret_val = atl2_phy_setup_autoneg_adv(hw);
2706 if (ret_val)
2707 return ret_val;
2708
2709 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2710 ret_val = atl2_phy_commit(hw);
2711 if (ret_val)
2712 return ret_val;
2713
2714 hw->phy_configured = true;
2715
2716 return ret_val;
2717 }
2718
2719 static void atl2_set_mac_addr(struct atl2_hw *hw)
2720 {
2721 u32 value;
2722 /* 00-0B-6A-F6-00-DC
2723 * 0: 6AF600DC 1: 000B
2724 * low dword */
2725 value = (((u32)hw->mac_addr[2]) << 24) |
2726 (((u32)hw->mac_addr[3]) << 16) |
2727 (((u32)hw->mac_addr[4]) << 8) |
2728 (((u32)hw->mac_addr[5]));
2729 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2730 /* hight dword */
2731 value = (((u32)hw->mac_addr[0]) << 8) |
2732 (((u32)hw->mac_addr[1]));
2733 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2734 }
2735
2736 /*
2737 * check_eeprom_exist
2738 * return 0 if eeprom exist
2739 */
2740 static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2741 {
2742 u32 value;
2743
2744 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2745 if (value & SPI_FLASH_CTRL_EN_VPD) {
2746 value &= ~SPI_FLASH_CTRL_EN_VPD;
2747 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2748 }
2749 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2750 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2751 }
2752
2753 /* FIXME: This doesn't look right. -- CHS */
2754 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2755 {
2756 return true;
2757 }
2758
2759 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2760 {
2761 int i;
2762 u32 Control;
2763
2764 if (Offset & 0x3)
2765 return false; /* address do not align */
2766
2767 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2768 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2769 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2770
2771 for (i = 0; i < 10; i++) {
2772 msleep(2);
2773 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2774 if (Control & VPD_CAP_VPD_FLAG)
2775 break;
2776 }
2777
2778 if (Control & VPD_CAP_VPD_FLAG) {
2779 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2780 return true;
2781 }
2782 return false; /* timeout */
2783 }
2784
2785 static void atl2_force_ps(struct atl2_hw *hw)
2786 {
2787 u16 phy_val;
2788
2789 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2790 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2791 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2792
2793 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2794 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2795 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2796 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2797 }
2798
2799 /* This is the only thing that needs to be changed to adjust the
2800 * maximum number of ports that the driver can manage.
2801 */
2802 #define ATL2_MAX_NIC 4
2803
2804 #define OPTION_UNSET -1
2805 #define OPTION_DISABLED 0
2806 #define OPTION_ENABLED 1
2807
2808 /* All parameters are treated the same, as an integer array of values.
2809 * This macro just reduces the need to repeat the same declaration code
2810 * over and over (plus this helps to avoid typo bugs).
2811 */
2812 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2813 #ifndef module_param_array
2814 /* Module Parameters are always initialized to -1, so that the driver
2815 * can tell the difference between no user specified value or the
2816 * user asking for the default value.
2817 * The true default values are loaded in when atl2_check_options is called.
2818 *
2819 * This is a GCC extension to ANSI C.
2820 * See the item "Labeled Elements in Initializers" in the section
2821 * "Extensions to the C Language Family" of the GCC documentation.
2822 */
2823
2824 #define ATL2_PARAM(X, desc) \
2825 static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2826 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2827 MODULE_PARM_DESC(X, desc);
2828 #else
2829 #define ATL2_PARAM(X, desc) \
2830 static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2831 static unsigned int num_##X; \
2832 module_param_array_named(X, X, int, &num_##X, 0); \
2833 MODULE_PARM_DESC(X, desc);
2834 #endif
2835
2836 /*
2837 * Transmit Memory Size
2838 * Valid Range: 64-2048
2839 * Default Value: 128
2840 */
2841 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2842 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2843 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2844 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2845
2846 /*
2847 * Receive Memory Block Count
2848 * Valid Range: 16-512
2849 * Default Value: 128
2850 */
2851 #define ATL2_MIN_RXD_COUNT 16
2852 #define ATL2_MAX_RXD_COUNT 512
2853 #define ATL2_DEFAULT_RXD_COUNT 64
2854 ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2855
2856 /*
2857 * User Specified MediaType Override
2858 *
2859 * Valid Range: 0-5
2860 * - 0 - auto-negotiate at all supported speeds
2861 * - 1 - only link at 1000Mbps Full Duplex
2862 * - 2 - only link at 100Mbps Full Duplex
2863 * - 3 - only link at 100Mbps Half Duplex
2864 * - 4 - only link at 10Mbps Full Duplex
2865 * - 5 - only link at 10Mbps Half Duplex
2866 * Default Value: 0
2867 */
2868 ATL2_PARAM(MediaType, "MediaType Select");
2869
2870 /*
2871 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2872 * Valid Range: 10-65535
2873 * Default Value: 45000(90ms)
2874 */
2875 #define INT_MOD_DEFAULT_CNT 100 /* 200us */
2876 #define INT_MOD_MAX_CNT 65000
2877 #define INT_MOD_MIN_CNT 50
2878 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2879
2880 /*
2881 * FlashVendor
2882 * Valid Range: 0-2
2883 * 0 - Atmel
2884 * 1 - SST
2885 * 2 - ST
2886 */
2887 ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2888
2889 #define AUTONEG_ADV_DEFAULT 0x2F
2890 #define AUTONEG_ADV_MASK 0x2F
2891 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2892
2893 #define FLASH_VENDOR_DEFAULT 0
2894 #define FLASH_VENDOR_MIN 0
2895 #define FLASH_VENDOR_MAX 2
2896
2897 struct atl2_option {
2898 enum { enable_option, range_option, list_option } type;
2899 char *name;
2900 char *err;
2901 int def;
2902 union {
2903 struct { /* range_option info */
2904 int min;
2905 int max;
2906 } r;
2907 struct { /* list_option info */
2908 int nr;
2909 struct atl2_opt_list { int i; char *str; } *p;
2910 } l;
2911 } arg;
2912 };
2913
2914 static int atl2_validate_option(int *value, struct atl2_option *opt)
2915 {
2916 int i;
2917 struct atl2_opt_list *ent;
2918
2919 if (*value == OPTION_UNSET) {
2920 *value = opt->def;
2921 return 0;
2922 }
2923
2924 switch (opt->type) {
2925 case enable_option:
2926 switch (*value) {
2927 case OPTION_ENABLED:
2928 printk(KERN_INFO "%s Enabled\n", opt->name);
2929 return 0;
2930 case OPTION_DISABLED:
2931 printk(KERN_INFO "%s Disabled\n", opt->name);
2932 return 0;
2933 }
2934 break;
2935 case range_option:
2936 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2937 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2938 return 0;
2939 }
2940 break;
2941 case list_option:
2942 for (i = 0; i < opt->arg.l.nr; i++) {
2943 ent = &opt->arg.l.p[i];
2944 if (*value == ent->i) {
2945 if (ent->str[0] != '\0')
2946 printk(KERN_INFO "%s\n", ent->str);
2947 return 0;
2948 }
2949 }
2950 break;
2951 default:
2952 BUG();
2953 }
2954
2955 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2956 opt->name, *value, opt->err);
2957 *value = opt->def;
2958 return -1;
2959 }
2960
2961 /**
2962 * atl2_check_options - Range Checking for Command Line Parameters
2963 * @adapter: board private structure
2964 *
2965 * This routine checks all command line parameters for valid user
2966 * input. If an invalid value is given, or if no user specified
2967 * value exists, a default value is used. The final value is stored
2968 * in a variable in the adapter structure.
2969 */
2970 static void atl2_check_options(struct atl2_adapter *adapter)
2971 {
2972 int val;
2973 struct atl2_option opt;
2974 int bd = adapter->bd_number;
2975 if (bd >= ATL2_MAX_NIC) {
2976 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
2977 bd);
2978 printk(KERN_NOTICE "Using defaults for all values\n");
2979 #ifndef module_param_array
2980 bd = ATL2_MAX_NIC;
2981 #endif
2982 }
2983
2984 /* Bytes of Transmit Memory */
2985 opt.type = range_option;
2986 opt.name = "Bytes of Transmit Memory";
2987 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
2988 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
2989 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
2990 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
2991 #ifdef module_param_array
2992 if (num_TxMemSize > bd) {
2993 #endif
2994 val = TxMemSize[bd];
2995 atl2_validate_option(&val, &opt);
2996 adapter->txd_ring_size = ((u32) val) * 1024;
2997 #ifdef module_param_array
2998 } else
2999 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3000 #endif
3001 /* txs ring size: */
3002 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3003 if (adapter->txs_ring_size > 160)
3004 adapter->txs_ring_size = 160;
3005
3006 /* Receive Memory Block Count */
3007 opt.type = range_option;
3008 opt.name = "Number of receive memory block";
3009 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3010 opt.def = ATL2_DEFAULT_RXD_COUNT;
3011 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3012 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3013 #ifdef module_param_array
3014 if (num_RxMemBlock > bd) {
3015 #endif
3016 val = RxMemBlock[bd];
3017 atl2_validate_option(&val, &opt);
3018 adapter->rxd_ring_size = (u32)val;
3019 /* FIXME */
3020 /* ((u16)val)&~1; */ /* even number */
3021 #ifdef module_param_array
3022 } else
3023 adapter->rxd_ring_size = (u32)opt.def;
3024 #endif
3025 /* init RXD Flow control value */
3026 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3027 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3028 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3029 (adapter->rxd_ring_size / 12);
3030
3031 /* Interrupt Moderate Timer */
3032 opt.type = range_option;
3033 opt.name = "Interrupt Moderate Timer";
3034 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3035 opt.def = INT_MOD_DEFAULT_CNT;
3036 opt.arg.r.min = INT_MOD_MIN_CNT;
3037 opt.arg.r.max = INT_MOD_MAX_CNT;
3038 #ifdef module_param_array
3039 if (num_IntModTimer > bd) {
3040 #endif
3041 val = IntModTimer[bd];
3042 atl2_validate_option(&val, &opt);
3043 adapter->imt = (u16) val;
3044 #ifdef module_param_array
3045 } else
3046 adapter->imt = (u16)(opt.def);
3047 #endif
3048 /* Flash Vendor */
3049 opt.type = range_option;
3050 opt.name = "SPI Flash Vendor";
3051 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3052 opt.def = FLASH_VENDOR_DEFAULT;
3053 opt.arg.r.min = FLASH_VENDOR_MIN;
3054 opt.arg.r.max = FLASH_VENDOR_MAX;
3055 #ifdef module_param_array
3056 if (num_FlashVendor > bd) {
3057 #endif
3058 val = FlashVendor[bd];
3059 atl2_validate_option(&val, &opt);
3060 adapter->hw.flash_vendor = (u8) val;
3061 #ifdef module_param_array
3062 } else
3063 adapter->hw.flash_vendor = (u8)(opt.def);
3064 #endif
3065 /* MediaType */
3066 opt.type = range_option;
3067 opt.name = "Speed/Duplex Selection";
3068 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3069 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3070 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3071 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3072 #ifdef module_param_array
3073 if (num_MediaType > bd) {
3074 #endif
3075 val = MediaType[bd];
3076 atl2_validate_option(&val, &opt);
3077 adapter->hw.MediaType = (u16) val;
3078 #ifdef module_param_array
3079 } else
3080 adapter->hw.MediaType = (u16)(opt.def);
3081 #endif
3082 }
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