queue-4.14/perf-x86-intel-ds-fix-event-vs.-uevent-pebs-constrai.patch

   1 From 1f99c2a9b68edcd5d8ab5548aafae4704022a487 Mon Sep 17 00:00:00 2001
   2 From: Stephane Eranian <eranian@google.com>
   3 Date: Mon, 20 May 2019 17:52:46 -0700
   4 Subject: perf/x86/intel/ds: Fix EVENT vs. UEVENT PEBS constraints
   5
   6 [ Upstream commit 23e3983a466cd540ffdd2bbc6e0c51e31934f941 ]
   7
   8 This patch fixes an bug revealed by the following commit:
   9
  10   6b89d4c1ae85 ("perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking")
  11
  12 That patch modified INTEL_FLAGS_EVENT_CONSTRAINT() to only look at the event code
  13 when matching a constraint. If code+umask were needed, then the
  14 INTEL_FLAGS_UEVENT_CONSTRAINT() macro was needed instead.
  15 This broke with some of the constraints for PEBS events.
  16
  17 Several of them, including the one used for cycles:p, cycles:pp, cycles:ppp
  18 fell in that category and caused the event to be rejected in PEBS mode.
  19 In other words, on some platforms a cmdline such as:
  20
  21   $ perf top -e cycles:pp
  22
  23 would fail with -EINVAL.
  24
  25 This patch fixes this bug by properly using INTEL_FLAGS_UEVENT_CONSTRAINT()
  26 when needed in the PEBS constraint tables.
  27
  28 Reported-by: Ingo Molnar <mingo@kernel.org>
  29 Signed-off-by: Stephane Eranian <eranian@google.com>
  30 Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
  31 Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
  32 Cc: Jiri Olsa <jolsa@redhat.com>
  33 Cc: Linus Torvalds <torvalds@linux-foundation.org>
  34 Cc: Peter Zijlstra <peterz@infradead.org>
  35 Cc: Thomas Gleixner <tglx@linutronix.de>
  36 Cc: Vince Weaver <vincent.weaver@maine.edu>
  37 Cc: kan.liang@intel.com
  38 Link: http://lkml.kernel.org/r/20190521005246.423-1-eranian@google.com
  39 Signed-off-by: Ingo Molnar <mingo@kernel.org>
  40 Signed-off-by: Sasha Levin <sashal@kernel.org>
  41 ---
  42  arch/x86/events/intel/ds.c | 28 ++++++++++++++--------------
  43  1 file changed, 14 insertions(+), 14 deletions(-)
  44
  45 diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
  46 index 25386be0d757..3310f9f6c3e1 100644
  47 --- a/arch/x86/events/intel/ds.c
  48 +++ b/arch/x86/events/intel/ds.c
  49 @@ -681,7 +681,7 @@ struct event_constraint intel_core2_pebs_event_constraints[] = {
  50         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
  51         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
  52         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  53 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
  54 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
  55         EVENT_CONSTRAINT_END
  56  };
  57
  58 @@ -690,7 +690,7 @@ struct event_constraint intel_atom_pebs_event_constraints[] = {
  59         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
  60         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
  61         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  62 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
  63 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
  64         /* Allow all events as PEBS with no flags */
  65         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
  66         EVENT_CONSTRAINT_END
  67 @@ -698,7 +698,7 @@ struct event_constraint intel_atom_pebs_event_constraints[] = {
  68
  69  struct event_constraint intel_slm_pebs_event_constraints[] = {
  70         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  71 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
  72 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
  73         /* Allow all events as PEBS with no flags */
  74         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
  75         EVENT_CONSTRAINT_END
  76 @@ -729,7 +729,7 @@ struct event_constraint intel_nehalem_pebs_event_constraints[] = {
  77         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
  78         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
  79         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  80 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
  81 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
  82         EVENT_CONSTRAINT_END
  83  };
  84
  85 @@ -746,7 +746,7 @@ struct event_constraint intel_westmere_pebs_event_constraints[] = {
  86         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
  87         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
  88         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  89 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
  90 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
  91         EVENT_CONSTRAINT_END
  92  };
  93
  94 @@ -755,7 +755,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
  95         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
  96         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
  97         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
  98 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
  99 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 100          INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 101          INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 102          INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 103 @@ -770,9 +770,9 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
 104          INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 105         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 106         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 107 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 108 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 109         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 110 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
 111 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 112         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 113         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 114         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 115 @@ -786,9 +786,9 @@ struct event_constraint intel_hsw_pebs_event_constraints[] = {
 116         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 117         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 118         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 119 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 120 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 121         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 122 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
 123 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 124         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 125         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 126         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 127 @@ -809,9 +809,9 @@ struct event_constraint intel_bdw_pebs_event_constraints[] = {
 128         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 129         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 130         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 131 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 132 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 133         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 134 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
 135 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 136         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 137         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 138         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 139 @@ -832,9 +832,9 @@ struct event_constraint intel_bdw_pebs_event_constraints[] = {
 140  struct event_constraint intel_skl_pebs_event_constraints[] = {
 141         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),      /* INST_RETIRED.PREC_DIST */
 142         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 143 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
 144 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 145         /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
 146 -       INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
 147 +       INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 148         INTEL_PLD_CONSTRAINT(0x1cd, 0xf),                     /* MEM_TRANS_RETIRED.* */
 149         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
 150         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
 151 --
 152 2.20.1
 153