queue-4.19/arm-exynos-fix-undefined-instruction-during-exynos54.patch

   1 From ffde4cfbf3faf1466349ab2423189e25ffc16e4e Mon Sep 17 00:00:00 2001
   2 From: Marek Szyprowski <m.szyprowski@samsung.com>
   3 Date: Mon, 18 Feb 2019 15:34:12 +0100
   4 Subject: ARM: exynos: Fix undefined instruction during Exynos5422 resume
   5
   6 [ Upstream commit 4d8e3e951a856777720272ce27f2c738a3eeef8c ]
   7
   8 During early system resume on Exynos5422 with performance counters enabled
   9 the following kernel oops happens:
  10
  11     Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP ARM
  12     Modules linked in:
  13     CPU: 0 PID: 1433 Comm: bash Tainted: G        W         5.0.0-rc5-next-20190208-00023-gd5fb5a8a13e6-dirty #5480
  14     Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
  15     ...
  16     Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment none
  17     Control: 10c5387d  Table: 4451006a  DAC: 00000051
  18     Process bash (pid: 1433, stack limit = 0xb7e0e22f)
  19     ...
  20     (reset_ctrl_regs) from [<c0112ad0>] (dbg_cpu_pm_notify+0x1c/0x24)
  21     (dbg_cpu_pm_notify) from [<c014c840>] (notifier_call_chain+0x44/0x84)
  22     (notifier_call_chain) from [<c014cbc0>] (__atomic_notifier_call_chain+0x7c/0x128)
  23     (__atomic_notifier_call_chain) from [<c01ffaac>] (cpu_pm_notify+0x30/0x54)
  24     (cpu_pm_notify) from [<c055116c>] (syscore_resume+0x98/0x3f4)
  25     (syscore_resume) from [<c0189350>] (suspend_devices_and_enter+0x97c/0xe74)
  26     (suspend_devices_and_enter) from [<c0189fb8>] (pm_suspend+0x770/0xc04)
  27     (pm_suspend) from [<c0187740>] (state_store+0x6c/0xcc)
  28     (state_store) from [<c09fa698>] (kobj_attr_store+0x14/0x20)
  29     (kobj_attr_store) from [<c030159c>] (sysfs_kf_write+0x4c/0x50)
  30     (sysfs_kf_write) from [<c0300620>] (kernfs_fop_write+0xfc/0x1e0)
  31     (kernfs_fop_write) from [<c0282be8>] (__vfs_write+0x2c/0x160)
  32     (__vfs_write) from [<c0282ea4>] (vfs_write+0xa4/0x16c)
  33     (vfs_write) from [<c0283080>] (ksys_write+0x40/0x8c)
  34     (ksys_write) from [<c0101000>] (ret_fast_syscall+0x0/0x28)
  35
  36 Undefined instruction is triggered during CP14 reset, because bits: #16
  37 (Secure privileged invasive debug disabled) and #17 (Secure privileged
  38 noninvasive debug disable) are set in DSCR. Those bits depend on SPNIDEN
  39 and SPIDEN lines, which are provided by Secure JTAG hardware block. That
  40 block in turn is powered from cluster 0 (big/Eagle), but the Exynos5422
  41 boots on cluster 1 (LITTLE/KFC).
  42
  43 To fix this issue it is enough to turn on the power on the cluster 0 for
  44 a while. This lets the Secure JTAG block to propagate the needed signals
  45 to LITTLE/KFC cores and change their DSCR.
  46
  47 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
  48 Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
  49 Signed-off-by: Sasha Levin <sashal@kernel.org>
  50 ---
  51  arch/arm/mach-exynos/suspend.c | 19 +++++++++++++++++++
  52  1 file changed, 19 insertions(+)
  53
  54 diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
  55 index b1fe53e8b460..088c34e99b02 100644
  56 --- a/arch/arm/mach-exynos/suspend.c
  57 +++ b/arch/arm/mach-exynos/suspend.c
  58 @@ -434,8 +434,27 @@ early_wakeup:
  59
  60  static void exynos5420_prepare_pm_resume(void)
  61  {
  62 +       unsigned int mpidr, cluster;
  63 +
  64 +       mpidr = read_cpuid_mpidr();
  65 +       cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
  66 +
  67         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
  68                 WARN_ON(mcpm_cpu_powered_up());
  69 +
  70 +       if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
  71 +               /*
  72 +                * When system is resumed on the LITTLE/KFC core (cluster 1),
  73 +                * the DSCR is not properly updated until the power is turned
  74 +                * on also for the cluster 0. Enable it for a while to
  75 +                * propagate the SPNIDEN and SPIDEN signals from Secure JTAG
  76 +                * block and avoid undefined instruction issue on CP14 reset.
  77 +                */
  78 +               pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
  79 +                               EXYNOS_COMMON_CONFIGURATION(0));
  80 +               pmu_raw_writel(0,
  81 +                               EXYNOS_COMMON_CONFIGURATION(0));
  82 +       }
  83  }
  84
  85  static void exynos5420_pm_resume(void)
  86 --
  87 2.20.1
  88