queue-4.19/arm64-dts-rockchip-fix-rk3328-sdmmc0-write-errors.patch

   1 From 09f91381fa5de1d44bc323d8bf345f5d57b3d9b5 Mon Sep 17 00:00:00 2001
   2 From: Peter Geis <pgwipeout@gmail.com>
   3 Date: Wed, 13 Mar 2019 19:02:30 +0000
   4 Subject: arm64: dts: rockchip: fix rk3328 sdmmc0 write errors
   5
   6 From: Peter Geis <pgwipeout@gmail.com>
   7
   8 commit 09f91381fa5de1d44bc323d8bf345f5d57b3d9b5 upstream.
   9
  10 Various rk3328 based boards experience occasional sdmmc0 write errors.
  11 This is due to the rk3328.dtsi tx drive levels being set to 4ma, vs
  12 8ma per the rk3328 datasheet default settings.
  13
  14 Fix this by setting the tx signal pins to 8ma.
  15 Inspiration from tonymac32's patch,
  16 https://github.com/ayufan-rock64/linux-kernel/commit/dc1212b347e0da17c5460bcc0a56b07d02bac3f8
  17
  18 Fixes issues on the rk3328-roc-cc and the rk3328-rock64 (as per the
  19 above commit message).
  20
  21 Tested on the rk3328-roc-cc board.
  22
  23 Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs")
  24 Cc: stable@vger.kernel.org
  25 Signed-off-by: Peter Geis <pgwipeout@gmail.com>
  26 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  27 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  28
  29 ---
  30  arch/arm64/boot/dts/rockchip/rk3328.dtsi |   14 +++++++-------
  31  1 file changed, 7 insertions(+), 7 deletions(-)
  32
  33 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
  34 +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
  35 @@ -1356,11 +1356,11 @@
  36
  37                 sdmmc0 {
  38                         sdmmc0_clk: sdmmc0-clk {
  39 -                               rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
  40 +                               rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
  41                         };
  42
  43                         sdmmc0_cmd: sdmmc0-cmd {
  44 -                               rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
  45 +                               rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
  46                         };
  47
  48                         sdmmc0_dectn: sdmmc0-dectn {
  49 @@ -1372,14 +1372,14 @@
  50                         };
  51
  52                         sdmmc0_bus1: sdmmc0-bus1 {
  53 -                               rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
  54 +                               rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
  55                         };
  56
  57                         sdmmc0_bus4: sdmmc0-bus4 {
  58 -                               rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
  59 -                                               <1 RK_PA1 1 &pcfg_pull_up_4ma>,
  60 -                                               <1 RK_PA2 1 &pcfg_pull_up_4ma>,
  61 -                                               <1 RK_PA3 1 &pcfg_pull_up_4ma>;
  62 +                               rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
  63 +                                               <1 RK_PA1 1 &pcfg_pull_up_8ma>,
  64 +                                               <1 RK_PA2 1 &pcfg_pull_up_8ma>,
  65 +                                               <1 RK_PA3 1 &pcfg_pull_up_8ma>;
  66                         };
  67
  68                         sdmmc0_gpio: sdmmc0-gpio {