queue-4.19/clk-rockchip-fix-frac-settings-of-gpll-clock-for-rk3.patch

   1 From 72268a5da9a9953f44719ef307e4576281e935b6 Mon Sep 17 00:00:00 2001
   2 From: Katsuhiro Suzuki <katsuhiro@katsuster.net>
   3 Date: Sun, 23 Dec 2018 01:42:49 +0900
   4 Subject: clk: rockchip: fix frac settings of GPLL clock for rk3328
   5
   6 [ Upstream commit a0e447b0c50240a90ab84b7126b3c06b0bab4adc ]
   7
   8 This patch fixes settings of GPLL frequency in fractional mode for
   9 rk3328. In this mode, FOUTVCO is calcurated by following formula:
  10   FOUTVCO = FREF * FBDIV / REFDIV + ((FREF * FRAC / REFDIV) >> 24)
  11
  12 The problem is in FREF * FRAC >> 24 term. This result always lacks
  13 one from target value is specified by rate member. For example first
  14 itme of rk3328_pll_frac_rate originally has
  15   - rate  : 1016064000
  16   - refdiv: 3
  17   - fbdiv : 127
  18   - frac  : 134217
  19   - FREF * FBDIV / REFDIV        = 1016000000
  20   - (FREF * FRAC / REFDIV) >> 24 = 63999
  21 Thus calculated rate is 1016063999. It seems wrong.
  22
  23 If frac has 134218 (it is increased 1 from original value), second
  24 term is 64000. All other items have same situation. So this patch
  25 adds 1 to frac member in all items of rk3328_pll_frac_rate.
  26
  27 Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
  28 Acked-by: Elaine Zhang <zhangqing@rock-chips.com>
  29 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  30 Signed-off-by: Sasha Levin <sashal@kernel.org>
  31 ---
  32  drivers/clk/rockchip/clk-rk3328.c | 12 ++++++------
  33  1 file changed, 6 insertions(+), 6 deletions(-)
  34
  35 diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
  36 index 2c5426607790..e431661fe874 100644
  37 --- a/drivers/clk/rockchip/clk-rk3328.c
  38 +++ b/drivers/clk/rockchip/clk-rk3328.c
  39 @@ -78,17 +78,17 @@ static struct rockchip_pll_rate_table rk3328_pll_rates[] = {
  40
  41  static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {
  42         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  43 -       RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217),
  44 +       RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218),
  45         /* vco = 1016064000 */
  46 -       RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088),
  47 +       RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089),
  48         /* vco = 983040000 */
  49 -       RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088),
  50 +       RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089),
  51         /* vco = 983040000 */
  52 -       RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088),
  53 +       RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089),
  54         /* vco = 860156000 */
  55 -       RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894),
  56 +       RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895),
  57         /* vco = 903168000 */
  58 -       RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329),
  59 +       RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330),
  60         /* vco = 819200000 */
  61         { /* sentinel */ },
  62  };
  63 --
  64 2.19.1
  65