queue-4.19/drm-i915-gvt-initialize-intel_gvt_gtt_entry-in-stack.patch

   1 From 387a4c2b55291b37e245c840813bd8a8bd06ed49 Mon Sep 17 00:00:00 2001
   2 From: Tina Zhang <tina.zhang@intel.com>
   3 Date: Thu, 23 May 2019 06:18:36 +0800
   4 Subject: drm/i915/gvt: Initialize intel_gvt_gtt_entry in stack
   5
   6 From: Tina Zhang <tina.zhang@intel.com>
   7
   8 commit 387a4c2b55291b37e245c840813bd8a8bd06ed49 upstream.
   9
  10 Stack struct intel_gvt_gtt_entry value needs to be initialized before
  11 being used, as the fields may contain garbage values.
  12
  13 W/o this patch, set_ggtt_entry prints:
  14 -------------------------------------
  15 274.046840: set_ggtt_entry: vgpu1:set ggtt entry 0x9bed8000ffffe900
  16 274.046846: set_ggtt_entry: vgpu1:set ggtt entry 0xe55df001
  17 274.046852: set_ggtt_entry: vgpu1:set ggtt entry 0x9bed8000ffffe900
  18
  19 0x9bed8000 is the stack grabage.
  20
  21 W/ this patch, set_ggtt_entry prints:
  22 ------------------------------------
  23 274.046840: set_ggtt_entry: vgpu1:set ggtt entry 0xffffe900
  24 274.046846: set_ggtt_entry: vgpu1:set ggtt entry 0xe55df001
  25 274.046852: set_ggtt_entry: vgpu1:set ggtt entry 0xffffe900
  26
  27 v2:
  28 - Initialize during declaration. (Zhenyu)
  29
  30 Fixes: 7598e8700e9a ("drm/i915/gvt: Missed to cancel dma map for ggtt entries")
  31 Cc: stable@vger.kernel.org # v4.20+
  32 Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
  33 Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
  34 Signed-off-by: Tina Zhang <tina.zhang@intel.com>
  35 Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
  36 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  37
  38 ---
  39  drivers/gpu/drm/i915/gvt/gtt.c |    6 ++++--
  40  1 file changed, 4 insertions(+), 2 deletions(-)
  41
  42 --- a/drivers/gpu/drm/i915/gvt/gtt.c
  43 +++ b/drivers/gpu/drm/i915/gvt/gtt.c
  44 @@ -2161,7 +2161,8 @@ static int emulate_ggtt_mmio_write(struc
  45         struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
  46         unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
  47         unsigned long gma, gfn;
  48 -       struct intel_gvt_gtt_entry e, m;
  49 +       struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
  50 +       struct intel_gvt_gtt_entry m = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
  51         dma_addr_t dma_addr;
  52         int ret;
  53
  54 @@ -2237,7 +2238,8 @@ static int emulate_ggtt_mmio_write(struc
  55
  56         if (ops->test_present(&e)) {
  57                 gfn = ops->get_pfn(&e);
  58 -               m = e;
  59 +               m.val64 = e.val64;
  60 +               m.type = e.type;
  61
  62                 /* one PTE update may be issued in multiple writes and the
  63                  * first write may not construct a valid gfn