queue-6.6/arm64-dts-imx8-ss-lsio-fix-pwm-lpcg-indices.patch

   1 From 1d86c2b3946e69d6b0b93568d312aae6247847c0 Mon Sep 17 00:00:00 2001
   2 From: Frank Li <Frank.Li@nxp.com>
   3 Date: Mon, 1 Apr 2024 18:25:03 -0400
   4 Subject: arm64: dts: imx8-ss-lsio: fix pwm lpcg indices
   5
   6 From: Frank Li <Frank.Li@nxp.com>
   7
   8 commit 1d86c2b3946e69d6b0b93568d312aae6247847c0 upstream.
   9
  10 lpcg's arg0 should use clock indices instead of index.
  11
  12 pwm0_lpcg: clock-controller@5d400000 {
  13         ...                                                // Col1  Col2
  14         clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,  // 0     0
  15                  <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,  // 1     1
  16                  <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,  // 2     4
  17                  <&lsio_bus_clk>,                          // 3     5
  18                  <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;  // 4     6
  19         clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
  20                         <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
  21                         <IMX_LPCG_CLK_6>;
  22 };
  23
  24 Col1: index, which existing dts try to get.
  25 Col2: actual index in lpcg driver.
  26
  27 pwm1 {
  28         ....
  29         clocks = <&pwm1_lpcg 4>, <&pwm1_lpcg 1>;
  30                              ^^              ^^
  31 should be:
  32
  33         clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>, <&pwm1_lpcg IMX_LPCG_CLK_1>;
  34 };
  35
  36 Arg0 is divided by 4 in lpcg driver, so index 0 and 1 will be get by pwm
  37 driver, which are same as IMX_LPCG_CLK_6 and IMX_LPCG_CLK_1. Even it can
  38 work, but code logic is wrong. Fixed it by use correct indices.
  39
  40 Cc: stable@vger.kernel.org
  41 Fixes: 23fa99b205ea ("arm64: dts: freescale: imx8-ss-lsio: add support for lsio_pwm0-3")
  42 Signed-off-by: Frank Li <Frank.Li@nxp.com>
  43 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  44 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  45 ---
  46  arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi |   16 ++++++++--------
  47  1 file changed, 8 insertions(+), 8 deletions(-)
  48
  49 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
  50 +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
  51 @@ -32,8 +32,8 @@ lsio_subsys: bus@5d000000 {
  52                 compatible = "fsl,imx27-pwm";
  53                 reg = <0x5d000000 0x10000>;
  54                 clock-names = "ipg", "per";
  55 -               clocks = <&pwm0_lpcg 4>,
  56 -                        <&pwm0_lpcg 1>;
  57 +               clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>,
  58 +                        <&pwm0_lpcg IMX_LPCG_CLK_1>;
  59                 assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
  60                 assigned-clock-rates = <24000000>;
  61                 #pwm-cells = <3>;
  62 @@ -45,8 +45,8 @@ lsio_subsys: bus@5d000000 {
  63                 compatible = "fsl,imx27-pwm";
  64                 reg = <0x5d010000 0x10000>;
  65                 clock-names = "ipg", "per";
  66 -               clocks = <&pwm1_lpcg 4>,
  67 -                        <&pwm1_lpcg 1>;
  68 +               clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>,
  69 +                        <&pwm1_lpcg IMX_LPCG_CLK_1>;
  70                 assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
  71                 assigned-clock-rates = <24000000>;
  72                 #pwm-cells = <3>;
  73 @@ -58,8 +58,8 @@ lsio_subsys: bus@5d000000 {
  74                 compatible = "fsl,imx27-pwm";
  75                 reg = <0x5d020000 0x10000>;
  76                 clock-names = "ipg", "per";
  77 -               clocks = <&pwm2_lpcg 4>,
  78 -                        <&pwm2_lpcg 1>;
  79 +               clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>,
  80 +                        <&pwm2_lpcg IMX_LPCG_CLK_1>;
  81                 assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
  82                 assigned-clock-rates = <24000000>;
  83                 #pwm-cells = <3>;
  84 @@ -71,8 +71,8 @@ lsio_subsys: bus@5d000000 {
  85                 compatible = "fsl,imx27-pwm";
  86                 reg = <0x5d030000 0x10000>;
  87                 clock-names = "ipg", "per";
  88 -               clocks = <&pwm3_lpcg 4>,
  89 -                        <&pwm3_lpcg 1>;
  90 +               clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>,
  91 +                        <&pwm3_lpcg IMX_LPCG_CLK_1>;
  92                 assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
  93                 assigned-clock-rates = <24000000>;
  94                 #pwm-cells = <3>;