releases/4.19.34/arm-8830-1-nommu-toggle-only-bits-in-exc_return-we-a.patch

   1 From e4abe8a88d880d81f78573634b9f2e4ff476006d Mon Sep 17 00:00:00 2001
   2 From: Vladimir Murzin <vladimir.murzin@arm.com>
   3 Date: Fri, 25 Jan 2019 15:18:37 +0100
   4 Subject: ARM: 8830/1: NOMMU: Toggle only bits in EXC_RETURN we are really care
   5  of
   6
   7 [ Upstream commit 72cd4064fccaae15ab84d40d4be23667402df4ed ]
   8
   9 ARMv8M introduces support for Security extension to M class, among
  10 other things it affects exception handling, especially, encoding of
  11 EXC_RETURN.
  12
  13 The new bits have been added:
  14
  15 Bit [6] Secure or Non-secure stack
  16 Bit [5] Default callee register stacking
  17 Bit [0] Exception Secure
  18
  19 which conflicts with hard-coded value of EXC_RETURN:
  20
  21 In fact, we only care of few bits:
  22
  23 Bit [3]  Mode (0 - Handler, 1 - Thread)
  24 Bit [2]  Stack pointer selection (0 - Main, 1 - Process)
  25
  26 We can toggle only those bits and left other bits as they were on
  27 exception entry.
  28
  29 It is basically, what patch does - saves EXC_RETURN when we do
  30 transition form Thread to Handler mode (it is first svc), so later
  31 saved value is used instead of EXC_RET_THREADMODE_PROCESSSTACK.
  32
  33 Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
  34 Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
  35 Signed-off-by: Sasha Levin <sashal@kernel.org>
  36 ---
  37  arch/arm/include/asm/v7m.h     | 2 +-
  38  arch/arm/kernel/entry-header.S | 3 ++-
  39  arch/arm/kernel/entry-v7m.S    | 4 ++++
  40  arch/arm/mm/proc-v7m.S         | 3 +++
  41  4 files changed, 10 insertions(+), 2 deletions(-)
  42
  43 diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
  44 index 187ccf6496ad..2cb00d15831b 100644
  45 --- a/arch/arm/include/asm/v7m.h
  46 +++ b/arch/arm/include/asm/v7m.h
  47 @@ -49,7 +49,7 @@
  48   * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
  49   */
  50  #define EXC_RET_STACK_MASK                     0x00000004
  51 -#define EXC_RET_THREADMODE_PROCESSSTACK                0xfffffffd
  52 +#define EXC_RET_THREADMODE_PROCESSSTACK                (3 << 2)
  53
  54  /* Cache related definitions */
  55
  56 diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
  57 index 773424843d6e..62db1c9746cb 100644
  58 --- a/arch/arm/kernel/entry-header.S
  59 +++ b/arch/arm/kernel/entry-header.S
  60 @@ -127,7 +127,8 @@
  61           */
  62         .macro  v7m_exception_slow_exit ret_r0
  63         cpsid   i
  64 -       ldr     lr, =EXC_RET_THREADMODE_PROCESSSTACK
  65 +       ldr     lr, =exc_ret
  66 +       ldr     lr, [lr]
  67
  68         @ read original r12, sp, lr, pc and xPSR
  69         add     r12, sp, #S_IP
  70 diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
  71 index abcf47848525..19d2dcd6530d 100644
  72 --- a/arch/arm/kernel/entry-v7m.S
  73 +++ b/arch/arm/kernel/entry-v7m.S
  74 @@ -146,3 +146,7 @@ ENTRY(vector_table)
  75         .rept   CONFIG_CPU_V7M_NUM_IRQ
  76         .long   __irq_entry             @ External Interrupts
  77         .endr
  78 +       .align  2
  79 +       .globl  exc_ret
  80 +exc_ret:
  81 +       .space  4
  82 diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
  83 index 47a5acc64433..92e84181933a 100644
  84 --- a/arch/arm/mm/proc-v7m.S
  85 +++ b/arch/arm/mm/proc-v7m.S
  86 @@ -139,6 +139,9 @@ __v7m_setup_cont:
  87         cpsie   i
  88         svc     #0
  89  1:     cpsid   i
  90 +       ldr     r0, =exc_ret
  91 +       orr     lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK
  92 +       str     lr, [r0]
  93         ldmia   sp, {r0-r3, r12}
  94         str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
  95         mov     lr, r6                  @ restore LR
  96 --
  97 2.19.1
  98