releases/4.19.34/hid-intel-ish-ipc-handle-pimr-before-ish_wakeup-also.patch

   1 From 88c886725dabffa44e02088a9c075fc99491e2b8 Mon Sep 17 00:00:00 2001
   2 From: Song Hongyan <hongyan.song@intel.com>
   3 Date: Tue, 22 Jan 2019 09:06:26 +0800
   4 Subject: HID: intel-ish: ipc: handle PIMR before ish_wakeup also clear PISR
   5  busy_clear bit
   6
   7 [ Upstream commit 2edefc056e4f0e6ec9508dd1aca2c18fa320efef ]
   8
   9 Host driver should handle interrupt mask register earlier than wake up ish FW
  10 else there will be conditions when FW interrupt comes, host PIMR register still
  11 not set ready, so move the interrupt mask setting before ish_wakeup.
  12
  13 Clear PISR busy_clear bit in ish_irq_handler. If not clear, there will be
  14 conditions host driver received a busy_clear interrupt (before the busy_clear
  15 mask bit is ready), it will return IRQ_NONE after check_generated_interrupt,
  16 the interrupt will never be cleared, causing the DEVICE not sending following
  17 IRQ.
  18
  19 Since PISR clear should not be called for the CHV device we do this change.
  20 After the change, both ISH2HOST interrupt and busy_clear interrupt will be
  21 considered as interrupt from ISH, busy_clear interrupt will return IRQ_HANDLED
  22 from IPC_IS_BUSY check.
  23
  24 Signed-off-by: Song Hongyan <hongyan.song@intel.com>
  25 Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
  26 Signed-off-by: Jiri Kosina <jkosina@suse.cz>
  27 Signed-off-by: Sasha Levin <sashal@kernel.org>
  28 ---
  29  drivers/hid/intel-ish-hid/ipc/ipc.c | 9 ++++++---
  30  1 file changed, 6 insertions(+), 3 deletions(-)
  31
  32 diff --git a/drivers/hid/intel-ish-hid/ipc/ipc.c b/drivers/hid/intel-ish-hid/ipc/ipc.c
  33 index bfbca7ec54ce..e00b9dbe220f 100644
  34 --- a/drivers/hid/intel-ish-hid/ipc/ipc.c
  35 +++ b/drivers/hid/intel-ish-hid/ipc/ipc.c
  36 @@ -91,7 +91,10 @@ static bool check_generated_interrupt(struct ishtp_device *dev)
  37                         IPC_INT_FROM_ISH_TO_HOST_CHV_AB(pisr_val);
  38         } else {
  39                 pisr_val = ish_reg_read(dev, IPC_REG_PISR_BXT);
  40 -               interrupt_generated = IPC_INT_FROM_ISH_TO_HOST_BXT(pisr_val);
  41 +               interrupt_generated = !!pisr_val;
  42 +               /* only busy-clear bit is RW, others are RO */
  43 +               if (pisr_val)
  44 +                       ish_reg_write(dev, IPC_REG_PISR_BXT, pisr_val);
  45         }
  46
  47         return interrupt_generated;
  48 @@ -843,11 +846,11 @@ int ish_hw_start(struct ishtp_device *dev)
  49  {
  50         ish_set_host_rdy(dev);
  51
  52 +       set_host_ready(dev);
  53 +
  54         /* After that we can enable ISH DMA operation and wakeup ISHFW */
  55         ish_wakeup(dev);
  56
  57 -       set_host_ready(dev);
  58 -
  59         /* wait for FW-initiated reset flow */
  60         if (!dev->recvd_hw_ready)
  61                 wait_event_interruptible_timeout(dev->wait_hw_ready,
  62 --
  63 2.19.1
  64