releases/4.19.35/net-mlx5-decrease-default-mr-cache-size.patch

   1 From 18ebbcd621e172be4417ae27cc339ff2efb04ada Mon Sep 17 00:00:00 2001
   2 From: Artemy Kovalyov <artemyko@mellanox.com>
   3 Date: Tue, 19 Mar 2019 11:24:38 +0200
   4 Subject: net/mlx5: Decrease default mr cache size
   5
   6 [ Upstream commit e8b26b2135dedc0284490bfeac06dfc4418d0105 ]
   7
   8 Delete initialization of high order entries in mr cache to decrease initial
   9 memory footprint. When required, the administrator can populate the
  10 entries with memory keys via the /sys interface.
  11
  12 This approach is very helpful to significantly reduce the per HW function
  13 memory footprint in virtualization environments such as SRIOV.
  14
  15 Fixes: 9603b61de1ee ("mlx5: Move pci device handling from mlx5_ib to mlx5_core")
  16 Signed-off-by: Artemy Kovalyov <artemyko@mellanox.com>
  17 Signed-off-by: Moni Shoua <monis@mellanox.com>
  18 Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
  19 Reported-by:  Shalom Toledo <shalomt@mellanox.com>
  20 Acked-by: Or Gerlitz <ogerlitz@mellanox.com>
  21 Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
  22 Signed-off-by: Sasha Levin <sashal@kernel.org>
  23 ---
  24  .../net/ethernet/mellanox/mlx5/core/main.c    | 20 -------------------
  25  1 file changed, 20 deletions(-)
  26
  27 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c
  28 index 563ce3fedab4..0e820cf92f8a 100644
  29 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c
  30 +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c
  31 @@ -162,26 +162,6 @@ static struct mlx5_profile profile[] = {
  32                         .size   = 8,
  33                         .limit  = 4
  34                 },
  35 -               .mr_cache[16]   = {
  36 -                       .size   = 8,
  37 -                       .limit  = 4
  38 -               },
  39 -               .mr_cache[17]   = {
  40 -                       .size   = 8,
  41 -                       .limit  = 4
  42 -               },
  43 -               .mr_cache[18]   = {
  44 -                       .size   = 8,
  45 -                       .limit  = 4
  46 -               },
  47 -               .mr_cache[19]   = {
  48 -                       .size   = 4,
  49 -                       .limit  = 2
  50 -               },
  51 -               .mr_cache[20]   = {
  52 -                       .size   = 4,
  53 -                       .limit  = 2
  54 -               },
  55         },
  56  };
  57
  58 --
  59 2.19.1
  60