releases/4.19.51/pci-keystone-prevent-arm32-specific-code-to-be-compi.patch

   1 From bd5d4593c79cfd56af12d91c911bd3a6abae2e44 Mon Sep 17 00:00:00 2001
   2 From: Kishon Vijay Abraham I <kishon@ti.com>
   3 Date: Mon, 25 Mar 2019 15:09:33 +0530
   4 Subject: PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64
   5
   6 [ Upstream commit f316a2b53cd7f37963ae20ec7072eb27a349a4ce ]
   7
   8 hook_fault_code() is an ARM32 specific API for hooking into data abort.
   9
  10 AM65X platforms (that integrate ARM v8 cores and select CONFIG_ARM64 as
  11 arch) rely on pci-keystone.c but on them the enumeration of a
  12 non-present BDF does not trigger a bus error, so the fixup exception
  13 provided by calling hook_fault_code() is not needed and can be guarded
  14 with CONFIG_ARM.
  15
  16 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  17 [lorenzo.pieralisi@arm.com: commit log]
  18 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  19 Signed-off-by: Sasha Levin <sashal@kernel.org>
  20 ---
  21  drivers/pci/controller/dwc/pci-keystone.c | 4 ++++
  22  1 file changed, 4 insertions(+)
  23
  24 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
  25 index e88bd221fffe..5e199e7d2d4f 100644
  26 --- a/drivers/pci/controller/dwc/pci-keystone.c
  27 +++ b/drivers/pci/controller/dwc/pci-keystone.c
  28 @@ -237,6 +237,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
  29                 ks_dw_pcie_enable_error_irq(ks_pcie);
  30  }
  31
  32 +#ifdef CONFIG_ARM
  33  /*
  34   * When a PCI device does not exist during config cycles, keystone host gets a
  35   * bus error instead of returning 0xffffffff. This handler always returns 0
  36 @@ -256,6 +257,7 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
  37
  38         return 0;
  39  }
  40 +#endif
  41
  42  static int __init ks_pcie_host_init(struct pcie_port *pp)
  43  {
  44 @@ -279,12 +281,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
  45         val |= BIT(12);
  46         writel(val, pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
  47
  48 +#ifdef CONFIG_ARM
  49         /*
  50          * PCIe access errors that result into OCP errors are caught by ARM as
  51          * "External aborts"
  52          */
  53         hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
  54                         "Asynchronous external abort");
  55 +#endif
  56
  57         return 0;
  58  }
  59 --
  60 2.20.1
  61