releases/5.0.8/drm-i915-dp-revert-back-to-max-link-rate-and-lane-count-on-edp.patch

   1 From 21635d7311734d2d1b177f8a95e2f9386174b76d Mon Sep 17 00:00:00 2001
   2 From: Jani Nikula <jani.nikula@intel.com>
   3 Date: Fri, 5 Apr 2019 10:52:20 +0300
   4 Subject: drm/i915/dp: revert back to max link rate and lane count on eDP
   5 MIME-Version: 1.0
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   8
   9 From: Jani Nikula <jani.nikula@intel.com>
  10
  11 commit 21635d7311734d2d1b177f8a95e2f9386174b76d upstream.
  12
  13 Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast
  14 and narrow") started to optize the eDP 1.4+ link config, both per spec
  15 and as preparation for display stream compression support.
  16
  17 Sadly, we again face panels that flat out fail with parameters they
  18 claim to support. Revert, and go back to the drawing board.
  19
  20 v2: Actually revert to max params instead of just wide-and-slow.
  21
  22 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959
  23 Fixes: 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow")
  24 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
  25 Cc: Manasi Navare <manasi.d.navare@intel.com>
  26 Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
  27 Cc: Matt Atwood <matthew.s.atwood@intel.com>
  28 Cc: "Lee, Shawn C" <shawn.c.lee@intel.com>
  29 Cc: Dave Airlie <airlied@gmail.com>
  30 Cc: intel-gfx@lists.freedesktop.org
  31 Cc: <stable@vger.kernel.org> # v5.0+
  32 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
  33 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
  34 Tested-by: Albert Astals Cid <aacid@kde.org> # v5.0 backport
  35 Tested-by: Emanuele Panigati <ilpanich@gmail.com> # v5.0 backport
  36 Tested-by: Matteo Iervasi <matteoiervasi@gmail.com> # v5.0 backport
  37 Signed-off-by: Jani Nikula <jani.nikula@intel.com>
  38 Link: https://patchwork.freedesktop.org/patch/msgid/20190405075220.9815-1-jani.nikula@intel.com
  39 (cherry picked from commit f11cb1c19ad0563b3c1ea5eb16a6bac0e401f428)
  40 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
  41 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  42
  43
  44 ---
  45  drivers/gpu/drm/i915/intel_dp.c |   69 +++++-----------------------------------
  46  1 file changed, 10 insertions(+), 59 deletions(-)
  47
  48 --- a/drivers/gpu/drm/i915/intel_dp.c
  49 +++ b/drivers/gpu/drm/i915/intel_dp.c
  50 @@ -1845,42 +1845,6 @@ intel_dp_compute_link_config_wide(struct
  51         return false;
  52  }
  53
  54 -/* Optimize link config in order: max bpp, min lanes, min clock */
  55 -static bool
  56 -intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
  57 -                                 struct intel_crtc_state *pipe_config,
  58 -                                 const struct link_config_limits *limits)
  59 -{
  60 -       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
  61 -       int bpp, clock, lane_count;
  62 -       int mode_rate, link_clock, link_avail;
  63 -
  64 -       for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
  65 -               mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
  66 -                                                  bpp);
  67 -
  68 -               for (lane_count = limits->min_lane_count;
  69 -                    lane_count <= limits->max_lane_count;
  70 -                    lane_count <<= 1) {
  71 -                       for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
  72 -                               link_clock = intel_dp->common_rates[clock];
  73 -                               link_avail = intel_dp_max_data_rate(link_clock,
  74 -                                                                   lane_count);
  75 -
  76 -                               if (mode_rate <= link_avail) {
  77 -                                       pipe_config->lane_count = lane_count;
  78 -                                       pipe_config->pipe_bpp = bpp;
  79 -                                       pipe_config->port_clock = link_clock;
  80 -
  81 -                                       return true;
  82 -                               }
  83 -                       }
  84 -               }
  85 -       }
  86 -
  87 -       return false;
  88 -}
  89 -
  90  static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
  91  {
  92         int i, num_bpc;
  93 @@ -2013,15 +1977,13 @@ intel_dp_compute_link_config(struct inte
  94         limits.min_bpp = 6 * 3;
  95         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
  96
  97 -       if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
  98 +       if (intel_dp_is_edp(intel_dp)) {
  99                 /*
 100                  * Use the maximum clock and number of lanes the eDP panel
 101 -                * advertizes being capable of. The eDP 1.3 and earlier panels
 102 -                * are generally designed to support only a single clock and
 103 -                * lane configuration, and typically these values correspond to
 104 -                * the native resolution of the panel. With eDP 1.4 rate select
 105 -                * and DSC, this is decreasingly the case, and we need to be
 106 -                * able to select less than maximum link config.
 107 +                * advertizes being capable of. The panels are generally
 108 +                * designed to support only a single clock and lane
 109 +                * configuration, and typically these values correspond to the
 110 +                * native resolution of the panel.
 111                  */
 112                 limits.min_lane_count = limits.max_lane_count;
 113                 limits.min_clock = limits.max_clock;
 114 @@ -2035,22 +1997,11 @@ intel_dp_compute_link_config(struct inte
 115                       intel_dp->common_rates[limits.max_clock],
 116                       limits.max_bpp, adjusted_mode->crtc_clock);
 117
 118 -       if (intel_dp_is_edp(intel_dp))
 119 -               /*
 120 -                * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
 121 -                * section A.1: "It is recommended that the minimum number of
 122 -                * lanes be used, using the minimum link rate allowed for that
 123 -                * lane configuration."
 124 -                *
 125 -                * Note that we use the max clock and lane count for eDP 1.3 and
 126 -                * earlier, and fast vs. wide is irrelevant.
 127 -                */
 128 -               ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
 129 -                                                       &limits);
 130 -       else
 131 -               /* Optimize for slow and wide. */
 132 -               ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
 133 -                                                       &limits);
 134 +       /*
 135 +        * Optimize for slow and wide. This is the place to add alternative
 136 +        * optimization policy.
 137 +        */
 138 +       ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
 139
 140         /* enable compression if the mode doesn't fit available BW */
 141         if (!ret) {