5.0-stable patches

added patches:
	drm-i915-dp-revert-back-to-max-link-rate-and-lane-count-on-edp.patch

diff --git a/queue-5.0/drm-i915-dp-revert-back-to-max-link-rate-and-lane-count-on-edp.patch b/queue-5.0/drm-i915-dp-revert-back-to-max-link-rate-and-lane-count-on-edp.patch
new file mode 100644 (file)
index 0000000..9f7933c
--- /dev/null
+++ b/queue-5.0/drm-i915-dp-revert-back-to-max-link-rate-and-lane-count-on-edp.patch
@@ -0,0 +1,141 @@
+From 21635d7311734d2d1b177f8a95e2f9386174b76d Mon Sep 17 00:00:00 2001
+From: Jani Nikula <jani.nikula@intel.com>
+Date: Fri, 5 Apr 2019 10:52:20 +0300
+Subject: drm/i915/dp: revert back to max link rate and lane count on eDP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Jani Nikula <jani.nikula@intel.com>
+
+commit 21635d7311734d2d1b177f8a95e2f9386174b76d upstream.
+
+Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast
+and narrow") started to optize the eDP 1.4+ link config, both per spec
+and as preparation for display stream compression support.
+
+Sadly, we again face panels that flat out fail with parameters they
+claim to support. Revert, and go back to the drawing board.
+
+v2: Actually revert to max params instead of just wide-and-slow.
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959
+Fixes: 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow")
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Manasi Navare <manasi.d.navare@intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: Matt Atwood <matthew.s.atwood@intel.com>
+Cc: "Lee, Shawn C" <shawn.c.lee@intel.com>
+Cc: Dave Airlie <airlied@gmail.com>
+Cc: intel-gfx@lists.freedesktop.org
+Cc: <stable@vger.kernel.org> # v5.0+
+Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
+Tested-by: Albert Astals Cid <aacid@kde.org> # v5.0 backport
+Tested-by: Emanuele Panigati <ilpanich@gmail.com> # v5.0 backport
+Tested-by: Matteo Iervasi <matteoiervasi@gmail.com> # v5.0 backport
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190405075220.9815-1-jani.nikula@intel.com
+(cherry picked from commit f11cb1c19ad0563b3c1ea5eb16a6bac0e401f428)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+
+---
+ drivers/gpu/drm/i915/intel_dp.c |   69 +++++-----------------------------------
+ 1 file changed, 10 insertions(+), 59 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -1845,42 +1845,6 @@ intel_dp_compute_link_config_wide(struct
+       return false;
+ }
+ 
+-/* Optimize link config in order: max bpp, min lanes, min clock */
+-static bool
+-intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
+-                                struct intel_crtc_state *pipe_config,
+-                                const struct link_config_limits *limits)
+-{
+-      struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+-      int bpp, clock, lane_count;
+-      int mode_rate, link_clock, link_avail;
+-
+-      for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+-              mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
+-                                                 bpp);
+-
+-              for (lane_count = limits->min_lane_count;
+-                   lane_count <= limits->max_lane_count;
+-                   lane_count <<= 1) {
+-                      for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
+-                              link_clock = intel_dp->common_rates[clock];
+-                              link_avail = intel_dp_max_data_rate(link_clock,
+-                                                                  lane_count);
+-
+-                              if (mode_rate <= link_avail) {
+-                                      pipe_config->lane_count = lane_count;
+-                                      pipe_config->pipe_bpp = bpp;
+-                                      pipe_config->port_clock = link_clock;
+-
+-                                      return true;
+-                              }
+-                      }
+-              }
+-      }
+-
+-      return false;
+-}
+-
+ static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+ {
+       int i, num_bpc;
+@@ -2013,15 +1977,13 @@ intel_dp_compute_link_config(struct inte
+       limits.min_bpp = 6 * 3;
+       limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
+ 
+-      if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
++      if (intel_dp_is_edp(intel_dp)) {
+               /*
+                * Use the maximum clock and number of lanes the eDP panel
+-               * advertizes being capable of. The eDP 1.3 and earlier panels
+-               * are generally designed to support only a single clock and
+-               * lane configuration, and typically these values correspond to
+-               * the native resolution of the panel. With eDP 1.4 rate select
+-               * and DSC, this is decreasingly the case, and we need to be
+-               * able to select less than maximum link config.
++               * advertizes being capable of. The panels are generally
++               * designed to support only a single clock and lane
++               * configuration, and typically these values correspond to the
++               * native resolution of the panel.
+                */
+               limits.min_lane_count = limits.max_lane_count;
+               limits.min_clock = limits.max_clock;
+@@ -2035,22 +1997,11 @@ intel_dp_compute_link_config(struct inte
+                     intel_dp->common_rates[limits.max_clock],
+                     limits.max_bpp, adjusted_mode->crtc_clock);
+ 
+-      if (intel_dp_is_edp(intel_dp))
+-              /*
+-               * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
+-               * section A.1: "It is recommended that the minimum number of
+-               * lanes be used, using the minimum link rate allowed for that
+-               * lane configuration."
+-               *
+-               * Note that we use the max clock and lane count for eDP 1.3 and
+-               * earlier, and fast vs. wide is irrelevant.
+-               */
+-              ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
+-                                                      &limits);
+-      else
+-              /* Optimize for slow and wide. */
+-              ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
+-                                                      &limits);
++      /*
++       * Optimize for slow and wide. This is the place to add alternative
++       * optimization policy.
++       */
++      ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
+ 
+       /* enable compression if the mode doesn't fit available BW */
+       if (!ret) {

diff --git a/queue-5.0/series b/queue-5.0/series
index b762c73a56023f35d9db28e5f882605a46475941..5c0b337e24c632aace664c1d975b68355785d0bb 100644 (file)
--- a/queue-5.0/series
+++ b/queue-5.0/series
@@ -81,3 +81,4 @@ block-fix-the-return-errno-for-direct-io.patch
 genirq-respect-irqchip_skip_set_wake-in-irq_chip_set_wake_parent.patch
 genirq-initialize-request_mutex-if-config_sparse_irq-n.patch
 virtio-honour-may_reduce_num-in-vring_create_virtqueue.patch
+drm-i915-dp-revert-back-to-max-link-rate-and-lane-count-on-edp.patch