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Commit | Line | Data |
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b3901d54 CM |
1 | /* |
2 | * Based on arch/arm/kernel/process.c | |
3 | * | |
4 | * Original Copyright (C) 1995 Linus Torvalds | |
5 | * Copyright (C) 1996-2000 Russell King - Converted to ARM. | |
6 | * Copyright (C) 2012 ARM Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <stdarg.h> | |
22 | ||
fd92d4a5 | 23 | #include <linux/compat.h> |
60c0d45a | 24 | #include <linux/efi.h> |
b3901d54 CM |
25 | #include <linux/export.h> |
26 | #include <linux/sched.h> | |
b17b0153 | 27 | #include <linux/sched/debug.h> |
29930025 | 28 | #include <linux/sched/task.h> |
68db0cf1 | 29 | #include <linux/sched/task_stack.h> |
b3901d54 CM |
30 | #include <linux/kernel.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/stddef.h> | |
33 | #include <linux/unistd.h> | |
34 | #include <linux/user.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/reboot.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/kallsyms.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/cpu.h> | |
41 | #include <linux/elfcore.h> | |
42 | #include <linux/pm.h> | |
43 | #include <linux/tick.h> | |
44 | #include <linux/utsname.h> | |
45 | #include <linux/uaccess.h> | |
46 | #include <linux/random.h> | |
47 | #include <linux/hw_breakpoint.h> | |
48 | #include <linux/personality.h> | |
49 | #include <linux/notifier.h> | |
096b3224 | 50 | #include <trace/events/power.h> |
c02433dd | 51 | #include <linux/percpu.h> |
bc0ee476 | 52 | #include <linux/thread_info.h> |
b3901d54 | 53 | |
57f4959b | 54 | #include <asm/alternative.h> |
b3901d54 CM |
55 | #include <asm/compat.h> |
56 | #include <asm/cacheflush.h> | |
d0854412 | 57 | #include <asm/exec.h> |
ec45d1cf WD |
58 | #include <asm/fpsimd.h> |
59 | #include <asm/mmu_context.h> | |
b3901d54 CM |
60 | #include <asm/processor.h> |
61 | #include <asm/stacktrace.h> | |
b3901d54 | 62 | |
c0c264ae LA |
63 | #ifdef CONFIG_CC_STACKPROTECTOR |
64 | #include <linux/stackprotector.h> | |
65 | unsigned long __stack_chk_guard __read_mostly; | |
66 | EXPORT_SYMBOL(__stack_chk_guard); | |
67 | #endif | |
68 | ||
b3901d54 CM |
69 | /* |
70 | * Function pointers to optional machine specific functions | |
71 | */ | |
72 | void (*pm_power_off)(void); | |
73 | EXPORT_SYMBOL_GPL(pm_power_off); | |
74 | ||
b0946fc8 | 75 | void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); |
b3901d54 | 76 | |
b3901d54 CM |
77 | /* |
78 | * This is our default idle handler. | |
79 | */ | |
0087298f | 80 | void arch_cpu_idle(void) |
b3901d54 CM |
81 | { |
82 | /* | |
83 | * This should do all the clock switching and wait for interrupt | |
84 | * tricks | |
85 | */ | |
096b3224 | 86 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
6990566b NP |
87 | cpu_do_idle(); |
88 | local_irq_enable(); | |
096b3224 | 89 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
b3901d54 CM |
90 | } |
91 | ||
9327e2c6 MR |
92 | #ifdef CONFIG_HOTPLUG_CPU |
93 | void arch_cpu_idle_dead(void) | |
94 | { | |
95 | cpu_die(); | |
96 | } | |
97 | #endif | |
98 | ||
90f51a09 AK |
99 | /* |
100 | * Called by kexec, immediately prior to machine_kexec(). | |
101 | * | |
102 | * This must completely disable all secondary CPUs; simply causing those CPUs | |
103 | * to execute e.g. a RAM-based pin loop is not sufficient. This allows the | |
104 | * kexec'd kernel to use any and all RAM as it sees fit, without having to | |
105 | * avoid any code or data used by any SW CPU pin loop. The CPU hotplug | |
106 | * functionality embodied in disable_nonboot_cpus() to achieve this. | |
107 | */ | |
b3901d54 CM |
108 | void machine_shutdown(void) |
109 | { | |
90f51a09 | 110 | disable_nonboot_cpus(); |
b3901d54 CM |
111 | } |
112 | ||
90f51a09 AK |
113 | /* |
114 | * Halting simply requires that the secondary CPUs stop performing any | |
115 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
116 | * achieves this. | |
117 | */ | |
b3901d54 CM |
118 | void machine_halt(void) |
119 | { | |
b9acc49e | 120 | local_irq_disable(); |
90f51a09 | 121 | smp_send_stop(); |
b3901d54 CM |
122 | while (1); |
123 | } | |
124 | ||
90f51a09 AK |
125 | /* |
126 | * Power-off simply requires that the secondary CPUs stop performing any | |
127 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
128 | * achieves this. When the system power is turned off, it will take all CPUs | |
129 | * with it. | |
130 | */ | |
b3901d54 CM |
131 | void machine_power_off(void) |
132 | { | |
b9acc49e | 133 | local_irq_disable(); |
90f51a09 | 134 | smp_send_stop(); |
b3901d54 CM |
135 | if (pm_power_off) |
136 | pm_power_off(); | |
137 | } | |
138 | ||
90f51a09 AK |
139 | /* |
140 | * Restart requires that the secondary CPUs stop performing any activity | |
68234df4 | 141 | * while the primary CPU resets the system. Systems with multiple CPUs must |
90f51a09 AK |
142 | * provide a HW restart implementation, to ensure that all CPUs reset at once. |
143 | * This is required so that any code running after reset on the primary CPU | |
144 | * doesn't have to co-ordinate with other CPUs to ensure they aren't still | |
145 | * executing pre-reset code, and using RAM that the primary CPU's code wishes | |
146 | * to use. Implementing such co-ordination would be essentially impossible. | |
147 | */ | |
b3901d54 CM |
148 | void machine_restart(char *cmd) |
149 | { | |
b3901d54 CM |
150 | /* Disable interrupts first */ |
151 | local_irq_disable(); | |
b9acc49e | 152 | smp_send_stop(); |
b3901d54 | 153 | |
60c0d45a AB |
154 | /* |
155 | * UpdateCapsule() depends on the system being reset via | |
156 | * ResetSystem(). | |
157 | */ | |
158 | if (efi_enabled(EFI_RUNTIME_SERVICES)) | |
159 | efi_reboot(reboot_mode, NULL); | |
160 | ||
b3901d54 | 161 | /* Now call the architecture specific reboot code. */ |
aa1e8ec1 | 162 | if (arm_pm_restart) |
ff701306 | 163 | arm_pm_restart(reboot_mode, cmd); |
1c7ffc32 GR |
164 | else |
165 | do_kernel_restart(cmd); | |
b3901d54 CM |
166 | |
167 | /* | |
168 | * Whoops - the architecture was unable to reboot. | |
169 | */ | |
170 | printk("Reboot failed -- System halted\n"); | |
171 | while (1); | |
172 | } | |
173 | ||
b7300d4c WD |
174 | static void print_pstate(struct pt_regs *regs) |
175 | { | |
176 | u64 pstate = regs->pstate; | |
177 | ||
178 | if (compat_user_mode(regs)) { | |
179 | printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c)\n", | |
180 | pstate, | |
181 | pstate & COMPAT_PSR_N_BIT ? 'N' : 'n', | |
182 | pstate & COMPAT_PSR_Z_BIT ? 'Z' : 'z', | |
183 | pstate & COMPAT_PSR_C_BIT ? 'C' : 'c', | |
184 | pstate & COMPAT_PSR_V_BIT ? 'V' : 'v', | |
185 | pstate & COMPAT_PSR_Q_BIT ? 'Q' : 'q', | |
186 | pstate & COMPAT_PSR_T_BIT ? "T32" : "A32", | |
187 | pstate & COMPAT_PSR_E_BIT ? "BE" : "LE", | |
188 | pstate & COMPAT_PSR_A_BIT ? 'A' : 'a', | |
189 | pstate & COMPAT_PSR_I_BIT ? 'I' : 'i', | |
190 | pstate & COMPAT_PSR_F_BIT ? 'F' : 'f'); | |
191 | } else { | |
192 | printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO)\n", | |
193 | pstate, | |
194 | pstate & PSR_N_BIT ? 'N' : 'n', | |
195 | pstate & PSR_Z_BIT ? 'Z' : 'z', | |
196 | pstate & PSR_C_BIT ? 'C' : 'c', | |
197 | pstate & PSR_V_BIT ? 'V' : 'v', | |
198 | pstate & PSR_D_BIT ? 'D' : 'd', | |
199 | pstate & PSR_A_BIT ? 'A' : 'a', | |
200 | pstate & PSR_I_BIT ? 'I' : 'i', | |
201 | pstate & PSR_F_BIT ? 'F' : 'f', | |
202 | pstate & PSR_PAN_BIT ? '+' : '-', | |
203 | pstate & PSR_UAO_BIT ? '+' : '-'); | |
204 | } | |
205 | } | |
206 | ||
b3901d54 CM |
207 | void __show_regs(struct pt_regs *regs) |
208 | { | |
6ca68e80 CM |
209 | int i, top_reg; |
210 | u64 lr, sp; | |
211 | ||
212 | if (compat_user_mode(regs)) { | |
213 | lr = regs->compat_lr; | |
214 | sp = regs->compat_sp; | |
215 | top_reg = 12; | |
216 | } else { | |
217 | lr = regs->regs[30]; | |
218 | sp = regs->sp; | |
219 | top_reg = 29; | |
220 | } | |
b3901d54 | 221 | |
a43cb95d | 222 | show_regs_print_info(KERN_DEFAULT); |
b7300d4c | 223 | print_pstate(regs); |
a25ffd3a WD |
224 | print_symbol("pc : %s\n", regs->pc); |
225 | print_symbol("lr : %s\n", lr); | |
b7300d4c | 226 | printk("sp : %016llx\n", sp); |
db4b0710 MR |
227 | |
228 | i = top_reg; | |
229 | ||
230 | while (i >= 0) { | |
b3901d54 | 231 | printk("x%-2d: %016llx ", i, regs->regs[i]); |
db4b0710 MR |
232 | i--; |
233 | ||
234 | if (i % 2 == 0) { | |
235 | pr_cont("x%-2d: %016llx ", i, regs->regs[i]); | |
236 | i--; | |
237 | } | |
238 | ||
239 | pr_cont("\n"); | |
b3901d54 | 240 | } |
b3901d54 CM |
241 | } |
242 | ||
243 | void show_regs(struct pt_regs * regs) | |
244 | { | |
b3901d54 | 245 | __show_regs(regs); |
1149aad1 | 246 | dump_backtrace(regs, NULL); |
b3901d54 CM |
247 | } |
248 | ||
eb35bdd7 WD |
249 | static void tls_thread_flush(void) |
250 | { | |
adf75899 | 251 | write_sysreg(0, tpidr_el0); |
eb35bdd7 WD |
252 | |
253 | if (is_compat_task()) { | |
254 | current->thread.tp_value = 0; | |
255 | ||
256 | /* | |
257 | * We need to ensure ordering between the shadow state and the | |
258 | * hardware state, so that we don't corrupt the hardware state | |
259 | * with a stale shadow state during context switch. | |
260 | */ | |
261 | barrier(); | |
adf75899 | 262 | write_sysreg(0, tpidrro_el0); |
eb35bdd7 WD |
263 | } |
264 | } | |
265 | ||
b3901d54 CM |
266 | void flush_thread(void) |
267 | { | |
268 | fpsimd_flush_thread(); | |
eb35bdd7 | 269 | tls_thread_flush(); |
b3901d54 CM |
270 | flush_ptrace_hw_breakpoint(current); |
271 | } | |
272 | ||
273 | void release_thread(struct task_struct *dead_task) | |
274 | { | |
275 | } | |
276 | ||
bc0ee476 DM |
277 | void arch_release_task_struct(struct task_struct *tsk) |
278 | { | |
279 | fpsimd_release_task(tsk); | |
280 | } | |
281 | ||
282 | /* | |
283 | * src and dst may temporarily have aliased sve_state after task_struct | |
284 | * is copied. We cannot fix this properly here, because src may have | |
285 | * live SVE state and dst's thread_info may not exist yet, so tweaking | |
286 | * either src's or dst's TIF_SVE is not safe. | |
287 | * | |
288 | * The unaliasing is done in copy_thread() instead. This works because | |
289 | * dst is not schedulable or traceable until both of these functions | |
290 | * have been called. | |
291 | */ | |
b3901d54 CM |
292 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
293 | { | |
6eb6c801 JL |
294 | if (current->mm) |
295 | fpsimd_preserve_current_state(); | |
b3901d54 | 296 | *dst = *src; |
bc0ee476 | 297 | |
b3901d54 CM |
298 | return 0; |
299 | } | |
300 | ||
301 | asmlinkage void ret_from_fork(void) asm("ret_from_fork"); | |
302 | ||
303 | int copy_thread(unsigned long clone_flags, unsigned long stack_start, | |
afa86fc4 | 304 | unsigned long stk_sz, struct task_struct *p) |
b3901d54 CM |
305 | { |
306 | struct pt_regs *childregs = task_pt_regs(p); | |
b3901d54 | 307 | |
c34501d2 | 308 | memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context)); |
b3901d54 | 309 | |
bc0ee476 DM |
310 | /* |
311 | * Unalias p->thread.sve_state (if any) from the parent task | |
312 | * and disable discard SVE state for p: | |
313 | */ | |
314 | clear_tsk_thread_flag(p, TIF_SVE); | |
315 | p->thread.sve_state = NULL; | |
316 | ||
9ac08002 AV |
317 | if (likely(!(p->flags & PF_KTHREAD))) { |
318 | *childregs = *current_pt_regs(); | |
c34501d2 | 319 | childregs->regs[0] = 0; |
d00a3810 WD |
320 | |
321 | /* | |
322 | * Read the current TLS pointer from tpidr_el0 as it may be | |
323 | * out-of-sync with the saved value. | |
324 | */ | |
adf75899 | 325 | *task_user_tls(p) = read_sysreg(tpidr_el0); |
d00a3810 WD |
326 | |
327 | if (stack_start) { | |
328 | if (is_compat_thread(task_thread_info(p))) | |
e0fd18ce | 329 | childregs->compat_sp = stack_start; |
d00a3810 | 330 | else |
e0fd18ce | 331 | childregs->sp = stack_start; |
c34501d2 | 332 | } |
d00a3810 | 333 | |
b3901d54 | 334 | /* |
c34501d2 CM |
335 | * If a TLS pointer was passed to clone (4th argument), use it |
336 | * for the new thread. | |
b3901d54 | 337 | */ |
c34501d2 | 338 | if (clone_flags & CLONE_SETTLS) |
d00a3810 | 339 | p->thread.tp_value = childregs->regs[3]; |
c34501d2 CM |
340 | } else { |
341 | memset(childregs, 0, sizeof(struct pt_regs)); | |
342 | childregs->pstate = PSR_MODE_EL1h; | |
57f4959b | 343 | if (IS_ENABLED(CONFIG_ARM64_UAO) && |
a4023f68 | 344 | cpus_have_const_cap(ARM64_HAS_UAO)) |
57f4959b | 345 | childregs->pstate |= PSR_UAO_BIT; |
c34501d2 CM |
346 | p->thread.cpu_context.x19 = stack_start; |
347 | p->thread.cpu_context.x20 = stk_sz; | |
b3901d54 | 348 | } |
b3901d54 | 349 | p->thread.cpu_context.pc = (unsigned long)ret_from_fork; |
c34501d2 | 350 | p->thread.cpu_context.sp = (unsigned long)childregs; |
b3901d54 CM |
351 | |
352 | ptrace_hw_copy_thread(p); | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
936eb65c DM |
357 | void tls_preserve_current_state(void) |
358 | { | |
359 | *task_user_tls(current) = read_sysreg(tpidr_el0); | |
360 | } | |
361 | ||
b3901d54 CM |
362 | static void tls_thread_switch(struct task_struct *next) |
363 | { | |
364 | unsigned long tpidr, tpidrro; | |
365 | ||
936eb65c | 366 | tls_preserve_current_state(); |
b3901d54 | 367 | |
d00a3810 WD |
368 | tpidr = *task_user_tls(next); |
369 | tpidrro = is_compat_thread(task_thread_info(next)) ? | |
370 | next->thread.tp_value : 0; | |
b3901d54 | 371 | |
adf75899 MR |
372 | write_sysreg(tpidr, tpidr_el0); |
373 | write_sysreg(tpidrro, tpidrro_el0); | |
b3901d54 CM |
374 | } |
375 | ||
57f4959b | 376 | /* Restore the UAO state depending on next's addr_limit */ |
d0854412 | 377 | void uao_thread_switch(struct task_struct *next) |
57f4959b | 378 | { |
e950631e CM |
379 | if (IS_ENABLED(CONFIG_ARM64_UAO)) { |
380 | if (task_thread_info(next)->addr_limit == KERNEL_DS) | |
381 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); | |
382 | else | |
383 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO)); | |
384 | } | |
57f4959b JM |
385 | } |
386 | ||
c02433dd MR |
387 | /* |
388 | * We store our current task in sp_el0, which is clobbered by userspace. Keep a | |
389 | * shadow copy so that we can restore this upon entry from userspace. | |
390 | * | |
391 | * This is *only* for exception entry from EL0, and is not valid until we | |
392 | * __switch_to() a user task. | |
393 | */ | |
394 | DEFINE_PER_CPU(struct task_struct *, __entry_task); | |
395 | ||
396 | static void entry_task_switch(struct task_struct *next) | |
397 | { | |
398 | __this_cpu_write(__entry_task, next); | |
399 | } | |
400 | ||
b3901d54 CM |
401 | /* |
402 | * Thread switching. | |
403 | */ | |
8f4b326d | 404 | __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, |
b3901d54 CM |
405 | struct task_struct *next) |
406 | { | |
407 | struct task_struct *last; | |
408 | ||
409 | fpsimd_thread_switch(next); | |
410 | tls_thread_switch(next); | |
411 | hw_breakpoint_thread_switch(next); | |
3325732f | 412 | contextidr_thread_switch(next); |
c02433dd | 413 | entry_task_switch(next); |
57f4959b | 414 | uao_thread_switch(next); |
b3901d54 | 415 | |
5108c67c CM |
416 | /* |
417 | * Complete any pending TLB or cache maintenance on this CPU in case | |
418 | * the thread migrates to a different CPU. | |
22e4ebb9 MD |
419 | * This full barrier is also required by the membarrier system |
420 | * call. | |
5108c67c | 421 | */ |
98f7685e | 422 | dsb(ish); |
b3901d54 CM |
423 | |
424 | /* the actual thread switch */ | |
425 | last = cpu_switch_to(prev, next); | |
426 | ||
427 | return last; | |
428 | } | |
429 | ||
b3901d54 CM |
430 | unsigned long get_wchan(struct task_struct *p) |
431 | { | |
432 | struct stackframe frame; | |
9bbd4c56 | 433 | unsigned long stack_page, ret = 0; |
b3901d54 CM |
434 | int count = 0; |
435 | if (!p || p == current || p->state == TASK_RUNNING) | |
436 | return 0; | |
437 | ||
9bbd4c56 MR |
438 | stack_page = (unsigned long)try_get_task_stack(p); |
439 | if (!stack_page) | |
440 | return 0; | |
441 | ||
b3901d54 | 442 | frame.fp = thread_saved_fp(p); |
b3901d54 | 443 | frame.pc = thread_saved_pc(p); |
20380bb3 AT |
444 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
445 | frame.graph = p->curr_ret_stack; | |
446 | #endif | |
b3901d54 | 447 | do { |
31e43ad3 | 448 | if (unwind_frame(p, &frame)) |
9bbd4c56 MR |
449 | goto out; |
450 | if (!in_sched_functions(frame.pc)) { | |
451 | ret = frame.pc; | |
452 | goto out; | |
453 | } | |
b3901d54 | 454 | } while (count ++ < 16); |
9bbd4c56 MR |
455 | |
456 | out: | |
457 | put_task_stack(p); | |
458 | return ret; | |
b3901d54 CM |
459 | } |
460 | ||
461 | unsigned long arch_align_stack(unsigned long sp) | |
462 | { | |
463 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
464 | sp -= get_random_int() & ~PAGE_MASK; | |
465 | return sp & ~0xf; | |
466 | } | |
467 | ||
b3901d54 CM |
468 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
469 | { | |
61462c8a | 470 | if (is_compat_task()) |
ffe3d1e4 | 471 | return randomize_page(mm->brk, SZ_32M); |
61462c8a | 472 | else |
ffe3d1e4 | 473 | return randomize_page(mm->brk, SZ_1G); |
b3901d54 | 474 | } |
d1be5c99 YN |
475 | |
476 | /* | |
477 | * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY. | |
478 | */ | |
479 | void arch_setup_new_exec(void) | |
480 | { | |
481 | current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0; | |
482 | } |