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KVM: Document KVM specific review items
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
043405e1 58
313a3dc7 59#define MAX_IO_MSRS 256
a03490ed
CO		 60#define CR0_RESERVED_BITS \
61 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
62 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
63 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
64#define CR4_RESERVED_BITS \
65 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
66 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
67 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 68 | X86_CR4_OSXSAVE \
a03490ed
CO		 69 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
70
71#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 72
73#define KVM_MAX_MCE_BANKS 32
74#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
75
50a37eb4
JR		 76/* EFER defaults:
77 * - enable syscall per default because its emulated by KVM
78 * - enable LME and LMA per default on 64 bit KVM
79 */
80#ifdef CONFIG_X86_64
81static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
82#else
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 90static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
91 struct kvm_cpuid_entry2 __user *entries);
92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
ed85c068
AP		 96int ignore_msrs = 0;
97module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
18863bdd
AK		 99#define KVM_NR_SHARED_MSRS 16
100
101struct kvm_shared_msrs_global {
102 int nr;
2bf78fa7 103 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106struct kvm_shared_msrs {
107 struct user_return_notifier urn;
108 bool registered;
2bf78fa7
SY		 109 struct kvm_shared_msr_values {
110 u64 host;
111 u64 curr;
112 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 113};
114
115static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
117
417bc304 118struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 131 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 139 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 140 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 148 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 150 { "largepages", VM_STAT(lpages) },
417bc304
HB		 151 { NULL }
152};
153
2acf923e
DC		 154u64 __read_mostly host_xcr0;
155
156static inline u32 bit(int bitno)
157{
158 return 1 << (bitno & 31);
159}
160
18863bdd
AK		 161static void kvm_on_user_return(struct user_return_notifier *urn)
162{
163 unsigned slot;
18863bdd
AK		 164 struct kvm_shared_msrs *locals
165 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 166 struct kvm_shared_msr_values *values;
18863bdd
AK		 167
168 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 169 values = &locals->values[slot];
170 if (values->host != values->curr) {
171 wrmsrl(shared_msrs_global.msrs[slot], values->host);
172 values->curr = values->host;
18863bdd
AK		 173 }
174 }
175 locals->registered = false;
176 user_return_notifier_unregister(urn);
177}
178
2bf78fa7 179static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 180{
2bf78fa7 181 struct kvm_shared_msrs *smsr;
18863bdd
AK		 182 u64 value;
183
2bf78fa7
SY		 184 smsr = &__get_cpu_var(shared_msrs);
185 /* only read, and nobody should modify it at this time,
186 * so don't need lock */
187 if (slot >= shared_msrs_global.nr) {
188 printk(KERN_ERR "kvm: invalid MSR slot!");
189 return;
190 }
191 rdmsrl_safe(msr, &value);
192 smsr->values[slot].host = value;
193 smsr->values[slot].curr = value;
194}
195
196void kvm_define_shared_msr(unsigned slot, u32 msr)
197{
18863bdd
AK		 198 if (slot >= shared_msrs_global.nr)
199 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 200 shared_msrs_global.msrs[slot] = msr;
201 /* we need ensured the shared_msr_global have been updated */
202 smp_wmb();
18863bdd
AK		 203}
204EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
205
206static void kvm_shared_msr_cpu_online(void)
207{
208 unsigned i;
18863bdd
AK		 209
210 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 211 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 212}
213
d5696725 214void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 215{
216 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
217
2bf78fa7 218 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 219 return;
2bf78fa7
SY		 220 smsr->values[slot].curr = value;
221 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 222 if (!smsr->registered) {
223 smsr->urn.on_user_return = kvm_on_user_return;
224 user_return_notifier_register(&smsr->urn);
225 smsr->registered = true;
226 }
227}
228EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
229
3548bab5
AK		 230static void drop_user_return_notifiers(void *ignore)
231{
232 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
233
234 if (smsr->registered)
235 kvm_on_user_return(&smsr->urn);
236}
237
6866b83e
CO		 238u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
239{
240 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 241 return vcpu->arch.apic_base;
6866b83e 242 else
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e
CO		 244}
245EXPORT_SYMBOL_GPL(kvm_get_apic_base);
246
247void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
248{
249 /* TODO: reserve bits check */
250 if (irqchip_in_kernel(vcpu->kvm))
251 kvm_lapic_set_base(vcpu, data);
252 else
ad312c7c 253 vcpu->arch.apic_base = data;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_set_apic_base);
256
3fd28fce
ED		 257#define EXCPT_BENIGN 0
258#define EXCPT_CONTRIBUTORY 1
259#define EXCPT_PF 2
260
261static int exception_class(int vector)
262{
263 switch (vector) {
264 case PF_VECTOR:
265 return EXCPT_PF;
266 case DE_VECTOR:
267 case TS_VECTOR:
268 case NP_VECTOR:
269 case SS_VECTOR:
270 case GP_VECTOR:
271 return EXCPT_CONTRIBUTORY;
272 default:
273 break;
274 }
275 return EXCPT_BENIGN;
276}
277
278static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 279 unsigned nr, bool has_error, u32 error_code,
280 bool reinject)
3fd28fce
ED		 281{
282 u32 prev_nr;
283 int class1, class2;
284
285 if (!vcpu->arch.exception.pending) {
286 queue:
287 vcpu->arch.exception.pending = true;
288 vcpu->arch.exception.has_error_code = has_error;
289 vcpu->arch.exception.nr = nr;
290 vcpu->arch.exception.error_code = error_code;
3f0fd292 291 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 292 return;
293 }
294
295 /* to check exception */
296 prev_nr = vcpu->arch.exception.nr;
297 if (prev_nr == DF_VECTOR) {
298 /* triple fault -> shutdown */
a8eeb04a 299 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 300 return;
301 }
302 class1 = exception_class(prev_nr);
303 class2 = exception_class(nr);
304 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
305 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
306 /* generate double fault per SDM Table 5-5 */
307 vcpu->arch.exception.pending = true;
308 vcpu->arch.exception.has_error_code = true;
309 vcpu->arch.exception.nr = DF_VECTOR;
310 vcpu->arch.exception.error_code = 0;
311 } else
312 /* replace previous exception with a new one in a hope
313 that instruction re-execution will regenerate lost
314 exception */
315 goto queue;
316}
317
298101da
AK		 318void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
319{
ce7ddec4 320 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 321}
322EXPORT_SYMBOL_GPL(kvm_queue_exception);
323
ce7ddec4
JR		 324void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
326 kvm_multiple_exception(vcpu, nr, false, 0, true);
327}
328EXPORT_SYMBOL_GPL(kvm_requeue_exception);
329
c3c91fee
AK		 330void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
331 u32 error_code)
332{
333 ++vcpu->stat.pf_guest;
ad312c7c 334 vcpu->arch.cr2 = addr;
c3c91fee
AK		 335 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
336}
337
3419ffc8
SY		 338void kvm_inject_nmi(struct kvm_vcpu *vcpu)
339{
340 vcpu->arch.nmi_pending = 1;
341}
342EXPORT_SYMBOL_GPL(kvm_inject_nmi);
343
298101da
AK		 344void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
345{
ce7ddec4 346 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 347}
348EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
349
ce7ddec4
JR		 350void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
351{
352 kvm_multiple_exception(vcpu, nr, true, error_code, true);
353}
354EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
355
0a79b009
AK		 356/*
357 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
358 * a #GP and return false.
359 */
360bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 361{
0a79b009
AK		 362 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
363 return true;
364 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
365 return false;
298101da 366}
0a79b009 367EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 368
a03490ed
CO		 369/*
370 * Load the pae pdptrs. Return true is they are all valid.
371 */
372int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
373{
374 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
375 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
376 int i;
377 int ret;
ad312c7c 378 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 379
a03490ed
CO		 380 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
381 offset * sizeof(u64), sizeof(pdpte));
382 if (ret < 0) {
383 ret = 0;
384 goto out;
385 }
386 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 387 if (is_present_gpte(pdpte[i]) &&
20c466b5 388 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 389 ret = 0;
390 goto out;
391 }
392 }
393 ret = 1;
394
ad312c7c 395 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 396 __set_bit(VCPU_EXREG_PDPTR,
397 (unsigned long *)&vcpu->arch.regs_avail);
398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 400out:
a03490ed
CO		 401
402 return ret;
403}
cc4b6871 404EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 405
d835dfec
AK		 406static bool pdptrs_changed(struct kvm_vcpu *vcpu)
407{
ad312c7c 408 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 409 bool changed = true;
410 int r;
411
412 if (is_long_mode(vcpu) || !is_pae(vcpu))
413 return false;
414
6de4f3ad
AK		 415 if (!test_bit(VCPU_EXREG_PDPTR,
416 (unsigned long *)&vcpu->arch.regs_avail))
417 return true;
418
ad312c7c 419 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 420 if (r < 0)
421 goto out;
ad312c7c 422 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 423out:
d835dfec
AK		 424
425 return changed;
426}
427
49a9b07e 428int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 429{
aad82703
SY		 430 unsigned long old_cr0 = kvm_read_cr0(vcpu);
431 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
432 X86_CR0_CD | X86_CR0_NW;
433
f9a48e6a
AK		 434 cr0 |= X86_CR0_ET;
435
ab344828 436#ifdef CONFIG_X86_64
0f12244f
GN		 437 if (cr0 & 0xffffffff00000000UL)
438 return 1;
ab344828
GN		 439#endif
440
441 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 442
0f12244f
GN		 443 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
444 return 1;
a03490ed 445
0f12244f
GN		 446 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
447 return 1;
a03490ed
CO		 448
449 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
450#ifdef CONFIG_X86_64
f6801dff 451 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 452 int cs_db, cs_l;
453
0f12244f
GN		 454 if (!is_pae(vcpu))
455 return 1;
a03490ed 456 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 457 if (cs_l)
458 return 1;
a03490ed
CO		 459 } else
460#endif
0f12244f
GN		 461 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
462 return 1;
a03490ed
CO		 463 }
464
465 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 466
aad82703
SY		 467 if ((cr0 ^ old_cr0) & update_bits)
468 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 469 return 0;
470}
2d3ad1f4 471EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 472
2d3ad1f4 473void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 474{
49a9b07e 475 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 476}
2d3ad1f4 477EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 478
2acf923e
DC		 479int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
480{
481 u64 xcr0;
482
483 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
484 if (index != XCR_XFEATURE_ENABLED_MASK)
485 return 1;
486 xcr0 = xcr;
487 if (kvm_x86_ops->get_cpl(vcpu) != 0)
488 return 1;
489 if (!(xcr0 & XSTATE_FP))
490 return 1;
491 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
492 return 1;
493 if (xcr0 & ~host_xcr0)
494 return 1;
495 vcpu->arch.xcr0 = xcr0;
496 vcpu->guest_xcr0_loaded = 0;
497 return 0;
498}
499
500int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
501{
502 if (__kvm_set_xcr(vcpu, index, xcr)) {
503 kvm_inject_gp(vcpu, 0);
504 return 1;
505 }
506 return 0;
507}
508EXPORT_SYMBOL_GPL(kvm_set_xcr);
509
510static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
511{
512 struct kvm_cpuid_entry2 *best;
513
514 best = kvm_find_cpuid_entry(vcpu, 1, 0);
515 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
516}
517
518static void update_cpuid(struct kvm_vcpu *vcpu)
519{
520 struct kvm_cpuid_entry2 *best;
521
522 best = kvm_find_cpuid_entry(vcpu, 1, 0);
523 if (!best)
524 return;
525
526 /* Update OSXSAVE bit */
527 if (cpu_has_xsave && best->function == 0x1) {
528 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
529 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
530 best->ecx |= bit(X86_FEATURE_OSXSAVE);
531 }
532}
533
a83b29c6 534int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 535{
fc78f519 536 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 537 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
538
0f12244f
GN		 539 if (cr4 & CR4_RESERVED_BITS)
540 return 1;
a03490ed 541
2acf923e
DC		 542 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
543 return 1;
544
a03490ed 545 if (is_long_mode(vcpu)) {
0f12244f
GN		 546 if (!(cr4 & X86_CR4_PAE))
547 return 1;
a2edf57f
AK		 548 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
549 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 550 && !load_pdptrs(vcpu, vcpu->arch.cr3))
551 return 1;
552
553 if (cr4 & X86_CR4_VMXE)
554 return 1;
a03490ed 555
a03490ed 556 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 557
aad82703
SY		 558 if ((cr4 ^ old_cr4) & pdptr_bits)
559 kvm_mmu_reset_context(vcpu);
0f12244f 560
2acf923e
DC		 561 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
562 update_cpuid(vcpu);
563
0f12244f
GN		 564 return 0;
565}
2d3ad1f4 566EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 567
2390218b 568int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 569{
ad312c7c 570 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 571 kvm_mmu_sync_roots(vcpu);
d835dfec 572 kvm_mmu_flush_tlb(vcpu);
0f12244f 573 return 0;
d835dfec
AK		 574 }
575
a03490ed 576 if (is_long_mode(vcpu)) {
0f12244f
GN		 577 if (cr3 & CR3_L_MODE_RESERVED_BITS)
578 return 1;
a03490ed
CO		 579 } else {
580 if (is_pae(vcpu)) {
0f12244f
GN		 581 if (cr3 & CR3_PAE_RESERVED_BITS)
582 return 1;
583 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
584 return 1;
a03490ed
CO		 585 }
586 /*
587 * We don't check reserved bits in nonpae mode, because
588 * this isn't enforced, and VMware depends on this.
589 */
590 }
591
a03490ed
CO		 592 /*
593 * Does the new cr3 value map to physical memory? (Note, we
594 * catch an invalid cr3 even in real-mode, because it would
595 * cause trouble later on when we turn on paging anyway.)
596 *
597 * A real CPU would silently accept an invalid cr3 and would
598 * attempt to use it - with largely undefined (and often hard
599 * to debug) behavior on the guest side.
600 */
601 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 602 return 1;
603 vcpu->arch.cr3 = cr3;
604 vcpu->arch.mmu.new_cr3(vcpu);
605 return 0;
606}
2d3ad1f4 607EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 608
0f12244f 609int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 610{
0f12244f
GN		 611 if (cr8 & CR8_RESERVED_BITS)
612 return 1;
a03490ed
CO		 613 if (irqchip_in_kernel(vcpu->kvm))
614 kvm_lapic_set_tpr(vcpu, cr8);
615 else
ad312c7c 616 vcpu->arch.cr8 = cr8;
0f12244f
GN		 617 return 0;
618}
619
620void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
621{
622 if (__kvm_set_cr8(vcpu, cr8))
623 kvm_inject_gp(vcpu, 0);
a03490ed 624}
2d3ad1f4 625EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 626
2d3ad1f4 627unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 628{
629 if (irqchip_in_kernel(vcpu->kvm))
630 return kvm_lapic_get_cr8(vcpu);
631 else
ad312c7c 632 return vcpu->arch.cr8;
a03490ed 633}
2d3ad1f4 634EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 635
338dbc97 636static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 637{
638 switch (dr) {
639 case 0 ... 3:
640 vcpu->arch.db[dr] = val;
641 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
642 vcpu->arch.eff_db[dr] = val;
643 break;
644 case 4:
338dbc97
GN		 645 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
646 return 1; /* #UD */
020df079
GN		 647 /* fall through */
648 case 6:
338dbc97
GN		 649 if (val & 0xffffffff00000000ULL)
650 return -1; /* #GP */
020df079
GN		 651 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
652 break;
653 case 5:
338dbc97
GN		 654 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
655 return 1; /* #UD */
020df079
GN		 656 /* fall through */
657 default: /* 7 */
338dbc97
GN		 658 if (val & 0xffffffff00000000ULL)
659 return -1; /* #GP */
020df079
GN		 660 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
661 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
662 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
663 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
664 }
665 break;
666 }
667
668 return 0;
669}
338dbc97
GN		 670
671int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
672{
673 int res;
674
675 res = __kvm_set_dr(vcpu, dr, val);
676 if (res > 0)
677 kvm_queue_exception(vcpu, UD_VECTOR);
678 else if (res < 0)
679 kvm_inject_gp(vcpu, 0);
680
681 return res;
682}
020df079
GN		 683EXPORT_SYMBOL_GPL(kvm_set_dr);
684
338dbc97 685static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 686{
687 switch (dr) {
688 case 0 ... 3:
689 *val = vcpu->arch.db[dr];
690 break;
691 case 4:
338dbc97 692 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 693 return 1;
020df079
GN		 694 /* fall through */
695 case 6:
696 *val = vcpu->arch.dr6;
697 break;
698 case 5:
338dbc97 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 700 return 1;
020df079
GN		 701 /* fall through */
702 default: /* 7 */
703 *val = vcpu->arch.dr7;
704 break;
705 }
706
707 return 0;
708}
338dbc97
GN		 709
710int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
711{
712 if (_kvm_get_dr(vcpu, dr, val)) {
713 kvm_queue_exception(vcpu, UD_VECTOR);
714 return 1;
715 }
716 return 0;
717}
020df079
GN		 718EXPORT_SYMBOL_GPL(kvm_get_dr);
719
043405e1
CO		 720/*
721 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
722 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
723 *
724 * This list is modified at module load time to reflect the
e3267cbb
GC		 725 * capabilities of the host cpu. This capabilities test skips MSRs that are
726 * kvm-specific. Those are put in the beginning of the list.
043405e1 727 */
e3267cbb 728
11c6bffa 729#define KVM_SAVE_MSRS_BEGIN 7
043405e1 730static u32 msrs_to_save[] = {
e3267cbb 731 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 732 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 733 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 734 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 735 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
736 MSR_K6_STAR,
737#ifdef CONFIG_X86_64
738 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
739#endif
e3267cbb 740 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 741};
742
743static unsigned num_msrs_to_save;
744
745static u32 emulated_msrs[] = {
746 MSR_IA32_MISC_ENABLE,
747};
748
b69e8cae 749static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 750{
aad82703
SY		 751 u64 old_efer = vcpu->arch.efer;
752
b69e8cae
RJ		 753 if (efer & efer_reserved_bits)
754 return 1;
15c4a640
CO		 755
756 if (is_paging(vcpu)
b69e8cae
RJ		 757 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
758 return 1;
15c4a640 759
1b2fd70c
AG		 760 if (efer & EFER_FFXSR) {
761 struct kvm_cpuid_entry2 *feat;
762
763 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 764 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
765 return 1;
1b2fd70c
AG		 766 }
767
d8017474
AG		 768 if (efer & EFER_SVME) {
769 struct kvm_cpuid_entry2 *feat;
770
771 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 772 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
773 return 1;
d8017474
AG		 774 }
775
15c4a640 776 efer &= ~EFER_LMA;
f6801dff 777 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 778
a3d204e2
SY		 779 kvm_x86_ops->set_efer(vcpu, efer);
780
9645bb56
AK		 781 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
782 kvm_mmu_reset_context(vcpu);
b69e8cae 783
aad82703
SY		 784 /* Update reserved bits */
785 if ((efer ^ old_efer) & EFER_NX)
786 kvm_mmu_reset_context(vcpu);
787
b69e8cae 788 return 0;
15c4a640
CO		 789}
790
f2b4b7dd
JR		 791void kvm_enable_efer_bits(u64 mask)
792{
793 efer_reserved_bits &= ~mask;
794}
795EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
796
797
15c4a640
CO		 798/*
799 * Writes msr value into into the appropriate "register".
800 * Returns 0 on success, non-0 otherwise.
801 * Assumes vcpu_load() was already called.
802 */
803int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
804{
805 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
806}
807
313a3dc7
CO		 808/*
809 * Adapt set_msr() to msr_io()'s calling convention
810 */
811static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
812{
813 return kvm_set_msr(vcpu, index, *data);
814}
815
18068523
GOC		 816static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
817{
9ed3c444
AK		 818 int version;
819 int r;
50d0a0f9 820 struct pvclock_wall_clock wc;
923de3cf 821 struct timespec boot;
18068523
GOC		 822
823 if (!wall_clock)
824 return;
825
9ed3c444
AK		 826 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
827 if (r)
828 return;
829
830 if (version & 1)
831 ++version; /* first time write, random junk */
832
833 ++version;
18068523 834
18068523
GOC		 835 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
836
50d0a0f9
GH		 837 /*
838 * The guest calculates current wall clock time by adding
839 * system time (updated by kvm_write_guest_time below) to the
840 * wall clock specified here. guest system time equals host
841 * system time for us, thus we must fill in host boot time here.
842 */
923de3cf 843 getboottime(&boot);
50d0a0f9
GH		 844
845 wc.sec = boot.tv_sec;
846 wc.nsec = boot.tv_nsec;
847 wc.version = version;
18068523
GOC		 848
849 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
850
851 version++;
852 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 853}
854
50d0a0f9
GH		 855static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
856{
857 uint32_t quotient, remainder;
858
859 /* Don't try to replace with do_div(), this one calculates
860 * "(dividend << 32) / divisor" */
861 __asm__ ( "divl %4"
862 : "=a" (quotient), "=d" (remainder)
863 : "0" (0), "1" (dividend), "r" (divisor) );
864 return quotient;
865}
866
867static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
868{
869 uint64_t nsecs = 1000000000LL;
870 int32_t shift = 0;
871 uint64_t tps64;
872 uint32_t tps32;
873
874 tps64 = tsc_khz * 1000LL;
875 while (tps64 > nsecs*2) {
876 tps64 >>= 1;
877 shift--;
878 }
879
880 tps32 = (uint32_t)tps64;
881 while (tps32 <= (uint32_t)nsecs) {
882 tps32 <<= 1;
883 shift++;
884 }
885
886 hv_clock->tsc_shift = shift;
887 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
888
889 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 890 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 891 hv_clock->tsc_to_system_mul);
892}
893
c8076604
GH		 894static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
895
18068523
GOC		 896static void kvm_write_guest_time(struct kvm_vcpu *v)
897{
898 struct timespec ts;
899 unsigned long flags;
900 struct kvm_vcpu_arch *vcpu = &v->arch;
901 void *shared_kaddr;
463656c0 902 unsigned long this_tsc_khz;
18068523
GOC		 903
904 if ((!vcpu->time_page))
905 return;
906
463656c0
AK		 907 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
908 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
909 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
910 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 911 }
463656c0 912 put_cpu_var(cpu_tsc_khz);
50d0a0f9 913
18068523
GOC		 914 /* Keep irq disabled to prevent changes to the clock */
915 local_irq_save(flags);
af24a4e4 916 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 917 ktime_get_ts(&ts);
923de3cf 918 monotonic_to_bootbased(&ts);
18068523
GOC		 919 local_irq_restore(flags);
920
921 /* With all the info we got, fill in the values */
922
923 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 924 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
925
371bcf64
GC		 926 vcpu->hv_clock.flags = 0;
927
18068523
GOC		 928 /*
929 * The interface expects us to write an even number signaling that the
930 * update is finished. Since the guest won't see the intermediate
50d0a0f9 931 * state, we just increase by 2 at the end.
18068523 932 */
50d0a0f9 933 vcpu->hv_clock.version += 2;
18068523
GOC		 934
935 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
936
937 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 938 sizeof(vcpu->hv_clock));
18068523
GOC		 939
940 kunmap_atomic(shared_kaddr, KM_USER0);
941
942 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
943}
944
c8076604
GH		 945static int kvm_request_guest_time_update(struct kvm_vcpu *v)
946{
947 struct kvm_vcpu_arch *vcpu = &v->arch;
948
949 if (!vcpu->time_page)
950 return 0;
a8eeb04a 951 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 952 return 1;
953}
954
9ba075a6
AK		 955static bool msr_mtrr_valid(unsigned msr)
956{
957 switch (msr) {
958 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
959 case MSR_MTRRfix64K_00000:
960 case MSR_MTRRfix16K_80000:
961 case MSR_MTRRfix16K_A0000:
962 case MSR_MTRRfix4K_C0000:
963 case MSR_MTRRfix4K_C8000:
964 case MSR_MTRRfix4K_D0000:
965 case MSR_MTRRfix4K_D8000:
966 case MSR_MTRRfix4K_E0000:
967 case MSR_MTRRfix4K_E8000:
968 case MSR_MTRRfix4K_F0000:
969 case MSR_MTRRfix4K_F8000:
970 case MSR_MTRRdefType:
971 case MSR_IA32_CR_PAT:
972 return true;
973 case 0x2f8:
974 return true;
975 }
976 return false;
977}
978
d6289b93
MT		 979static bool valid_pat_type(unsigned t)
980{
981 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
982}
983
984static bool valid_mtrr_type(unsigned t)
985{
986 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
987}
988
989static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
990{
991 int i;
992
993 if (!msr_mtrr_valid(msr))
994 return false;
995
996 if (msr == MSR_IA32_CR_PAT) {
997 for (i = 0; i < 8; i++)
998 if (!valid_pat_type((data >> (i * 8)) & 0xff))
999 return false;
1000 return true;
1001 } else if (msr == MSR_MTRRdefType) {
1002 if (data & ~0xcff)
1003 return false;
1004 return valid_mtrr_type(data & 0xff);
1005 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1006 for (i = 0; i < 8 ; i++)
1007 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1008 return false;
1009 return true;
1010 }
1011
1012 /* variable MTRRs */
1013 return valid_mtrr_type(data & 0xff);
1014}
1015
9ba075a6
AK		 1016static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1017{
0bed3b56
SY		 1018 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1019
d6289b93 1020 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1021 return 1;
1022
0bed3b56
SY		 1023 if (msr == MSR_MTRRdefType) {
1024 vcpu->arch.mtrr_state.def_type = data;
1025 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1026 } else if (msr == MSR_MTRRfix64K_00000)
1027 p[0] = data;
1028 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1029 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1030 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1031 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1032 else if (msr == MSR_IA32_CR_PAT)
1033 vcpu->arch.pat = data;
1034 else { /* Variable MTRRs */
1035 int idx, is_mtrr_mask;
1036 u64 *pt;
1037
1038 idx = (msr - 0x200) / 2;
1039 is_mtrr_mask = msr - 0x200 - 2 * idx;
1040 if (!is_mtrr_mask)
1041 pt =
1042 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1043 else
1044 pt =
1045 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1046 *pt = data;
1047 }
1048
1049 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1050 return 0;
1051}
15c4a640 1052
890ca9ae 1053static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1054{
890ca9ae
HY		 1055 u64 mcg_cap = vcpu->arch.mcg_cap;
1056 unsigned bank_num = mcg_cap & 0xff;
1057
15c4a640 1058 switch (msr) {
15c4a640 1059 case MSR_IA32_MCG_STATUS:
890ca9ae 1060 vcpu->arch.mcg_status = data;
15c4a640 1061 break;
c7ac679c 1062 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1063 if (!(mcg_cap & MCG_CTL_P))
1064 return 1;
1065 if (data != 0 && data != ~(u64)0)
1066 return -1;
1067 vcpu->arch.mcg_ctl = data;
1068 break;
1069 default:
1070 if (msr >= MSR_IA32_MC0_CTL &&
1071 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1072 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1073 /* only 0 or all 1s can be written to IA32_MCi_CTL
1074 * some Linux kernels though clear bit 10 in bank 4 to
1075 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1076 * this to avoid an uncatched #GP in the guest
1077 */
890ca9ae 1078 if ((offset & 0x3) == 0 &&
114be429 1079 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1080 return -1;
1081 vcpu->arch.mce_banks[offset] = data;
1082 break;
1083 }
1084 return 1;
1085 }
1086 return 0;
1087}
1088
ffde22ac
ES		 1089static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1090{
1091 struct kvm *kvm = vcpu->kvm;
1092 int lm = is_long_mode(vcpu);
1093 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1094 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1095 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1096 : kvm->arch.xen_hvm_config.blob_size_32;
1097 u32 page_num = data & ~PAGE_MASK;
1098 u64 page_addr = data & PAGE_MASK;
1099 u8 *page;
1100 int r;
1101
1102 r = -E2BIG;
1103 if (page_num >= blob_size)
1104 goto out;
1105 r = -ENOMEM;
1106 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1107 if (!page)
1108 goto out;
1109 r = -EFAULT;
1110 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1111 goto out_free;
1112 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1113 goto out_free;
1114 r = 0;
1115out_free:
1116 kfree(page);
1117out:
1118 return r;
1119}
1120
55cd8e5a
GN		 1121static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1122{
1123 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1124}
1125
1126static bool kvm_hv_msr_partition_wide(u32 msr)
1127{
1128 bool r = false;
1129 switch (msr) {
1130 case HV_X64_MSR_GUEST_OS_ID:
1131 case HV_X64_MSR_HYPERCALL:
1132 r = true;
1133 break;
1134 }
1135
1136 return r;
1137}
1138
1139static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1140{
1141 struct kvm *kvm = vcpu->kvm;
1142
1143 switch (msr) {
1144 case HV_X64_MSR_GUEST_OS_ID:
1145 kvm->arch.hv_guest_os_id = data;
1146 /* setting guest os id to zero disables hypercall page */
1147 if (!kvm->arch.hv_guest_os_id)
1148 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1149 break;
1150 case HV_X64_MSR_HYPERCALL: {
1151 u64 gfn;
1152 unsigned long addr;
1153 u8 instructions[4];
1154
1155 /* if guest os id is not set hypercall should remain disabled */
1156 if (!kvm->arch.hv_guest_os_id)
1157 break;
1158 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1159 kvm->arch.hv_hypercall = data;
1160 break;
1161 }
1162 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1163 addr = gfn_to_hva(kvm, gfn);
1164 if (kvm_is_error_hva(addr))
1165 return 1;
1166 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1167 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1168 if (copy_to_user((void __user *)addr, instructions, 4))
1169 return 1;
1170 kvm->arch.hv_hypercall = data;
1171 break;
1172 }
1173 default:
1174 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1175 "data 0x%llx\n", msr, data);
1176 return 1;
1177 }
1178 return 0;
1179}
1180
1181static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1182{
10388a07
GN		 1183 switch (msr) {
1184 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1185 unsigned long addr;
55cd8e5a 1186
10388a07
GN		 1187 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1188 vcpu->arch.hv_vapic = data;
1189 break;
1190 }
1191 addr = gfn_to_hva(vcpu->kvm, data >>
1192 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1193 if (kvm_is_error_hva(addr))
1194 return 1;
1195 if (clear_user((void __user *)addr, PAGE_SIZE))
1196 return 1;
1197 vcpu->arch.hv_vapic = data;
1198 break;
1199 }
1200 case HV_X64_MSR_EOI:
1201 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1202 case HV_X64_MSR_ICR:
1203 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1204 case HV_X64_MSR_TPR:
1205 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1206 default:
1207 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1208 "data 0x%llx\n", msr, data);
1209 return 1;
1210 }
1211
1212 return 0;
55cd8e5a
GN		 1213}
1214
15c4a640
CO		 1215int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1216{
1217 switch (msr) {
15c4a640 1218 case MSR_EFER:
b69e8cae 1219 return set_efer(vcpu, data);
8f1589d9
AP		 1220 case MSR_K7_HWCR:
1221 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1222 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1223 if (data != 0) {
1224 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1225 data);
1226 return 1;
1227 }
15c4a640 1228 break;
f7c6d140
AP		 1229 case MSR_FAM10H_MMIO_CONF_BASE:
1230 if (data != 0) {
1231 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1232 "0x%llx\n", data);
1233 return 1;
1234 }
15c4a640 1235 break;
c323c0e5 1236 case MSR_AMD64_NB_CFG:
c7ac679c 1237 break;
b5e2fec0
AG		 1238 case MSR_IA32_DEBUGCTLMSR:
1239 if (!data) {
1240 /* We support the non-activated case already */
1241 break;
1242 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1243 /* Values other than LBR and BTF are vendor-specific,
1244 thus reserved and should throw a #GP */
1245 return 1;
1246 }
1247 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1248 __func__, data);
1249 break;
15c4a640
CO		 1250 case MSR_IA32_UCODE_REV:
1251 case MSR_IA32_UCODE_WRITE:
61a6bd67 1252 case MSR_VM_HSAVE_PA:
6098ca93 1253 case MSR_AMD64_PATCH_LOADER:
15c4a640 1254 break;
9ba075a6
AK		 1255 case 0x200 ... 0x2ff:
1256 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1257 case MSR_IA32_APICBASE:
1258 kvm_set_apic_base(vcpu, data);
1259 break;
0105d1a5
GN		 1260 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1261 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1262 case MSR_IA32_MISC_ENABLE:
ad312c7c 1263 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1264 break;
11c6bffa 1265 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1266 case MSR_KVM_WALL_CLOCK:
1267 vcpu->kvm->arch.wall_clock = data;
1268 kvm_write_wall_clock(vcpu->kvm, data);
1269 break;
11c6bffa 1270 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1271 case MSR_KVM_SYSTEM_TIME: {
1272 if (vcpu->arch.time_page) {
1273 kvm_release_page_dirty(vcpu->arch.time_page);
1274 vcpu->arch.time_page = NULL;
1275 }
1276
1277 vcpu->arch.time = data;
1278
1279 /* we verify if the enable bit is set... */
1280 if (!(data & 1))
1281 break;
1282
1283 /* ...but clean it before doing the actual write */
1284 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1285
18068523
GOC		 1286 vcpu->arch.time_page =
1287 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1288
1289 if (is_error_page(vcpu->arch.time_page)) {
1290 kvm_release_page_clean(vcpu->arch.time_page);
1291 vcpu->arch.time_page = NULL;
1292 }
1293
c8076604 1294 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1295 break;
1296 }
890ca9ae
HY		 1297 case MSR_IA32_MCG_CTL:
1298 case MSR_IA32_MCG_STATUS:
1299 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1300 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1301
1302 /* Performance counters are not protected by a CPUID bit,
1303 * so we should check all of them in the generic path for the sake of
1304 * cross vendor migration.
1305 * Writing a zero into the event select MSRs disables them,
1306 * which we perfectly emulate ;-). Any other value should be at least
1307 * reported, some guests depend on them.
1308 */
1309 case MSR_P6_EVNTSEL0:
1310 case MSR_P6_EVNTSEL1:
1311 case MSR_K7_EVNTSEL0:
1312 case MSR_K7_EVNTSEL1:
1313 case MSR_K7_EVNTSEL2:
1314 case MSR_K7_EVNTSEL3:
1315 if (data != 0)
1316 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1317 "0x%x data 0x%llx\n", msr, data);
1318 break;
1319 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1320 * so we ignore writes to make it happy.
1321 */
1322 case MSR_P6_PERFCTR0:
1323 case MSR_P6_PERFCTR1:
1324 case MSR_K7_PERFCTR0:
1325 case MSR_K7_PERFCTR1:
1326 case MSR_K7_PERFCTR2:
1327 case MSR_K7_PERFCTR3:
1328 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1329 "0x%x data 0x%llx\n", msr, data);
1330 break;
55cd8e5a
GN		 1331 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1332 if (kvm_hv_msr_partition_wide(msr)) {
1333 int r;
1334 mutex_lock(&vcpu->kvm->lock);
1335 r = set_msr_hyperv_pw(vcpu, msr, data);
1336 mutex_unlock(&vcpu->kvm->lock);
1337 return r;
1338 } else
1339 return set_msr_hyperv(vcpu, msr, data);
1340 break;
15c4a640 1341 default:
ffde22ac
ES		 1342 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1343 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1344 if (!ignore_msrs) {
1345 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1346 msr, data);
1347 return 1;
1348 } else {
1349 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1350 msr, data);
1351 break;
1352 }
15c4a640
CO		 1353 }
1354 return 0;
1355}
1356EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1357
1358
1359/*
1360 * Reads an msr value (of 'msr_index') into 'pdata'.
1361 * Returns 0 on success, non-0 otherwise.
1362 * Assumes vcpu_load() was already called.
1363 */
1364int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1365{
1366 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1367}
1368
9ba075a6
AK		 1369static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1370{
0bed3b56
SY		 1371 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1372
9ba075a6
AK		 1373 if (!msr_mtrr_valid(msr))
1374 return 1;
1375
0bed3b56
SY		 1376 if (msr == MSR_MTRRdefType)
1377 *pdata = vcpu->arch.mtrr_state.def_type +
1378 (vcpu->arch.mtrr_state.enabled << 10);
1379 else if (msr == MSR_MTRRfix64K_00000)
1380 *pdata = p[0];
1381 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1382 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1383 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1384 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1385 else if (msr == MSR_IA32_CR_PAT)
1386 *pdata = vcpu->arch.pat;
1387 else { /* Variable MTRRs */
1388 int idx, is_mtrr_mask;
1389 u64 *pt;
1390
1391 idx = (msr - 0x200) / 2;
1392 is_mtrr_mask = msr - 0x200 - 2 * idx;
1393 if (!is_mtrr_mask)
1394 pt =
1395 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1396 else
1397 pt =
1398 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1399 *pdata = *pt;
1400 }
1401
9ba075a6
AK		 1402 return 0;
1403}
1404
890ca9ae 1405static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1406{
1407 u64 data;
890ca9ae
HY		 1408 u64 mcg_cap = vcpu->arch.mcg_cap;
1409 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1410
1411 switch (msr) {
15c4a640
CO		 1412 case MSR_IA32_P5_MC_ADDR:
1413 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1414 data = 0;
1415 break;
15c4a640 1416 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1417 data = vcpu->arch.mcg_cap;
1418 break;
c7ac679c 1419 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1420 if (!(mcg_cap & MCG_CTL_P))
1421 return 1;
1422 data = vcpu->arch.mcg_ctl;
1423 break;
1424 case MSR_IA32_MCG_STATUS:
1425 data = vcpu->arch.mcg_status;
1426 break;
1427 default:
1428 if (msr >= MSR_IA32_MC0_CTL &&
1429 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1430 u32 offset = msr - MSR_IA32_MC0_CTL;
1431 data = vcpu->arch.mce_banks[offset];
1432 break;
1433 }
1434 return 1;
1435 }
1436 *pdata = data;
1437 return 0;
1438}
1439
55cd8e5a
GN		 1440static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1441{
1442 u64 data = 0;
1443 struct kvm *kvm = vcpu->kvm;
1444
1445 switch (msr) {
1446 case HV_X64_MSR_GUEST_OS_ID:
1447 data = kvm->arch.hv_guest_os_id;
1448 break;
1449 case HV_X64_MSR_HYPERCALL:
1450 data = kvm->arch.hv_hypercall;
1451 break;
1452 default:
1453 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1454 return 1;
1455 }
1456
1457 *pdata = data;
1458 return 0;
1459}
1460
1461static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1462{
1463 u64 data = 0;
1464
1465 switch (msr) {
1466 case HV_X64_MSR_VP_INDEX: {
1467 int r;
1468 struct kvm_vcpu *v;
1469 kvm_for_each_vcpu(r, v, vcpu->kvm)
1470 if (v == vcpu)
1471 data = r;
1472 break;
1473 }
10388a07
GN		 1474 case HV_X64_MSR_EOI:
1475 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1476 case HV_X64_MSR_ICR:
1477 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1478 case HV_X64_MSR_TPR:
1479 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1480 default:
1481 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1482 return 1;
1483 }
1484 *pdata = data;
1485 return 0;
1486}
1487
890ca9ae
HY		 1488int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1489{
1490 u64 data;
1491
1492 switch (msr) {
890ca9ae 1493 case MSR_IA32_PLATFORM_ID:
15c4a640 1494 case MSR_IA32_UCODE_REV:
15c4a640 1495 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1496 case MSR_IA32_DEBUGCTLMSR:
1497 case MSR_IA32_LASTBRANCHFROMIP:
1498 case MSR_IA32_LASTBRANCHTOIP:
1499 case MSR_IA32_LASTINTFROMIP:
1500 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1501 case MSR_K8_SYSCFG:
1502 case MSR_K7_HWCR:
61a6bd67 1503 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1504 case MSR_P6_PERFCTR0:
1505 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1506 case MSR_P6_EVNTSEL0:
1507 case MSR_P6_EVNTSEL1:
9e699624 1508 case MSR_K7_EVNTSEL0:
1f3ee616 1509 case MSR_K7_PERFCTR0:
1fdbd48c 1510 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1511 case MSR_AMD64_NB_CFG:
f7c6d140 1512 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1513 data = 0;
1514 break;
9ba075a6
AK		 1515 case MSR_MTRRcap:
1516 data = 0x500 | KVM_NR_VAR_MTRR;
1517 break;
1518 case 0x200 ... 0x2ff:
1519 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1520 case 0xcd: /* fsb frequency */
1521 data = 3;
1522 break;
1523 case MSR_IA32_APICBASE:
1524 data = kvm_get_apic_base(vcpu);
1525 break;
0105d1a5
GN		 1526 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1527 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1528 break;
15c4a640 1529 case MSR_IA32_MISC_ENABLE:
ad312c7c 1530 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1531 break;
847f0ad8
AG		 1532 case MSR_IA32_PERF_STATUS:
1533 /* TSC increment by tick */
1534 data = 1000ULL;
1535 /* CPU multiplier */
1536 data |= (((uint64_t)4ULL) << 40);
1537 break;
15c4a640 1538 case MSR_EFER:
f6801dff 1539 data = vcpu->arch.efer;
15c4a640 1540 break;
18068523 1541 case MSR_KVM_WALL_CLOCK:
11c6bffa 1542 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1543 data = vcpu->kvm->arch.wall_clock;
1544 break;
1545 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1546 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1547 data = vcpu->arch.time;
1548 break;
890ca9ae
HY		 1549 case MSR_IA32_P5_MC_ADDR:
1550 case MSR_IA32_P5_MC_TYPE:
1551 case MSR_IA32_MCG_CAP:
1552 case MSR_IA32_MCG_CTL:
1553 case MSR_IA32_MCG_STATUS:
1554 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1555 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1556 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1557 if (kvm_hv_msr_partition_wide(msr)) {
1558 int r;
1559 mutex_lock(&vcpu->kvm->lock);
1560 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1561 mutex_unlock(&vcpu->kvm->lock);
1562 return r;
1563 } else
1564 return get_msr_hyperv(vcpu, msr, pdata);
1565 break;
15c4a640 1566 default:
ed85c068
AP		 1567 if (!ignore_msrs) {
1568 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1569 return 1;
1570 } else {
1571 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1572 data = 0;
1573 }
1574 break;
15c4a640
CO		 1575 }
1576 *pdata = data;
1577 return 0;
1578}
1579EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1580
313a3dc7
CO		 1581/*
1582 * Read or write a bunch of msrs. All parameters are kernel addresses.
1583 *
1584 * @return number of msrs set successfully.
1585 */
1586static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1587 struct kvm_msr_entry *entries,
1588 int (*do_msr)(struct kvm_vcpu *vcpu,
1589 unsigned index, u64 *data))
1590{
f656ce01 1591 int i, idx;
313a3dc7 1592
f656ce01 1593 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1594 for (i = 0; i < msrs->nmsrs; ++i)
1595 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1596 break;
f656ce01 1597 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1598
313a3dc7
CO		 1599 return i;
1600}
1601
1602/*
1603 * Read or write a bunch of msrs. Parameters are user addresses.
1604 *
1605 * @return number of msrs set successfully.
1606 */
1607static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1608 int (*do_msr)(struct kvm_vcpu *vcpu,
1609 unsigned index, u64 *data),
1610 int writeback)
1611{
1612 struct kvm_msrs msrs;
1613 struct kvm_msr_entry *entries;
1614 int r, n;
1615 unsigned size;
1616
1617 r = -EFAULT;
1618 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1619 goto out;
1620
1621 r = -E2BIG;
1622 if (msrs.nmsrs >= MAX_IO_MSRS)
1623 goto out;
1624
1625 r = -ENOMEM;
1626 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1627 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1628 if (!entries)
1629 goto out;
1630
1631 r = -EFAULT;
1632 if (copy_from_user(entries, user_msrs->entries, size))
1633 goto out_free;
1634
1635 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1636 if (r < 0)
1637 goto out_free;
1638
1639 r = -EFAULT;
1640 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1641 goto out_free;
1642
1643 r = n;
1644
1645out_free:
7a73c028 1646 kfree(entries);
313a3dc7
CO		 1647out:
1648 return r;
1649}
1650
018d00d2
ZX		 1651int kvm_dev_ioctl_check_extension(long ext)
1652{
1653 int r;
1654
1655 switch (ext) {
1656 case KVM_CAP_IRQCHIP:
1657 case KVM_CAP_HLT:
1658 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1659 case KVM_CAP_SET_TSS_ADDR:
07716717 1660 case KVM_CAP_EXT_CPUID:
c8076604 1661 case KVM_CAP_CLOCKSOURCE:
7837699f 1662 case KVM_CAP_PIT:
a28e4f5a 1663 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1664 case KVM_CAP_MP_STATE:
ed848624 1665 case KVM_CAP_SYNC_MMU:
52d939a0 1666 case KVM_CAP_REINJECT_CONTROL:
4925663a 1667 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1668 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1669 case KVM_CAP_IRQFD:
d34e6b17 1670 case KVM_CAP_IOEVENTFD:
c5ff41ce 1671 case KVM_CAP_PIT2:
e9f42757 1672 case KVM_CAP_PIT_STATE2:
b927a3ce 1673 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1674 case KVM_CAP_XEN_HVM:
afbcf7ab 1675 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1676 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1677 case KVM_CAP_HYPERV:
10388a07 1678 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1679 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1680 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1681 case KVM_CAP_DEBUGREGS:
d2be1651 1682 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1683 case KVM_CAP_XSAVE:
018d00d2
ZX		 1684 r = 1;
1685 break;
542472b5
LV		 1686 case KVM_CAP_COALESCED_MMIO:
1687 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1688 break;
774ead3a
AK		 1689 case KVM_CAP_VAPIC:
1690 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1691 break;
f725230a
AK		 1692 case KVM_CAP_NR_VCPUS:
1693 r = KVM_MAX_VCPUS;
1694 break;
a988b910
AK		 1695 case KVM_CAP_NR_MEMSLOTS:
1696 r = KVM_MEMORY_SLOTS;
1697 break;
a68a6a72
MT		 1698 case KVM_CAP_PV_MMU: /* obsolete */
1699 r = 0;
2f333bcb 1700 break;
62c476c7 1701 case KVM_CAP_IOMMU:
19de40a8 1702 r = iommu_found();
62c476c7 1703 break;
890ca9ae
HY		 1704 case KVM_CAP_MCE:
1705 r = KVM_MAX_MCE_BANKS;
1706 break;
2d5b5a66
SY		 1707 case KVM_CAP_XCRS:
1708 r = cpu_has_xsave;
1709 break;
018d00d2
ZX		 1710 default:
1711 r = 0;
1712 break;
1713 }
1714 return r;
1715
1716}
1717
043405e1
CO		 1718long kvm_arch_dev_ioctl(struct file *filp,
1719 unsigned int ioctl, unsigned long arg)
1720{
1721 void __user *argp = (void __user *)arg;
1722 long r;
1723
1724 switch (ioctl) {
1725 case KVM_GET_MSR_INDEX_LIST: {
1726 struct kvm_msr_list __user *user_msr_list = argp;
1727 struct kvm_msr_list msr_list;
1728 unsigned n;
1729
1730 r = -EFAULT;
1731 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1732 goto out;
1733 n = msr_list.nmsrs;
1734 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1735 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1736 goto out;
1737 r = -E2BIG;
e125e7b6 1738 if (n < msr_list.nmsrs)
043405e1
CO		 1739 goto out;
1740 r = -EFAULT;
1741 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1742 num_msrs_to_save * sizeof(u32)))
1743 goto out;
e125e7b6 1744 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1745 &emulated_msrs,
1746 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1747 goto out;
1748 r = 0;
1749 break;
1750 }
674eea0f
AK		 1751 case KVM_GET_SUPPORTED_CPUID: {
1752 struct kvm_cpuid2 __user *cpuid_arg = argp;
1753 struct kvm_cpuid2 cpuid;
1754
1755 r = -EFAULT;
1756 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1757 goto out;
1758 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1759 cpuid_arg->entries);
674eea0f
AK		 1760 if (r)
1761 goto out;
1762
1763 r = -EFAULT;
1764 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1765 goto out;
1766 r = 0;
1767 break;
1768 }
890ca9ae
HY		 1769 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1770 u64 mce_cap;
1771
1772 mce_cap = KVM_MCE_CAP_SUPPORTED;
1773 r = -EFAULT;
1774 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1775 goto out;
1776 r = 0;
1777 break;
1778 }
043405e1
CO		 1779 default:
1780 r = -EINVAL;
1781 }
1782out:
1783 return r;
1784}
1785
313a3dc7
CO		 1786void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1787{
1788 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1789 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1790 unsigned long khz = cpufreq_quick_get(cpu);
1791 if (!khz)
1792 khz = tsc_khz;
1793 per_cpu(cpu_tsc_khz, cpu) = khz;
1794 }
c8076604 1795 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1796}
1797
1798void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1799{
02daab21 1800 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1801 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1802}
1803
07716717 1804static int is_efer_nx(void)
313a3dc7 1805{
e286e86e 1806 unsigned long long efer = 0;
313a3dc7 1807
e286e86e 1808 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1809 return efer & EFER_NX;
1810}
1811
1812static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1813{
1814 int i;
1815 struct kvm_cpuid_entry2 *e, *entry;
1816
313a3dc7 1817 entry = NULL;
ad312c7c
ZX		 1818 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1819 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1820 if (e->function == 0x80000001) {
1821 entry = e;
1822 break;
1823 }
1824 }
07716717 1825 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1826 entry->edx &= ~(1 << 20);
1827 printk(KERN_INFO "kvm: guest NX capability removed\n");
1828 }
1829}
1830
07716717 1831/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1832static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1833 struct kvm_cpuid *cpuid,
1834 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1835{
1836 int r, i;
1837 struct kvm_cpuid_entry *cpuid_entries;
1838
1839 r = -E2BIG;
1840 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1841 goto out;
1842 r = -ENOMEM;
1843 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1844 if (!cpuid_entries)
1845 goto out;
1846 r = -EFAULT;
1847 if (copy_from_user(cpuid_entries, entries,
1848 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1849 goto out_free;
1850 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1851 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1852 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1853 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1854 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1855 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1856 vcpu->arch.cpuid_entries[i].index = 0;
1857 vcpu->arch.cpuid_entries[i].flags = 0;
1858 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1859 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1860 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1861 }
1862 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1863 cpuid_fix_nx_cap(vcpu);
1864 r = 0;
fc61b800 1865 kvm_apic_set_version(vcpu);
0e851880 1866 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 1867 update_cpuid(vcpu);
07716717
DK		 1868
1869out_free:
1870 vfree(cpuid_entries);
1871out:
1872 return r;
1873}
1874
1875static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1876 struct kvm_cpuid2 *cpuid,
1877 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1878{
1879 int r;
1880
1881 r = -E2BIG;
1882 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1883 goto out;
1884 r = -EFAULT;
ad312c7c 1885 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1886 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1887 goto out;
ad312c7c 1888 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1889 kvm_apic_set_version(vcpu);
0e851880 1890 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 1891 update_cpuid(vcpu);
313a3dc7
CO		 1892 return 0;
1893
1894out:
1895 return r;
1896}
1897
07716717 1898static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1899 struct kvm_cpuid2 *cpuid,
1900 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1901{
1902 int r;
1903
1904 r = -E2BIG;
ad312c7c 1905 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1906 goto out;
1907 r = -EFAULT;
ad312c7c 1908 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1909 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1910 goto out;
1911 return 0;
1912
1913out:
ad312c7c 1914 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1915 return r;
1916}
1917
07716717 1918static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1919 u32 index)
07716717
DK		 1920{
1921 entry->function = function;
1922 entry->index = index;
1923 cpuid_count(entry->function, entry->index,
19355475 1924 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1925 entry->flags = 0;
1926}
1927
7faa4ee1
AK		 1928#define F(x) bit(X86_FEATURE_##x)
1929
07716717
DK		 1930static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1931 u32 index, int *nent, int maxnent)
1932{
7faa4ee1 1933 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1934#ifdef CONFIG_X86_64
17cc3935
SY		 1935 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1936 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1937 unsigned f_lm = F(LM);
1938#else
17cc3935 1939 unsigned f_gbpages = 0;
7faa4ee1 1940 unsigned f_lm = 0;
07716717 1941#endif
4e47c7a6 1942 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1943
1944 /* cpuid 1.edx */
1945 const u32 kvm_supported_word0_x86_features =
1946 F(FPU) | F(VME) | F(DE) | F(PSE) |
1947 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1948 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1949 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1950 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1951 0 /* Reserved, DS, ACPI */ | F(MMX) |
1952 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1953 0 /* HTT, TM, Reserved, PBE */;
1954 /* cpuid 0x80000001.edx */
1955 const u32 kvm_supported_word1_x86_features =
1956 F(FPU) | F(VME) | F(DE) | F(PSE) |
1957 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1958 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1959 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1960 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1961 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1962 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1963 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1964 /* cpuid 1.ecx */
1965 const u32 kvm_supported_word4_x86_features =
6c3f6041 1966 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 1967 0 /* DS-CPL, VMX, SMX, EST */ |
1968 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1969 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1970 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1971 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 1972 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 1973 /* cpuid 0x80000001.ecx */
07716717 1974 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1975 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1976 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1977 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1978 0 /* SKINIT */ | 0 /* WDT */;
07716717 1979
19355475 1980 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1981 get_cpu();
1982 do_cpuid_1_ent(entry, function, index);
1983 ++*nent;
1984
1985 switch (function) {
1986 case 0:
2acf923e 1987 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 1988 break;
1989 case 1:
1990 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1991 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1992 /* we support x2apic emulation even if host does not support
1993 * it since we emulate x2apic in software */
1994 entry->ecx |= F(X2APIC);
07716717
DK		 1995 break;
1996 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1997 * may return different values. This forces us to get_cpu() before
1998 * issuing the first command, and also to emulate this annoying behavior
1999 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2000 case 2: {
2001 int t, times = entry->eax & 0xff;
2002
2003 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2004 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2005 for (t = 1; t < times && *nent < maxnent; ++t) {
2006 do_cpuid_1_ent(&entry[t], function, 0);
2007 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2008 ++*nent;
2009 }
2010 break;
2011 }
2012 /* function 4 and 0xb have additional index. */
2013 case 4: {
14af3f3c 2014 int i, cache_type;
07716717
DK		 2015
2016 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2017 /* read more entries until cache_type is zero */
14af3f3c
HH		 2018 for (i = 1; *nent < maxnent; ++i) {
2019 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2020 if (!cache_type)
2021 break;
14af3f3c
HH		 2022 do_cpuid_1_ent(&entry[i], function, i);
2023 entry[i].flags |=
07716717
DK		 2024 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2025 ++*nent;
2026 }
2027 break;
2028 }
2029 case 0xb: {
14af3f3c 2030 int i, level_type;
07716717
DK		 2031
2032 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2033 /* read more entries until level_type is zero */
14af3f3c 2034 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2035 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2036 if (!level_type)
2037 break;
14af3f3c
HH		 2038 do_cpuid_1_ent(&entry[i], function, i);
2039 entry[i].flags |=
07716717
DK		 2040 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2041 ++*nent;
2042 }
2043 break;
2044 }
2acf923e
DC		 2045 case 0xd: {
2046 int i;
2047
2048 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2049 for (i = 1; *nent < maxnent; ++i) {
2050 if (entry[i - 1].eax == 0 && i != 2)
2051 break;
2052 do_cpuid_1_ent(&entry[i], function, i);
2053 entry[i].flags |=
2054 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2055 ++*nent;
2056 }
2057 break;
2058 }
84478c82
GC		 2059 case KVM_CPUID_SIGNATURE: {
2060 char signature[12] = "KVMKVMKVM\0\0";
2061 u32 *sigptr = (u32 *)signature;
2062 entry->eax = 0;
2063 entry->ebx = sigptr[0];
2064 entry->ecx = sigptr[1];
2065 entry->edx = sigptr[2];
2066 break;
2067 }
2068 case KVM_CPUID_FEATURES:
2069 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2070 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2071 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2072 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2073 entry->ebx = 0;
2074 entry->ecx = 0;
2075 entry->edx = 0;
2076 break;
07716717
DK		 2077 case 0x80000000:
2078 entry->eax = min(entry->eax, 0x8000001a);
2079 break;
2080 case 0x80000001:
2081 entry->edx &= kvm_supported_word1_x86_features;
2082 entry->ecx &= kvm_supported_word6_x86_features;
2083 break;
2084 }
d4330ef2
JR		 2085
2086 kvm_x86_ops->set_supported_cpuid(function, entry);
2087
07716717
DK		 2088 put_cpu();
2089}
2090
7faa4ee1
AK		 2091#undef F
2092
674eea0f 2093static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2094 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2095{
2096 struct kvm_cpuid_entry2 *cpuid_entries;
2097 int limit, nent = 0, r = -E2BIG;
2098 u32 func;
2099
2100 if (cpuid->nent < 1)
2101 goto out;
6a544355
AK		 2102 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2103 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2104 r = -ENOMEM;
2105 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2106 if (!cpuid_entries)
2107 goto out;
2108
2109 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2110 limit = cpuid_entries[0].eax;
2111 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2112 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2113 &nent, cpuid->nent);
07716717
DK		 2114 r = -E2BIG;
2115 if (nent >= cpuid->nent)
2116 goto out_free;
2117
2118 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2119 limit = cpuid_entries[nent - 1].eax;
2120 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2121 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2122 &nent, cpuid->nent);
84478c82
GC		 2123
2124
2125
2126 r = -E2BIG;
2127 if (nent >= cpuid->nent)
2128 goto out_free;
2129
2130 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2131 cpuid->nent);
2132
2133 r = -E2BIG;
2134 if (nent >= cpuid->nent)
2135 goto out_free;
2136
2137 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2138 cpuid->nent);
2139
cb007648
MM		 2140 r = -E2BIG;
2141 if (nent >= cpuid->nent)
2142 goto out_free;
2143
07716717
DK		 2144 r = -EFAULT;
2145 if (copy_to_user(entries, cpuid_entries,
19355475 2146 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2147 goto out_free;
2148 cpuid->nent = nent;
2149 r = 0;
2150
2151out_free:
2152 vfree(cpuid_entries);
2153out:
2154 return r;
2155}
2156
313a3dc7
CO		 2157static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2158 struct kvm_lapic_state *s)
2159{
ad312c7c 2160 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2161
2162 return 0;
2163}
2164
2165static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2166 struct kvm_lapic_state *s)
2167{
ad312c7c 2168 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2169 kvm_apic_post_state_restore(vcpu);
cb142eb7 2170 update_cr8_intercept(vcpu);
313a3dc7
CO		 2171
2172 return 0;
2173}
2174
f77bc6a4
ZX		 2175static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2176 struct kvm_interrupt *irq)
2177{
2178 if (irq->irq < 0 || irq->irq >= 256)
2179 return -EINVAL;
2180 if (irqchip_in_kernel(vcpu->kvm))
2181 return -ENXIO;
f77bc6a4 2182
66fd3f7f 2183 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2184
f77bc6a4
ZX		 2185 return 0;
2186}
2187
c4abb7c9
JK		 2188static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2189{
c4abb7c9 2190 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2191
2192 return 0;
2193}
2194
b209749f
AK		 2195static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2196 struct kvm_tpr_access_ctl *tac)
2197{
2198 if (tac->flags)
2199 return -EINVAL;
2200 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2201 return 0;
2202}
2203
890ca9ae
HY		 2204static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2205 u64 mcg_cap)
2206{
2207 int r;
2208 unsigned bank_num = mcg_cap & 0xff, bank;
2209
2210 r = -EINVAL;
a9e38c3e 2211 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2212 goto out;
2213 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2214 goto out;
2215 r = 0;
2216 vcpu->arch.mcg_cap = mcg_cap;
2217 /* Init IA32_MCG_CTL to all 1s */
2218 if (mcg_cap & MCG_CTL_P)
2219 vcpu->arch.mcg_ctl = ~(u64)0;
2220 /* Init IA32_MCi_CTL to all 1s */
2221 for (bank = 0; bank < bank_num; bank++)
2222 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2223out:
2224 return r;
2225}
2226
2227static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2228 struct kvm_x86_mce *mce)
2229{
2230 u64 mcg_cap = vcpu->arch.mcg_cap;
2231 unsigned bank_num = mcg_cap & 0xff;
2232 u64 *banks = vcpu->arch.mce_banks;
2233
2234 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2235 return -EINVAL;
2236 /*
2237 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2238 * reporting is disabled
2239 */
2240 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2241 vcpu->arch.mcg_ctl != ~(u64)0)
2242 return 0;
2243 banks += 4 * mce->bank;
2244 /*
2245 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2246 * reporting is disabled for the bank
2247 */
2248 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2249 return 0;
2250 if (mce->status & MCI_STATUS_UC) {
2251 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2252 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2253 printk(KERN_DEBUG "kvm: set_mce: "
2254 "injects mce exception while "
2255 "previous one is in progress!\n");
a8eeb04a 2256 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2257 return 0;
2258 }
2259 if (banks[1] & MCI_STATUS_VAL)
2260 mce->status |= MCI_STATUS_OVER;
2261 banks[2] = mce->addr;
2262 banks[3] = mce->misc;
2263 vcpu->arch.mcg_status = mce->mcg_status;
2264 banks[1] = mce->status;
2265 kvm_queue_exception(vcpu, MC_VECTOR);
2266 } else if (!(banks[1] & MCI_STATUS_VAL)
2267 || !(banks[1] & MCI_STATUS_UC)) {
2268 if (banks[1] & MCI_STATUS_VAL)
2269 mce->status |= MCI_STATUS_OVER;
2270 banks[2] = mce->addr;
2271 banks[3] = mce->misc;
2272 banks[1] = mce->status;
2273 } else
2274 banks[1] |= MCI_STATUS_OVER;
2275 return 0;
2276}
2277
3cfc3092
JK		 2278static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2279 struct kvm_vcpu_events *events)
2280{
03b82a30
JK		 2281 events->exception.injected =
2282 vcpu->arch.exception.pending &&
2283 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2284 events->exception.nr = vcpu->arch.exception.nr;
2285 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2286 events->exception.error_code = vcpu->arch.exception.error_code;
2287
03b82a30
JK		 2288 events->interrupt.injected =
2289 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2290 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2291 events->interrupt.soft = 0;
48005f64
JK		 2292 events->interrupt.shadow =
2293 kvm_x86_ops->get_interrupt_shadow(vcpu,
2294 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2295
2296 events->nmi.injected = vcpu->arch.nmi_injected;
2297 events->nmi.pending = vcpu->arch.nmi_pending;
2298 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2299
2300 events->sipi_vector = vcpu->arch.sipi_vector;
2301
dab4b911 2302 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2303 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2304 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2305}
2306
2307static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2308 struct kvm_vcpu_events *events)
2309{
dab4b911 2310 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2311 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2312 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2313 return -EINVAL;
2314
3cfc3092
JK		 2315 vcpu->arch.exception.pending = events->exception.injected;
2316 vcpu->arch.exception.nr = events->exception.nr;
2317 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2318 vcpu->arch.exception.error_code = events->exception.error_code;
2319
2320 vcpu->arch.interrupt.pending = events->interrupt.injected;
2321 vcpu->arch.interrupt.nr = events->interrupt.nr;
2322 vcpu->arch.interrupt.soft = events->interrupt.soft;
2323 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2324 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2325 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2326 kvm_x86_ops->set_interrupt_shadow(vcpu,
2327 events->interrupt.shadow);
3cfc3092
JK		 2328
2329 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2330 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2331 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2332 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2333
dab4b911
JK		 2334 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2335 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2336
3cfc3092
JK		 2337 return 0;
2338}
2339
a1efbe77
JK		 2340static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2341 struct kvm_debugregs *dbgregs)
2342{
a1efbe77
JK		 2343 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2344 dbgregs->dr6 = vcpu->arch.dr6;
2345 dbgregs->dr7 = vcpu->arch.dr7;
2346 dbgregs->flags = 0;
a1efbe77
JK		 2347}
2348
2349static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2350 struct kvm_debugregs *dbgregs)
2351{
2352 if (dbgregs->flags)
2353 return -EINVAL;
2354
a1efbe77
JK		 2355 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2356 vcpu->arch.dr6 = dbgregs->dr6;
2357 vcpu->arch.dr7 = dbgregs->dr7;
2358
a1efbe77
JK		 2359 return 0;
2360}
2361
2d5b5a66
SY		 2362static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2363 struct kvm_xsave *guest_xsave)
2364{
2365 if (cpu_has_xsave)
2366 memcpy(guest_xsave->region,
2367 &vcpu->arch.guest_fpu.state->xsave,
2368 sizeof(struct xsave_struct));
2369 else {
2370 memcpy(guest_xsave->region,
2371 &vcpu->arch.guest_fpu.state->fxsave,
2372 sizeof(struct i387_fxsave_struct));
2373 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2374 XSTATE_FPSSE;
2375 }
2376}
2377
2378static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2379 struct kvm_xsave *guest_xsave)
2380{
2381 u64 xstate_bv =
2382 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2383
2384 if (cpu_has_xsave)
2385 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2386 guest_xsave->region, sizeof(struct xsave_struct));
2387 else {
2388 if (xstate_bv & ~XSTATE_FPSSE)
2389 return -EINVAL;
2390 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2391 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2392 }
2393 return 0;
2394}
2395
2396static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2397 struct kvm_xcrs *guest_xcrs)
2398{
2399 if (!cpu_has_xsave) {
2400 guest_xcrs->nr_xcrs = 0;
2401 return;
2402 }
2403
2404 guest_xcrs->nr_xcrs = 1;
2405 guest_xcrs->flags = 0;
2406 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2407 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2408}
2409
2410static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2411 struct kvm_xcrs *guest_xcrs)
2412{
2413 int i, r = 0;
2414
2415 if (!cpu_has_xsave)
2416 return -EINVAL;
2417
2418 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2419 return -EINVAL;
2420
2421 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2422 /* Only support XCR0 currently */
2423 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2424 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2425 guest_xcrs->xcrs[0].value);
2426 break;
2427 }
2428 if (r)
2429 r = -EINVAL;
2430 return r;
2431}
2432
313a3dc7
CO		 2433long kvm_arch_vcpu_ioctl(struct file *filp,
2434 unsigned int ioctl, unsigned long arg)
2435{
2436 struct kvm_vcpu *vcpu = filp->private_data;
2437 void __user *argp = (void __user *)arg;
2438 int r;
d1ac91d8
AK		 2439 union {
2440 struct kvm_lapic_state *lapic;
2441 struct kvm_xsave *xsave;
2442 struct kvm_xcrs *xcrs;
2443 void *buffer;
2444 } u;
2445
2446 u.buffer = NULL;
313a3dc7
CO		 2447 switch (ioctl) {
2448 case KVM_GET_LAPIC: {
2204ae3c
MT		 2449 r = -EINVAL;
2450 if (!vcpu->arch.apic)
2451 goto out;
d1ac91d8 2452 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2453
b772ff36 2454 r = -ENOMEM;
d1ac91d8 2455 if (!u.lapic)
b772ff36 2456 goto out;
d1ac91d8 2457 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2458 if (r)
2459 goto out;
2460 r = -EFAULT;
d1ac91d8 2461 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2462 goto out;
2463 r = 0;
2464 break;
2465 }
2466 case KVM_SET_LAPIC: {
2204ae3c
MT		 2467 r = -EINVAL;
2468 if (!vcpu->arch.apic)
2469 goto out;
d1ac91d8 2470 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2471 r = -ENOMEM;
d1ac91d8 2472 if (!u.lapic)
b772ff36 2473 goto out;
313a3dc7 2474 r = -EFAULT;
d1ac91d8 2475 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2476 goto out;
d1ac91d8 2477 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2478 if (r)
2479 goto out;
2480 r = 0;
2481 break;
2482 }
f77bc6a4
ZX		 2483 case KVM_INTERRUPT: {
2484 struct kvm_interrupt irq;
2485
2486 r = -EFAULT;
2487 if (copy_from_user(&irq, argp, sizeof irq))
2488 goto out;
2489 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2490 if (r)
2491 goto out;
2492 r = 0;
2493 break;
2494 }
c4abb7c9
JK		 2495 case KVM_NMI: {
2496 r = kvm_vcpu_ioctl_nmi(vcpu);
2497 if (r)
2498 goto out;
2499 r = 0;
2500 break;
2501 }
313a3dc7
CO		 2502 case KVM_SET_CPUID: {
2503 struct kvm_cpuid __user *cpuid_arg = argp;
2504 struct kvm_cpuid cpuid;
2505
2506 r = -EFAULT;
2507 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2508 goto out;
2509 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2510 if (r)
2511 goto out;
2512 break;
2513 }
07716717
DK		 2514 case KVM_SET_CPUID2: {
2515 struct kvm_cpuid2 __user *cpuid_arg = argp;
2516 struct kvm_cpuid2 cpuid;
2517
2518 r = -EFAULT;
2519 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2520 goto out;
2521 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2522 cpuid_arg->entries);
07716717
DK		 2523 if (r)
2524 goto out;
2525 break;
2526 }
2527 case KVM_GET_CPUID2: {
2528 struct kvm_cpuid2 __user *cpuid_arg = argp;
2529 struct kvm_cpuid2 cpuid;
2530
2531 r = -EFAULT;
2532 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2533 goto out;
2534 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2535 cpuid_arg->entries);
07716717
DK		 2536 if (r)
2537 goto out;
2538 r = -EFAULT;
2539 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2540 goto out;
2541 r = 0;
2542 break;
2543 }
313a3dc7
CO		 2544 case KVM_GET_MSRS:
2545 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2546 break;
2547 case KVM_SET_MSRS:
2548 r = msr_io(vcpu, argp, do_set_msr, 0);
2549 break;
b209749f
AK		 2550 case KVM_TPR_ACCESS_REPORTING: {
2551 struct kvm_tpr_access_ctl tac;
2552
2553 r = -EFAULT;
2554 if (copy_from_user(&tac, argp, sizeof tac))
2555 goto out;
2556 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2557 if (r)
2558 goto out;
2559 r = -EFAULT;
2560 if (copy_to_user(argp, &tac, sizeof tac))
2561 goto out;
2562 r = 0;
2563 break;
2564 };
b93463aa
AK		 2565 case KVM_SET_VAPIC_ADDR: {
2566 struct kvm_vapic_addr va;
2567
2568 r = -EINVAL;
2569 if (!irqchip_in_kernel(vcpu->kvm))
2570 goto out;
2571 r = -EFAULT;
2572 if (copy_from_user(&va, argp, sizeof va))
2573 goto out;
2574 r = 0;
2575 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2576 break;
2577 }
890ca9ae
HY		 2578 case KVM_X86_SETUP_MCE: {
2579 u64 mcg_cap;
2580
2581 r = -EFAULT;
2582 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2583 goto out;
2584 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2585 break;
2586 }
2587 case KVM_X86_SET_MCE: {
2588 struct kvm_x86_mce mce;
2589
2590 r = -EFAULT;
2591 if (copy_from_user(&mce, argp, sizeof mce))
2592 goto out;
2593 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2594 break;
2595 }
3cfc3092
JK		 2596 case KVM_GET_VCPU_EVENTS: {
2597 struct kvm_vcpu_events events;
2598
2599 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2600
2601 r = -EFAULT;
2602 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2603 break;
2604 r = 0;
2605 break;
2606 }
2607 case KVM_SET_VCPU_EVENTS: {
2608 struct kvm_vcpu_events events;
2609
2610 r = -EFAULT;
2611 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2612 break;
2613
2614 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2615 break;
2616 }
a1efbe77
JK		 2617 case KVM_GET_DEBUGREGS: {
2618 struct kvm_debugregs dbgregs;
2619
2620 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2621
2622 r = -EFAULT;
2623 if (copy_to_user(argp, &dbgregs,
2624 sizeof(struct kvm_debugregs)))
2625 break;
2626 r = 0;
2627 break;
2628 }
2629 case KVM_SET_DEBUGREGS: {
2630 struct kvm_debugregs dbgregs;
2631
2632 r = -EFAULT;
2633 if (copy_from_user(&dbgregs, argp,
2634 sizeof(struct kvm_debugregs)))
2635 break;
2636
2637 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2638 break;
2639 }
2d5b5a66 2640 case KVM_GET_XSAVE: {
d1ac91d8 2641 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2642 r = -ENOMEM;
d1ac91d8 2643 if (!u.xsave)
2d5b5a66
SY		 2644 break;
2645
d1ac91d8 2646 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2647
2648 r = -EFAULT;
d1ac91d8 2649 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2650 break;
2651 r = 0;
2652 break;
2653 }
2654 case KVM_SET_XSAVE: {
d1ac91d8 2655 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2656 r = -ENOMEM;
d1ac91d8 2657 if (!u.xsave)
2d5b5a66
SY		 2658 break;
2659
2660 r = -EFAULT;
d1ac91d8 2661 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2662 break;
2663
d1ac91d8 2664 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2665 break;
2666 }
2667 case KVM_GET_XCRS: {
d1ac91d8 2668 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2669 r = -ENOMEM;
d1ac91d8 2670 if (!u.xcrs)
2d5b5a66
SY		 2671 break;
2672
d1ac91d8 2673 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2674
2675 r = -EFAULT;
d1ac91d8 2676 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2677 sizeof(struct kvm_xcrs)))
2678 break;
2679 r = 0;
2680 break;
2681 }
2682 case KVM_SET_XCRS: {
d1ac91d8 2683 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2684 r = -ENOMEM;
d1ac91d8 2685 if (!u.xcrs)
2d5b5a66
SY		 2686 break;
2687
2688 r = -EFAULT;
d1ac91d8 2689 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2690 sizeof(struct kvm_xcrs)))
2691 break;
2692
d1ac91d8 2693 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2694 break;
2695 }
313a3dc7
CO		 2696 default:
2697 r = -EINVAL;
2698 }
2699out:
d1ac91d8 2700 kfree(u.buffer);
313a3dc7
CO		 2701 return r;
2702}
2703
1fe779f8
CO		 2704static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2705{
2706 int ret;
2707
2708 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2709 return -1;
2710 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2711 return ret;
2712}
2713
b927a3ce
SY		 2714static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2715 u64 ident_addr)
2716{
2717 kvm->arch.ept_identity_map_addr = ident_addr;
2718 return 0;
2719}
2720
1fe779f8
CO		 2721static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2722 u32 kvm_nr_mmu_pages)
2723{
2724 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2725 return -EINVAL;
2726
79fac95e 2727 mutex_lock(&kvm->slots_lock);
7c8a83b7 2728 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2729
2730 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2731 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2732
7c8a83b7 2733 spin_unlock(&kvm->mmu_lock);
79fac95e 2734 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2735 return 0;
2736}
2737
2738static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2739{
f05e70ac 2740 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2741}
2742
1fe779f8
CO		 2743static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2744{
2745 int r;
2746
2747 r = 0;
2748 switch (chip->chip_id) {
2749 case KVM_IRQCHIP_PIC_MASTER:
2750 memcpy(&chip->chip.pic,
2751 &pic_irqchip(kvm)->pics[0],
2752 sizeof(struct kvm_pic_state));
2753 break;
2754 case KVM_IRQCHIP_PIC_SLAVE:
2755 memcpy(&chip->chip.pic,
2756 &pic_irqchip(kvm)->pics[1],
2757 sizeof(struct kvm_pic_state));
2758 break;
2759 case KVM_IRQCHIP_IOAPIC:
eba0226b 2760 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2761 break;
2762 default:
2763 r = -EINVAL;
2764 break;
2765 }
2766 return r;
2767}
2768
2769static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2770{
2771 int r;
2772
2773 r = 0;
2774 switch (chip->chip_id) {
2775 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2776 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2777 memcpy(&pic_irqchip(kvm)->pics[0],
2778 &chip->chip.pic,
2779 sizeof(struct kvm_pic_state));
fa8273e9 2780 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2781 break;
2782 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2783 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2784 memcpy(&pic_irqchip(kvm)->pics[1],
2785 &chip->chip.pic,
2786 sizeof(struct kvm_pic_state));
fa8273e9 2787 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2788 break;
2789 case KVM_IRQCHIP_IOAPIC:
eba0226b 2790 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2791 break;
2792 default:
2793 r = -EINVAL;
2794 break;
2795 }
2796 kvm_pic_update_irq(pic_irqchip(kvm));
2797 return r;
2798}
2799
e0f63cb9
SY		 2800static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2801{
2802 int r = 0;
2803
894a9c55 2804 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2805 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2806 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2807 return r;
2808}
2809
2810static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2811{
2812 int r = 0;
2813
894a9c55 2814 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2815 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2816 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2817 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2818 return r;
2819}
2820
2821static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2822{
2823 int r = 0;
2824
2825 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2826 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2827 sizeof(ps->channels));
2828 ps->flags = kvm->arch.vpit->pit_state.flags;
2829 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2830 return r;
2831}
2832
2833static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2834{
2835 int r = 0, start = 0;
2836 u32 prev_legacy, cur_legacy;
2837 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2838 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2839 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2840 if (!prev_legacy && cur_legacy)
2841 start = 1;
2842 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2843 sizeof(kvm->arch.vpit->pit_state.channels));
2844 kvm->arch.vpit->pit_state.flags = ps->flags;
2845 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2846 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2847 return r;
2848}
2849
52d939a0
MT		 2850static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2851 struct kvm_reinject_control *control)
2852{
2853 if (!kvm->arch.vpit)
2854 return -ENXIO;
894a9c55 2855 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2856 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2857 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2858 return 0;
2859}
2860
5bb064dc
ZX		 2861/*
2862 * Get (and clear) the dirty memory log for a memory slot.
2863 */
2864int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2865 struct kvm_dirty_log *log)
2866{
87bf6e7d 2867 int r, i;
5bb064dc 2868 struct kvm_memory_slot *memslot;
87bf6e7d 2869 unsigned long n;
b050b015 2870 unsigned long is_dirty = 0;
5bb064dc 2871
79fac95e 2872 mutex_lock(&kvm->slots_lock);
5bb064dc 2873
b050b015
MT		 2874 r = -EINVAL;
2875 if (log->slot >= KVM_MEMORY_SLOTS)
2876 goto out;
2877
2878 memslot = &kvm->memslots->memslots[log->slot];
2879 r = -ENOENT;
2880 if (!memslot->dirty_bitmap)
2881 goto out;
2882
87bf6e7d 2883 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 2884
b050b015
MT		 2885 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2886 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2887
2888 /* If nothing is dirty, don't bother messing with page tables. */
2889 if (is_dirty) {
b050b015 2890 struct kvm_memslots *slots, *old_slots;
914ebccd 2891 unsigned long *dirty_bitmap;
b050b015 2892
7c8a83b7 2893 spin_lock(&kvm->mmu_lock);
5bb064dc 2894 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2895 spin_unlock(&kvm->mmu_lock);
b050b015 2896
914ebccd
TY		 2897 r = -ENOMEM;
2898 dirty_bitmap = vmalloc(n);
2899 if (!dirty_bitmap)
2900 goto out;
2901 memset(dirty_bitmap, 0, n);
b050b015 2902
914ebccd
TY		 2903 r = -ENOMEM;
2904 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2905 if (!slots) {
2906 vfree(dirty_bitmap);
2907 goto out;
2908 }
b050b015
MT		 2909 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2910 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2911
2912 old_slots = kvm->memslots;
2913 rcu_assign_pointer(kvm->memslots, slots);
2914 synchronize_srcu_expedited(&kvm->srcu);
2915 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2916 kfree(old_slots);
914ebccd
TY		 2917
2918 r = -EFAULT;
2919 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
2920 vfree(dirty_bitmap);
2921 goto out;
2922 }
2923 vfree(dirty_bitmap);
2924 } else {
2925 r = -EFAULT;
2926 if (clear_user(log->dirty_bitmap, n))
2927 goto out;
5bb064dc 2928 }
b050b015 2929
5bb064dc
ZX		 2930 r = 0;
2931out:
79fac95e 2932 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2933 return r;
2934}
2935
1fe779f8
CO		 2936long kvm_arch_vm_ioctl(struct file *filp,
2937 unsigned int ioctl, unsigned long arg)
2938{
2939 struct kvm *kvm = filp->private_data;
2940 void __user *argp = (void __user *)arg;
367e1319 2941 int r = -ENOTTY;
f0d66275
DH		 2942 /*
2943 * This union makes it completely explicit to gcc-3.x
2944 * that these two variables' stack usage should be
2945 * combined, not added together.
2946 */
2947 union {
2948 struct kvm_pit_state ps;
e9f42757 2949 struct kvm_pit_state2 ps2;
c5ff41ce 2950 struct kvm_pit_config pit_config;
f0d66275 2951 } u;
1fe779f8
CO		 2952
2953 switch (ioctl) {
2954 case KVM_SET_TSS_ADDR:
2955 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2956 if (r < 0)
2957 goto out;
2958 break;
b927a3ce
SY		 2959 case KVM_SET_IDENTITY_MAP_ADDR: {
2960 u64 ident_addr;
2961
2962 r = -EFAULT;
2963 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2964 goto out;
2965 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2966 if (r < 0)
2967 goto out;
2968 break;
2969 }
1fe779f8
CO		 2970 case KVM_SET_NR_MMU_PAGES:
2971 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2972 if (r)
2973 goto out;
2974 break;
2975 case KVM_GET_NR_MMU_PAGES:
2976 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2977 break;
3ddea128
MT		 2978 case KVM_CREATE_IRQCHIP: {
2979 struct kvm_pic *vpic;
2980
2981 mutex_lock(&kvm->lock);
2982 r = -EEXIST;
2983 if (kvm->arch.vpic)
2984 goto create_irqchip_unlock;
1fe779f8 2985 r = -ENOMEM;
3ddea128
MT		 2986 vpic = kvm_create_pic(kvm);
2987 if (vpic) {
1fe779f8
CO		 2988 r = kvm_ioapic_init(kvm);
2989 if (r) {
72bb2fcd
WY		 2990 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2991 &vpic->dev);
3ddea128
MT		 2992 kfree(vpic);
2993 goto create_irqchip_unlock;
1fe779f8
CO		 2994 }
2995 } else
3ddea128
MT		 2996 goto create_irqchip_unlock;
2997 smp_wmb();
2998 kvm->arch.vpic = vpic;
2999 smp_wmb();
399ec807
AK		 3000 r = kvm_setup_default_irq_routing(kvm);
3001 if (r) {
3ddea128 3002 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3003 kvm_ioapic_destroy(kvm);
3004 kvm_destroy_pic(kvm);
3ddea128 3005 mutex_unlock(&kvm->irq_lock);
399ec807 3006 }
3ddea128
MT		 3007 create_irqchip_unlock:
3008 mutex_unlock(&kvm->lock);
1fe779f8 3009 break;
3ddea128 3010 }
7837699f 3011 case KVM_CREATE_PIT:
c5ff41ce
JK		 3012 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3013 goto create_pit;
3014 case KVM_CREATE_PIT2:
3015 r = -EFAULT;
3016 if (copy_from_user(&u.pit_config, argp,
3017 sizeof(struct kvm_pit_config)))
3018 goto out;
3019 create_pit:
79fac95e 3020 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3021 r = -EEXIST;
3022 if (kvm->arch.vpit)
3023 goto create_pit_unlock;
7837699f 3024 r = -ENOMEM;
c5ff41ce 3025 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3026 if (kvm->arch.vpit)
3027 r = 0;
269e05e4 3028 create_pit_unlock:
79fac95e 3029 mutex_unlock(&kvm->slots_lock);
7837699f 3030 break;
4925663a 3031 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3032 case KVM_IRQ_LINE: {
3033 struct kvm_irq_level irq_event;
3034
3035 r = -EFAULT;
3036 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3037 goto out;
160d2f6c 3038 r = -ENXIO;
1fe779f8 3039 if (irqchip_in_kernel(kvm)) {
4925663a 3040 __s32 status;
4925663a
GN		 3041 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3042 irq_event.irq, irq_event.level);
4925663a 3043 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3044 r = -EFAULT;
4925663a
GN		 3045 irq_event.status = status;
3046 if (copy_to_user(argp, &irq_event,
3047 sizeof irq_event))
3048 goto out;
3049 }
1fe779f8
CO		 3050 r = 0;
3051 }
3052 break;
3053 }
3054 case KVM_GET_IRQCHIP: {
3055 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3056 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3057
f0d66275
DH		 3058 r = -ENOMEM;
3059 if (!chip)
1fe779f8 3060 goto out;
f0d66275
DH		 3061 r = -EFAULT;
3062 if (copy_from_user(chip, argp, sizeof *chip))
3063 goto get_irqchip_out;
1fe779f8
CO		 3064 r = -ENXIO;
3065 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3066 goto get_irqchip_out;
3067 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3068 if (r)
f0d66275 3069 goto get_irqchip_out;
1fe779f8 3070 r = -EFAULT;
f0d66275
DH		 3071 if (copy_to_user(argp, chip, sizeof *chip))
3072 goto get_irqchip_out;
1fe779f8 3073 r = 0;
f0d66275
DH		 3074 get_irqchip_out:
3075 kfree(chip);
3076 if (r)
3077 goto out;
1fe779f8
CO		 3078 break;
3079 }
3080 case KVM_SET_IRQCHIP: {
3081 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3082 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3083
f0d66275
DH		 3084 r = -ENOMEM;
3085 if (!chip)
1fe779f8 3086 goto out;
f0d66275
DH		 3087 r = -EFAULT;
3088 if (copy_from_user(chip, argp, sizeof *chip))
3089 goto set_irqchip_out;
1fe779f8
CO		 3090 r = -ENXIO;
3091 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3092 goto set_irqchip_out;
3093 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3094 if (r)
f0d66275 3095 goto set_irqchip_out;
1fe779f8 3096 r = 0;
f0d66275
DH		 3097 set_irqchip_out:
3098 kfree(chip);
3099 if (r)
3100 goto out;
1fe779f8
CO		 3101 break;
3102 }
e0f63cb9 3103 case KVM_GET_PIT: {
e0f63cb9 3104 r = -EFAULT;
f0d66275 3105 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3106 goto out;
3107 r = -ENXIO;
3108 if (!kvm->arch.vpit)
3109 goto out;
f0d66275 3110 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3111 if (r)
3112 goto out;
3113 r = -EFAULT;
f0d66275 3114 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3115 goto out;
3116 r = 0;
3117 break;
3118 }
3119 case KVM_SET_PIT: {
e0f63cb9 3120 r = -EFAULT;
f0d66275 3121 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3122 goto out;
3123 r = -ENXIO;
3124 if (!kvm->arch.vpit)
3125 goto out;
f0d66275 3126 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3127 if (r)
3128 goto out;
3129 r = 0;
3130 break;
3131 }
e9f42757
BK		 3132 case KVM_GET_PIT2: {
3133 r = -ENXIO;
3134 if (!kvm->arch.vpit)
3135 goto out;
3136 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3137 if (r)
3138 goto out;
3139 r = -EFAULT;
3140 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3141 goto out;
3142 r = 0;
3143 break;
3144 }
3145 case KVM_SET_PIT2: {
3146 r = -EFAULT;
3147 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3148 goto out;
3149 r = -ENXIO;
3150 if (!kvm->arch.vpit)
3151 goto out;
3152 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3153 if (r)
3154 goto out;
3155 r = 0;
3156 break;
3157 }
52d939a0
MT		 3158 case KVM_REINJECT_CONTROL: {
3159 struct kvm_reinject_control control;
3160 r = -EFAULT;
3161 if (copy_from_user(&control, argp, sizeof(control)))
3162 goto out;
3163 r = kvm_vm_ioctl_reinject(kvm, &control);
3164 if (r)
3165 goto out;
3166 r = 0;
3167 break;
3168 }
ffde22ac
ES		 3169 case KVM_XEN_HVM_CONFIG: {
3170 r = -EFAULT;
3171 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3172 sizeof(struct kvm_xen_hvm_config)))
3173 goto out;
3174 r = -EINVAL;
3175 if (kvm->arch.xen_hvm_config.flags)
3176 goto out;
3177 r = 0;
3178 break;
3179 }
afbcf7ab
GC		 3180 case KVM_SET_CLOCK: {
3181 struct timespec now;
3182 struct kvm_clock_data user_ns;
3183 u64 now_ns;
3184 s64 delta;
3185
3186 r = -EFAULT;
3187 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3188 goto out;
3189
3190 r = -EINVAL;
3191 if (user_ns.flags)
3192 goto out;
3193
3194 r = 0;
3195 ktime_get_ts(&now);
3196 now_ns = timespec_to_ns(&now);
3197 delta = user_ns.clock - now_ns;
3198 kvm->arch.kvmclock_offset = delta;
3199 break;
3200 }
3201 case KVM_GET_CLOCK: {
3202 struct timespec now;
3203 struct kvm_clock_data user_ns;
3204 u64 now_ns;
3205
3206 ktime_get_ts(&now);
3207 now_ns = timespec_to_ns(&now);
3208 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3209 user_ns.flags = 0;
3210
3211 r = -EFAULT;
3212 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3213 goto out;
3214 r = 0;
3215 break;
3216 }
3217
1fe779f8
CO		 3218 default:
3219 ;
3220 }
3221out:
3222 return r;
3223}
3224
a16b043c 3225static void kvm_init_msr_list(void)
043405e1
CO		 3226{
3227 u32 dummy[2];
3228 unsigned i, j;
3229
e3267cbb
GC		 3230 /* skip the first msrs in the list. KVM-specific */
3231 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3232 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3233 continue;
3234 if (j < i)
3235 msrs_to_save[j] = msrs_to_save[i];
3236 j++;
3237 }
3238 num_msrs_to_save = j;
3239}
3240
bda9020e
MT		 3241static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3242 const void *v)
bbd9b64e 3243{
bda9020e
MT		 3244 if (vcpu->arch.apic &&
3245 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3246 return 0;
bbd9b64e 3247
e93f8a0f 3248 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3249}
3250
bda9020e 3251static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3252{
bda9020e
MT		 3253 if (vcpu->arch.apic &&
3254 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3255 return 0;
bbd9b64e 3256
e93f8a0f 3257 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3258}
3259
2dafc6c2
GN		 3260static void kvm_set_segment(struct kvm_vcpu *vcpu,
3261 struct kvm_segment *var, int seg)
3262{
3263 kvm_x86_ops->set_segment(vcpu, var, seg);
3264}
3265
3266void kvm_get_segment(struct kvm_vcpu *vcpu,
3267 struct kvm_segment *var, int seg)
3268{
3269 kvm_x86_ops->get_segment(vcpu, var, seg);
3270}
3271
1871c602
GN		 3272gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3273{
3274 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3275 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3276}
3277
3278 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3279{
3280 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3281 access |= PFERR_FETCH_MASK;
3282 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3283}
3284
3285gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3286{
3287 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3288 access |= PFERR_WRITE_MASK;
3289 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3290}
3291
3292/* uses this to access any guest's mapped memory without checking CPL */
3293gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3294{
3295 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3296}
3297
3298static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3299 struct kvm_vcpu *vcpu, u32 access,
3300 u32 *error)
bbd9b64e
CO		 3301{
3302 void *data = val;
10589a46 3303 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3304
3305 while (bytes) {
1871c602 3306 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3307 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3308 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3309 int ret;
3310
10589a46
MT		 3311 if (gpa == UNMAPPED_GVA) {
3312 r = X86EMUL_PROPAGATE_FAULT;
3313 goto out;
3314 }
77c2002e 3315 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3316 if (ret < 0) {
c3cd7ffa 3317 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3318 goto out;
3319 }
bbd9b64e 3320
77c2002e
IE		 3321 bytes -= toread;
3322 data += toread;
3323 addr += toread;
bbd9b64e 3324 }
10589a46 3325out:
10589a46 3326 return r;
bbd9b64e 3327}
77c2002e 3328
1871c602
GN		 3329/* used for instruction fetching */
3330static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3331 struct kvm_vcpu *vcpu, u32 *error)
3332{
3333 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3334 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3335 access | PFERR_FETCH_MASK, error);
3336}
3337
3338static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3339 struct kvm_vcpu *vcpu, u32 *error)
3340{
3341 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3342 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3343 error);
3344}
3345
3346static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3347 struct kvm_vcpu *vcpu, u32 *error)
3348{
3349 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3350}
3351
7972995b 3352static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3353 unsigned int bytes,
7972995b 3354 struct kvm_vcpu *vcpu,
2dafc6c2 3355 u32 *error)
77c2002e
IE		 3356{
3357 void *data = val;
3358 int r = X86EMUL_CONTINUE;
3359
3360 while (bytes) {
7972995b
GN		 3361 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3362 PFERR_WRITE_MASK, error);
77c2002e
IE		 3363 unsigned offset = addr & (PAGE_SIZE-1);
3364 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3365 int ret;
3366
3367 if (gpa == UNMAPPED_GVA) {
3368 r = X86EMUL_PROPAGATE_FAULT;
3369 goto out;
3370 }
3371 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3372 if (ret < 0) {
c3cd7ffa 3373 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3374 goto out;
3375 }
3376
3377 bytes -= towrite;
3378 data += towrite;
3379 addr += towrite;
3380 }
3381out:
3382 return r;
3383}
3384
bbd9b64e
CO		 3385static int emulator_read_emulated(unsigned long addr,
3386 void *val,
3387 unsigned int bytes,
8fe681e9 3388 unsigned int *error_code,
bbd9b64e
CO		 3389 struct kvm_vcpu *vcpu)
3390{
bbd9b64e
CO		 3391 gpa_t gpa;
3392
3393 if (vcpu->mmio_read_completed) {
3394 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3395 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3396 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3397 vcpu->mmio_read_completed = 0;
3398 return X86EMUL_CONTINUE;
3399 }
3400
8fe681e9 3401 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3402
8fe681e9 3403 if (gpa == UNMAPPED_GVA)
1871c602 3404 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3405
3406 /* For APIC access vmexit */
3407 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3408 goto mmio;
3409
1871c602 3410 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3411 == X86EMUL_CONTINUE)
bbd9b64e 3412 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3413
3414mmio:
3415 /*
3416 * Is this MMIO handled locally?
3417 */
aec51dc4
AK		 3418 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3419 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3420 return X86EMUL_CONTINUE;
3421 }
aec51dc4
AK		 3422
3423 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3424
3425 vcpu->mmio_needed = 1;
411c35b7
GN		 3426 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3427 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3428 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3429 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3430
c3cd7ffa 3431 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3432}
3433
3200f405 3434int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3435 const void *val, int bytes)
bbd9b64e
CO		 3436{
3437 int ret;
3438
3439 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3440 if (ret < 0)
bbd9b64e 3441 return 0;
ad218f85 3442 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3443 return 1;
3444}
3445
3446static int emulator_write_emulated_onepage(unsigned long addr,
3447 const void *val,
3448 unsigned int bytes,
8fe681e9 3449 unsigned int *error_code,
bbd9b64e
CO		 3450 struct kvm_vcpu *vcpu)
3451{
10589a46
MT		 3452 gpa_t gpa;
3453
8fe681e9 3454 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3455
8fe681e9 3456 if (gpa == UNMAPPED_GVA)
bbd9b64e 3457 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3458
3459 /* For APIC access vmexit */
3460 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3461 goto mmio;
3462
3463 if (emulator_write_phys(vcpu, gpa, val, bytes))
3464 return X86EMUL_CONTINUE;
3465
3466mmio:
aec51dc4 3467 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3468 /*
3469 * Is this MMIO handled locally?
3470 */
bda9020e 3471 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3472 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3473
3474 vcpu->mmio_needed = 1;
411c35b7
GN		 3475 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3476 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3477 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3478 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3479 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3480
3481 return X86EMUL_CONTINUE;
3482}
3483
3484int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3485 const void *val,
3486 unsigned int bytes,
8fe681e9 3487 unsigned int *error_code,
8f6abd06 3488 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3489{
3490 /* Crossing a page boundary? */
3491 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3492 int rc, now;
3493
3494 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3495 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3496 vcpu);
bbd9b64e
CO		 3497 if (rc != X86EMUL_CONTINUE)
3498 return rc;
3499 addr += now;
3500 val += now;
3501 bytes -= now;
3502 }
8fe681e9
GN		 3503 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3504 vcpu);
bbd9b64e 3505}
bbd9b64e 3506
daea3e73
AK		 3507#define CMPXCHG_TYPE(t, ptr, old, new) \
3508 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3509
3510#ifdef CONFIG_X86_64
3511# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3512#else
3513# define CMPXCHG64(ptr, old, new) \
9749a6c0 3514 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3515#endif
3516
bbd9b64e
CO		 3517static int emulator_cmpxchg_emulated(unsigned long addr,
3518 const void *old,
3519 const void *new,
3520 unsigned int bytes,
8fe681e9 3521 unsigned int *error_code,
bbd9b64e
CO		 3522 struct kvm_vcpu *vcpu)
3523{
daea3e73
AK		 3524 gpa_t gpa;
3525 struct page *page;
3526 char *kaddr;
3527 bool exchanged;
2bacc55c 3528
daea3e73
AK		 3529 /* guests cmpxchg8b have to be emulated atomically */
3530 if (bytes > 8 || (bytes & (bytes - 1)))
3531 goto emul_write;
10589a46 3532
daea3e73 3533 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3534
daea3e73
AK		 3535 if (gpa == UNMAPPED_GVA ||
3536 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3537 goto emul_write;
2bacc55c 3538
daea3e73
AK		 3539 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3540 goto emul_write;
72dc67a6 3541
daea3e73 3542 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3543
daea3e73
AK		 3544 kaddr = kmap_atomic(page, KM_USER0);
3545 kaddr += offset_in_page(gpa);
3546 switch (bytes) {
3547 case 1:
3548 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3549 break;
3550 case 2:
3551 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3552 break;
3553 case 4:
3554 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3555 break;
3556 case 8:
3557 exchanged = CMPXCHG64(kaddr, old, new);
3558 break;
3559 default:
3560 BUG();
2bacc55c 3561 }
daea3e73
AK		 3562 kunmap_atomic(kaddr, KM_USER0);
3563 kvm_release_page_dirty(page);
3564
3565 if (!exchanged)
3566 return X86EMUL_CMPXCHG_FAILED;
3567
8f6abd06
GN		 3568 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3569
3570 return X86EMUL_CONTINUE;
4a5f48f6 3571
3200f405 3572emul_write:
daea3e73 3573 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3574
8fe681e9 3575 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3576}
3577
cf8f70bf
GN		 3578static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3579{
3580 /* TODO: String I/O for in kernel device */
3581 int r;
3582
3583 if (vcpu->arch.pio.in)
3584 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3585 vcpu->arch.pio.size, pd);
3586 else
3587 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3588 vcpu->arch.pio.port, vcpu->arch.pio.size,
3589 pd);
3590 return r;
3591}
3592
3593
3594static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3595 unsigned int count, struct kvm_vcpu *vcpu)
3596{
7972995b 3597 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3598 goto data_avail;
3599
3600 trace_kvm_pio(1, port, size, 1);
3601
3602 vcpu->arch.pio.port = port;
3603 vcpu->arch.pio.in = 1;
7972995b 3604 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3605 vcpu->arch.pio.size = size;
3606
3607 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3608 data_avail:
3609 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3610 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3611 return 1;
3612 }
3613
3614 vcpu->run->exit_reason = KVM_EXIT_IO;
3615 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3616 vcpu->run->io.size = size;
3617 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3618 vcpu->run->io.count = count;
3619 vcpu->run->io.port = port;
3620
3621 return 0;
3622}
3623
3624static int emulator_pio_out_emulated(int size, unsigned short port,
3625 const void *val, unsigned int count,
3626 struct kvm_vcpu *vcpu)
3627{
3628 trace_kvm_pio(0, port, size, 1);
3629
3630 vcpu->arch.pio.port = port;
3631 vcpu->arch.pio.in = 0;
7972995b 3632 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3633 vcpu->arch.pio.size = size;
3634
3635 memcpy(vcpu->arch.pio_data, val, size * count);
3636
3637 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3638 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3639 return 1;
3640 }
3641
3642 vcpu->run->exit_reason = KVM_EXIT_IO;
3643 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3644 vcpu->run->io.size = size;
3645 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3646 vcpu->run->io.count = count;
3647 vcpu->run->io.port = port;
3648
3649 return 0;
3650}
3651
bbd9b64e
CO		 3652static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3653{
3654 return kvm_x86_ops->get_segment_base(vcpu, seg);
3655}
3656
3657int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3658{
a7052897 3659 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3660 return X86EMUL_CONTINUE;
3661}
3662
3663int emulate_clts(struct kvm_vcpu *vcpu)
3664{
4d4ec087 3665 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3666 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3667 return X86EMUL_CONTINUE;
3668}
3669
35aa5375 3670int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3671{
338dbc97 3672 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3673}
3674
35aa5375 3675int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3676{
338dbc97
GN		 3677
3678 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3679}
3680
52a46617 3681static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3682{
52a46617 3683 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3684}
3685
52a46617 3686static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3687{
52a46617
GN		 3688 unsigned long value;
3689
3690 switch (cr) {
3691 case 0:
3692 value = kvm_read_cr0(vcpu);
3693 break;
3694 case 2:
3695 value = vcpu->arch.cr2;
3696 break;
3697 case 3:
3698 value = vcpu->arch.cr3;
3699 break;
3700 case 4:
3701 value = kvm_read_cr4(vcpu);
3702 break;
3703 case 8:
3704 value = kvm_get_cr8(vcpu);
3705 break;
3706 default:
3707 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3708 return 0;
3709 }
3710
3711 return value;
3712}
3713
0f12244f 3714static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3715{
0f12244f
GN		 3716 int res = 0;
3717
52a46617
GN		 3718 switch (cr) {
3719 case 0:
49a9b07e 3720 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3721 break;
3722 case 2:
3723 vcpu->arch.cr2 = val;
3724 break;
3725 case 3:
2390218b 3726 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 3727 break;
3728 case 4:
a83b29c6 3729 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3730 break;
3731 case 8:
0f12244f 3732 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3733 break;
3734 default:
3735 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3736 res = -1;
52a46617 3737 }
0f12244f
GN		 3738
3739 return res;
52a46617
GN		 3740}
3741
9c537244
GN		 3742static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3743{
3744 return kvm_x86_ops->get_cpl(vcpu);
3745}
3746
2dafc6c2
GN		 3747static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3748{
3749 kvm_x86_ops->get_gdt(vcpu, dt);
3750}
3751
5951c442
GN		 3752static unsigned long emulator_get_cached_segment_base(int seg,
3753 struct kvm_vcpu *vcpu)
3754{
3755 return get_segment_base(vcpu, seg);
3756}
3757
2dafc6c2
GN		 3758static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3759 struct kvm_vcpu *vcpu)
3760{
3761 struct kvm_segment var;
3762
3763 kvm_get_segment(vcpu, &var, seg);
3764
3765 if (var.unusable)
3766 return false;
3767
3768 if (var.g)
3769 var.limit >>= 12;
3770 set_desc_limit(desc, var.limit);
3771 set_desc_base(desc, (unsigned long)var.base);
3772 desc->type = var.type;
3773 desc->s = var.s;
3774 desc->dpl = var.dpl;
3775 desc->p = var.present;
3776 desc->avl = var.avl;
3777 desc->l = var.l;
3778 desc->d = var.db;
3779 desc->g = var.g;
3780
3781 return true;
3782}
3783
3784static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3785 struct kvm_vcpu *vcpu)
3786{
3787 struct kvm_segment var;
3788
3789 /* needed to preserve selector */
3790 kvm_get_segment(vcpu, &var, seg);
3791
3792 var.base = get_desc_base(desc);
3793 var.limit = get_desc_limit(desc);
3794 if (desc->g)
3795 var.limit = (var.limit << 12) | 0xfff;
3796 var.type = desc->type;
3797 var.present = desc->p;
3798 var.dpl = desc->dpl;
3799 var.db = desc->d;
3800 var.s = desc->s;
3801 var.l = desc->l;
3802 var.g = desc->g;
3803 var.avl = desc->avl;
3804 var.present = desc->p;
3805 var.unusable = !var.present;
3806 var.padding = 0;
3807
3808 kvm_set_segment(vcpu, &var, seg);
3809 return;
3810}
3811
3812static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3813{
3814 struct kvm_segment kvm_seg;
3815
3816 kvm_get_segment(vcpu, &kvm_seg, seg);
3817 return kvm_seg.selector;
3818}
3819
3820static void emulator_set_segment_selector(u16 sel, int seg,
3821 struct kvm_vcpu *vcpu)
3822{
3823 struct kvm_segment kvm_seg;
3824
3825 kvm_get_segment(vcpu, &kvm_seg, seg);
3826 kvm_seg.selector = sel;
3827 kvm_set_segment(vcpu, &kvm_seg, seg);
3828}
3829
14af3f3c 3830static struct x86_emulate_ops emulate_ops = {
1871c602 3831 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3832 .write_std = kvm_write_guest_virt_system,
1871c602 3833 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3834 .read_emulated = emulator_read_emulated,
3835 .write_emulated = emulator_write_emulated,
3836 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3837 .pio_in_emulated = emulator_pio_in_emulated,
3838 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3839 .get_cached_descriptor = emulator_get_cached_descriptor,
3840 .set_cached_descriptor = emulator_set_cached_descriptor,
3841 .get_segment_selector = emulator_get_segment_selector,
3842 .set_segment_selector = emulator_set_segment_selector,
5951c442 3843 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 3844 .get_gdt = emulator_get_gdt,
52a46617
GN		 3845 .get_cr = emulator_get_cr,
3846 .set_cr = emulator_set_cr,
9c537244 3847 .cpl = emulator_get_cpl,
35aa5375
GN		 3848 .get_dr = emulator_get_dr,
3849 .set_dr = emulator_set_dr,
3fb1b5db
GN		 3850 .set_msr = kvm_set_msr,
3851 .get_msr = kvm_get_msr,
bbd9b64e
CO		 3852};
3853
5fdbf976
MT		 3854static void cache_all_regs(struct kvm_vcpu *vcpu)
3855{
3856 kvm_register_read(vcpu, VCPU_REGS_RAX);
3857 kvm_register_read(vcpu, VCPU_REGS_RSP);
3858 kvm_register_read(vcpu, VCPU_REGS_RIP);
3859 vcpu->arch.regs_dirty = ~0;
3860}
3861
95cb2295
GN		 3862static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
3863{
3864 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
3865 /*
3866 * an sti; sti; sequence only disable interrupts for the first
3867 * instruction. So, if the last instruction, be it emulated or
3868 * not, left the system with the INT_STI flag enabled, it
3869 * means that the last instruction is an sti. We should not
3870 * leave the flag on in this case. The same goes for mov ss
3871 */
3872 if (!(int_shadow & mask))
3873 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
3874}
3875
54b8486f
GN		 3876static void inject_emulated_exception(struct kvm_vcpu *vcpu)
3877{
3878 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
3879 if (ctxt->exception == PF_VECTOR)
3880 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
3881 else if (ctxt->error_code_valid)
3882 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
3883 else
3884 kvm_queue_exception(vcpu, ctxt->exception);
3885}
3886
6d77dbfc
GN		 3887static int handle_emulation_failure(struct kvm_vcpu *vcpu)
3888{
6d77dbfc
GN		 3889 ++vcpu->stat.insn_emulation_fail;
3890 trace_kvm_emulate_insn_failed(vcpu);
3891 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3892 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3893 vcpu->run->internal.ndata = 0;
3894 kvm_queue_exception(vcpu, UD_VECTOR);
3895 return EMULATE_FAIL;
3896}
3897
bbd9b64e 3898int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3899 unsigned long cr2,
3900 u16 error_code,
571008da 3901 int emulation_type)
bbd9b64e 3902{
95cb2295 3903 int r;
4d2179e1 3904 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 3905
26eef70c 3906 kvm_clear_exception_queue(vcpu);
ad312c7c 3907 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3908 /*
56e82318 3909 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3910 * instead of direct ->regs accesses, can save hundred cycles
3911 * on Intel for instructions that don't read/change RSP, for
3912 * for example.
3913 */
3914 cache_all_regs(vcpu);
bbd9b64e 3915
571008da 3916 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3917 int cs_db, cs_l;
3918 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3919
ad312c7c 3920 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3921 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3922 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3923 vcpu->arch.emulate_ctxt.mode =
a0044755 3924 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3925 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3926 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3927 ? X86EMUL_MODE_PROT64 : cs_db
3928 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 3929 memset(c, 0, sizeof(struct decode_cache));
3930 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
95cb2295 3931 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 3932 vcpu->arch.emulate_ctxt.exception = -1;
bbd9b64e 3933
ad312c7c 3934 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3935 trace_kvm_emulate_insn_start(vcpu);
571008da 3936
0cb5762e
AP		 3937 /* Only allow emulation of specific instructions on #UD
3938 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 3939 if (emulation_type & EMULTYPE_TRAP_UD) {
3940 if (!c->twobyte)
3941 return EMULATE_FAIL;
3942 switch (c->b) {
3943 case 0x01: /* VMMCALL */
3944 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3945 return EMULATE_FAIL;
3946 break;
3947 case 0x34: /* sysenter */
3948 case 0x35: /* sysexit */
3949 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3950 return EMULATE_FAIL;
3951 break;
3952 case 0x05: /* syscall */
3953 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3954 return EMULATE_FAIL;
3955 break;
3956 default:
3957 return EMULATE_FAIL;
3958 }
3959
3960 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3961 return EMULATE_FAIL;
3962 }
571008da 3963
f2b5756b 3964 ++vcpu->stat.insn_emulation;
bbd9b64e
CO		 3965 if (r) {
3966 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3967 return EMULATE_DONE;
6d77dbfc
GN		 3968 if (emulation_type & EMULTYPE_SKIP)
3969 return EMULATE_FAIL;
3970 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3971 }
3972 }
3973
ba8afb6b
GN		 3974 if (emulation_type & EMULTYPE_SKIP) {
3975 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3976 return EMULATE_DONE;
3977 }
3978
4d2179e1
GN		 3979 /* this is needed for vmware backdor interface to work since it
3980 changes registers values during IO operation */
3981 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
3982
5cd21917 3983restart:
ad312c7c 3984 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 3985
c3cd7ffa
GN		 3986 if (r) { /* emulation failed */
3987 /*
3988 * if emulation was due to access to shadowed page table
3989 * and it failed try to unshadow page and re-entetr the
3990 * guest to let CPU execute the instruction.
3991 */
3992 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3993 return EMULATE_DONE;
3994
6d77dbfc 3995 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3996 }
3997
95cb2295 3998 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
ef050dc0 3999 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4d2179e1 4000 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 4001 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
3457e419 4002
54b8486f
GN		 4003 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4004 inject_emulated_exception(vcpu);
4005 return EMULATE_DONE;
4006 }
4007
3457e419
GN		 4008 if (vcpu->arch.pio.count) {
4009 if (!vcpu->arch.pio.in)
4010 vcpu->arch.pio.count = 0;
4011 return EMULATE_DO_MMIO;
4012 }
4013
4014 if (vcpu->mmio_needed) {
4015 if (vcpu->mmio_is_write)
4016 vcpu->mmio_needed = 0;
4017 return EMULATE_DO_MMIO;
4018 }
4019
5cd21917
GN		 4020 if (vcpu->arch.emulate_ctxt.restart)
4021 goto restart;
f850e2e6 4022
bbd9b64e 4023 return EMULATE_DONE;
de7d789a 4024}
bbd9b64e 4025EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4026
cf8f70bf 4027int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4028{
cf8f70bf
GN		 4029 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4030 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4031 /* do not return to emulator after return from userspace */
7972995b 4032 vcpu->arch.pio.count = 0;
de7d789a
CO		 4033 return ret;
4034}
cf8f70bf 4035EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4036
c8076604
GH		 4037static void bounce_off(void *info)
4038{
4039 /* nothing */
4040}
4041
c8076604
GH		 4042static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4043 void *data)
4044{
4045 struct cpufreq_freqs *freq = data;
4046 struct kvm *kvm;
4047 struct kvm_vcpu *vcpu;
4048 int i, send_ipi = 0;
4049
c8076604
GH		 4050 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4051 return 0;
4052 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4053 return 0;
0cca7907 4054 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 4055
4056 spin_lock(&kvm_lock);
4057 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4058 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4059 if (vcpu->cpu != freq->cpu)
4060 continue;
4061 if (!kvm_request_guest_time_update(vcpu))
4062 continue;
4063 if (vcpu->cpu != smp_processor_id())
4064 send_ipi++;
4065 }
4066 }
4067 spin_unlock(&kvm_lock);
4068
4069 if (freq->old < freq->new && send_ipi) {
4070 /*
4071 * We upscale the frequency. Must make the guest
4072 * doesn't see old kvmclock values while running with
4073 * the new frequency, otherwise we risk the guest sees
4074 * time go backwards.
4075 *
4076 * In case we update the frequency for another cpu
4077 * (which might be in guest context) send an interrupt
4078 * to kick the cpu out of guest context. Next time
4079 * guest context is entered kvmclock will be updated,
4080 * so the guest will not see stale values.
4081 */
4082 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4083 }
4084 return 0;
4085}
4086
4087static struct notifier_block kvmclock_cpufreq_notifier_block = {
4088 .notifier_call = kvmclock_cpufreq_notifier
4089};
4090
b820cc0c
ZA		 4091static void kvm_timer_init(void)
4092{
4093 int cpu;
4094
b820cc0c 4095 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4096 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4097 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4098 for_each_online_cpu(cpu) {
4099 unsigned long khz = cpufreq_get(cpu);
4100 if (!khz)
4101 khz = tsc_khz;
4102 per_cpu(cpu_tsc_khz, cpu) = khz;
4103 }
0cca7907
ZA		 4104 } else {
4105 for_each_possible_cpu(cpu)
4106 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4107 }
4108}
4109
ff9d07a0
ZY		 4110static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4111
4112static int kvm_is_in_guest(void)
4113{
4114 return percpu_read(current_vcpu) != NULL;
4115}
4116
4117static int kvm_is_user_mode(void)
4118{
4119 int user_mode = 3;
dcf46b94 4120
ff9d07a0
ZY		 4121 if (percpu_read(current_vcpu))
4122 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4123
ff9d07a0
ZY		 4124 return user_mode != 0;
4125}
4126
4127static unsigned long kvm_get_guest_ip(void)
4128{
4129 unsigned long ip = 0;
dcf46b94 4130
ff9d07a0
ZY		 4131 if (percpu_read(current_vcpu))
4132 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4133
ff9d07a0
ZY		 4134 return ip;
4135}
4136
4137static struct perf_guest_info_callbacks kvm_guest_cbs = {
4138 .is_in_guest = kvm_is_in_guest,
4139 .is_user_mode = kvm_is_user_mode,
4140 .get_guest_ip = kvm_get_guest_ip,
4141};
4142
4143void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4144{
4145 percpu_write(current_vcpu, vcpu);
4146}
4147EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4148
4149void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4150{
4151 percpu_write(current_vcpu, NULL);
4152}
4153EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4154
f8c16bba 4155int kvm_arch_init(void *opaque)
043405e1 4156{
b820cc0c 4157 int r;
f8c16bba
ZX		 4158 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4159
f8c16bba
ZX		 4160 if (kvm_x86_ops) {
4161 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4162 r = -EEXIST;
4163 goto out;
f8c16bba
ZX		 4164 }
4165
4166 if (!ops->cpu_has_kvm_support()) {
4167 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4168 r = -EOPNOTSUPP;
4169 goto out;
f8c16bba
ZX		 4170 }
4171 if (ops->disabled_by_bios()) {
4172 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4173 r = -EOPNOTSUPP;
4174 goto out;
f8c16bba
ZX		 4175 }
4176
97db56ce
AK		 4177 r = kvm_mmu_module_init();
4178 if (r)
4179 goto out;
4180
4181 kvm_init_msr_list();
4182
f8c16bba 4183 kvm_x86_ops = ops;
56c6d28a 4184 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4185 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4186 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4187 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4188
b820cc0c 4189 kvm_timer_init();
c8076604 4190
ff9d07a0
ZY		 4191 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4192
2acf923e
DC		 4193 if (cpu_has_xsave)
4194 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4195
f8c16bba 4196 return 0;
56c6d28a
ZX		 4197
4198out:
56c6d28a 4199 return r;
043405e1 4200}
8776e519 4201
f8c16bba
ZX		 4202void kvm_arch_exit(void)
4203{
ff9d07a0
ZY		 4204 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4205
888d256e
JK		 4206 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4207 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4208 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4209 kvm_x86_ops = NULL;
56c6d28a
ZX		 4210 kvm_mmu_module_exit();
4211}
f8c16bba 4212
8776e519
HB		 4213int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4214{
4215 ++vcpu->stat.halt_exits;
4216 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4217 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4218 return 1;
4219 } else {
4220 vcpu->run->exit_reason = KVM_EXIT_HLT;
4221 return 0;
4222 }
4223}
4224EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4225
2f333bcb
MT		 4226static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4227 unsigned long a1)
4228{
4229 if (is_long_mode(vcpu))
4230 return a0;
4231 else
4232 return a0 | ((gpa_t)a1 << 32);
4233}
4234
55cd8e5a
GN		 4235int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4236{
4237 u64 param, ingpa, outgpa, ret;
4238 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4239 bool fast, longmode;
4240 int cs_db, cs_l;
4241
4242 /*
4243 * hypercall generates UD from non zero cpl and real mode
4244 * per HYPER-V spec
4245 */
3eeb3288 4246 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4247 kvm_queue_exception(vcpu, UD_VECTOR);
4248 return 0;
4249 }
4250
4251 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4252 longmode = is_long_mode(vcpu) && cs_l == 1;
4253
4254 if (!longmode) {
ccd46936
GN		 4255 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4256 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4257 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4258 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4259 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4260 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4261 }
4262#ifdef CONFIG_X86_64
4263 else {
4264 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4265 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4266 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4267 }
4268#endif
4269
4270 code = param & 0xffff;
4271 fast = (param >> 16) & 0x1;
4272 rep_cnt = (param >> 32) & 0xfff;
4273 rep_idx = (param >> 48) & 0xfff;
4274
4275 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4276
c25bc163
GN		 4277 switch (code) {
4278 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4279 kvm_vcpu_on_spin(vcpu);
4280 break;
4281 default:
4282 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4283 break;
4284 }
55cd8e5a
GN		 4285
4286 ret = res | (((u64)rep_done & 0xfff) << 32);
4287 if (longmode) {
4288 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4289 } else {
4290 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4291 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4292 }
4293
4294 return 1;
4295}
4296
8776e519
HB		 4297int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4298{
4299 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4300 int r = 1;
8776e519 4301
55cd8e5a
GN		 4302 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4303 return kvm_hv_hypercall(vcpu);
4304
5fdbf976
MT		 4305 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4306 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4307 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4308 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4309 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4310
229456fc 4311 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4312
8776e519
HB		 4313 if (!is_long_mode(vcpu)) {
4314 nr &= 0xFFFFFFFF;
4315 a0 &= 0xFFFFFFFF;
4316 a1 &= 0xFFFFFFFF;
4317 a2 &= 0xFFFFFFFF;
4318 a3 &= 0xFFFFFFFF;
4319 }
4320
07708c4a
JK		 4321 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4322 ret = -KVM_EPERM;
4323 goto out;
4324 }
4325
8776e519 4326 switch (nr) {
b93463aa
AK		 4327 case KVM_HC_VAPIC_POLL_IRQ:
4328 ret = 0;
4329 break;
2f333bcb
MT		 4330 case KVM_HC_MMU_OP:
4331 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4332 break;
8776e519
HB		 4333 default:
4334 ret = -KVM_ENOSYS;
4335 break;
4336 }
07708c4a 4337out:
5fdbf976 4338 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4339 ++vcpu->stat.hypercalls;
2f333bcb 4340 return r;
8776e519
HB		 4341}
4342EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4343
4344int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4345{
4346 char instruction[3];
5fdbf976 4347 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4348
8776e519
HB		 4349 /*
4350 * Blow out the MMU to ensure that no other VCPU has an active mapping
4351 * to ensure that the updated hypercall appears atomically across all
4352 * VCPUs.
4353 */
4354 kvm_mmu_zap_all(vcpu->kvm);
4355
8776e519 4356 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4357
8fe681e9 4358 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4359}
4360
8776e519
HB		 4361void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4362{
89a27f4d 4363 struct desc_ptr dt = { limit, base };
8776e519
HB		 4364
4365 kvm_x86_ops->set_gdt(vcpu, &dt);
4366}
4367
4368void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4369{
89a27f4d 4370 struct desc_ptr dt = { limit, base };
8776e519
HB		 4371
4372 kvm_x86_ops->set_idt(vcpu, &dt);
4373}
4374
07716717
DK		 4375static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4376{
ad312c7c
ZX		 4377 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4378 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4379
4380 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4381 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4382 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4383 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4384 if (ej->function == e->function) {
4385 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4386 return j;
4387 }
4388 }
4389 return 0; /* silence gcc, even though control never reaches here */
4390}
4391
4392/* find an entry with matching function, matching index (if needed), and that
4393 * should be read next (if it's stateful) */
4394static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4395 u32 function, u32 index)
4396{
4397 if (e->function != function)
4398 return 0;
4399 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4400 return 0;
4401 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4402 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4403 return 0;
4404 return 1;
4405}
4406
d8017474
AG		 4407struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4408 u32 function, u32 index)
8776e519
HB		 4409{
4410 int i;
d8017474 4411 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4412
ad312c7c 4413 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4414 struct kvm_cpuid_entry2 *e;
4415
ad312c7c 4416 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4417 if (is_matching_cpuid_entry(e, function, index)) {
4418 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4419 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4420 best = e;
4421 break;
4422 }
4423 /*
4424 * Both basic or both extended?
4425 */
4426 if (((e->function ^ function) & 0x80000000) == 0)
4427 if (!best || e->function > best->function)
4428 best = e;
4429 }
d8017474
AG		 4430 return best;
4431}
0e851880 4432EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4433
82725b20
DE		 4434int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4435{
4436 struct kvm_cpuid_entry2 *best;
4437
f7a71197
AK		 4438 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4439 if (!best || best->eax < 0x80000008)
4440 goto not_found;
82725b20
DE		 4441 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4442 if (best)
4443 return best->eax & 0xff;
f7a71197 4444not_found:
82725b20
DE		 4445 return 36;
4446}
4447
d8017474
AG		 4448void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4449{
4450 u32 function, index;
4451 struct kvm_cpuid_entry2 *best;
4452
4453 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4454 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4455 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4456 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4457 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4458 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4459 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4460 if (best) {
5fdbf976
MT		 4461 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4462 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4463 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4464 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4465 }
8776e519 4466 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4467 trace_kvm_cpuid(function,
4468 kvm_register_read(vcpu, VCPU_REGS_RAX),
4469 kvm_register_read(vcpu, VCPU_REGS_RBX),
4470 kvm_register_read(vcpu, VCPU_REGS_RCX),
4471 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4472}
4473EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4474
b6c7a5dc
HB		 4475/*
4476 * Check if userspace requested an interrupt window, and that the
4477 * interrupt window is open.
4478 *
4479 * No need to exit to userspace if we already have an interrupt queued.
4480 */
851ba692 4481static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4482{
8061823a 4483 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4484 vcpu->run->request_interrupt_window &&
5df56646 4485 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4486}
4487
851ba692 4488static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4489{
851ba692
AK		 4490 struct kvm_run *kvm_run = vcpu->run;
4491
91586a3b 4492 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4493 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4494 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4495 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4496 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4497 else
b6c7a5dc 4498 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4499 kvm_arch_interrupt_allowed(vcpu) &&
4500 !kvm_cpu_has_interrupt(vcpu) &&
4501 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4502}
4503
b93463aa
AK		 4504static void vapic_enter(struct kvm_vcpu *vcpu)
4505{
4506 struct kvm_lapic *apic = vcpu->arch.apic;
4507 struct page *page;
4508
4509 if (!apic || !apic->vapic_addr)
4510 return;
4511
4512 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4513
4514 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4515}
4516
4517static void vapic_exit(struct kvm_vcpu *vcpu)
4518{
4519 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4520 int idx;
b93463aa
AK		 4521
4522 if (!apic || !apic->vapic_addr)
4523 return;
4524
f656ce01 4525 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4526 kvm_release_page_dirty(apic->vapic_page);
4527 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4528 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4529}
4530
95ba8273
GN		 4531static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4532{
4533 int max_irr, tpr;
4534
4535 if (!kvm_x86_ops->update_cr8_intercept)
4536 return;
4537
88c808fd
AK		 4538 if (!vcpu->arch.apic)
4539 return;
4540
8db3baa2
GN		 4541 if (!vcpu->arch.apic->vapic_addr)
4542 max_irr = kvm_lapic_find_highest_irr(vcpu);
4543 else
4544 max_irr = -1;
95ba8273
GN		 4545
4546 if (max_irr != -1)
4547 max_irr >>= 4;
4548
4549 tpr = kvm_lapic_get_cr8(vcpu);
4550
4551 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4552}
4553
851ba692 4554static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4555{
4556 /* try to reinject previous events if any */
b59bb7bd 4557 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4558 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4559 vcpu->arch.exception.has_error_code,
4560 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4561 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4562 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4563 vcpu->arch.exception.error_code,
4564 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4565 return;
4566 }
4567
95ba8273
GN		 4568 if (vcpu->arch.nmi_injected) {
4569 kvm_x86_ops->set_nmi(vcpu);
4570 return;
4571 }
4572
4573 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4574 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4575 return;
4576 }
4577
4578 /* try to inject new event if pending */
4579 if (vcpu->arch.nmi_pending) {
4580 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4581 vcpu->arch.nmi_pending = false;
4582 vcpu->arch.nmi_injected = true;
4583 kvm_x86_ops->set_nmi(vcpu);
4584 }
4585 } else if (kvm_cpu_has_interrupt(vcpu)) {
4586 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4587 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4588 false);
4589 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4590 }
4591 }
4592}
4593
2acf923e
DC		 4594static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4595{
4596 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4597 !vcpu->guest_xcr0_loaded) {
4598 /* kvm_set_xcr() also depends on this */
4599 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4600 vcpu->guest_xcr0_loaded = 1;
4601 }
4602}
4603
4604static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4605{
4606 if (vcpu->guest_xcr0_loaded) {
4607 if (vcpu->arch.xcr0 != host_xcr0)
4608 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4609 vcpu->guest_xcr0_loaded = 0;
4610 }
4611}
4612
851ba692 4613static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4614{
4615 int r;
6a8b1d13 4616 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4617 vcpu->run->request_interrupt_window;
b6c7a5dc 4618
3e007509 4619 if (vcpu->requests) {
a8eeb04a 4620 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 4621 kvm_mmu_unload(vcpu);
a8eeb04a 4622 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 4623 __kvm_migrate_timers(vcpu);
a8eeb04a 4624 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu))
c8076604 4625 kvm_write_guest_time(vcpu);
a8eeb04a 4626 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 4627 kvm_mmu_sync_roots(vcpu);
a8eeb04a 4628 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 4629 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 4630 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 4631 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4632 r = 0;
4633 goto out;
4634 }
a8eeb04a 4635 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 4636 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4637 r = 0;
4638 goto out;
4639 }
a8eeb04a 4640 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 4641 vcpu->fpu_active = 0;
4642 kvm_x86_ops->fpu_deactivate(vcpu);
4643 }
2f52d58c 4644 }
b93463aa 4645
3e007509
AK		 4646 r = kvm_mmu_reload(vcpu);
4647 if (unlikely(r))
4648 goto out;
4649
b6c7a5dc
HB		 4650 preempt_disable();
4651
4652 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4653 if (vcpu->fpu_active)
4654 kvm_load_guest_fpu(vcpu);
2acf923e 4655 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 4656
d94e1dc9
AK		 4657 atomic_set(&vcpu->guest_mode, 1);
4658 smp_wmb();
b6c7a5dc 4659
d94e1dc9 4660 local_irq_disable();
32f88400 4661
d94e1dc9
AK		 4662 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4663 || need_resched() || signal_pending(current)) {
4664 atomic_set(&vcpu->guest_mode, 0);
4665 smp_wmb();
6c142801
AK		 4666 local_irq_enable();
4667 preempt_enable();
4668 r = 1;
4669 goto out;
4670 }
4671
851ba692 4672 inject_pending_event(vcpu);
b6c7a5dc 4673
6a8b1d13
GN		 4674 /* enable NMI/IRQ window open exits if needed */
4675 if (vcpu->arch.nmi_pending)
4676 kvm_x86_ops->enable_nmi_window(vcpu);
4677 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4678 kvm_x86_ops->enable_irq_window(vcpu);
4679
95ba8273 4680 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4681 update_cr8_intercept(vcpu);
4682 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4683 }
b93463aa 4684
f656ce01 4685 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4686
b6c7a5dc
HB		 4687 kvm_guest_enter();
4688
42dbaa5a 4689 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4690 set_debugreg(0, 7);
4691 set_debugreg(vcpu->arch.eff_db[0], 0);
4692 set_debugreg(vcpu->arch.eff_db[1], 1);
4693 set_debugreg(vcpu->arch.eff_db[2], 2);
4694 set_debugreg(vcpu->arch.eff_db[3], 3);
4695 }
b6c7a5dc 4696
229456fc 4697 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4698 kvm_x86_ops->run(vcpu);
b6c7a5dc 4699
24f1e32c
FW		 4700 /*
4701 * If the guest has used debug registers, at least dr7
4702 * will be disabled while returning to the host.
4703 * If we don't have active breakpoints in the host, we don't
4704 * care about the messed up debug address registers. But if
4705 * we have some of them active, restore the old state.
4706 */
59d8eb53 4707 if (hw_breakpoint_active())
24f1e32c 4708 hw_breakpoint_restore();
42dbaa5a 4709
d94e1dc9
AK		 4710 atomic_set(&vcpu->guest_mode, 0);
4711 smp_wmb();
b6c7a5dc
HB		 4712 local_irq_enable();
4713
4714 ++vcpu->stat.exits;
4715
4716 /*
4717 * We must have an instruction between local_irq_enable() and
4718 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4719 * the interrupt shadow. The stat.exits increment will do nicely.
4720 * But we need to prevent reordering, hence this barrier():
4721 */
4722 barrier();
4723
4724 kvm_guest_exit();
4725
4726 preempt_enable();
4727
f656ce01 4728 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4729
b6c7a5dc
HB		 4730 /*
4731 * Profile KVM exit RIPs:
4732 */
4733 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4734 unsigned long rip = kvm_rip_read(vcpu);
4735 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4736 }
4737
298101da 4738
b93463aa
AK		 4739 kvm_lapic_sync_from_vapic(vcpu);
4740
851ba692 4741 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4742out:
4743 return r;
4744}
b6c7a5dc 4745
09cec754 4746
851ba692 4747static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4748{
4749 int r;
f656ce01 4750 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4751
4752 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4753 pr_debug("vcpu %d received sipi with vector # %x\n",
4754 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4755 kvm_lapic_reset(vcpu);
5f179287 4756 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4757 if (r)
4758 return r;
4759 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4760 }
4761
f656ce01 4762 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4763 vapic_enter(vcpu);
4764
4765 r = 1;
4766 while (r > 0) {
af2152f5 4767 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4768 r = vcpu_enter_guest(vcpu);
d7690175 4769 else {
f656ce01 4770 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4771 kvm_vcpu_block(vcpu);
f656ce01 4772 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 4773 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 4774 {
4775 switch(vcpu->arch.mp_state) {
4776 case KVM_MP_STATE_HALTED:
d7690175 4777 vcpu->arch.mp_state =
09cec754
GN		 4778 KVM_MP_STATE_RUNNABLE;
4779 case KVM_MP_STATE_RUNNABLE:
4780 break;
4781 case KVM_MP_STATE_SIPI_RECEIVED:
4782 default:
4783 r = -EINTR;
4784 break;
4785 }
4786 }
d7690175
MT		 4787 }
4788
09cec754
GN		 4789 if (r <= 0)
4790 break;
4791
4792 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4793 if (kvm_cpu_has_pending_timer(vcpu))
4794 kvm_inject_pending_timer_irqs(vcpu);
4795
851ba692 4796 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4797 r = -EINTR;
851ba692 4798 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4799 ++vcpu->stat.request_irq_exits;
4800 }
4801 if (signal_pending(current)) {
4802 r = -EINTR;
851ba692 4803 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4804 ++vcpu->stat.signal_exits;
4805 }
4806 if (need_resched()) {
f656ce01 4807 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4808 kvm_resched(vcpu);
f656ce01 4809 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4810 }
b6c7a5dc
HB		 4811 }
4812
f656ce01 4813 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4814
b93463aa
AK		 4815 vapic_exit(vcpu);
4816
b6c7a5dc
HB		 4817 return r;
4818}
4819
4820int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4821{
4822 int r;
4823 sigset_t sigsaved;
4824
ac9f6dc0
AK		 4825 if (vcpu->sigset_active)
4826 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4827
a4535290 4828 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4829 kvm_vcpu_block(vcpu);
d7690175 4830 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4831 r = -EAGAIN;
4832 goto out;
b6c7a5dc
HB		 4833 }
4834
b6c7a5dc
HB		 4835 /* re-sync apic's tpr */
4836 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4837 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4838
92bf9748
GN		 4839 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4840 vcpu->arch.emulate_ctxt.restart) {
4841 if (vcpu->mmio_needed) {
4842 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4843 vcpu->mmio_read_completed = 1;
4844 vcpu->mmio_needed = 0;
b6c7a5dc 4845 }
f656ce01 4846 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4847 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4848 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 4849 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 4850 r = 0;
4851 goto out;
4852 }
4853 }
5fdbf976
MT		 4854 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4855 kvm_register_write(vcpu, VCPU_REGS_RAX,
4856 kvm_run->hypercall.ret);
b6c7a5dc 4857
851ba692 4858 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4859
4860out:
f1d86e46 4861 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4862 if (vcpu->sigset_active)
4863 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4864
b6c7a5dc
HB		 4865 return r;
4866}
4867
4868int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4869{
5fdbf976
MT		 4870 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4871 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4872 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4873 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4874 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4875 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4876 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4877 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4878#ifdef CONFIG_X86_64
5fdbf976
MT		 4879 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4880 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4881 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4882 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4883 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4884 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4885 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4886 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4887#endif
4888
5fdbf976 4889 regs->rip = kvm_rip_read(vcpu);
91586a3b 4890 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 4891
b6c7a5dc
HB		 4892 return 0;
4893}
4894
4895int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4896{
5fdbf976
MT		 4897 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4898 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4899 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4900 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4901 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4902 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4903 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4904 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4905#ifdef CONFIG_X86_64
5fdbf976
MT		 4906 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4907 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4908 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4909 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4910 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4911 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4912 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4913 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4914#endif
4915
5fdbf976 4916 kvm_rip_write(vcpu, regs->rip);
91586a3b 4917 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4918
b4f14abd
JK		 4919 vcpu->arch.exception.pending = false;
4920
b6c7a5dc
HB		 4921 return 0;
4922}
4923
b6c7a5dc
HB		 4924void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4925{
4926 struct kvm_segment cs;
4927
3e6e0aab 4928 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4929 *db = cs.db;
4930 *l = cs.l;
4931}
4932EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4933
4934int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4935 struct kvm_sregs *sregs)
4936{
89a27f4d 4937 struct desc_ptr dt;
b6c7a5dc 4938
3e6e0aab
GT		 4939 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4940 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4941 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4942 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4943 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4944 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4945
3e6e0aab
GT		 4946 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4947 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4948
4949 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4950 sregs->idt.limit = dt.size;
4951 sregs->idt.base = dt.address;
b6c7a5dc 4952 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4953 sregs->gdt.limit = dt.size;
4954 sregs->gdt.base = dt.address;
b6c7a5dc 4955
4d4ec087 4956 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4957 sregs->cr2 = vcpu->arch.cr2;
4958 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4959 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4960 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4961 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4962 sregs->apic_base = kvm_get_apic_base(vcpu);
4963
923c61bb 4964 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4965
36752c9b 4966 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4967 set_bit(vcpu->arch.interrupt.nr,
4968 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4969
b6c7a5dc
HB		 4970 return 0;
4971}
4972
62d9f0db
MT		 4973int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4974 struct kvm_mp_state *mp_state)
4975{
62d9f0db 4976 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 4977 return 0;
4978}
4979
4980int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4981 struct kvm_mp_state *mp_state)
4982{
62d9f0db 4983 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 4984 return 0;
4985}
4986
e269fb21
JK		 4987int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4988 bool has_error_code, u32 error_code)
b6c7a5dc 4989{
4d2179e1 4990 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
ceffb459
GN		 4991 int cs_db, cs_l, ret;
4992 cache_all_regs(vcpu);
37817f29 4993
ceffb459 4994 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 4995
ceffb459
GN		 4996 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4997 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4998 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4999 vcpu->arch.emulate_ctxt.mode =
5000 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5001 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
5002 ? X86EMUL_MODE_VM86 : cs_l
5003 ? X86EMUL_MODE_PROT64 : cs_db
5004 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 5005 memset(c, 0, sizeof(struct decode_cache));
5006 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
c697518a 5007
ceffb459 5008 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 5009 tss_selector, reason, has_error_code,
5010 error_code);
c697518a 5011
c697518a 5012 if (ret)
19d04437 5013 return EMULATE_FAIL;
37817f29 5014
4d2179e1 5015 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5016 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5017 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5018 return EMULATE_DONE;
37817f29
IE		 5019}
5020EXPORT_SYMBOL_GPL(kvm_task_switch);
5021
b6c7a5dc
HB		 5022int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5023 struct kvm_sregs *sregs)
5024{
5025 int mmu_reset_needed = 0;
923c61bb 5026 int pending_vec, max_bits;
89a27f4d 5027 struct desc_ptr dt;
b6c7a5dc 5028
89a27f4d
GN		 5029 dt.size = sregs->idt.limit;
5030 dt.address = sregs->idt.base;
b6c7a5dc 5031 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5032 dt.size = sregs->gdt.limit;
5033 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5034 kvm_x86_ops->set_gdt(vcpu, &dt);
5035
ad312c7c
ZX		 5036 vcpu->arch.cr2 = sregs->cr2;
5037 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5038 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5039
2d3ad1f4 5040 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5041
f6801dff 5042 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5043 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5044 kvm_set_apic_base(vcpu, sregs->apic_base);
5045
4d4ec087 5046 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5047 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5048 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5049
fc78f519 5050 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5051 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5052 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5053 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5054 mmu_reset_needed = 1;
5055 }
b6c7a5dc
HB		 5056
5057 if (mmu_reset_needed)
5058 kvm_mmu_reset_context(vcpu);
5059
923c61bb
GN		 5060 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5061 pending_vec = find_first_bit(
5062 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5063 if (pending_vec < max_bits) {
66fd3f7f 5064 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5065 pr_debug("Set back pending irq %d\n", pending_vec);
5066 if (irqchip_in_kernel(vcpu->kvm))
5067 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5068 }
5069
3e6e0aab
GT		 5070 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5071 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5072 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5073 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5074 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5075 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5076
3e6e0aab
GT		 5077 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5078 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5079
5f0269f5
ME		 5080 update_cr8_intercept(vcpu);
5081
9c3e4aab 5082 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5083 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5084 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5085 !is_protmode(vcpu))
9c3e4aab
MT		 5086 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5087
b6c7a5dc
HB		 5088 return 0;
5089}
5090
d0bfb940
JK		 5091int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5092 struct kvm_guest_debug *dbg)
b6c7a5dc 5093{
355be0b9 5094 unsigned long rflags;
ae675ef0 5095 int i, r;
b6c7a5dc 5096
4f926bf2
JK		 5097 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5098 r = -EBUSY;
5099 if (vcpu->arch.exception.pending)
2122ff5e 5100 goto out;
4f926bf2
JK		 5101 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5102 kvm_queue_exception(vcpu, DB_VECTOR);
5103 else
5104 kvm_queue_exception(vcpu, BP_VECTOR);
5105 }
5106
91586a3b
JK		 5107 /*
5108 * Read rflags as long as potentially injected trace flags are still
5109 * filtered out.
5110 */
5111 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5112
5113 vcpu->guest_debug = dbg->control;
5114 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5115 vcpu->guest_debug = 0;
5116
5117 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5118 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5119 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5120 vcpu->arch.switch_db_regs =
5121 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5122 } else {
5123 for (i = 0; i < KVM_NR_DB_REGS; i++)
5124 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5125 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5126 }
5127
f92653ee
JK		 5128 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5129 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5130 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5131
91586a3b
JK		 5132 /*
5133 * Trigger an rflags update that will inject or remove the trace
5134 * flags.
5135 */
5136 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5137
355be0b9 5138 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5139
4f926bf2 5140 r = 0;
d0bfb940 5141
2122ff5e 5142out:
b6c7a5dc
HB		 5143
5144 return r;
5145}
5146
8b006791
ZX		 5147/*
5148 * Translate a guest virtual address to a guest physical address.
5149 */
5150int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5151 struct kvm_translation *tr)
5152{
5153 unsigned long vaddr = tr->linear_address;
5154 gpa_t gpa;
f656ce01 5155 int idx;
8b006791 5156
f656ce01 5157 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5158 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5159 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5160 tr->physical_address = gpa;
5161 tr->valid = gpa != UNMAPPED_GVA;
5162 tr->writeable = 1;
5163 tr->usermode = 0;
8b006791
ZX		 5164
5165 return 0;
5166}
5167
d0752060
HB		 5168int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5169{
98918833
SY		 5170 struct i387_fxsave_struct *fxsave =
5171 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5172
d0752060
HB		 5173 memcpy(fpu->fpr, fxsave->st_space, 128);
5174 fpu->fcw = fxsave->cwd;
5175 fpu->fsw = fxsave->swd;
5176 fpu->ftwx = fxsave->twd;
5177 fpu->last_opcode = fxsave->fop;
5178 fpu->last_ip = fxsave->rip;
5179 fpu->last_dp = fxsave->rdp;
5180 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5181
d0752060
HB		 5182 return 0;
5183}
5184
5185int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5186{
98918833
SY		 5187 struct i387_fxsave_struct *fxsave =
5188 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5189
d0752060
HB		 5190 memcpy(fxsave->st_space, fpu->fpr, 128);
5191 fxsave->cwd = fpu->fcw;
5192 fxsave->swd = fpu->fsw;
5193 fxsave->twd = fpu->ftwx;
5194 fxsave->fop = fpu->last_opcode;
5195 fxsave->rip = fpu->last_ip;
5196 fxsave->rdp = fpu->last_dp;
5197 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5198
d0752060
HB		 5199 return 0;
5200}
5201
10ab25cd 5202int fx_init(struct kvm_vcpu *vcpu)
d0752060 5203{
10ab25cd
JK		 5204 int err;
5205
5206 err = fpu_alloc(&vcpu->arch.guest_fpu);
5207 if (err)
5208 return err;
5209
98918833 5210 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5211
2acf923e
DC		 5212 /*
5213 * Ensure guest xcr0 is valid for loading
5214 */
5215 vcpu->arch.xcr0 = XSTATE_FP;
5216
ad312c7c 5217 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5218
5219 return 0;
d0752060
HB		 5220}
5221EXPORT_SYMBOL_GPL(fx_init);
5222
98918833
SY		 5223static void fx_free(struct kvm_vcpu *vcpu)
5224{
5225 fpu_free(&vcpu->arch.guest_fpu);
5226}
5227
d0752060
HB		 5228void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5229{
2608d7a1 5230 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5231 return;
5232
2acf923e
DC		 5233 /*
5234 * Restore all possible states in the guest,
5235 * and assume host would use all available bits.
5236 * Guest xcr0 would be loaded later.
5237 */
5238 kvm_put_guest_xcr0(vcpu);
d0752060 5239 vcpu->guest_fpu_loaded = 1;
7cf30855 5240 unlazy_fpu(current);
98918833 5241 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5242 trace_kvm_fpu(1);
d0752060 5243}
d0752060
HB		 5244
5245void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5246{
2acf923e
DC		 5247 kvm_put_guest_xcr0(vcpu);
5248
d0752060
HB		 5249 if (!vcpu->guest_fpu_loaded)
5250 return;
5251
5252 vcpu->guest_fpu_loaded = 0;
98918833 5253 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5254 ++vcpu->stat.fpu_reload;
a8eeb04a 5255 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5256 trace_kvm_fpu(0);
d0752060 5257}
e9b11c17
ZX		 5258
5259void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5260{
7f1ea208
JR		 5261 if (vcpu->arch.time_page) {
5262 kvm_release_page_dirty(vcpu->arch.time_page);
5263 vcpu->arch.time_page = NULL;
5264 }
5265
98918833 5266 fx_free(vcpu);
e9b11c17
ZX		 5267 kvm_x86_ops->vcpu_free(vcpu);
5268}
5269
5270struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5271 unsigned int id)
5272{
26e5215f
AK		 5273 return kvm_x86_ops->vcpu_create(kvm, id);
5274}
e9b11c17 5275
26e5215f
AK		 5276int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5277{
5278 int r;
e9b11c17 5279
0bed3b56 5280 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5281 vcpu_load(vcpu);
5282 r = kvm_arch_vcpu_reset(vcpu);
5283 if (r == 0)
5284 r = kvm_mmu_setup(vcpu);
5285 vcpu_put(vcpu);
5286 if (r < 0)
5287 goto free_vcpu;
5288
26e5215f 5289 return 0;
e9b11c17
ZX		 5290free_vcpu:
5291 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5292 return r;
e9b11c17
ZX		 5293}
5294
d40ccc62 5295void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5296{
5297 vcpu_load(vcpu);
5298 kvm_mmu_unload(vcpu);
5299 vcpu_put(vcpu);
5300
98918833 5301 fx_free(vcpu);
e9b11c17
ZX		 5302 kvm_x86_ops->vcpu_free(vcpu);
5303}
5304
5305int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5306{
448fa4a9
JK		 5307 vcpu->arch.nmi_pending = false;
5308 vcpu->arch.nmi_injected = false;
5309
42dbaa5a
JK		 5310 vcpu->arch.switch_db_regs = 0;
5311 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5312 vcpu->arch.dr6 = DR6_FIXED_1;
5313 vcpu->arch.dr7 = DR7_FIXED_1;
5314
e9b11c17
ZX		 5315 return kvm_x86_ops->vcpu_reset(vcpu);
5316}
5317
10474ae8 5318int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5319{
0cca7907
ZA		 5320 /*
5321 * Since this may be called from a hotplug notifcation,
5322 * we can't get the CPU frequency directly.
5323 */
5324 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5325 int cpu = raw_smp_processor_id();
5326 per_cpu(cpu_tsc_khz, cpu) = 0;
5327 }
18863bdd
AK		 5328
5329 kvm_shared_msr_cpu_online();
5330
10474ae8 5331 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5332}
5333
5334void kvm_arch_hardware_disable(void *garbage)
5335{
5336 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5337 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5338}
5339
5340int kvm_arch_hardware_setup(void)
5341{
5342 return kvm_x86_ops->hardware_setup();
5343}
5344
5345void kvm_arch_hardware_unsetup(void)
5346{
5347 kvm_x86_ops->hardware_unsetup();
5348}
5349
5350void kvm_arch_check_processor_compat(void *rtn)
5351{
5352 kvm_x86_ops->check_processor_compatibility(rtn);
5353}
5354
5355int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5356{
5357 struct page *page;
5358 struct kvm *kvm;
5359 int r;
5360
5361 BUG_ON(vcpu->kvm == NULL);
5362 kvm = vcpu->kvm;
5363
ad312c7c 5364 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5365 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5366 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5367 else
a4535290 5368 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5369
5370 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5371 if (!page) {
5372 r = -ENOMEM;
5373 goto fail;
5374 }
ad312c7c 5375 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5376
5377 r = kvm_mmu_create(vcpu);
5378 if (r < 0)
5379 goto fail_free_pio_data;
5380
5381 if (irqchip_in_kernel(kvm)) {
5382 r = kvm_create_lapic(vcpu);
5383 if (r < 0)
5384 goto fail_mmu_destroy;
5385 }
5386
890ca9ae
HY		 5387 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5388 GFP_KERNEL);
5389 if (!vcpu->arch.mce_banks) {
5390 r = -ENOMEM;
443c39bc 5391 goto fail_free_lapic;
890ca9ae
HY		 5392 }
5393 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5394
e9b11c17 5395 return 0;
443c39bc
WY		 5396fail_free_lapic:
5397 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5398fail_mmu_destroy:
5399 kvm_mmu_destroy(vcpu);
5400fail_free_pio_data:
ad312c7c 5401 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5402fail:
5403 return r;
5404}
5405
5406void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5407{
f656ce01
MT		 5408 int idx;
5409
36cb93fd 5410 kfree(vcpu->arch.mce_banks);
e9b11c17 5411 kvm_free_lapic(vcpu);
f656ce01 5412 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5413 kvm_mmu_destroy(vcpu);
f656ce01 5414 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5415 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5416}
d19a9cd2
ZX		 5417
5418struct kvm *kvm_arch_create_vm(void)
5419{
5420 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5421
5422 if (!kvm)
5423 return ERR_PTR(-ENOMEM);
5424
f05e70ac 5425 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5426 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5427
5550af4d
SY		 5428 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5429 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5430
53f658b3
MT		 5431 rdtscll(kvm->arch.vm_init_tsc);
5432
d19a9cd2
ZX		 5433 return kvm;
5434}
5435
5436static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5437{
5438 vcpu_load(vcpu);
5439 kvm_mmu_unload(vcpu);
5440 vcpu_put(vcpu);
5441}
5442
5443static void kvm_free_vcpus(struct kvm *kvm)
5444{
5445 unsigned int i;
988a2cae 5446 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5447
5448 /*
5449 * Unpin any mmu pages first.
5450 */
988a2cae
GN		 5451 kvm_for_each_vcpu(i, vcpu, kvm)
5452 kvm_unload_vcpu_mmu(vcpu);
5453 kvm_for_each_vcpu(i, vcpu, kvm)
5454 kvm_arch_vcpu_free(vcpu);
5455
5456 mutex_lock(&kvm->lock);
5457 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5458 kvm->vcpus[i] = NULL;
d19a9cd2 5459
988a2cae
GN		 5460 atomic_set(&kvm->online_vcpus, 0);
5461 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5462}
5463
ad8ba2cd
SY		 5464void kvm_arch_sync_events(struct kvm *kvm)
5465{
ba4cef31 5466 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5467}
5468
d19a9cd2
ZX		 5469void kvm_arch_destroy_vm(struct kvm *kvm)
5470{
6eb55818 5471 kvm_iommu_unmap_guest(kvm);
7837699f 5472 kvm_free_pit(kvm);
d7deeeb0
ZX		 5473 kfree(kvm->arch.vpic);
5474 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5475 kvm_free_vcpus(kvm);
5476 kvm_free_physmem(kvm);
3d45830c
AK		 5477 if (kvm->arch.apic_access_page)
5478 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5479 if (kvm->arch.ept_identity_pagetable)
5480 put_page(kvm->arch.ept_identity_pagetable);
64749204 5481 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5482 kfree(kvm);
5483}
0de10343 5484
f7784b8e
MT		 5485int kvm_arch_prepare_memory_region(struct kvm *kvm,
5486 struct kvm_memory_slot *memslot,
0de10343 5487 struct kvm_memory_slot old,
f7784b8e 5488 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5489 int user_alloc)
5490{
f7784b8e 5491 int npages = memslot->npages;
7ac77099
AK		 5492 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5493
5494 /* Prevent internal slot pages from being moved by fork()/COW. */
5495 if (memslot->id >= KVM_MEMORY_SLOTS)
5496 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5497
5498 /*To keep backward compatibility with older userspace,
5499 *x86 needs to hanlde !user_alloc case.
5500 */
5501 if (!user_alloc) {
5502 if (npages && !old.rmap) {
604b38ac
AA		 5503 unsigned long userspace_addr;
5504
72dc67a6 5505 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5506 userspace_addr = do_mmap(NULL, 0,
5507 npages * PAGE_SIZE,
5508 PROT_READ | PROT_WRITE,
7ac77099 5509 map_flags,
604b38ac 5510 0);
72dc67a6 5511 up_write(&current->mm->mmap_sem);
0de10343 5512
604b38ac
AA		 5513 if (IS_ERR((void *)userspace_addr))
5514 return PTR_ERR((void *)userspace_addr);
5515
604b38ac 5516 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5517 }
5518 }
5519
f7784b8e
MT		 5520
5521 return 0;
5522}
5523
5524void kvm_arch_commit_memory_region(struct kvm *kvm,
5525 struct kvm_userspace_memory_region *mem,
5526 struct kvm_memory_slot old,
5527 int user_alloc)
5528{
5529
5530 int npages = mem->memory_size >> PAGE_SHIFT;
5531
5532 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5533 int ret;
5534
5535 down_write(&current->mm->mmap_sem);
5536 ret = do_munmap(current->mm, old.userspace_addr,
5537 old.npages * PAGE_SIZE);
5538 up_write(&current->mm->mmap_sem);
5539 if (ret < 0)
5540 printk(KERN_WARNING
5541 "kvm_vm_ioctl_set_memory_region: "
5542 "failed to munmap memory\n");
5543 }
5544
7c8a83b7 5545 spin_lock(&kvm->mmu_lock);
f05e70ac 5546 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5547 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5548 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5549 }
5550
5551 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5552 spin_unlock(&kvm->mmu_lock);
0de10343 5553}
1d737c8a 5554
34d4cb8f
MT		 5555void kvm_arch_flush_shadow(struct kvm *kvm)
5556{
5557 kvm_mmu_zap_all(kvm);
8986ecc0 5558 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5559}
5560
1d737c8a
ZX		 5561int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5562{
a4535290 5563 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5564 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5565 || vcpu->arch.nmi_pending ||
5566 (kvm_arch_interrupt_allowed(vcpu) &&
5567 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5568}
5736199a 5569
5736199a
ZX		 5570void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5571{
32f88400
MT		 5572 int me;
5573 int cpu = vcpu->cpu;
5736199a
ZX		 5574
5575 if (waitqueue_active(&vcpu->wq)) {
5576 wake_up_interruptible(&vcpu->wq);
5577 ++vcpu->stat.halt_wakeup;
5578 }
32f88400
MT		 5579
5580 me = get_cpu();
5581 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5582 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5583 smp_send_reschedule(cpu);
e9571ed5 5584 put_cpu();
5736199a 5585}
78646121
GN		 5586
5587int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5588{
5589 return kvm_x86_ops->interrupt_allowed(vcpu);
5590}
229456fc 5591
f92653ee
JK		 5592bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5593{
5594 unsigned long current_rip = kvm_rip_read(vcpu) +
5595 get_segment_base(vcpu, VCPU_SREG_CS);
5596
5597 return current_rip == linear_rip;
5598}
5599EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5600
94fe45da
JK		 5601unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5602{
5603 unsigned long rflags;
5604
5605 rflags = kvm_x86_ops->get_rflags(vcpu);
5606 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5607 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5608 return rflags;
5609}
5610EXPORT_SYMBOL_GPL(kvm_get_rflags);
5611
5612void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5613{
5614 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5615 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5616 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5617 kvm_x86_ops->set_rflags(vcpu, rflags);
5618}
5619EXPORT_SYMBOL_GPL(kvm_set_rflags);
5620
229456fc
MT		 5621EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5622EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5623EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5624EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5625EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5626EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5627EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5628EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5629EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5630EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5631EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5632EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git