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f453ba04 DA |
1 | /* |
2 | * Copyright (c) 2006 Luc Verhaegen (quirks list) | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
61e57a8d | 5 | * Copyright 2010 Red Hat, Inc. |
f453ba04 DA |
6 | * |
7 | * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from | |
8 | * FB layer. | |
9 | * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the | |
19 | * next paragraph) shall be included in all copies or substantial portions | |
20 | * of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
27 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | */ | |
30 | #include <linux/kernel.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
10a85120 | 32 | #include <linux/hdmi.h> |
f453ba04 | 33 | #include <linux/i2c.h> |
47819ba2 | 34 | #include <linux/module.h> |
5cb8eaa2 | 35 | #include <linux/vga_switcheroo.h> |
760285e7 DH |
36 | #include <drm/drmP.h> |
37 | #include <drm/drm_edid.h> | |
9338203c | 38 | #include <drm/drm_encoder.h> |
40d9b043 | 39 | #include <drm/drm_displayid.h> |
f453ba04 | 40 | |
13931579 AJ |
41 | #define version_greater(edid, maj, min) \ |
42 | (((edid)->version > (maj)) || \ | |
43 | ((edid)->version == (maj) && (edid)->revision > (min))) | |
f453ba04 | 44 | |
d1ff6409 AJ |
45 | #define EDID_EST_TIMINGS 16 |
46 | #define EDID_STD_TIMINGS 8 | |
47 | #define EDID_DETAILED_TIMINGS 4 | |
f453ba04 DA |
48 | |
49 | /* | |
50 | * EDID blocks out in the wild have a variety of bugs, try to collect | |
51 | * them here (note that userspace may work around broken monitors first, | |
52 | * but fixes should make their way here so that the kernel "just works" | |
53 | * on as many displays as possible). | |
54 | */ | |
55 | ||
56 | /* First detailed mode wrong, use largest 60Hz mode */ | |
57 | #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) | |
58 | /* Reported 135MHz pixel clock is too high, needs adjustment */ | |
59 | #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) | |
60 | /* Prefer the largest mode at 75 Hz */ | |
61 | #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) | |
62 | /* Detail timing is in cm not mm */ | |
63 | #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) | |
64 | /* Detailed timing descriptors have bogus size values, so just take the | |
65 | * maximum size and use that. | |
66 | */ | |
67 | #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) | |
68 | /* Monitor forgot to set the first detailed is preferred bit. */ | |
69 | #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) | |
70 | /* use +hsync +vsync for detailed mode */ | |
71 | #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) | |
bc42aabc AJ |
72 | /* Force reduced-blanking timings for detailed modes */ |
73 | #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) | |
49d45a31 RM |
74 | /* Force 8bpc */ |
75 | #define EDID_QUIRK_FORCE_8BPC (1 << 8) | |
bc5b9641 MK |
76 | /* Force 12bpc */ |
77 | #define EDID_QUIRK_FORCE_12BPC (1 << 9) | |
e10aec65 MK |
78 | /* Force 6bpc */ |
79 | #define EDID_QUIRK_FORCE_6BPC (1 << 10) | |
3c537889 | 80 | |
13931579 AJ |
81 | struct detailed_mode_closure { |
82 | struct drm_connector *connector; | |
83 | struct edid *edid; | |
84 | bool preferred; | |
85 | u32 quirks; | |
86 | int modes; | |
87 | }; | |
f453ba04 | 88 | |
5c61259e ZY |
89 | #define LEVEL_DMT 0 |
90 | #define LEVEL_GTF 1 | |
7a374350 AJ |
91 | #define LEVEL_GTF2 2 |
92 | #define LEVEL_CVT 3 | |
5c61259e | 93 | |
23c4cfbd | 94 | static const struct edid_quirk { |
c51a3fd6 | 95 | char vendor[4]; |
f453ba04 DA |
96 | int product_id; |
97 | u32 quirks; | |
98 | } edid_quirk_list[] = { | |
99 | /* Acer AL1706 */ | |
100 | { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, | |
101 | /* Acer F51 */ | |
102 | { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, | |
103 | /* Unknown Acer */ | |
104 | { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
105 | ||
e10aec65 MK |
106 | /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ |
107 | { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, | |
108 | ||
f453ba04 DA |
109 | /* Belinea 10 15 55 */ |
110 | { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, | |
111 | { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, | |
112 | ||
113 | /* Envision Peripherals, Inc. EN-7100e */ | |
114 | { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, | |
ba1163de AJ |
115 | /* Envision EN2028 */ |
116 | { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, | |
f453ba04 DA |
117 | |
118 | /* Funai Electronics PM36B */ | |
119 | { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | | |
120 | EDID_QUIRK_DETAILED_IN_CM }, | |
121 | ||
122 | /* LG Philips LCD LP154W01-A5 */ | |
123 | { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
124 | { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
125 | ||
126 | /* Philips 107p5 CRT */ | |
127 | { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
128 | ||
129 | /* Proview AY765C */ | |
130 | { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
131 | ||
132 | /* Samsung SyncMaster 205BW. Note: irony */ | |
133 | { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, | |
134 | /* Samsung SyncMaster 22[5-6]BW */ | |
135 | { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, | |
136 | { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, | |
bc42aabc | 137 | |
bc5b9641 MK |
138 | /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ |
139 | { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, | |
140 | ||
bc42aabc AJ |
141 | /* ViewSonic VA2026w */ |
142 | { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, | |
118bdbd8 AD |
143 | |
144 | /* Medion MD 30217 PG */ | |
145 | { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, | |
49d45a31 RM |
146 | |
147 | /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ | |
148 | { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, | |
f453ba04 DA |
149 | }; |
150 | ||
a6b21831 TR |
151 | /* |
152 | * Autogenerated from the DMT spec. | |
153 | * This table is copied from xfree86/modes/xf86EdidModes.c. | |
154 | */ | |
155 | static const struct drm_display_mode drm_dmt_modes[] = { | |
24b856b1 | 156 | /* 0x01 - 640x350@85Hz */ |
a6b21831 TR |
157 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, |
158 | 736, 832, 0, 350, 382, 385, 445, 0, | |
159 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 160 | /* 0x02 - 640x400@85Hz */ |
a6b21831 TR |
161 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, |
162 | 736, 832, 0, 400, 401, 404, 445, 0, | |
163 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 164 | /* 0x03 - 720x400@85Hz */ |
a6b21831 TR |
165 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, |
166 | 828, 936, 0, 400, 401, 404, 446, 0, | |
167 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 168 | /* 0x04 - 640x480@60Hz */ |
a6b21831 | 169 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, |
fcf22d05 | 170 | 752, 800, 0, 480, 490, 492, 525, 0, |
a6b21831 | 171 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, |
24b856b1 | 172 | /* 0x05 - 640x480@72Hz */ |
a6b21831 TR |
173 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, |
174 | 704, 832, 0, 480, 489, 492, 520, 0, | |
175 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 176 | /* 0x06 - 640x480@75Hz */ |
a6b21831 TR |
177 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, |
178 | 720, 840, 0, 480, 481, 484, 500, 0, | |
179 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 180 | /* 0x07 - 640x480@85Hz */ |
a6b21831 TR |
181 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, |
182 | 752, 832, 0, 480, 481, 484, 509, 0, | |
183 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 184 | /* 0x08 - 800x600@56Hz */ |
a6b21831 TR |
185 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, |
186 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
187 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 188 | /* 0x09 - 800x600@60Hz */ |
a6b21831 TR |
189 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, |
190 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
191 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 192 | /* 0x0a - 800x600@72Hz */ |
a6b21831 TR |
193 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, |
194 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
195 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 196 | /* 0x0b - 800x600@75Hz */ |
a6b21831 TR |
197 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, |
198 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
199 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 200 | /* 0x0c - 800x600@85Hz */ |
a6b21831 TR |
201 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, |
202 | 896, 1048, 0, 600, 601, 604, 631, 0, | |
203 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 204 | /* 0x0d - 800x600@120Hz RB */ |
a6b21831 TR |
205 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, |
206 | 880, 960, 0, 600, 603, 607, 636, 0, | |
207 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 208 | /* 0x0e - 848x480@60Hz */ |
a6b21831 TR |
209 | { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, |
210 | 976, 1088, 0, 480, 486, 494, 517, 0, | |
211 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 212 | /* 0x0f - 1024x768@43Hz, interlace */ |
a6b21831 | 213 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, |
735b100f | 214 | 1208, 1264, 0, 768, 768, 776, 817, 0, |
a6b21831 | 215 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | |
fcf22d05 | 216 | DRM_MODE_FLAG_INTERLACE) }, |
24b856b1 | 217 | /* 0x10 - 1024x768@60Hz */ |
a6b21831 TR |
218 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, |
219 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
220 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 221 | /* 0x11 - 1024x768@70Hz */ |
a6b21831 TR |
222 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, |
223 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
224 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 225 | /* 0x12 - 1024x768@75Hz */ |
a6b21831 TR |
226 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, |
227 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
228 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 229 | /* 0x13 - 1024x768@85Hz */ |
a6b21831 TR |
230 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, |
231 | 1168, 1376, 0, 768, 769, 772, 808, 0, | |
232 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 233 | /* 0x14 - 1024x768@120Hz RB */ |
a6b21831 TR |
234 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, |
235 | 1104, 1184, 0, 768, 771, 775, 813, 0, | |
236 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 237 | /* 0x15 - 1152x864@75Hz */ |
a6b21831 TR |
238 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, |
239 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
240 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
bfcd74d2 VS |
241 | /* 0x55 - 1280x720@60Hz */ |
242 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, | |
243 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
244 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 245 | /* 0x16 - 1280x768@60Hz RB */ |
a6b21831 TR |
246 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, |
247 | 1360, 1440, 0, 768, 771, 778, 790, 0, | |
248 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 249 | /* 0x17 - 1280x768@60Hz */ |
a6b21831 TR |
250 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, |
251 | 1472, 1664, 0, 768, 771, 778, 798, 0, | |
252 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 253 | /* 0x18 - 1280x768@75Hz */ |
a6b21831 TR |
254 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, |
255 | 1488, 1696, 0, 768, 771, 778, 805, 0, | |
fcf22d05 | 256 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
24b856b1 | 257 | /* 0x19 - 1280x768@85Hz */ |
a6b21831 TR |
258 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, |
259 | 1496, 1712, 0, 768, 771, 778, 809, 0, | |
260 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 261 | /* 0x1a - 1280x768@120Hz RB */ |
a6b21831 TR |
262 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, |
263 | 1360, 1440, 0, 768, 771, 778, 813, 0, | |
264 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 265 | /* 0x1b - 1280x800@60Hz RB */ |
a6b21831 TR |
266 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, |
267 | 1360, 1440, 0, 800, 803, 809, 823, 0, | |
268 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 269 | /* 0x1c - 1280x800@60Hz */ |
a6b21831 TR |
270 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, |
271 | 1480, 1680, 0, 800, 803, 809, 831, 0, | |
fcf22d05 | 272 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
24b856b1 | 273 | /* 0x1d - 1280x800@75Hz */ |
a6b21831 TR |
274 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, |
275 | 1488, 1696, 0, 800, 803, 809, 838, 0, | |
276 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 277 | /* 0x1e - 1280x800@85Hz */ |
a6b21831 TR |
278 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, |
279 | 1496, 1712, 0, 800, 803, 809, 843, 0, | |
280 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 281 | /* 0x1f - 1280x800@120Hz RB */ |
a6b21831 TR |
282 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, |
283 | 1360, 1440, 0, 800, 803, 809, 847, 0, | |
284 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 285 | /* 0x20 - 1280x960@60Hz */ |
a6b21831 TR |
286 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, |
287 | 1488, 1800, 0, 960, 961, 964, 1000, 0, | |
288 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 289 | /* 0x21 - 1280x960@85Hz */ |
a6b21831 TR |
290 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, |
291 | 1504, 1728, 0, 960, 961, 964, 1011, 0, | |
292 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 293 | /* 0x22 - 1280x960@120Hz RB */ |
a6b21831 TR |
294 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, |
295 | 1360, 1440, 0, 960, 963, 967, 1017, 0, | |
296 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 297 | /* 0x23 - 1280x1024@60Hz */ |
a6b21831 TR |
298 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, |
299 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
300 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 301 | /* 0x24 - 1280x1024@75Hz */ |
a6b21831 TR |
302 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, |
303 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
304 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 305 | /* 0x25 - 1280x1024@85Hz */ |
a6b21831 TR |
306 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, |
307 | 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, | |
308 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 309 | /* 0x26 - 1280x1024@120Hz RB */ |
a6b21831 TR |
310 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, |
311 | 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, | |
312 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 313 | /* 0x27 - 1360x768@60Hz */ |
a6b21831 TR |
314 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, |
315 | 1536, 1792, 0, 768, 771, 777, 795, 0, | |
316 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 317 | /* 0x28 - 1360x768@120Hz RB */ |
a6b21831 TR |
318 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, |
319 | 1440, 1520, 0, 768, 771, 776, 813, 0, | |
320 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
321 | /* 0x51 - 1366x768@60Hz */ |
322 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, | |
323 | 1579, 1792, 0, 768, 771, 774, 798, 0, | |
324 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
325 | /* 0x56 - 1366x768@60Hz */ | |
326 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, | |
327 | 1436, 1500, 0, 768, 769, 772, 800, 0, | |
328 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 329 | /* 0x29 - 1400x1050@60Hz RB */ |
a6b21831 TR |
330 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, |
331 | 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, | |
332 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 333 | /* 0x2a - 1400x1050@60Hz */ |
a6b21831 TR |
334 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, |
335 | 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, | |
336 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 337 | /* 0x2b - 1400x1050@75Hz */ |
a6b21831 TR |
338 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, |
339 | 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, | |
340 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 341 | /* 0x2c - 1400x1050@85Hz */ |
a6b21831 TR |
342 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, |
343 | 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, | |
344 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 345 | /* 0x2d - 1400x1050@120Hz RB */ |
a6b21831 TR |
346 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, |
347 | 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, | |
348 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 349 | /* 0x2e - 1440x900@60Hz RB */ |
a6b21831 TR |
350 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, |
351 | 1520, 1600, 0, 900, 903, 909, 926, 0, | |
352 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 353 | /* 0x2f - 1440x900@60Hz */ |
a6b21831 TR |
354 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, |
355 | 1672, 1904, 0, 900, 903, 909, 934, 0, | |
356 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 357 | /* 0x30 - 1440x900@75Hz */ |
a6b21831 TR |
358 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, |
359 | 1688, 1936, 0, 900, 903, 909, 942, 0, | |
360 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 361 | /* 0x31 - 1440x900@85Hz */ |
a6b21831 TR |
362 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, |
363 | 1696, 1952, 0, 900, 903, 909, 948, 0, | |
364 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 365 | /* 0x32 - 1440x900@120Hz RB */ |
a6b21831 TR |
366 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, |
367 | 1520, 1600, 0, 900, 903, 909, 953, 0, | |
368 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
369 | /* 0x53 - 1600x900@60Hz */ |
370 | { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, | |
371 | 1704, 1800, 0, 900, 901, 904, 1000, 0, | |
372 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 373 | /* 0x33 - 1600x1200@60Hz */ |
a6b21831 TR |
374 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, |
375 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
376 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 377 | /* 0x34 - 1600x1200@65Hz */ |
a6b21831 TR |
378 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, |
379 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
380 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 381 | /* 0x35 - 1600x1200@70Hz */ |
a6b21831 TR |
382 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, |
383 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
384 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 385 | /* 0x36 - 1600x1200@75Hz */ |
a6b21831 TR |
386 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, |
387 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
388 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 389 | /* 0x37 - 1600x1200@85Hz */ |
a6b21831 TR |
390 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, |
391 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
392 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 393 | /* 0x38 - 1600x1200@120Hz RB */ |
a6b21831 TR |
394 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, |
395 | 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, | |
396 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 397 | /* 0x39 - 1680x1050@60Hz RB */ |
a6b21831 TR |
398 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, |
399 | 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, | |
400 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 401 | /* 0x3a - 1680x1050@60Hz */ |
a6b21831 TR |
402 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, |
403 | 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, | |
404 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 405 | /* 0x3b - 1680x1050@75Hz */ |
a6b21831 TR |
406 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, |
407 | 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, | |
408 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 409 | /* 0x3c - 1680x1050@85Hz */ |
a6b21831 TR |
410 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, |
411 | 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, | |
412 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 413 | /* 0x3d - 1680x1050@120Hz RB */ |
a6b21831 TR |
414 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, |
415 | 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, | |
416 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 417 | /* 0x3e - 1792x1344@60Hz */ |
a6b21831 TR |
418 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, |
419 | 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, | |
420 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 421 | /* 0x3f - 1792x1344@75Hz */ |
a6b21831 TR |
422 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, |
423 | 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, | |
424 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 425 | /* 0x40 - 1792x1344@120Hz RB */ |
a6b21831 TR |
426 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, |
427 | 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, | |
428 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 429 | /* 0x41 - 1856x1392@60Hz */ |
a6b21831 TR |
430 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, |
431 | 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, | |
432 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 433 | /* 0x42 - 1856x1392@75Hz */ |
a6b21831 | 434 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, |
fcf22d05 | 435 | 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, |
a6b21831 | 436 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
24b856b1 | 437 | /* 0x43 - 1856x1392@120Hz RB */ |
a6b21831 TR |
438 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, |
439 | 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, | |
440 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
441 | /* 0x52 - 1920x1080@60Hz */ |
442 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
443 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
444 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 445 | /* 0x44 - 1920x1200@60Hz RB */ |
a6b21831 TR |
446 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, |
447 | 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, | |
448 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 449 | /* 0x45 - 1920x1200@60Hz */ |
a6b21831 TR |
450 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, |
451 | 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, | |
452 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 453 | /* 0x46 - 1920x1200@75Hz */ |
a6b21831 TR |
454 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, |
455 | 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, | |
456 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 457 | /* 0x47 - 1920x1200@85Hz */ |
a6b21831 TR |
458 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, |
459 | 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, | |
460 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 461 | /* 0x48 - 1920x1200@120Hz RB */ |
a6b21831 TR |
462 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, |
463 | 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, | |
464 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 465 | /* 0x49 - 1920x1440@60Hz */ |
a6b21831 TR |
466 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, |
467 | 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, | |
468 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 469 | /* 0x4a - 1920x1440@75Hz */ |
a6b21831 TR |
470 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, |
471 | 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, | |
472 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 473 | /* 0x4b - 1920x1440@120Hz RB */ |
a6b21831 TR |
474 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, |
475 | 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, | |
476 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
477 | /* 0x54 - 2048x1152@60Hz */ |
478 | { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, | |
479 | 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, | |
480 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 481 | /* 0x4c - 2560x1600@60Hz RB */ |
a6b21831 TR |
482 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, |
483 | 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, | |
484 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 485 | /* 0x4d - 2560x1600@60Hz */ |
a6b21831 TR |
486 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, |
487 | 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, | |
488 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 489 | /* 0x4e - 2560x1600@75Hz */ |
a6b21831 TR |
490 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, |
491 | 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, | |
492 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 493 | /* 0x4f - 2560x1600@85Hz */ |
a6b21831 TR |
494 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, |
495 | 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, | |
496 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 497 | /* 0x50 - 2560x1600@120Hz RB */ |
a6b21831 TR |
498 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, |
499 | 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, | |
500 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
501 | /* 0x57 - 4096x2160@60Hz RB */ |
502 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, | |
503 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, | |
504 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
505 | /* 0x58 - 4096x2160@59.94Hz RB */ | |
506 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, | |
507 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, | |
508 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
a6b21831 TR |
509 | }; |
510 | ||
e7bfa5c4 VS |
511 | /* |
512 | * These more or less come from the DMT spec. The 720x400 modes are | |
513 | * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 | |
514 | * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode | |
515 | * should be 1152x870, again for the Mac, but instead we use the x864 DMT | |
516 | * mode. | |
517 | * | |
518 | * The DMT modes have been fact-checked; the rest are mild guesses. | |
519 | */ | |
a6b21831 TR |
520 | static const struct drm_display_mode edid_est_modes[] = { |
521 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
522 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
523 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ | |
524 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
525 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
526 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ | |
527 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
528 | 720, 840, 0, 480, 481, 484, 500, 0, | |
529 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ | |
530 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
87707cfd | 531 | 704, 832, 0, 480, 489, 492, 520, 0, |
a6b21831 TR |
532 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ |
533 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, | |
534 | 768, 864, 0, 480, 483, 486, 525, 0, | |
535 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ | |
87707cfd | 536 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, |
a6b21831 TR |
537 | 752, 800, 0, 480, 490, 492, 525, 0, |
538 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ | |
539 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, | |
540 | 846, 900, 0, 400, 421, 423, 449, 0, | |
541 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ | |
542 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, | |
543 | 846, 900, 0, 400, 412, 414, 449, 0, | |
544 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ | |
545 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
546 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
547 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ | |
87707cfd | 548 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, |
a6b21831 TR |
549 | 1136, 1312, 0, 768, 769, 772, 800, 0, |
550 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ | |
551 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
552 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
553 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ | |
554 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
555 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
556 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ | |
557 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, | |
558 | 1208, 1264, 0, 768, 768, 776, 817, 0, | |
559 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ | |
560 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, | |
561 | 928, 1152, 0, 624, 625, 628, 667, 0, | |
562 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ | |
563 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
564 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
565 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ | |
566 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
567 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
568 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ | |
569 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
570 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
571 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ | |
572 | }; | |
573 | ||
574 | struct minimode { | |
575 | short w; | |
576 | short h; | |
577 | short r; | |
578 | short rb; | |
579 | }; | |
580 | ||
581 | static const struct minimode est3_modes[] = { | |
582 | /* byte 6 */ | |
583 | { 640, 350, 85, 0 }, | |
584 | { 640, 400, 85, 0 }, | |
585 | { 720, 400, 85, 0 }, | |
586 | { 640, 480, 85, 0 }, | |
587 | { 848, 480, 60, 0 }, | |
588 | { 800, 600, 85, 0 }, | |
589 | { 1024, 768, 85, 0 }, | |
590 | { 1152, 864, 75, 0 }, | |
591 | /* byte 7 */ | |
592 | { 1280, 768, 60, 1 }, | |
593 | { 1280, 768, 60, 0 }, | |
594 | { 1280, 768, 75, 0 }, | |
595 | { 1280, 768, 85, 0 }, | |
596 | { 1280, 960, 60, 0 }, | |
597 | { 1280, 960, 85, 0 }, | |
598 | { 1280, 1024, 60, 0 }, | |
599 | { 1280, 1024, 85, 0 }, | |
600 | /* byte 8 */ | |
601 | { 1360, 768, 60, 0 }, | |
602 | { 1440, 900, 60, 1 }, | |
603 | { 1440, 900, 60, 0 }, | |
604 | { 1440, 900, 75, 0 }, | |
605 | { 1440, 900, 85, 0 }, | |
606 | { 1400, 1050, 60, 1 }, | |
607 | { 1400, 1050, 60, 0 }, | |
608 | { 1400, 1050, 75, 0 }, | |
609 | /* byte 9 */ | |
610 | { 1400, 1050, 85, 0 }, | |
611 | { 1680, 1050, 60, 1 }, | |
612 | { 1680, 1050, 60, 0 }, | |
613 | { 1680, 1050, 75, 0 }, | |
614 | { 1680, 1050, 85, 0 }, | |
615 | { 1600, 1200, 60, 0 }, | |
616 | { 1600, 1200, 65, 0 }, | |
617 | { 1600, 1200, 70, 0 }, | |
618 | /* byte 10 */ | |
619 | { 1600, 1200, 75, 0 }, | |
620 | { 1600, 1200, 85, 0 }, | |
621 | { 1792, 1344, 60, 0 }, | |
c068b32a | 622 | { 1792, 1344, 75, 0 }, |
a6b21831 TR |
623 | { 1856, 1392, 60, 0 }, |
624 | { 1856, 1392, 75, 0 }, | |
625 | { 1920, 1200, 60, 1 }, | |
626 | { 1920, 1200, 60, 0 }, | |
627 | /* byte 11 */ | |
628 | { 1920, 1200, 75, 0 }, | |
629 | { 1920, 1200, 85, 0 }, | |
630 | { 1920, 1440, 60, 0 }, | |
631 | { 1920, 1440, 75, 0 }, | |
632 | }; | |
633 | ||
634 | static const struct minimode extra_modes[] = { | |
635 | { 1024, 576, 60, 0 }, | |
636 | { 1366, 768, 60, 0 }, | |
637 | { 1600, 900, 60, 0 }, | |
638 | { 1680, 945, 60, 0 }, | |
639 | { 1920, 1080, 60, 0 }, | |
640 | { 2048, 1152, 60, 0 }, | |
641 | { 2048, 1536, 60, 0 }, | |
642 | }; | |
643 | ||
644 | /* | |
645 | * Probably taken from CEA-861 spec. | |
646 | * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. | |
d9278b4c JN |
647 | * |
648 | * Index using the VIC. | |
a6b21831 TR |
649 | */ |
650 | static const struct drm_display_mode edid_cea_modes[] = { | |
d9278b4c JN |
651 | /* 0 - dummy, VICs start at 1 */ |
652 | { }, | |
a6b21831 TR |
653 | /* 1 - 640x480@60Hz */ |
654 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, | |
655 | 752, 800, 0, 480, 490, 492, 525, 0, | |
ee7925bb | 656 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 657 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
658 | /* 2 - 720x480@60Hz */ |
659 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, | |
660 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 661 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 662 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
663 | /* 3 - 720x480@60Hz */ |
664 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, | |
665 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 666 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 667 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
668 | /* 4 - 1280x720@60Hz */ |
669 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, | |
670 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 671 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 672 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
673 | /* 5 - 1920x1080i@60Hz */ |
674 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, | |
675 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
676 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 677 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 678 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
679 | /* 6 - 720(1440)x480i@60Hz */ |
680 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, | |
681 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 682 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 683 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 684 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
685 | /* 7 - 720(1440)x480i@60Hz */ |
686 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, | |
687 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 688 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 689 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 690 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
691 | /* 8 - 720(1440)x240@60Hz */ |
692 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, | |
693 | 801, 858, 0, 240, 244, 247, 262, 0, | |
a6b21831 | 694 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 695 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 696 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
697 | /* 9 - 720(1440)x240@60Hz */ |
698 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, | |
699 | 801, 858, 0, 240, 244, 247, 262, 0, | |
a6b21831 | 700 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 701 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 702 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
703 | /* 10 - 2880x480i@60Hz */ |
704 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
705 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
706 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 707 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 708 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
709 | /* 11 - 2880x480i@60Hz */ |
710 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
711 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
712 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 713 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 714 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
715 | /* 12 - 2880x240@60Hz */ |
716 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
717 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb | 718 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 719 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
720 | /* 13 - 2880x240@60Hz */ |
721 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
722 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb | 723 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 724 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
725 | /* 14 - 1440x480@60Hz */ |
726 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, | |
727 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 728 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 729 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
730 | /* 15 - 1440x480@60Hz */ |
731 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, | |
732 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 733 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 734 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
735 | /* 16 - 1920x1080@60Hz */ |
736 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
737 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 738 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 739 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
740 | /* 17 - 720x576@50Hz */ |
741 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
742 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 743 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 744 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
745 | /* 18 - 720x576@50Hz */ |
746 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
747 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 748 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 749 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
750 | /* 19 - 1280x720@50Hz */ |
751 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, | |
752 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 753 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 754 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
755 | /* 20 - 1920x1080i@50Hz */ |
756 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, | |
757 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
758 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 759 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 760 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
761 | /* 21 - 720(1440)x576i@50Hz */ |
762 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, | |
763 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 764 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 765 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 766 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
767 | /* 22 - 720(1440)x576i@50Hz */ |
768 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, | |
769 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 770 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 771 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 772 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
773 | /* 23 - 720(1440)x288@50Hz */ |
774 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, | |
775 | 795, 864, 0, 288, 290, 293, 312, 0, | |
a6b21831 | 776 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 777 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 778 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
779 | /* 24 - 720(1440)x288@50Hz */ |
780 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, | |
781 | 795, 864, 0, 288, 290, 293, 312, 0, | |
a6b21831 | 782 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 783 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 784 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
785 | /* 25 - 2880x576i@50Hz */ |
786 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
787 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
788 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 789 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 790 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
791 | /* 26 - 2880x576i@50Hz */ |
792 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
793 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
794 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 795 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 796 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
797 | /* 27 - 2880x288@50Hz */ |
798 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
799 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb | 800 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 801 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
802 | /* 28 - 2880x288@50Hz */ |
803 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
804 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb | 805 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 806 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
807 | /* 29 - 1440x576@50Hz */ |
808 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
809 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 810 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 811 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
812 | /* 30 - 1440x576@50Hz */ |
813 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
814 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 815 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 816 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
817 | /* 31 - 1920x1080@50Hz */ |
818 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, | |
819 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 820 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 821 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
822 | /* 32 - 1920x1080@24Hz */ |
823 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, | |
824 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 825 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 826 | .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
827 | /* 33 - 1920x1080@25Hz */ |
828 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, | |
829 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 830 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 831 | .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
832 | /* 34 - 1920x1080@30Hz */ |
833 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, | |
834 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 835 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 836 | .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
837 | /* 35 - 2880x480@60Hz */ |
838 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, | |
839 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 840 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 841 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
842 | /* 36 - 2880x480@60Hz */ |
843 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, | |
844 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 845 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 846 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
847 | /* 37 - 2880x576@50Hz */ |
848 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, | |
849 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 850 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 851 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
852 | /* 38 - 2880x576@50Hz */ |
853 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, | |
854 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 855 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 856 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
857 | /* 39 - 1920x1080i@50Hz */ |
858 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, | |
859 | 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, | |
860 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 861 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 862 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
863 | /* 40 - 1920x1080i@100Hz */ |
864 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, | |
865 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
866 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 867 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 868 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
869 | /* 41 - 1280x720@100Hz */ |
870 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, | |
871 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 872 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 873 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
874 | /* 42 - 720x576@100Hz */ |
875 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
876 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 877 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 878 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
879 | /* 43 - 720x576@100Hz */ |
880 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
881 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 882 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 883 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
884 | /* 44 - 720(1440)x576i@100Hz */ |
885 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
886 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 887 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
5a11f7f8 | 888 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 889 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
890 | /* 45 - 720(1440)x576i@100Hz */ |
891 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
892 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 893 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
5a11f7f8 | 894 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 895 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
896 | /* 46 - 1920x1080i@120Hz */ |
897 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
898 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
899 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 900 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 901 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
902 | /* 47 - 1280x720@120Hz */ |
903 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, | |
904 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 905 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 906 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
907 | /* 48 - 720x480@120Hz */ |
908 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, | |
909 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 910 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 911 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
912 | /* 49 - 720x480@120Hz */ |
913 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, | |
914 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 915 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 916 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
917 | /* 50 - 720(1440)x480i@120Hz */ |
918 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, | |
919 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 920 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 921 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 922 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
923 | /* 51 - 720(1440)x480i@120Hz */ |
924 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, | |
925 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 926 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 927 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 928 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
929 | /* 52 - 720x576@200Hz */ |
930 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, | |
931 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 932 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 933 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
934 | /* 53 - 720x576@200Hz */ |
935 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, | |
936 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 937 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 938 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
939 | /* 54 - 720(1440)x576i@200Hz */ |
940 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
941 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 942 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 943 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 944 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
945 | /* 55 - 720(1440)x576i@200Hz */ |
946 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
947 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 948 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 949 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 950 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
951 | /* 56 - 720x480@240Hz */ |
952 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, | |
953 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 954 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 955 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
956 | /* 57 - 720x480@240Hz */ |
957 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, | |
958 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 959 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 960 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
e587803c | 961 | /* 58 - 720(1440)x480i@240Hz */ |
fb01d280 CT |
962 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, |
963 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 964 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 965 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 966 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
e587803c | 967 | /* 59 - 720(1440)x480i@240Hz */ |
fb01d280 CT |
968 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, |
969 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 970 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 971 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 972 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
973 | /* 60 - 1280x720@24Hz */ |
974 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, | |
975 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 976 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 977 | .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
978 | /* 61 - 1280x720@25Hz */ |
979 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, | |
980 | 3740, 3960, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 981 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 982 | .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
983 | /* 62 - 1280x720@30Hz */ |
984 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, | |
985 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 986 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 987 | .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
988 | /* 63 - 1920x1080@120Hz */ |
989 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, | |
990 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 991 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 992 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
993 | /* 64 - 1920x1080@100Hz */ |
994 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, | |
8f0e4907 | 995 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, |
ee7925bb | 996 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 997 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
998 | }; |
999 | ||
7ebe1963 | 1000 | /* |
d9278b4c | 1001 | * HDMI 1.4 4k modes. Index using the VIC. |
7ebe1963 LD |
1002 | */ |
1003 | static const struct drm_display_mode edid_4k_modes[] = { | |
d9278b4c JN |
1004 | /* 0 - dummy, VICs start at 1 */ |
1005 | { }, | |
7ebe1963 LD |
1006 | /* 1 - 3840x2160@30Hz */ |
1007 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1008 | 3840, 4016, 4104, 4400, 0, | |
1009 | 2160, 2168, 2178, 2250, 0, | |
1010 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
1011 | .vrefresh = 30, }, | |
1012 | /* 2 - 3840x2160@25Hz */ | |
1013 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1014 | 3840, 4896, 4984, 5280, 0, | |
1015 | 2160, 2168, 2178, 2250, 0, | |
1016 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
1017 | .vrefresh = 25, }, | |
1018 | /* 3 - 3840x2160@24Hz */ | |
1019 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1020 | 3840, 5116, 5204, 5500, 0, | |
1021 | 2160, 2168, 2178, 2250, 0, | |
1022 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
1023 | .vrefresh = 24, }, | |
1024 | /* 4 - 4096x2160@24Hz (SMPTE) */ | |
1025 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1026 | 4096, 5116, 5204, 5500, 0, | |
1027 | 2160, 2168, 2178, 2250, 0, | |
1028 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
1029 | .vrefresh = 24, }, | |
1030 | }; | |
1031 | ||
61e57a8d | 1032 | /*** DDC fetch and block validation ***/ |
f453ba04 | 1033 | |
083ae056 AJ |
1034 | static const u8 edid_header[] = { |
1035 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | |
1036 | }; | |
f453ba04 | 1037 | |
db6cf833 TR |
1038 | /** |
1039 | * drm_edid_header_is_valid - sanity check the header of the base EDID block | |
1040 | * @raw_edid: pointer to raw base EDID block | |
1041 | * | |
1042 | * Sanity check the header of the base EDID block. | |
1043 | * | |
1044 | * Return: 8 if the header is perfect, down to 0 if it's totally wrong. | |
051963d4 TR |
1045 | */ |
1046 | int drm_edid_header_is_valid(const u8 *raw_edid) | |
1047 | { | |
1048 | int i, score = 0; | |
1049 | ||
1050 | for (i = 0; i < sizeof(edid_header); i++) | |
1051 | if (raw_edid[i] == edid_header[i]) | |
1052 | score++; | |
1053 | ||
1054 | return score; | |
1055 | } | |
1056 | EXPORT_SYMBOL(drm_edid_header_is_valid); | |
1057 | ||
47819ba2 AJ |
1058 | static int edid_fixup __read_mostly = 6; |
1059 | module_param_named(edid_fixup, edid_fixup, int, 0400); | |
1060 | MODULE_PARM_DESC(edid_fixup, | |
1061 | "Minimum number of valid EDID header bytes (0-8, default 6)"); | |
051963d4 | 1062 | |
40d9b043 DA |
1063 | static void drm_get_displayid(struct drm_connector *connector, |
1064 | struct edid *edid); | |
da9df2f4 | 1065 | |
c465bbc8 SB |
1066 | static int drm_edid_block_checksum(const u8 *raw_edid) |
1067 | { | |
1068 | int i; | |
1069 | u8 csum = 0; | |
1070 | for (i = 0; i < EDID_LENGTH; i++) | |
1071 | csum += raw_edid[i]; | |
1072 | ||
1073 | return csum; | |
1074 | } | |
1075 | ||
d6885d65 SB |
1076 | static bool drm_edid_is_zero(const u8 *in_edid, int length) |
1077 | { | |
1078 | if (memchr_inv(in_edid, 0, length)) | |
1079 | return false; | |
1080 | ||
1081 | return true; | |
1082 | } | |
1083 | ||
db6cf833 TR |
1084 | /** |
1085 | * drm_edid_block_valid - Sanity check the EDID block (base or extension) | |
1086 | * @raw_edid: pointer to raw EDID block | |
1087 | * @block: type of block to validate (0 for base, extension otherwise) | |
1088 | * @print_bad_edid: if true, dump bad EDID blocks to the console | |
6ba2bd3d | 1089 | * @edid_corrupt: if true, the header or checksum is invalid |
db6cf833 TR |
1090 | * |
1091 | * Validate a base or extension EDID block and optionally dump bad blocks to | |
1092 | * the console. | |
1093 | * | |
1094 | * Return: True if the block is valid, false otherwise. | |
f453ba04 | 1095 | */ |
6ba2bd3d TP |
1096 | bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, |
1097 | bool *edid_corrupt) | |
f453ba04 | 1098 | { |
c465bbc8 | 1099 | u8 csum; |
61e57a8d | 1100 | struct edid *edid = (struct edid *)raw_edid; |
f453ba04 | 1101 | |
fe2ef780 SWK |
1102 | if (WARN_ON(!raw_edid)) |
1103 | return false; | |
1104 | ||
47819ba2 AJ |
1105 | if (edid_fixup > 8 || edid_fixup < 0) |
1106 | edid_fixup = 6; | |
1107 | ||
f89ec8a4 | 1108 | if (block == 0) { |
051963d4 | 1109 | int score = drm_edid_header_is_valid(raw_edid); |
6ba2bd3d TP |
1110 | if (score == 8) { |
1111 | if (edid_corrupt) | |
ac6f2e29 | 1112 | *edid_corrupt = false; |
6ba2bd3d TP |
1113 | } else if (score >= edid_fixup) { |
1114 | /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 | |
1115 | * The corrupt flag needs to be set here otherwise, the | |
1116 | * fix-up code here will correct the problem, the | |
1117 | * checksum is correct and the test fails | |
1118 | */ | |
1119 | if (edid_corrupt) | |
ac6f2e29 | 1120 | *edid_corrupt = true; |
61e57a8d AJ |
1121 | DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); |
1122 | memcpy(raw_edid, edid_header, sizeof(edid_header)); | |
1123 | } else { | |
6ba2bd3d | 1124 | if (edid_corrupt) |
ac6f2e29 | 1125 | *edid_corrupt = true; |
61e57a8d AJ |
1126 | goto bad; |
1127 | } | |
1128 | } | |
f453ba04 | 1129 | |
c465bbc8 | 1130 | csum = drm_edid_block_checksum(raw_edid); |
f453ba04 | 1131 | if (csum) { |
0b2443ed JG |
1132 | if (print_bad_edid) { |
1133 | DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); | |
1134 | } | |
4a638b4e | 1135 | |
6ba2bd3d | 1136 | if (edid_corrupt) |
ac6f2e29 | 1137 | *edid_corrupt = true; |
6ba2bd3d | 1138 | |
4a638b4e AJ |
1139 | /* allow CEA to slide through, switches mangle this */ |
1140 | if (raw_edid[0] != 0x02) | |
1141 | goto bad; | |
f453ba04 DA |
1142 | } |
1143 | ||
61e57a8d AJ |
1144 | /* per-block-type checks */ |
1145 | switch (raw_edid[0]) { | |
1146 | case 0: /* base */ | |
1147 | if (edid->version != 1) { | |
1148 | DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); | |
1149 | goto bad; | |
1150 | } | |
862b89c0 | 1151 | |
61e57a8d AJ |
1152 | if (edid->revision > 4) |
1153 | DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); | |
1154 | break; | |
862b89c0 | 1155 | |
61e57a8d AJ |
1156 | default: |
1157 | break; | |
1158 | } | |
47ee4ccf | 1159 | |
fe2ef780 | 1160 | return true; |
f453ba04 DA |
1161 | |
1162 | bad: | |
fe2ef780 | 1163 | if (print_bad_edid) { |
da4c07b7 SB |
1164 | if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { |
1165 | printk(KERN_ERR "EDID block is all zeroes\n"); | |
1166 | } else { | |
1167 | printk(KERN_ERR "Raw EDID:\n"); | |
1168 | print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, | |
0aff47f2 | 1169 | raw_edid, EDID_LENGTH, false); |
da4c07b7 | 1170 | } |
f453ba04 | 1171 | } |
fe2ef780 | 1172 | return false; |
f453ba04 | 1173 | } |
da0df92b | 1174 | EXPORT_SYMBOL(drm_edid_block_valid); |
61e57a8d AJ |
1175 | |
1176 | /** | |
1177 | * drm_edid_is_valid - sanity check EDID data | |
1178 | * @edid: EDID data | |
1179 | * | |
1180 | * Sanity-check an entire EDID record (including extensions) | |
db6cf833 TR |
1181 | * |
1182 | * Return: True if the EDID data is valid, false otherwise. | |
61e57a8d AJ |
1183 | */ |
1184 | bool drm_edid_is_valid(struct edid *edid) | |
1185 | { | |
1186 | int i; | |
1187 | u8 *raw = (u8 *)edid; | |
1188 | ||
1189 | if (!edid) | |
1190 | return false; | |
1191 | ||
1192 | for (i = 0; i <= edid->extensions; i++) | |
6ba2bd3d | 1193 | if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) |
61e57a8d AJ |
1194 | return false; |
1195 | ||
1196 | return true; | |
1197 | } | |
3c537889 | 1198 | EXPORT_SYMBOL(drm_edid_is_valid); |
f453ba04 | 1199 | |
61e57a8d AJ |
1200 | #define DDC_SEGMENT_ADDR 0x30 |
1201 | /** | |
db6cf833 | 1202 | * drm_do_probe_ddc_edid() - get EDID information via I2C |
7c58e87e | 1203 | * @data: I2C device adapter |
fc66811c DV |
1204 | * @buf: EDID data buffer to be filled |
1205 | * @block: 128 byte EDID block to start fetching from | |
1206 | * @len: EDID data buffer length to fetch | |
1207 | * | |
db6cf833 | 1208 | * Try to fetch EDID information by calling I2C driver functions. |
61e57a8d | 1209 | * |
db6cf833 | 1210 | * Return: 0 on success or -1 on failure. |
61e57a8d AJ |
1211 | */ |
1212 | static int | |
18df89fe | 1213 | drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) |
61e57a8d | 1214 | { |
18df89fe | 1215 | struct i2c_adapter *adapter = data; |
61e57a8d | 1216 | unsigned char start = block * EDID_LENGTH; |
cd004b3f S |
1217 | unsigned char segment = block >> 1; |
1218 | unsigned char xfers = segment ? 3 : 2; | |
4819d2e4 CW |
1219 | int ret, retries = 5; |
1220 | ||
db6cf833 TR |
1221 | /* |
1222 | * The core I2C driver will automatically retry the transfer if the | |
4819d2e4 CW |
1223 | * adapter reports EAGAIN. However, we find that bit-banging transfers |
1224 | * are susceptible to errors under a heavily loaded machine and | |
1225 | * generate spurious NAKs and timeouts. Retrying the transfer | |
1226 | * of the individual block a few times seems to overcome this. | |
1227 | */ | |
1228 | do { | |
1229 | struct i2c_msg msgs[] = { | |
1230 | { | |
cd004b3f S |
1231 | .addr = DDC_SEGMENT_ADDR, |
1232 | .flags = 0, | |
1233 | .len = 1, | |
1234 | .buf = &segment, | |
1235 | }, { | |
4819d2e4 CW |
1236 | .addr = DDC_ADDR, |
1237 | .flags = 0, | |
1238 | .len = 1, | |
1239 | .buf = &start, | |
1240 | }, { | |
1241 | .addr = DDC_ADDR, | |
1242 | .flags = I2C_M_RD, | |
1243 | .len = len, | |
1244 | .buf = buf, | |
1245 | } | |
1246 | }; | |
cd004b3f | 1247 | |
db6cf833 TR |
1248 | /* |
1249 | * Avoid sending the segment addr to not upset non-compliant | |
1250 | * DDC monitors. | |
1251 | */ | |
cd004b3f S |
1252 | ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); |
1253 | ||
9292f37e ED |
1254 | if (ret == -ENXIO) { |
1255 | DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", | |
1256 | adapter->name); | |
1257 | break; | |
1258 | } | |
cd004b3f | 1259 | } while (ret != xfers && --retries); |
4819d2e4 | 1260 | |
cd004b3f | 1261 | return ret == xfers ? 0 : -1; |
61e57a8d AJ |
1262 | } |
1263 | ||
14544d09 CW |
1264 | static void connector_bad_edid(struct drm_connector *connector, |
1265 | u8 *edid, int num_blocks) | |
1266 | { | |
1267 | int i; | |
1268 | ||
1269 | if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) | |
1270 | return; | |
1271 | ||
1272 | dev_warn(connector->dev->dev, | |
1273 | "%s: EDID is invalid:\n", | |
1274 | connector->name); | |
1275 | for (i = 0; i < num_blocks; i++) { | |
1276 | u8 *block = edid + i * EDID_LENGTH; | |
1277 | char prefix[20]; | |
1278 | ||
1279 | if (drm_edid_is_zero(block, EDID_LENGTH)) | |
1280 | sprintf(prefix, "\t[%02x] ZERO ", i); | |
1281 | else if (!drm_edid_block_valid(block, i, false, NULL)) | |
1282 | sprintf(prefix, "\t[%02x] BAD ", i); | |
1283 | else | |
1284 | sprintf(prefix, "\t[%02x] GOOD ", i); | |
1285 | ||
1286 | print_hex_dump(KERN_WARNING, | |
1287 | prefix, DUMP_PREFIX_NONE, 16, 1, | |
1288 | block, EDID_LENGTH, false); | |
1289 | } | |
1290 | } | |
1291 | ||
18df89fe LPC |
1292 | /** |
1293 | * drm_do_get_edid - get EDID data using a custom EDID block read function | |
1294 | * @connector: connector we're probing | |
1295 | * @get_edid_block: EDID block read function | |
1296 | * @data: private data passed to the block read function | |
1297 | * | |
1298 | * When the I2C adapter connected to the DDC bus is hidden behind a device that | |
1299 | * exposes a different interface to read EDID blocks this function can be used | |
1300 | * to get EDID data using a custom block read function. | |
1301 | * | |
1302 | * As in the general case the DDC bus is accessible by the kernel at the I2C | |
1303 | * level, drivers must make all reasonable efforts to expose it as an I2C | |
1304 | * adapter and use drm_get_edid() instead of abusing this function. | |
1305 | * | |
1306 | * Return: Pointer to valid EDID or NULL if we couldn't find any. | |
1307 | */ | |
1308 | struct edid *drm_do_get_edid(struct drm_connector *connector, | |
1309 | int (*get_edid_block)(void *data, u8 *buf, unsigned int block, | |
1310 | size_t len), | |
1311 | void *data) | |
61e57a8d | 1312 | { |
0ea75e23 | 1313 | int i, j = 0, valid_extensions = 0; |
f14f3686 | 1314 | u8 *edid, *new; |
61e57a8d | 1315 | |
f14f3686 | 1316 | if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) |
61e57a8d AJ |
1317 | return NULL; |
1318 | ||
1319 | /* base block fetch */ | |
1320 | for (i = 0; i < 4; i++) { | |
f14f3686 | 1321 | if (get_edid_block(data, edid, 0, EDID_LENGTH)) |
61e57a8d | 1322 | goto out; |
14544d09 | 1323 | if (drm_edid_block_valid(edid, 0, false, |
6ba2bd3d | 1324 | &connector->edid_corrupt)) |
61e57a8d | 1325 | break; |
f14f3686 | 1326 | if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { |
4a9a8b71 DA |
1327 | connector->null_edid_counter++; |
1328 | goto carp; | |
1329 | } | |
61e57a8d AJ |
1330 | } |
1331 | if (i == 4) | |
1332 | goto carp; | |
1333 | ||
1334 | /* if there's no extensions, we're done */ | |
14544d09 CW |
1335 | valid_extensions = edid[0x7e]; |
1336 | if (valid_extensions == 0) | |
f14f3686 | 1337 | return (struct edid *)edid; |
61e57a8d | 1338 | |
14544d09 | 1339 | new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); |
61e57a8d AJ |
1340 | if (!new) |
1341 | goto out; | |
f14f3686 | 1342 | edid = new; |
61e57a8d | 1343 | |
f14f3686 | 1344 | for (j = 1; j <= edid[0x7e]; j++) { |
14544d09 | 1345 | u8 *block = edid + j * EDID_LENGTH; |
a28187cc | 1346 | |
61e57a8d | 1347 | for (i = 0; i < 4; i++) { |
a28187cc | 1348 | if (get_edid_block(data, block, j, EDID_LENGTH)) |
61e57a8d | 1349 | goto out; |
14544d09 | 1350 | if (drm_edid_block_valid(block, j, false, NULL)) |
61e57a8d AJ |
1351 | break; |
1352 | } | |
f934ec8c | 1353 | |
14544d09 CW |
1354 | if (i == 4) |
1355 | valid_extensions--; | |
0ea75e23 ST |
1356 | } |
1357 | ||
f14f3686 | 1358 | if (valid_extensions != edid[0x7e]) { |
14544d09 CW |
1359 | u8 *base; |
1360 | ||
1361 | connector_bad_edid(connector, edid, edid[0x7e] + 1); | |
1362 | ||
f14f3686 CW |
1363 | edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; |
1364 | edid[0x7e] = valid_extensions; | |
14544d09 CW |
1365 | |
1366 | new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
0ea75e23 ST |
1367 | if (!new) |
1368 | goto out; | |
14544d09 CW |
1369 | |
1370 | base = new; | |
1371 | for (i = 0; i <= edid[0x7e]; i++) { | |
1372 | u8 *block = edid + i * EDID_LENGTH; | |
1373 | ||
1374 | if (!drm_edid_block_valid(block, i, false, NULL)) | |
1375 | continue; | |
1376 | ||
1377 | memcpy(base, block, EDID_LENGTH); | |
1378 | base += EDID_LENGTH; | |
1379 | } | |
1380 | ||
1381 | kfree(edid); | |
f14f3686 | 1382 | edid = new; |
61e57a8d AJ |
1383 | } |
1384 | ||
f14f3686 | 1385 | return (struct edid *)edid; |
61e57a8d AJ |
1386 | |
1387 | carp: | |
14544d09 | 1388 | connector_bad_edid(connector, edid, 1); |
61e57a8d | 1389 | out: |
f14f3686 | 1390 | kfree(edid); |
61e57a8d AJ |
1391 | return NULL; |
1392 | } | |
18df89fe | 1393 | EXPORT_SYMBOL_GPL(drm_do_get_edid); |
61e57a8d AJ |
1394 | |
1395 | /** | |
db6cf833 TR |
1396 | * drm_probe_ddc() - probe DDC presence |
1397 | * @adapter: I2C adapter to probe | |
fc66811c | 1398 | * |
db6cf833 | 1399 | * Return: True on success, false on failure. |
61e57a8d | 1400 | */ |
fbff4690 | 1401 | bool |
61e57a8d AJ |
1402 | drm_probe_ddc(struct i2c_adapter *adapter) |
1403 | { | |
1404 | unsigned char out; | |
1405 | ||
1406 | return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); | |
1407 | } | |
fbff4690 | 1408 | EXPORT_SYMBOL(drm_probe_ddc); |
61e57a8d AJ |
1409 | |
1410 | /** | |
1411 | * drm_get_edid - get EDID data, if available | |
1412 | * @connector: connector we're probing | |
db6cf833 | 1413 | * @adapter: I2C adapter to use for DDC |
61e57a8d | 1414 | * |
db6cf833 | 1415 | * Poke the given I2C channel to grab EDID data if possible. If found, |
61e57a8d AJ |
1416 | * attach it to the connector. |
1417 | * | |
db6cf833 | 1418 | * Return: Pointer to valid EDID or NULL if we couldn't find any. |
61e57a8d AJ |
1419 | */ |
1420 | struct edid *drm_get_edid(struct drm_connector *connector, | |
1421 | struct i2c_adapter *adapter) | |
1422 | { | |
40d9b043 DA |
1423 | struct edid *edid; |
1424 | ||
18df89fe LPC |
1425 | if (!drm_probe_ddc(adapter)) |
1426 | return NULL; | |
61e57a8d | 1427 | |
40d9b043 DA |
1428 | edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); |
1429 | if (edid) | |
1430 | drm_get_displayid(connector, edid); | |
1431 | return edid; | |
61e57a8d AJ |
1432 | } |
1433 | EXPORT_SYMBOL(drm_get_edid); | |
1434 | ||
5cb8eaa2 LW |
1435 | /** |
1436 | * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output | |
1437 | * @connector: connector we're probing | |
1438 | * @adapter: I2C adapter to use for DDC | |
1439 | * | |
1440 | * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of | |
1441 | * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily | |
1442 | * switch DDC to the GPU which is retrieving EDID. | |
1443 | * | |
1444 | * Return: Pointer to valid EDID or %NULL if we couldn't find any. | |
1445 | */ | |
1446 | struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, | |
1447 | struct i2c_adapter *adapter) | |
1448 | { | |
1449 | struct pci_dev *pdev = connector->dev->pdev; | |
1450 | struct edid *edid; | |
1451 | ||
1452 | vga_switcheroo_lock_ddc(pdev); | |
1453 | edid = drm_get_edid(connector, adapter); | |
1454 | vga_switcheroo_unlock_ddc(pdev); | |
1455 | ||
1456 | return edid; | |
1457 | } | |
1458 | EXPORT_SYMBOL(drm_get_edid_switcheroo); | |
1459 | ||
51f8da59 JN |
1460 | /** |
1461 | * drm_edid_duplicate - duplicate an EDID and the extensions | |
1462 | * @edid: EDID to duplicate | |
1463 | * | |
db6cf833 | 1464 | * Return: Pointer to duplicated EDID or NULL on allocation failure. |
51f8da59 JN |
1465 | */ |
1466 | struct edid *drm_edid_duplicate(const struct edid *edid) | |
1467 | { | |
1468 | return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
1469 | } | |
1470 | EXPORT_SYMBOL(drm_edid_duplicate); | |
1471 | ||
61e57a8d AJ |
1472 | /*** EDID parsing ***/ |
1473 | ||
f453ba04 DA |
1474 | /** |
1475 | * edid_vendor - match a string against EDID's obfuscated vendor field | |
1476 | * @edid: EDID to match | |
1477 | * @vendor: vendor string | |
1478 | * | |
1479 | * Returns true if @vendor is in @edid, false otherwise | |
1480 | */ | |
23c4cfbd | 1481 | static bool edid_vendor(struct edid *edid, const char *vendor) |
f453ba04 DA |
1482 | { |
1483 | char edid_vendor[3]; | |
1484 | ||
1485 | edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; | |
1486 | edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | | |
1487 | ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; | |
16456c87 | 1488 | edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; |
f453ba04 DA |
1489 | |
1490 | return !strncmp(edid_vendor, vendor, 3); | |
1491 | } | |
1492 | ||
1493 | /** | |
1494 | * edid_get_quirks - return quirk flags for a given EDID | |
1495 | * @edid: EDID to process | |
1496 | * | |
1497 | * This tells subsequent routines what fixes they need to apply. | |
1498 | */ | |
1499 | static u32 edid_get_quirks(struct edid *edid) | |
1500 | { | |
23c4cfbd | 1501 | const struct edid_quirk *quirk; |
f453ba04 DA |
1502 | int i; |
1503 | ||
1504 | for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { | |
1505 | quirk = &edid_quirk_list[i]; | |
1506 | ||
1507 | if (edid_vendor(edid, quirk->vendor) && | |
1508 | (EDID_PRODUCT_ID(edid) == quirk->product_id)) | |
1509 | return quirk->quirks; | |
1510 | } | |
1511 | ||
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) | |
339d202c | 1516 | #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) |
f453ba04 | 1517 | |
f453ba04 DA |
1518 | /** |
1519 | * edid_fixup_preferred - set preferred modes based on quirk list | |
1520 | * @connector: has mode list to fix up | |
1521 | * @quirks: quirks list | |
1522 | * | |
1523 | * Walk the mode list for @connector, clearing the preferred status | |
1524 | * on existing modes and setting it anew for the right mode ala @quirks. | |
1525 | */ | |
1526 | static void edid_fixup_preferred(struct drm_connector *connector, | |
1527 | u32 quirks) | |
1528 | { | |
1529 | struct drm_display_mode *t, *cur_mode, *preferred_mode; | |
f890607b | 1530 | int target_refresh = 0; |
339d202c | 1531 | int cur_vrefresh, preferred_vrefresh; |
f453ba04 DA |
1532 | |
1533 | if (list_empty(&connector->probed_modes)) | |
1534 | return; | |
1535 | ||
1536 | if (quirks & EDID_QUIRK_PREFER_LARGE_60) | |
1537 | target_refresh = 60; | |
1538 | if (quirks & EDID_QUIRK_PREFER_LARGE_75) | |
1539 | target_refresh = 75; | |
1540 | ||
1541 | preferred_mode = list_first_entry(&connector->probed_modes, | |
1542 | struct drm_display_mode, head); | |
1543 | ||
1544 | list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { | |
1545 | cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
1546 | ||
1547 | if (cur_mode == preferred_mode) | |
1548 | continue; | |
1549 | ||
1550 | /* Largest mode is preferred */ | |
1551 | if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) | |
1552 | preferred_mode = cur_mode; | |
1553 | ||
339d202c AD |
1554 | cur_vrefresh = cur_mode->vrefresh ? |
1555 | cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); | |
1556 | preferred_vrefresh = preferred_mode->vrefresh ? | |
1557 | preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); | |
f453ba04 DA |
1558 | /* At a given size, try to get closest to target refresh */ |
1559 | if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && | |
339d202c AD |
1560 | MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < |
1561 | MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { | |
f453ba04 DA |
1562 | preferred_mode = cur_mode; |
1563 | } | |
1564 | } | |
1565 | ||
1566 | preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
1567 | } | |
1568 | ||
f6e252ba AJ |
1569 | static bool |
1570 | mode_is_rb(const struct drm_display_mode *mode) | |
1571 | { | |
1572 | return (mode->htotal - mode->hdisplay == 160) && | |
1573 | (mode->hsync_end - mode->hdisplay == 80) && | |
1574 | (mode->hsync_end - mode->hsync_start == 32) && | |
1575 | (mode->vsync_start - mode->vdisplay == 3); | |
1576 | } | |
1577 | ||
33c7531d AJ |
1578 | /* |
1579 | * drm_mode_find_dmt - Create a copy of a mode if present in DMT | |
1580 | * @dev: Device to duplicate against | |
1581 | * @hsize: Mode width | |
1582 | * @vsize: Mode height | |
1583 | * @fresh: Mode refresh rate | |
f6e252ba | 1584 | * @rb: Mode reduced-blanking-ness |
33c7531d AJ |
1585 | * |
1586 | * Walk the DMT mode list looking for a match for the given parameters. | |
db6cf833 TR |
1587 | * |
1588 | * Return: A newly allocated copy of the mode, or NULL if not found. | |
33c7531d | 1589 | */ |
1d42bbc8 | 1590 | struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, |
f6e252ba AJ |
1591 | int hsize, int vsize, int fresh, |
1592 | bool rb) | |
559ee21d | 1593 | { |
07a5e632 | 1594 | int i; |
559ee21d | 1595 | |
a6b21831 | 1596 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
b1f559ec | 1597 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
f8b46a05 AJ |
1598 | if (hsize != ptr->hdisplay) |
1599 | continue; | |
1600 | if (vsize != ptr->vdisplay) | |
1601 | continue; | |
1602 | if (fresh != drm_mode_vrefresh(ptr)) | |
1603 | continue; | |
f6e252ba AJ |
1604 | if (rb != mode_is_rb(ptr)) |
1605 | continue; | |
f8b46a05 AJ |
1606 | |
1607 | return drm_mode_duplicate(dev, ptr); | |
559ee21d | 1608 | } |
f8b46a05 AJ |
1609 | |
1610 | return NULL; | |
559ee21d | 1611 | } |
1d42bbc8 | 1612 | EXPORT_SYMBOL(drm_mode_find_dmt); |
23425cae | 1613 | |
d1ff6409 AJ |
1614 | typedef void detailed_cb(struct detailed_timing *timing, void *closure); |
1615 | ||
4d76a221 AJ |
1616 | static void |
1617 | cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | |
1618 | { | |
1619 | int i, n = 0; | |
4966b2a9 | 1620 | u8 d = ext[0x02]; |
4d76a221 AJ |
1621 | u8 *det_base = ext + d; |
1622 | ||
4966b2a9 | 1623 | n = (127 - d) / 18; |
4d76a221 AJ |
1624 | for (i = 0; i < n; i++) |
1625 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | |
1626 | } | |
1627 | ||
cbba98f8 AJ |
1628 | static void |
1629 | vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | |
1630 | { | |
1631 | unsigned int i, n = min((int)ext[0x02], 6); | |
1632 | u8 *det_base = ext + 5; | |
1633 | ||
1634 | if (ext[0x01] != 1) | |
1635 | return; /* unknown version */ | |
1636 | ||
1637 | for (i = 0; i < n; i++) | |
1638 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | |
1639 | } | |
1640 | ||
d1ff6409 AJ |
1641 | static void |
1642 | drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) | |
1643 | { | |
1644 | int i; | |
1645 | struct edid *edid = (struct edid *)raw_edid; | |
1646 | ||
1647 | if (edid == NULL) | |
1648 | return; | |
1649 | ||
1650 | for (i = 0; i < EDID_DETAILED_TIMINGS; i++) | |
1651 | cb(&(edid->detailed_timings[i]), closure); | |
1652 | ||
4d76a221 AJ |
1653 | for (i = 1; i <= raw_edid[0x7e]; i++) { |
1654 | u8 *ext = raw_edid + (i * EDID_LENGTH); | |
1655 | switch (*ext) { | |
1656 | case CEA_EXT: | |
1657 | cea_for_each_detailed_block(ext, cb, closure); | |
1658 | break; | |
cbba98f8 AJ |
1659 | case VTB_EXT: |
1660 | vtb_for_each_detailed_block(ext, cb, closure); | |
1661 | break; | |
4d76a221 AJ |
1662 | default: |
1663 | break; | |
1664 | } | |
1665 | } | |
d1ff6409 AJ |
1666 | } |
1667 | ||
1668 | static void | |
1669 | is_rb(struct detailed_timing *t, void *data) | |
1670 | { | |
1671 | u8 *r = (u8 *)t; | |
1672 | if (r[3] == EDID_DETAIL_MONITOR_RANGE) | |
1673 | if (r[15] & 0x10) | |
1674 | *(bool *)data = true; | |
1675 | } | |
1676 | ||
1677 | /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ | |
1678 | static bool | |
1679 | drm_monitor_supports_rb(struct edid *edid) | |
1680 | { | |
1681 | if (edid->revision >= 4) { | |
b196a498 | 1682 | bool ret = false; |
d1ff6409 AJ |
1683 | drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); |
1684 | return ret; | |
1685 | } | |
1686 | ||
1687 | return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); | |
1688 | } | |
1689 | ||
7a374350 AJ |
1690 | static void |
1691 | find_gtf2(struct detailed_timing *t, void *data) | |
1692 | { | |
1693 | u8 *r = (u8 *)t; | |
1694 | if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) | |
1695 | *(u8 **)data = r; | |
1696 | } | |
1697 | ||
1698 | /* Secondary GTF curve kicks in above some break frequency */ | |
1699 | static int | |
1700 | drm_gtf2_hbreak(struct edid *edid) | |
1701 | { | |
1702 | u8 *r = NULL; | |
1703 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1704 | return r ? (r[12] * 2) : 0; | |
1705 | } | |
1706 | ||
1707 | static int | |
1708 | drm_gtf2_2c(struct edid *edid) | |
1709 | { | |
1710 | u8 *r = NULL; | |
1711 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1712 | return r ? r[13] : 0; | |
1713 | } | |
1714 | ||
1715 | static int | |
1716 | drm_gtf2_m(struct edid *edid) | |
1717 | { | |
1718 | u8 *r = NULL; | |
1719 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1720 | return r ? (r[15] << 8) + r[14] : 0; | |
1721 | } | |
1722 | ||
1723 | static int | |
1724 | drm_gtf2_k(struct edid *edid) | |
1725 | { | |
1726 | u8 *r = NULL; | |
1727 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1728 | return r ? r[16] : 0; | |
1729 | } | |
1730 | ||
1731 | static int | |
1732 | drm_gtf2_2j(struct edid *edid) | |
1733 | { | |
1734 | u8 *r = NULL; | |
1735 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1736 | return r ? r[17] : 0; | |
1737 | } | |
1738 | ||
1739 | /** | |
1740 | * standard_timing_level - get std. timing level(CVT/GTF/DMT) | |
1741 | * @edid: EDID block to scan | |
1742 | */ | |
1743 | static int standard_timing_level(struct edid *edid) | |
1744 | { | |
1745 | if (edid->revision >= 2) { | |
1746 | if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) | |
1747 | return LEVEL_CVT; | |
1748 | if (drm_gtf2_hbreak(edid)) | |
1749 | return LEVEL_GTF2; | |
1750 | return LEVEL_GTF; | |
1751 | } | |
1752 | return LEVEL_DMT; | |
1753 | } | |
1754 | ||
23425cae AJ |
1755 | /* |
1756 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | |
1757 | * monitors fill with ascii space (0x20) instead. | |
1758 | */ | |
1759 | static int | |
1760 | bad_std_timing(u8 a, u8 b) | |
1761 | { | |
1762 | return (a == 0x00 && b == 0x00) || | |
1763 | (a == 0x01 && b == 0x01) || | |
1764 | (a == 0x20 && b == 0x20); | |
1765 | } | |
1766 | ||
f453ba04 DA |
1767 | /** |
1768 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode | |
fc66811c DV |
1769 | * @connector: connector of for the EDID block |
1770 | * @edid: EDID block to scan | |
f453ba04 DA |
1771 | * @t: standard timing params |
1772 | * | |
1773 | * Take the standard timing params (in this case width, aspect, and refresh) | |
5c61259e | 1774 | * and convert them into a real mode using CVT/GTF/DMT. |
f453ba04 | 1775 | */ |
7ca6adb3 | 1776 | static struct drm_display_mode * |
7a374350 | 1777 | drm_mode_std(struct drm_connector *connector, struct edid *edid, |
464fdeca | 1778 | struct std_timing *t) |
f453ba04 | 1779 | { |
7ca6adb3 AJ |
1780 | struct drm_device *dev = connector->dev; |
1781 | struct drm_display_mode *m, *mode = NULL; | |
5c61259e ZY |
1782 | int hsize, vsize; |
1783 | int vrefresh_rate; | |
0454beab MD |
1784 | unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) |
1785 | >> EDID_TIMING_ASPECT_SHIFT; | |
5c61259e ZY |
1786 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) |
1787 | >> EDID_TIMING_VFREQ_SHIFT; | |
7a374350 | 1788 | int timing_level = standard_timing_level(edid); |
5c61259e | 1789 | |
23425cae AJ |
1790 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) |
1791 | return NULL; | |
1792 | ||
5c61259e ZY |
1793 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ |
1794 | hsize = t->hsize * 8 + 248; | |
1795 | /* vrefresh_rate = vfreq + 60 */ | |
1796 | vrefresh_rate = vfreq + 60; | |
1797 | /* the vdisplay is calculated based on the aspect ratio */ | |
f066a17d | 1798 | if (aspect_ratio == 0) { |
464fdeca | 1799 | if (edid->revision < 3) |
f066a17d AJ |
1800 | vsize = hsize; |
1801 | else | |
1802 | vsize = (hsize * 10) / 16; | |
1803 | } else if (aspect_ratio == 1) | |
f453ba04 | 1804 | vsize = (hsize * 3) / 4; |
0454beab | 1805 | else if (aspect_ratio == 2) |
f453ba04 DA |
1806 | vsize = (hsize * 4) / 5; |
1807 | else | |
1808 | vsize = (hsize * 9) / 16; | |
a0910c8e AJ |
1809 | |
1810 | /* HDTV hack, part 1 */ | |
1811 | if (vrefresh_rate == 60 && | |
1812 | ((hsize == 1360 && vsize == 765) || | |
1813 | (hsize == 1368 && vsize == 769))) { | |
1814 | hsize = 1366; | |
1815 | vsize = 768; | |
1816 | } | |
1817 | ||
7ca6adb3 AJ |
1818 | /* |
1819 | * If this connector already has a mode for this size and refresh | |
1820 | * rate (because it came from detailed or CVT info), use that | |
1821 | * instead. This way we don't have to guess at interlace or | |
1822 | * reduced blanking. | |
1823 | */ | |
522032da | 1824 | list_for_each_entry(m, &connector->probed_modes, head) |
7ca6adb3 AJ |
1825 | if (m->hdisplay == hsize && m->vdisplay == vsize && |
1826 | drm_mode_vrefresh(m) == vrefresh_rate) | |
1827 | return NULL; | |
1828 | ||
a0910c8e AJ |
1829 | /* HDTV hack, part 2 */ |
1830 | if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { | |
1831 | mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, | |
d50ba256 | 1832 | false); |
559ee21d | 1833 | mode->hdisplay = 1366; |
a4967de6 AJ |
1834 | mode->hsync_start = mode->hsync_start - 1; |
1835 | mode->hsync_end = mode->hsync_end - 1; | |
559ee21d ZY |
1836 | return mode; |
1837 | } | |
a0910c8e | 1838 | |
559ee21d | 1839 | /* check whether it can be found in default mode table */ |
f6e252ba AJ |
1840 | if (drm_monitor_supports_rb(edid)) { |
1841 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, | |
1842 | true); | |
1843 | if (mode) | |
1844 | return mode; | |
1845 | } | |
1846 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); | |
559ee21d ZY |
1847 | if (mode) |
1848 | return mode; | |
1849 | ||
f6e252ba | 1850 | /* okay, generate it */ |
5c61259e ZY |
1851 | switch (timing_level) { |
1852 | case LEVEL_DMT: | |
5c61259e ZY |
1853 | break; |
1854 | case LEVEL_GTF: | |
1855 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
1856 | break; | |
7a374350 AJ |
1857 | case LEVEL_GTF2: |
1858 | /* | |
1859 | * This is potentially wrong if there's ever a monitor with | |
1860 | * more than one ranges section, each claiming a different | |
1861 | * secondary GTF curve. Please don't do that. | |
1862 | */ | |
1863 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
fc48f169 TI |
1864 | if (!mode) |
1865 | return NULL; | |
7a374350 | 1866 | if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { |
aefd330e | 1867 | drm_mode_destroy(dev, mode); |
7a374350 AJ |
1868 | mode = drm_gtf_mode_complex(dev, hsize, vsize, |
1869 | vrefresh_rate, 0, 0, | |
1870 | drm_gtf2_m(edid), | |
1871 | drm_gtf2_2c(edid), | |
1872 | drm_gtf2_k(edid), | |
1873 | drm_gtf2_2j(edid)); | |
1874 | } | |
1875 | break; | |
5c61259e | 1876 | case LEVEL_CVT: |
d50ba256 DA |
1877 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
1878 | false); | |
5c61259e ZY |
1879 | break; |
1880 | } | |
f453ba04 DA |
1881 | return mode; |
1882 | } | |
1883 | ||
b58db2c6 AJ |
1884 | /* |
1885 | * EDID is delightfully ambiguous about how interlaced modes are to be | |
1886 | * encoded. Our internal representation is of frame height, but some | |
1887 | * HDTV detailed timings are encoded as field height. | |
1888 | * | |
1889 | * The format list here is from CEA, in frame size. Technically we | |
1890 | * should be checking refresh rate too. Whatever. | |
1891 | */ | |
1892 | static void | |
1893 | drm_mode_do_interlace_quirk(struct drm_display_mode *mode, | |
1894 | struct detailed_pixel_timing *pt) | |
1895 | { | |
1896 | int i; | |
1897 | static const struct { | |
1898 | int w, h; | |
1899 | } cea_interlaced[] = { | |
1900 | { 1920, 1080 }, | |
1901 | { 720, 480 }, | |
1902 | { 1440, 480 }, | |
1903 | { 2880, 480 }, | |
1904 | { 720, 576 }, | |
1905 | { 1440, 576 }, | |
1906 | { 2880, 576 }, | |
1907 | }; | |
b58db2c6 AJ |
1908 | |
1909 | if (!(pt->misc & DRM_EDID_PT_INTERLACED)) | |
1910 | return; | |
1911 | ||
3c581411 | 1912 | for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { |
b58db2c6 AJ |
1913 | if ((mode->hdisplay == cea_interlaced[i].w) && |
1914 | (mode->vdisplay == cea_interlaced[i].h / 2)) { | |
1915 | mode->vdisplay *= 2; | |
1916 | mode->vsync_start *= 2; | |
1917 | mode->vsync_end *= 2; | |
1918 | mode->vtotal *= 2; | |
1919 | mode->vtotal |= 1; | |
1920 | } | |
1921 | } | |
1922 | ||
1923 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1924 | } | |
1925 | ||
f453ba04 DA |
1926 | /** |
1927 | * drm_mode_detailed - create a new mode from an EDID detailed timing section | |
1928 | * @dev: DRM device (needed to create new mode) | |
1929 | * @edid: EDID block | |
1930 | * @timing: EDID detailed timing info | |
1931 | * @quirks: quirks to apply | |
1932 | * | |
1933 | * An EDID detailed timing block contains enough info for us to create and | |
1934 | * return a new struct drm_display_mode. | |
1935 | */ | |
1936 | static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, | |
1937 | struct edid *edid, | |
1938 | struct detailed_timing *timing, | |
1939 | u32 quirks) | |
1940 | { | |
1941 | struct drm_display_mode *mode; | |
1942 | struct detailed_pixel_timing *pt = &timing->data.pixel_data; | |
0454beab MD |
1943 | unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; |
1944 | unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; | |
1945 | unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; | |
1946 | unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; | |
e14cbee4 MD |
1947 | unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; |
1948 | unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; | |
16dad1d7 | 1949 | unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; |
e14cbee4 | 1950 | unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); |
f453ba04 | 1951 | |
fc438966 | 1952 | /* ignore tiny modes */ |
0454beab | 1953 | if (hactive < 64 || vactive < 64) |
fc438966 AJ |
1954 | return NULL; |
1955 | ||
0454beab | 1956 | if (pt->misc & DRM_EDID_PT_STEREO) { |
c7d015f3 | 1957 | DRM_DEBUG_KMS("stereo mode not supported\n"); |
f453ba04 DA |
1958 | return NULL; |
1959 | } | |
0454beab | 1960 | if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { |
c7d015f3 | 1961 | DRM_DEBUG_KMS("composite sync not supported\n"); |
f453ba04 DA |
1962 | } |
1963 | ||
fcb45611 ZY |
1964 | /* it is incorrect if hsync/vsync width is zero */ |
1965 | if (!hsync_pulse_width || !vsync_pulse_width) { | |
1966 | DRM_DEBUG_KMS("Incorrect Detailed timing. " | |
1967 | "Wrong Hsync/Vsync pulse width\n"); | |
1968 | return NULL; | |
1969 | } | |
bc42aabc AJ |
1970 | |
1971 | if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { | |
1972 | mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); | |
1973 | if (!mode) | |
1974 | return NULL; | |
1975 | ||
1976 | goto set_size; | |
1977 | } | |
1978 | ||
f453ba04 DA |
1979 | mode = drm_mode_create(dev); |
1980 | if (!mode) | |
1981 | return NULL; | |
1982 | ||
f453ba04 | 1983 | if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) |
0454beab MD |
1984 | timing->pixel_clock = cpu_to_le16(1088); |
1985 | ||
1986 | mode->clock = le16_to_cpu(timing->pixel_clock) * 10; | |
1987 | ||
1988 | mode->hdisplay = hactive; | |
1989 | mode->hsync_start = mode->hdisplay + hsync_offset; | |
1990 | mode->hsync_end = mode->hsync_start + hsync_pulse_width; | |
1991 | mode->htotal = mode->hdisplay + hblank; | |
1992 | ||
1993 | mode->vdisplay = vactive; | |
1994 | mode->vsync_start = mode->vdisplay + vsync_offset; | |
1995 | mode->vsync_end = mode->vsync_start + vsync_pulse_width; | |
1996 | mode->vtotal = mode->vdisplay + vblank; | |
f453ba04 | 1997 | |
7064fef5 JB |
1998 | /* Some EDIDs have bogus h/vtotal values */ |
1999 | if (mode->hsync_end > mode->htotal) | |
2000 | mode->htotal = mode->hsync_end + 1; | |
2001 | if (mode->vsync_end > mode->vtotal) | |
2002 | mode->vtotal = mode->vsync_end + 1; | |
2003 | ||
b58db2c6 | 2004 | drm_mode_do_interlace_quirk(mode, pt); |
f453ba04 DA |
2005 | |
2006 | if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { | |
0454beab | 2007 | pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; |
f453ba04 DA |
2008 | } |
2009 | ||
0454beab MD |
2010 | mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? |
2011 | DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
2012 | mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? | |
2013 | DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
f453ba04 | 2014 | |
bc42aabc | 2015 | set_size: |
e14cbee4 MD |
2016 | mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; |
2017 | mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; | |
f453ba04 DA |
2018 | |
2019 | if (quirks & EDID_QUIRK_DETAILED_IN_CM) { | |
2020 | mode->width_mm *= 10; | |
2021 | mode->height_mm *= 10; | |
2022 | } | |
2023 | ||
2024 | if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { | |
2025 | mode->width_mm = edid->width_cm * 10; | |
2026 | mode->height_mm = edid->height_cm * 10; | |
2027 | } | |
2028 | ||
bc42aabc | 2029 | mode->type = DRM_MODE_TYPE_DRIVER; |
c19b3b0f | 2030 | mode->vrefresh = drm_mode_vrefresh(mode); |
bc42aabc AJ |
2031 | drm_mode_set_name(mode); |
2032 | ||
f453ba04 DA |
2033 | return mode; |
2034 | } | |
2035 | ||
b17e52ef | 2036 | static bool |
b1f559ec CW |
2037 | mode_in_hsync_range(const struct drm_display_mode *mode, |
2038 | struct edid *edid, u8 *t) | |
b17e52ef AJ |
2039 | { |
2040 | int hsync, hmin, hmax; | |
2041 | ||
2042 | hmin = t[7]; | |
2043 | if (edid->revision >= 4) | |
2044 | hmin += ((t[4] & 0x04) ? 255 : 0); | |
2045 | hmax = t[8]; | |
2046 | if (edid->revision >= 4) | |
2047 | hmax += ((t[4] & 0x08) ? 255 : 0); | |
07a5e632 | 2048 | hsync = drm_mode_hsync(mode); |
07a5e632 | 2049 | |
b17e52ef AJ |
2050 | return (hsync <= hmax && hsync >= hmin); |
2051 | } | |
2052 | ||
2053 | static bool | |
b1f559ec CW |
2054 | mode_in_vsync_range(const struct drm_display_mode *mode, |
2055 | struct edid *edid, u8 *t) | |
b17e52ef AJ |
2056 | { |
2057 | int vsync, vmin, vmax; | |
2058 | ||
2059 | vmin = t[5]; | |
2060 | if (edid->revision >= 4) | |
2061 | vmin += ((t[4] & 0x01) ? 255 : 0); | |
2062 | vmax = t[6]; | |
2063 | if (edid->revision >= 4) | |
2064 | vmax += ((t[4] & 0x02) ? 255 : 0); | |
2065 | vsync = drm_mode_vrefresh(mode); | |
2066 | ||
2067 | return (vsync <= vmax && vsync >= vmin); | |
2068 | } | |
2069 | ||
2070 | static u32 | |
2071 | range_pixel_clock(struct edid *edid, u8 *t) | |
2072 | { | |
2073 | /* unspecified */ | |
2074 | if (t[9] == 0 || t[9] == 255) | |
2075 | return 0; | |
2076 | ||
2077 | /* 1.4 with CVT support gives us real precision, yay */ | |
2078 | if (edid->revision >= 4 && t[10] == 0x04) | |
2079 | return (t[9] * 10000) - ((t[12] >> 2) * 250); | |
2080 | ||
2081 | /* 1.3 is pathetic, so fuzz up a bit */ | |
2082 | return t[9] * 10000 + 5001; | |
2083 | } | |
2084 | ||
b17e52ef | 2085 | static bool |
b1f559ec | 2086 | mode_in_range(const struct drm_display_mode *mode, struct edid *edid, |
b17e52ef AJ |
2087 | struct detailed_timing *timing) |
2088 | { | |
2089 | u32 max_clock; | |
2090 | u8 *t = (u8 *)timing; | |
2091 | ||
2092 | if (!mode_in_hsync_range(mode, edid, t)) | |
07a5e632 AJ |
2093 | return false; |
2094 | ||
b17e52ef | 2095 | if (!mode_in_vsync_range(mode, edid, t)) |
07a5e632 AJ |
2096 | return false; |
2097 | ||
b17e52ef | 2098 | if ((max_clock = range_pixel_clock(edid, t))) |
07a5e632 AJ |
2099 | if (mode->clock > max_clock) |
2100 | return false; | |
b17e52ef AJ |
2101 | |
2102 | /* 1.4 max horizontal check */ | |
2103 | if (edid->revision >= 4 && t[10] == 0x04) | |
2104 | if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) | |
2105 | return false; | |
2106 | ||
2107 | if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) | |
2108 | return false; | |
07a5e632 AJ |
2109 | |
2110 | return true; | |
2111 | } | |
2112 | ||
7b668ebe TI |
2113 | static bool valid_inferred_mode(const struct drm_connector *connector, |
2114 | const struct drm_display_mode *mode) | |
2115 | { | |
85f8fcd6 | 2116 | const struct drm_display_mode *m; |
7b668ebe TI |
2117 | bool ok = false; |
2118 | ||
2119 | list_for_each_entry(m, &connector->probed_modes, head) { | |
2120 | if (mode->hdisplay == m->hdisplay && | |
2121 | mode->vdisplay == m->vdisplay && | |
2122 | drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) | |
2123 | return false; /* duplicated */ | |
2124 | if (mode->hdisplay <= m->hdisplay && | |
2125 | mode->vdisplay <= m->vdisplay) | |
2126 | ok = true; | |
2127 | } | |
2128 | return ok; | |
2129 | } | |
2130 | ||
b17e52ef | 2131 | static int |
cd4cd3de | 2132 | drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, |
b17e52ef | 2133 | struct detailed_timing *timing) |
07a5e632 AJ |
2134 | { |
2135 | int i, modes = 0; | |
2136 | struct drm_display_mode *newmode; | |
2137 | struct drm_device *dev = connector->dev; | |
2138 | ||
a6b21831 | 2139 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
7b668ebe TI |
2140 | if (mode_in_range(drm_dmt_modes + i, edid, timing) && |
2141 | valid_inferred_mode(connector, drm_dmt_modes + i)) { | |
07a5e632 AJ |
2142 | newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); |
2143 | if (newmode) { | |
2144 | drm_mode_probed_add(connector, newmode); | |
2145 | modes++; | |
2146 | } | |
2147 | } | |
2148 | } | |
2149 | ||
2150 | return modes; | |
2151 | } | |
2152 | ||
c09dedb7 TI |
2153 | /* fix up 1366x768 mode from 1368x768; |
2154 | * GFT/CVT can't express 1366 width which isn't dividable by 8 | |
2155 | */ | |
2156 | static void fixup_mode_1366x768(struct drm_display_mode *mode) | |
2157 | { | |
2158 | if (mode->hdisplay == 1368 && mode->vdisplay == 768) { | |
2159 | mode->hdisplay = 1366; | |
2160 | mode->hsync_start--; | |
2161 | mode->hsync_end--; | |
2162 | drm_mode_set_name(mode); | |
2163 | } | |
2164 | } | |
2165 | ||
b309bd37 AJ |
2166 | static int |
2167 | drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, | |
2168 | struct detailed_timing *timing) | |
2169 | { | |
2170 | int i, modes = 0; | |
2171 | struct drm_display_mode *newmode; | |
2172 | struct drm_device *dev = connector->dev; | |
2173 | ||
a6b21831 | 2174 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 AJ |
2175 | const struct minimode *m = &extra_modes[i]; |
2176 | newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); | |
fc48f169 TI |
2177 | if (!newmode) |
2178 | return modes; | |
b309bd37 | 2179 | |
c09dedb7 | 2180 | fixup_mode_1366x768(newmode); |
7b668ebe TI |
2181 | if (!mode_in_range(newmode, edid, timing) || |
2182 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
2183 | drm_mode_destroy(dev, newmode); |
2184 | continue; | |
2185 | } | |
2186 | ||
2187 | drm_mode_probed_add(connector, newmode); | |
2188 | modes++; | |
2189 | } | |
2190 | ||
2191 | return modes; | |
2192 | } | |
2193 | ||
2194 | static int | |
2195 | drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, | |
2196 | struct detailed_timing *timing) | |
2197 | { | |
2198 | int i, modes = 0; | |
2199 | struct drm_display_mode *newmode; | |
2200 | struct drm_device *dev = connector->dev; | |
2201 | bool rb = drm_monitor_supports_rb(edid); | |
2202 | ||
a6b21831 | 2203 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 AJ |
2204 | const struct minimode *m = &extra_modes[i]; |
2205 | newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); | |
fc48f169 TI |
2206 | if (!newmode) |
2207 | return modes; | |
b309bd37 | 2208 | |
c09dedb7 | 2209 | fixup_mode_1366x768(newmode); |
7b668ebe TI |
2210 | if (!mode_in_range(newmode, edid, timing) || |
2211 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
2212 | drm_mode_destroy(dev, newmode); |
2213 | continue; | |
2214 | } | |
2215 | ||
2216 | drm_mode_probed_add(connector, newmode); | |
2217 | modes++; | |
2218 | } | |
2219 | ||
2220 | return modes; | |
2221 | } | |
2222 | ||
13931579 AJ |
2223 | static void |
2224 | do_inferred_modes(struct detailed_timing *timing, void *c) | |
9340d8cf | 2225 | { |
13931579 AJ |
2226 | struct detailed_mode_closure *closure = c; |
2227 | struct detailed_non_pixel *data = &timing->data.other_data; | |
b309bd37 | 2228 | struct detailed_data_monitor_range *range = &data->data.range; |
9340d8cf | 2229 | |
cb21aafe AJ |
2230 | if (data->type != EDID_DETAIL_MONITOR_RANGE) |
2231 | return; | |
2232 | ||
2233 | closure->modes += drm_dmt_modes_for_range(closure->connector, | |
2234 | closure->edid, | |
2235 | timing); | |
b309bd37 AJ |
2236 | |
2237 | if (!version_greater(closure->edid, 1, 1)) | |
2238 | return; /* GTF not defined yet */ | |
2239 | ||
2240 | switch (range->flags) { | |
2241 | case 0x02: /* secondary gtf, XXX could do more */ | |
2242 | case 0x00: /* default gtf */ | |
2243 | closure->modes += drm_gtf_modes_for_range(closure->connector, | |
2244 | closure->edid, | |
2245 | timing); | |
2246 | break; | |
2247 | case 0x04: /* cvt, only in 1.4+ */ | |
2248 | if (!version_greater(closure->edid, 1, 3)) | |
2249 | break; | |
2250 | ||
2251 | closure->modes += drm_cvt_modes_for_range(closure->connector, | |
2252 | closure->edid, | |
2253 | timing); | |
2254 | break; | |
2255 | case 0x01: /* just the ranges, no formula */ | |
2256 | default: | |
2257 | break; | |
2258 | } | |
13931579 | 2259 | } |
69da3015 | 2260 | |
13931579 AJ |
2261 | static int |
2262 | add_inferred_modes(struct drm_connector *connector, struct edid *edid) | |
2263 | { | |
2264 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
2265 | .connector = connector, |
2266 | .edid = edid, | |
13931579 | 2267 | }; |
9340d8cf | 2268 | |
13931579 AJ |
2269 | if (version_greater(edid, 1, 0)) |
2270 | drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, | |
2271 | &closure); | |
9340d8cf | 2272 | |
13931579 | 2273 | return closure.modes; |
9340d8cf AJ |
2274 | } |
2275 | ||
2255be14 AJ |
2276 | static int |
2277 | drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) | |
2278 | { | |
2279 | int i, j, m, modes = 0; | |
2280 | struct drm_display_mode *mode; | |
f3a32d74 | 2281 | u8 *est = ((u8 *)timing) + 6; |
2255be14 AJ |
2282 | |
2283 | for (i = 0; i < 6; i++) { | |
891a7469 | 2284 | for (j = 7; j >= 0; j--) { |
2255be14 | 2285 | m = (i * 8) + (7 - j); |
3c581411 | 2286 | if (m >= ARRAY_SIZE(est3_modes)) |
2255be14 AJ |
2287 | break; |
2288 | if (est[i] & (1 << j)) { | |
1d42bbc8 DA |
2289 | mode = drm_mode_find_dmt(connector->dev, |
2290 | est3_modes[m].w, | |
2291 | est3_modes[m].h, | |
f6e252ba AJ |
2292 | est3_modes[m].r, |
2293 | est3_modes[m].rb); | |
2255be14 AJ |
2294 | if (mode) { |
2295 | drm_mode_probed_add(connector, mode); | |
2296 | modes++; | |
2297 | } | |
2298 | } | |
2299 | } | |
2300 | } | |
2301 | ||
2302 | return modes; | |
2303 | } | |
2304 | ||
13931579 AJ |
2305 | static void |
2306 | do_established_modes(struct detailed_timing *timing, void *c) | |
9cf00977 | 2307 | { |
13931579 | 2308 | struct detailed_mode_closure *closure = c; |
9cf00977 | 2309 | struct detailed_non_pixel *data = &timing->data.other_data; |
9cf00977 | 2310 | |
13931579 AJ |
2311 | if (data->type == EDID_DETAIL_EST_TIMINGS) |
2312 | closure->modes += drm_est3_modes(closure->connector, timing); | |
2313 | } | |
9cf00977 | 2314 | |
13931579 AJ |
2315 | /** |
2316 | * add_established_modes - get est. modes from EDID and add them | |
db6cf833 | 2317 | * @connector: connector to add mode(s) to |
13931579 AJ |
2318 | * @edid: EDID block to scan |
2319 | * | |
2320 | * Each EDID block contains a bitmap of the supported "established modes" list | |
2321 | * (defined above). Tease them out and add them to the global modes list. | |
2322 | */ | |
2323 | static int | |
2324 | add_established_modes(struct drm_connector *connector, struct edid *edid) | |
2325 | { | |
2326 | struct drm_device *dev = connector->dev; | |
2327 | unsigned long est_bits = edid->established_timings.t1 | | |
2328 | (edid->established_timings.t2 << 8) | | |
2329 | ((edid->established_timings.mfg_rsvd & 0x80) << 9); | |
2330 | int i, modes = 0; | |
2331 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
2332 | .connector = connector, |
2333 | .edid = edid, | |
13931579 | 2334 | }; |
9cf00977 | 2335 | |
13931579 AJ |
2336 | for (i = 0; i <= EDID_EST_TIMINGS; i++) { |
2337 | if (est_bits & (1<<i)) { | |
2338 | struct drm_display_mode *newmode; | |
2339 | newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); | |
2340 | if (newmode) { | |
2341 | drm_mode_probed_add(connector, newmode); | |
2342 | modes++; | |
2343 | } | |
2344 | } | |
9cf00977 AJ |
2345 | } |
2346 | ||
13931579 AJ |
2347 | if (version_greater(edid, 1, 0)) |
2348 | drm_for_each_detailed_block((u8 *)edid, | |
2349 | do_established_modes, &closure); | |
2350 | ||
2351 | return modes + closure.modes; | |
2352 | } | |
2353 | ||
2354 | static void | |
2355 | do_standard_modes(struct detailed_timing *timing, void *c) | |
2356 | { | |
2357 | struct detailed_mode_closure *closure = c; | |
2358 | struct detailed_non_pixel *data = &timing->data.other_data; | |
2359 | struct drm_connector *connector = closure->connector; | |
2360 | struct edid *edid = closure->edid; | |
2361 | ||
2362 | if (data->type == EDID_DETAIL_STD_MODES) { | |
2363 | int i; | |
9cf00977 AJ |
2364 | for (i = 0; i < 6; i++) { |
2365 | struct std_timing *std; | |
2366 | struct drm_display_mode *newmode; | |
2367 | ||
2368 | std = &data->data.timings[i]; | |
464fdeca | 2369 | newmode = drm_mode_std(connector, edid, std); |
9cf00977 AJ |
2370 | if (newmode) { |
2371 | drm_mode_probed_add(connector, newmode); | |
13931579 | 2372 | closure->modes++; |
9cf00977 AJ |
2373 | } |
2374 | } | |
9cf00977 | 2375 | } |
9cf00977 AJ |
2376 | } |
2377 | ||
f453ba04 | 2378 | /** |
13931579 | 2379 | * add_standard_modes - get std. modes from EDID and add them |
db6cf833 | 2380 | * @connector: connector to add mode(s) to |
f453ba04 | 2381 | * @edid: EDID block to scan |
f453ba04 | 2382 | * |
13931579 AJ |
2383 | * Standard modes can be calculated using the appropriate standard (DMT, |
2384 | * GTF or CVT. Grab them from @edid and add them to the list. | |
f453ba04 | 2385 | */ |
13931579 AJ |
2386 | static int |
2387 | add_standard_modes(struct drm_connector *connector, struct edid *edid) | |
f453ba04 | 2388 | { |
9cf00977 | 2389 | int i, modes = 0; |
13931579 | 2390 | struct detailed_mode_closure closure = { |
d456ea2e JL |
2391 | .connector = connector, |
2392 | .edid = edid, | |
13931579 AJ |
2393 | }; |
2394 | ||
2395 | for (i = 0; i < EDID_STD_TIMINGS; i++) { | |
2396 | struct drm_display_mode *newmode; | |
2397 | ||
2398 | newmode = drm_mode_std(connector, edid, | |
464fdeca | 2399 | &edid->standard_timings[i]); |
13931579 AJ |
2400 | if (newmode) { |
2401 | drm_mode_probed_add(connector, newmode); | |
2402 | modes++; | |
2403 | } | |
2404 | } | |
2405 | ||
2406 | if (version_greater(edid, 1, 0)) | |
2407 | drm_for_each_detailed_block((u8 *)edid, do_standard_modes, | |
2408 | &closure); | |
2409 | ||
2410 | /* XXX should also look for standard codes in VTB blocks */ | |
2411 | ||
2412 | return modes + closure.modes; | |
2413 | } | |
f453ba04 | 2414 | |
13931579 AJ |
2415 | static int drm_cvt_modes(struct drm_connector *connector, |
2416 | struct detailed_timing *timing) | |
2417 | { | |
2418 | int i, j, modes = 0; | |
2419 | struct drm_display_mode *newmode; | |
2420 | struct drm_device *dev = connector->dev; | |
2421 | struct cvt_timing *cvt; | |
2422 | const int rates[] = { 60, 85, 75, 60, 50 }; | |
2423 | const u8 empty[3] = { 0, 0, 0 }; | |
a327f6b8 | 2424 | |
13931579 AJ |
2425 | for (i = 0; i < 4; i++) { |
2426 | int uninitialized_var(width), height; | |
2427 | cvt = &(timing->data.other_data.data.cvt[i]); | |
f453ba04 | 2428 | |
13931579 | 2429 | if (!memcmp(cvt->code, empty, 3)) |
9cf00977 | 2430 | continue; |
f453ba04 | 2431 | |
13931579 AJ |
2432 | height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; |
2433 | switch (cvt->code[1] & 0x0c) { | |
2434 | case 0x00: | |
2435 | width = height * 4 / 3; | |
2436 | break; | |
2437 | case 0x04: | |
2438 | width = height * 16 / 9; | |
2439 | break; | |
2440 | case 0x08: | |
2441 | width = height * 16 / 10; | |
2442 | break; | |
2443 | case 0x0c: | |
2444 | width = height * 15 / 9; | |
2445 | break; | |
2446 | } | |
2447 | ||
2448 | for (j = 1; j < 5; j++) { | |
2449 | if (cvt->code[2] & (1 << j)) { | |
2450 | newmode = drm_cvt_mode(dev, width, height, | |
2451 | rates[j], j == 0, | |
2452 | false, false); | |
2453 | if (newmode) { | |
2454 | drm_mode_probed_add(connector, newmode); | |
2455 | modes++; | |
2456 | } | |
2457 | } | |
2458 | } | |
f453ba04 DA |
2459 | } |
2460 | ||
2461 | return modes; | |
2462 | } | |
9cf00977 | 2463 | |
13931579 AJ |
2464 | static void |
2465 | do_cvt_mode(struct detailed_timing *timing, void *c) | |
882f0219 | 2466 | { |
13931579 AJ |
2467 | struct detailed_mode_closure *closure = c; |
2468 | struct detailed_non_pixel *data = &timing->data.other_data; | |
882f0219 | 2469 | |
13931579 AJ |
2470 | if (data->type == EDID_DETAIL_CVT_3BYTE) |
2471 | closure->modes += drm_cvt_modes(closure->connector, timing); | |
2472 | } | |
882f0219 | 2473 | |
13931579 AJ |
2474 | static int |
2475 | add_cvt_modes(struct drm_connector *connector, struct edid *edid) | |
2476 | { | |
2477 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
2478 | .connector = connector, |
2479 | .edid = edid, | |
13931579 | 2480 | }; |
882f0219 | 2481 | |
13931579 AJ |
2482 | if (version_greater(edid, 1, 2)) |
2483 | drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); | |
882f0219 | 2484 | |
13931579 | 2485 | /* XXX should also look for CVT codes in VTB blocks */ |
882f0219 | 2486 | |
13931579 AJ |
2487 | return closure.modes; |
2488 | } | |
2489 | ||
fa3a7340 VS |
2490 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); |
2491 | ||
13931579 AJ |
2492 | static void |
2493 | do_detailed_mode(struct detailed_timing *timing, void *c) | |
2494 | { | |
2495 | struct detailed_mode_closure *closure = c; | |
2496 | struct drm_display_mode *newmode; | |
2497 | ||
2498 | if (timing->pixel_clock) { | |
2499 | newmode = drm_mode_detailed(closure->connector->dev, | |
2500 | closure->edid, timing, | |
2501 | closure->quirks); | |
2502 | if (!newmode) | |
2503 | return; | |
2504 | ||
2505 | if (closure->preferred) | |
2506 | newmode->type |= DRM_MODE_TYPE_PREFERRED; | |
2507 | ||
fa3a7340 VS |
2508 | /* |
2509 | * Detailed modes are limited to 10kHz pixel clock resolution, | |
2510 | * so fix up anything that looks like CEA/HDMI mode, but the clock | |
2511 | * is just slightly off. | |
2512 | */ | |
2513 | fixup_detailed_cea_mode_clock(newmode); | |
2514 | ||
13931579 AJ |
2515 | drm_mode_probed_add(closure->connector, newmode); |
2516 | closure->modes++; | |
2517 | closure->preferred = 0; | |
882f0219 | 2518 | } |
13931579 | 2519 | } |
882f0219 | 2520 | |
13931579 AJ |
2521 | /* |
2522 | * add_detailed_modes - Add modes from detailed timings | |
2523 | * @connector: attached connector | |
2524 | * @edid: EDID block to scan | |
2525 | * @quirks: quirks to apply | |
2526 | */ | |
2527 | static int | |
2528 | add_detailed_modes(struct drm_connector *connector, struct edid *edid, | |
2529 | u32 quirks) | |
2530 | { | |
2531 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
2532 | .connector = connector, |
2533 | .edid = edid, | |
2534 | .preferred = 1, | |
2535 | .quirks = quirks, | |
13931579 AJ |
2536 | }; |
2537 | ||
2538 | if (closure.preferred && !version_greater(edid, 1, 3)) | |
2539 | closure.preferred = | |
2540 | (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); | |
2541 | ||
2542 | drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); | |
2543 | ||
2544 | return closure.modes; | |
882f0219 | 2545 | } |
f453ba04 | 2546 | |
8fe9790d | 2547 | #define AUDIO_BLOCK 0x01 |
54ac76f8 | 2548 | #define VIDEO_BLOCK 0x02 |
f23c20c8 | 2549 | #define VENDOR_BLOCK 0x03 |
76adaa34 | 2550 | #define SPEAKER_BLOCK 0x04 |
b1edd6a6 | 2551 | #define VIDEO_CAPABILITY_BLOCK 0x07 |
8fe9790d | 2552 | #define EDID_BASIC_AUDIO (1 << 6) |
a988bc72 LPC |
2553 | #define EDID_CEA_YCRCB444 (1 << 5) |
2554 | #define EDID_CEA_YCRCB422 (1 << 4) | |
b1edd6a6 | 2555 | #define EDID_CEA_VCDB_QS (1 << 6) |
8fe9790d | 2556 | |
d4e4a31d | 2557 | /* |
8fe9790d | 2558 | * Search EDID for CEA extension block. |
f23c20c8 | 2559 | */ |
40d9b043 | 2560 | static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) |
f23c20c8 | 2561 | { |
8fe9790d ZW |
2562 | u8 *edid_ext = NULL; |
2563 | int i; | |
f23c20c8 ML |
2564 | |
2565 | /* No EDID or EDID extensions */ | |
2566 | if (edid == NULL || edid->extensions == 0) | |
8fe9790d | 2567 | return NULL; |
f23c20c8 | 2568 | |
f23c20c8 | 2569 | /* Find CEA extension */ |
7466f4cc | 2570 | for (i = 0; i < edid->extensions; i++) { |
8fe9790d | 2571 | edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); |
40d9b043 | 2572 | if (edid_ext[0] == ext_id) |
f23c20c8 ML |
2573 | break; |
2574 | } | |
2575 | ||
7466f4cc | 2576 | if (i == edid->extensions) |
8fe9790d ZW |
2577 | return NULL; |
2578 | ||
2579 | return edid_ext; | |
2580 | } | |
2581 | ||
40d9b043 DA |
2582 | static u8 *drm_find_cea_extension(struct edid *edid) |
2583 | { | |
2584 | return drm_find_edid_extension(edid, CEA_EXT); | |
2585 | } | |
2586 | ||
2587 | static u8 *drm_find_displayid_extension(struct edid *edid) | |
2588 | { | |
2589 | return drm_find_edid_extension(edid, DISPLAYID_EXT); | |
2590 | } | |
2591 | ||
e6e79209 VS |
2592 | /* |
2593 | * Calculate the alternate clock for the CEA mode | |
2594 | * (60Hz vs. 59.94Hz etc.) | |
2595 | */ | |
2596 | static unsigned int | |
2597 | cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) | |
2598 | { | |
2599 | unsigned int clock = cea_mode->clock; | |
2600 | ||
2601 | if (cea_mode->vrefresh % 6 != 0) | |
2602 | return clock; | |
2603 | ||
2604 | /* | |
2605 | * edid_cea_modes contains the 59.94Hz | |
2606 | * variant for 240 and 480 line modes, | |
2607 | * and the 60Hz variant otherwise. | |
2608 | */ | |
2609 | if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) | |
9afd808c | 2610 | clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); |
e6e79209 | 2611 | else |
9afd808c | 2612 | clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); |
e6e79209 VS |
2613 | |
2614 | return clock; | |
2615 | } | |
2616 | ||
c45a4e46 VS |
2617 | static bool |
2618 | cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) | |
2619 | { | |
2620 | /* | |
2621 | * For certain VICs the spec allows the vertical | |
2622 | * front porch to vary by one or two lines. | |
2623 | * | |
2624 | * cea_modes[] stores the variant with the shortest | |
2625 | * vertical front porch. We can adjust the mode to | |
2626 | * get the other variants by simply increasing the | |
2627 | * vertical front porch length. | |
2628 | */ | |
2629 | BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || | |
2630 | edid_cea_modes[9].vtotal != 262 || | |
2631 | edid_cea_modes[12].vtotal != 262 || | |
2632 | edid_cea_modes[13].vtotal != 262 || | |
2633 | edid_cea_modes[23].vtotal != 312 || | |
2634 | edid_cea_modes[24].vtotal != 312 || | |
2635 | edid_cea_modes[27].vtotal != 312 || | |
2636 | edid_cea_modes[28].vtotal != 312); | |
2637 | ||
2638 | if (((vic == 8 || vic == 9 || | |
2639 | vic == 12 || vic == 13) && mode->vtotal < 263) || | |
2640 | ((vic == 23 || vic == 24 || | |
2641 | vic == 27 || vic == 28) && mode->vtotal < 314)) { | |
2642 | mode->vsync_start++; | |
2643 | mode->vsync_end++; | |
2644 | mode->vtotal++; | |
2645 | ||
2646 | return true; | |
2647 | } | |
2648 | ||
2649 | return false; | |
2650 | } | |
2651 | ||
4c6bcf44 VS |
2652 | static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, |
2653 | unsigned int clock_tolerance) | |
2654 | { | |
d9278b4c | 2655 | u8 vic; |
4c6bcf44 VS |
2656 | |
2657 | if (!to_match->clock) | |
2658 | return 0; | |
2659 | ||
d9278b4c | 2660 | for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { |
c45a4e46 | 2661 | struct drm_display_mode cea_mode = edid_cea_modes[vic]; |
4c6bcf44 VS |
2662 | unsigned int clock1, clock2; |
2663 | ||
2664 | /* Check both 60Hz and 59.94Hz */ | |
c45a4e46 VS |
2665 | clock1 = cea_mode.clock; |
2666 | clock2 = cea_mode_alternate_clock(&cea_mode); | |
4c6bcf44 VS |
2667 | |
2668 | if (abs(to_match->clock - clock1) > clock_tolerance && | |
2669 | abs(to_match->clock - clock2) > clock_tolerance) | |
2670 | continue; | |
2671 | ||
c45a4e46 VS |
2672 | do { |
2673 | if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode)) | |
2674 | return vic; | |
2675 | } while (cea_mode_alternate_timings(vic, &cea_mode)); | |
4c6bcf44 VS |
2676 | } |
2677 | ||
2678 | return 0; | |
2679 | } | |
2680 | ||
18316c8c TR |
2681 | /** |
2682 | * drm_match_cea_mode - look for a CEA mode matching given mode | |
2683 | * @to_match: display mode | |
2684 | * | |
db6cf833 | 2685 | * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 |
18316c8c | 2686 | * mode. |
a4799037 | 2687 | */ |
18316c8c | 2688 | u8 drm_match_cea_mode(const struct drm_display_mode *to_match) |
a4799037 | 2689 | { |
d9278b4c | 2690 | u8 vic; |
a4799037 | 2691 | |
a90b590e VS |
2692 | if (!to_match->clock) |
2693 | return 0; | |
2694 | ||
d9278b4c | 2695 | for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { |
c45a4e46 | 2696 | struct drm_display_mode cea_mode = edid_cea_modes[vic]; |
a90b590e VS |
2697 | unsigned int clock1, clock2; |
2698 | ||
a90b590e | 2699 | /* Check both 60Hz and 59.94Hz */ |
c45a4e46 VS |
2700 | clock1 = cea_mode.clock; |
2701 | clock2 = cea_mode_alternate_clock(&cea_mode); | |
a4799037 | 2702 | |
c45a4e46 VS |
2703 | if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && |
2704 | KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) | |
2705 | continue; | |
2706 | ||
2707 | do { | |
2708 | if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode)) | |
2709 | return vic; | |
2710 | } while (cea_mode_alternate_timings(vic, &cea_mode)); | |
a4799037 | 2711 | } |
c45a4e46 | 2712 | |
a4799037 SM |
2713 | return 0; |
2714 | } | |
2715 | EXPORT_SYMBOL(drm_match_cea_mode); | |
2716 | ||
d9278b4c JN |
2717 | static bool drm_valid_cea_vic(u8 vic) |
2718 | { | |
2719 | return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); | |
2720 | } | |
2721 | ||
0967e6a5 VK |
2722 | /** |
2723 | * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to | |
2724 | * the input VIC from the CEA mode list | |
2725 | * @video_code: ID given to each of the CEA modes | |
2726 | * | |
2727 | * Returns picture aspect ratio | |
2728 | */ | |
2729 | enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) | |
2730 | { | |
d9278b4c | 2731 | return edid_cea_modes[video_code].picture_aspect_ratio; |
0967e6a5 VK |
2732 | } |
2733 | EXPORT_SYMBOL(drm_get_cea_aspect_ratio); | |
2734 | ||
3f2f6533 LD |
2735 | /* |
2736 | * Calculate the alternate clock for HDMI modes (those from the HDMI vendor | |
2737 | * specific block). | |
2738 | * | |
2739 | * It's almost like cea_mode_alternate_clock(), we just need to add an | |
2740 | * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this | |
2741 | * one. | |
2742 | */ | |
2743 | static unsigned int | |
2744 | hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) | |
2745 | { | |
2746 | if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) | |
2747 | return hdmi_mode->clock; | |
2748 | ||
2749 | return cea_mode_alternate_clock(hdmi_mode); | |
2750 | } | |
2751 | ||
4c6bcf44 VS |
2752 | static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, |
2753 | unsigned int clock_tolerance) | |
2754 | { | |
d9278b4c | 2755 | u8 vic; |
4c6bcf44 VS |
2756 | |
2757 | if (!to_match->clock) | |
2758 | return 0; | |
2759 | ||
d9278b4c JN |
2760 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { |
2761 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | |
4c6bcf44 VS |
2762 | unsigned int clock1, clock2; |
2763 | ||
2764 | /* Make sure to also match alternate clocks */ | |
2765 | clock1 = hdmi_mode->clock; | |
2766 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | |
2767 | ||
2768 | if (abs(to_match->clock - clock1) > clock_tolerance && | |
2769 | abs(to_match->clock - clock2) > clock_tolerance) | |
2770 | continue; | |
2771 | ||
2772 | if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) | |
d9278b4c | 2773 | return vic; |
4c6bcf44 VS |
2774 | } |
2775 | ||
2776 | return 0; | |
2777 | } | |
2778 | ||
3f2f6533 LD |
2779 | /* |
2780 | * drm_match_hdmi_mode - look for a HDMI mode matching given mode | |
2781 | * @to_match: display mode | |
2782 | * | |
2783 | * An HDMI mode is one defined in the HDMI vendor specific block. | |
2784 | * | |
2785 | * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. | |
2786 | */ | |
2787 | static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) | |
2788 | { | |
d9278b4c | 2789 | u8 vic; |
3f2f6533 LD |
2790 | |
2791 | if (!to_match->clock) | |
2792 | return 0; | |
2793 | ||
d9278b4c JN |
2794 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { |
2795 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | |
3f2f6533 LD |
2796 | unsigned int clock1, clock2; |
2797 | ||
2798 | /* Make sure to also match alternate clocks */ | |
2799 | clock1 = hdmi_mode->clock; | |
2800 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | |
2801 | ||
2802 | if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || | |
2803 | KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && | |
f2ecf2e3 | 2804 | drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) |
d9278b4c | 2805 | return vic; |
3f2f6533 LD |
2806 | } |
2807 | return 0; | |
2808 | } | |
2809 | ||
d9278b4c JN |
2810 | static bool drm_valid_hdmi_vic(u8 vic) |
2811 | { | |
2812 | return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); | |
2813 | } | |
2814 | ||
e6e79209 VS |
2815 | static int |
2816 | add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) | |
2817 | { | |
2818 | struct drm_device *dev = connector->dev; | |
2819 | struct drm_display_mode *mode, *tmp; | |
2820 | LIST_HEAD(list); | |
2821 | int modes = 0; | |
2822 | ||
2823 | /* Don't add CEA modes if the CEA extension block is missing */ | |
2824 | if (!drm_find_cea_extension(edid)) | |
2825 | return 0; | |
2826 | ||
2827 | /* | |
2828 | * Go through all probed modes and create a new mode | |
2829 | * with the alternate clock for certain CEA modes. | |
2830 | */ | |
2831 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
3f2f6533 | 2832 | const struct drm_display_mode *cea_mode = NULL; |
e6e79209 | 2833 | struct drm_display_mode *newmode; |
d9278b4c | 2834 | u8 vic = drm_match_cea_mode(mode); |
e6e79209 VS |
2835 | unsigned int clock1, clock2; |
2836 | ||
d9278b4c JN |
2837 | if (drm_valid_cea_vic(vic)) { |
2838 | cea_mode = &edid_cea_modes[vic]; | |
3f2f6533 LD |
2839 | clock2 = cea_mode_alternate_clock(cea_mode); |
2840 | } else { | |
d9278b4c JN |
2841 | vic = drm_match_hdmi_mode(mode); |
2842 | if (drm_valid_hdmi_vic(vic)) { | |
2843 | cea_mode = &edid_4k_modes[vic]; | |
3f2f6533 LD |
2844 | clock2 = hdmi_mode_alternate_clock(cea_mode); |
2845 | } | |
2846 | } | |
e6e79209 | 2847 | |
3f2f6533 LD |
2848 | if (!cea_mode) |
2849 | continue; | |
e6e79209 VS |
2850 | |
2851 | clock1 = cea_mode->clock; | |
e6e79209 VS |
2852 | |
2853 | if (clock1 == clock2) | |
2854 | continue; | |
2855 | ||
2856 | if (mode->clock != clock1 && mode->clock != clock2) | |
2857 | continue; | |
2858 | ||
2859 | newmode = drm_mode_duplicate(dev, cea_mode); | |
2860 | if (!newmode) | |
2861 | continue; | |
2862 | ||
27130212 DL |
2863 | /* Carry over the stereo flags */ |
2864 | newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; | |
2865 | ||
e6e79209 VS |
2866 | /* |
2867 | * The current mode could be either variant. Make | |
2868 | * sure to pick the "other" clock for the new mode. | |
2869 | */ | |
2870 | if (mode->clock != clock1) | |
2871 | newmode->clock = clock1; | |
2872 | else | |
2873 | newmode->clock = clock2; | |
2874 | ||
2875 | list_add_tail(&newmode->head, &list); | |
2876 | } | |
2877 | ||
2878 | list_for_each_entry_safe(mode, tmp, &list, head) { | |
2879 | list_del(&mode->head); | |
2880 | drm_mode_probed_add(connector, mode); | |
2881 | modes++; | |
2882 | } | |
2883 | ||
2884 | return modes; | |
2885 | } | |
a4799037 | 2886 | |
aff04ace TW |
2887 | static struct drm_display_mode * |
2888 | drm_display_mode_from_vic_index(struct drm_connector *connector, | |
2889 | const u8 *video_db, u8 video_len, | |
2890 | u8 video_index) | |
54ac76f8 CS |
2891 | { |
2892 | struct drm_device *dev = connector->dev; | |
aff04ace | 2893 | struct drm_display_mode *newmode; |
d9278b4c | 2894 | u8 vic; |
54ac76f8 | 2895 | |
aff04ace TW |
2896 | if (video_db == NULL || video_index >= video_len) |
2897 | return NULL; | |
2898 | ||
2899 | /* CEA modes are numbered 1..127 */ | |
d9278b4c JN |
2900 | vic = (video_db[video_index] & 127); |
2901 | if (!drm_valid_cea_vic(vic)) | |
aff04ace TW |
2902 | return NULL; |
2903 | ||
d9278b4c | 2904 | newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); |
409bbf1e DL |
2905 | if (!newmode) |
2906 | return NULL; | |
2907 | ||
aff04ace TW |
2908 | newmode->vrefresh = 0; |
2909 | ||
2910 | return newmode; | |
2911 | } | |
2912 | ||
2913 | static int | |
2914 | do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) | |
2915 | { | |
2916 | int i, modes = 0; | |
2917 | ||
2918 | for (i = 0; i < len; i++) { | |
2919 | struct drm_display_mode *mode; | |
2920 | mode = drm_display_mode_from_vic_index(connector, db, len, i); | |
2921 | if (mode) { | |
2922 | drm_mode_probed_add(connector, mode); | |
2923 | modes++; | |
54ac76f8 CS |
2924 | } |
2925 | } | |
2926 | ||
2927 | return modes; | |
2928 | } | |
2929 | ||
c858cfca DL |
2930 | struct stereo_mandatory_mode { |
2931 | int width, height, vrefresh; | |
2932 | unsigned int flags; | |
2933 | }; | |
2934 | ||
2935 | static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { | |
f7e121b7 DL |
2936 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
2937 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
c858cfca DL |
2938 | { 1920, 1080, 50, |
2939 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
2940 | { 1920, 1080, 60, | |
2941 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
f7e121b7 DL |
2942 | { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
2943 | { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
2944 | { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, | |
2945 | { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } | |
c858cfca DL |
2946 | }; |
2947 | ||
2948 | static bool | |
2949 | stereo_match_mandatory(const struct drm_display_mode *mode, | |
2950 | const struct stereo_mandatory_mode *stereo_mode) | |
2951 | { | |
2952 | unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; | |
2953 | ||
2954 | return mode->hdisplay == stereo_mode->width && | |
2955 | mode->vdisplay == stereo_mode->height && | |
2956 | interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && | |
2957 | drm_mode_vrefresh(mode) == stereo_mode->vrefresh; | |
2958 | } | |
2959 | ||
c858cfca DL |
2960 | static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) |
2961 | { | |
2962 | struct drm_device *dev = connector->dev; | |
2963 | const struct drm_display_mode *mode; | |
2964 | struct list_head stereo_modes; | |
f7e121b7 | 2965 | int modes = 0, i; |
c858cfca DL |
2966 | |
2967 | INIT_LIST_HEAD(&stereo_modes); | |
2968 | ||
2969 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
f7e121b7 DL |
2970 | for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { |
2971 | const struct stereo_mandatory_mode *mandatory; | |
c858cfca DL |
2972 | struct drm_display_mode *new_mode; |
2973 | ||
f7e121b7 DL |
2974 | if (!stereo_match_mandatory(mode, |
2975 | &stereo_mandatory_modes[i])) | |
2976 | continue; | |
c858cfca | 2977 | |
f7e121b7 | 2978 | mandatory = &stereo_mandatory_modes[i]; |
c858cfca DL |
2979 | new_mode = drm_mode_duplicate(dev, mode); |
2980 | if (!new_mode) | |
2981 | continue; | |
2982 | ||
f7e121b7 | 2983 | new_mode->flags |= mandatory->flags; |
c858cfca DL |
2984 | list_add_tail(&new_mode->head, &stereo_modes); |
2985 | modes++; | |
f7e121b7 | 2986 | } |
c858cfca DL |
2987 | } |
2988 | ||
2989 | list_splice_tail(&stereo_modes, &connector->probed_modes); | |
2990 | ||
2991 | return modes; | |
2992 | } | |
2993 | ||
1deee8d7 DL |
2994 | static int add_hdmi_mode(struct drm_connector *connector, u8 vic) |
2995 | { | |
2996 | struct drm_device *dev = connector->dev; | |
2997 | struct drm_display_mode *newmode; | |
2998 | ||
d9278b4c | 2999 | if (!drm_valid_hdmi_vic(vic)) { |
1deee8d7 DL |
3000 | DRM_ERROR("Unknown HDMI VIC: %d\n", vic); |
3001 | return 0; | |
3002 | } | |
3003 | ||
3004 | newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); | |
3005 | if (!newmode) | |
3006 | return 0; | |
3007 | ||
3008 | drm_mode_probed_add(connector, newmode); | |
3009 | ||
3010 | return 1; | |
3011 | } | |
3012 | ||
fbf46025 TW |
3013 | static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, |
3014 | const u8 *video_db, u8 video_len, u8 video_index) | |
3015 | { | |
fbf46025 TW |
3016 | struct drm_display_mode *newmode; |
3017 | int modes = 0; | |
fbf46025 TW |
3018 | |
3019 | if (structure & (1 << 0)) { | |
aff04ace TW |
3020 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
3021 | video_len, | |
3022 | video_index); | |
fbf46025 TW |
3023 | if (newmode) { |
3024 | newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; | |
3025 | drm_mode_probed_add(connector, newmode); | |
3026 | modes++; | |
3027 | } | |
3028 | } | |
3029 | if (structure & (1 << 6)) { | |
aff04ace TW |
3030 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
3031 | video_len, | |
3032 | video_index); | |
fbf46025 TW |
3033 | if (newmode) { |
3034 | newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; | |
3035 | drm_mode_probed_add(connector, newmode); | |
3036 | modes++; | |
3037 | } | |
3038 | } | |
3039 | if (structure & (1 << 8)) { | |
aff04ace TW |
3040 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
3041 | video_len, | |
3042 | video_index); | |
fbf46025 | 3043 | if (newmode) { |
89570eeb | 3044 | newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; |
fbf46025 TW |
3045 | drm_mode_probed_add(connector, newmode); |
3046 | modes++; | |
3047 | } | |
3048 | } | |
3049 | ||
3050 | return modes; | |
3051 | } | |
3052 | ||
7ebe1963 LD |
3053 | /* |
3054 | * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block | |
3055 | * @connector: connector corresponding to the HDMI sink | |
3056 | * @db: start of the CEA vendor specific block | |
3057 | * @len: length of the CEA block payload, ie. one can access up to db[len] | |
3058 | * | |
c858cfca DL |
3059 | * Parses the HDMI VSDB looking for modes to add to @connector. This function |
3060 | * also adds the stereo 3d modes when applicable. | |
7ebe1963 LD |
3061 | */ |
3062 | static int | |
fbf46025 TW |
3063 | do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, |
3064 | const u8 *video_db, u8 video_len) | |
7ebe1963 | 3065 | { |
0e5083aa | 3066 | int modes = 0, offset = 0, i, multi_present = 0, multi_len; |
fbf46025 TW |
3067 | u8 vic_len, hdmi_3d_len = 0; |
3068 | u16 mask; | |
3069 | u16 structure_all; | |
7ebe1963 LD |
3070 | |
3071 | if (len < 8) | |
3072 | goto out; | |
3073 | ||
3074 | /* no HDMI_Video_Present */ | |
3075 | if (!(db[8] & (1 << 5))) | |
3076 | goto out; | |
3077 | ||
3078 | /* Latency_Fields_Present */ | |
3079 | if (db[8] & (1 << 7)) | |
3080 | offset += 2; | |
3081 | ||
3082 | /* I_Latency_Fields_Present */ | |
3083 | if (db[8] & (1 << 6)) | |
3084 | offset += 2; | |
3085 | ||
3086 | /* the declared length is not long enough for the 2 first bytes | |
3087 | * of additional video format capabilities */ | |
c858cfca | 3088 | if (len < (8 + offset + 2)) |
7ebe1963 LD |
3089 | goto out; |
3090 | ||
c858cfca DL |
3091 | /* 3D_Present */ |
3092 | offset++; | |
fbf46025 | 3093 | if (db[8 + offset] & (1 << 7)) { |
c858cfca DL |
3094 | modes += add_hdmi_mandatory_stereo_modes(connector); |
3095 | ||
fbf46025 TW |
3096 | /* 3D_Multi_present */ |
3097 | multi_present = (db[8 + offset] & 0x60) >> 5; | |
3098 | } | |
3099 | ||
c858cfca | 3100 | offset++; |
7ebe1963 | 3101 | vic_len = db[8 + offset] >> 5; |
fbf46025 | 3102 | hdmi_3d_len = db[8 + offset] & 0x1f; |
7ebe1963 LD |
3103 | |
3104 | for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { | |
7ebe1963 LD |
3105 | u8 vic; |
3106 | ||
3107 | vic = db[9 + offset + i]; | |
1deee8d7 | 3108 | modes += add_hdmi_mode(connector, vic); |
7ebe1963 | 3109 | } |
fbf46025 TW |
3110 | offset += 1 + vic_len; |
3111 | ||
0e5083aa TW |
3112 | if (multi_present == 1) |
3113 | multi_len = 2; | |
3114 | else if (multi_present == 2) | |
3115 | multi_len = 4; | |
3116 | else | |
3117 | multi_len = 0; | |
fbf46025 | 3118 | |
0e5083aa | 3119 | if (len < (8 + offset + hdmi_3d_len - 1)) |
fbf46025 TW |
3120 | goto out; |
3121 | ||
0e5083aa | 3122 | if (hdmi_3d_len < multi_len) |
fbf46025 TW |
3123 | goto out; |
3124 | ||
0e5083aa TW |
3125 | if (multi_present == 1 || multi_present == 2) { |
3126 | /* 3D_Structure_ALL */ | |
3127 | structure_all = (db[8 + offset] << 8) | db[9 + offset]; | |
fbf46025 | 3128 | |
0e5083aa TW |
3129 | /* check if 3D_MASK is present */ |
3130 | if (multi_present == 2) | |
3131 | mask = (db[10 + offset] << 8) | db[11 + offset]; | |
3132 | else | |
3133 | mask = 0xffff; | |
3134 | ||
3135 | for (i = 0; i < 16; i++) { | |
3136 | if (mask & (1 << i)) | |
3137 | modes += add_3d_struct_modes(connector, | |
3138 | structure_all, | |
3139 | video_db, | |
3140 | video_len, i); | |
3141 | } | |
3142 | } | |
3143 | ||
3144 | offset += multi_len; | |
3145 | ||
3146 | for (i = 0; i < (hdmi_3d_len - multi_len); i++) { | |
3147 | int vic_index; | |
3148 | struct drm_display_mode *newmode = NULL; | |
3149 | unsigned int newflag = 0; | |
3150 | bool detail_present; | |
3151 | ||
3152 | detail_present = ((db[8 + offset + i] & 0x0f) > 7); | |
3153 | ||
3154 | if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) | |
3155 | break; | |
3156 | ||
3157 | /* 2D_VIC_order_X */ | |
3158 | vic_index = db[8 + offset + i] >> 4; | |
3159 | ||
3160 | /* 3D_Structure_X */ | |
3161 | switch (db[8 + offset + i] & 0x0f) { | |
3162 | case 0: | |
3163 | newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; | |
3164 | break; | |
3165 | case 6: | |
3166 | newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; | |
3167 | break; | |
3168 | case 8: | |
3169 | /* 3D_Detail_X */ | |
3170 | if ((db[9 + offset + i] >> 4) == 1) | |
3171 | newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; | |
3172 | break; | |
3173 | } | |
3174 | ||
3175 | if (newflag != 0) { | |
3176 | newmode = drm_display_mode_from_vic_index(connector, | |
3177 | video_db, | |
3178 | video_len, | |
3179 | vic_index); | |
3180 | ||
3181 | if (newmode) { | |
3182 | newmode->flags |= newflag; | |
3183 | drm_mode_probed_add(connector, newmode); | |
3184 | modes++; | |
3185 | } | |
3186 | } | |
3187 | ||
3188 | if (detail_present) | |
3189 | i++; | |
fbf46025 | 3190 | } |
7ebe1963 LD |
3191 | |
3192 | out: | |
3193 | return modes; | |
3194 | } | |
3195 | ||
9e50b9d5 VS |
3196 | static int |
3197 | cea_db_payload_len(const u8 *db) | |
3198 | { | |
3199 | return db[0] & 0x1f; | |
3200 | } | |
3201 | ||
3202 | static int | |
3203 | cea_db_tag(const u8 *db) | |
3204 | { | |
3205 | return db[0] >> 5; | |
3206 | } | |
3207 | ||
3208 | static int | |
3209 | cea_revision(const u8 *cea) | |
3210 | { | |
3211 | return cea[1]; | |
3212 | } | |
3213 | ||
3214 | static int | |
3215 | cea_db_offsets(const u8 *cea, int *start, int *end) | |
3216 | { | |
3217 | /* Data block offset in CEA extension block */ | |
3218 | *start = 4; | |
3219 | *end = cea[2]; | |
3220 | if (*end == 0) | |
3221 | *end = 127; | |
3222 | if (*end < 4 || *end > 127) | |
3223 | return -ERANGE; | |
3224 | return 0; | |
3225 | } | |
3226 | ||
7ebe1963 LD |
3227 | static bool cea_db_is_hdmi_vsdb(const u8 *db) |
3228 | { | |
3229 | int hdmi_id; | |
3230 | ||
3231 | if (cea_db_tag(db) != VENDOR_BLOCK) | |
3232 | return false; | |
3233 | ||
3234 | if (cea_db_payload_len(db) < 5) | |
3235 | return false; | |
3236 | ||
3237 | hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); | |
3238 | ||
6cb3b7f1 | 3239 | return hdmi_id == HDMI_IEEE_OUI; |
7ebe1963 LD |
3240 | } |
3241 | ||
9e50b9d5 VS |
3242 | #define for_each_cea_db(cea, i, start, end) \ |
3243 | for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) | |
3244 | ||
54ac76f8 CS |
3245 | static int |
3246 | add_cea_modes(struct drm_connector *connector, struct edid *edid) | |
3247 | { | |
13ac3f55 | 3248 | const u8 *cea = drm_find_cea_extension(edid); |
fbf46025 TW |
3249 | const u8 *db, *hdmi = NULL, *video = NULL; |
3250 | u8 dbl, hdmi_len, video_len = 0; | |
54ac76f8 CS |
3251 | int modes = 0; |
3252 | ||
9e50b9d5 VS |
3253 | if (cea && cea_revision(cea) >= 3) { |
3254 | int i, start, end; | |
3255 | ||
3256 | if (cea_db_offsets(cea, &start, &end)) | |
3257 | return 0; | |
3258 | ||
3259 | for_each_cea_db(cea, i, start, end) { | |
3260 | db = &cea[i]; | |
3261 | dbl = cea_db_payload_len(db); | |
3262 | ||
fbf46025 TW |
3263 | if (cea_db_tag(db) == VIDEO_BLOCK) { |
3264 | video = db + 1; | |
3265 | video_len = dbl; | |
3266 | modes += do_cea_modes(connector, video, dbl); | |
3267 | } | |
c858cfca DL |
3268 | else if (cea_db_is_hdmi_vsdb(db)) { |
3269 | hdmi = db; | |
3270 | hdmi_len = dbl; | |
3271 | } | |
54ac76f8 CS |
3272 | } |
3273 | } | |
3274 | ||
c858cfca DL |
3275 | /* |
3276 | * We parse the HDMI VSDB after having added the cea modes as we will | |
3277 | * be patching their flags when the sink supports stereo 3D. | |
3278 | */ | |
3279 | if (hdmi) | |
fbf46025 TW |
3280 | modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, |
3281 | video_len); | |
c858cfca | 3282 | |
54ac76f8 CS |
3283 | return modes; |
3284 | } | |
3285 | ||
fa3a7340 VS |
3286 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) |
3287 | { | |
3288 | const struct drm_display_mode *cea_mode; | |
3289 | int clock1, clock2, clock; | |
d9278b4c | 3290 | u8 vic; |
fa3a7340 VS |
3291 | const char *type; |
3292 | ||
4c6bcf44 VS |
3293 | /* |
3294 | * allow 5kHz clock difference either way to account for | |
3295 | * the 10kHz clock resolution limit of detailed timings. | |
3296 | */ | |
d9278b4c JN |
3297 | vic = drm_match_cea_mode_clock_tolerance(mode, 5); |
3298 | if (drm_valid_cea_vic(vic)) { | |
fa3a7340 | 3299 | type = "CEA"; |
d9278b4c | 3300 | cea_mode = &edid_cea_modes[vic]; |
fa3a7340 VS |
3301 | clock1 = cea_mode->clock; |
3302 | clock2 = cea_mode_alternate_clock(cea_mode); | |
3303 | } else { | |
d9278b4c JN |
3304 | vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); |
3305 | if (drm_valid_hdmi_vic(vic)) { | |
fa3a7340 | 3306 | type = "HDMI"; |
d9278b4c | 3307 | cea_mode = &edid_4k_modes[vic]; |
fa3a7340 VS |
3308 | clock1 = cea_mode->clock; |
3309 | clock2 = hdmi_mode_alternate_clock(cea_mode); | |
3310 | } else { | |
3311 | return; | |
3312 | } | |
3313 | } | |
3314 | ||
3315 | /* pick whichever is closest */ | |
3316 | if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) | |
3317 | clock = clock1; | |
3318 | else | |
3319 | clock = clock2; | |
3320 | ||
3321 | if (mode->clock == clock) | |
3322 | return; | |
3323 | ||
3324 | DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", | |
d9278b4c | 3325 | type, vic, mode->clock, clock); |
fa3a7340 VS |
3326 | mode->clock = clock; |
3327 | } | |
3328 | ||
76adaa34 | 3329 | static void |
23ebf8b9 | 3330 | drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) |
76adaa34 | 3331 | { |
8504072a | 3332 | u8 len = cea_db_payload_len(db); |
76adaa34 | 3333 | |
23ebf8b9 | 3334 | if (len >= 6) |
8504072a | 3335 | connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ |
8504072a VS |
3336 | if (len >= 8) { |
3337 | connector->latency_present[0] = db[8] >> 7; | |
3338 | connector->latency_present[1] = (db[8] >> 6) & 1; | |
3339 | } | |
3340 | if (len >= 9) | |
3341 | connector->video_latency[0] = db[9]; | |
3342 | if (len >= 10) | |
3343 | connector->audio_latency[0] = db[10]; | |
3344 | if (len >= 11) | |
3345 | connector->video_latency[1] = db[11]; | |
3346 | if (len >= 12) | |
3347 | connector->audio_latency[1] = db[12]; | |
76adaa34 | 3348 | |
23ebf8b9 VS |
3349 | DRM_DEBUG_KMS("HDMI: latency present %d %d, " |
3350 | "video latency %d %d, " | |
3351 | "audio latency %d %d\n", | |
3352 | connector->latency_present[0], | |
3353 | connector->latency_present[1], | |
3354 | connector->video_latency[0], | |
3355 | connector->video_latency[1], | |
3356 | connector->audio_latency[0], | |
3357 | connector->audio_latency[1]); | |
76adaa34 WF |
3358 | } |
3359 | ||
3360 | static void | |
3361 | monitor_name(struct detailed_timing *t, void *data) | |
3362 | { | |
3363 | if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) | |
3364 | *(u8 **)data = t->data.other_data.data.str.str; | |
14f77fdd VS |
3365 | } |
3366 | ||
59f7c0fa JB |
3367 | static int get_monitor_name(struct edid *edid, char name[13]) |
3368 | { | |
3369 | char *edid_name = NULL; | |
3370 | int mnl; | |
3371 | ||
3372 | if (!edid || !name) | |
3373 | return 0; | |
3374 | ||
3375 | drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); | |
3376 | for (mnl = 0; edid_name && mnl < 13; mnl++) { | |
3377 | if (edid_name[mnl] == 0x0a) | |
3378 | break; | |
3379 | ||
3380 | name[mnl] = edid_name[mnl]; | |
3381 | } | |
3382 | ||
3383 | return mnl; | |
3384 | } | |
3385 | ||
3386 | /** | |
3387 | * drm_edid_get_monitor_name - fetch the monitor name from the edid | |
3388 | * @edid: monitor EDID information | |
3389 | * @name: pointer to a character array to hold the name of the monitor | |
3390 | * @bufsize: The size of the name buffer (should be at least 14 chars.) | |
3391 | * | |
3392 | */ | |
3393 | void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) | |
3394 | { | |
3395 | int name_length; | |
3396 | char buf[13]; | |
3397 | ||
3398 | if (bufsize <= 0) | |
3399 | return; | |
3400 | ||
3401 | name_length = min(get_monitor_name(edid, buf), bufsize - 1); | |
3402 | memcpy(name, buf, name_length); | |
3403 | name[name_length] = '\0'; | |
3404 | } | |
3405 | EXPORT_SYMBOL(drm_edid_get_monitor_name); | |
3406 | ||
76adaa34 WF |
3407 | /** |
3408 | * drm_edid_to_eld - build ELD from EDID | |
3409 | * @connector: connector corresponding to the HDMI/DP sink | |
3410 | * @edid: EDID to parse | |
3411 | * | |
db6cf833 TR |
3412 | * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The |
3413 | * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to | |
3414 | * fill in. | |
76adaa34 WF |
3415 | */ |
3416 | void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) | |
3417 | { | |
3418 | uint8_t *eld = connector->eld; | |
3419 | u8 *cea; | |
76adaa34 | 3420 | u8 *db; |
7c018782 | 3421 | int total_sad_count = 0; |
76adaa34 WF |
3422 | int mnl; |
3423 | int dbl; | |
3424 | ||
3425 | memset(eld, 0, sizeof(connector->eld)); | |
3426 | ||
85c91580 VS |
3427 | connector->latency_present[0] = false; |
3428 | connector->latency_present[1] = false; | |
3429 | connector->video_latency[0] = 0; | |
3430 | connector->audio_latency[0] = 0; | |
3431 | connector->video_latency[1] = 0; | |
3432 | connector->audio_latency[1] = 0; | |
3433 | ||
76adaa34 WF |
3434 | cea = drm_find_cea_extension(edid); |
3435 | if (!cea) { | |
3436 | DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); | |
3437 | return; | |
3438 | } | |
3439 | ||
59f7c0fa JB |
3440 | mnl = get_monitor_name(edid, eld + 20); |
3441 | ||
76adaa34 WF |
3442 | eld[4] = (cea[1] << 5) | mnl; |
3443 | DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); | |
3444 | ||
3445 | eld[0] = 2 << 3; /* ELD version: 2 */ | |
3446 | ||
3447 | eld[16] = edid->mfg_id[0]; | |
3448 | eld[17] = edid->mfg_id[1]; | |
3449 | eld[18] = edid->prod_code[0]; | |
3450 | eld[19] = edid->prod_code[1]; | |
3451 | ||
9e50b9d5 VS |
3452 | if (cea_revision(cea) >= 3) { |
3453 | int i, start, end; | |
3454 | ||
3455 | if (cea_db_offsets(cea, &start, &end)) { | |
3456 | start = 0; | |
3457 | end = 0; | |
3458 | } | |
3459 | ||
3460 | for_each_cea_db(cea, i, start, end) { | |
3461 | db = &cea[i]; | |
3462 | dbl = cea_db_payload_len(db); | |
3463 | ||
3464 | switch (cea_db_tag(db)) { | |
7c018782 VS |
3465 | int sad_count; |
3466 | ||
a0ab734d CS |
3467 | case AUDIO_BLOCK: |
3468 | /* Audio Data Block, contains SADs */ | |
7c018782 VS |
3469 | sad_count = min(dbl / 3, 15 - total_sad_count); |
3470 | if (sad_count >= 1) | |
3471 | memcpy(eld + 20 + mnl + total_sad_count * 3, | |
3472 | &db[1], sad_count * 3); | |
3473 | total_sad_count += sad_count; | |
a0ab734d CS |
3474 | break; |
3475 | case SPEAKER_BLOCK: | |
9e50b9d5 VS |
3476 | /* Speaker Allocation Data Block */ |
3477 | if (dbl >= 1) | |
3478 | eld[7] = db[1]; | |
a0ab734d CS |
3479 | break; |
3480 | case VENDOR_BLOCK: | |
3481 | /* HDMI Vendor-Specific Data Block */ | |
14f77fdd | 3482 | if (cea_db_is_hdmi_vsdb(db)) |
23ebf8b9 | 3483 | drm_parse_hdmi_vsdb_audio(connector, db); |
a0ab734d CS |
3484 | break; |
3485 | default: | |
3486 | break; | |
3487 | } | |
76adaa34 | 3488 | } |
9e50b9d5 | 3489 | } |
7c018782 | 3490 | eld[5] |= total_sad_count << 4; |
76adaa34 | 3491 | |
938fd8aa JN |
3492 | eld[DRM_ELD_BASELINE_ELD_LEN] = |
3493 | DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); | |
3494 | ||
3495 | DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", | |
7c018782 | 3496 | drm_eld_size(eld), total_sad_count); |
76adaa34 WF |
3497 | } |
3498 | EXPORT_SYMBOL(drm_edid_to_eld); | |
3499 | ||
fe214163 RM |
3500 | /** |
3501 | * drm_edid_to_sad - extracts SADs from EDID | |
3502 | * @edid: EDID to parse | |
3503 | * @sads: pointer that will be set to the extracted SADs | |
3504 | * | |
3505 | * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. | |
fe214163 | 3506 | * |
db6cf833 TR |
3507 | * Note: The returned pointer needs to be freed using kfree(). |
3508 | * | |
3509 | * Return: The number of found SADs or negative number on error. | |
fe214163 RM |
3510 | */ |
3511 | int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) | |
3512 | { | |
3513 | int count = 0; | |
3514 | int i, start, end, dbl; | |
3515 | u8 *cea; | |
3516 | ||
3517 | cea = drm_find_cea_extension(edid); | |
3518 | if (!cea) { | |
3519 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
3520 | return -ENOENT; | |
3521 | } | |
3522 | ||
3523 | if (cea_revision(cea) < 3) { | |
3524 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
3525 | return -ENOTSUPP; | |
3526 | } | |
3527 | ||
3528 | if (cea_db_offsets(cea, &start, &end)) { | |
3529 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
3530 | return -EPROTO; | |
3531 | } | |
3532 | ||
3533 | for_each_cea_db(cea, i, start, end) { | |
3534 | u8 *db = &cea[i]; | |
3535 | ||
3536 | if (cea_db_tag(db) == AUDIO_BLOCK) { | |
3537 | int j; | |
3538 | dbl = cea_db_payload_len(db); | |
3539 | ||
3540 | count = dbl / 3; /* SAD is 3B */ | |
3541 | *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); | |
3542 | if (!*sads) | |
3543 | return -ENOMEM; | |
3544 | for (j = 0; j < count; j++) { | |
3545 | u8 *sad = &db[1 + j * 3]; | |
3546 | ||
3547 | (*sads)[j].format = (sad[0] & 0x78) >> 3; | |
3548 | (*sads)[j].channels = sad[0] & 0x7; | |
3549 | (*sads)[j].freq = sad[1] & 0x7F; | |
3550 | (*sads)[j].byte2 = sad[2]; | |
3551 | } | |
3552 | break; | |
3553 | } | |
3554 | } | |
3555 | ||
3556 | return count; | |
3557 | } | |
3558 | EXPORT_SYMBOL(drm_edid_to_sad); | |
3559 | ||
d105f476 AD |
3560 | /** |
3561 | * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID | |
3562 | * @edid: EDID to parse | |
3563 | * @sadb: pointer to the speaker block | |
3564 | * | |
3565 | * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. | |
d105f476 | 3566 | * |
db6cf833 TR |
3567 | * Note: The returned pointer needs to be freed using kfree(). |
3568 | * | |
3569 | * Return: The number of found Speaker Allocation Blocks or negative number on | |
3570 | * error. | |
d105f476 AD |
3571 | */ |
3572 | int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) | |
3573 | { | |
3574 | int count = 0; | |
3575 | int i, start, end, dbl; | |
3576 | const u8 *cea; | |
3577 | ||
3578 | cea = drm_find_cea_extension(edid); | |
3579 | if (!cea) { | |
3580 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
3581 | return -ENOENT; | |
3582 | } | |
3583 | ||
3584 | if (cea_revision(cea) < 3) { | |
3585 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
3586 | return -ENOTSUPP; | |
3587 | } | |
3588 | ||
3589 | if (cea_db_offsets(cea, &start, &end)) { | |
3590 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
3591 | return -EPROTO; | |
3592 | } | |
3593 | ||
3594 | for_each_cea_db(cea, i, start, end) { | |
3595 | const u8 *db = &cea[i]; | |
3596 | ||
3597 | if (cea_db_tag(db) == SPEAKER_BLOCK) { | |
3598 | dbl = cea_db_payload_len(db); | |
3599 | ||
3600 | /* Speaker Allocation Data Block */ | |
3601 | if (dbl == 3) { | |
89086bca | 3602 | *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); |
618e3776 AD |
3603 | if (!*sadb) |
3604 | return -ENOMEM; | |
d105f476 AD |
3605 | count = dbl; |
3606 | break; | |
3607 | } | |
3608 | } | |
3609 | } | |
3610 | ||
3611 | return count; | |
3612 | } | |
3613 | EXPORT_SYMBOL(drm_edid_to_speaker_allocation); | |
3614 | ||
76adaa34 | 3615 | /** |
db6cf833 | 3616 | * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay |
76adaa34 WF |
3617 | * @connector: connector associated with the HDMI/DP sink |
3618 | * @mode: the display mode | |
db6cf833 TR |
3619 | * |
3620 | * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if | |
3621 | * the sink doesn't support audio or video. | |
76adaa34 WF |
3622 | */ |
3623 | int drm_av_sync_delay(struct drm_connector *connector, | |
3a818d35 | 3624 | const struct drm_display_mode *mode) |
76adaa34 WF |
3625 | { |
3626 | int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); | |
3627 | int a, v; | |
3628 | ||
3629 | if (!connector->latency_present[0]) | |
3630 | return 0; | |
3631 | if (!connector->latency_present[1]) | |
3632 | i = 0; | |
3633 | ||
3634 | a = connector->audio_latency[i]; | |
3635 | v = connector->video_latency[i]; | |
3636 | ||
3637 | /* | |
3638 | * HDMI/DP sink doesn't support audio or video? | |
3639 | */ | |
3640 | if (a == 255 || v == 255) | |
3641 | return 0; | |
3642 | ||
3643 | /* | |
3644 | * Convert raw EDID values to millisecond. | |
3645 | * Treat unknown latency as 0ms. | |
3646 | */ | |
3647 | if (a) | |
3648 | a = min(2 * (a - 1), 500); | |
3649 | if (v) | |
3650 | v = min(2 * (v - 1), 500); | |
3651 | ||
3652 | return max(v - a, 0); | |
3653 | } | |
3654 | EXPORT_SYMBOL(drm_av_sync_delay); | |
3655 | ||
8fe9790d | 3656 | /** |
db6cf833 | 3657 | * drm_detect_hdmi_monitor - detect whether monitor is HDMI |
8fe9790d ZW |
3658 | * @edid: monitor EDID information |
3659 | * | |
3660 | * Parse the CEA extension according to CEA-861-B. | |
db6cf833 TR |
3661 | * |
3662 | * Return: True if the monitor is HDMI, false if not or unknown. | |
8fe9790d ZW |
3663 | */ |
3664 | bool drm_detect_hdmi_monitor(struct edid *edid) | |
3665 | { | |
3666 | u8 *edid_ext; | |
14f77fdd | 3667 | int i; |
8fe9790d | 3668 | int start_offset, end_offset; |
8fe9790d ZW |
3669 | |
3670 | edid_ext = drm_find_cea_extension(edid); | |
3671 | if (!edid_ext) | |
14f77fdd | 3672 | return false; |
f23c20c8 | 3673 | |
9e50b9d5 | 3674 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
14f77fdd | 3675 | return false; |
f23c20c8 ML |
3676 | |
3677 | /* | |
3678 | * Because HDMI identifier is in Vendor Specific Block, | |
3679 | * search it from all data blocks of CEA extension. | |
3680 | */ | |
9e50b9d5 | 3681 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
14f77fdd VS |
3682 | if (cea_db_is_hdmi_vsdb(&edid_ext[i])) |
3683 | return true; | |
f23c20c8 ML |
3684 | } |
3685 | ||
14f77fdd | 3686 | return false; |
f23c20c8 ML |
3687 | } |
3688 | EXPORT_SYMBOL(drm_detect_hdmi_monitor); | |
3689 | ||
8fe9790d ZW |
3690 | /** |
3691 | * drm_detect_monitor_audio - check monitor audio capability | |
fc66811c | 3692 | * @edid: EDID block to scan |
8fe9790d ZW |
3693 | * |
3694 | * Monitor should have CEA extension block. | |
3695 | * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic | |
3696 | * audio' only. If there is any audio extension block and supported | |
3697 | * audio format, assume at least 'basic audio' support, even if 'basic | |
3698 | * audio' is not defined in EDID. | |
3699 | * | |
db6cf833 | 3700 | * Return: True if the monitor supports audio, false otherwise. |
8fe9790d ZW |
3701 | */ |
3702 | bool drm_detect_monitor_audio(struct edid *edid) | |
3703 | { | |
3704 | u8 *edid_ext; | |
3705 | int i, j; | |
3706 | bool has_audio = false; | |
3707 | int start_offset, end_offset; | |
3708 | ||
3709 | edid_ext = drm_find_cea_extension(edid); | |
3710 | if (!edid_ext) | |
3711 | goto end; | |
3712 | ||
3713 | has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); | |
3714 | ||
3715 | if (has_audio) { | |
3716 | DRM_DEBUG_KMS("Monitor has basic audio support\n"); | |
3717 | goto end; | |
3718 | } | |
3719 | ||
9e50b9d5 VS |
3720 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
3721 | goto end; | |
8fe9790d | 3722 | |
9e50b9d5 VS |
3723 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
3724 | if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { | |
8fe9790d | 3725 | has_audio = true; |
9e50b9d5 | 3726 | for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) |
8fe9790d ZW |
3727 | DRM_DEBUG_KMS("CEA audio format %d\n", |
3728 | (edid_ext[i + j] >> 3) & 0xf); | |
3729 | goto end; | |
3730 | } | |
3731 | } | |
3732 | end: | |
3733 | return has_audio; | |
3734 | } | |
3735 | EXPORT_SYMBOL(drm_detect_monitor_audio); | |
3736 | ||
b1edd6a6 VS |
3737 | /** |
3738 | * drm_rgb_quant_range_selectable - is RGB quantization range selectable? | |
fc66811c | 3739 | * @edid: EDID block to scan |
b1edd6a6 VS |
3740 | * |
3741 | * Check whether the monitor reports the RGB quantization range selection | |
3742 | * as supported. The AVI infoframe can then be used to inform the monitor | |
3743 | * which quantization range (full or limited) is used. | |
db6cf833 TR |
3744 | * |
3745 | * Return: True if the RGB quantization range is selectable, false otherwise. | |
b1edd6a6 VS |
3746 | */ |
3747 | bool drm_rgb_quant_range_selectable(struct edid *edid) | |
3748 | { | |
3749 | u8 *edid_ext; | |
3750 | int i, start, end; | |
3751 | ||
3752 | edid_ext = drm_find_cea_extension(edid); | |
3753 | if (!edid_ext) | |
3754 | return false; | |
3755 | ||
3756 | if (cea_db_offsets(edid_ext, &start, &end)) | |
3757 | return false; | |
3758 | ||
3759 | for_each_cea_db(edid_ext, i, start, end) { | |
3760 | if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && | |
3761 | cea_db_payload_len(&edid_ext[i]) == 2) { | |
3762 | DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); | |
3763 | return edid_ext[i + 2] & EDID_CEA_VCDB_QS; | |
3764 | } | |
3765 | } | |
3766 | ||
3767 | return false; | |
3768 | } | |
3769 | EXPORT_SYMBOL(drm_rgb_quant_range_selectable); | |
3770 | ||
1cea146a VS |
3771 | static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, |
3772 | const u8 *hdmi) | |
d0c94692 | 3773 | { |
1826750f | 3774 | struct drm_display_info *info = &connector->display_info; |
d0c94692 MK |
3775 | unsigned int dc_bpc = 0; |
3776 | ||
1cea146a VS |
3777 | /* HDMI supports at least 8 bpc */ |
3778 | info->bpc = 8; | |
d0c94692 | 3779 | |
1cea146a VS |
3780 | if (cea_db_payload_len(hdmi) < 6) |
3781 | return; | |
3782 | ||
3783 | if (hdmi[6] & DRM_EDID_HDMI_DC_30) { | |
3784 | dc_bpc = 10; | |
3785 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; | |
3786 | DRM_DEBUG("%s: HDMI sink does deep color 30.\n", | |
3787 | connector->name); | |
3788 | } | |
3789 | ||
3790 | if (hdmi[6] & DRM_EDID_HDMI_DC_36) { | |
3791 | dc_bpc = 12; | |
3792 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; | |
3793 | DRM_DEBUG("%s: HDMI sink does deep color 36.\n", | |
3794 | connector->name); | |
3795 | } | |
3796 | ||
3797 | if (hdmi[6] & DRM_EDID_HDMI_DC_48) { | |
3798 | dc_bpc = 16; | |
3799 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; | |
3800 | DRM_DEBUG("%s: HDMI sink does deep color 48.\n", | |
3801 | connector->name); | |
3802 | } | |
3803 | ||
3804 | if (dc_bpc == 0) { | |
3805 | DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", | |
3806 | connector->name); | |
3807 | return; | |
3808 | } | |
3809 | ||
3810 | DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", | |
3811 | connector->name, dc_bpc); | |
3812 | info->bpc = dc_bpc; | |
d0c94692 MK |
3813 | |
3814 | /* | |
1cea146a VS |
3815 | * Deep color support mandates RGB444 support for all video |
3816 | * modes and forbids YCRCB422 support for all video modes per | |
3817 | * HDMI 1.3 spec. | |
d0c94692 | 3818 | */ |
1cea146a | 3819 | info->color_formats = DRM_COLOR_FORMAT_RGB444; |
d0c94692 | 3820 | |
1cea146a VS |
3821 | /* YCRCB444 is optional according to spec. */ |
3822 | if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { | |
3823 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3824 | DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", | |
3825 | connector->name); | |
3826 | } | |
d0c94692 | 3827 | |
1cea146a VS |
3828 | /* |
3829 | * Spec says that if any deep color mode is supported at all, | |
3830 | * then deep color 36 bit must be supported. | |
3831 | */ | |
3832 | if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { | |
3833 | DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", | |
3834 | connector->name); | |
3835 | } | |
3836 | } | |
d0c94692 | 3837 | |
23ebf8b9 VS |
3838 | static void |
3839 | drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) | |
3840 | { | |
3841 | struct drm_display_info *info = &connector->display_info; | |
3842 | u8 len = cea_db_payload_len(db); | |
3843 | ||
3844 | if (len >= 6) | |
3845 | info->dvi_dual = db[6] & 1; | |
3846 | if (len >= 7) | |
3847 | info->max_tmds_clock = db[7] * 5000; | |
3848 | ||
3849 | DRM_DEBUG_KMS("HDMI: DVI dual %d, " | |
3850 | "max TMDS clock %d kHz\n", | |
3851 | info->dvi_dual, | |
3852 | info->max_tmds_clock); | |
3853 | ||
3854 | drm_parse_hdmi_deep_color_info(connector, db); | |
3855 | } | |
3856 | ||
1cea146a VS |
3857 | static void drm_parse_cea_ext(struct drm_connector *connector, |
3858 | struct edid *edid) | |
3859 | { | |
3860 | struct drm_display_info *info = &connector->display_info; | |
3861 | const u8 *edid_ext; | |
3862 | int i, start, end; | |
d0c94692 | 3863 | |
1cea146a VS |
3864 | edid_ext = drm_find_cea_extension(edid); |
3865 | if (!edid_ext) | |
3866 | return; | |
d0c94692 | 3867 | |
1cea146a | 3868 | info->cea_rev = edid_ext[1]; |
d0c94692 | 3869 | |
1cea146a VS |
3870 | /* The existence of a CEA block should imply RGB support */ |
3871 | info->color_formats = DRM_COLOR_FORMAT_RGB444; | |
3872 | if (edid_ext[3] & EDID_CEA_YCRCB444) | |
3873 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3874 | if (edid_ext[3] & EDID_CEA_YCRCB422) | |
3875 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; | |
3876 | ||
3877 | if (cea_db_offsets(edid_ext, &start, &end)) | |
3878 | return; | |
3879 | ||
3880 | for_each_cea_db(edid_ext, i, start, end) { | |
3881 | const u8 *db = &edid_ext[i]; | |
3882 | ||
23ebf8b9 VS |
3883 | if (cea_db_is_hdmi_vsdb(db)) |
3884 | drm_parse_hdmi_vsdb_video(connector, db); | |
1cea146a | 3885 | } |
d0c94692 MK |
3886 | } |
3887 | ||
1cea146a VS |
3888 | static void drm_add_display_info(struct drm_connector *connector, |
3889 | struct edid *edid) | |
3b11228b | 3890 | { |
1826750f | 3891 | struct drm_display_info *info = &connector->display_info; |
ebec9a7b | 3892 | |
3b11228b JB |
3893 | info->width_mm = edid->width_cm * 10; |
3894 | info->height_mm = edid->height_cm * 10; | |
3895 | ||
3896 | /* driver figures it out in this case */ | |
3897 | info->bpc = 0; | |
da05a5a7 | 3898 | info->color_formats = 0; |
011acce2 | 3899 | info->cea_rev = 0; |
23ebf8b9 VS |
3900 | info->max_tmds_clock = 0; |
3901 | info->dvi_dual = false; | |
3b11228b | 3902 | |
a988bc72 | 3903 | if (edid->revision < 3) |
3b11228b JB |
3904 | return; |
3905 | ||
3906 | if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) | |
3907 | return; | |
3908 | ||
1cea146a | 3909 | drm_parse_cea_ext(connector, edid); |
d0c94692 | 3910 | |
210a021d MK |
3911 | /* |
3912 | * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? | |
3913 | * | |
3914 | * For such displays, the DFP spec 1.0, section 3.10 "EDID support" | |
3915 | * tells us to assume 8 bpc color depth if the EDID doesn't have | |
3916 | * extensions which tell otherwise. | |
3917 | */ | |
3918 | if ((info->bpc == 0) && (edid->revision < 4) && | |
3919 | (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { | |
3920 | info->bpc = 8; | |
3921 | DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", | |
3922 | connector->name, info->bpc); | |
3923 | } | |
3924 | ||
a988bc72 LPC |
3925 | /* Only defined for 1.4 with digital displays */ |
3926 | if (edid->revision < 4) | |
3927 | return; | |
3928 | ||
3b11228b JB |
3929 | switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { |
3930 | case DRM_EDID_DIGITAL_DEPTH_6: | |
3931 | info->bpc = 6; | |
3932 | break; | |
3933 | case DRM_EDID_DIGITAL_DEPTH_8: | |
3934 | info->bpc = 8; | |
3935 | break; | |
3936 | case DRM_EDID_DIGITAL_DEPTH_10: | |
3937 | info->bpc = 10; | |
3938 | break; | |
3939 | case DRM_EDID_DIGITAL_DEPTH_12: | |
3940 | info->bpc = 12; | |
3941 | break; | |
3942 | case DRM_EDID_DIGITAL_DEPTH_14: | |
3943 | info->bpc = 14; | |
3944 | break; | |
3945 | case DRM_EDID_DIGITAL_DEPTH_16: | |
3946 | info->bpc = 16; | |
3947 | break; | |
3948 | case DRM_EDID_DIGITAL_DEPTH_UNDEF: | |
3949 | default: | |
3950 | info->bpc = 0; | |
3951 | break; | |
3952 | } | |
da05a5a7 | 3953 | |
d0c94692 | 3954 | DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", |
25933820 | 3955 | connector->name, info->bpc); |
d0c94692 | 3956 | |
a988bc72 | 3957 | info->color_formats |= DRM_COLOR_FORMAT_RGB444; |
ee58808d LPC |
3958 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) |
3959 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3960 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) | |
3961 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; | |
3b11228b JB |
3962 | } |
3963 | ||
c9729177 DA |
3964 | static int validate_displayid(u8 *displayid, int length, int idx) |
3965 | { | |
3966 | int i; | |
3967 | u8 csum = 0; | |
3968 | struct displayid_hdr *base; | |
3969 | ||
3970 | base = (struct displayid_hdr *)&displayid[idx]; | |
3971 | ||
3972 | DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", | |
3973 | base->rev, base->bytes, base->prod_id, base->ext_count); | |
3974 | ||
3975 | if (base->bytes + 5 > length - idx) | |
3976 | return -EINVAL; | |
3977 | for (i = idx; i <= base->bytes + 5; i++) { | |
3978 | csum += displayid[i]; | |
3979 | } | |
3980 | if (csum) { | |
3981 | DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); | |
3982 | return -EINVAL; | |
3983 | } | |
3984 | return 0; | |
3985 | } | |
3986 | ||
a39ed680 DA |
3987 | static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, |
3988 | struct displayid_detailed_timings_1 *timings) | |
3989 | { | |
3990 | struct drm_display_mode *mode; | |
3991 | unsigned pixel_clock = (timings->pixel_clock[0] | | |
3992 | (timings->pixel_clock[1] << 8) | | |
3993 | (timings->pixel_clock[2] << 16)); | |
3994 | unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; | |
3995 | unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; | |
3996 | unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; | |
3997 | unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; | |
3998 | unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; | |
3999 | unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; | |
4000 | unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; | |
4001 | unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; | |
4002 | bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; | |
4003 | bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; | |
4004 | mode = drm_mode_create(dev); | |
4005 | if (!mode) | |
4006 | return NULL; | |
4007 | ||
4008 | mode->clock = pixel_clock * 10; | |
4009 | mode->hdisplay = hactive; | |
4010 | mode->hsync_start = mode->hdisplay + hsync; | |
4011 | mode->hsync_end = mode->hsync_start + hsync_width; | |
4012 | mode->htotal = mode->hdisplay + hblank; | |
4013 | ||
4014 | mode->vdisplay = vactive; | |
4015 | mode->vsync_start = mode->vdisplay + vsync; | |
4016 | mode->vsync_end = mode->vsync_start + vsync_width; | |
4017 | mode->vtotal = mode->vdisplay + vblank; | |
4018 | ||
4019 | mode->flags = 0; | |
4020 | mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
4021 | mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
4022 | mode->type = DRM_MODE_TYPE_DRIVER; | |
4023 | ||
4024 | if (timings->flags & 0x80) | |
4025 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
4026 | mode->vrefresh = drm_mode_vrefresh(mode); | |
4027 | drm_mode_set_name(mode); | |
4028 | ||
4029 | return mode; | |
4030 | } | |
4031 | ||
4032 | static int add_displayid_detailed_1_modes(struct drm_connector *connector, | |
4033 | struct displayid_block *block) | |
4034 | { | |
4035 | struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; | |
4036 | int i; | |
4037 | int num_timings; | |
4038 | struct drm_display_mode *newmode; | |
4039 | int num_modes = 0; | |
4040 | /* blocks must be multiple of 20 bytes length */ | |
4041 | if (block->num_bytes % 20) | |
4042 | return 0; | |
4043 | ||
4044 | num_timings = block->num_bytes / 20; | |
4045 | for (i = 0; i < num_timings; i++) { | |
4046 | struct displayid_detailed_timings_1 *timings = &det->timings[i]; | |
4047 | ||
4048 | newmode = drm_mode_displayid_detailed(connector->dev, timings); | |
4049 | if (!newmode) | |
4050 | continue; | |
4051 | ||
4052 | drm_mode_probed_add(connector, newmode); | |
4053 | num_modes++; | |
4054 | } | |
4055 | return num_modes; | |
4056 | } | |
4057 | ||
4058 | static int add_displayid_detailed_modes(struct drm_connector *connector, | |
4059 | struct edid *edid) | |
4060 | { | |
4061 | u8 *displayid; | |
4062 | int ret; | |
4063 | int idx = 1; | |
4064 | int length = EDID_LENGTH; | |
4065 | struct displayid_block *block; | |
4066 | int num_modes = 0; | |
4067 | ||
4068 | displayid = drm_find_displayid_extension(edid); | |
4069 | if (!displayid) | |
4070 | return 0; | |
4071 | ||
4072 | ret = validate_displayid(displayid, length, idx); | |
4073 | if (ret) | |
4074 | return 0; | |
4075 | ||
4076 | idx += sizeof(struct displayid_hdr); | |
4077 | while (block = (struct displayid_block *)&displayid[idx], | |
4078 | idx + sizeof(struct displayid_block) <= length && | |
4079 | idx + sizeof(struct displayid_block) + block->num_bytes <= length && | |
4080 | block->num_bytes > 0) { | |
4081 | idx += block->num_bytes + sizeof(struct displayid_block); | |
4082 | switch (block->tag) { | |
4083 | case DATA_BLOCK_TYPE_1_DETAILED_TIMING: | |
4084 | num_modes += add_displayid_detailed_1_modes(connector, block); | |
4085 | break; | |
4086 | } | |
4087 | } | |
4088 | return num_modes; | |
4089 | } | |
4090 | ||
f453ba04 DA |
4091 | /** |
4092 | * drm_add_edid_modes - add modes from EDID data, if available | |
4093 | * @connector: connector we're probing | |
db6cf833 | 4094 | * @edid: EDID data |
f453ba04 | 4095 | * |
b3c6c8bf DV |
4096 | * Add the specified modes to the connector's mode list. Also fills out the |
4097 | * &drm_display_info structure in @connector with any information which can be | |
4098 | * derived from the edid. | |
f453ba04 | 4099 | * |
db6cf833 | 4100 | * Return: The number of modes added or 0 if we couldn't find any. |
f453ba04 DA |
4101 | */ |
4102 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) | |
4103 | { | |
4104 | int num_modes = 0; | |
4105 | u32 quirks; | |
4106 | ||
4107 | if (edid == NULL) { | |
4108 | return 0; | |
4109 | } | |
3c537889 | 4110 | if (!drm_edid_is_valid(edid)) { |
dcdb1674 | 4111 | dev_warn(connector->dev->dev, "%s: EDID invalid.\n", |
25933820 | 4112 | connector->name); |
f453ba04 DA |
4113 | return 0; |
4114 | } | |
4115 | ||
4116 | quirks = edid_get_quirks(edid); | |
4117 | ||
c867df70 AJ |
4118 | /* |
4119 | * EDID spec says modes should be preferred in this order: | |
4120 | * - preferred detailed mode | |
4121 | * - other detailed modes from base block | |
4122 | * - detailed modes from extension blocks | |
4123 | * - CVT 3-byte code modes | |
4124 | * - standard timing codes | |
4125 | * - established timing codes | |
4126 | * - modes inferred from GTF or CVT range information | |
4127 | * | |
13931579 | 4128 | * We get this pretty much right. |
c867df70 AJ |
4129 | * |
4130 | * XXX order for additional mode types in extension blocks? | |
4131 | */ | |
13931579 AJ |
4132 | num_modes += add_detailed_modes(connector, edid, quirks); |
4133 | num_modes += add_cvt_modes(connector, edid); | |
c867df70 AJ |
4134 | num_modes += add_standard_modes(connector, edid); |
4135 | num_modes += add_established_modes(connector, edid); | |
54ac76f8 | 4136 | num_modes += add_cea_modes(connector, edid); |
e6e79209 | 4137 | num_modes += add_alternate_cea_modes(connector, edid); |
a39ed680 | 4138 | num_modes += add_displayid_detailed_modes(connector, edid); |
4d53dc0c VS |
4139 | if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) |
4140 | num_modes += add_inferred_modes(connector, edid); | |
f453ba04 DA |
4141 | |
4142 | if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) | |
4143 | edid_fixup_preferred(connector, quirks); | |
4144 | ||
1cea146a | 4145 | drm_add_display_info(connector, edid); |
f453ba04 | 4146 | |
e10aec65 MK |
4147 | if (quirks & EDID_QUIRK_FORCE_6BPC) |
4148 | connector->display_info.bpc = 6; | |
4149 | ||
49d45a31 RM |
4150 | if (quirks & EDID_QUIRK_FORCE_8BPC) |
4151 | connector->display_info.bpc = 8; | |
4152 | ||
bc5b9641 MK |
4153 | if (quirks & EDID_QUIRK_FORCE_12BPC) |
4154 | connector->display_info.bpc = 12; | |
4155 | ||
f453ba04 DA |
4156 | return num_modes; |
4157 | } | |
4158 | EXPORT_SYMBOL(drm_add_edid_modes); | |
f0fda0a4 ZY |
4159 | |
4160 | /** | |
4161 | * drm_add_modes_noedid - add modes for the connectors without EDID | |
4162 | * @connector: connector we're probing | |
4163 | * @hdisplay: the horizontal display limit | |
4164 | * @vdisplay: the vertical display limit | |
4165 | * | |
4166 | * Add the specified modes to the connector's mode list. Only when the | |
4167 | * hdisplay/vdisplay is not beyond the given limit, it will be added. | |
4168 | * | |
db6cf833 | 4169 | * Return: The number of modes added or 0 if we couldn't find any. |
f0fda0a4 ZY |
4170 | */ |
4171 | int drm_add_modes_noedid(struct drm_connector *connector, | |
4172 | int hdisplay, int vdisplay) | |
4173 | { | |
4174 | int i, count, num_modes = 0; | |
b1f559ec | 4175 | struct drm_display_mode *mode; |
f0fda0a4 ZY |
4176 | struct drm_device *dev = connector->dev; |
4177 | ||
fbb40b28 | 4178 | count = ARRAY_SIZE(drm_dmt_modes); |
f0fda0a4 ZY |
4179 | if (hdisplay < 0) |
4180 | hdisplay = 0; | |
4181 | if (vdisplay < 0) | |
4182 | vdisplay = 0; | |
4183 | ||
4184 | for (i = 0; i < count; i++) { | |
b1f559ec | 4185 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
f0fda0a4 ZY |
4186 | if (hdisplay && vdisplay) { |
4187 | /* | |
4188 | * Only when two are valid, they will be used to check | |
4189 | * whether the mode should be added to the mode list of | |
4190 | * the connector. | |
4191 | */ | |
4192 | if (ptr->hdisplay > hdisplay || | |
4193 | ptr->vdisplay > vdisplay) | |
4194 | continue; | |
4195 | } | |
f985dedb AJ |
4196 | if (drm_mode_vrefresh(ptr) > 61) |
4197 | continue; | |
f0fda0a4 ZY |
4198 | mode = drm_mode_duplicate(dev, ptr); |
4199 | if (mode) { | |
4200 | drm_mode_probed_add(connector, mode); | |
4201 | num_modes++; | |
4202 | } | |
4203 | } | |
4204 | return num_modes; | |
4205 | } | |
4206 | EXPORT_SYMBOL(drm_add_modes_noedid); | |
10a85120 | 4207 | |
db6cf833 TR |
4208 | /** |
4209 | * drm_set_preferred_mode - Sets the preferred mode of a connector | |
4210 | * @connector: connector whose mode list should be processed | |
4211 | * @hpref: horizontal resolution of preferred mode | |
4212 | * @vpref: vertical resolution of preferred mode | |
4213 | * | |
4214 | * Marks a mode as preferred if it matches the resolution specified by @hpref | |
4215 | * and @vpref. | |
4216 | */ | |
3cf70daf GH |
4217 | void drm_set_preferred_mode(struct drm_connector *connector, |
4218 | int hpref, int vpref) | |
4219 | { | |
4220 | struct drm_display_mode *mode; | |
4221 | ||
4222 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
db6cf833 | 4223 | if (mode->hdisplay == hpref && |
9d3de138 | 4224 | mode->vdisplay == vpref) |
3cf70daf GH |
4225 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
4226 | } | |
4227 | } | |
4228 | EXPORT_SYMBOL(drm_set_preferred_mode); | |
4229 | ||
10a85120 TR |
4230 | /** |
4231 | * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with | |
4232 | * data from a DRM display mode | |
4233 | * @frame: HDMI AVI infoframe | |
4234 | * @mode: DRM display mode | |
4235 | * | |
db6cf833 | 4236 | * Return: 0 on success or a negative error code on failure. |
10a85120 TR |
4237 | */ |
4238 | int | |
4239 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, | |
4240 | const struct drm_display_mode *mode) | |
4241 | { | |
4242 | int err; | |
4243 | ||
4244 | if (!frame || !mode) | |
4245 | return -EINVAL; | |
4246 | ||
4247 | err = hdmi_avi_infoframe_init(frame); | |
4248 | if (err < 0) | |
4249 | return err; | |
4250 | ||
bf02db99 DL |
4251 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
4252 | frame->pixel_repeat = 1; | |
4253 | ||
10a85120 | 4254 | frame->video_code = drm_match_cea_mode(mode); |
10a85120 TR |
4255 | |
4256 | frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; | |
0967e6a5 | 4257 | |
69ab6d35 VK |
4258 | /* |
4259 | * Populate picture aspect ratio from either | |
4260 | * user input (if specified) or from the CEA mode list. | |
4261 | */ | |
4262 | if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || | |
4263 | mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) | |
4264 | frame->picture_aspect = mode->picture_aspect_ratio; | |
4265 | else if (frame->video_code > 0) | |
0967e6a5 VK |
4266 | frame->picture_aspect = drm_get_cea_aspect_ratio( |
4267 | frame->video_code); | |
4268 | ||
10a85120 | 4269 | frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; |
24d01805 | 4270 | frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; |
10a85120 TR |
4271 | |
4272 | return 0; | |
4273 | } | |
4274 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); | |
83dd0008 | 4275 | |
4eed4a0a DL |
4276 | static enum hdmi_3d_structure |
4277 | s3d_structure_from_display_mode(const struct drm_display_mode *mode) | |
4278 | { | |
4279 | u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; | |
4280 | ||
4281 | switch (layout) { | |
4282 | case DRM_MODE_FLAG_3D_FRAME_PACKING: | |
4283 | return HDMI_3D_STRUCTURE_FRAME_PACKING; | |
4284 | case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: | |
4285 | return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; | |
4286 | case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: | |
4287 | return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; | |
4288 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: | |
4289 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; | |
4290 | case DRM_MODE_FLAG_3D_L_DEPTH: | |
4291 | return HDMI_3D_STRUCTURE_L_DEPTH; | |
4292 | case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: | |
4293 | return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; | |
4294 | case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: | |
4295 | return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; | |
4296 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: | |
4297 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; | |
4298 | default: | |
4299 | return HDMI_3D_STRUCTURE_INVALID; | |
4300 | } | |
4301 | } | |
4302 | ||
83dd0008 LD |
4303 | /** |
4304 | * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with | |
4305 | * data from a DRM display mode | |
4306 | * @frame: HDMI vendor infoframe | |
4307 | * @mode: DRM display mode | |
4308 | * | |
4309 | * Note that there's is a need to send HDMI vendor infoframes only when using a | |
4310 | * 4k or stereoscopic 3D mode. So when giving any other mode as input this | |
4311 | * function will return -EINVAL, error that can be safely ignored. | |
4312 | * | |
db6cf833 | 4313 | * Return: 0 on success or a negative error code on failure. |
83dd0008 LD |
4314 | */ |
4315 | int | |
4316 | drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, | |
4317 | const struct drm_display_mode *mode) | |
4318 | { | |
4319 | int err; | |
4eed4a0a | 4320 | u32 s3d_flags; |
83dd0008 LD |
4321 | u8 vic; |
4322 | ||
4323 | if (!frame || !mode) | |
4324 | return -EINVAL; | |
4325 | ||
4326 | vic = drm_match_hdmi_mode(mode); | |
4eed4a0a DL |
4327 | s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; |
4328 | ||
4329 | if (!vic && !s3d_flags) | |
4330 | return -EINVAL; | |
4331 | ||
4332 | if (vic && s3d_flags) | |
83dd0008 LD |
4333 | return -EINVAL; |
4334 | ||
4335 | err = hdmi_vendor_infoframe_init(frame); | |
4336 | if (err < 0) | |
4337 | return err; | |
4338 | ||
4eed4a0a DL |
4339 | if (vic) |
4340 | frame->vic = vic; | |
4341 | else | |
4342 | frame->s3d_struct = s3d_structure_from_display_mode(mode); | |
83dd0008 LD |
4343 | |
4344 | return 0; | |
4345 | } | |
4346 | EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); | |
40d9b043 | 4347 | |
5e546cd5 DA |
4348 | static int drm_parse_tiled_block(struct drm_connector *connector, |
4349 | struct displayid_block *block) | |
4350 | { | |
4351 | struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; | |
4352 | u16 w, h; | |
4353 | u8 tile_v_loc, tile_h_loc; | |
4354 | u8 num_v_tile, num_h_tile; | |
4355 | struct drm_tile_group *tg; | |
4356 | ||
4357 | w = tile->tile_size[0] | tile->tile_size[1] << 8; | |
4358 | h = tile->tile_size[2] | tile->tile_size[3] << 8; | |
4359 | ||
4360 | num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); | |
4361 | num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); | |
4362 | tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); | |
4363 | tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); | |
4364 | ||
4365 | connector->has_tile = true; | |
4366 | if (tile->tile_cap & 0x80) | |
4367 | connector->tile_is_single_monitor = true; | |
4368 | ||
4369 | connector->num_h_tile = num_h_tile + 1; | |
4370 | connector->num_v_tile = num_v_tile + 1; | |
4371 | connector->tile_h_loc = tile_h_loc; | |
4372 | connector->tile_v_loc = tile_v_loc; | |
4373 | connector->tile_h_size = w + 1; | |
4374 | connector->tile_v_size = h + 1; | |
4375 | ||
4376 | DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); | |
4377 | DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); | |
4378 | DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", | |
4379 | num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); | |
4380 | DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); | |
4381 | ||
4382 | tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); | |
4383 | if (!tg) { | |
4384 | tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); | |
4385 | } | |
4386 | if (!tg) | |
4387 | return -ENOMEM; | |
4388 | ||
4389 | if (connector->tile_group != tg) { | |
4390 | /* if we haven't got a pointer, | |
4391 | take the reference, drop ref to old tile group */ | |
4392 | if (connector->tile_group) { | |
4393 | drm_mode_put_tile_group(connector->dev, connector->tile_group); | |
4394 | } | |
4395 | connector->tile_group = tg; | |
4396 | } else | |
4397 | /* if same tile group, then release the ref we just took. */ | |
4398 | drm_mode_put_tile_group(connector->dev, tg); | |
4399 | return 0; | |
4400 | } | |
4401 | ||
40d9b043 DA |
4402 | static int drm_parse_display_id(struct drm_connector *connector, |
4403 | u8 *displayid, int length, | |
4404 | bool is_edid_extension) | |
4405 | { | |
4406 | /* if this is an EDID extension the first byte will be 0x70 */ | |
4407 | int idx = 0; | |
40d9b043 | 4408 | struct displayid_block *block; |
5e546cd5 | 4409 | int ret; |
40d9b043 DA |
4410 | |
4411 | if (is_edid_extension) | |
4412 | idx = 1; | |
4413 | ||
c9729177 DA |
4414 | ret = validate_displayid(displayid, length, idx); |
4415 | if (ret) | |
4416 | return ret; | |
40d9b043 | 4417 | |
3a4a2ea3 TB |
4418 | idx += sizeof(struct displayid_hdr); |
4419 | while (block = (struct displayid_block *)&displayid[idx], | |
4420 | idx + sizeof(struct displayid_block) <= length && | |
4421 | idx + sizeof(struct displayid_block) + block->num_bytes <= length && | |
4422 | block->num_bytes > 0) { | |
4423 | idx += block->num_bytes + sizeof(struct displayid_block); | |
4424 | DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", | |
4425 | block->tag, block->rev, block->num_bytes); | |
4426 | ||
4427 | switch (block->tag) { | |
4428 | case DATA_BLOCK_TILED_DISPLAY: | |
4429 | ret = drm_parse_tiled_block(connector, block); | |
4430 | if (ret) | |
4431 | return ret; | |
4432 | break; | |
a39ed680 DA |
4433 | case DATA_BLOCK_TYPE_1_DETAILED_TIMING: |
4434 | /* handled in mode gathering code. */ | |
4435 | break; | |
3a4a2ea3 TB |
4436 | default: |
4437 | DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); | |
4438 | break; | |
4439 | } | |
40d9b043 DA |
4440 | } |
4441 | return 0; | |
4442 | } | |
4443 | ||
4444 | static void drm_get_displayid(struct drm_connector *connector, | |
4445 | struct edid *edid) | |
4446 | { | |
4447 | void *displayid = NULL; | |
4448 | int ret; | |
4449 | connector->has_tile = false; | |
4450 | displayid = drm_find_displayid_extension(edid); | |
4451 | if (!displayid) { | |
4452 | /* drop reference to any tile group we had */ | |
4453 | goto out_drop_ref; | |
4454 | } | |
4455 | ||
4456 | ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); | |
4457 | if (ret < 0) | |
4458 | goto out_drop_ref; | |
4459 | if (!connector->has_tile) | |
4460 | goto out_drop_ref; | |
4461 | return; | |
4462 | out_drop_ref: | |
4463 | if (connector->tile_group) { | |
4464 | drm_mode_put_tile_group(connector->dev, connector->tile_group); | |
4465 | connector->tile_group = NULL; | |
4466 | } | |
4467 | return; | |
4468 | } |