arch/arm64/include/asm/processor.h

   1 /*
   2  * Based on arch/arm/include/asm/processor.h
   3  *
   4  * Copyright (C) 1995-1999 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_PROCESSOR_H
  20 #define __ASM_PROCESSOR_H
  21
  22 #define TASK_SIZE_64            (UL(1) << VA_BITS)
  23
  24 #ifndef __ASSEMBLY__
  25
  26 /*
  27  * Default implementation of macro that returns current
  28  * instruction pointer ("program counter").
  29  */
  30 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  31
  32 #ifdef __KERNEL__
  33
  34 #include <linux/string.h>
  35
  36 #include <asm/alternative.h>
  37 #include <asm/fpsimd.h>
  38 #include <asm/hw_breakpoint.h>
  39 #include <asm/lse.h>
  40 #include <asm/pgtable-hwdef.h>
  41 #include <asm/ptrace.h>
  42 #include <asm/types.h>
  43
  44 /*
  45  * TASK_SIZE - the maximum size of a user space task.
  46  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
  47  */
  48 #ifdef CONFIG_COMPAT
  49 #define TASK_SIZE_32            UL(0x100000000)
  50 #define TASK_SIZE               (test_thread_flag(TIF_32BIT) ? \
  51                                 TASK_SIZE_32 : TASK_SIZE_64)
  52 #define TASK_SIZE_OF(tsk)       (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
  53                                 TASK_SIZE_32 : TASK_SIZE_64)
  54 #else
  55 #define TASK_SIZE               TASK_SIZE_64
  56 #endif /* CONFIG_COMPAT */
  57
  58 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 4))
  59
  60 #define STACK_TOP_MAX           TASK_SIZE_64
  61 #ifdef CONFIG_COMPAT
  62 #define AARCH32_VECTORS_BASE    0xffff0000
  63 #define STACK_TOP               (test_thread_flag(TIF_32BIT) ? \
  64                                 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
  65 #else
  66 #define STACK_TOP               STACK_TOP_MAX
  67 #endif /* CONFIG_COMPAT */
  68
  69 extern phys_addr_t arm64_dma_phys_limit;
  70 #define ARCH_LOW_ADDRESS_LIMIT  (arm64_dma_phys_limit - 1)
  71
  72 struct debug_info {
  73 #ifdef CONFIG_HAVE_HW_BREAKPOINT
  74         /* Have we suspended stepping by a debugger? */
  75         int                     suspended_step;
  76         /* Allow breakpoints and watchpoints to be disabled for this thread. */
  77         int                     bps_disabled;
  78         int                     wps_disabled;
  79         /* Hardware breakpoints pinned to this task. */
  80         struct perf_event       *hbp_break[ARM_MAX_BRP];
  81         struct perf_event       *hbp_watch[ARM_MAX_WRP];
  82 #endif
  83 };
  84
  85 struct cpu_context {
  86         unsigned long x19;
  87         unsigned long x20;
  88         unsigned long x21;
  89         unsigned long x22;
  90         unsigned long x23;
  91         unsigned long x24;
  92         unsigned long x25;
  93         unsigned long x26;
  94         unsigned long x27;
  95         unsigned long x28;
  96         unsigned long fp;
  97         unsigned long sp;
  98         unsigned long pc;
  99 };
 100
 101 struct thread_struct {
 102         struct cpu_context      cpu_context;    /* cpu context */
 103         unsigned long           tp_value;       /* TLS register */
 104 #ifdef CONFIG_COMPAT
 105         unsigned long           tp2_value;
 106 #endif
 107         struct fpsimd_state     fpsimd_state;
 108         void                    *sve_state;     /* SVE registers, if any */
 109         unsigned int            sve_vl;         /* SVE vector length */
 110         unsigned long           fault_address;  /* fault info */
 111         unsigned long           fault_code;     /* ESR_EL1 value */
 112         struct debug_info       debug;          /* debugging */
 113 };
 114
 115 #ifdef CONFIG_COMPAT
 116 #define task_user_tls(t)                                                \
 117 ({                                                                      \
 118         unsigned long *__tls;                                           \
 119         if (is_compat_thread(task_thread_info(t)))                      \
 120                 __tls = &(t)->thread.tp2_value;                         \
 121         else                                                            \
 122                 __tls = &(t)->thread.tp_value;                          \
 123         __tls;                                                          \
 124  })
 125 #else
 126 #define task_user_tls(t)        (&(t)->thread.tp_value)
 127 #endif
 128
 129 /* Sync TPIDR_EL0 back to thread_struct for current */
 130 void tls_preserve_current_state(void);
 131
 132 #define INIT_THREAD  {  }
 133
 134 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
 135 {
 136         memset(regs, 0, sizeof(*regs));
 137         forget_syscall(regs);
 138         regs->pc = pc;
 139 }
 140
 141 static inline void start_thread(struct pt_regs *regs, unsigned long pc,
 142                                 unsigned long sp)
 143 {
 144         start_thread_common(regs, pc);
 145         regs->pstate = PSR_MODE_EL0t;
 146         regs->sp = sp;
 147 }
 148
 149 #ifdef CONFIG_COMPAT
 150 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
 151                                        unsigned long sp)
 152 {
 153         start_thread_common(regs, pc);
 154         regs->pstate = COMPAT_PSR_MODE_USR;
 155         if (pc & 1)
 156                 regs->pstate |= COMPAT_PSR_T_BIT;
 157
 158 #ifdef __AARCH64EB__
 159         regs->pstate |= COMPAT_PSR_E_BIT;
 160 #endif
 161
 162         regs->compat_sp = sp;
 163 }
 164 #endif
 165
 166 /* Forward declaration, a strange C thing */
 167 struct task_struct;
 168
 169 /* Free all resources held by a thread. */
 170 extern void release_thread(struct task_struct *);
 171
 172 unsigned long get_wchan(struct task_struct *p);
 173
 174 static inline void cpu_relax(void)
 175 {
 176         asm volatile("yield" ::: "memory");
 177 }
 178
 179 /* Thread switching */
 180 extern struct task_struct *cpu_switch_to(struct task_struct *prev,
 181                                          struct task_struct *next);
 182
 183 #define task_pt_regs(p) \
 184         ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
 185
 186 #define KSTK_EIP(tsk)   ((unsigned long)task_pt_regs(tsk)->pc)
 187 #define KSTK_ESP(tsk)   user_stack_pointer(task_pt_regs(tsk))
 188
 189 /*
 190  * Prefetching support
 191  */
 192 #define ARCH_HAS_PREFETCH
 193 static inline void prefetch(const void *ptr)
 194 {
 195         asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
 196 }
 197
 198 #define ARCH_HAS_PREFETCHW
 199 static inline void prefetchw(const void *ptr)
 200 {
 201         asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
 202 }
 203
 204 #define ARCH_HAS_SPINLOCK_PREFETCH
 205 static inline void spin_lock_prefetch(const void *ptr)
 206 {
 207         asm volatile(ARM64_LSE_ATOMIC_INSN(
 208                      "prfm pstl1strm, %a0",
 209                      "nop") : : "p" (ptr));
 210 }
 211
 212 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 213
 214 #endif
 215
 216 int cpu_enable_pan(void *__unused);
 217 int cpu_enable_cache_maint_trap(void *__unused);
 218
 219 #endif /* __ASSEMBLY__ */
 220 #endif /* __ASM_PROCESSOR_H */