2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
36 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
37 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
39 #define PT_MAX_FULL_LEVELS 4
40 #define CMPXCHG cmpxchg
42 #define CMPXCHG cmpxchg64
43 #define PT_MAX_FULL_LEVELS 2
46 #define pt_element_t u32
47 #define guest_walker guest_walker32
48 #define FNAME(name) paging##32_##name
49 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
50 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
51 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
52 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
53 #define PT_LEVEL_BITS PT32_LEVEL_BITS
54 #define PT_MAX_FULL_LEVELS 2
55 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
56 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
57 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
58 #define CMPXCHG cmpxchg
59 #elif PTTYPE == PTTYPE_EPT
60 #define pt_element_t u64
61 #define guest_walker guest_walkerEPT
62 #define FNAME(name) ept_##name
63 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
64 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
65 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
66 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
67 #define PT_LEVEL_BITS PT64_LEVEL_BITS
68 #define PT_GUEST_DIRTY_SHIFT 9
69 #define PT_GUEST_ACCESSED_SHIFT 8
70 #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
71 #define CMPXCHG cmpxchg64
72 #define PT_MAX_FULL_LEVELS 4
74 #error Invalid PTTYPE value
77 #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
78 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
80 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
81 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
84 * The guest_walker structure emulates the behavior of the hardware page
90 gfn_t table_gfn
[PT_MAX_FULL_LEVELS
];
91 pt_element_t ptes
[PT_MAX_FULL_LEVELS
];
92 pt_element_t prefetch_ptes
[PTE_PREFETCH_NUM
];
93 gpa_t pte_gpa
[PT_MAX_FULL_LEVELS
];
94 pt_element_t __user
*ptep_user
[PT_MAX_FULL_LEVELS
];
95 bool pte_writable
[PT_MAX_FULL_LEVELS
];
99 struct x86_exception fault
;
102 static gfn_t
gpte_to_gfn_lvl(pt_element_t gpte
, int lvl
)
104 return (gpte
& PT_LVL_ADDR_MASK(lvl
)) >> PAGE_SHIFT
;
107 static inline void FNAME(protect_clean_gpte
)(struct kvm_mmu
*mmu
, unsigned *access
,
112 /* dirty bit is not supported, so no need to track it */
113 if (!PT_HAVE_ACCESSED_DIRTY(mmu
))
116 BUILD_BUG_ON(PT_WRITABLE_MASK
!= ACC_WRITE_MASK
);
118 mask
= (unsigned)~ACC_WRITE_MASK
;
119 /* Allow write access to dirty gptes */
120 mask
|= (gpte
>> (PT_GUEST_DIRTY_SHIFT
- PT_WRITABLE_SHIFT
)) &
125 static inline int FNAME(is_present_gpte
)(unsigned long pte
)
127 #if PTTYPE != PTTYPE_EPT
128 return pte
& PT_PRESENT_MASK
;
134 static int FNAME(cmpxchg_gpte
)(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
135 pt_element_t __user
*ptep_user
, unsigned index
,
136 pt_element_t orig_pte
, pt_element_t new_pte
)
143 npages
= get_user_pages_fast((unsigned long)ptep_user
, 1, FOLL_WRITE
, &page
);
144 /* Check if the user is doing something meaningless. */
145 if (unlikely(npages
!= 1))
148 table
= kmap_atomic(page
);
149 ret
= CMPXCHG(&table
[index
], orig_pte
, new_pte
);
150 kunmap_atomic(table
);
152 kvm_release_page_dirty(page
);
154 return (ret
!= orig_pte
);
157 static bool FNAME(prefetch_invalid_gpte
)(struct kvm_vcpu
*vcpu
,
158 struct kvm_mmu_page
*sp
, u64
*spte
,
161 if (is_rsvd_bits_set(vcpu
->arch
.mmu
, gpte
, PT_PAGE_TABLE_LEVEL
))
164 if (!FNAME(is_present_gpte
)(gpte
))
167 /* if accessed bit is not supported prefetch non accessed gpte */
168 if (PT_HAVE_ACCESSED_DIRTY(vcpu
->arch
.mmu
) &&
169 !(gpte
& PT_GUEST_ACCESSED_MASK
))
175 drop_spte(vcpu
->kvm
, spte
);
180 * For PTTYPE_EPT, a page table can be executable but not readable
181 * on supported processors. Therefore, set_spte does not automatically
182 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
183 * to signify readability since it isn't used in the EPT case
185 static inline unsigned FNAME(gpte_access
)(u64 gpte
)
188 #if PTTYPE == PTTYPE_EPT
189 access
= ((gpte
& VMX_EPT_WRITABLE_MASK
) ? ACC_WRITE_MASK
: 0) |
190 ((gpte
& VMX_EPT_EXECUTABLE_MASK
) ? ACC_EXEC_MASK
: 0) |
191 ((gpte
& VMX_EPT_READABLE_MASK
) ? ACC_USER_MASK
: 0);
193 BUILD_BUG_ON(ACC_EXEC_MASK
!= PT_PRESENT_MASK
);
194 BUILD_BUG_ON(ACC_EXEC_MASK
!= 1);
195 access
= gpte
& (PT_WRITABLE_MASK
| PT_USER_MASK
| PT_PRESENT_MASK
);
196 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
197 access
^= (gpte
>> PT64_NX_SHIFT
);
203 static int FNAME(update_accessed_dirty_bits
)(struct kvm_vcpu
*vcpu
,
205 struct guest_walker
*walker
,
208 unsigned level
, index
;
209 pt_element_t pte
, orig_pte
;
210 pt_element_t __user
*ptep_user
;
214 /* dirty/accessed bits are not supported, so no need to update them */
215 if (!PT_HAVE_ACCESSED_DIRTY(mmu
))
218 for (level
= walker
->max_level
; level
>= walker
->level
; --level
) {
219 pte
= orig_pte
= walker
->ptes
[level
- 1];
220 table_gfn
= walker
->table_gfn
[level
- 1];
221 ptep_user
= walker
->ptep_user
[level
- 1];
222 index
= offset_in_page(ptep_user
) / sizeof(pt_element_t
);
223 if (!(pte
& PT_GUEST_ACCESSED_MASK
)) {
224 trace_kvm_mmu_set_accessed_bit(table_gfn
, index
, sizeof(pte
));
225 pte
|= PT_GUEST_ACCESSED_MASK
;
227 if (level
== walker
->level
&& write_fault
&&
228 !(pte
& PT_GUEST_DIRTY_MASK
)) {
229 trace_kvm_mmu_set_dirty_bit(table_gfn
, index
, sizeof(pte
));
230 #if PTTYPE == PTTYPE_EPT
231 if (kvm_arch_write_log_dirty(vcpu
))
234 pte
|= PT_GUEST_DIRTY_MASK
;
240 * If the slot is read-only, simply do not process the accessed
241 * and dirty bits. This is the correct thing to do if the slot
242 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
243 * are only supported if the accessed and dirty bits are already
244 * set in the ROM (so that MMIO writes are never needed).
246 * Note that NPT does not allow this at all and faults, since
247 * it always wants nested page table entries for the guest
248 * page tables to be writable. And EPT works but will simply
249 * overwrite the read-only memory to set the accessed and dirty
252 if (unlikely(!walker
->pte_writable
[level
- 1]))
255 ret
= FNAME(cmpxchg_gpte
)(vcpu
, mmu
, ptep_user
, index
, orig_pte
, pte
);
259 kvm_vcpu_mark_page_dirty(vcpu
, table_gfn
);
260 walker
->ptes
[level
- 1] = pte
;
265 static inline unsigned FNAME(gpte_pkeys
)(struct kvm_vcpu
*vcpu
, u64 gpte
)
269 pte_t pte
= {.pte
= gpte
};
271 pkeys
= pte_flags_pkey(pte_flags(pte
));
277 * Fetch a guest pte for a guest virtual address
279 static int FNAME(walk_addr_generic
)(struct guest_walker
*walker
,
280 struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
281 gva_t addr
, u32 access
)
285 pt_element_t __user
*uninitialized_var(ptep_user
);
287 u64 pt_access
, pte_access
;
288 unsigned index
, accessed_dirty
, pte_pkey
;
289 unsigned nested_access
;
293 u64 walk_nx_mask
= 0;
294 const int write_fault
= access
& PFERR_WRITE_MASK
;
295 const int user_fault
= access
& PFERR_USER_MASK
;
296 const int fetch_fault
= access
& PFERR_FETCH_MASK
;
301 trace_kvm_mmu_pagetable_walk(addr
, access
);
303 walker
->level
= mmu
->root_level
;
304 pte
= mmu
->get_cr3(vcpu
);
305 have_ad
= PT_HAVE_ACCESSED_DIRTY(mmu
);
308 walk_nx_mask
= 1ULL << PT64_NX_SHIFT
;
309 if (walker
->level
== PT32E_ROOT_LEVEL
) {
310 pte
= mmu
->get_pdptr(vcpu
, (addr
>> 30) & 3);
311 trace_kvm_mmu_paging_element(pte
, walker
->level
);
312 if (!FNAME(is_present_gpte
)(pte
))
317 walker
->max_level
= walker
->level
;
318 ASSERT(!(is_long_mode(vcpu
) && !is_pae(vcpu
)));
321 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
322 * by the MOV to CR instruction are treated as reads and do not cause the
323 * processor to set the dirty flag in any EPT paging-structure entry.
325 nested_access
= (have_ad
? PFERR_WRITE_MASK
: 0) | PFERR_USER_MASK
;
332 unsigned long host_addr
;
334 pt_access
= pte_access
;
337 index
= PT_INDEX(addr
, walker
->level
);
338 table_gfn
= gpte_to_gfn(pte
);
339 offset
= index
* sizeof(pt_element_t
);
340 pte_gpa
= gfn_to_gpa(table_gfn
) + offset
;
342 BUG_ON(walker
->level
< 1);
343 walker
->table_gfn
[walker
->level
- 1] = table_gfn
;
344 walker
->pte_gpa
[walker
->level
- 1] = pte_gpa
;
346 real_gfn
= mmu
->translate_gpa(vcpu
, gfn_to_gpa(table_gfn
),
351 * FIXME: This can happen if emulation (for of an INS/OUTS
352 * instruction) triggers a nested page fault. The exit
353 * qualification / exit info field will incorrectly have
354 * "guest page access" as the nested page fault's cause,
355 * instead of "guest page structure access". To fix this,
356 * the x86_exception struct should be augmented with enough
357 * information to fix the exit_qualification or exit_info_1
360 if (unlikely(real_gfn
== UNMAPPED_GVA
))
363 real_gfn
= gpa_to_gfn(real_gfn
);
365 host_addr
= kvm_vcpu_gfn_to_hva_prot(vcpu
, real_gfn
,
366 &walker
->pte_writable
[walker
->level
- 1]);
367 if (unlikely(kvm_is_error_hva(host_addr
)))
370 ptep_user
= (pt_element_t __user
*)((void *)host_addr
+ offset
);
371 if (unlikely(__copy_from_user(&pte
, ptep_user
, sizeof(pte
))))
373 walker
->ptep_user
[walker
->level
- 1] = ptep_user
;
375 trace_kvm_mmu_paging_element(pte
, walker
->level
);
378 * Inverting the NX it lets us AND it like other
381 pte_access
= pt_access
& (pte
^ walk_nx_mask
);
383 if (unlikely(!FNAME(is_present_gpte
)(pte
)))
386 if (unlikely(is_rsvd_bits_set(mmu
, pte
, walker
->level
))) {
387 errcode
= PFERR_RSVD_MASK
| PFERR_PRESENT_MASK
;
391 walker
->ptes
[walker
->level
- 1] = pte
;
392 } while (!is_last_gpte(mmu
, walker
->level
, pte
));
394 pte_pkey
= FNAME(gpte_pkeys
)(vcpu
, pte
);
395 accessed_dirty
= have_ad
? pte_access
& PT_GUEST_ACCESSED_MASK
: 0;
397 /* Convert to ACC_*_MASK flags for struct guest_walker. */
398 walker
->pt_access
= FNAME(gpte_access
)(pt_access
^ walk_nx_mask
);
399 walker
->pte_access
= FNAME(gpte_access
)(pte_access
^ walk_nx_mask
);
400 errcode
= permission_fault(vcpu
, mmu
, walker
->pte_access
, pte_pkey
, access
);
401 if (unlikely(errcode
))
404 gfn
= gpte_to_gfn_lvl(pte
, walker
->level
);
405 gfn
+= (addr
& PT_LVL_OFFSET_MASK(walker
->level
)) >> PAGE_SHIFT
;
407 if (PTTYPE
== 32 && walker
->level
== PT_DIRECTORY_LEVEL
&& is_cpuid_PSE36())
408 gfn
+= pse36_gfn_delta(pte
);
410 real_gpa
= mmu
->translate_gpa(vcpu
, gfn_to_gpa(gfn
), access
, &walker
->fault
);
411 if (real_gpa
== UNMAPPED_GVA
)
414 walker
->gfn
= real_gpa
>> PAGE_SHIFT
;
417 FNAME(protect_clean_gpte
)(mmu
, &walker
->pte_access
, pte
);
420 * On a write fault, fold the dirty bit into accessed_dirty.
421 * For modes without A/D bits support accessed_dirty will be
424 accessed_dirty
&= pte
>>
425 (PT_GUEST_DIRTY_SHIFT
- PT_GUEST_ACCESSED_SHIFT
);
427 if (unlikely(!accessed_dirty
)) {
428 ret
= FNAME(update_accessed_dirty_bits
)(vcpu
, mmu
, walker
, write_fault
);
429 if (unlikely(ret
< 0))
435 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
436 __func__
, (u64
)pte
, walker
->pte_access
, walker
->pt_access
);
440 errcode
|= write_fault
| user_fault
;
441 if (fetch_fault
&& (mmu
->nx
||
442 kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
)))
443 errcode
|= PFERR_FETCH_MASK
;
445 walker
->fault
.vector
= PF_VECTOR
;
446 walker
->fault
.error_code_valid
= true;
447 walker
->fault
.error_code
= errcode
;
449 #if PTTYPE == PTTYPE_EPT
451 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
452 * misconfiguration requires to be injected. The detection is
453 * done by is_rsvd_bits_set() above.
455 * We set up the value of exit_qualification to inject:
456 * [2:0] - Derive from the access bits. The exit_qualification might be
457 * out of date if it is serving an EPT misconfiguration.
458 * [5:3] - Calculated by the page walk of the guest EPT page tables
459 * [7:8] - Derived from [7:8] of real exit_qualification
461 * The other bits are set to 0.
463 if (!(errcode
& PFERR_RSVD_MASK
)) {
464 vcpu
->arch
.exit_qualification
&= 0x180;
466 vcpu
->arch
.exit_qualification
|= EPT_VIOLATION_ACC_WRITE
;
468 vcpu
->arch
.exit_qualification
|= EPT_VIOLATION_ACC_READ
;
470 vcpu
->arch
.exit_qualification
|= EPT_VIOLATION_ACC_INSTR
;
471 vcpu
->arch
.exit_qualification
|= (pte_access
& 0x7) << 3;
474 walker
->fault
.address
= addr
;
475 walker
->fault
.nested_page_fault
= mmu
!= vcpu
->arch
.walk_mmu
;
477 trace_kvm_mmu_walker_error(walker
->fault
.error_code
);
481 static int FNAME(walk_addr
)(struct guest_walker
*walker
,
482 struct kvm_vcpu
*vcpu
, gva_t addr
, u32 access
)
484 return FNAME(walk_addr_generic
)(walker
, vcpu
, vcpu
->arch
.mmu
, addr
,
488 #if PTTYPE != PTTYPE_EPT
489 static int FNAME(walk_addr_nested
)(struct guest_walker
*walker
,
490 struct kvm_vcpu
*vcpu
, gva_t addr
,
493 return FNAME(walk_addr_generic
)(walker
, vcpu
, &vcpu
->arch
.nested_mmu
,
499 FNAME(prefetch_gpte
)(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
500 u64
*spte
, pt_element_t gpte
, bool no_dirty_log
)
506 if (FNAME(prefetch_invalid_gpte
)(vcpu
, sp
, spte
, gpte
))
509 pgprintk("%s: gpte %llx spte %p\n", __func__
, (u64
)gpte
, spte
);
511 gfn
= gpte_to_gfn(gpte
);
512 pte_access
= sp
->role
.access
& FNAME(gpte_access
)(gpte
);
513 FNAME(protect_clean_gpte
)(vcpu
->arch
.mmu
, &pte_access
, gpte
);
514 pfn
= pte_prefetch_gfn_to_pfn(vcpu
, gfn
,
515 no_dirty_log
&& (pte_access
& ACC_WRITE_MASK
));
516 if (is_error_pfn(pfn
))
520 * we call mmu_set_spte() with host_writable = true because
521 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
523 mmu_set_spte(vcpu
, spte
, pte_access
, 0, PT_PAGE_TABLE_LEVEL
, gfn
, pfn
,
529 static void FNAME(update_pte
)(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
530 u64
*spte
, const void *pte
)
532 pt_element_t gpte
= *(const pt_element_t
*)pte
;
534 FNAME(prefetch_gpte
)(vcpu
, sp
, spte
, gpte
, false);
537 static bool FNAME(gpte_changed
)(struct kvm_vcpu
*vcpu
,
538 struct guest_walker
*gw
, int level
)
540 pt_element_t curr_pte
;
541 gpa_t base_gpa
, pte_gpa
= gw
->pte_gpa
[level
- 1];
545 if (level
== PT_PAGE_TABLE_LEVEL
) {
546 mask
= PTE_PREFETCH_NUM
* sizeof(pt_element_t
) - 1;
547 base_gpa
= pte_gpa
& ~mask
;
548 index
= (pte_gpa
- base_gpa
) / sizeof(pt_element_t
);
550 r
= kvm_vcpu_read_guest_atomic(vcpu
, base_gpa
,
551 gw
->prefetch_ptes
, sizeof(gw
->prefetch_ptes
));
552 curr_pte
= gw
->prefetch_ptes
[index
];
554 r
= kvm_vcpu_read_guest_atomic(vcpu
, pte_gpa
,
555 &curr_pte
, sizeof(curr_pte
));
557 return r
|| curr_pte
!= gw
->ptes
[level
- 1];
560 static void FNAME(pte_prefetch
)(struct kvm_vcpu
*vcpu
, struct guest_walker
*gw
,
563 struct kvm_mmu_page
*sp
;
564 pt_element_t
*gptep
= gw
->prefetch_ptes
;
568 sp
= page_header(__pa(sptep
));
570 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
574 return __direct_pte_prefetch(vcpu
, sp
, sptep
);
576 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
579 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
583 if (is_shadow_present_pte(*spte
))
586 if (!FNAME(prefetch_gpte
)(vcpu
, sp
, spte
, gptep
[i
], true))
592 * Fetch a shadow pte for a specific level in the paging hierarchy.
593 * If the guest tries to write a write-protected page, we need to
594 * emulate this operation, return 1 to indicate this case.
596 static int FNAME(fetch
)(struct kvm_vcpu
*vcpu
, gva_t addr
,
597 struct guest_walker
*gw
,
598 int write_fault
, int hlevel
,
599 kvm_pfn_t pfn
, bool map_writable
, bool prefault
)
601 struct kvm_mmu_page
*sp
= NULL
;
602 struct kvm_shadow_walk_iterator it
;
603 unsigned direct_access
, access
= gw
->pt_access
;
606 direct_access
= gw
->pte_access
;
608 top_level
= vcpu
->arch
.mmu
->root_level
;
609 if (top_level
== PT32E_ROOT_LEVEL
)
610 top_level
= PT32_ROOT_LEVEL
;
612 * Verify that the top-level gpte is still there. Since the page
613 * is a root page, it is either write protected (and cannot be
614 * changed from now on) or it is invalid (in which case, we don't
615 * really care if it changes underneath us after this point).
617 if (FNAME(gpte_changed
)(vcpu
, gw
, top_level
))
618 goto out_gpte_changed
;
620 if (!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
))
621 goto out_gpte_changed
;
623 for (shadow_walk_init(&it
, vcpu
, addr
);
624 shadow_walk_okay(&it
) && it
.level
> gw
->level
;
625 shadow_walk_next(&it
)) {
628 clear_sp_write_flooding_count(it
.sptep
);
629 drop_large_spte(vcpu
, it
.sptep
);
632 if (!is_shadow_present_pte(*it
.sptep
)) {
633 table_gfn
= gw
->table_gfn
[it
.level
- 2];
634 sp
= kvm_mmu_get_page(vcpu
, table_gfn
, addr
, it
.level
-1,
639 * Verify that the gpte in the page we've just write
640 * protected is still there.
642 if (FNAME(gpte_changed
)(vcpu
, gw
, it
.level
- 1))
643 goto out_gpte_changed
;
646 link_shadow_page(vcpu
, it
.sptep
, sp
);
650 shadow_walk_okay(&it
) && it
.level
> hlevel
;
651 shadow_walk_next(&it
)) {
654 clear_sp_write_flooding_count(it
.sptep
);
655 validate_direct_spte(vcpu
, it
.sptep
, direct_access
);
657 drop_large_spte(vcpu
, it
.sptep
);
659 if (is_shadow_present_pte(*it
.sptep
))
662 direct_gfn
= gw
->gfn
& ~(KVM_PAGES_PER_HPAGE(it
.level
) - 1);
664 sp
= kvm_mmu_get_page(vcpu
, direct_gfn
, addr
, it
.level
-1,
665 true, direct_access
);
666 link_shadow_page(vcpu
, it
.sptep
, sp
);
669 clear_sp_write_flooding_count(it
.sptep
);
670 ret
= mmu_set_spte(vcpu
, it
.sptep
, gw
->pte_access
, write_fault
,
671 it
.level
, gw
->gfn
, pfn
, prefault
, map_writable
);
672 FNAME(pte_prefetch
)(vcpu
, gw
, it
.sptep
);
677 kvm_release_pfn_clean(pfn
);
682 * To see whether the mapped gfn can write its page table in the current
685 * It is the helper function of FNAME(page_fault). When guest uses large page
686 * size to map the writable gfn which is used as current page table, we should
687 * force kvm to use small page size to map it because new shadow page will be
688 * created when kvm establishes shadow page table that stop kvm using large
689 * page size. Do it early can avoid unnecessary #PF and emulation.
691 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
692 * currently used as its page table.
694 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
695 * since the PDPT is always shadowed, that means, we can not use large page
696 * size to map the gfn which is used as PDPT.
699 FNAME(is_self_change_mapping
)(struct kvm_vcpu
*vcpu
,
700 struct guest_walker
*walker
, int user_fault
,
701 bool *write_fault_to_shadow_pgtable
)
704 gfn_t mask
= ~(KVM_PAGES_PER_HPAGE(walker
->level
) - 1);
705 bool self_changed
= false;
707 if (!(walker
->pte_access
& ACC_WRITE_MASK
||
708 (!is_write_protection(vcpu
) && !user_fault
)))
711 for (level
= walker
->level
; level
<= walker
->max_level
; level
++) {
712 gfn_t gfn
= walker
->gfn
^ walker
->table_gfn
[level
- 1];
714 self_changed
|= !(gfn
& mask
);
715 *write_fault_to_shadow_pgtable
|= !gfn
;
722 * Page fault handler. There are several causes for a page fault:
723 * - there is no shadow pte for the guest pte
724 * - write access through a shadow pte marked read only so that we can set
726 * - write access to a shadow pte marked read only so we can update the page
727 * dirty bitmap, when userspace requests it
728 * - mmio access; in this case we will never install a present shadow pte
729 * - normal guest page fault due to the guest pte marked not present, not
730 * writable, or not executable
732 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
733 * a negative value on error.
735 static int FNAME(page_fault
)(struct kvm_vcpu
*vcpu
, gva_t addr
, u32 error_code
,
738 int write_fault
= error_code
& PFERR_WRITE_MASK
;
739 int user_fault
= error_code
& PFERR_USER_MASK
;
740 struct guest_walker walker
;
743 int level
= PT_PAGE_TABLE_LEVEL
;
744 bool force_pt_level
= false;
745 unsigned long mmu_seq
;
746 bool map_writable
, is_self_change_mapping
;
748 pgprintk("%s: addr %lx err %x\n", __func__
, addr
, error_code
);
750 r
= mmu_topup_memory_caches(vcpu
);
755 * If PFEC.RSVD is set, this is a shadow page fault.
756 * The bit needs to be cleared before walking guest page tables.
758 error_code
&= ~PFERR_RSVD_MASK
;
761 * Look up the guest pte for the faulting address.
763 r
= FNAME(walk_addr
)(&walker
, vcpu
, addr
, error_code
);
766 * The page is not mapped by the guest. Let the guest handle it.
769 pgprintk("%s: guest page fault\n", __func__
);
771 inject_page_fault(vcpu
, &walker
.fault
);
776 if (page_fault_handle_page_track(vcpu
, error_code
, walker
.gfn
)) {
777 shadow_page_table_clear_flood(vcpu
, addr
);
778 return RET_PF_EMULATE
;
781 vcpu
->arch
.write_fault_to_shadow_pgtable
= false;
783 is_self_change_mapping
= FNAME(is_self_change_mapping
)(vcpu
,
784 &walker
, user_fault
, &vcpu
->arch
.write_fault_to_shadow_pgtable
);
786 if (walker
.level
>= PT_DIRECTORY_LEVEL
&& !is_self_change_mapping
) {
787 level
= mapping_level(vcpu
, walker
.gfn
, &force_pt_level
);
788 if (likely(!force_pt_level
)) {
789 level
= min(walker
.level
, level
);
790 walker
.gfn
= walker
.gfn
& ~(KVM_PAGES_PER_HPAGE(level
) - 1);
793 force_pt_level
= true;
795 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
798 if (try_async_pf(vcpu
, prefault
, walker
.gfn
, addr
, &pfn
, write_fault
,
802 if (handle_abnormal_pfn(vcpu
, addr
, walker
.gfn
, pfn
, walker
.pte_access
, &r
))
806 * Do not change pte_access if the pfn is a mmio page, otherwise
807 * we will cache the incorrect access into mmio spte.
809 if (write_fault
&& !(walker
.pte_access
& ACC_WRITE_MASK
) &&
810 !is_write_protection(vcpu
) && !user_fault
&&
811 !is_noslot_pfn(pfn
)) {
812 walker
.pte_access
|= ACC_WRITE_MASK
;
813 walker
.pte_access
&= ~ACC_USER_MASK
;
816 * If we converted a user page to a kernel page,
817 * so that the kernel can write to it when cr0.wp=0,
818 * then we should prevent the kernel from executing it
819 * if SMEP is enabled.
821 if (kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
))
822 walker
.pte_access
&= ~ACC_EXEC_MASK
;
825 spin_lock(&vcpu
->kvm
->mmu_lock
);
826 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
829 kvm_mmu_audit(vcpu
, AUDIT_PRE_PAGE_FAULT
);
830 if (make_mmu_pages_available(vcpu
) < 0)
833 transparent_hugepage_adjust(vcpu
, &walker
.gfn
, &pfn
, &level
);
834 r
= FNAME(fetch
)(vcpu
, addr
, &walker
, write_fault
,
835 level
, pfn
, map_writable
, prefault
);
836 ++vcpu
->stat
.pf_fixed
;
837 kvm_mmu_audit(vcpu
, AUDIT_POST_PAGE_FAULT
);
838 spin_unlock(&vcpu
->kvm
->mmu_lock
);
843 spin_unlock(&vcpu
->kvm
->mmu_lock
);
844 kvm_release_pfn_clean(pfn
);
848 static gpa_t
FNAME(get_level1_sp_gpa
)(struct kvm_mmu_page
*sp
)
852 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
855 offset
= sp
->role
.quadrant
<< PT64_LEVEL_BITS
;
857 return gfn_to_gpa(sp
->gfn
) + offset
* sizeof(pt_element_t
);
860 static void FNAME(invlpg
)(struct kvm_vcpu
*vcpu
, gva_t gva
, hpa_t root_hpa
)
862 struct kvm_shadow_walk_iterator iterator
;
863 struct kvm_mmu_page
*sp
;
867 vcpu_clear_mmio_info(vcpu
, gva
);
870 * No need to check return value here, rmap_can_add() can
871 * help us to skip pte prefetch later.
873 mmu_topup_memory_caches(vcpu
);
875 if (!VALID_PAGE(root_hpa
)) {
880 spin_lock(&vcpu
->kvm
->mmu_lock
);
881 for_each_shadow_entry_using_root(vcpu
, root_hpa
, gva
, iterator
) {
882 level
= iterator
.level
;
883 sptep
= iterator
.sptep
;
885 sp
= page_header(__pa(sptep
));
886 if (is_last_spte(*sptep
, level
)) {
893 pte_gpa
= FNAME(get_level1_sp_gpa
)(sp
);
894 pte_gpa
+= (sptep
- sp
->spt
) * sizeof(pt_element_t
);
896 if (mmu_page_zap_pte(vcpu
->kvm
, sp
, sptep
))
897 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
,
898 sp
->gfn
, KVM_PAGES_PER_HPAGE(sp
->role
.level
));
900 if (!rmap_can_add(vcpu
))
903 if (kvm_vcpu_read_guest_atomic(vcpu
, pte_gpa
, &gpte
,
904 sizeof(pt_element_t
)))
907 FNAME(update_pte
)(vcpu
, sp
, sptep
, &gpte
);
910 if (!is_shadow_present_pte(*sptep
) || !sp
->unsync_children
)
913 spin_unlock(&vcpu
->kvm
->mmu_lock
);
916 static gpa_t
FNAME(gva_to_gpa
)(struct kvm_vcpu
*vcpu
, gva_t vaddr
, u32 access
,
917 struct x86_exception
*exception
)
919 struct guest_walker walker
;
920 gpa_t gpa
= UNMAPPED_GVA
;
923 r
= FNAME(walk_addr
)(&walker
, vcpu
, vaddr
, access
);
926 gpa
= gfn_to_gpa(walker
.gfn
);
927 gpa
|= vaddr
& ~PAGE_MASK
;
928 } else if (exception
)
929 *exception
= walker
.fault
;
934 #if PTTYPE != PTTYPE_EPT
935 static gpa_t
FNAME(gva_to_gpa_nested
)(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
937 struct x86_exception
*exception
)
939 struct guest_walker walker
;
940 gpa_t gpa
= UNMAPPED_GVA
;
943 r
= FNAME(walk_addr_nested
)(&walker
, vcpu
, vaddr
, access
);
946 gpa
= gfn_to_gpa(walker
.gfn
);
947 gpa
|= vaddr
& ~PAGE_MASK
;
948 } else if (exception
)
949 *exception
= walker
.fault
;
956 * Using the cached information from sp->gfns is safe because:
957 * - The spte has a reference to the struct page, so the pfn for a given gfn
958 * can't change unless all sptes pointing to it are nuked first.
961 * We should flush all tlbs if spte is dropped even though guest is
962 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
963 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
964 * used by guest then tlbs are not flushed, so guest is allowed to access the
966 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
968 static int FNAME(sync_page
)(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
970 int i
, nr_present
= 0;
973 int set_spte_ret
= 0;
975 /* direct kvm_mmu_page can not be unsync. */
976 BUG_ON(sp
->role
.direct
);
978 first_pte_gpa
= FNAME(get_level1_sp_gpa
)(sp
);
980 for (i
= 0; i
< PT64_ENT_PER_PAGE
; i
++) {
989 pte_gpa
= first_pte_gpa
+ i
* sizeof(pt_element_t
);
991 if (kvm_vcpu_read_guest_atomic(vcpu
, pte_gpa
, &gpte
,
992 sizeof(pt_element_t
)))
995 if (FNAME(prefetch_invalid_gpte
)(vcpu
, sp
, &sp
->spt
[i
], gpte
)) {
997 * Update spte before increasing tlbs_dirty to make
998 * sure no tlb flush is lost after spte is zapped; see
999 * the comments in kvm_flush_remote_tlbs().
1002 vcpu
->kvm
->tlbs_dirty
++;
1006 gfn
= gpte_to_gfn(gpte
);
1007 pte_access
= sp
->role
.access
;
1008 pte_access
&= FNAME(gpte_access
)(gpte
);
1009 FNAME(protect_clean_gpte
)(vcpu
->arch
.mmu
, &pte_access
, gpte
);
1011 if (sync_mmio_spte(vcpu
, &sp
->spt
[i
], gfn
, pte_access
,
1015 if (gfn
!= sp
->gfns
[i
]) {
1016 drop_spte(vcpu
->kvm
, &sp
->spt
[i
]);
1018 * The same as above where we are doing
1019 * prefetch_invalid_gpte().
1022 vcpu
->kvm
->tlbs_dirty
++;
1028 host_writable
= sp
->spt
[i
] & SPTE_HOST_WRITEABLE
;
1030 set_spte_ret
|= set_spte(vcpu
, &sp
->spt
[i
],
1031 pte_access
, PT_PAGE_TABLE_LEVEL
,
1032 gfn
, spte_to_pfn(sp
->spt
[i
]),
1033 true, false, host_writable
);
1036 if (set_spte_ret
& SET_SPTE_NEED_REMOTE_TLB_FLUSH
)
1037 kvm_flush_remote_tlbs(vcpu
->kvm
);
1045 #undef PT_BASE_ADDR_MASK
1047 #undef PT_LVL_ADDR_MASK
1048 #undef PT_LVL_OFFSET_MASK
1049 #undef PT_LEVEL_BITS
1050 #undef PT_MAX_FULL_LEVELS
1052 #undef gpte_to_gfn_lvl
1054 #undef PT_GUEST_ACCESSED_MASK
1055 #undef PT_GUEST_DIRTY_MASK
1056 #undef PT_GUEST_DIRTY_SHIFT
1057 #undef PT_GUEST_ACCESSED_SHIFT
1058 #undef PT_HAVE_ACCESSED_DIRTY