1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Yaniv Kamay <yaniv@qumranet.com>
12 * Avi Kivity <avi@qumranet.com>
15 #define pr_fmt(fmt) "SVM: " fmt
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/hashtable.h>
36 #include <linux/frame.h>
37 #include <linux/psp-sev.h>
38 #include <linux/file.h>
39 #include <linux/pagemap.h>
40 #include <linux/swap.h>
43 #include <asm/perf_event.h>
44 #include <asm/tlbflush.h>
46 #include <asm/debugreg.h>
47 #include <asm/kvm_para.h>
48 #include <asm/irq_remapping.h>
49 #include <asm/spec-ctrl.h>
51 #include <asm/virtext.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
59 static const struct x86_cpu_id svm_cpu_id
[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
63 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
65 #define IOPM_ALLOC_ORDER 2
66 #define MSRPM_ALLOC_ORDER 1
68 #define SEG_TYPE_LDT 2
69 #define SEG_TYPE_BUSY_TSS16 3
71 #define SVM_FEATURE_NPT (1 << 0)
72 #define SVM_FEATURE_LBRV (1 << 1)
73 #define SVM_FEATURE_SVML (1 << 2)
74 #define SVM_FEATURE_NRIP (1 << 3)
75 #define SVM_FEATURE_TSC_RATE (1 << 4)
76 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
77 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
78 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
79 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
81 #define SVM_AVIC_DOORBELL 0xc001011b
83 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
84 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
85 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
87 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
89 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
90 #define TSC_RATIO_MIN 0x0000000000000001ULL
91 #define TSC_RATIO_MAX 0x000000ffffffffffULL
93 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
96 * 0xff is broadcast, so the max index allowed for physical APIC ID
97 * table is 0xfe. APIC IDs above 0xff are reserved.
99 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
101 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
102 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
103 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
105 /* AVIC GATAG is encoded using VM and VCPU IDs */
106 #define AVIC_VCPU_ID_BITS 8
107 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
109 #define AVIC_VM_ID_BITS 24
110 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
111 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
113 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
114 (y & AVIC_VCPU_ID_MASK))
115 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
116 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
118 static bool erratum_383_found __read_mostly
;
120 static const u32 host_save_user_msrs
[] = {
122 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
125 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
129 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
131 struct kvm_sev_info
{
132 bool active
; /* SEV enabled guest */
133 unsigned int asid
; /* ASID used for this guest */
134 unsigned int handle
; /* SEV firmware handle */
135 int fd
; /* SEV device fd */
136 unsigned long pages_locked
; /* Number of pages locked */
137 struct list_head regions_list
; /* List of registered regions */
143 /* Struct members for AVIC */
145 struct page
*avic_logical_id_table_page
;
146 struct page
*avic_physical_id_table_page
;
147 struct hlist_node hnode
;
149 struct kvm_sev_info sev_info
;
154 struct nested_state
{
160 /* These are the merged vectors */
163 /* gpa pointers to the real vectors */
167 /* A VMEXIT is required but not yet emulated */
170 /* cache for intercepts of the guest */
173 u32 intercept_exceptions
;
176 /* Nested Paging related state */
180 #define MSRPM_OFFSETS 16
181 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
184 * Set osvw_len to higher value when updated Revision Guides
185 * are published and we know what the new status bits are
187 static uint64_t osvw_len
= 4, osvw_status
;
190 struct kvm_vcpu vcpu
;
192 unsigned long vmcb_pa
;
193 struct svm_cpu_data
*svm_data
;
194 uint64_t asid_generation
;
195 uint64_t sysenter_esp
;
196 uint64_t sysenter_eip
;
203 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
213 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
214 * translated into the appropriate L2_CFG bits on the host to
215 * perform speculative control.
223 struct nested_state nested
;
226 u64 nmi_singlestep_guest_rflags
;
228 unsigned int3_injected
;
229 unsigned long int3_rip
;
231 /* cached guest cpuid flags for faster access */
232 bool nrips_enabled
: 1;
236 struct page
*avic_backing_page
;
237 u64
*avic_physical_id_cache
;
238 bool avic_is_running
;
241 * Per-vcpu list of struct amd_svm_iommu_ir:
242 * This is used mainly to store interrupt remapping information used
243 * when update the vcpu affinity. This avoids the need to scan for
244 * IRTE and try to match ga_tag in the IOMMU driver.
246 struct list_head ir_list
;
247 spinlock_t ir_list_lock
;
249 /* which host CPU was used for running this vcpu */
250 unsigned int last_cpu
;
254 * This is a wrapper of struct amd_iommu_ir_data.
256 struct amd_svm_iommu_ir
{
257 struct list_head node
; /* Used by SVM for per-vcpu ir_list */
258 void *data
; /* Storing pointer to struct amd_ir_data */
261 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
262 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
263 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
265 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
266 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
267 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
268 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
270 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
271 #define TSC_RATIO_DEFAULT 0x0100000000ULL
273 #define MSR_INVALID 0xffffffffU
275 static const struct svm_direct_access_msrs
{
276 u32 index
; /* Index of the MSR */
277 bool always
; /* True if intercept is always on */
278 } direct_access_msrs
[] = {
279 { .index
= MSR_STAR
, .always
= true },
280 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
282 { .index
= MSR_GS_BASE
, .always
= true },
283 { .index
= MSR_FS_BASE
, .always
= true },
284 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
285 { .index
= MSR_LSTAR
, .always
= true },
286 { .index
= MSR_CSTAR
, .always
= true },
287 { .index
= MSR_SYSCALL_MASK
, .always
= true },
289 { .index
= MSR_IA32_SPEC_CTRL
, .always
= false },
290 { .index
= MSR_IA32_PRED_CMD
, .always
= false },
291 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
292 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
293 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
294 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
295 { .index
= MSR_INVALID
, .always
= false },
298 /* enable NPT for AMD64 and X86 with PAE */
299 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
300 static bool npt_enabled
= true;
302 static bool npt_enabled
;
306 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
307 * pause_filter_count: On processors that support Pause filtering(indicated
308 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
309 * count value. On VMRUN this value is loaded into an internal counter.
310 * Each time a pause instruction is executed, this counter is decremented
311 * until it reaches zero at which time a #VMEXIT is generated if pause
312 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
313 * Intercept Filtering for more details.
314 * This also indicate if ple logic enabled.
316 * pause_filter_thresh: In addition, some processor families support advanced
317 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
318 * the amount of time a guest is allowed to execute in a pause loop.
319 * In this mode, a 16-bit pause filter threshold field is added in the
320 * VMCB. The threshold value is a cycle count that is used to reset the
321 * pause counter. As with simple pause filtering, VMRUN loads the pause
322 * count value from VMCB into an internal counter. Then, on each pause
323 * instruction the hardware checks the elapsed number of cycles since
324 * the most recent pause instruction against the pause filter threshold.
325 * If the elapsed cycle count is greater than the pause filter threshold,
326 * then the internal pause count is reloaded from the VMCB and execution
327 * continues. If the elapsed cycle count is less than the pause filter
328 * threshold, then the internal pause count is decremented. If the count
329 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
330 * triggered. If advanced pause filtering is supported and pause filter
331 * threshold field is set to zero, the filter will operate in the simpler,
335 static unsigned short pause_filter_thresh
= KVM_DEFAULT_PLE_GAP
;
336 module_param(pause_filter_thresh
, ushort
, 0444);
338 static unsigned short pause_filter_count
= KVM_SVM_DEFAULT_PLE_WINDOW
;
339 module_param(pause_filter_count
, ushort
, 0444);
341 /* Default doubles per-vcpu window every exit. */
342 static unsigned short pause_filter_count_grow
= KVM_DEFAULT_PLE_WINDOW_GROW
;
343 module_param(pause_filter_count_grow
, ushort
, 0444);
345 /* Default resets per-vcpu window every exit to pause_filter_count. */
346 static unsigned short pause_filter_count_shrink
= KVM_DEFAULT_PLE_WINDOW_SHRINK
;
347 module_param(pause_filter_count_shrink
, ushort
, 0444);
349 /* Default is to compute the maximum so we can never overflow. */
350 static unsigned short pause_filter_count_max
= KVM_SVM_DEFAULT_PLE_WINDOW_MAX
;
351 module_param(pause_filter_count_max
, ushort
, 0444);
353 /* allow nested paging (virtualized MMU) for all guests */
354 static int npt
= true;
355 module_param(npt
, int, S_IRUGO
);
357 /* allow nested virtualization in KVM/SVM */
358 static int nested
= true;
359 module_param(nested
, int, S_IRUGO
);
361 /* enable / disable AVIC */
363 #ifdef CONFIG_X86_LOCAL_APIC
364 module_param(avic
, int, S_IRUGO
);
367 /* enable/disable Virtual VMLOAD VMSAVE */
368 static int vls
= true;
369 module_param(vls
, int, 0444);
371 /* enable/disable Virtual GIF */
372 static int vgif
= true;
373 module_param(vgif
, int, 0444);
375 /* enable/disable SEV support */
376 static int sev
= IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT
);
377 module_param(sev
, int, 0444);
379 static bool __read_mostly dump_invalid_vmcb
= 0;
380 module_param(dump_invalid_vmcb
, bool, 0644);
382 static u8 rsm_ins_bytes
[] = "\x0f\xaa";
384 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
);
385 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
);
386 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
388 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
389 static int nested_svm_intercept(struct vcpu_svm
*svm
);
390 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
391 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
392 bool has_error_code
, u32 error_code
);
395 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
396 pause filter count */
397 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
398 VMCB_ASID
, /* ASID */
399 VMCB_INTR
, /* int_ctl, int_vector */
400 VMCB_NPT
, /* npt_en, nCR3, gPAT */
401 VMCB_CR
, /* CR0, CR3, CR4, EFER */
402 VMCB_DR
, /* DR6, DR7 */
403 VMCB_DT
, /* GDT, IDT */
404 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
405 VMCB_CR2
, /* CR2 only */
406 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
407 VMCB_AVIC
, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
408 * AVIC PHYSICAL_TABLE pointer,
409 * AVIC LOGICAL_TABLE pointer
414 /* TPR and CR2 are always written before VMRUN */
415 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
417 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
419 static unsigned int max_sev_asid
;
420 static unsigned int min_sev_asid
;
421 static unsigned long *sev_asid_bitmap
;
422 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
425 struct list_head list
;
426 unsigned long npages
;
433 static inline struct kvm_svm
*to_kvm_svm(struct kvm
*kvm
)
435 return container_of(kvm
, struct kvm_svm
, kvm
);
438 static inline bool svm_sev_enabled(void)
440 return IS_ENABLED(CONFIG_KVM_AMD_SEV
) ? max_sev_asid
: 0;
443 static inline bool sev_guest(struct kvm
*kvm
)
445 #ifdef CONFIG_KVM_AMD_SEV
446 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
454 static inline int sev_get_asid(struct kvm
*kvm
)
456 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
461 static inline void mark_all_dirty(struct vmcb
*vmcb
)
463 vmcb
->control
.clean
= 0;
466 static inline void mark_all_clean(struct vmcb
*vmcb
)
468 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
469 & ~VMCB_ALWAYS_DIRTY_MASK
;
472 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
474 vmcb
->control
.clean
&= ~(1 << bit
);
477 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
479 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
482 static inline void avic_update_vapic_bar(struct vcpu_svm
*svm
, u64 data
)
484 svm
->vmcb
->control
.avic_vapic_bar
= data
& VMCB_AVIC_APIC_BAR_MASK
;
485 mark_dirty(svm
->vmcb
, VMCB_AVIC
);
488 static inline bool avic_vcpu_is_running(struct kvm_vcpu
*vcpu
)
490 struct vcpu_svm
*svm
= to_svm(vcpu
);
491 u64
*entry
= svm
->avic_physical_id_cache
;
496 return (READ_ONCE(*entry
) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
499 static void recalc_intercepts(struct vcpu_svm
*svm
)
501 struct vmcb_control_area
*c
, *h
;
502 struct nested_state
*g
;
504 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
506 if (!is_guest_mode(&svm
->vcpu
))
509 c
= &svm
->vmcb
->control
;
510 h
= &svm
->nested
.hsave
->control
;
513 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
514 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
515 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
516 c
->intercept
= h
->intercept
| g
->intercept
;
519 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
521 if (is_guest_mode(&svm
->vcpu
))
522 return svm
->nested
.hsave
;
527 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
529 struct vmcb
*vmcb
= get_host_vmcb(svm
);
531 vmcb
->control
.intercept_cr
|= (1U << bit
);
533 recalc_intercepts(svm
);
536 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
538 struct vmcb
*vmcb
= get_host_vmcb(svm
);
540 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
542 recalc_intercepts(svm
);
545 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
547 struct vmcb
*vmcb
= get_host_vmcb(svm
);
549 return vmcb
->control
.intercept_cr
& (1U << bit
);
552 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
554 struct vmcb
*vmcb
= get_host_vmcb(svm
);
556 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
557 | (1 << INTERCEPT_DR1_READ
)
558 | (1 << INTERCEPT_DR2_READ
)
559 | (1 << INTERCEPT_DR3_READ
)
560 | (1 << INTERCEPT_DR4_READ
)
561 | (1 << INTERCEPT_DR5_READ
)
562 | (1 << INTERCEPT_DR6_READ
)
563 | (1 << INTERCEPT_DR7_READ
)
564 | (1 << INTERCEPT_DR0_WRITE
)
565 | (1 << INTERCEPT_DR1_WRITE
)
566 | (1 << INTERCEPT_DR2_WRITE
)
567 | (1 << INTERCEPT_DR3_WRITE
)
568 | (1 << INTERCEPT_DR4_WRITE
)
569 | (1 << INTERCEPT_DR5_WRITE
)
570 | (1 << INTERCEPT_DR6_WRITE
)
571 | (1 << INTERCEPT_DR7_WRITE
);
573 recalc_intercepts(svm
);
576 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
578 struct vmcb
*vmcb
= get_host_vmcb(svm
);
580 vmcb
->control
.intercept_dr
= 0;
582 recalc_intercepts(svm
);
585 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
587 struct vmcb
*vmcb
= get_host_vmcb(svm
);
589 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
591 recalc_intercepts(svm
);
594 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
596 struct vmcb
*vmcb
= get_host_vmcb(svm
);
598 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
600 recalc_intercepts(svm
);
603 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
605 struct vmcb
*vmcb
= get_host_vmcb(svm
);
607 vmcb
->control
.intercept
|= (1ULL << bit
);
609 recalc_intercepts(svm
);
612 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
614 struct vmcb
*vmcb
= get_host_vmcb(svm
);
616 vmcb
->control
.intercept
&= ~(1ULL << bit
);
618 recalc_intercepts(svm
);
621 static inline bool vgif_enabled(struct vcpu_svm
*svm
)
623 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_ENABLE_MASK
);
626 static inline void enable_gif(struct vcpu_svm
*svm
)
628 if (vgif_enabled(svm
))
629 svm
->vmcb
->control
.int_ctl
|= V_GIF_MASK
;
631 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
634 static inline void disable_gif(struct vcpu_svm
*svm
)
636 if (vgif_enabled(svm
))
637 svm
->vmcb
->control
.int_ctl
&= ~V_GIF_MASK
;
639 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
642 static inline bool gif_set(struct vcpu_svm
*svm
)
644 if (vgif_enabled(svm
))
645 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_MASK
);
647 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
650 static unsigned long iopm_base
;
652 struct kvm_ldttss_desc
{
655 unsigned base1
:8, type
:5, dpl
:2, p
:1;
656 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
659 } __attribute__((packed
));
661 struct svm_cpu_data
{
668 struct kvm_ldttss_desc
*tss_desc
;
670 struct page
*save_area
;
671 struct vmcb
*current_vmcb
;
673 /* index = sev_asid, value = vmcb pointer */
674 struct vmcb
**sev_vmcbs
;
677 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
679 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
681 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
682 #define MSRS_RANGE_SIZE 2048
683 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
685 static u32
svm_msrpm_offset(u32 msr
)
690 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
691 if (msr
< msrpm_ranges
[i
] ||
692 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
695 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
696 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
698 /* Now we have the u8 offset - but need the u32 offset */
702 /* MSR not in any range */
706 #define MAX_INST_SIZE 15
708 static inline void clgi(void)
710 asm volatile (__ex("clgi"));
713 static inline void stgi(void)
715 asm volatile (__ex("stgi"));
718 static inline void invlpga(unsigned long addr
, u32 asid
)
720 asm volatile (__ex("invlpga %1, %0") : : "c"(asid
), "a"(addr
));
723 static int get_npt_level(struct kvm_vcpu
*vcpu
)
726 return PT64_ROOT_4LEVEL
;
728 return PT32E_ROOT_LEVEL
;
732 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
734 vcpu
->arch
.efer
= efer
;
735 if (!npt_enabled
&& !(efer
& EFER_LMA
))
738 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
739 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
742 static int is_external_interrupt(u32 info
)
744 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
745 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
748 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
750 struct vcpu_svm
*svm
= to_svm(vcpu
);
753 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
754 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
758 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
760 struct vcpu_svm
*svm
= to_svm(vcpu
);
763 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
765 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
769 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
771 struct vcpu_svm
*svm
= to_svm(vcpu
);
773 if (svm
->vmcb
->control
.next_rip
!= 0) {
774 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
775 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
778 if (!svm
->next_rip
) {
779 if (kvm_emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
781 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
784 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
785 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
786 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
788 kvm_rip_write(vcpu
, svm
->next_rip
);
789 svm_set_interrupt_shadow(vcpu
, 0);
792 static void svm_queue_exception(struct kvm_vcpu
*vcpu
)
794 struct vcpu_svm
*svm
= to_svm(vcpu
);
795 unsigned nr
= vcpu
->arch
.exception
.nr
;
796 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
797 bool reinject
= vcpu
->arch
.exception
.injected
;
798 u32 error_code
= vcpu
->arch
.exception
.error_code
;
801 * If we are within a nested VM we'd better #VMEXIT and let the guest
802 * handle the exception
805 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
808 kvm_deliver_exception_payload(&svm
->vcpu
);
810 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
811 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
814 * For guest debugging where we have to reinject #BP if some
815 * INT3 is guest-owned:
816 * Emulate nRIP by moving RIP forward. Will fail if injection
817 * raises a fault that is not intercepted. Still better than
818 * failing in all cases.
820 skip_emulated_instruction(&svm
->vcpu
);
821 rip
= kvm_rip_read(&svm
->vcpu
);
822 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
823 svm
->int3_injected
= rip
- old_rip
;
826 svm
->vmcb
->control
.event_inj
= nr
828 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
829 | SVM_EVTINJ_TYPE_EXEPT
;
830 svm
->vmcb
->control
.event_inj_err
= error_code
;
833 static void svm_init_erratum_383(void)
839 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
842 /* Use _safe variants to not break nested virtualization */
843 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
849 low
= lower_32_bits(val
);
850 high
= upper_32_bits(val
);
852 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
854 erratum_383_found
= true;
857 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
860 * Guests should see errata 400 and 415 as fixed (assuming that
861 * HLT and IO instructions are intercepted).
863 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
864 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
867 * By increasing VCPU's osvw.length to 3 we are telling the guest that
868 * all osvw.status bits inside that length, including bit 0 (which is
869 * reserved for erratum 298), are valid. However, if host processor's
870 * osvw_len is 0 then osvw_status[0] carries no information. We need to
871 * be conservative here and therefore we tell the guest that erratum 298
872 * is present (because we really don't know).
874 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
875 vcpu
->arch
.osvw
.status
|= 1;
878 static int has_svm(void)
882 if (!cpu_has_svm(&msg
)) {
883 printk(KERN_INFO
"has_svm: %s\n", msg
);
890 static void svm_hardware_disable(void)
892 /* Make sure we clean up behind us */
893 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
894 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
898 amd_pmu_disable_virt();
901 static int svm_hardware_enable(void)
904 struct svm_cpu_data
*sd
;
906 struct desc_struct
*gdt
;
907 int me
= raw_smp_processor_id();
909 rdmsrl(MSR_EFER
, efer
);
910 if (efer
& EFER_SVME
)
914 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
917 sd
= per_cpu(svm_data
, me
);
919 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
923 sd
->asid_generation
= 1;
924 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
925 sd
->next_asid
= sd
->max_asid
+ 1;
926 sd
->min_asid
= max_sev_asid
+ 1;
928 gdt
= get_current_gdt_rw();
929 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
931 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
933 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
935 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
936 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
937 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
944 * Note that it is possible to have a system with mixed processor
945 * revisions and therefore different OSVW bits. If bits are not the same
946 * on different processors then choose the worst case (i.e. if erratum
947 * is present on one processor and not on another then assume that the
948 * erratum is present everywhere).
950 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
951 uint64_t len
, status
= 0;
954 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
956 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
960 osvw_status
= osvw_len
= 0;
964 osvw_status
|= status
;
965 osvw_status
&= (1ULL << osvw_len
) - 1;
968 osvw_status
= osvw_len
= 0;
970 svm_init_erratum_383();
972 amd_pmu_enable_virt();
977 static void svm_cpu_uninit(int cpu
)
979 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
984 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
985 kfree(sd
->sev_vmcbs
);
986 __free_page(sd
->save_area
);
990 static int svm_cpu_init(int cpu
)
992 struct svm_cpu_data
*sd
;
995 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
1000 sd
->save_area
= alloc_page(GFP_KERNEL
);
1004 if (svm_sev_enabled()) {
1006 sd
->sev_vmcbs
= kmalloc_array(max_sev_asid
+ 1,
1013 per_cpu(svm_data
, cpu
) = sd
;
1023 static bool valid_msr_intercept(u32 index
)
1027 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
1028 if (direct_access_msrs
[i
].index
== index
)
1034 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, unsigned msr
)
1041 msrpm
= is_guest_mode(vcpu
) ? to_svm(vcpu
)->nested
.msrpm
:
1042 to_svm(vcpu
)->msrpm
;
1044 offset
= svm_msrpm_offset(msr
);
1045 bit_write
= 2 * (msr
& 0x0f) + 1;
1046 tmp
= msrpm
[offset
];
1048 BUG_ON(offset
== MSR_INVALID
);
1050 return !!test_bit(bit_write
, &tmp
);
1053 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
1054 int read
, int write
)
1056 u8 bit_read
, bit_write
;
1061 * If this warning triggers extend the direct_access_msrs list at the
1062 * beginning of the file
1064 WARN_ON(!valid_msr_intercept(msr
));
1066 offset
= svm_msrpm_offset(msr
);
1067 bit_read
= 2 * (msr
& 0x0f);
1068 bit_write
= 2 * (msr
& 0x0f) + 1;
1069 tmp
= msrpm
[offset
];
1071 BUG_ON(offset
== MSR_INVALID
);
1073 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
1074 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
1076 msrpm
[offset
] = tmp
;
1079 static void svm_vcpu_init_msrpm(u32
*msrpm
)
1083 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
1085 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
1086 if (!direct_access_msrs
[i
].always
)
1089 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
1093 static void add_msr_offset(u32 offset
)
1097 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
1099 /* Offset already in list? */
1100 if (msrpm_offsets
[i
] == offset
)
1103 /* Slot used by another offset? */
1104 if (msrpm_offsets
[i
] != MSR_INVALID
)
1107 /* Add offset to list */
1108 msrpm_offsets
[i
] = offset
;
1114 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1115 * increase MSRPM_OFFSETS in this case.
1120 static void init_msrpm_offsets(void)
1124 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
1126 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
1129 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
1130 BUG_ON(offset
== MSR_INVALID
);
1132 add_msr_offset(offset
);
1136 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
1138 u32
*msrpm
= svm
->msrpm
;
1140 svm
->vmcb
->control
.virt_ext
|= LBR_CTL_ENABLE_MASK
;
1141 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
1142 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
1143 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
1144 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
1147 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
1149 u32
*msrpm
= svm
->msrpm
;
1151 svm
->vmcb
->control
.virt_ext
&= ~LBR_CTL_ENABLE_MASK
;
1152 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
1153 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
1154 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
1155 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
1158 static void disable_nmi_singlestep(struct vcpu_svm
*svm
)
1160 svm
->nmi_singlestep
= false;
1162 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
)) {
1163 /* Clear our flags if they were not set by the guest */
1164 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1165 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_TF
;
1166 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1167 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_RF
;
1172 * This hash table is used to map VM_ID to a struct kvm_svm,
1173 * when handling AMD IOMMU GALOG notification to schedule in
1174 * a particular vCPU.
1176 #define SVM_VM_DATA_HASH_BITS 8
1177 static DEFINE_HASHTABLE(svm_vm_data_hash
, SVM_VM_DATA_HASH_BITS
);
1178 static u32 next_vm_id
= 0;
1179 static bool next_vm_id_wrapped
= 0;
1180 static DEFINE_SPINLOCK(svm_vm_data_hash_lock
);
1183 * This function is called from IOMMU driver to notify
1184 * SVM to schedule in a particular vCPU of a particular VM.
1186 static int avic_ga_log_notifier(u32 ga_tag
)
1188 unsigned long flags
;
1189 struct kvm_svm
*kvm_svm
;
1190 struct kvm_vcpu
*vcpu
= NULL
;
1191 u32 vm_id
= AVIC_GATAG_TO_VMID(ga_tag
);
1192 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(ga_tag
);
1194 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__
, vm_id
, vcpu_id
);
1196 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1197 hash_for_each_possible(svm_vm_data_hash
, kvm_svm
, hnode
, vm_id
) {
1198 if (kvm_svm
->avic_vm_id
!= vm_id
)
1200 vcpu
= kvm_get_vcpu_by_id(&kvm_svm
->kvm
, vcpu_id
);
1203 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1206 * At this point, the IOMMU should have already set the pending
1207 * bit in the vAPIC backing page. So, we just need to schedule
1211 kvm_vcpu_wake_up(vcpu
);
1216 static __init
int sev_hardware_setup(void)
1218 struct sev_user_data_status
*status
;
1221 /* Maximum number of encrypted guests supported simultaneously */
1222 max_sev_asid
= cpuid_ecx(0x8000001F);
1227 /* Minimum ASID value that should be used for SEV guest */
1228 min_sev_asid
= cpuid_edx(0x8000001F);
1230 /* Initialize SEV ASID bitmap */
1231 sev_asid_bitmap
= bitmap_zalloc(max_sev_asid
, GFP_KERNEL
);
1232 if (!sev_asid_bitmap
)
1235 status
= kmalloc(sizeof(*status
), GFP_KERNEL
);
1240 * Check SEV platform status.
1242 * PLATFORM_STATUS can be called in any state, if we failed to query
1243 * the PLATFORM status then either PSP firmware does not support SEV
1244 * feature or SEV firmware is dead.
1246 rc
= sev_platform_status(status
, NULL
);
1250 pr_info("SEV supported\n");
1257 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
1259 struct vcpu_svm
*svm
= to_svm(vcpu
);
1260 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1261 int old
= control
->pause_filter_count
;
1263 control
->pause_filter_count
= __grow_ple_window(old
,
1265 pause_filter_count_grow
,
1266 pause_filter_count_max
);
1268 if (control
->pause_filter_count
!= old
)
1269 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1271 trace_kvm_ple_window_grow(vcpu
->vcpu_id
,
1272 control
->pause_filter_count
, old
);
1275 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
1277 struct vcpu_svm
*svm
= to_svm(vcpu
);
1278 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1279 int old
= control
->pause_filter_count
;
1281 control
->pause_filter_count
=
1282 __shrink_ple_window(old
,
1284 pause_filter_count_shrink
,
1285 pause_filter_count
);
1286 if (control
->pause_filter_count
!= old
)
1287 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1289 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
,
1290 control
->pause_filter_count
, old
);
1293 static __init
int svm_hardware_setup(void)
1296 struct page
*iopm_pages
;
1300 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
1305 iopm_va
= page_address(iopm_pages
);
1306 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
1307 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
1309 init_msrpm_offsets();
1311 if (boot_cpu_has(X86_FEATURE_NX
))
1312 kvm_enable_efer_bits(EFER_NX
);
1314 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
1315 kvm_enable_efer_bits(EFER_FFXSR
);
1317 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1318 kvm_has_tsc_control
= true;
1319 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
1320 kvm_tsc_scaling_ratio_frac_bits
= 32;
1323 /* Check for pause filtering support */
1324 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1325 pause_filter_count
= 0;
1326 pause_filter_thresh
= 0;
1327 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD
)) {
1328 pause_filter_thresh
= 0;
1332 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
1333 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
1337 if (boot_cpu_has(X86_FEATURE_SEV
) &&
1338 IS_ENABLED(CONFIG_KVM_AMD_SEV
)) {
1339 r
= sev_hardware_setup();
1347 for_each_possible_cpu(cpu
) {
1348 r
= svm_cpu_init(cpu
);
1353 if (!boot_cpu_has(X86_FEATURE_NPT
))
1354 npt_enabled
= false;
1356 if (npt_enabled
&& !npt
) {
1357 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
1358 npt_enabled
= false;
1362 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
1369 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1370 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1373 pr_info("AVIC enabled\n");
1375 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1381 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD
) ||
1382 !IS_ENABLED(CONFIG_X86_64
)) {
1385 pr_info("Virtual VMLOAD VMSAVE supported\n");
1390 if (!boot_cpu_has(X86_FEATURE_VGIF
))
1393 pr_info("Virtual GIF supported\n");
1399 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
1404 static __exit
void svm_hardware_unsetup(void)
1408 if (svm_sev_enabled())
1409 bitmap_free(sev_asid_bitmap
);
1411 for_each_possible_cpu(cpu
)
1412 svm_cpu_uninit(cpu
);
1414 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
1418 static void init_seg(struct vmcb_seg
*seg
)
1421 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1422 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1423 seg
->limit
= 0xffff;
1427 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1430 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1431 seg
->limit
= 0xffff;
1435 static u64
svm_read_l1_tsc_offset(struct kvm_vcpu
*vcpu
)
1437 struct vcpu_svm
*svm
= to_svm(vcpu
);
1439 if (is_guest_mode(vcpu
))
1440 return svm
->nested
.hsave
->control
.tsc_offset
;
1442 return vcpu
->arch
.tsc_offset
;
1445 static u64
svm_write_l1_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1447 struct vcpu_svm
*svm
= to_svm(vcpu
);
1448 u64 g_tsc_offset
= 0;
1450 if (is_guest_mode(vcpu
)) {
1451 /* Write L1's TSC offset. */
1452 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1453 svm
->nested
.hsave
->control
.tsc_offset
;
1454 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1457 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1458 svm
->vmcb
->control
.tsc_offset
- g_tsc_offset
,
1461 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1463 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1464 return svm
->vmcb
->control
.tsc_offset
;
1467 static void avic_init_vmcb(struct vcpu_svm
*svm
)
1469 struct vmcb
*vmcb
= svm
->vmcb
;
1470 struct kvm_svm
*kvm_svm
= to_kvm_svm(svm
->vcpu
.kvm
);
1471 phys_addr_t bpa
= __sme_set(page_to_phys(svm
->avic_backing_page
));
1472 phys_addr_t lpa
= __sme_set(page_to_phys(kvm_svm
->avic_logical_id_table_page
));
1473 phys_addr_t ppa
= __sme_set(page_to_phys(kvm_svm
->avic_physical_id_table_page
));
1475 vmcb
->control
.avic_backing_page
= bpa
& AVIC_HPA_MASK
;
1476 vmcb
->control
.avic_logical_id
= lpa
& AVIC_HPA_MASK
;
1477 vmcb
->control
.avic_physical_id
= ppa
& AVIC_HPA_MASK
;
1478 vmcb
->control
.avic_physical_id
|= AVIC_MAX_PHYSICAL_ID_COUNT
;
1479 vmcb
->control
.int_ctl
|= AVIC_ENABLE_MASK
;
1482 static void init_vmcb(struct vcpu_svm
*svm
)
1484 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1485 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1487 svm
->vcpu
.arch
.hflags
= 0;
1489 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1490 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1491 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1492 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1493 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1494 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1495 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1496 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1498 set_dr_intercepts(svm
);
1500 set_exception_intercept(svm
, PF_VECTOR
);
1501 set_exception_intercept(svm
, UD_VECTOR
);
1502 set_exception_intercept(svm
, MC_VECTOR
);
1503 set_exception_intercept(svm
, AC_VECTOR
);
1504 set_exception_intercept(svm
, DB_VECTOR
);
1506 * Guest access to VMware backdoor ports could legitimately
1507 * trigger #GP because of TSS I/O permission bitmap.
1508 * We intercept those #GP and allow access to them anyway
1511 if (enable_vmware_backdoor
)
1512 set_exception_intercept(svm
, GP_VECTOR
);
1514 set_intercept(svm
, INTERCEPT_INTR
);
1515 set_intercept(svm
, INTERCEPT_NMI
);
1516 set_intercept(svm
, INTERCEPT_SMI
);
1517 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1518 set_intercept(svm
, INTERCEPT_RDPMC
);
1519 set_intercept(svm
, INTERCEPT_CPUID
);
1520 set_intercept(svm
, INTERCEPT_INVD
);
1521 set_intercept(svm
, INTERCEPT_INVLPG
);
1522 set_intercept(svm
, INTERCEPT_INVLPGA
);
1523 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1524 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1525 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1526 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1527 set_intercept(svm
, INTERCEPT_VMRUN
);
1528 set_intercept(svm
, INTERCEPT_VMMCALL
);
1529 set_intercept(svm
, INTERCEPT_VMLOAD
);
1530 set_intercept(svm
, INTERCEPT_VMSAVE
);
1531 set_intercept(svm
, INTERCEPT_STGI
);
1532 set_intercept(svm
, INTERCEPT_CLGI
);
1533 set_intercept(svm
, INTERCEPT_SKINIT
);
1534 set_intercept(svm
, INTERCEPT_WBINVD
);
1535 set_intercept(svm
, INTERCEPT_XSETBV
);
1536 set_intercept(svm
, INTERCEPT_RSM
);
1538 if (!kvm_mwait_in_guest(svm
->vcpu
.kvm
)) {
1539 set_intercept(svm
, INTERCEPT_MONITOR
);
1540 set_intercept(svm
, INTERCEPT_MWAIT
);
1543 if (!kvm_hlt_in_guest(svm
->vcpu
.kvm
))
1544 set_intercept(svm
, INTERCEPT_HLT
);
1546 control
->iopm_base_pa
= __sme_set(iopm_base
);
1547 control
->msrpm_base_pa
= __sme_set(__pa(svm
->msrpm
));
1548 control
->int_ctl
= V_INTR_MASKING_MASK
;
1550 init_seg(&save
->es
);
1551 init_seg(&save
->ss
);
1552 init_seg(&save
->ds
);
1553 init_seg(&save
->fs
);
1554 init_seg(&save
->gs
);
1556 save
->cs
.selector
= 0xf000;
1557 save
->cs
.base
= 0xffff0000;
1558 /* Executable/Readable Code Segment */
1559 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1560 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1561 save
->cs
.limit
= 0xffff;
1563 save
->gdtr
.limit
= 0xffff;
1564 save
->idtr
.limit
= 0xffff;
1566 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1567 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1569 svm_set_efer(&svm
->vcpu
, 0);
1570 save
->dr6
= 0xffff0ff0;
1571 kvm_set_rflags(&svm
->vcpu
, 2);
1572 save
->rip
= 0x0000fff0;
1573 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1576 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1577 * It also updates the guest-visible cr0 value.
1579 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1580 kvm_mmu_reset_context(&svm
->vcpu
);
1582 save
->cr4
= X86_CR4_PAE
;
1586 /* Setup VMCB for Nested Paging */
1587 control
->nested_ctl
|= SVM_NESTED_CTL_NP_ENABLE
;
1588 clr_intercept(svm
, INTERCEPT_INVLPG
);
1589 clr_exception_intercept(svm
, PF_VECTOR
);
1590 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1591 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1592 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1596 svm
->asid_generation
= 0;
1598 svm
->nested
.vmcb
= 0;
1599 svm
->vcpu
.arch
.hflags
= 0;
1601 if (pause_filter_count
) {
1602 control
->pause_filter_count
= pause_filter_count
;
1603 if (pause_filter_thresh
)
1604 control
->pause_filter_thresh
= pause_filter_thresh
;
1605 set_intercept(svm
, INTERCEPT_PAUSE
);
1607 clr_intercept(svm
, INTERCEPT_PAUSE
);
1610 if (kvm_vcpu_apicv_active(&svm
->vcpu
))
1611 avic_init_vmcb(svm
);
1614 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1615 * in VMCB and clear intercepts to avoid #VMEXIT.
1618 clr_intercept(svm
, INTERCEPT_VMLOAD
);
1619 clr_intercept(svm
, INTERCEPT_VMSAVE
);
1620 svm
->vmcb
->control
.virt_ext
|= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
1624 clr_intercept(svm
, INTERCEPT_STGI
);
1625 clr_intercept(svm
, INTERCEPT_CLGI
);
1626 svm
->vmcb
->control
.int_ctl
|= V_GIF_ENABLE_MASK
;
1629 if (sev_guest(svm
->vcpu
.kvm
)) {
1630 svm
->vmcb
->control
.nested_ctl
|= SVM_NESTED_CTL_SEV_ENABLE
;
1631 clr_exception_intercept(svm
, UD_VECTOR
);
1634 mark_all_dirty(svm
->vmcb
);
1640 static u64
*avic_get_physical_id_entry(struct kvm_vcpu
*vcpu
,
1643 u64
*avic_physical_id_table
;
1644 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
1646 if (index
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1649 avic_physical_id_table
= page_address(kvm_svm
->avic_physical_id_table_page
);
1651 return &avic_physical_id_table
[index
];
1656 * AVIC hardware walks the nested page table to check permissions,
1657 * but does not use the SPA address specified in the leaf page
1658 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1659 * field of the VMCB. Therefore, we set up the
1660 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1662 static int avic_init_access_page(struct kvm_vcpu
*vcpu
)
1664 struct kvm
*kvm
= vcpu
->kvm
;
1667 mutex_lock(&kvm
->slots_lock
);
1668 if (kvm
->arch
.apic_access_page_done
)
1671 ret
= __x86_set_memory_region(kvm
,
1672 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
1673 APIC_DEFAULT_PHYS_BASE
,
1678 kvm
->arch
.apic_access_page_done
= true;
1680 mutex_unlock(&kvm
->slots_lock
);
1684 static int avic_init_backing_page(struct kvm_vcpu
*vcpu
)
1687 u64
*entry
, new_entry
;
1688 int id
= vcpu
->vcpu_id
;
1689 struct vcpu_svm
*svm
= to_svm(vcpu
);
1691 ret
= avic_init_access_page(vcpu
);
1695 if (id
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1698 if (!svm
->vcpu
.arch
.apic
->regs
)
1701 svm
->avic_backing_page
= virt_to_page(svm
->vcpu
.arch
.apic
->regs
);
1703 /* Setting AVIC backing page address in the phy APIC ID table */
1704 entry
= avic_get_physical_id_entry(vcpu
, id
);
1708 new_entry
= READ_ONCE(*entry
);
1709 new_entry
= __sme_set((page_to_phys(svm
->avic_backing_page
) &
1710 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK
) |
1711 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK
);
1712 WRITE_ONCE(*entry
, new_entry
);
1714 svm
->avic_physical_id_cache
= entry
;
1719 static void __sev_asid_free(int asid
)
1721 struct svm_cpu_data
*sd
;
1725 clear_bit(pos
, sev_asid_bitmap
);
1727 for_each_possible_cpu(cpu
) {
1728 sd
= per_cpu(svm_data
, cpu
);
1729 sd
->sev_vmcbs
[pos
] = NULL
;
1733 static void sev_asid_free(struct kvm
*kvm
)
1735 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1737 __sev_asid_free(sev
->asid
);
1740 static void sev_unbind_asid(struct kvm
*kvm
, unsigned int handle
)
1742 struct sev_data_decommission
*decommission
;
1743 struct sev_data_deactivate
*data
;
1748 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
1752 /* deactivate handle */
1753 data
->handle
= handle
;
1754 sev_guest_deactivate(data
, NULL
);
1756 wbinvd_on_all_cpus();
1757 sev_guest_df_flush(NULL
);
1760 decommission
= kzalloc(sizeof(*decommission
), GFP_KERNEL
);
1764 /* decommission handle */
1765 decommission
->handle
= handle
;
1766 sev_guest_decommission(decommission
, NULL
);
1768 kfree(decommission
);
1771 static struct page
**sev_pin_memory(struct kvm
*kvm
, unsigned long uaddr
,
1772 unsigned long ulen
, unsigned long *n
,
1775 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1776 unsigned long npages
, npinned
, size
;
1777 unsigned long locked
, lock_limit
;
1778 struct page
**pages
;
1779 unsigned long first
, last
;
1781 if (ulen
== 0 || uaddr
+ ulen
< uaddr
)
1784 /* Calculate number of pages. */
1785 first
= (uaddr
& PAGE_MASK
) >> PAGE_SHIFT
;
1786 last
= ((uaddr
+ ulen
- 1) & PAGE_MASK
) >> PAGE_SHIFT
;
1787 npages
= (last
- first
+ 1);
1789 locked
= sev
->pages_locked
+ npages
;
1790 lock_limit
= rlimit(RLIMIT_MEMLOCK
) >> PAGE_SHIFT
;
1791 if (locked
> lock_limit
&& !capable(CAP_IPC_LOCK
)) {
1792 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked
, lock_limit
);
1796 /* Avoid using vmalloc for smaller buffers. */
1797 size
= npages
* sizeof(struct page
*);
1798 if (size
> PAGE_SIZE
)
1799 pages
= __vmalloc(size
, GFP_KERNEL_ACCOUNT
| __GFP_ZERO
,
1802 pages
= kmalloc(size
, GFP_KERNEL_ACCOUNT
);
1807 /* Pin the user virtual address. */
1808 npinned
= get_user_pages_fast(uaddr
, npages
, FOLL_WRITE
, pages
);
1809 if (npinned
!= npages
) {
1810 pr_err("SEV: Failure locking %lu pages.\n", npages
);
1815 sev
->pages_locked
= locked
;
1821 release_pages(pages
, npinned
);
1827 static void sev_unpin_memory(struct kvm
*kvm
, struct page
**pages
,
1828 unsigned long npages
)
1830 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1832 release_pages(pages
, npages
);
1834 sev
->pages_locked
-= npages
;
1837 static void sev_clflush_pages(struct page
*pages
[], unsigned long npages
)
1839 uint8_t *page_virtual
;
1842 if (npages
== 0 || pages
== NULL
)
1845 for (i
= 0; i
< npages
; i
++) {
1846 page_virtual
= kmap_atomic(pages
[i
]);
1847 clflush_cache_range(page_virtual
, PAGE_SIZE
);
1848 kunmap_atomic(page_virtual
);
1852 static void __unregister_enc_region_locked(struct kvm
*kvm
,
1853 struct enc_region
*region
)
1856 * The guest may change the memory encryption attribute from C=0 -> C=1
1857 * or vice versa for this memory range. Lets make sure caches are
1858 * flushed to ensure that guest data gets written into memory with
1861 sev_clflush_pages(region
->pages
, region
->npages
);
1863 sev_unpin_memory(kvm
, region
->pages
, region
->npages
);
1864 list_del(®ion
->list
);
1868 static struct kvm
*svm_vm_alloc(void)
1870 struct kvm_svm
*kvm_svm
= __vmalloc(sizeof(struct kvm_svm
),
1871 GFP_KERNEL_ACCOUNT
| __GFP_ZERO
,
1873 return &kvm_svm
->kvm
;
1876 static void svm_vm_free(struct kvm
*kvm
)
1878 vfree(to_kvm_svm(kvm
));
1881 static void sev_vm_destroy(struct kvm
*kvm
)
1883 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1884 struct list_head
*head
= &sev
->regions_list
;
1885 struct list_head
*pos
, *q
;
1887 if (!sev_guest(kvm
))
1890 mutex_lock(&kvm
->lock
);
1893 * if userspace was terminated before unregistering the memory regions
1894 * then lets unpin all the registered memory.
1896 if (!list_empty(head
)) {
1897 list_for_each_safe(pos
, q
, head
) {
1898 __unregister_enc_region_locked(kvm
,
1899 list_entry(pos
, struct enc_region
, list
));
1903 mutex_unlock(&kvm
->lock
);
1905 sev_unbind_asid(kvm
, sev
->handle
);
1909 static void avic_vm_destroy(struct kvm
*kvm
)
1911 unsigned long flags
;
1912 struct kvm_svm
*kvm_svm
= to_kvm_svm(kvm
);
1917 if (kvm_svm
->avic_logical_id_table_page
)
1918 __free_page(kvm_svm
->avic_logical_id_table_page
);
1919 if (kvm_svm
->avic_physical_id_table_page
)
1920 __free_page(kvm_svm
->avic_physical_id_table_page
);
1922 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1923 hash_del(&kvm_svm
->hnode
);
1924 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1927 static void svm_vm_destroy(struct kvm
*kvm
)
1929 avic_vm_destroy(kvm
);
1930 sev_vm_destroy(kvm
);
1933 static int avic_vm_init(struct kvm
*kvm
)
1935 unsigned long flags
;
1937 struct kvm_svm
*kvm_svm
= to_kvm_svm(kvm
);
1939 struct page
*p_page
;
1940 struct page
*l_page
;
1946 /* Allocating physical APIC ID table (4KB) */
1947 p_page
= alloc_page(GFP_KERNEL_ACCOUNT
);
1951 kvm_svm
->avic_physical_id_table_page
= p_page
;
1952 clear_page(page_address(p_page
));
1954 /* Allocating logical APIC ID table (4KB) */
1955 l_page
= alloc_page(GFP_KERNEL_ACCOUNT
);
1959 kvm_svm
->avic_logical_id_table_page
= l_page
;
1960 clear_page(page_address(l_page
));
1962 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1964 vm_id
= next_vm_id
= (next_vm_id
+ 1) & AVIC_VM_ID_MASK
;
1965 if (vm_id
== 0) { /* id is 1-based, zero is not okay */
1966 next_vm_id_wrapped
= 1;
1969 /* Is it still in use? Only possible if wrapped at least once */
1970 if (next_vm_id_wrapped
) {
1971 hash_for_each_possible(svm_vm_data_hash
, k2
, hnode
, vm_id
) {
1972 if (k2
->avic_vm_id
== vm_id
)
1976 kvm_svm
->avic_vm_id
= vm_id
;
1977 hash_add(svm_vm_data_hash
, &kvm_svm
->hnode
, kvm_svm
->avic_vm_id
);
1978 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1983 avic_vm_destroy(kvm
);
1988 avic_update_iommu_vcpu_affinity(struct kvm_vcpu
*vcpu
, int cpu
, bool r
)
1991 unsigned long flags
;
1992 struct amd_svm_iommu_ir
*ir
;
1993 struct vcpu_svm
*svm
= to_svm(vcpu
);
1995 if (!kvm_arch_has_assigned_device(vcpu
->kvm
))
1999 * Here, we go through the per-vcpu ir_list to update all existing
2000 * interrupt remapping table entry targeting this vcpu.
2002 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
2004 if (list_empty(&svm
->ir_list
))
2007 list_for_each_entry(ir
, &svm
->ir_list
, node
) {
2008 ret
= amd_iommu_update_ga(cpu
, r
, ir
->data
);
2013 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
2017 static void avic_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2020 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2021 int h_physical_id
= kvm_cpu_get_apicid(cpu
);
2022 struct vcpu_svm
*svm
= to_svm(vcpu
);
2024 if (!kvm_vcpu_apicv_active(vcpu
))
2028 * Since the host physical APIC id is 8 bits,
2029 * we can support host APIC ID upto 255.
2031 if (WARN_ON(h_physical_id
> AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
))
2034 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
2035 WARN_ON(entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
2037 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
;
2038 entry
|= (h_physical_id
& AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
);
2040 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2041 if (svm
->avic_is_running
)
2042 entry
|= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2044 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
2045 avic_update_iommu_vcpu_affinity(vcpu
, h_physical_id
,
2046 svm
->avic_is_running
);
2049 static void avic_vcpu_put(struct kvm_vcpu
*vcpu
)
2052 struct vcpu_svm
*svm
= to_svm(vcpu
);
2054 if (!kvm_vcpu_apicv_active(vcpu
))
2057 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
2058 if (entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
)
2059 avic_update_iommu_vcpu_affinity(vcpu
, -1, 0);
2061 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2062 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
2066 * This function is called during VCPU halt/unhalt.
2068 static void avic_set_running(struct kvm_vcpu
*vcpu
, bool is_run
)
2070 struct vcpu_svm
*svm
= to_svm(vcpu
);
2072 svm
->avic_is_running
= is_run
;
2074 avic_vcpu_load(vcpu
, vcpu
->cpu
);
2076 avic_vcpu_put(vcpu
);
2079 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
2081 struct vcpu_svm
*svm
= to_svm(vcpu
);
2085 vcpu
->arch
.microcode_version
= 0x01000065;
2087 svm
->virt_spec_ctrl
= 0;
2090 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
2091 MSR_IA32_APICBASE_ENABLE
;
2092 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
2093 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
2097 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
, true);
2098 kvm_rdx_write(vcpu
, eax
);
2100 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
2101 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
2104 static int avic_init_vcpu(struct vcpu_svm
*svm
)
2108 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
2111 ret
= avic_init_backing_page(&svm
->vcpu
);
2115 INIT_LIST_HEAD(&svm
->ir_list
);
2116 spin_lock_init(&svm
->ir_list_lock
);
2117 svm
->dfr_reg
= APIC_DFR_FLAT
;
2122 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
2124 struct vcpu_svm
*svm
;
2126 struct page
*msrpm_pages
;
2127 struct page
*hsave_page
;
2128 struct page
*nested_msrpm_pages
;
2131 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL_ACCOUNT
);
2137 svm
->vcpu
.arch
.guest_fpu
= kmem_cache_zalloc(x86_fpu_cache
,
2138 GFP_KERNEL_ACCOUNT
);
2139 if (!svm
->vcpu
.arch
.guest_fpu
) {
2140 printk(KERN_ERR
"kvm: failed to allocate vcpu's fpu\n");
2142 goto free_partial_svm
;
2145 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
2150 page
= alloc_page(GFP_KERNEL_ACCOUNT
);
2154 msrpm_pages
= alloc_pages(GFP_KERNEL_ACCOUNT
, MSRPM_ALLOC_ORDER
);
2158 nested_msrpm_pages
= alloc_pages(GFP_KERNEL_ACCOUNT
, MSRPM_ALLOC_ORDER
);
2159 if (!nested_msrpm_pages
)
2162 hsave_page
= alloc_page(GFP_KERNEL_ACCOUNT
);
2166 err
= avic_init_vcpu(svm
);
2170 /* We initialize this flag to true to make sure that the is_running
2171 * bit would be set the first time the vcpu is loaded.
2173 svm
->avic_is_running
= true;
2175 svm
->nested
.hsave
= page_address(hsave_page
);
2177 svm
->msrpm
= page_address(msrpm_pages
);
2178 svm_vcpu_init_msrpm(svm
->msrpm
);
2180 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
2181 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
2183 svm
->vmcb
= page_address(page
);
2184 clear_page(svm
->vmcb
);
2185 svm
->vmcb_pa
= __sme_set(page_to_pfn(page
) << PAGE_SHIFT
);
2186 svm
->asid_generation
= 0;
2189 svm_init_osvw(&svm
->vcpu
);
2194 __free_page(hsave_page
);
2196 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
2198 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
2202 kvm_vcpu_uninit(&svm
->vcpu
);
2204 kmem_cache_free(x86_fpu_cache
, svm
->vcpu
.arch
.guest_fpu
);
2206 kmem_cache_free(kvm_vcpu_cache
, svm
);
2208 return ERR_PTR(err
);
2211 static void svm_clear_current_vmcb(struct vmcb
*vmcb
)
2215 for_each_online_cpu(i
)
2216 cmpxchg(&per_cpu(svm_data
, i
)->current_vmcb
, vmcb
, NULL
);
2219 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
2221 struct vcpu_svm
*svm
= to_svm(vcpu
);
2224 * The vmcb page can be recycled, causing a false negative in
2225 * svm_vcpu_load(). So, ensure that no logical CPU has this
2226 * vmcb page recorded as its current vmcb.
2228 svm_clear_current_vmcb(svm
->vmcb
);
2230 __free_page(pfn_to_page(__sme_clr(svm
->vmcb_pa
) >> PAGE_SHIFT
));
2231 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
2232 __free_page(virt_to_page(svm
->nested
.hsave
));
2233 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
2234 kvm_vcpu_uninit(vcpu
);
2235 kmem_cache_free(x86_fpu_cache
, svm
->vcpu
.arch
.guest_fpu
);
2236 kmem_cache_free(kvm_vcpu_cache
, svm
);
2239 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2241 struct vcpu_svm
*svm
= to_svm(vcpu
);
2242 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2245 if (unlikely(cpu
!= vcpu
->cpu
)) {
2246 svm
->asid_generation
= 0;
2247 mark_all_dirty(svm
->vmcb
);
2250 #ifdef CONFIG_X86_64
2251 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
2253 savesegment(fs
, svm
->host
.fs
);
2254 savesegment(gs
, svm
->host
.gs
);
2255 svm
->host
.ldt
= kvm_read_ldt();
2257 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
2258 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
2260 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
2261 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
2262 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
2263 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
2264 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
2267 /* This assumes that the kernel never uses MSR_TSC_AUX */
2268 if (static_cpu_has(X86_FEATURE_RDTSCP
))
2269 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
2271 if (sd
->current_vmcb
!= svm
->vmcb
) {
2272 sd
->current_vmcb
= svm
->vmcb
;
2273 indirect_branch_prediction_barrier();
2275 avic_vcpu_load(vcpu
, cpu
);
2278 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
2280 struct vcpu_svm
*svm
= to_svm(vcpu
);
2283 avic_vcpu_put(vcpu
);
2285 ++vcpu
->stat
.host_state_reload
;
2286 kvm_load_ldt(svm
->host
.ldt
);
2287 #ifdef CONFIG_X86_64
2288 loadsegment(fs
, svm
->host
.fs
);
2289 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gsbase
);
2290 load_gs_index(svm
->host
.gs
);
2292 #ifdef CONFIG_X86_32_LAZY_GS
2293 loadsegment(gs
, svm
->host
.gs
);
2296 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
2297 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
2300 static void svm_vcpu_blocking(struct kvm_vcpu
*vcpu
)
2302 avic_set_running(vcpu
, false);
2305 static void svm_vcpu_unblocking(struct kvm_vcpu
*vcpu
)
2307 avic_set_running(vcpu
, true);
2310 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
2312 struct vcpu_svm
*svm
= to_svm(vcpu
);
2313 unsigned long rflags
= svm
->vmcb
->save
.rflags
;
2315 if (svm
->nmi_singlestep
) {
2316 /* Hide our flags if they were not set by the guest */
2317 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
2318 rflags
&= ~X86_EFLAGS_TF
;
2319 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
2320 rflags
&= ~X86_EFLAGS_RF
;
2325 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2327 if (to_svm(vcpu
)->nmi_singlestep
)
2328 rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2331 * Any change of EFLAGS.VM is accompanied by a reload of SS
2332 * (caused by either a task switch or an inter-privilege IRET),
2333 * so we do not need to update the CPL here.
2335 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
2338 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2341 case VCPU_EXREG_PDPTR
:
2342 BUG_ON(!npt_enabled
);
2343 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
2350 static void svm_set_vintr(struct vcpu_svm
*svm
)
2352 set_intercept(svm
, INTERCEPT_VINTR
);
2355 static void svm_clear_vintr(struct vcpu_svm
*svm
)
2357 clr_intercept(svm
, INTERCEPT_VINTR
);
2360 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
2362 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
2365 case VCPU_SREG_CS
: return &save
->cs
;
2366 case VCPU_SREG_DS
: return &save
->ds
;
2367 case VCPU_SREG_ES
: return &save
->es
;
2368 case VCPU_SREG_FS
: return &save
->fs
;
2369 case VCPU_SREG_GS
: return &save
->gs
;
2370 case VCPU_SREG_SS
: return &save
->ss
;
2371 case VCPU_SREG_TR
: return &save
->tr
;
2372 case VCPU_SREG_LDTR
: return &save
->ldtr
;
2378 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
2380 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2385 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
2386 struct kvm_segment
*var
, int seg
)
2388 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2390 var
->base
= s
->base
;
2391 var
->limit
= s
->limit
;
2392 var
->selector
= s
->selector
;
2393 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
2394 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
2395 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
2396 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
2397 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
2398 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
2399 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
2402 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2403 * However, the SVM spec states that the G bit is not observed by the
2404 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2405 * So let's synthesize a legal G bit for all segments, this helps
2406 * running KVM nested. It also helps cross-vendor migration, because
2407 * Intel's vmentry has a check on the 'G' bit.
2409 var
->g
= s
->limit
> 0xfffff;
2412 * AMD's VMCB does not have an explicit unusable field, so emulate it
2413 * for cross vendor migration purposes by "not present"
2415 var
->unusable
= !var
->present
;
2420 * Work around a bug where the busy flag in the tr selector
2430 * The accessed bit must always be set in the segment
2431 * descriptor cache, although it can be cleared in the
2432 * descriptor, the cached bit always remains at 1. Since
2433 * Intel has a check on this, set it here to support
2434 * cross-vendor migration.
2441 * On AMD CPUs sometimes the DB bit in the segment
2442 * descriptor is left as 1, although the whole segment has
2443 * been made unusable. Clear it here to pass an Intel VMX
2444 * entry check when cross vendor migrating.
2448 /* This is symmetric with svm_set_segment() */
2449 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
2454 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
2456 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
2461 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2463 struct vcpu_svm
*svm
= to_svm(vcpu
);
2465 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
2466 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
2469 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2471 struct vcpu_svm
*svm
= to_svm(vcpu
);
2473 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
2474 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
2475 mark_dirty(svm
->vmcb
, VMCB_DT
);
2478 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2480 struct vcpu_svm
*svm
= to_svm(vcpu
);
2482 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
2483 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
2486 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2488 struct vcpu_svm
*svm
= to_svm(vcpu
);
2490 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
2491 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
2492 mark_dirty(svm
->vmcb
, VMCB_DT
);
2495 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2499 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
2503 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2507 static void update_cr0_intercept(struct vcpu_svm
*svm
)
2509 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
2510 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
2512 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
2513 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
2515 mark_dirty(svm
->vmcb
, VMCB_CR
);
2517 if (gcr0
== *hcr0
) {
2518 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2519 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2521 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2522 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2526 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2528 struct vcpu_svm
*svm
= to_svm(vcpu
);
2530 #ifdef CONFIG_X86_64
2531 if (vcpu
->arch
.efer
& EFER_LME
) {
2532 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
2533 vcpu
->arch
.efer
|= EFER_LMA
;
2534 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
2537 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
2538 vcpu
->arch
.efer
&= ~EFER_LMA
;
2539 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
2543 vcpu
->arch
.cr0
= cr0
;
2546 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
2549 * re-enable caching here because the QEMU bios
2550 * does not do it - this results in some delay at
2553 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
2554 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
2555 svm
->vmcb
->save
.cr0
= cr0
;
2556 mark_dirty(svm
->vmcb
, VMCB_CR
);
2557 update_cr0_intercept(svm
);
2560 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2562 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
2563 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
2565 if (cr4
& X86_CR4_VMXE
)
2568 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
2569 svm_flush_tlb(vcpu
, true);
2571 vcpu
->arch
.cr4
= cr4
;
2574 cr4
|= host_cr4_mce
;
2575 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
2576 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
2580 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
2581 struct kvm_segment
*var
, int seg
)
2583 struct vcpu_svm
*svm
= to_svm(vcpu
);
2584 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2586 s
->base
= var
->base
;
2587 s
->limit
= var
->limit
;
2588 s
->selector
= var
->selector
;
2589 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
2590 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
2591 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
2592 s
->attrib
|= ((var
->present
& 1) && !var
->unusable
) << SVM_SELECTOR_P_SHIFT
;
2593 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
2594 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
2595 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
2596 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
2599 * This is always accurate, except if SYSRET returned to a segment
2600 * with SS.DPL != 3. Intel does not have this quirk, and always
2601 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2602 * would entail passing the CPL to userspace and back.
2604 if (seg
== VCPU_SREG_SS
)
2605 /* This is symmetric with svm_get_segment() */
2606 svm
->vmcb
->save
.cpl
= (var
->dpl
& 3);
2608 mark_dirty(svm
->vmcb
, VMCB_SEG
);
2611 static void update_bp_intercept(struct kvm_vcpu
*vcpu
)
2613 struct vcpu_svm
*svm
= to_svm(vcpu
);
2615 clr_exception_intercept(svm
, BP_VECTOR
);
2617 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
2618 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2619 set_exception_intercept(svm
, BP_VECTOR
);
2621 vcpu
->guest_debug
= 0;
2624 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
2626 if (sd
->next_asid
> sd
->max_asid
) {
2627 ++sd
->asid_generation
;
2628 sd
->next_asid
= sd
->min_asid
;
2629 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
2632 svm
->asid_generation
= sd
->asid_generation
;
2633 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
2635 mark_dirty(svm
->vmcb
, VMCB_ASID
);
2638 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
2640 return to_svm(vcpu
)->vmcb
->save
.dr6
;
2643 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
2645 struct vcpu_svm
*svm
= to_svm(vcpu
);
2647 svm
->vmcb
->save
.dr6
= value
;
2648 mark_dirty(svm
->vmcb
, VMCB_DR
);
2651 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
2653 struct vcpu_svm
*svm
= to_svm(vcpu
);
2655 get_debugreg(vcpu
->arch
.db
[0], 0);
2656 get_debugreg(vcpu
->arch
.db
[1], 1);
2657 get_debugreg(vcpu
->arch
.db
[2], 2);
2658 get_debugreg(vcpu
->arch
.db
[3], 3);
2659 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
2660 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
2662 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
2663 set_dr_intercepts(svm
);
2666 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
2668 struct vcpu_svm
*svm
= to_svm(vcpu
);
2670 svm
->vmcb
->save
.dr7
= value
;
2671 mark_dirty(svm
->vmcb
, VMCB_DR
);
2674 static int pf_interception(struct vcpu_svm
*svm
)
2676 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
2677 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2679 return kvm_handle_page_fault(&svm
->vcpu
, error_code
, fault_address
,
2680 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2681 svm
->vmcb
->control
.insn_bytes
: NULL
,
2682 svm
->vmcb
->control
.insn_len
);
2685 static int npf_interception(struct vcpu_svm
*svm
)
2687 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
2688 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2690 trace_kvm_page_fault(fault_address
, error_code
);
2691 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
2692 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2693 svm
->vmcb
->control
.insn_bytes
: NULL
,
2694 svm
->vmcb
->control
.insn_len
);
2697 static int db_interception(struct vcpu_svm
*svm
)
2699 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2700 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2702 if (!(svm
->vcpu
.guest_debug
&
2703 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
2704 !svm
->nmi_singlestep
) {
2705 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
2709 if (svm
->nmi_singlestep
) {
2710 disable_nmi_singlestep(svm
);
2711 /* Make sure we check for pending NMIs upon entry */
2712 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
2715 if (svm
->vcpu
.guest_debug
&
2716 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
2717 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2718 kvm_run
->debug
.arch
.pc
=
2719 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2720 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2727 static int bp_interception(struct vcpu_svm
*svm
)
2729 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2731 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2732 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2733 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
2737 static int ud_interception(struct vcpu_svm
*svm
)
2739 return handle_ud(&svm
->vcpu
);
2742 static int ac_interception(struct vcpu_svm
*svm
)
2744 kvm_queue_exception_e(&svm
->vcpu
, AC_VECTOR
, 0);
2748 static int gp_interception(struct vcpu_svm
*svm
)
2750 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2751 u32 error_code
= svm
->vmcb
->control
.exit_info_1
;
2754 WARN_ON_ONCE(!enable_vmware_backdoor
);
2756 er
= kvm_emulate_instruction(vcpu
,
2757 EMULTYPE_VMWARE
| EMULTYPE_NO_UD_ON_FAIL
);
2758 if (er
== EMULATE_USER_EXIT
)
2760 else if (er
!= EMULATE_DONE
)
2761 kvm_queue_exception_e(vcpu
, GP_VECTOR
, error_code
);
2765 static bool is_erratum_383(void)
2770 if (!erratum_383_found
)
2773 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
2777 /* Bit 62 may or may not be set for this mce */
2778 value
&= ~(1ULL << 62);
2780 if (value
!= 0xb600000000010015ULL
)
2783 /* Clear MCi_STATUS registers */
2784 for (i
= 0; i
< 6; ++i
)
2785 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
2787 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
2791 value
&= ~(1ULL << 2);
2792 low
= lower_32_bits(value
);
2793 high
= upper_32_bits(value
);
2795 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
2798 /* Flush tlb to evict multi-match entries */
2804 static void svm_handle_mce(struct vcpu_svm
*svm
)
2806 if (is_erratum_383()) {
2808 * Erratum 383 triggered. Guest state is corrupt so kill the
2811 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2813 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
2819 * On an #MC intercept the MCE handler is not called automatically in
2820 * the host. So do it by hand here.
2824 /* not sure if we ever come back to this point */
2829 static int mc_interception(struct vcpu_svm
*svm
)
2834 static int shutdown_interception(struct vcpu_svm
*svm
)
2836 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2839 * VMCB is undefined after a SHUTDOWN intercept
2840 * so reinitialize it.
2842 clear_page(svm
->vmcb
);
2845 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2849 static int io_interception(struct vcpu_svm
*svm
)
2851 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2852 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2853 int size
, in
, string
;
2856 ++svm
->vcpu
.stat
.io_exits
;
2857 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2858 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2860 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
2862 port
= io_info
>> 16;
2863 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2864 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2866 return kvm_fast_pio(&svm
->vcpu
, size
, port
, in
);
2869 static int nmi_interception(struct vcpu_svm
*svm
)
2874 static int intr_interception(struct vcpu_svm
*svm
)
2876 ++svm
->vcpu
.stat
.irq_exits
;
2880 static int nop_on_interception(struct vcpu_svm
*svm
)
2885 static int halt_interception(struct vcpu_svm
*svm
)
2887 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
2888 return kvm_emulate_halt(&svm
->vcpu
);
2891 static int vmmcall_interception(struct vcpu_svm
*svm
)
2893 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2894 return kvm_emulate_hypercall(&svm
->vcpu
);
2897 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
2899 struct vcpu_svm
*svm
= to_svm(vcpu
);
2901 return svm
->nested
.nested_cr3
;
2904 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
2906 struct vcpu_svm
*svm
= to_svm(vcpu
);
2907 u64 cr3
= svm
->nested
.nested_cr3
;
2911 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(__sme_clr(cr3
)), &pdpte
,
2912 offset_in_page(cr3
) + index
* 8, 8);
2918 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
2921 struct vcpu_svm
*svm
= to_svm(vcpu
);
2923 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
2924 mark_dirty(svm
->vmcb
, VMCB_NPT
);
2927 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
2928 struct x86_exception
*fault
)
2930 struct vcpu_svm
*svm
= to_svm(vcpu
);
2932 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
2934 * TODO: track the cause of the nested page fault, and
2935 * correctly fill in the high bits of exit_info_1.
2937 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
2938 svm
->vmcb
->control
.exit_code_hi
= 0;
2939 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
2940 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
2943 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
2944 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2947 * The present bit is always zero for page structure faults on real
2950 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2951 svm
->vmcb
->control
.exit_info_1
&= ~1;
2953 nested_svm_vmexit(svm
);
2956 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2958 WARN_ON(mmu_is_nested(vcpu
));
2960 vcpu
->arch
.mmu
= &vcpu
->arch
.guest_mmu
;
2961 kvm_init_shadow_mmu(vcpu
);
2962 vcpu
->arch
.mmu
->set_cr3
= nested_svm_set_tdp_cr3
;
2963 vcpu
->arch
.mmu
->get_cr3
= nested_svm_get_tdp_cr3
;
2964 vcpu
->arch
.mmu
->get_pdptr
= nested_svm_get_tdp_pdptr
;
2965 vcpu
->arch
.mmu
->inject_page_fault
= nested_svm_inject_npf_exit
;
2966 vcpu
->arch
.mmu
->shadow_root_level
= get_npt_level(vcpu
);
2967 reset_shadow_zero_bits_mask(vcpu
, vcpu
->arch
.mmu
);
2968 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2971 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2973 vcpu
->arch
.mmu
= &vcpu
->arch
.root_mmu
;
2974 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.root_mmu
;
2977 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2979 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
) ||
2980 !is_paging(&svm
->vcpu
)) {
2981 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2985 if (svm
->vmcb
->save
.cpl
) {
2986 kvm_inject_gp(&svm
->vcpu
, 0);
2993 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2994 bool has_error_code
, u32 error_code
)
2998 if (!is_guest_mode(&svm
->vcpu
))
3001 vmexit
= nested_svm_intercept(svm
);
3002 if (vmexit
!= NESTED_EXIT_DONE
)
3005 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
3006 svm
->vmcb
->control
.exit_code_hi
= 0;
3007 svm
->vmcb
->control
.exit_info_1
= error_code
;
3010 * EXITINFO2 is undefined for all exception intercepts other
3013 if (svm
->vcpu
.arch
.exception
.nested_apf
)
3014 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.apf
.nested_apf_token
;
3015 else if (svm
->vcpu
.arch
.exception
.has_payload
)
3016 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.exception
.payload
;
3018 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
3020 svm
->nested
.exit_required
= true;
3024 /* This function returns true if it is save to enable the irq window */
3025 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
3027 if (!is_guest_mode(&svm
->vcpu
))
3030 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
3033 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
3037 * if vmexit was already requested (by intercepted exception
3038 * for instance) do not overwrite it with "external interrupt"
3041 if (svm
->nested
.exit_required
)
3044 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
3045 svm
->vmcb
->control
.exit_info_1
= 0;
3046 svm
->vmcb
->control
.exit_info_2
= 0;
3048 if (svm
->nested
.intercept
& 1ULL) {
3050 * The #vmexit can't be emulated here directly because this
3051 * code path runs with irqs and preemption disabled. A
3052 * #vmexit emulation might sleep. Only signal request for
3055 svm
->nested
.exit_required
= true;
3056 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
3063 /* This function returns true if it is save to enable the nmi window */
3064 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
3066 if (!is_guest_mode(&svm
->vcpu
))
3069 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
3072 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
3073 svm
->nested
.exit_required
= true;
3078 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
3080 unsigned port
, size
, iopm_len
;
3085 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
3086 return NESTED_EXIT_HOST
;
3088 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
3089 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
3090 SVM_IOIO_SIZE_SHIFT
;
3091 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
3092 start_bit
= port
% 8;
3093 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
3094 mask
= (0xf >> (4 - size
)) << start_bit
;
3097 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
3098 return NESTED_EXIT_DONE
;
3100 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
3103 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
3105 u32 offset
, msr
, value
;
3108 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
3109 return NESTED_EXIT_HOST
;
3111 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3112 offset
= svm_msrpm_offset(msr
);
3113 write
= svm
->vmcb
->control
.exit_info_1
& 1;
3114 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
3116 if (offset
== MSR_INVALID
)
3117 return NESTED_EXIT_DONE
;
3119 /* Offset is in 32 bit units but need in 8 bit units */
3122 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
3123 return NESTED_EXIT_DONE
;
3125 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
3128 /* DB exceptions for our internal use must not cause vmexit */
3129 static int nested_svm_intercept_db(struct vcpu_svm
*svm
)
3133 /* if we're not singlestepping, it's not ours */
3134 if (!svm
->nmi_singlestep
)
3135 return NESTED_EXIT_DONE
;
3137 /* if it's not a singlestep exception, it's not ours */
3138 if (kvm_get_dr(&svm
->vcpu
, 6, &dr6
))
3139 return NESTED_EXIT_DONE
;
3140 if (!(dr6
& DR6_BS
))
3141 return NESTED_EXIT_DONE
;
3143 /* if the guest is singlestepping, it should get the vmexit */
3144 if (svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
) {
3145 disable_nmi_singlestep(svm
);
3146 return NESTED_EXIT_DONE
;
3149 /* it's ours, the nested hypervisor must not see this one */
3150 return NESTED_EXIT_HOST
;
3153 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
3155 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3157 switch (exit_code
) {
3160 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
3161 return NESTED_EXIT_HOST
;
3163 /* For now we are always handling NPFs when using them */
3165 return NESTED_EXIT_HOST
;
3167 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
3168 /* When we're shadowing, trap PFs, but not async PF */
3169 if (!npt_enabled
&& svm
->vcpu
.arch
.apf
.host_apf_reason
== 0)
3170 return NESTED_EXIT_HOST
;
3176 return NESTED_EXIT_CONTINUE
;
3180 * If this function returns true, this #vmexit was already handled
3182 static int nested_svm_intercept(struct vcpu_svm
*svm
)
3184 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3185 int vmexit
= NESTED_EXIT_HOST
;
3187 switch (exit_code
) {
3189 vmexit
= nested_svm_exit_handled_msr(svm
);
3192 vmexit
= nested_svm_intercept_ioio(svm
);
3194 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
3195 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
3196 if (svm
->nested
.intercept_cr
& bit
)
3197 vmexit
= NESTED_EXIT_DONE
;
3200 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
3201 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
3202 if (svm
->nested
.intercept_dr
& bit
)
3203 vmexit
= NESTED_EXIT_DONE
;
3206 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
3207 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
3208 if (svm
->nested
.intercept_exceptions
& excp_bits
) {
3209 if (exit_code
== SVM_EXIT_EXCP_BASE
+ DB_VECTOR
)
3210 vmexit
= nested_svm_intercept_db(svm
);
3212 vmexit
= NESTED_EXIT_DONE
;
3214 /* async page fault always cause vmexit */
3215 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
3216 svm
->vcpu
.arch
.exception
.nested_apf
!= 0)
3217 vmexit
= NESTED_EXIT_DONE
;
3220 case SVM_EXIT_ERR
: {
3221 vmexit
= NESTED_EXIT_DONE
;
3225 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
3226 if (svm
->nested
.intercept
& exit_bits
)
3227 vmexit
= NESTED_EXIT_DONE
;
3234 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
3238 vmexit
= nested_svm_intercept(svm
);
3240 if (vmexit
== NESTED_EXIT_DONE
)
3241 nested_svm_vmexit(svm
);
3246 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
3248 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
3249 struct vmcb_control_area
*from
= &from_vmcb
->control
;
3251 dst
->intercept_cr
= from
->intercept_cr
;
3252 dst
->intercept_dr
= from
->intercept_dr
;
3253 dst
->intercept_exceptions
= from
->intercept_exceptions
;
3254 dst
->intercept
= from
->intercept
;
3255 dst
->iopm_base_pa
= from
->iopm_base_pa
;
3256 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
3257 dst
->tsc_offset
= from
->tsc_offset
;
3258 dst
->asid
= from
->asid
;
3259 dst
->tlb_ctl
= from
->tlb_ctl
;
3260 dst
->int_ctl
= from
->int_ctl
;
3261 dst
->int_vector
= from
->int_vector
;
3262 dst
->int_state
= from
->int_state
;
3263 dst
->exit_code
= from
->exit_code
;
3264 dst
->exit_code_hi
= from
->exit_code_hi
;
3265 dst
->exit_info_1
= from
->exit_info_1
;
3266 dst
->exit_info_2
= from
->exit_info_2
;
3267 dst
->exit_int_info
= from
->exit_int_info
;
3268 dst
->exit_int_info_err
= from
->exit_int_info_err
;
3269 dst
->nested_ctl
= from
->nested_ctl
;
3270 dst
->event_inj
= from
->event_inj
;
3271 dst
->event_inj_err
= from
->event_inj_err
;
3272 dst
->nested_cr3
= from
->nested_cr3
;
3273 dst
->virt_ext
= from
->virt_ext
;
3274 dst
->pause_filter_count
= from
->pause_filter_count
;
3275 dst
->pause_filter_thresh
= from
->pause_filter_thresh
;
3278 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
3281 struct vmcb
*nested_vmcb
;
3282 struct vmcb
*hsave
= svm
->nested
.hsave
;
3283 struct vmcb
*vmcb
= svm
->vmcb
;
3284 struct kvm_host_map map
;
3286 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
3287 vmcb
->control
.exit_info_1
,
3288 vmcb
->control
.exit_info_2
,
3289 vmcb
->control
.exit_int_info
,
3290 vmcb
->control
.exit_int_info_err
,
3293 rc
= kvm_vcpu_map(&svm
->vcpu
, gfn_to_gpa(svm
->nested
.vmcb
), &map
);
3296 kvm_inject_gp(&svm
->vcpu
, 0);
3300 nested_vmcb
= map
.hva
;
3302 /* Exit Guest-Mode */
3303 leave_guest_mode(&svm
->vcpu
);
3304 svm
->nested
.vmcb
= 0;
3306 /* Give the current vmcb to the guest */
3309 nested_vmcb
->save
.es
= vmcb
->save
.es
;
3310 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
3311 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
3312 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
3313 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
3314 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
3315 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
3316 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3317 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3318 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
3319 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3320 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3321 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
3322 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
3323 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
3324 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
3325 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
3326 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
3328 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
3329 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
3330 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
3331 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
3332 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
3333 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
3334 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
3335 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
3336 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
3338 if (svm
->nrips_enabled
)
3339 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
3342 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3343 * to make sure that we do not lose injected events. So check event_inj
3344 * here and copy it to exit_int_info if it is valid.
3345 * Exit_int_info and event_inj can't be both valid because the case
3346 * below only happens on a VMRUN instruction intercept which has
3347 * no valid exit_int_info set.
3349 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
3350 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
3352 nc
->exit_int_info
= vmcb
->control
.event_inj
;
3353 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
3356 nested_vmcb
->control
.tlb_ctl
= 0;
3357 nested_vmcb
->control
.event_inj
= 0;
3358 nested_vmcb
->control
.event_inj_err
= 0;
3360 nested_vmcb
->control
.pause_filter_count
=
3361 svm
->vmcb
->control
.pause_filter_count
;
3362 nested_vmcb
->control
.pause_filter_thresh
=
3363 svm
->vmcb
->control
.pause_filter_thresh
;
3365 /* We always set V_INTR_MASKING and remember the old value in hflags */
3366 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
3367 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
3369 /* Restore the original control entries */
3370 copy_vmcb_control_area(vmcb
, hsave
);
3372 svm
->vcpu
.arch
.tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
3373 kvm_clear_exception_queue(&svm
->vcpu
);
3374 kvm_clear_interrupt_queue(&svm
->vcpu
);
3376 svm
->nested
.nested_cr3
= 0;
3378 /* Restore selected save entries */
3379 svm
->vmcb
->save
.es
= hsave
->save
.es
;
3380 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
3381 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
3382 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
3383 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
3384 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
3385 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
3386 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
3387 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
3388 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
3390 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
3391 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
3393 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
3395 kvm_rax_write(&svm
->vcpu
, hsave
->save
.rax
);
3396 kvm_rsp_write(&svm
->vcpu
, hsave
->save
.rsp
);
3397 kvm_rip_write(&svm
->vcpu
, hsave
->save
.rip
);
3398 svm
->vmcb
->save
.dr7
= 0;
3399 svm
->vmcb
->save
.cpl
= 0;
3400 svm
->vmcb
->control
.exit_int_info
= 0;
3402 mark_all_dirty(svm
->vmcb
);
3404 kvm_vcpu_unmap(&svm
->vcpu
, &map
, true);
3406 nested_svm_uninit_mmu_context(&svm
->vcpu
);
3407 kvm_mmu_reset_context(&svm
->vcpu
);
3408 kvm_mmu_load(&svm
->vcpu
);
3411 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3412 * doesn't end up in L1.
3414 svm
->vcpu
.arch
.nmi_injected
= false;
3415 kvm_clear_exception_queue(&svm
->vcpu
);
3416 kvm_clear_interrupt_queue(&svm
->vcpu
);
3421 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
3424 * This function merges the msr permission bitmaps of kvm and the
3425 * nested vmcb. It is optimized in that it only merges the parts where
3426 * the kvm msr permission bitmap may contain zero bits
3430 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
3433 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
3437 if (msrpm_offsets
[i
] == 0xffffffff)
3440 p
= msrpm_offsets
[i
];
3441 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
3443 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
3446 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
3449 svm
->vmcb
->control
.msrpm_base_pa
= __sme_set(__pa(svm
->nested
.msrpm
));
3454 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
3456 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
3459 if (vmcb
->control
.asid
== 0)
3462 if ((vmcb
->control
.nested_ctl
& SVM_NESTED_CTL_NP_ENABLE
) &&
3469 static void enter_svm_guest_mode(struct vcpu_svm
*svm
, u64 vmcb_gpa
,
3470 struct vmcb
*nested_vmcb
, struct kvm_host_map
*map
)
3472 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
3473 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
3475 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
3477 if (nested_vmcb
->control
.nested_ctl
& SVM_NESTED_CTL_NP_ENABLE
) {
3478 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
3479 nested_svm_init_mmu_context(&svm
->vcpu
);
3482 /* Load the nested guest state */
3483 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
3484 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
3485 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
3486 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
3487 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
3488 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
3489 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
3490 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
3491 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
3492 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
3494 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
3495 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
3497 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
3499 /* Guest paging mode is active - reset mmu */
3500 kvm_mmu_reset_context(&svm
->vcpu
);
3502 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
3503 kvm_rax_write(&svm
->vcpu
, nested_vmcb
->save
.rax
);
3504 kvm_rsp_write(&svm
->vcpu
, nested_vmcb
->save
.rsp
);
3505 kvm_rip_write(&svm
->vcpu
, nested_vmcb
->save
.rip
);
3507 /* In case we don't even reach vcpu_run, the fields are not updated */
3508 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
3509 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
3510 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
3511 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
3512 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
3513 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
3515 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
3516 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
3518 /* cache intercepts */
3519 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
3520 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
3521 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
3522 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
3524 svm_flush_tlb(&svm
->vcpu
, true);
3525 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
3526 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
3527 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
3529 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
3531 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
3532 /* We only want the cr8 intercept bits of the guest */
3533 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
3534 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3537 /* We don't want to see VMMCALLs from a nested guest */
3538 clr_intercept(svm
, INTERCEPT_VMMCALL
);
3540 svm
->vcpu
.arch
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
3541 svm
->vmcb
->control
.tsc_offset
= svm
->vcpu
.arch
.tsc_offset
;
3543 svm
->vmcb
->control
.virt_ext
= nested_vmcb
->control
.virt_ext
;
3544 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
3545 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
3546 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
3547 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
3549 svm
->vmcb
->control
.pause_filter_count
=
3550 nested_vmcb
->control
.pause_filter_count
;
3551 svm
->vmcb
->control
.pause_filter_thresh
=
3552 nested_vmcb
->control
.pause_filter_thresh
;
3554 kvm_vcpu_unmap(&svm
->vcpu
, map
, true);
3556 /* Enter Guest-Mode */
3557 enter_guest_mode(&svm
->vcpu
);
3560 * Merge guest and host intercepts - must be called with vcpu in
3561 * guest-mode to take affect here
3563 recalc_intercepts(svm
);
3565 svm
->nested
.vmcb
= vmcb_gpa
;
3569 mark_all_dirty(svm
->vmcb
);
3572 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
3575 struct vmcb
*nested_vmcb
;
3576 struct vmcb
*hsave
= svm
->nested
.hsave
;
3577 struct vmcb
*vmcb
= svm
->vmcb
;
3578 struct kvm_host_map map
;
3581 vmcb_gpa
= svm
->vmcb
->save
.rax
;
3583 rc
= kvm_vcpu_map(&svm
->vcpu
, gfn_to_gpa(vmcb_gpa
), &map
);
3586 kvm_inject_gp(&svm
->vcpu
, 0);
3590 nested_vmcb
= map
.hva
;
3592 if (!nested_vmcb_checks(nested_vmcb
)) {
3593 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3594 nested_vmcb
->control
.exit_code_hi
= 0;
3595 nested_vmcb
->control
.exit_info_1
= 0;
3596 nested_vmcb
->control
.exit_info_2
= 0;
3598 kvm_vcpu_unmap(&svm
->vcpu
, &map
, true);
3603 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
3604 nested_vmcb
->save
.rip
,
3605 nested_vmcb
->control
.int_ctl
,
3606 nested_vmcb
->control
.event_inj
,
3607 nested_vmcb
->control
.nested_ctl
);
3609 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
3610 nested_vmcb
->control
.intercept_cr
>> 16,
3611 nested_vmcb
->control
.intercept_exceptions
,
3612 nested_vmcb
->control
.intercept
);
3614 /* Clear internal status */
3615 kvm_clear_exception_queue(&svm
->vcpu
);
3616 kvm_clear_interrupt_queue(&svm
->vcpu
);
3619 * Save the old vmcb, so we don't need to pick what we save, but can
3620 * restore everything when a VMEXIT occurs
3622 hsave
->save
.es
= vmcb
->save
.es
;
3623 hsave
->save
.cs
= vmcb
->save
.cs
;
3624 hsave
->save
.ss
= vmcb
->save
.ss
;
3625 hsave
->save
.ds
= vmcb
->save
.ds
;
3626 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
3627 hsave
->save
.idtr
= vmcb
->save
.idtr
;
3628 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
3629 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3630 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3631 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3632 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
3633 hsave
->save
.rsp
= vmcb
->save
.rsp
;
3634 hsave
->save
.rax
= vmcb
->save
.rax
;
3636 hsave
->save
.cr3
= vmcb
->save
.cr3
;
3638 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3640 copy_vmcb_control_area(hsave
, vmcb
);
3642 enter_svm_guest_mode(svm
, vmcb_gpa
, nested_vmcb
, &map
);
3647 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
3649 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
3650 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
3651 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
3652 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
3653 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
3654 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
3655 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
3656 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
3657 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
3658 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
3659 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
3660 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
3663 static int vmload_interception(struct vcpu_svm
*svm
)
3665 struct vmcb
*nested_vmcb
;
3666 struct kvm_host_map map
;
3669 if (nested_svm_check_permissions(svm
))
3672 ret
= kvm_vcpu_map(&svm
->vcpu
, gpa_to_gfn(svm
->vmcb
->save
.rax
), &map
);
3675 kvm_inject_gp(&svm
->vcpu
, 0);
3679 nested_vmcb
= map
.hva
;
3681 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3682 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3684 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
3685 kvm_vcpu_unmap(&svm
->vcpu
, &map
, true);
3690 static int vmsave_interception(struct vcpu_svm
*svm
)
3692 struct vmcb
*nested_vmcb
;
3693 struct kvm_host_map map
;
3696 if (nested_svm_check_permissions(svm
))
3699 ret
= kvm_vcpu_map(&svm
->vcpu
, gpa_to_gfn(svm
->vmcb
->save
.rax
), &map
);
3702 kvm_inject_gp(&svm
->vcpu
, 0);
3706 nested_vmcb
= map
.hva
;
3708 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3709 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3711 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
3712 kvm_vcpu_unmap(&svm
->vcpu
, &map
, true);
3717 static int vmrun_interception(struct vcpu_svm
*svm
)
3719 if (nested_svm_check_permissions(svm
))
3722 /* Save rip after vmrun instruction */
3723 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
3725 if (!nested_svm_vmrun(svm
))
3728 if (!nested_svm_vmrun_msrpm(svm
))
3735 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3736 svm
->vmcb
->control
.exit_code_hi
= 0;
3737 svm
->vmcb
->control
.exit_info_1
= 0;
3738 svm
->vmcb
->control
.exit_info_2
= 0;
3740 nested_svm_vmexit(svm
);
3745 static int stgi_interception(struct vcpu_svm
*svm
)
3749 if (nested_svm_check_permissions(svm
))
3753 * If VGIF is enabled, the STGI intercept is only added to
3754 * detect the opening of the SMI/NMI window; remove it now.
3756 if (vgif_enabled(svm
))
3757 clr_intercept(svm
, INTERCEPT_STGI
);
3759 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3760 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3761 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3768 static int clgi_interception(struct vcpu_svm
*svm
)
3772 if (nested_svm_check_permissions(svm
))
3775 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3776 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3780 /* After a CLGI no interrupts should come */
3781 if (!kvm_vcpu_apicv_active(&svm
->vcpu
)) {
3782 svm_clear_vintr(svm
);
3783 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3784 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3790 static int invlpga_interception(struct vcpu_svm
*svm
)
3792 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3794 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_rcx_read(&svm
->vcpu
),
3795 kvm_rax_read(&svm
->vcpu
));
3797 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3798 kvm_mmu_invlpg(vcpu
, kvm_rax_read(&svm
->vcpu
));
3800 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3801 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3804 static int skinit_interception(struct vcpu_svm
*svm
)
3806 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_rax_read(&svm
->vcpu
));
3808 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3812 static int wbinvd_interception(struct vcpu_svm
*svm
)
3814 return kvm_emulate_wbinvd(&svm
->vcpu
);
3817 static int xsetbv_interception(struct vcpu_svm
*svm
)
3819 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
3820 u32 index
= kvm_rcx_read(&svm
->vcpu
);
3822 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
3823 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3824 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3830 static int task_switch_interception(struct vcpu_svm
*svm
)
3834 int int_type
= svm
->vmcb
->control
.exit_int_info
&
3835 SVM_EXITINTINFO_TYPE_MASK
;
3836 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
3838 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
3840 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
3841 bool has_error_code
= false;
3844 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
3846 if (svm
->vmcb
->control
.exit_info_2
&
3847 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
3848 reason
= TASK_SWITCH_IRET
;
3849 else if (svm
->vmcb
->control
.exit_info_2
&
3850 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
3851 reason
= TASK_SWITCH_JMP
;
3853 reason
= TASK_SWITCH_GATE
;
3855 reason
= TASK_SWITCH_CALL
;
3857 if (reason
== TASK_SWITCH_GATE
) {
3859 case SVM_EXITINTINFO_TYPE_NMI
:
3860 svm
->vcpu
.arch
.nmi_injected
= false;
3862 case SVM_EXITINTINFO_TYPE_EXEPT
:
3863 if (svm
->vmcb
->control
.exit_info_2
&
3864 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
3865 has_error_code
= true;
3867 (u32
)svm
->vmcb
->control
.exit_info_2
;
3869 kvm_clear_exception_queue(&svm
->vcpu
);
3871 case SVM_EXITINTINFO_TYPE_INTR
:
3872 kvm_clear_interrupt_queue(&svm
->vcpu
);
3879 if (reason
!= TASK_SWITCH_GATE
||
3880 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
3881 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
3882 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
3883 skip_emulated_instruction(&svm
->vcpu
);
3885 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
3888 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
3889 has_error_code
, error_code
) == EMULATE_FAIL
) {
3890 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3891 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3892 svm
->vcpu
.run
->internal
.ndata
= 0;
3898 static int cpuid_interception(struct vcpu_svm
*svm
)
3900 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3901 return kvm_emulate_cpuid(&svm
->vcpu
);
3904 static int iret_interception(struct vcpu_svm
*svm
)
3906 ++svm
->vcpu
.stat
.nmi_window_exits
;
3907 clr_intercept(svm
, INTERCEPT_IRET
);
3908 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
3909 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
3910 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3914 static int invlpg_interception(struct vcpu_svm
*svm
)
3916 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3917 return kvm_emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3919 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
3920 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3923 static int emulate_on_interception(struct vcpu_svm
*svm
)
3925 return kvm_emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3928 static int rsm_interception(struct vcpu_svm
*svm
)
3930 return kvm_emulate_instruction_from_buffer(&svm
->vcpu
,
3931 rsm_ins_bytes
, 2) == EMULATE_DONE
;
3934 static int rdpmc_interception(struct vcpu_svm
*svm
)
3938 if (!static_cpu_has(X86_FEATURE_NRIPS
))
3939 return emulate_on_interception(svm
);
3941 err
= kvm_rdpmc(&svm
->vcpu
);
3942 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3945 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
3948 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
3952 intercept
= svm
->nested
.intercept
;
3954 if (!is_guest_mode(&svm
->vcpu
) ||
3955 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
3958 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
3959 val
&= ~SVM_CR0_SELECTIVE_MASK
;
3962 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
3963 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
3969 #define CR_VALID (1ULL << 63)
3971 static int cr_interception(struct vcpu_svm
*svm
)
3977 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3978 return emulate_on_interception(svm
);
3980 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
3981 return emulate_on_interception(svm
);
3983 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3984 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
3985 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
3987 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
3990 if (cr
>= 16) { /* mov to cr */
3992 val
= kvm_register_read(&svm
->vcpu
, reg
);
3995 if (!check_selective_cr0_intercepted(svm
, val
))
3996 err
= kvm_set_cr0(&svm
->vcpu
, val
);
4002 err
= kvm_set_cr3(&svm
->vcpu
, val
);
4005 err
= kvm_set_cr4(&svm
->vcpu
, val
);
4008 err
= kvm_set_cr8(&svm
->vcpu
, val
);
4011 WARN(1, "unhandled write to CR%d", cr
);
4012 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
4015 } else { /* mov from cr */
4018 val
= kvm_read_cr0(&svm
->vcpu
);
4021 val
= svm
->vcpu
.arch
.cr2
;
4024 val
= kvm_read_cr3(&svm
->vcpu
);
4027 val
= kvm_read_cr4(&svm
->vcpu
);
4030 val
= kvm_get_cr8(&svm
->vcpu
);
4033 WARN(1, "unhandled read from CR%d", cr
);
4034 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
4037 kvm_register_write(&svm
->vcpu
, reg
, val
);
4039 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
4042 static int dr_interception(struct vcpu_svm
*svm
)
4047 if (svm
->vcpu
.guest_debug
== 0) {
4049 * No more DR vmexits; force a reload of the debug registers
4050 * and reenter on this instruction. The next vmexit will
4051 * retrieve the full state of the debug registers.
4053 clr_dr_intercepts(svm
);
4054 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
4058 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
4059 return emulate_on_interception(svm
);
4061 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
4062 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
4064 if (dr
>= 16) { /* mov to DRn */
4065 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
4067 val
= kvm_register_read(&svm
->vcpu
, reg
);
4068 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
4070 if (!kvm_require_dr(&svm
->vcpu
, dr
))
4072 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
4073 kvm_register_write(&svm
->vcpu
, reg
, val
);
4076 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4079 static int cr8_write_interception(struct vcpu_svm
*svm
)
4081 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
4084 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
4085 /* instruction emulation calls kvm_set_cr8() */
4086 r
= cr_interception(svm
);
4087 if (lapic_in_kernel(&svm
->vcpu
))
4089 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
4091 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
4095 static int svm_get_msr_feature(struct kvm_msr_entry
*msr
)
4099 switch (msr
->index
) {
4100 case MSR_F10H_DECFG
:
4101 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
))
4102 msr
->data
|= MSR_F10H_DECFG_LFENCE_SERIALIZE
;
4111 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
4113 struct vcpu_svm
*svm
= to_svm(vcpu
);
4115 switch (msr_info
->index
) {
4117 msr_info
->data
= svm
->vmcb
->save
.star
;
4119 #ifdef CONFIG_X86_64
4121 msr_info
->data
= svm
->vmcb
->save
.lstar
;
4124 msr_info
->data
= svm
->vmcb
->save
.cstar
;
4126 case MSR_KERNEL_GS_BASE
:
4127 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
4129 case MSR_SYSCALL_MASK
:
4130 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
4133 case MSR_IA32_SYSENTER_CS
:
4134 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
4136 case MSR_IA32_SYSENTER_EIP
:
4137 msr_info
->data
= svm
->sysenter_eip
;
4139 case MSR_IA32_SYSENTER_ESP
:
4140 msr_info
->data
= svm
->sysenter_esp
;
4143 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
4145 msr_info
->data
= svm
->tsc_aux
;
4148 * Nobody will change the following 5 values in the VMCB so we can
4149 * safely return them on rdmsr. They will always be 0 until LBRV is
4152 case MSR_IA32_DEBUGCTLMSR
:
4153 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
4155 case MSR_IA32_LASTBRANCHFROMIP
:
4156 msr_info
->data
= svm
->vmcb
->save
.br_from
;
4158 case MSR_IA32_LASTBRANCHTOIP
:
4159 msr_info
->data
= svm
->vmcb
->save
.br_to
;
4161 case MSR_IA32_LASTINTFROMIP
:
4162 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
4164 case MSR_IA32_LASTINTTOIP
:
4165 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
4167 case MSR_VM_HSAVE_PA
:
4168 msr_info
->data
= svm
->nested
.hsave_msr
;
4171 msr_info
->data
= svm
->nested
.vm_cr_msr
;
4173 case MSR_IA32_SPEC_CTRL
:
4174 if (!msr_info
->host_initiated
&&
4175 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBRS
) &&
4176 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_SSBD
))
4179 msr_info
->data
= svm
->spec_ctrl
;
4181 case MSR_AMD64_VIRT_SPEC_CTRL
:
4182 if (!msr_info
->host_initiated
&&
4183 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
4186 msr_info
->data
= svm
->virt_spec_ctrl
;
4188 case MSR_F15H_IC_CFG
: {
4192 family
= guest_cpuid_family(vcpu
);
4193 model
= guest_cpuid_model(vcpu
);
4195 if (family
< 0 || model
< 0)
4196 return kvm_get_msr_common(vcpu
, msr_info
);
4200 if (family
== 0x15 &&
4201 (model
>= 0x2 && model
< 0x20))
4202 msr_info
->data
= 0x1E;
4205 case MSR_F10H_DECFG
:
4206 msr_info
->data
= svm
->msr_decfg
;
4209 return kvm_get_msr_common(vcpu
, msr_info
);
4214 static int rdmsr_interception(struct vcpu_svm
*svm
)
4216 u32 ecx
= kvm_rcx_read(&svm
->vcpu
);
4217 struct msr_data msr_info
;
4219 msr_info
.index
= ecx
;
4220 msr_info
.host_initiated
= false;
4221 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
4222 trace_kvm_msr_read_ex(ecx
);
4223 kvm_inject_gp(&svm
->vcpu
, 0);
4226 trace_kvm_msr_read(ecx
, msr_info
.data
);
4228 kvm_rax_write(&svm
->vcpu
, msr_info
.data
& 0xffffffff);
4229 kvm_rdx_write(&svm
->vcpu
, msr_info
.data
>> 32);
4230 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
4231 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4235 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
4237 struct vcpu_svm
*svm
= to_svm(vcpu
);
4238 int svm_dis
, chg_mask
;
4240 if (data
& ~SVM_VM_CR_VALID_MASK
)
4243 chg_mask
= SVM_VM_CR_VALID_MASK
;
4245 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
4246 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
4248 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
4249 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
4251 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
4253 /* check for svm_disable while efer.svme is set */
4254 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
4260 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
4262 struct vcpu_svm
*svm
= to_svm(vcpu
);
4264 u32 ecx
= msr
->index
;
4265 u64 data
= msr
->data
;
4267 case MSR_IA32_CR_PAT
:
4268 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
4270 vcpu
->arch
.pat
= data
;
4271 svm
->vmcb
->save
.g_pat
= data
;
4272 mark_dirty(svm
->vmcb
, VMCB_NPT
);
4274 case MSR_IA32_SPEC_CTRL
:
4275 if (!msr
->host_initiated
&&
4276 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBRS
) &&
4277 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_SSBD
))
4280 /* The STIBP bit doesn't fault even if it's not advertised */
4281 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
| SPEC_CTRL_SSBD
))
4284 svm
->spec_ctrl
= data
;
4291 * When it's written (to non-zero) for the first time, pass
4295 * The handling of the MSR bitmap for L2 guests is done in
4296 * nested_svm_vmrun_msrpm.
4297 * We update the L1 MSR bit as well since it will end up
4298 * touching the MSR anyway now.
4300 set_msr_interception(svm
->msrpm
, MSR_IA32_SPEC_CTRL
, 1, 1);
4302 case MSR_IA32_PRED_CMD
:
4303 if (!msr
->host_initiated
&&
4304 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBPB
))
4307 if (data
& ~PRED_CMD_IBPB
)
4313 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
4314 if (is_guest_mode(vcpu
))
4316 set_msr_interception(svm
->msrpm
, MSR_IA32_PRED_CMD
, 0, 1);
4318 case MSR_AMD64_VIRT_SPEC_CTRL
:
4319 if (!msr
->host_initiated
&&
4320 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
4323 if (data
& ~SPEC_CTRL_SSBD
)
4326 svm
->virt_spec_ctrl
= data
;
4329 svm
->vmcb
->save
.star
= data
;
4331 #ifdef CONFIG_X86_64
4333 svm
->vmcb
->save
.lstar
= data
;
4336 svm
->vmcb
->save
.cstar
= data
;
4338 case MSR_KERNEL_GS_BASE
:
4339 svm
->vmcb
->save
.kernel_gs_base
= data
;
4341 case MSR_SYSCALL_MASK
:
4342 svm
->vmcb
->save
.sfmask
= data
;
4345 case MSR_IA32_SYSENTER_CS
:
4346 svm
->vmcb
->save
.sysenter_cs
= data
;
4348 case MSR_IA32_SYSENTER_EIP
:
4349 svm
->sysenter_eip
= data
;
4350 svm
->vmcb
->save
.sysenter_eip
= data
;
4352 case MSR_IA32_SYSENTER_ESP
:
4353 svm
->sysenter_esp
= data
;
4354 svm
->vmcb
->save
.sysenter_esp
= data
;
4357 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
4361 * This is rare, so we update the MSR here instead of using
4362 * direct_access_msrs. Doing that would require a rdmsr in
4365 svm
->tsc_aux
= data
;
4366 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
4368 case MSR_IA32_DEBUGCTLMSR
:
4369 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
4370 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4374 if (data
& DEBUGCTL_RESERVED_BITS
)
4377 svm
->vmcb
->save
.dbgctl
= data
;
4378 mark_dirty(svm
->vmcb
, VMCB_LBR
);
4379 if (data
& (1ULL<<0))
4380 svm_enable_lbrv(svm
);
4382 svm_disable_lbrv(svm
);
4384 case MSR_VM_HSAVE_PA
:
4385 svm
->nested
.hsave_msr
= data
;
4388 return svm_set_vm_cr(vcpu
, data
);
4390 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
4392 case MSR_F10H_DECFG
: {
4393 struct kvm_msr_entry msr_entry
;
4395 msr_entry
.index
= msr
->index
;
4396 if (svm_get_msr_feature(&msr_entry
))
4399 /* Check the supported bits */
4400 if (data
& ~msr_entry
.data
)
4403 /* Don't allow the guest to change a bit, #GP */
4404 if (!msr
->host_initiated
&& (data
^ msr_entry
.data
))
4407 svm
->msr_decfg
= data
;
4410 case MSR_IA32_APICBASE
:
4411 if (kvm_vcpu_apicv_active(vcpu
))
4412 avic_update_vapic_bar(to_svm(vcpu
), data
);
4415 return kvm_set_msr_common(vcpu
, msr
);
4420 static int wrmsr_interception(struct vcpu_svm
*svm
)
4422 struct msr_data msr
;
4423 u32 ecx
= kvm_rcx_read(&svm
->vcpu
);
4424 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
4428 msr
.host_initiated
= false;
4430 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
4431 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
4432 trace_kvm_msr_write_ex(ecx
, data
);
4433 kvm_inject_gp(&svm
->vcpu
, 0);
4436 trace_kvm_msr_write(ecx
, data
);
4437 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4441 static int msr_interception(struct vcpu_svm
*svm
)
4443 if (svm
->vmcb
->control
.exit_info_1
)
4444 return wrmsr_interception(svm
);
4446 return rdmsr_interception(svm
);
4449 static int interrupt_window_interception(struct vcpu_svm
*svm
)
4451 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4452 svm_clear_vintr(svm
);
4453 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
4454 mark_dirty(svm
->vmcb
, VMCB_INTR
);
4455 ++svm
->vcpu
.stat
.irq_window_exits
;
4459 static int pause_interception(struct vcpu_svm
*svm
)
4461 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
4462 bool in_kernel
= (svm_get_cpl(vcpu
) == 0);
4464 if (pause_filter_thresh
)
4465 grow_ple_window(vcpu
);
4467 kvm_vcpu_on_spin(vcpu
, in_kernel
);
4471 static int nop_interception(struct vcpu_svm
*svm
)
4473 return kvm_skip_emulated_instruction(&(svm
->vcpu
));
4476 static int monitor_interception(struct vcpu_svm
*svm
)
4478 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
4479 return nop_interception(svm
);
4482 static int mwait_interception(struct vcpu_svm
*svm
)
4484 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
4485 return nop_interception(svm
);
4488 enum avic_ipi_failure_cause
{
4489 AVIC_IPI_FAILURE_INVALID_INT_TYPE
,
4490 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
,
4491 AVIC_IPI_FAILURE_INVALID_TARGET
,
4492 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
,
4495 static int avic_incomplete_ipi_interception(struct vcpu_svm
*svm
)
4497 u32 icrh
= svm
->vmcb
->control
.exit_info_1
>> 32;
4498 u32 icrl
= svm
->vmcb
->control
.exit_info_1
;
4499 u32 id
= svm
->vmcb
->control
.exit_info_2
>> 32;
4500 u32 index
= svm
->vmcb
->control
.exit_info_2
& 0xFF;
4501 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4503 trace_kvm_avic_incomplete_ipi(svm
->vcpu
.vcpu_id
, icrh
, icrl
, id
, index
);
4506 case AVIC_IPI_FAILURE_INVALID_INT_TYPE
:
4508 * AVIC hardware handles the generation of
4509 * IPIs when the specified Message Type is Fixed
4510 * (also known as fixed delivery mode) and
4511 * the Trigger Mode is edge-triggered. The hardware
4512 * also supports self and broadcast delivery modes
4513 * specified via the Destination Shorthand(DSH)
4514 * field of the ICRL. Logical and physical APIC ID
4515 * formats are supported. All other IPI types cause
4516 * a #VMEXIT, which needs to emulated.
4518 kvm_lapic_reg_write(apic
, APIC_ICR2
, icrh
);
4519 kvm_lapic_reg_write(apic
, APIC_ICR
, icrl
);
4521 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
: {
4523 struct kvm_vcpu
*vcpu
;
4524 struct kvm
*kvm
= svm
->vcpu
.kvm
;
4525 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4528 * At this point, we expect that the AVIC HW has already
4529 * set the appropriate IRR bits on the valid target
4530 * vcpus. So, we just need to kick the appropriate vcpu.
4532 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
4533 bool m
= kvm_apic_match_dest(vcpu
, apic
,
4534 icrl
& KVM_APIC_SHORT_MASK
,
4535 GET_APIC_DEST_FIELD(icrh
),
4536 icrl
& KVM_APIC_DEST_MASK
);
4538 if (m
&& !avic_vcpu_is_running(vcpu
))
4539 kvm_vcpu_wake_up(vcpu
);
4543 case AVIC_IPI_FAILURE_INVALID_TARGET
:
4544 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4545 index
, svm
->vcpu
.vcpu_id
, icrh
, icrl
);
4547 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
:
4548 WARN_ONCE(1, "Invalid backing page\n");
4551 pr_err("Unknown IPI interception\n");
4557 static u32
*avic_get_logical_id_entry(struct kvm_vcpu
*vcpu
, u32 ldr
, bool flat
)
4559 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
4561 u32
*logical_apic_id_table
;
4562 int dlid
= GET_APIC_LOGICAL_ID(ldr
);
4567 if (flat
) { /* flat */
4568 index
= ffs(dlid
) - 1;
4571 } else { /* cluster */
4572 int cluster
= (dlid
& 0xf0) >> 4;
4573 int apic
= ffs(dlid
& 0x0f) - 1;
4575 if ((apic
< 0) || (apic
> 7) ||
4578 index
= (cluster
<< 2) + apic
;
4581 logical_apic_id_table
= (u32
*) page_address(kvm_svm
->avic_logical_id_table_page
);
4583 return &logical_apic_id_table
[index
];
4586 static int avic_ldr_write(struct kvm_vcpu
*vcpu
, u8 g_physical_id
, u32 ldr
)
4589 u32
*entry
, new_entry
;
4591 flat
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
) == APIC_DFR_FLAT
;
4592 entry
= avic_get_logical_id_entry(vcpu
, ldr
, flat
);
4596 new_entry
= READ_ONCE(*entry
);
4597 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
;
4598 new_entry
|= (g_physical_id
& AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
);
4599 new_entry
|= AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
4600 WRITE_ONCE(*entry
, new_entry
);
4605 static void avic_invalidate_logical_id_entry(struct kvm_vcpu
*vcpu
)
4607 struct vcpu_svm
*svm
= to_svm(vcpu
);
4608 bool flat
= svm
->dfr_reg
== APIC_DFR_FLAT
;
4609 u32
*entry
= avic_get_logical_id_entry(vcpu
, svm
->ldr_reg
, flat
);
4612 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT
, (unsigned long *)entry
);
4615 static int avic_handle_ldr_update(struct kvm_vcpu
*vcpu
)
4618 struct vcpu_svm
*svm
= to_svm(vcpu
);
4619 u32 ldr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LDR
);
4621 if (ldr
== svm
->ldr_reg
)
4624 avic_invalidate_logical_id_entry(vcpu
);
4627 ret
= avic_ldr_write(vcpu
, vcpu
->vcpu_id
, ldr
);
4635 static int avic_handle_apic_id_update(struct kvm_vcpu
*vcpu
)
4638 struct vcpu_svm
*svm
= to_svm(vcpu
);
4639 u32 apic_id_reg
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_ID
);
4640 u32 id
= (apic_id_reg
>> 24) & 0xff;
4642 if (vcpu
->vcpu_id
== id
)
4645 old
= avic_get_physical_id_entry(vcpu
, vcpu
->vcpu_id
);
4646 new = avic_get_physical_id_entry(vcpu
, id
);
4650 /* We need to move physical_id_entry to new offset */
4653 to_svm(vcpu
)->avic_physical_id_cache
= new;
4656 * Also update the guest physical APIC ID in the logical
4657 * APIC ID table entry if already setup the LDR.
4660 avic_handle_ldr_update(vcpu
);
4665 static void avic_handle_dfr_update(struct kvm_vcpu
*vcpu
)
4667 struct vcpu_svm
*svm
= to_svm(vcpu
);
4668 u32 dfr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
);
4670 if (svm
->dfr_reg
== dfr
)
4673 avic_invalidate_logical_id_entry(vcpu
);
4677 static int avic_unaccel_trap_write(struct vcpu_svm
*svm
)
4679 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4680 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4681 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4685 if (avic_handle_apic_id_update(&svm
->vcpu
))
4689 if (avic_handle_ldr_update(&svm
->vcpu
))
4693 avic_handle_dfr_update(&svm
->vcpu
);
4699 kvm_lapic_reg_write(apic
, offset
, kvm_lapic_get_reg(apic
, offset
));
4704 static bool is_avic_unaccelerated_access_trap(u32 offset
)
4733 static int avic_unaccelerated_access_interception(struct vcpu_svm
*svm
)
4736 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4737 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4738 u32 vector
= svm
->vmcb
->control
.exit_info_2
&
4739 AVIC_UNACCEL_ACCESS_VECTOR_MASK
;
4740 bool write
= (svm
->vmcb
->control
.exit_info_1
>> 32) &
4741 AVIC_UNACCEL_ACCESS_WRITE_MASK
;
4742 bool trap
= is_avic_unaccelerated_access_trap(offset
);
4744 trace_kvm_avic_unaccelerated_access(svm
->vcpu
.vcpu_id
, offset
,
4745 trap
, write
, vector
);
4748 WARN_ONCE(!write
, "svm: Handling trap read.\n");
4749 ret
= avic_unaccel_trap_write(svm
);
4751 /* Handling Fault */
4752 ret
= (kvm_emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
);
4758 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
4759 [SVM_EXIT_READ_CR0
] = cr_interception
,
4760 [SVM_EXIT_READ_CR3
] = cr_interception
,
4761 [SVM_EXIT_READ_CR4
] = cr_interception
,
4762 [SVM_EXIT_READ_CR8
] = cr_interception
,
4763 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
4764 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
4765 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
4766 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
4767 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
4768 [SVM_EXIT_READ_DR0
] = dr_interception
,
4769 [SVM_EXIT_READ_DR1
] = dr_interception
,
4770 [SVM_EXIT_READ_DR2
] = dr_interception
,
4771 [SVM_EXIT_READ_DR3
] = dr_interception
,
4772 [SVM_EXIT_READ_DR4
] = dr_interception
,
4773 [SVM_EXIT_READ_DR5
] = dr_interception
,
4774 [SVM_EXIT_READ_DR6
] = dr_interception
,
4775 [SVM_EXIT_READ_DR7
] = dr_interception
,
4776 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
4777 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
4778 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
4779 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
4780 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
4781 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
4782 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
4783 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
4784 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
4785 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
4786 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
4787 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
4788 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
4789 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
4790 [SVM_EXIT_EXCP_BASE
+ GP_VECTOR
] = gp_interception
,
4791 [SVM_EXIT_INTR
] = intr_interception
,
4792 [SVM_EXIT_NMI
] = nmi_interception
,
4793 [SVM_EXIT_SMI
] = nop_on_interception
,
4794 [SVM_EXIT_INIT
] = nop_on_interception
,
4795 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
4796 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
4797 [SVM_EXIT_CPUID
] = cpuid_interception
,
4798 [SVM_EXIT_IRET
] = iret_interception
,
4799 [SVM_EXIT_INVD
] = emulate_on_interception
,
4800 [SVM_EXIT_PAUSE
] = pause_interception
,
4801 [SVM_EXIT_HLT
] = halt_interception
,
4802 [SVM_EXIT_INVLPG
] = invlpg_interception
,
4803 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
4804 [SVM_EXIT_IOIO
] = io_interception
,
4805 [SVM_EXIT_MSR
] = msr_interception
,
4806 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
4807 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
4808 [SVM_EXIT_VMRUN
] = vmrun_interception
,
4809 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
4810 [SVM_EXIT_VMLOAD
] = vmload_interception
,
4811 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
4812 [SVM_EXIT_STGI
] = stgi_interception
,
4813 [SVM_EXIT_CLGI
] = clgi_interception
,
4814 [SVM_EXIT_SKINIT
] = skinit_interception
,
4815 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
4816 [SVM_EXIT_MONITOR
] = monitor_interception
,
4817 [SVM_EXIT_MWAIT
] = mwait_interception
,
4818 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
4819 [SVM_EXIT_NPF
] = npf_interception
,
4820 [SVM_EXIT_RSM
] = rsm_interception
,
4821 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
4822 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
4825 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
4827 struct vcpu_svm
*svm
= to_svm(vcpu
);
4828 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4829 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
4831 if (!dump_invalid_vmcb
) {
4832 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
4836 pr_err("VMCB Control Area:\n");
4837 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
4838 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
4839 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
4840 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
4841 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
4842 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
4843 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
4844 pr_err("%-20s%d\n", "pause filter threshold:",
4845 control
->pause_filter_thresh
);
4846 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
4847 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
4848 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
4849 pr_err("%-20s%d\n", "asid:", control
->asid
);
4850 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
4851 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
4852 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
4853 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
4854 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
4855 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
4856 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
4857 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
4858 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
4859 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
4860 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
4861 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
4862 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
4863 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
4864 pr_err("%-20s%lld\n", "virt_ext:", control
->virt_ext
);
4865 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
4866 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
4867 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
4868 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
4869 pr_err("VMCB State Save Area:\n");
4870 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4872 save
->es
.selector
, save
->es
.attrib
,
4873 save
->es
.limit
, save
->es
.base
);
4874 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4876 save
->cs
.selector
, save
->cs
.attrib
,
4877 save
->cs
.limit
, save
->cs
.base
);
4878 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4880 save
->ss
.selector
, save
->ss
.attrib
,
4881 save
->ss
.limit
, save
->ss
.base
);
4882 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4884 save
->ds
.selector
, save
->ds
.attrib
,
4885 save
->ds
.limit
, save
->ds
.base
);
4886 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4888 save
->fs
.selector
, save
->fs
.attrib
,
4889 save
->fs
.limit
, save
->fs
.base
);
4890 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4892 save
->gs
.selector
, save
->gs
.attrib
,
4893 save
->gs
.limit
, save
->gs
.base
);
4894 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4896 save
->gdtr
.selector
, save
->gdtr
.attrib
,
4897 save
->gdtr
.limit
, save
->gdtr
.base
);
4898 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4900 save
->ldtr
.selector
, save
->ldtr
.attrib
,
4901 save
->ldtr
.limit
, save
->ldtr
.base
);
4902 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4904 save
->idtr
.selector
, save
->idtr
.attrib
,
4905 save
->idtr
.limit
, save
->idtr
.base
);
4906 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4908 save
->tr
.selector
, save
->tr
.attrib
,
4909 save
->tr
.limit
, save
->tr
.base
);
4910 pr_err("cpl: %d efer: %016llx\n",
4911 save
->cpl
, save
->efer
);
4912 pr_err("%-15s %016llx %-13s %016llx\n",
4913 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
4914 pr_err("%-15s %016llx %-13s %016llx\n",
4915 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
4916 pr_err("%-15s %016llx %-13s %016llx\n",
4917 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
4918 pr_err("%-15s %016llx %-13s %016llx\n",
4919 "rip:", save
->rip
, "rflags:", save
->rflags
);
4920 pr_err("%-15s %016llx %-13s %016llx\n",
4921 "rsp:", save
->rsp
, "rax:", save
->rax
);
4922 pr_err("%-15s %016llx %-13s %016llx\n",
4923 "star:", save
->star
, "lstar:", save
->lstar
);
4924 pr_err("%-15s %016llx %-13s %016llx\n",
4925 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
4926 pr_err("%-15s %016llx %-13s %016llx\n",
4927 "kernel_gs_base:", save
->kernel_gs_base
,
4928 "sysenter_cs:", save
->sysenter_cs
);
4929 pr_err("%-15s %016llx %-13s %016llx\n",
4930 "sysenter_esp:", save
->sysenter_esp
,
4931 "sysenter_eip:", save
->sysenter_eip
);
4932 pr_err("%-15s %016llx %-13s %016llx\n",
4933 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
4934 pr_err("%-15s %016llx %-13s %016llx\n",
4935 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
4936 pr_err("%-15s %016llx %-13s %016llx\n",
4937 "excp_from:", save
->last_excp_from
,
4938 "excp_to:", save
->last_excp_to
);
4941 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4943 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
4945 *info1
= control
->exit_info_1
;
4946 *info2
= control
->exit_info_2
;
4949 static int handle_exit(struct kvm_vcpu
*vcpu
)
4951 struct vcpu_svm
*svm
= to_svm(vcpu
);
4952 struct kvm_run
*kvm_run
= vcpu
->run
;
4953 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
4955 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
4957 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
4958 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
4960 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
4962 if (unlikely(svm
->nested
.exit_required
)) {
4963 nested_svm_vmexit(svm
);
4964 svm
->nested
.exit_required
= false;
4969 if (is_guest_mode(vcpu
)) {
4972 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
4973 svm
->vmcb
->control
.exit_info_1
,
4974 svm
->vmcb
->control
.exit_info_2
,
4975 svm
->vmcb
->control
.exit_int_info
,
4976 svm
->vmcb
->control
.exit_int_info_err
,
4979 vmexit
= nested_svm_exit_special(svm
);
4981 if (vmexit
== NESTED_EXIT_CONTINUE
)
4982 vmexit
= nested_svm_exit_handled(svm
);
4984 if (vmexit
== NESTED_EXIT_DONE
)
4988 svm_complete_interrupts(svm
);
4990 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
4991 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4992 kvm_run
->fail_entry
.hardware_entry_failure_reason
4993 = svm
->vmcb
->control
.exit_code
;
4998 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
4999 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
5000 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
5001 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
5002 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
5004 __func__
, svm
->vmcb
->control
.exit_int_info
,
5007 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
5008 || !svm_exit_handlers
[exit_code
]) {
5009 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
5010 kvm_queue_exception(vcpu
, UD_VECTOR
);
5014 return svm_exit_handlers
[exit_code
](svm
);
5017 static void reload_tss(struct kvm_vcpu
*vcpu
)
5019 int cpu
= raw_smp_processor_id();
5021 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
5022 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
5026 static void pre_sev_run(struct vcpu_svm
*svm
, int cpu
)
5028 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
5029 int asid
= sev_get_asid(svm
->vcpu
.kvm
);
5031 /* Assign the asid allocated with this SEV guest */
5032 svm
->vmcb
->control
.asid
= asid
;
5037 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5038 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5040 if (sd
->sev_vmcbs
[asid
] == svm
->vmcb
&&
5041 svm
->last_cpu
== cpu
)
5044 svm
->last_cpu
= cpu
;
5045 sd
->sev_vmcbs
[asid
] = svm
->vmcb
;
5046 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
5047 mark_dirty(svm
->vmcb
, VMCB_ASID
);
5050 static void pre_svm_run(struct vcpu_svm
*svm
)
5052 int cpu
= raw_smp_processor_id();
5054 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
5056 if (sev_guest(svm
->vcpu
.kvm
))
5057 return pre_sev_run(svm
, cpu
);
5059 /* FIXME: handle wraparound of asid_generation */
5060 if (svm
->asid_generation
!= sd
->asid_generation
)
5064 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
5066 struct vcpu_svm
*svm
= to_svm(vcpu
);
5068 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
5069 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
5070 set_intercept(svm
, INTERCEPT_IRET
);
5071 ++vcpu
->stat
.nmi_injections
;
5074 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
5076 struct vmcb_control_area
*control
;
5078 /* The following fields are ignored when AVIC is enabled */
5079 control
= &svm
->vmcb
->control
;
5080 control
->int_vector
= irq
;
5081 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
5082 control
->int_ctl
|= V_IRQ_MASK
|
5083 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
5084 mark_dirty(svm
->vmcb
, VMCB_INTR
);
5087 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
5089 struct vcpu_svm
*svm
= to_svm(vcpu
);
5091 BUG_ON(!(gif_set(svm
)));
5093 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
5094 ++vcpu
->stat
.irq_injections
;
5096 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
5097 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
5100 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu
*vcpu
)
5102 return is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
);
5105 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
5107 struct vcpu_svm
*svm
= to_svm(vcpu
);
5109 if (svm_nested_virtualize_tpr(vcpu
) ||
5110 kvm_vcpu_apicv_active(vcpu
))
5113 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
5119 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
5122 static void svm_set_virtual_apic_mode(struct kvm_vcpu
*vcpu
)
5127 static bool svm_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5129 return avic
&& irqchip_split(vcpu
->kvm
);
5132 static void svm_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
5136 static void svm_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
5140 /* Note: Currently only used by Hyper-V. */
5141 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5143 struct vcpu_svm
*svm
= to_svm(vcpu
);
5144 struct vmcb
*vmcb
= svm
->vmcb
;
5146 if (kvm_vcpu_apicv_active(vcpu
))
5147 vmcb
->control
.int_ctl
|= AVIC_ENABLE_MASK
;
5149 vmcb
->control
.int_ctl
&= ~AVIC_ENABLE_MASK
;
5150 mark_dirty(vmcb
, VMCB_AVIC
);
5153 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
5158 static void svm_deliver_avic_intr(struct kvm_vcpu
*vcpu
, int vec
)
5160 kvm_lapic_set_irr(vec
, vcpu
->arch
.apic
);
5161 smp_mb__after_atomic();
5163 if (avic_vcpu_is_running(vcpu
))
5164 wrmsrl(SVM_AVIC_DOORBELL
,
5165 kvm_cpu_get_apicid(vcpu
->cpu
));
5167 kvm_vcpu_wake_up(vcpu
);
5170 static void svm_ir_list_del(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
5172 unsigned long flags
;
5173 struct amd_svm_iommu_ir
*cur
;
5175 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
5176 list_for_each_entry(cur
, &svm
->ir_list
, node
) {
5177 if (cur
->data
!= pi
->ir_data
)
5179 list_del(&cur
->node
);
5183 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
5186 static int svm_ir_list_add(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
5189 unsigned long flags
;
5190 struct amd_svm_iommu_ir
*ir
;
5193 * In some cases, the existing irte is updaed and re-set,
5194 * so we need to check here if it's already been * added
5197 if (pi
->ir_data
&& (pi
->prev_ga_tag
!= 0)) {
5198 struct kvm
*kvm
= svm
->vcpu
.kvm
;
5199 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(pi
->prev_ga_tag
);
5200 struct kvm_vcpu
*prev_vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
5201 struct vcpu_svm
*prev_svm
;
5208 prev_svm
= to_svm(prev_vcpu
);
5209 svm_ir_list_del(prev_svm
, pi
);
5213 * Allocating new amd_iommu_pi_data, which will get
5214 * add to the per-vcpu ir_list.
5216 ir
= kzalloc(sizeof(struct amd_svm_iommu_ir
), GFP_KERNEL_ACCOUNT
);
5221 ir
->data
= pi
->ir_data
;
5223 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
5224 list_add(&ir
->node
, &svm
->ir_list
);
5225 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
5232 * The HW cannot support posting multicast/broadcast
5233 * interrupts to a vCPU. So, we still use legacy interrupt
5234 * remapping for these kind of interrupts.
5236 * For lowest-priority interrupts, we only support
5237 * those with single CPU as the destination, e.g. user
5238 * configures the interrupts via /proc/irq or uses
5239 * irqbalance to make the interrupts single-CPU.
5242 get_pi_vcpu_info(struct kvm
*kvm
, struct kvm_kernel_irq_routing_entry
*e
,
5243 struct vcpu_data
*vcpu_info
, struct vcpu_svm
**svm
)
5245 struct kvm_lapic_irq irq
;
5246 struct kvm_vcpu
*vcpu
= NULL
;
5248 kvm_set_msi_irq(kvm
, e
, &irq
);
5250 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
5251 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5252 __func__
, irq
.vector
);
5256 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__
,
5258 *svm
= to_svm(vcpu
);
5259 vcpu_info
->pi_desc_addr
= __sme_set(page_to_phys((*svm
)->avic_backing_page
));
5260 vcpu_info
->vector
= irq
.vector
;
5266 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5269 * @host_irq: host irq of the interrupt
5270 * @guest_irq: gsi of the interrupt
5271 * @set: set or unset PI
5272 * returns 0 on success, < 0 on failure
5274 static int svm_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
5275 uint32_t guest_irq
, bool set
)
5277 struct kvm_kernel_irq_routing_entry
*e
;
5278 struct kvm_irq_routing_table
*irq_rt
;
5279 int idx
, ret
= -EINVAL
;
5281 if (!kvm_arch_has_assigned_device(kvm
) ||
5282 !irq_remapping_cap(IRQ_POSTING_CAP
))
5285 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5286 __func__
, host_irq
, guest_irq
, set
);
5288 idx
= srcu_read_lock(&kvm
->irq_srcu
);
5289 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
5290 WARN_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
5292 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
5293 struct vcpu_data vcpu_info
;
5294 struct vcpu_svm
*svm
= NULL
;
5296 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
5300 * Here, we setup with legacy mode in the following cases:
5301 * 1. When cannot target interrupt to a specific vcpu.
5302 * 2. Unsetting posted interrupt.
5303 * 3. APIC virtialization is disabled for the vcpu.
5305 if (!get_pi_vcpu_info(kvm
, e
, &vcpu_info
, &svm
) && set
&&
5306 kvm_vcpu_apicv_active(&svm
->vcpu
)) {
5307 struct amd_iommu_pi_data pi
;
5309 /* Try to enable guest_mode in IRTE */
5310 pi
.base
= __sme_set(page_to_phys(svm
->avic_backing_page
) &
5312 pi
.ga_tag
= AVIC_GATAG(to_kvm_svm(kvm
)->avic_vm_id
,
5314 pi
.is_guest_mode
= true;
5315 pi
.vcpu_data
= &vcpu_info
;
5316 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
5319 * Here, we successfully setting up vcpu affinity in
5320 * IOMMU guest mode. Now, we need to store the posted
5321 * interrupt information in a per-vcpu ir_list so that
5322 * we can reference to them directly when we update vcpu
5323 * scheduling information in IOMMU irte.
5325 if (!ret
&& pi
.is_guest_mode
)
5326 svm_ir_list_add(svm
, &pi
);
5328 /* Use legacy mode in IRTE */
5329 struct amd_iommu_pi_data pi
;
5332 * Here, pi is used to:
5333 * - Tell IOMMU to use legacy mode for this interrupt.
5334 * - Retrieve ga_tag of prior interrupt remapping data.
5336 pi
.is_guest_mode
= false;
5337 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
5340 * Check if the posted interrupt was previously
5341 * setup with the guest_mode by checking if the ga_tag
5342 * was cached. If so, we need to clean up the per-vcpu
5345 if (!ret
&& pi
.prev_ga_tag
) {
5346 int id
= AVIC_GATAG_TO_VCPUID(pi
.prev_ga_tag
);
5347 struct kvm_vcpu
*vcpu
;
5349 vcpu
= kvm_get_vcpu_by_id(kvm
, id
);
5351 svm_ir_list_del(to_svm(vcpu
), &pi
);
5356 trace_kvm_pi_irte_update(host_irq
, svm
->vcpu
.vcpu_id
,
5357 e
->gsi
, vcpu_info
.vector
,
5358 vcpu_info
.pi_desc_addr
, set
);
5362 pr_err("%s: failed to update PI IRTE\n", __func__
);
5369 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
5373 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
5375 struct vcpu_svm
*svm
= to_svm(vcpu
);
5376 struct vmcb
*vmcb
= svm
->vmcb
;
5378 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
5379 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
5380 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
5385 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5387 struct vcpu_svm
*svm
= to_svm(vcpu
);
5389 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
5392 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5394 struct vcpu_svm
*svm
= to_svm(vcpu
);
5397 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
5398 set_intercept(svm
, INTERCEPT_IRET
);
5400 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
5401 clr_intercept(svm
, INTERCEPT_IRET
);
5405 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5407 struct vcpu_svm
*svm
= to_svm(vcpu
);
5408 struct vmcb
*vmcb
= svm
->vmcb
;
5411 if (!gif_set(svm
) ||
5412 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
5415 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
5417 if (is_guest_mode(vcpu
))
5418 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
5423 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5425 struct vcpu_svm
*svm
= to_svm(vcpu
);
5427 if (kvm_vcpu_apicv_active(vcpu
))
5431 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5432 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5433 * get that intercept, this function will be called again though and
5434 * we'll get the vintr intercept. However, if the vGIF feature is
5435 * enabled, the STGI interception will not occur. Enable the irq
5436 * window under the assumption that the hardware will set the GIF.
5438 if ((vgif_enabled(svm
) || gif_set(svm
)) && nested_svm_intr(svm
)) {
5440 svm_inject_irq(svm
, 0x0);
5444 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5446 struct vcpu_svm
*svm
= to_svm(vcpu
);
5448 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
5450 return; /* IRET will cause a vm exit */
5452 if (!gif_set(svm
)) {
5453 if (vgif_enabled(svm
))
5454 set_intercept(svm
, INTERCEPT_STGI
);
5455 return; /* STGI will cause a vm exit */
5458 if (svm
->nested
.exit_required
)
5459 return; /* we're not going to run the guest yet */
5462 * Something prevents NMI from been injected. Single step over possible
5463 * problem (IRET or exception injection or interrupt shadow)
5465 svm
->nmi_singlestep_guest_rflags
= svm_get_rflags(vcpu
);
5466 svm
->nmi_singlestep
= true;
5467 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
5470 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5475 static int svm_set_identity_map_addr(struct kvm
*kvm
, u64 ident_addr
)
5480 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
)
5482 struct vcpu_svm
*svm
= to_svm(vcpu
);
5484 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
5485 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
5487 svm
->asid_generation
--;
5490 static void svm_flush_tlb_gva(struct kvm_vcpu
*vcpu
, gva_t gva
)
5492 struct vcpu_svm
*svm
= to_svm(vcpu
);
5494 invlpga(gva
, svm
->vmcb
->control
.asid
);
5497 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
5501 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
5503 struct vcpu_svm
*svm
= to_svm(vcpu
);
5505 if (svm_nested_virtualize_tpr(vcpu
))
5508 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
5509 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
5510 kvm_set_cr8(vcpu
, cr8
);
5514 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
5516 struct vcpu_svm
*svm
= to_svm(vcpu
);
5519 if (svm_nested_virtualize_tpr(vcpu
) ||
5520 kvm_vcpu_apicv_active(vcpu
))
5523 cr8
= kvm_get_cr8(vcpu
);
5524 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
5525 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
5528 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
5532 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
5533 unsigned int3_injected
= svm
->int3_injected
;
5535 svm
->int3_injected
= 0;
5538 * If we've made progress since setting HF_IRET_MASK, we've
5539 * executed an IRET and can allow NMI injection.
5541 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
5542 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
5543 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
5544 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
5547 svm
->vcpu
.arch
.nmi_injected
= false;
5548 kvm_clear_exception_queue(&svm
->vcpu
);
5549 kvm_clear_interrupt_queue(&svm
->vcpu
);
5551 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
5554 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
5556 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
5557 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
5560 case SVM_EXITINTINFO_TYPE_NMI
:
5561 svm
->vcpu
.arch
.nmi_injected
= true;
5563 case SVM_EXITINTINFO_TYPE_EXEPT
:
5565 * In case of software exceptions, do not reinject the vector,
5566 * but re-execute the instruction instead. Rewind RIP first
5567 * if we emulated INT3 before.
5569 if (kvm_exception_is_soft(vector
)) {
5570 if (vector
== BP_VECTOR
&& int3_injected
&&
5571 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
5572 kvm_rip_write(&svm
->vcpu
,
5573 kvm_rip_read(&svm
->vcpu
) -
5577 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
5578 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
5579 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
5582 kvm_requeue_exception(&svm
->vcpu
, vector
);
5584 case SVM_EXITINTINFO_TYPE_INTR
:
5585 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
5592 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
5594 struct vcpu_svm
*svm
= to_svm(vcpu
);
5595 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
5597 control
->exit_int_info
= control
->event_inj
;
5598 control
->exit_int_info_err
= control
->event_inj_err
;
5599 control
->event_inj
= 0;
5600 svm_complete_interrupts(svm
);
5603 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
5605 struct vcpu_svm
*svm
= to_svm(vcpu
);
5607 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
5608 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
5609 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
5612 * A vmexit emulation is required before the vcpu can be executed
5615 if (unlikely(svm
->nested
.exit_required
))
5619 * Disable singlestep if we're injecting an interrupt/exception.
5620 * We don't want our modified rflags to be pushed on the stack where
5621 * we might not be able to easily reset them if we disabled NMI
5624 if (svm
->nmi_singlestep
&& svm
->vmcb
->control
.event_inj
) {
5626 * Event injection happens before external interrupts cause a
5627 * vmexit and interrupts are disabled here, so smp_send_reschedule
5628 * is enough to force an immediate vmexit.
5630 disable_nmi_singlestep(svm
);
5631 smp_send_reschedule(vcpu
->cpu
);
5636 sync_lapic_to_cr8(vcpu
);
5638 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
5641 kvm_load_guest_xcr0(vcpu
);
5644 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5645 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5646 * is no need to worry about the conditional branch over the wrmsr
5647 * being speculatively taken.
5649 x86_spec_ctrl_set_guest(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
5654 "push %%" _ASM_BP
"; \n\t"
5655 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
5656 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
5657 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
5658 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
5659 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
5660 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
5661 #ifdef CONFIG_X86_64
5662 "mov %c[r8](%[svm]), %%r8 \n\t"
5663 "mov %c[r9](%[svm]), %%r9 \n\t"
5664 "mov %c[r10](%[svm]), %%r10 \n\t"
5665 "mov %c[r11](%[svm]), %%r11 \n\t"
5666 "mov %c[r12](%[svm]), %%r12 \n\t"
5667 "mov %c[r13](%[svm]), %%r13 \n\t"
5668 "mov %c[r14](%[svm]), %%r14 \n\t"
5669 "mov %c[r15](%[svm]), %%r15 \n\t"
5672 /* Enter guest mode */
5673 "push %%" _ASM_AX
" \n\t"
5674 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
5675 __ex("vmload %%" _ASM_AX
) "\n\t"
5676 __ex("vmrun %%" _ASM_AX
) "\n\t"
5677 __ex("vmsave %%" _ASM_AX
) "\n\t"
5678 "pop %%" _ASM_AX
" \n\t"
5680 /* Save guest registers, load host registers */
5681 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
5682 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
5683 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
5684 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
5685 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
5686 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
5687 #ifdef CONFIG_X86_64
5688 "mov %%r8, %c[r8](%[svm]) \n\t"
5689 "mov %%r9, %c[r9](%[svm]) \n\t"
5690 "mov %%r10, %c[r10](%[svm]) \n\t"
5691 "mov %%r11, %c[r11](%[svm]) \n\t"
5692 "mov %%r12, %c[r12](%[svm]) \n\t"
5693 "mov %%r13, %c[r13](%[svm]) \n\t"
5694 "mov %%r14, %c[r14](%[svm]) \n\t"
5695 "mov %%r15, %c[r15](%[svm]) \n\t"
5697 * Clear host registers marked as clobbered to prevent
5700 "xor %%r8d, %%r8d \n\t"
5701 "xor %%r9d, %%r9d \n\t"
5702 "xor %%r10d, %%r10d \n\t"
5703 "xor %%r11d, %%r11d \n\t"
5704 "xor %%r12d, %%r12d \n\t"
5705 "xor %%r13d, %%r13d \n\t"
5706 "xor %%r14d, %%r14d \n\t"
5707 "xor %%r15d, %%r15d \n\t"
5709 "xor %%ebx, %%ebx \n\t"
5710 "xor %%ecx, %%ecx \n\t"
5711 "xor %%edx, %%edx \n\t"
5712 "xor %%esi, %%esi \n\t"
5713 "xor %%edi, %%edi \n\t"
5717 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
5718 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
5719 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
5720 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
5721 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
5722 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
5723 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
5724 #ifdef CONFIG_X86_64
5725 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
5726 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
5727 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
5728 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
5729 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
5730 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
5731 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
5732 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
5735 #ifdef CONFIG_X86_64
5736 , "rbx", "rcx", "rdx", "rsi", "rdi"
5737 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5739 , "ebx", "ecx", "edx", "esi", "edi"
5743 /* Eliminate branch target predictions from guest mode */
5746 #ifdef CONFIG_X86_64
5747 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
5749 loadsegment(fs
, svm
->host
.fs
);
5750 #ifndef CONFIG_X86_32_LAZY_GS
5751 loadsegment(gs
, svm
->host
.gs
);
5756 * We do not use IBRS in the kernel. If this vCPU has used the
5757 * SPEC_CTRL MSR it may have left it on; save the value and
5758 * turn it off. This is much more efficient than blindly adding
5759 * it to the atomic save/restore list. Especially as the former
5760 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5762 * For non-nested case:
5763 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5767 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5770 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
5771 svm
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
5775 local_irq_disable();
5777 x86_spec_ctrl_restore_host(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
5779 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
5780 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
5781 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
5782 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
5784 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5785 kvm_before_interrupt(&svm
->vcpu
);
5787 kvm_put_guest_xcr0(vcpu
);
5790 /* Any pending NMI will happen here */
5792 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5793 kvm_after_interrupt(&svm
->vcpu
);
5795 sync_cr8_to_lapic(vcpu
);
5799 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
5801 /* if exit due to PF check for async PF */
5802 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
5803 svm
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
5806 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
5807 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
5811 * We need to handle MC intercepts here before the vcpu has a chance to
5812 * change the physical cpu
5814 if (unlikely(svm
->vmcb
->control
.exit_code
==
5815 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
5816 svm_handle_mce(svm
);
5818 mark_all_clean(svm
->vmcb
);
5820 STACK_FRAME_NON_STANDARD(svm_vcpu_run
);
5822 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5824 struct vcpu_svm
*svm
= to_svm(vcpu
);
5826 svm
->vmcb
->save
.cr3
= __sme_set(root
);
5827 mark_dirty(svm
->vmcb
, VMCB_CR
);
5830 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5832 struct vcpu_svm
*svm
= to_svm(vcpu
);
5834 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
5835 mark_dirty(svm
->vmcb
, VMCB_NPT
);
5837 /* Also sync guest cr3 here in case we live migrate */
5838 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
5839 mark_dirty(svm
->vmcb
, VMCB_CR
);
5842 static int is_disabled(void)
5846 rdmsrl(MSR_VM_CR
, vm_cr
);
5847 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
5854 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5857 * Patch in the VMMCALL instruction:
5859 hypercall
[0] = 0x0f;
5860 hypercall
[1] = 0x01;
5861 hypercall
[2] = 0xd9;
5864 static void svm_check_processor_compat(void *rtn
)
5869 static bool svm_cpu_has_accelerated_tpr(void)
5874 static bool svm_has_emulated_msr(int index
)
5877 case MSR_IA32_MCG_EXT_CTL
:
5886 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
5891 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
5893 struct vcpu_svm
*svm
= to_svm(vcpu
);
5895 /* Update nrips enabled cache */
5896 svm
->nrips_enabled
= !!guest_cpuid_has(&svm
->vcpu
, X86_FEATURE_NRIPS
);
5898 if (!kvm_vcpu_apicv_active(vcpu
))
5901 guest_cpuid_clear(vcpu
, X86_FEATURE_X2APIC
);
5904 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5909 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5913 entry
->ecx
|= (1 << 2); /* Set SVM bit */
5916 entry
->eax
= 1; /* SVM revision 1 */
5917 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
5918 ASID emulation to nested SVM */
5919 entry
->ecx
= 0; /* Reserved */
5920 entry
->edx
= 0; /* Per default do not support any
5921 additional features */
5923 /* Support next_rip if host supports it */
5924 if (boot_cpu_has(X86_FEATURE_NRIPS
))
5925 entry
->edx
|= SVM_FEATURE_NRIP
;
5927 /* Support NPT for the guest if enabled */
5929 entry
->edx
|= SVM_FEATURE_NPT
;
5933 /* Support memory encryption cpuid if host supports it */
5934 if (boot_cpu_has(X86_FEATURE_SEV
))
5935 cpuid(0x8000001f, &entry
->eax
, &entry
->ebx
,
5936 &entry
->ecx
, &entry
->edx
);
5941 static int svm_get_lpage_level(void)
5943 return PT_PDPE_LEVEL
;
5946 static bool svm_rdtscp_supported(void)
5948 return boot_cpu_has(X86_FEATURE_RDTSCP
);
5951 static bool svm_invpcid_supported(void)
5956 static bool svm_mpx_supported(void)
5961 static bool svm_xsaves_supported(void)
5966 static bool svm_umip_emulated(void)
5971 static bool svm_pt_supported(void)
5976 static bool svm_has_wbinvd_exit(void)
5981 #define PRE_EX(exit) { .exit_code = (exit), \
5982 .stage = X86_ICPT_PRE_EXCEPT, }
5983 #define POST_EX(exit) { .exit_code = (exit), \
5984 .stage = X86_ICPT_POST_EXCEPT, }
5985 #define POST_MEM(exit) { .exit_code = (exit), \
5986 .stage = X86_ICPT_POST_MEMACCESS, }
5988 static const struct __x86_intercept
{
5990 enum x86_intercept_stage stage
;
5991 } x86_intercept_map
[] = {
5992 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
5993 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5994 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5995 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5996 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
5997 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
5998 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
5999 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
6000 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
6001 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
6002 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
6003 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
6004 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
6005 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
6006 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
6007 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
6008 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
6009 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
6010 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
6011 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
6012 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
6013 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
6014 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
6015 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
6016 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
6017 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
6018 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
6019 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
6020 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
6021 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
6022 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
6023 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
6024 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
6025 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
6026 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
6027 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
6028 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
6029 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
6030 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
6031 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
6032 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
6033 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
6034 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
6035 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
6036 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
6037 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
6044 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
6045 struct x86_instruction_info
*info
,
6046 enum x86_intercept_stage stage
)
6048 struct vcpu_svm
*svm
= to_svm(vcpu
);
6049 int vmexit
, ret
= X86EMUL_CONTINUE
;
6050 struct __x86_intercept icpt_info
;
6051 struct vmcb
*vmcb
= svm
->vmcb
;
6053 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
6056 icpt_info
= x86_intercept_map
[info
->intercept
];
6058 if (stage
!= icpt_info
.stage
)
6061 switch (icpt_info
.exit_code
) {
6062 case SVM_EXIT_READ_CR0
:
6063 if (info
->intercept
== x86_intercept_cr_read
)
6064 icpt_info
.exit_code
+= info
->modrm_reg
;
6066 case SVM_EXIT_WRITE_CR0
: {
6067 unsigned long cr0
, val
;
6070 if (info
->intercept
== x86_intercept_cr_write
)
6071 icpt_info
.exit_code
+= info
->modrm_reg
;
6073 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
6074 info
->intercept
== x86_intercept_clts
)
6077 intercept
= svm
->nested
.intercept
;
6079 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
6082 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
6083 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
6085 if (info
->intercept
== x86_intercept_lmsw
) {
6088 /* lmsw can't clear PE - catch this here */
6089 if (cr0
& X86_CR0_PE
)
6094 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
6098 case SVM_EXIT_READ_DR0
:
6099 case SVM_EXIT_WRITE_DR0
:
6100 icpt_info
.exit_code
+= info
->modrm_reg
;
6103 if (info
->intercept
== x86_intercept_wrmsr
)
6104 vmcb
->control
.exit_info_1
= 1;
6106 vmcb
->control
.exit_info_1
= 0;
6108 case SVM_EXIT_PAUSE
:
6110 * We get this for NOP only, but pause
6111 * is rep not, check this here
6113 if (info
->rep_prefix
!= REPE_PREFIX
)
6116 case SVM_EXIT_IOIO
: {
6120 if (info
->intercept
== x86_intercept_in
||
6121 info
->intercept
== x86_intercept_ins
) {
6122 exit_info
= ((info
->src_val
& 0xffff) << 16) |
6124 bytes
= info
->dst_bytes
;
6126 exit_info
= (info
->dst_val
& 0xffff) << 16;
6127 bytes
= info
->src_bytes
;
6130 if (info
->intercept
== x86_intercept_outs
||
6131 info
->intercept
== x86_intercept_ins
)
6132 exit_info
|= SVM_IOIO_STR_MASK
;
6134 if (info
->rep_prefix
)
6135 exit_info
|= SVM_IOIO_REP_MASK
;
6137 bytes
= min(bytes
, 4u);
6139 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
6141 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
6143 vmcb
->control
.exit_info_1
= exit_info
;
6144 vmcb
->control
.exit_info_2
= info
->next_rip
;
6152 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6153 if (static_cpu_has(X86_FEATURE_NRIPS
))
6154 vmcb
->control
.next_rip
= info
->next_rip
;
6155 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
6156 vmexit
= nested_svm_exit_handled(svm
);
6158 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
6165 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
6169 * We must have an instruction with interrupts enabled, so
6170 * the timer interrupt isn't delayed by the interrupt shadow.
6173 local_irq_disable();
6176 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
6178 if (pause_filter_thresh
)
6179 shrink_ple_window(vcpu
);
6182 static inline void avic_post_state_restore(struct kvm_vcpu
*vcpu
)
6184 if (avic_handle_apic_id_update(vcpu
) != 0)
6186 avic_handle_dfr_update(vcpu
);
6187 avic_handle_ldr_update(vcpu
);
6190 static void svm_setup_mce(struct kvm_vcpu
*vcpu
)
6192 /* [63:9] are reserved. */
6193 vcpu
->arch
.mcg_cap
&= 0x1ff;
6196 static int svm_smi_allowed(struct kvm_vcpu
*vcpu
)
6198 struct vcpu_svm
*svm
= to_svm(vcpu
);
6200 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6204 if (is_guest_mode(&svm
->vcpu
) &&
6205 svm
->nested
.intercept
& (1ULL << INTERCEPT_SMI
)) {
6206 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6207 svm
->vmcb
->control
.exit_code
= SVM_EXIT_SMI
;
6208 svm
->nested
.exit_required
= true;
6215 static int svm_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
6217 struct vcpu_svm
*svm
= to_svm(vcpu
);
6220 if (is_guest_mode(vcpu
)) {
6221 /* FED8h - SVM Guest */
6222 put_smstate(u64
, smstate
, 0x7ed8, 1);
6223 /* FEE0h - SVM Guest VMCB Physical Address */
6224 put_smstate(u64
, smstate
, 0x7ee0, svm
->nested
.vmcb
);
6226 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
6227 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
6228 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
6230 ret
= nested_svm_vmexit(svm
);
6237 static int svm_pre_leave_smm(struct kvm_vcpu
*vcpu
, const char *smstate
)
6239 struct vcpu_svm
*svm
= to_svm(vcpu
);
6240 struct vmcb
*nested_vmcb
;
6241 struct kvm_host_map map
;
6245 guest
= GET_SMSTATE(u64
, smstate
, 0x7ed8);
6246 vmcb
= GET_SMSTATE(u64
, smstate
, 0x7ee0);
6249 if (kvm_vcpu_map(&svm
->vcpu
, gpa_to_gfn(vmcb
), &map
) == -EINVAL
)
6251 nested_vmcb
= map
.hva
;
6252 enter_svm_guest_mode(svm
, vmcb
, nested_vmcb
, &map
);
6257 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
6259 struct vcpu_svm
*svm
= to_svm(vcpu
);
6261 if (!gif_set(svm
)) {
6262 if (vgif_enabled(svm
))
6263 set_intercept(svm
, INTERCEPT_STGI
);
6264 /* STGI will cause a vm exit */
6270 static int sev_asid_new(void)
6275 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6277 pos
= find_next_zero_bit(sev_asid_bitmap
, max_sev_asid
, min_sev_asid
- 1);
6278 if (pos
>= max_sev_asid
)
6281 set_bit(pos
, sev_asid_bitmap
);
6285 static int sev_guest_init(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6287 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6291 if (unlikely(sev
->active
))
6294 asid
= sev_asid_new();
6298 ret
= sev_platform_init(&argp
->error
);
6304 INIT_LIST_HEAD(&sev
->regions_list
);
6309 __sev_asid_free(asid
);
6313 static int sev_bind_asid(struct kvm
*kvm
, unsigned int handle
, int *error
)
6315 struct sev_data_activate
*data
;
6316 int asid
= sev_get_asid(kvm
);
6319 wbinvd_on_all_cpus();
6321 ret
= sev_guest_df_flush(error
);
6325 data
= kzalloc(sizeof(*data
), GFP_KERNEL_ACCOUNT
);
6329 /* activate ASID on the given handle */
6330 data
->handle
= handle
;
6332 ret
= sev_guest_activate(data
, error
);
6338 static int __sev_issue_cmd(int fd
, int id
, void *data
, int *error
)
6347 ret
= sev_issue_cmd_external_user(f
.file
, id
, data
, error
);
6353 static int sev_issue_cmd(struct kvm
*kvm
, int id
, void *data
, int *error
)
6355 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6357 return __sev_issue_cmd(sev
->fd
, id
, data
, error
);
6360 static int sev_launch_start(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6362 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6363 struct sev_data_launch_start
*start
;
6364 struct kvm_sev_launch_start params
;
6365 void *dh_blob
, *session_blob
;
6366 int *error
= &argp
->error
;
6369 if (!sev_guest(kvm
))
6372 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6375 start
= kzalloc(sizeof(*start
), GFP_KERNEL_ACCOUNT
);
6380 if (params
.dh_uaddr
) {
6381 dh_blob
= psp_copy_user_blob(params
.dh_uaddr
, params
.dh_len
);
6382 if (IS_ERR(dh_blob
)) {
6383 ret
= PTR_ERR(dh_blob
);
6387 start
->dh_cert_address
= __sme_set(__pa(dh_blob
));
6388 start
->dh_cert_len
= params
.dh_len
;
6391 session_blob
= NULL
;
6392 if (params
.session_uaddr
) {
6393 session_blob
= psp_copy_user_blob(params
.session_uaddr
, params
.session_len
);
6394 if (IS_ERR(session_blob
)) {
6395 ret
= PTR_ERR(session_blob
);
6399 start
->session_address
= __sme_set(__pa(session_blob
));
6400 start
->session_len
= params
.session_len
;
6403 start
->handle
= params
.handle
;
6404 start
->policy
= params
.policy
;
6406 /* create memory encryption context */
6407 ret
= __sev_issue_cmd(argp
->sev_fd
, SEV_CMD_LAUNCH_START
, start
, error
);
6409 goto e_free_session
;
6411 /* Bind ASID to this guest */
6412 ret
= sev_bind_asid(kvm
, start
->handle
, error
);
6414 goto e_free_session
;
6416 /* return handle to userspace */
6417 params
.handle
= start
->handle
;
6418 if (copy_to_user((void __user
*)(uintptr_t)argp
->data
, ¶ms
, sizeof(params
))) {
6419 sev_unbind_asid(kvm
, start
->handle
);
6421 goto e_free_session
;
6424 sev
->handle
= start
->handle
;
6425 sev
->fd
= argp
->sev_fd
;
6428 kfree(session_blob
);
6436 static unsigned long get_num_contig_pages(unsigned long idx
,
6437 struct page
**inpages
, unsigned long npages
)
6439 unsigned long paddr
, next_paddr
;
6440 unsigned long i
= idx
+ 1, pages
= 1;
6442 /* find the number of contiguous pages starting from idx */
6443 paddr
= __sme_page_pa(inpages
[idx
]);
6444 while (i
< npages
) {
6445 next_paddr
= __sme_page_pa(inpages
[i
++]);
6446 if ((paddr
+ PAGE_SIZE
) == next_paddr
) {
6457 static int sev_launch_update_data(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6459 unsigned long vaddr
, vaddr_end
, next_vaddr
, npages
, pages
, size
, i
;
6460 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6461 struct kvm_sev_launch_update_data params
;
6462 struct sev_data_launch_update_data
*data
;
6463 struct page
**inpages
;
6466 if (!sev_guest(kvm
))
6469 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6472 data
= kzalloc(sizeof(*data
), GFP_KERNEL_ACCOUNT
);
6476 vaddr
= params
.uaddr
;
6478 vaddr_end
= vaddr
+ size
;
6480 /* Lock the user memory. */
6481 inpages
= sev_pin_memory(kvm
, vaddr
, size
, &npages
, 1);
6488 * The LAUNCH_UPDATE command will perform in-place encryption of the
6489 * memory content (i.e it will write the same memory region with C=1).
6490 * It's possible that the cache may contain the data with C=0, i.e.,
6491 * unencrypted so invalidate it first.
6493 sev_clflush_pages(inpages
, npages
);
6495 for (i
= 0; vaddr
< vaddr_end
; vaddr
= next_vaddr
, i
+= pages
) {
6499 * If the user buffer is not page-aligned, calculate the offset
6502 offset
= vaddr
& (PAGE_SIZE
- 1);
6504 /* Calculate the number of pages that can be encrypted in one go. */
6505 pages
= get_num_contig_pages(i
, inpages
, npages
);
6507 len
= min_t(size_t, ((pages
* PAGE_SIZE
) - offset
), size
);
6509 data
->handle
= sev
->handle
;
6511 data
->address
= __sme_page_pa(inpages
[i
]) + offset
;
6512 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_UPDATE_DATA
, data
, &argp
->error
);
6517 next_vaddr
= vaddr
+ len
;
6521 /* content of memory is updated, mark pages dirty */
6522 for (i
= 0; i
< npages
; i
++) {
6523 set_page_dirty_lock(inpages
[i
]);
6524 mark_page_accessed(inpages
[i
]);
6526 /* unlock the user pages */
6527 sev_unpin_memory(kvm
, inpages
, npages
);
6533 static int sev_launch_measure(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6535 void __user
*measure
= (void __user
*)(uintptr_t)argp
->data
;
6536 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6537 struct sev_data_launch_measure
*data
;
6538 struct kvm_sev_launch_measure params
;
6539 void __user
*p
= NULL
;
6543 if (!sev_guest(kvm
))
6546 if (copy_from_user(¶ms
, measure
, sizeof(params
)))
6549 data
= kzalloc(sizeof(*data
), GFP_KERNEL_ACCOUNT
);
6553 /* User wants to query the blob length */
6557 p
= (void __user
*)(uintptr_t)params
.uaddr
;
6559 if (params
.len
> SEV_FW_BLOB_MAX_SIZE
) {
6565 blob
= kmalloc(params
.len
, GFP_KERNEL
);
6569 data
->address
= __psp_pa(blob
);
6570 data
->len
= params
.len
;
6574 data
->handle
= sev
->handle
;
6575 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_MEASURE
, data
, &argp
->error
);
6578 * If we query the session length, FW responded with expected data.
6587 if (copy_to_user(p
, blob
, params
.len
))
6592 params
.len
= data
->len
;
6593 if (copy_to_user(measure
, ¶ms
, sizeof(params
)))
6602 static int sev_launch_finish(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6604 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6605 struct sev_data_launch_finish
*data
;
6608 if (!sev_guest(kvm
))
6611 data
= kzalloc(sizeof(*data
), GFP_KERNEL_ACCOUNT
);
6615 data
->handle
= sev
->handle
;
6616 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_FINISH
, data
, &argp
->error
);
6622 static int sev_guest_status(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6624 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6625 struct kvm_sev_guest_status params
;
6626 struct sev_data_guest_status
*data
;
6629 if (!sev_guest(kvm
))
6632 data
= kzalloc(sizeof(*data
), GFP_KERNEL_ACCOUNT
);
6636 data
->handle
= sev
->handle
;
6637 ret
= sev_issue_cmd(kvm
, SEV_CMD_GUEST_STATUS
, data
, &argp
->error
);
6641 params
.policy
= data
->policy
;
6642 params
.state
= data
->state
;
6643 params
.handle
= data
->handle
;
6645 if (copy_to_user((void __user
*)(uintptr_t)argp
->data
, ¶ms
, sizeof(params
)))
6652 static int __sev_issue_dbg_cmd(struct kvm
*kvm
, unsigned long src
,
6653 unsigned long dst
, int size
,
6654 int *error
, bool enc
)
6656 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6657 struct sev_data_dbg
*data
;
6660 data
= kzalloc(sizeof(*data
), GFP_KERNEL_ACCOUNT
);
6664 data
->handle
= sev
->handle
;
6665 data
->dst_addr
= dst
;
6666 data
->src_addr
= src
;
6669 ret
= sev_issue_cmd(kvm
,
6670 enc
? SEV_CMD_DBG_ENCRYPT
: SEV_CMD_DBG_DECRYPT
,
6676 static int __sev_dbg_decrypt(struct kvm
*kvm
, unsigned long src_paddr
,
6677 unsigned long dst_paddr
, int sz
, int *err
)
6682 * Its safe to read more than we are asked, caller should ensure that
6683 * destination has enough space.
6685 src_paddr
= round_down(src_paddr
, 16);
6686 offset
= src_paddr
& 15;
6687 sz
= round_up(sz
+ offset
, 16);
6689 return __sev_issue_dbg_cmd(kvm
, src_paddr
, dst_paddr
, sz
, err
, false);
6692 static int __sev_dbg_decrypt_user(struct kvm
*kvm
, unsigned long paddr
,
6693 unsigned long __user dst_uaddr
,
6694 unsigned long dst_paddr
,
6697 struct page
*tpage
= NULL
;
6700 /* if inputs are not 16-byte then use intermediate buffer */
6701 if (!IS_ALIGNED(dst_paddr
, 16) ||
6702 !IS_ALIGNED(paddr
, 16) ||
6703 !IS_ALIGNED(size
, 16)) {
6704 tpage
= (void *)alloc_page(GFP_KERNEL
);
6708 dst_paddr
= __sme_page_pa(tpage
);
6711 ret
= __sev_dbg_decrypt(kvm
, paddr
, dst_paddr
, size
, err
);
6716 offset
= paddr
& 15;
6717 if (copy_to_user((void __user
*)(uintptr_t)dst_uaddr
,
6718 page_address(tpage
) + offset
, size
))
6729 static int __sev_dbg_encrypt_user(struct kvm
*kvm
, unsigned long paddr
,
6730 unsigned long __user vaddr
,
6731 unsigned long dst_paddr
,
6732 unsigned long __user dst_vaddr
,
6733 int size
, int *error
)
6735 struct page
*src_tpage
= NULL
;
6736 struct page
*dst_tpage
= NULL
;
6737 int ret
, len
= size
;
6739 /* If source buffer is not aligned then use an intermediate buffer */
6740 if (!IS_ALIGNED(vaddr
, 16)) {
6741 src_tpage
= alloc_page(GFP_KERNEL
);
6745 if (copy_from_user(page_address(src_tpage
),
6746 (void __user
*)(uintptr_t)vaddr
, size
)) {
6747 __free_page(src_tpage
);
6751 paddr
= __sme_page_pa(src_tpage
);
6755 * If destination buffer or length is not aligned then do read-modify-write:
6756 * - decrypt destination in an intermediate buffer
6757 * - copy the source buffer in an intermediate buffer
6758 * - use the intermediate buffer as source buffer
6760 if (!IS_ALIGNED(dst_vaddr
, 16) || !IS_ALIGNED(size
, 16)) {
6763 dst_tpage
= alloc_page(GFP_KERNEL
);
6769 ret
= __sev_dbg_decrypt(kvm
, dst_paddr
,
6770 __sme_page_pa(dst_tpage
), size
, error
);
6775 * If source is kernel buffer then use memcpy() otherwise
6778 dst_offset
= dst_paddr
& 15;
6781 memcpy(page_address(dst_tpage
) + dst_offset
,
6782 page_address(src_tpage
), size
);
6784 if (copy_from_user(page_address(dst_tpage
) + dst_offset
,
6785 (void __user
*)(uintptr_t)vaddr
, size
)) {
6791 paddr
= __sme_page_pa(dst_tpage
);
6792 dst_paddr
= round_down(dst_paddr
, 16);
6793 len
= round_up(size
, 16);
6796 ret
= __sev_issue_dbg_cmd(kvm
, paddr
, dst_paddr
, len
, error
, true);
6800 __free_page(src_tpage
);
6802 __free_page(dst_tpage
);
6806 static int sev_dbg_crypt(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
, bool dec
)
6808 unsigned long vaddr
, vaddr_end
, next_vaddr
;
6809 unsigned long dst_vaddr
;
6810 struct page
**src_p
, **dst_p
;
6811 struct kvm_sev_dbg debug
;
6816 if (!sev_guest(kvm
))
6819 if (copy_from_user(&debug
, (void __user
*)(uintptr_t)argp
->data
, sizeof(debug
)))
6822 if (!debug
.len
|| debug
.src_uaddr
+ debug
.len
< debug
.src_uaddr
)
6824 if (!debug
.dst_uaddr
)
6827 vaddr
= debug
.src_uaddr
;
6829 vaddr_end
= vaddr
+ size
;
6830 dst_vaddr
= debug
.dst_uaddr
;
6832 for (; vaddr
< vaddr_end
; vaddr
= next_vaddr
) {
6833 int len
, s_off
, d_off
;
6835 /* lock userspace source and destination page */
6836 src_p
= sev_pin_memory(kvm
, vaddr
& PAGE_MASK
, PAGE_SIZE
, &n
, 0);
6840 dst_p
= sev_pin_memory(kvm
, dst_vaddr
& PAGE_MASK
, PAGE_SIZE
, &n
, 1);
6842 sev_unpin_memory(kvm
, src_p
, n
);
6847 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6848 * memory content (i.e it will write the same memory region with C=1).
6849 * It's possible that the cache may contain the data with C=0, i.e.,
6850 * unencrypted so invalidate it first.
6852 sev_clflush_pages(src_p
, 1);
6853 sev_clflush_pages(dst_p
, 1);
6856 * Since user buffer may not be page aligned, calculate the
6857 * offset within the page.
6859 s_off
= vaddr
& ~PAGE_MASK
;
6860 d_off
= dst_vaddr
& ~PAGE_MASK
;
6861 len
= min_t(size_t, (PAGE_SIZE
- s_off
), size
);
6864 ret
= __sev_dbg_decrypt_user(kvm
,
6865 __sme_page_pa(src_p
[0]) + s_off
,
6867 __sme_page_pa(dst_p
[0]) + d_off
,
6870 ret
= __sev_dbg_encrypt_user(kvm
,
6871 __sme_page_pa(src_p
[0]) + s_off
,
6873 __sme_page_pa(dst_p
[0]) + d_off
,
6877 sev_unpin_memory(kvm
, src_p
, n
);
6878 sev_unpin_memory(kvm
, dst_p
, n
);
6883 next_vaddr
= vaddr
+ len
;
6884 dst_vaddr
= dst_vaddr
+ len
;
6891 static int sev_launch_secret(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6893 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6894 struct sev_data_launch_secret
*data
;
6895 struct kvm_sev_launch_secret params
;
6896 struct page
**pages
;
6901 if (!sev_guest(kvm
))
6904 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6907 pages
= sev_pin_memory(kvm
, params
.guest_uaddr
, params
.guest_len
, &n
, 1);
6912 * The secret must be copied into contiguous memory region, lets verify
6913 * that userspace memory pages are contiguous before we issue command.
6915 if (get_num_contig_pages(0, pages
, n
) != n
) {
6917 goto e_unpin_memory
;
6921 data
= kzalloc(sizeof(*data
), GFP_KERNEL_ACCOUNT
);
6923 goto e_unpin_memory
;
6925 offset
= params
.guest_uaddr
& (PAGE_SIZE
- 1);
6926 data
->guest_address
= __sme_page_pa(pages
[0]) + offset
;
6927 data
->guest_len
= params
.guest_len
;
6929 blob
= psp_copy_user_blob(params
.trans_uaddr
, params
.trans_len
);
6931 ret
= PTR_ERR(blob
);
6935 data
->trans_address
= __psp_pa(blob
);
6936 data
->trans_len
= params
.trans_len
;
6938 hdr
= psp_copy_user_blob(params
.hdr_uaddr
, params
.hdr_len
);
6943 data
->hdr_address
= __psp_pa(hdr
);
6944 data
->hdr_len
= params
.hdr_len
;
6946 data
->handle
= sev
->handle
;
6947 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_UPDATE_SECRET
, data
, &argp
->error
);
6956 sev_unpin_memory(kvm
, pages
, n
);
6960 static int svm_mem_enc_op(struct kvm
*kvm
, void __user
*argp
)
6962 struct kvm_sev_cmd sev_cmd
;
6965 if (!svm_sev_enabled())
6968 if (copy_from_user(&sev_cmd
, argp
, sizeof(struct kvm_sev_cmd
)))
6971 mutex_lock(&kvm
->lock
);
6973 switch (sev_cmd
.id
) {
6975 r
= sev_guest_init(kvm
, &sev_cmd
);
6977 case KVM_SEV_LAUNCH_START
:
6978 r
= sev_launch_start(kvm
, &sev_cmd
);
6980 case KVM_SEV_LAUNCH_UPDATE_DATA
:
6981 r
= sev_launch_update_data(kvm
, &sev_cmd
);
6983 case KVM_SEV_LAUNCH_MEASURE
:
6984 r
= sev_launch_measure(kvm
, &sev_cmd
);
6986 case KVM_SEV_LAUNCH_FINISH
:
6987 r
= sev_launch_finish(kvm
, &sev_cmd
);
6989 case KVM_SEV_GUEST_STATUS
:
6990 r
= sev_guest_status(kvm
, &sev_cmd
);
6992 case KVM_SEV_DBG_DECRYPT
:
6993 r
= sev_dbg_crypt(kvm
, &sev_cmd
, true);
6995 case KVM_SEV_DBG_ENCRYPT
:
6996 r
= sev_dbg_crypt(kvm
, &sev_cmd
, false);
6998 case KVM_SEV_LAUNCH_SECRET
:
6999 r
= sev_launch_secret(kvm
, &sev_cmd
);
7006 if (copy_to_user(argp
, &sev_cmd
, sizeof(struct kvm_sev_cmd
)))
7010 mutex_unlock(&kvm
->lock
);
7014 static int svm_register_enc_region(struct kvm
*kvm
,
7015 struct kvm_enc_region
*range
)
7017 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
7018 struct enc_region
*region
;
7021 if (!sev_guest(kvm
))
7024 if (range
->addr
> ULONG_MAX
|| range
->size
> ULONG_MAX
)
7027 region
= kzalloc(sizeof(*region
), GFP_KERNEL_ACCOUNT
);
7031 region
->pages
= sev_pin_memory(kvm
, range
->addr
, range
->size
, ®ion
->npages
, 1);
7032 if (!region
->pages
) {
7038 * The guest may change the memory encryption attribute from C=0 -> C=1
7039 * or vice versa for this memory range. Lets make sure caches are
7040 * flushed to ensure that guest data gets written into memory with
7043 sev_clflush_pages(region
->pages
, region
->npages
);
7045 region
->uaddr
= range
->addr
;
7046 region
->size
= range
->size
;
7048 mutex_lock(&kvm
->lock
);
7049 list_add_tail(®ion
->list
, &sev
->regions_list
);
7050 mutex_unlock(&kvm
->lock
);
7059 static struct enc_region
*
7060 find_enc_region(struct kvm
*kvm
, struct kvm_enc_region
*range
)
7062 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
7063 struct list_head
*head
= &sev
->regions_list
;
7064 struct enc_region
*i
;
7066 list_for_each_entry(i
, head
, list
) {
7067 if (i
->uaddr
== range
->addr
&&
7068 i
->size
== range
->size
)
7076 static int svm_unregister_enc_region(struct kvm
*kvm
,
7077 struct kvm_enc_region
*range
)
7079 struct enc_region
*region
;
7082 mutex_lock(&kvm
->lock
);
7084 if (!sev_guest(kvm
)) {
7089 region
= find_enc_region(kvm
, range
);
7095 __unregister_enc_region_locked(kvm
, region
);
7097 mutex_unlock(&kvm
->lock
);
7101 mutex_unlock(&kvm
->lock
);
7105 static uint16_t nested_get_evmcs_version(struct kvm_vcpu
*vcpu
)
7111 static int nested_enable_evmcs(struct kvm_vcpu
*vcpu
,
7112 uint16_t *vmcs_version
)
7114 /* Intel-only feature */
7118 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu
*vcpu
)
7122 is_user
= svm_get_cpl(vcpu
) == 3;
7123 smap
= !kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
7126 * Detect and workaround Errata 1096 Fam_17h_00_0Fh
7128 * In non SEV guest, hypervisor will be able to read the guest
7129 * memory to decode the instruction pointer when insn_len is zero
7130 * so we return true to indicate that decoding is possible.
7132 * But in the SEV guest, the guest memory is encrypted with the
7133 * guest specific key and hypervisor will not be able to decode the
7134 * instruction pointer so we will not able to workaround it. Lets
7135 * print the error and request to kill the guest.
7137 if (is_user
&& smap
) {
7138 if (!sev_guest(vcpu
->kvm
))
7141 pr_err_ratelimited("KVM: Guest triggered AMD Erratum 1096\n");
7142 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7148 static struct kvm_x86_ops svm_x86_ops __ro_after_init
= {
7149 .cpu_has_kvm_support
= has_svm
,
7150 .disabled_by_bios
= is_disabled
,
7151 .hardware_setup
= svm_hardware_setup
,
7152 .hardware_unsetup
= svm_hardware_unsetup
,
7153 .check_processor_compatibility
= svm_check_processor_compat
,
7154 .hardware_enable
= svm_hardware_enable
,
7155 .hardware_disable
= svm_hardware_disable
,
7156 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
7157 .has_emulated_msr
= svm_has_emulated_msr
,
7159 .vcpu_create
= svm_create_vcpu
,
7160 .vcpu_free
= svm_free_vcpu
,
7161 .vcpu_reset
= svm_vcpu_reset
,
7163 .vm_alloc
= svm_vm_alloc
,
7164 .vm_free
= svm_vm_free
,
7165 .vm_init
= avic_vm_init
,
7166 .vm_destroy
= svm_vm_destroy
,
7168 .prepare_guest_switch
= svm_prepare_guest_switch
,
7169 .vcpu_load
= svm_vcpu_load
,
7170 .vcpu_put
= svm_vcpu_put
,
7171 .vcpu_blocking
= svm_vcpu_blocking
,
7172 .vcpu_unblocking
= svm_vcpu_unblocking
,
7174 .update_bp_intercept
= update_bp_intercept
,
7175 .get_msr_feature
= svm_get_msr_feature
,
7176 .get_msr
= svm_get_msr
,
7177 .set_msr
= svm_set_msr
,
7178 .get_segment_base
= svm_get_segment_base
,
7179 .get_segment
= svm_get_segment
,
7180 .set_segment
= svm_set_segment
,
7181 .get_cpl
= svm_get_cpl
,
7182 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
7183 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
7184 .decache_cr3
= svm_decache_cr3
,
7185 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
7186 .set_cr0
= svm_set_cr0
,
7187 .set_cr3
= svm_set_cr3
,
7188 .set_cr4
= svm_set_cr4
,
7189 .set_efer
= svm_set_efer
,
7190 .get_idt
= svm_get_idt
,
7191 .set_idt
= svm_set_idt
,
7192 .get_gdt
= svm_get_gdt
,
7193 .set_gdt
= svm_set_gdt
,
7194 .get_dr6
= svm_get_dr6
,
7195 .set_dr6
= svm_set_dr6
,
7196 .set_dr7
= svm_set_dr7
,
7197 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
7198 .cache_reg
= svm_cache_reg
,
7199 .get_rflags
= svm_get_rflags
,
7200 .set_rflags
= svm_set_rflags
,
7202 .tlb_flush
= svm_flush_tlb
,
7203 .tlb_flush_gva
= svm_flush_tlb_gva
,
7205 .run
= svm_vcpu_run
,
7206 .handle_exit
= handle_exit
,
7207 .skip_emulated_instruction
= skip_emulated_instruction
,
7208 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
7209 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
7210 .patch_hypercall
= svm_patch_hypercall
,
7211 .set_irq
= svm_set_irq
,
7212 .set_nmi
= svm_inject_nmi
,
7213 .queue_exception
= svm_queue_exception
,
7214 .cancel_injection
= svm_cancel_injection
,
7215 .interrupt_allowed
= svm_interrupt_allowed
,
7216 .nmi_allowed
= svm_nmi_allowed
,
7217 .get_nmi_mask
= svm_get_nmi_mask
,
7218 .set_nmi_mask
= svm_set_nmi_mask
,
7219 .enable_nmi_window
= enable_nmi_window
,
7220 .enable_irq_window
= enable_irq_window
,
7221 .update_cr8_intercept
= update_cr8_intercept
,
7222 .set_virtual_apic_mode
= svm_set_virtual_apic_mode
,
7223 .get_enable_apicv
= svm_get_enable_apicv
,
7224 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
7225 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
7226 .hwapic_irr_update
= svm_hwapic_irr_update
,
7227 .hwapic_isr_update
= svm_hwapic_isr_update
,
7228 .sync_pir_to_irr
= kvm_lapic_find_highest_irr
,
7229 .apicv_post_state_restore
= avic_post_state_restore
,
7231 .set_tss_addr
= svm_set_tss_addr
,
7232 .set_identity_map_addr
= svm_set_identity_map_addr
,
7233 .get_tdp_level
= get_npt_level
,
7234 .get_mt_mask
= svm_get_mt_mask
,
7236 .get_exit_info
= svm_get_exit_info
,
7238 .get_lpage_level
= svm_get_lpage_level
,
7240 .cpuid_update
= svm_cpuid_update
,
7242 .rdtscp_supported
= svm_rdtscp_supported
,
7243 .invpcid_supported
= svm_invpcid_supported
,
7244 .mpx_supported
= svm_mpx_supported
,
7245 .xsaves_supported
= svm_xsaves_supported
,
7246 .umip_emulated
= svm_umip_emulated
,
7247 .pt_supported
= svm_pt_supported
,
7249 .set_supported_cpuid
= svm_set_supported_cpuid
,
7251 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
7253 .read_l1_tsc_offset
= svm_read_l1_tsc_offset
,
7254 .write_l1_tsc_offset
= svm_write_l1_tsc_offset
,
7256 .set_tdp_cr3
= set_tdp_cr3
,
7258 .check_intercept
= svm_check_intercept
,
7259 .handle_external_intr
= svm_handle_external_intr
,
7261 .request_immediate_exit
= __kvm_request_immediate_exit
,
7263 .sched_in
= svm_sched_in
,
7265 .pmu_ops
= &amd_pmu_ops
,
7266 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
7267 .update_pi_irte
= svm_update_pi_irte
,
7268 .setup_mce
= svm_setup_mce
,
7270 .smi_allowed
= svm_smi_allowed
,
7271 .pre_enter_smm
= svm_pre_enter_smm
,
7272 .pre_leave_smm
= svm_pre_leave_smm
,
7273 .enable_smi_window
= enable_smi_window
,
7275 .mem_enc_op
= svm_mem_enc_op
,
7276 .mem_enc_reg_region
= svm_register_enc_region
,
7277 .mem_enc_unreg_region
= svm_unregister_enc_region
,
7279 .nested_enable_evmcs
= nested_enable_evmcs
,
7280 .nested_get_evmcs_version
= nested_get_evmcs_version
,
7282 .need_emulation_on_page_fault
= svm_need_emulation_on_page_fault
,
7285 static int __init
svm_init(void)
7287 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
7288 __alignof__(struct vcpu_svm
), THIS_MODULE
);
7291 static void __exit
svm_exit(void)
7296 module_init(svm_init
)
7297 module_exit(svm_exit
)