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Merge tag 'drm-intel-fixes-2019-06-03' of git://anongit.freedesktop.org/drm/drm-intel...
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "pmu.h"
31 #include "hyperv.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
58
59 #include <trace/events/kvm.h>
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
72 #include <asm/intel_pt.h>
73
74 #define CREATE_TRACE_POINTS
75 #include "trace.h"
76
77 #define MAX_IO_MSRS 256
78 #define KVM_MAX_MCE_BANKS 32
79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81
82 #define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84
85 /* EFER defaults:
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
88 */
89 #ifdef CONFIG_X86_64
90 static
91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 #else
93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
94 #endif
95
96 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
98
99 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101
102 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
103 static void process_nmi(struct kvm_vcpu *vcpu);
104 static void enter_smm(struct kvm_vcpu *vcpu);
105 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
106 static void store_regs(struct kvm_vcpu *vcpu);
107 static int sync_regs(struct kvm_vcpu *vcpu);
108
109 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
110 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111
112 static bool __read_mostly ignore_msrs = 0;
113 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114
115 static bool __read_mostly report_ignored_msrs = true;
116 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117
118 unsigned int min_timer_period_us = 200;
119 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120
121 static bool __read_mostly kvmclock_periodic_sync = true;
122 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123
124 bool __read_mostly kvm_has_tsc_control;
125 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
126 u32 __read_mostly kvm_max_guest_tsc_khz;
127 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
128 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130 u64 __read_mostly kvm_max_tsc_scaling_ratio;
131 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
132 u64 __read_mostly kvm_default_tsc_scaling_ratio;
133 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134
135 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
136 static u32 __read_mostly tsc_tolerance_ppm = 250;
137 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138
139 /*
140 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
141 * adaptive tuning starting from default advancment of 1000ns. '0' disables
142 * advancement entirely. Any other value is used as-is and disables adaptive
143 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
144 */
145 static int __read_mostly lapic_timer_advance_ns = -1;
146 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
147
148 static bool __read_mostly vector_hashing = true;
149 module_param(vector_hashing, bool, S_IRUGO);
150
151 bool __read_mostly enable_vmware_backdoor = false;
152 module_param(enable_vmware_backdoor, bool, S_IRUGO);
153 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
154
155 static bool __read_mostly force_emulation_prefix = false;
156 module_param(force_emulation_prefix, bool, S_IRUGO);
157
158 #define KVM_NR_SHARED_MSRS 16
159
160 struct kvm_shared_msrs_global {
161 int nr;
162 u32 msrs[KVM_NR_SHARED_MSRS];
163 };
164
165 struct kvm_shared_msrs {
166 struct user_return_notifier urn;
167 bool registered;
168 struct kvm_shared_msr_values {
169 u64 host;
170 u64 curr;
171 } values[KVM_NR_SHARED_MSRS];
172 };
173
174 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
175 static struct kvm_shared_msrs __percpu *shared_msrs;
176
177 struct kvm_stats_debugfs_item debugfs_entries[] = {
178 { "pf_fixed", VCPU_STAT(pf_fixed) },
179 { "pf_guest", VCPU_STAT(pf_guest) },
180 { "tlb_flush", VCPU_STAT(tlb_flush) },
181 { "invlpg", VCPU_STAT(invlpg) },
182 { "exits", VCPU_STAT(exits) },
183 { "io_exits", VCPU_STAT(io_exits) },
184 { "mmio_exits", VCPU_STAT(mmio_exits) },
185 { "signal_exits", VCPU_STAT(signal_exits) },
186 { "irq_window", VCPU_STAT(irq_window_exits) },
187 { "nmi_window", VCPU_STAT(nmi_window_exits) },
188 { "halt_exits", VCPU_STAT(halt_exits) },
189 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
190 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
191 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
192 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
193 { "hypercalls", VCPU_STAT(hypercalls) },
194 { "request_irq", VCPU_STAT(request_irq_exits) },
195 { "irq_exits", VCPU_STAT(irq_exits) },
196 { "host_state_reload", VCPU_STAT(host_state_reload) },
197 { "fpu_reload", VCPU_STAT(fpu_reload) },
198 { "insn_emulation", VCPU_STAT(insn_emulation) },
199 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
200 { "irq_injections", VCPU_STAT(irq_injections) },
201 { "nmi_injections", VCPU_STAT(nmi_injections) },
202 { "req_event", VCPU_STAT(req_event) },
203 { "l1d_flush", VCPU_STAT(l1d_flush) },
204 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
205 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
206 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
207 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
208 { "mmu_flooded", VM_STAT(mmu_flooded) },
209 { "mmu_recycled", VM_STAT(mmu_recycled) },
210 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
211 { "mmu_unsync", VM_STAT(mmu_unsync) },
212 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
213 { "largepages", VM_STAT(lpages) },
214 { "max_mmu_page_hash_collisions",
215 VM_STAT(max_mmu_page_hash_collisions) },
216 { NULL }
217 };
218
219 u64 __read_mostly host_xcr0;
220
221 struct kmem_cache *x86_fpu_cache;
222 EXPORT_SYMBOL_GPL(x86_fpu_cache);
223
224 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
225
226 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
227 {
228 int i;
229 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
230 vcpu->arch.apf.gfns[i] = ~0;
231 }
232
233 static void kvm_on_user_return(struct user_return_notifier *urn)
234 {
235 unsigned slot;
236 struct kvm_shared_msrs *locals
237 = container_of(urn, struct kvm_shared_msrs, urn);
238 struct kvm_shared_msr_values *values;
239 unsigned long flags;
240
241 /*
242 * Disabling irqs at this point since the following code could be
243 * interrupted and executed through kvm_arch_hardware_disable()
244 */
245 local_irq_save(flags);
246 if (locals->registered) {
247 locals->registered = false;
248 user_return_notifier_unregister(urn);
249 }
250 local_irq_restore(flags);
251 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
252 values = &locals->values[slot];
253 if (values->host != values->curr) {
254 wrmsrl(shared_msrs_global.msrs[slot], values->host);
255 values->curr = values->host;
256 }
257 }
258 }
259
260 static void shared_msr_update(unsigned slot, u32 msr)
261 {
262 u64 value;
263 unsigned int cpu = smp_processor_id();
264 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
265
266 /* only read, and nobody should modify it at this time,
267 * so don't need lock */
268 if (slot >= shared_msrs_global.nr) {
269 printk(KERN_ERR "kvm: invalid MSR slot!");
270 return;
271 }
272 rdmsrl_safe(msr, &value);
273 smsr->values[slot].host = value;
274 smsr->values[slot].curr = value;
275 }
276
277 void kvm_define_shared_msr(unsigned slot, u32 msr)
278 {
279 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
280 shared_msrs_global.msrs[slot] = msr;
281 if (slot >= shared_msrs_global.nr)
282 shared_msrs_global.nr = slot + 1;
283 }
284 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
285
286 static void kvm_shared_msr_cpu_online(void)
287 {
288 unsigned i;
289
290 for (i = 0; i < shared_msrs_global.nr; ++i)
291 shared_msr_update(i, shared_msrs_global.msrs[i]);
292 }
293
294 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
295 {
296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
298 int err;
299
300 if (((value ^ smsr->values[slot].curr) & mask) == 0)
301 return 0;
302 smsr->values[slot].curr = value;
303 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
304 if (err)
305 return 1;
306
307 if (!smsr->registered) {
308 smsr->urn.on_user_return = kvm_on_user_return;
309 user_return_notifier_register(&smsr->urn);
310 smsr->registered = true;
311 }
312 return 0;
313 }
314 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
315
316 static void drop_user_return_notifiers(void)
317 {
318 unsigned int cpu = smp_processor_id();
319 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
320
321 if (smsr->registered)
322 kvm_on_user_return(&smsr->urn);
323 }
324
325 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
326 {
327 return vcpu->arch.apic_base;
328 }
329 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
330
331 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
332 {
333 return kvm_apic_mode(kvm_get_apic_base(vcpu));
334 }
335 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
336
337 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
338 {
339 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
340 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
341 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
342 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
343
344 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
345 return 1;
346 if (!msr_info->host_initiated) {
347 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
348 return 1;
349 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
350 return 1;
351 }
352
353 kvm_lapic_set_base(vcpu, msr_info->data);
354 return 0;
355 }
356 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
357
358 asmlinkage __visible void kvm_spurious_fault(void)
359 {
360 /* Fault while not rebooting. We want the trace. */
361 BUG();
362 }
363 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
364
365 #define EXCPT_BENIGN 0
366 #define EXCPT_CONTRIBUTORY 1
367 #define EXCPT_PF 2
368
369 static int exception_class(int vector)
370 {
371 switch (vector) {
372 case PF_VECTOR:
373 return EXCPT_PF;
374 case DE_VECTOR:
375 case TS_VECTOR:
376 case NP_VECTOR:
377 case SS_VECTOR:
378 case GP_VECTOR:
379 return EXCPT_CONTRIBUTORY;
380 default:
381 break;
382 }
383 return EXCPT_BENIGN;
384 }
385
386 #define EXCPT_FAULT 0
387 #define EXCPT_TRAP 1
388 #define EXCPT_ABORT 2
389 #define EXCPT_INTERRUPT 3
390
391 static int exception_type(int vector)
392 {
393 unsigned int mask;
394
395 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
396 return EXCPT_INTERRUPT;
397
398 mask = 1 << vector;
399
400 /* #DB is trap, as instruction watchpoints are handled elsewhere */
401 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
402 return EXCPT_TRAP;
403
404 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
405 return EXCPT_ABORT;
406
407 /* Reserved exceptions will result in fault */
408 return EXCPT_FAULT;
409 }
410
411 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
412 {
413 unsigned nr = vcpu->arch.exception.nr;
414 bool has_payload = vcpu->arch.exception.has_payload;
415 unsigned long payload = vcpu->arch.exception.payload;
416
417 if (!has_payload)
418 return;
419
420 switch (nr) {
421 case DB_VECTOR:
422 /*
423 * "Certain debug exceptions may clear bit 0-3. The
424 * remaining contents of the DR6 register are never
425 * cleared by the processor".
426 */
427 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
428 /*
429 * DR6.RTM is set by all #DB exceptions that don't clear it.
430 */
431 vcpu->arch.dr6 |= DR6_RTM;
432 vcpu->arch.dr6 |= payload;
433 /*
434 * Bit 16 should be set in the payload whenever the #DB
435 * exception should clear DR6.RTM. This makes the payload
436 * compatible with the pending debug exceptions under VMX.
437 * Though not currently documented in the SDM, this also
438 * makes the payload compatible with the exit qualification
439 * for #DB exceptions under VMX.
440 */
441 vcpu->arch.dr6 ^= payload & DR6_RTM;
442 break;
443 case PF_VECTOR:
444 vcpu->arch.cr2 = payload;
445 break;
446 }
447
448 vcpu->arch.exception.has_payload = false;
449 vcpu->arch.exception.payload = 0;
450 }
451 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
452
453 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
454 unsigned nr, bool has_error, u32 error_code,
455 bool has_payload, unsigned long payload, bool reinject)
456 {
457 u32 prev_nr;
458 int class1, class2;
459
460 kvm_make_request(KVM_REQ_EVENT, vcpu);
461
462 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
463 queue:
464 if (has_error && !is_protmode(vcpu))
465 has_error = false;
466 if (reinject) {
467 /*
468 * On vmentry, vcpu->arch.exception.pending is only
469 * true if an event injection was blocked by
470 * nested_run_pending. In that case, however,
471 * vcpu_enter_guest requests an immediate exit,
472 * and the guest shouldn't proceed far enough to
473 * need reinjection.
474 */
475 WARN_ON_ONCE(vcpu->arch.exception.pending);
476 vcpu->arch.exception.injected = true;
477 if (WARN_ON_ONCE(has_payload)) {
478 /*
479 * A reinjected event has already
480 * delivered its payload.
481 */
482 has_payload = false;
483 payload = 0;
484 }
485 } else {
486 vcpu->arch.exception.pending = true;
487 vcpu->arch.exception.injected = false;
488 }
489 vcpu->arch.exception.has_error_code = has_error;
490 vcpu->arch.exception.nr = nr;
491 vcpu->arch.exception.error_code = error_code;
492 vcpu->arch.exception.has_payload = has_payload;
493 vcpu->arch.exception.payload = payload;
494 /*
495 * In guest mode, payload delivery should be deferred,
496 * so that the L1 hypervisor can intercept #PF before
497 * CR2 is modified (or intercept #DB before DR6 is
498 * modified under nVMX). However, for ABI
499 * compatibility with KVM_GET_VCPU_EVENTS and
500 * KVM_SET_VCPU_EVENTS, we can't delay payload
501 * delivery unless userspace has enabled this
502 * functionality via the per-VM capability,
503 * KVM_CAP_EXCEPTION_PAYLOAD.
504 */
505 if (!vcpu->kvm->arch.exception_payload_enabled ||
506 !is_guest_mode(vcpu))
507 kvm_deliver_exception_payload(vcpu);
508 return;
509 }
510
511 /* to check exception */
512 prev_nr = vcpu->arch.exception.nr;
513 if (prev_nr == DF_VECTOR) {
514 /* triple fault -> shutdown */
515 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
516 return;
517 }
518 class1 = exception_class(prev_nr);
519 class2 = exception_class(nr);
520 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
521 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
522 /*
523 * Generate double fault per SDM Table 5-5. Set
524 * exception.pending = true so that the double fault
525 * can trigger a nested vmexit.
526 */
527 vcpu->arch.exception.pending = true;
528 vcpu->arch.exception.injected = false;
529 vcpu->arch.exception.has_error_code = true;
530 vcpu->arch.exception.nr = DF_VECTOR;
531 vcpu->arch.exception.error_code = 0;
532 vcpu->arch.exception.has_payload = false;
533 vcpu->arch.exception.payload = 0;
534 } else
535 /* replace previous exception with a new one in a hope
536 that instruction re-execution will regenerate lost
537 exception */
538 goto queue;
539 }
540
541 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
542 {
543 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
544 }
545 EXPORT_SYMBOL_GPL(kvm_queue_exception);
546
547 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
548 {
549 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
550 }
551 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
552
553 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
554 unsigned long payload)
555 {
556 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
557 }
558
559 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
560 u32 error_code, unsigned long payload)
561 {
562 kvm_multiple_exception(vcpu, nr, true, error_code,
563 true, payload, false);
564 }
565
566 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
567 {
568 if (err)
569 kvm_inject_gp(vcpu, 0);
570 else
571 return kvm_skip_emulated_instruction(vcpu);
572
573 return 1;
574 }
575 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
576
577 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
578 {
579 ++vcpu->stat.pf_guest;
580 vcpu->arch.exception.nested_apf =
581 is_guest_mode(vcpu) && fault->async_page_fault;
582 if (vcpu->arch.exception.nested_apf) {
583 vcpu->arch.apf.nested_apf_token = fault->address;
584 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
585 } else {
586 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
587 fault->address);
588 }
589 }
590 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
591
592 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
593 {
594 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
595 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
596 else
597 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
598
599 return fault->nested_page_fault;
600 }
601
602 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
603 {
604 atomic_inc(&vcpu->arch.nmi_queued);
605 kvm_make_request(KVM_REQ_NMI, vcpu);
606 }
607 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
608
609 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
610 {
611 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
612 }
613 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
614
615 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
616 {
617 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
618 }
619 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
620
621 /*
622 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
623 * a #GP and return false.
624 */
625 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
626 {
627 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
628 return true;
629 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
630 return false;
631 }
632 EXPORT_SYMBOL_GPL(kvm_require_cpl);
633
634 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
635 {
636 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
637 return true;
638
639 kvm_queue_exception(vcpu, UD_VECTOR);
640 return false;
641 }
642 EXPORT_SYMBOL_GPL(kvm_require_dr);
643
644 /*
645 * This function will be used to read from the physical memory of the currently
646 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
647 * can read from guest physical or from the guest's guest physical memory.
648 */
649 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
650 gfn_t ngfn, void *data, int offset, int len,
651 u32 access)
652 {
653 struct x86_exception exception;
654 gfn_t real_gfn;
655 gpa_t ngpa;
656
657 ngpa = gfn_to_gpa(ngfn);
658 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
659 if (real_gfn == UNMAPPED_GVA)
660 return -EFAULT;
661
662 real_gfn = gpa_to_gfn(real_gfn);
663
664 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
665 }
666 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
667
668 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
669 void *data, int offset, int len, u32 access)
670 {
671 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
672 data, offset, len, access);
673 }
674
675 /*
676 * Load the pae pdptrs. Return true is they are all valid.
677 */
678 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
679 {
680 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
681 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
682 int i;
683 int ret;
684 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
685
686 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
687 offset * sizeof(u64), sizeof(pdpte),
688 PFERR_USER_MASK|PFERR_WRITE_MASK);
689 if (ret < 0) {
690 ret = 0;
691 goto out;
692 }
693 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
694 if ((pdpte[i] & PT_PRESENT_MASK) &&
695 (pdpte[i] &
696 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
697 ret = 0;
698 goto out;
699 }
700 }
701 ret = 1;
702
703 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
704 __set_bit(VCPU_EXREG_PDPTR,
705 (unsigned long *)&vcpu->arch.regs_avail);
706 __set_bit(VCPU_EXREG_PDPTR,
707 (unsigned long *)&vcpu->arch.regs_dirty);
708 out:
709
710 return ret;
711 }
712 EXPORT_SYMBOL_GPL(load_pdptrs);
713
714 bool pdptrs_changed(struct kvm_vcpu *vcpu)
715 {
716 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
717 bool changed = true;
718 int offset;
719 gfn_t gfn;
720 int r;
721
722 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
723 return false;
724
725 if (!test_bit(VCPU_EXREG_PDPTR,
726 (unsigned long *)&vcpu->arch.regs_avail))
727 return true;
728
729 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
730 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
731 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
732 PFERR_USER_MASK | PFERR_WRITE_MASK);
733 if (r < 0)
734 goto out;
735 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
736 out:
737
738 return changed;
739 }
740 EXPORT_SYMBOL_GPL(pdptrs_changed);
741
742 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
743 {
744 unsigned long old_cr0 = kvm_read_cr0(vcpu);
745 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
746
747 cr0 |= X86_CR0_ET;
748
749 #ifdef CONFIG_X86_64
750 if (cr0 & 0xffffffff00000000UL)
751 return 1;
752 #endif
753
754 cr0 &= ~CR0_RESERVED_BITS;
755
756 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
757 return 1;
758
759 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
760 return 1;
761
762 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
763 #ifdef CONFIG_X86_64
764 if ((vcpu->arch.efer & EFER_LME)) {
765 int cs_db, cs_l;
766
767 if (!is_pae(vcpu))
768 return 1;
769 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
770 if (cs_l)
771 return 1;
772 } else
773 #endif
774 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 kvm_read_cr3(vcpu)))
776 return 1;
777 }
778
779 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
780 return 1;
781
782 kvm_x86_ops->set_cr0(vcpu, cr0);
783
784 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
785 kvm_clear_async_pf_completion_queue(vcpu);
786 kvm_async_pf_hash_reset(vcpu);
787 }
788
789 if ((cr0 ^ old_cr0) & update_bits)
790 kvm_mmu_reset_context(vcpu);
791
792 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
793 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
794 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
795 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
796
797 return 0;
798 }
799 EXPORT_SYMBOL_GPL(kvm_set_cr0);
800
801 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
802 {
803 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
804 }
805 EXPORT_SYMBOL_GPL(kvm_lmsw);
806
807 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
808 {
809 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
810 !vcpu->guest_xcr0_loaded) {
811 /* kvm_set_xcr() also depends on this */
812 if (vcpu->arch.xcr0 != host_xcr0)
813 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
814 vcpu->guest_xcr0_loaded = 1;
815 }
816 }
817 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
818
819 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
820 {
821 if (vcpu->guest_xcr0_loaded) {
822 if (vcpu->arch.xcr0 != host_xcr0)
823 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
824 vcpu->guest_xcr0_loaded = 0;
825 }
826 }
827 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
828
829 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
830 {
831 u64 xcr0 = xcr;
832 u64 old_xcr0 = vcpu->arch.xcr0;
833 u64 valid_bits;
834
835 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
836 if (index != XCR_XFEATURE_ENABLED_MASK)
837 return 1;
838 if (!(xcr0 & XFEATURE_MASK_FP))
839 return 1;
840 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
841 return 1;
842
843 /*
844 * Do not allow the guest to set bits that we do not support
845 * saving. However, xcr0 bit 0 is always set, even if the
846 * emulated CPU does not support XSAVE (see fx_init).
847 */
848 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
849 if (xcr0 & ~valid_bits)
850 return 1;
851
852 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
853 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
854 return 1;
855
856 if (xcr0 & XFEATURE_MASK_AVX512) {
857 if (!(xcr0 & XFEATURE_MASK_YMM))
858 return 1;
859 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
860 return 1;
861 }
862 vcpu->arch.xcr0 = xcr0;
863
864 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
865 kvm_update_cpuid(vcpu);
866 return 0;
867 }
868
869 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
870 {
871 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
872 __kvm_set_xcr(vcpu, index, xcr)) {
873 kvm_inject_gp(vcpu, 0);
874 return 1;
875 }
876 return 0;
877 }
878 EXPORT_SYMBOL_GPL(kvm_set_xcr);
879
880 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
881 {
882 unsigned long old_cr4 = kvm_read_cr4(vcpu);
883 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
884 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
885
886 if (cr4 & CR4_RESERVED_BITS)
887 return 1;
888
889 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
890 return 1;
891
892 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
893 return 1;
894
895 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
896 return 1;
897
898 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
899 return 1;
900
901 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
902 return 1;
903
904 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
905 return 1;
906
907 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
908 return 1;
909
910 if (is_long_mode(vcpu)) {
911 if (!(cr4 & X86_CR4_PAE))
912 return 1;
913 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
914 && ((cr4 ^ old_cr4) & pdptr_bits)
915 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
916 kvm_read_cr3(vcpu)))
917 return 1;
918
919 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
920 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
921 return 1;
922
923 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
924 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
925 return 1;
926 }
927
928 if (kvm_x86_ops->set_cr4(vcpu, cr4))
929 return 1;
930
931 if (((cr4 ^ old_cr4) & pdptr_bits) ||
932 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
933 kvm_mmu_reset_context(vcpu);
934
935 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
936 kvm_update_cpuid(vcpu);
937
938 return 0;
939 }
940 EXPORT_SYMBOL_GPL(kvm_set_cr4);
941
942 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
943 {
944 bool skip_tlb_flush = false;
945 #ifdef CONFIG_X86_64
946 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
947
948 if (pcid_enabled) {
949 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
950 cr3 &= ~X86_CR3_PCID_NOFLUSH;
951 }
952 #endif
953
954 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
955 if (!skip_tlb_flush) {
956 kvm_mmu_sync_roots(vcpu);
957 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
958 }
959 return 0;
960 }
961
962 if (is_long_mode(vcpu) &&
963 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
964 return 1;
965 else if (is_pae(vcpu) && is_paging(vcpu) &&
966 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
967 return 1;
968
969 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
970 vcpu->arch.cr3 = cr3;
971 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
972
973 return 0;
974 }
975 EXPORT_SYMBOL_GPL(kvm_set_cr3);
976
977 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
978 {
979 if (cr8 & CR8_RESERVED_BITS)
980 return 1;
981 if (lapic_in_kernel(vcpu))
982 kvm_lapic_set_tpr(vcpu, cr8);
983 else
984 vcpu->arch.cr8 = cr8;
985 return 0;
986 }
987 EXPORT_SYMBOL_GPL(kvm_set_cr8);
988
989 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
990 {
991 if (lapic_in_kernel(vcpu))
992 return kvm_lapic_get_cr8(vcpu);
993 else
994 return vcpu->arch.cr8;
995 }
996 EXPORT_SYMBOL_GPL(kvm_get_cr8);
997
998 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
999 {
1000 int i;
1001
1002 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1003 for (i = 0; i < KVM_NR_DB_REGS; i++)
1004 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1005 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1006 }
1007 }
1008
1009 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1010 {
1011 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1012 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1013 }
1014
1015 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1016 {
1017 unsigned long dr7;
1018
1019 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1020 dr7 = vcpu->arch.guest_debug_dr7;
1021 else
1022 dr7 = vcpu->arch.dr7;
1023 kvm_x86_ops->set_dr7(vcpu, dr7);
1024 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1025 if (dr7 & DR7_BP_EN_MASK)
1026 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1027 }
1028
1029 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1030 {
1031 u64 fixed = DR6_FIXED_1;
1032
1033 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1034 fixed |= DR6_RTM;
1035 return fixed;
1036 }
1037
1038 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1039 {
1040 switch (dr) {
1041 case 0 ... 3:
1042 vcpu->arch.db[dr] = val;
1043 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1044 vcpu->arch.eff_db[dr] = val;
1045 break;
1046 case 4:
1047 /* fall through */
1048 case 6:
1049 if (val & 0xffffffff00000000ULL)
1050 return -1; /* #GP */
1051 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1052 kvm_update_dr6(vcpu);
1053 break;
1054 case 5:
1055 /* fall through */
1056 default: /* 7 */
1057 if (val & 0xffffffff00000000ULL)
1058 return -1; /* #GP */
1059 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1060 kvm_update_dr7(vcpu);
1061 break;
1062 }
1063
1064 return 0;
1065 }
1066
1067 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1068 {
1069 if (__kvm_set_dr(vcpu, dr, val)) {
1070 kvm_inject_gp(vcpu, 0);
1071 return 1;
1072 }
1073 return 0;
1074 }
1075 EXPORT_SYMBOL_GPL(kvm_set_dr);
1076
1077 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1078 {
1079 switch (dr) {
1080 case 0 ... 3:
1081 *val = vcpu->arch.db[dr];
1082 break;
1083 case 4:
1084 /* fall through */
1085 case 6:
1086 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1087 *val = vcpu->arch.dr6;
1088 else
1089 *val = kvm_x86_ops->get_dr6(vcpu);
1090 break;
1091 case 5:
1092 /* fall through */
1093 default: /* 7 */
1094 *val = vcpu->arch.dr7;
1095 break;
1096 }
1097 return 0;
1098 }
1099 EXPORT_SYMBOL_GPL(kvm_get_dr);
1100
1101 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1102 {
1103 u32 ecx = kvm_rcx_read(vcpu);
1104 u64 data;
1105 int err;
1106
1107 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1108 if (err)
1109 return err;
1110 kvm_rax_write(vcpu, (u32)data);
1111 kvm_rdx_write(vcpu, data >> 32);
1112 return err;
1113 }
1114 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1115
1116 /*
1117 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1118 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1119 *
1120 * This list is modified at module load time to reflect the
1121 * capabilities of the host cpu. This capabilities test skips MSRs that are
1122 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1123 * may depend on host virtualization features rather than host cpu features.
1124 */
1125
1126 static u32 msrs_to_save[] = {
1127 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1128 MSR_STAR,
1129 #ifdef CONFIG_X86_64
1130 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1131 #endif
1132 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1133 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1134 MSR_IA32_SPEC_CTRL,
1135 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1136 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1137 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1138 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1139 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1140 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1141 };
1142
1143 static unsigned num_msrs_to_save;
1144
1145 static u32 emulated_msrs[] = {
1146 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1147 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1148 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1149 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1150 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1151 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1152 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1153 HV_X64_MSR_RESET,
1154 HV_X64_MSR_VP_INDEX,
1155 HV_X64_MSR_VP_RUNTIME,
1156 HV_X64_MSR_SCONTROL,
1157 HV_X64_MSR_STIMER0_CONFIG,
1158 HV_X64_MSR_VP_ASSIST_PAGE,
1159 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1160 HV_X64_MSR_TSC_EMULATION_STATUS,
1161
1162 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1163 MSR_KVM_PV_EOI_EN,
1164
1165 MSR_IA32_TSC_ADJUST,
1166 MSR_IA32_TSCDEADLINE,
1167 MSR_IA32_ARCH_CAPABILITIES,
1168 MSR_IA32_MISC_ENABLE,
1169 MSR_IA32_MCG_STATUS,
1170 MSR_IA32_MCG_CTL,
1171 MSR_IA32_MCG_EXT_CTL,
1172 MSR_IA32_SMBASE,
1173 MSR_SMI_COUNT,
1174 MSR_PLATFORM_INFO,
1175 MSR_MISC_FEATURES_ENABLES,
1176 MSR_AMD64_VIRT_SPEC_CTRL,
1177 MSR_IA32_POWER_CTL,
1178
1179 MSR_K7_HWCR,
1180 };
1181
1182 static unsigned num_emulated_msrs;
1183
1184 /*
1185 * List of msr numbers which are used to expose MSR-based features that
1186 * can be used by a hypervisor to validate requested CPU features.
1187 */
1188 static u32 msr_based_features[] = {
1189 MSR_IA32_VMX_BASIC,
1190 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1191 MSR_IA32_VMX_PINBASED_CTLS,
1192 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1193 MSR_IA32_VMX_PROCBASED_CTLS,
1194 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1195 MSR_IA32_VMX_EXIT_CTLS,
1196 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1197 MSR_IA32_VMX_ENTRY_CTLS,
1198 MSR_IA32_VMX_MISC,
1199 MSR_IA32_VMX_CR0_FIXED0,
1200 MSR_IA32_VMX_CR0_FIXED1,
1201 MSR_IA32_VMX_CR4_FIXED0,
1202 MSR_IA32_VMX_CR4_FIXED1,
1203 MSR_IA32_VMX_VMCS_ENUM,
1204 MSR_IA32_VMX_PROCBASED_CTLS2,
1205 MSR_IA32_VMX_EPT_VPID_CAP,
1206 MSR_IA32_VMX_VMFUNC,
1207
1208 MSR_F10H_DECFG,
1209 MSR_IA32_UCODE_REV,
1210 MSR_IA32_ARCH_CAPABILITIES,
1211 };
1212
1213 static unsigned int num_msr_based_features;
1214
1215 u64 kvm_get_arch_capabilities(void)
1216 {
1217 u64 data;
1218
1219 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1220
1221 /*
1222 * If we're doing cache flushes (either "always" or "cond")
1223 * we will do one whenever the guest does a vmlaunch/vmresume.
1224 * If an outer hypervisor is doing the cache flush for us
1225 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1226 * capability to the guest too, and if EPT is disabled we're not
1227 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1228 * require a nested hypervisor to do a flush of its own.
1229 */
1230 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1231 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1232
1233 return data;
1234 }
1235 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1236
1237 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1238 {
1239 switch (msr->index) {
1240 case MSR_IA32_ARCH_CAPABILITIES:
1241 msr->data = kvm_get_arch_capabilities();
1242 break;
1243 case MSR_IA32_UCODE_REV:
1244 rdmsrl_safe(msr->index, &msr->data);
1245 break;
1246 default:
1247 if (kvm_x86_ops->get_msr_feature(msr))
1248 return 1;
1249 }
1250 return 0;
1251 }
1252
1253 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1254 {
1255 struct kvm_msr_entry msr;
1256 int r;
1257
1258 msr.index = index;
1259 r = kvm_get_msr_feature(&msr);
1260 if (r)
1261 return r;
1262
1263 *data = msr.data;
1264
1265 return 0;
1266 }
1267
1268 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1269 {
1270 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1271 return false;
1272
1273 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1274 return false;
1275
1276 if (efer & (EFER_LME | EFER_LMA) &&
1277 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1278 return false;
1279
1280 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1281 return false;
1282
1283 return true;
1284
1285 }
1286 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1287 {
1288 if (efer & efer_reserved_bits)
1289 return false;
1290
1291 return __kvm_valid_efer(vcpu, efer);
1292 }
1293 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1294
1295 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1296 {
1297 u64 old_efer = vcpu->arch.efer;
1298 u64 efer = msr_info->data;
1299
1300 if (efer & efer_reserved_bits)
1301 return 1;
1302
1303 if (!msr_info->host_initiated) {
1304 if (!__kvm_valid_efer(vcpu, efer))
1305 return 1;
1306
1307 if (is_paging(vcpu) &&
1308 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1309 return 1;
1310 }
1311
1312 efer &= ~EFER_LMA;
1313 efer |= vcpu->arch.efer & EFER_LMA;
1314
1315 kvm_x86_ops->set_efer(vcpu, efer);
1316
1317 /* Update reserved bits */
1318 if ((efer ^ old_efer) & EFER_NX)
1319 kvm_mmu_reset_context(vcpu);
1320
1321 return 0;
1322 }
1323
1324 void kvm_enable_efer_bits(u64 mask)
1325 {
1326 efer_reserved_bits &= ~mask;
1327 }
1328 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1329
1330 /*
1331 * Writes msr value into into the appropriate "register".
1332 * Returns 0 on success, non-0 otherwise.
1333 * Assumes vcpu_load() was already called.
1334 */
1335 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1336 {
1337 switch (msr->index) {
1338 case MSR_FS_BASE:
1339 case MSR_GS_BASE:
1340 case MSR_KERNEL_GS_BASE:
1341 case MSR_CSTAR:
1342 case MSR_LSTAR:
1343 if (is_noncanonical_address(msr->data, vcpu))
1344 return 1;
1345 break;
1346 case MSR_IA32_SYSENTER_EIP:
1347 case MSR_IA32_SYSENTER_ESP:
1348 /*
1349 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1350 * non-canonical address is written on Intel but not on
1351 * AMD (which ignores the top 32-bits, because it does
1352 * not implement 64-bit SYSENTER).
1353 *
1354 * 64-bit code should hence be able to write a non-canonical
1355 * value on AMD. Making the address canonical ensures that
1356 * vmentry does not fail on Intel after writing a non-canonical
1357 * value, and that something deterministic happens if the guest
1358 * invokes 64-bit SYSENTER.
1359 */
1360 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1361 }
1362 return kvm_x86_ops->set_msr(vcpu, msr);
1363 }
1364 EXPORT_SYMBOL_GPL(kvm_set_msr);
1365
1366 /*
1367 * Adapt set_msr() to msr_io()'s calling convention
1368 */
1369 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1370 {
1371 struct msr_data msr;
1372 int r;
1373
1374 msr.index = index;
1375 msr.host_initiated = true;
1376 r = kvm_get_msr(vcpu, &msr);
1377 if (r)
1378 return r;
1379
1380 *data = msr.data;
1381 return 0;
1382 }
1383
1384 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1385 {
1386 struct msr_data msr;
1387
1388 msr.data = *data;
1389 msr.index = index;
1390 msr.host_initiated = true;
1391 return kvm_set_msr(vcpu, &msr);
1392 }
1393
1394 #ifdef CONFIG_X86_64
1395 struct pvclock_gtod_data {
1396 seqcount_t seq;
1397
1398 struct { /* extract of a clocksource struct */
1399 int vclock_mode;
1400 u64 cycle_last;
1401 u64 mask;
1402 u32 mult;
1403 u32 shift;
1404 } clock;
1405
1406 u64 boot_ns;
1407 u64 nsec_base;
1408 u64 wall_time_sec;
1409 };
1410
1411 static struct pvclock_gtod_data pvclock_gtod_data;
1412
1413 static void update_pvclock_gtod(struct timekeeper *tk)
1414 {
1415 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1416 u64 boot_ns;
1417
1418 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1419
1420 write_seqcount_begin(&vdata->seq);
1421
1422 /* copy pvclock gtod data */
1423 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1424 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1425 vdata->clock.mask = tk->tkr_mono.mask;
1426 vdata->clock.mult = tk->tkr_mono.mult;
1427 vdata->clock.shift = tk->tkr_mono.shift;
1428
1429 vdata->boot_ns = boot_ns;
1430 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1431
1432 vdata->wall_time_sec = tk->xtime_sec;
1433
1434 write_seqcount_end(&vdata->seq);
1435 }
1436 #endif
1437
1438 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1439 {
1440 /*
1441 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1442 * vcpu_enter_guest. This function is only called from
1443 * the physical CPU that is running vcpu.
1444 */
1445 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1446 }
1447
1448 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1449 {
1450 int version;
1451 int r;
1452 struct pvclock_wall_clock wc;
1453 struct timespec64 boot;
1454
1455 if (!wall_clock)
1456 return;
1457
1458 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1459 if (r)
1460 return;
1461
1462 if (version & 1)
1463 ++version; /* first time write, random junk */
1464
1465 ++version;
1466
1467 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1468 return;
1469
1470 /*
1471 * The guest calculates current wall clock time by adding
1472 * system time (updated by kvm_guest_time_update below) to the
1473 * wall clock specified here. guest system time equals host
1474 * system time for us, thus we must fill in host boot time here.
1475 */
1476 getboottime64(&boot);
1477
1478 if (kvm->arch.kvmclock_offset) {
1479 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1480 boot = timespec64_sub(boot, ts);
1481 }
1482 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1483 wc.nsec = boot.tv_nsec;
1484 wc.version = version;
1485
1486 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1487
1488 version++;
1489 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1490 }
1491
1492 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1493 {
1494 do_shl32_div32(dividend, divisor);
1495 return dividend;
1496 }
1497
1498 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1499 s8 *pshift, u32 *pmultiplier)
1500 {
1501 uint64_t scaled64;
1502 int32_t shift = 0;
1503 uint64_t tps64;
1504 uint32_t tps32;
1505
1506 tps64 = base_hz;
1507 scaled64 = scaled_hz;
1508 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1509 tps64 >>= 1;
1510 shift--;
1511 }
1512
1513 tps32 = (uint32_t)tps64;
1514 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1515 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1516 scaled64 >>= 1;
1517 else
1518 tps32 <<= 1;
1519 shift++;
1520 }
1521
1522 *pshift = shift;
1523 *pmultiplier = div_frac(scaled64, tps32);
1524
1525 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1526 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1527 }
1528
1529 #ifdef CONFIG_X86_64
1530 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1531 #endif
1532
1533 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1534 static unsigned long max_tsc_khz;
1535
1536 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1537 {
1538 u64 v = (u64)khz * (1000000 + ppm);
1539 do_div(v, 1000000);
1540 return v;
1541 }
1542
1543 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1544 {
1545 u64 ratio;
1546
1547 /* Guest TSC same frequency as host TSC? */
1548 if (!scale) {
1549 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1550 return 0;
1551 }
1552
1553 /* TSC scaling supported? */
1554 if (!kvm_has_tsc_control) {
1555 if (user_tsc_khz > tsc_khz) {
1556 vcpu->arch.tsc_catchup = 1;
1557 vcpu->arch.tsc_always_catchup = 1;
1558 return 0;
1559 } else {
1560 WARN(1, "user requested TSC rate below hardware speed\n");
1561 return -1;
1562 }
1563 }
1564
1565 /* TSC scaling required - calculate ratio */
1566 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1567 user_tsc_khz, tsc_khz);
1568
1569 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1570 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1571 user_tsc_khz);
1572 return -1;
1573 }
1574
1575 vcpu->arch.tsc_scaling_ratio = ratio;
1576 return 0;
1577 }
1578
1579 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1580 {
1581 u32 thresh_lo, thresh_hi;
1582 int use_scaling = 0;
1583
1584 /* tsc_khz can be zero if TSC calibration fails */
1585 if (user_tsc_khz == 0) {
1586 /* set tsc_scaling_ratio to a safe value */
1587 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1588 return -1;
1589 }
1590
1591 /* Compute a scale to convert nanoseconds in TSC cycles */
1592 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1593 &vcpu->arch.virtual_tsc_shift,
1594 &vcpu->arch.virtual_tsc_mult);
1595 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1596
1597 /*
1598 * Compute the variation in TSC rate which is acceptable
1599 * within the range of tolerance and decide if the
1600 * rate being applied is within that bounds of the hardware
1601 * rate. If so, no scaling or compensation need be done.
1602 */
1603 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1604 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1605 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1606 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1607 use_scaling = 1;
1608 }
1609 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1610 }
1611
1612 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1613 {
1614 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1615 vcpu->arch.virtual_tsc_mult,
1616 vcpu->arch.virtual_tsc_shift);
1617 tsc += vcpu->arch.this_tsc_write;
1618 return tsc;
1619 }
1620
1621 static inline int gtod_is_based_on_tsc(int mode)
1622 {
1623 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1624 }
1625
1626 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1627 {
1628 #ifdef CONFIG_X86_64
1629 bool vcpus_matched;
1630 struct kvm_arch *ka = &vcpu->kvm->arch;
1631 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1632
1633 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1634 atomic_read(&vcpu->kvm->online_vcpus));
1635
1636 /*
1637 * Once the masterclock is enabled, always perform request in
1638 * order to update it.
1639 *
1640 * In order to enable masterclock, the host clocksource must be TSC
1641 * and the vcpus need to have matched TSCs. When that happens,
1642 * perform request to enable masterclock.
1643 */
1644 if (ka->use_master_clock ||
1645 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1646 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1647
1648 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1649 atomic_read(&vcpu->kvm->online_vcpus),
1650 ka->use_master_clock, gtod->clock.vclock_mode);
1651 #endif
1652 }
1653
1654 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1655 {
1656 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1657 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1658 }
1659
1660 /*
1661 * Multiply tsc by a fixed point number represented by ratio.
1662 *
1663 * The most significant 64-N bits (mult) of ratio represent the
1664 * integral part of the fixed point number; the remaining N bits
1665 * (frac) represent the fractional part, ie. ratio represents a fixed
1666 * point number (mult + frac * 2^(-N)).
1667 *
1668 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1669 */
1670 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1671 {
1672 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1673 }
1674
1675 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1676 {
1677 u64 _tsc = tsc;
1678 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1679
1680 if (ratio != kvm_default_tsc_scaling_ratio)
1681 _tsc = __scale_tsc(ratio, tsc);
1682
1683 return _tsc;
1684 }
1685 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1686
1687 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1688 {
1689 u64 tsc;
1690
1691 tsc = kvm_scale_tsc(vcpu, rdtsc());
1692
1693 return target_tsc - tsc;
1694 }
1695
1696 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1697 {
1698 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1699
1700 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1701 }
1702 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1703
1704 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1705 {
1706 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1707 }
1708
1709 static inline bool kvm_check_tsc_unstable(void)
1710 {
1711 #ifdef CONFIG_X86_64
1712 /*
1713 * TSC is marked unstable when we're running on Hyper-V,
1714 * 'TSC page' clocksource is good.
1715 */
1716 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1717 return false;
1718 #endif
1719 return check_tsc_unstable();
1720 }
1721
1722 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1723 {
1724 struct kvm *kvm = vcpu->kvm;
1725 u64 offset, ns, elapsed;
1726 unsigned long flags;
1727 bool matched;
1728 bool already_matched;
1729 u64 data = msr->data;
1730 bool synchronizing = false;
1731
1732 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1733 offset = kvm_compute_tsc_offset(vcpu, data);
1734 ns = ktime_get_boot_ns();
1735 elapsed = ns - kvm->arch.last_tsc_nsec;
1736
1737 if (vcpu->arch.virtual_tsc_khz) {
1738 if (data == 0 && msr->host_initiated) {
1739 /*
1740 * detection of vcpu initialization -- need to sync
1741 * with other vCPUs. This particularly helps to keep
1742 * kvm_clock stable after CPU hotplug
1743 */
1744 synchronizing = true;
1745 } else {
1746 u64 tsc_exp = kvm->arch.last_tsc_write +
1747 nsec_to_cycles(vcpu, elapsed);
1748 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1749 /*
1750 * Special case: TSC write with a small delta (1 second)
1751 * of virtual cycle time against real time is
1752 * interpreted as an attempt to synchronize the CPU.
1753 */
1754 synchronizing = data < tsc_exp + tsc_hz &&
1755 data + tsc_hz > tsc_exp;
1756 }
1757 }
1758
1759 /*
1760 * For a reliable TSC, we can match TSC offsets, and for an unstable
1761 * TSC, we add elapsed time in this computation. We could let the
1762 * compensation code attempt to catch up if we fall behind, but
1763 * it's better to try to match offsets from the beginning.
1764 */
1765 if (synchronizing &&
1766 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1767 if (!kvm_check_tsc_unstable()) {
1768 offset = kvm->arch.cur_tsc_offset;
1769 pr_debug("kvm: matched tsc offset for %llu\n", data);
1770 } else {
1771 u64 delta = nsec_to_cycles(vcpu, elapsed);
1772 data += delta;
1773 offset = kvm_compute_tsc_offset(vcpu, data);
1774 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1775 }
1776 matched = true;
1777 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1778 } else {
1779 /*
1780 * We split periods of matched TSC writes into generations.
1781 * For each generation, we track the original measured
1782 * nanosecond time, offset, and write, so if TSCs are in
1783 * sync, we can match exact offset, and if not, we can match
1784 * exact software computation in compute_guest_tsc()
1785 *
1786 * These values are tracked in kvm->arch.cur_xxx variables.
1787 */
1788 kvm->arch.cur_tsc_generation++;
1789 kvm->arch.cur_tsc_nsec = ns;
1790 kvm->arch.cur_tsc_write = data;
1791 kvm->arch.cur_tsc_offset = offset;
1792 matched = false;
1793 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1794 kvm->arch.cur_tsc_generation, data);
1795 }
1796
1797 /*
1798 * We also track th most recent recorded KHZ, write and time to
1799 * allow the matching interval to be extended at each write.
1800 */
1801 kvm->arch.last_tsc_nsec = ns;
1802 kvm->arch.last_tsc_write = data;
1803 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1804
1805 vcpu->arch.last_guest_tsc = data;
1806
1807 /* Keep track of which generation this VCPU has synchronized to */
1808 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1809 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1810 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1811
1812 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1813 update_ia32_tsc_adjust_msr(vcpu, offset);
1814
1815 kvm_vcpu_write_tsc_offset(vcpu, offset);
1816 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1817
1818 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1819 if (!matched) {
1820 kvm->arch.nr_vcpus_matched_tsc = 0;
1821 } else if (!already_matched) {
1822 kvm->arch.nr_vcpus_matched_tsc++;
1823 }
1824
1825 kvm_track_tsc_matching(vcpu);
1826 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1827 }
1828
1829 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1830
1831 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1832 s64 adjustment)
1833 {
1834 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1835 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1836 }
1837
1838 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1839 {
1840 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1841 WARN_ON(adjustment < 0);
1842 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1843 adjust_tsc_offset_guest(vcpu, adjustment);
1844 }
1845
1846 #ifdef CONFIG_X86_64
1847
1848 static u64 read_tsc(void)
1849 {
1850 u64 ret = (u64)rdtsc_ordered();
1851 u64 last = pvclock_gtod_data.clock.cycle_last;
1852
1853 if (likely(ret >= last))
1854 return ret;
1855
1856 /*
1857 * GCC likes to generate cmov here, but this branch is extremely
1858 * predictable (it's just a function of time and the likely is
1859 * very likely) and there's a data dependence, so force GCC
1860 * to generate a branch instead. I don't barrier() because
1861 * we don't actually need a barrier, and if this function
1862 * ever gets inlined it will generate worse code.
1863 */
1864 asm volatile ("");
1865 return last;
1866 }
1867
1868 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1869 {
1870 long v;
1871 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1872 u64 tsc_pg_val;
1873
1874 switch (gtod->clock.vclock_mode) {
1875 case VCLOCK_HVCLOCK:
1876 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1877 tsc_timestamp);
1878 if (tsc_pg_val != U64_MAX) {
1879 /* TSC page valid */
1880 *mode = VCLOCK_HVCLOCK;
1881 v = (tsc_pg_val - gtod->clock.cycle_last) &
1882 gtod->clock.mask;
1883 } else {
1884 /* TSC page invalid */
1885 *mode = VCLOCK_NONE;
1886 }
1887 break;
1888 case VCLOCK_TSC:
1889 *mode = VCLOCK_TSC;
1890 *tsc_timestamp = read_tsc();
1891 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1892 gtod->clock.mask;
1893 break;
1894 default:
1895 *mode = VCLOCK_NONE;
1896 }
1897
1898 if (*mode == VCLOCK_NONE)
1899 *tsc_timestamp = v = 0;
1900
1901 return v * gtod->clock.mult;
1902 }
1903
1904 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1905 {
1906 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1907 unsigned long seq;
1908 int mode;
1909 u64 ns;
1910
1911 do {
1912 seq = read_seqcount_begin(&gtod->seq);
1913 ns = gtod->nsec_base;
1914 ns += vgettsc(tsc_timestamp, &mode);
1915 ns >>= gtod->clock.shift;
1916 ns += gtod->boot_ns;
1917 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1918 *t = ns;
1919
1920 return mode;
1921 }
1922
1923 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1924 {
1925 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1926 unsigned long seq;
1927 int mode;
1928 u64 ns;
1929
1930 do {
1931 seq = read_seqcount_begin(&gtod->seq);
1932 ts->tv_sec = gtod->wall_time_sec;
1933 ns = gtod->nsec_base;
1934 ns += vgettsc(tsc_timestamp, &mode);
1935 ns >>= gtod->clock.shift;
1936 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1937
1938 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1939 ts->tv_nsec = ns;
1940
1941 return mode;
1942 }
1943
1944 /* returns true if host is using TSC based clocksource */
1945 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1946 {
1947 /* checked again under seqlock below */
1948 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1949 return false;
1950
1951 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1952 tsc_timestamp));
1953 }
1954
1955 /* returns true if host is using TSC based clocksource */
1956 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1957 u64 *tsc_timestamp)
1958 {
1959 /* checked again under seqlock below */
1960 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1961 return false;
1962
1963 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1964 }
1965 #endif
1966
1967 /*
1968 *
1969 * Assuming a stable TSC across physical CPUS, and a stable TSC
1970 * across virtual CPUs, the following condition is possible.
1971 * Each numbered line represents an event visible to both
1972 * CPUs at the next numbered event.
1973 *
1974 * "timespecX" represents host monotonic time. "tscX" represents
1975 * RDTSC value.
1976 *
1977 * VCPU0 on CPU0 | VCPU1 on CPU1
1978 *
1979 * 1. read timespec0,tsc0
1980 * 2. | timespec1 = timespec0 + N
1981 * | tsc1 = tsc0 + M
1982 * 3. transition to guest | transition to guest
1983 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1984 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1985 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1986 *
1987 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1988 *
1989 * - ret0 < ret1
1990 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1991 * ...
1992 * - 0 < N - M => M < N
1993 *
1994 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1995 * always the case (the difference between two distinct xtime instances
1996 * might be smaller then the difference between corresponding TSC reads,
1997 * when updating guest vcpus pvclock areas).
1998 *
1999 * To avoid that problem, do not allow visibility of distinct
2000 * system_timestamp/tsc_timestamp values simultaneously: use a master
2001 * copy of host monotonic time values. Update that master copy
2002 * in lockstep.
2003 *
2004 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2005 *
2006 */
2007
2008 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2009 {
2010 #ifdef CONFIG_X86_64
2011 struct kvm_arch *ka = &kvm->arch;
2012 int vclock_mode;
2013 bool host_tsc_clocksource, vcpus_matched;
2014
2015 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2016 atomic_read(&kvm->online_vcpus));
2017
2018 /*
2019 * If the host uses TSC clock, then passthrough TSC as stable
2020 * to the guest.
2021 */
2022 host_tsc_clocksource = kvm_get_time_and_clockread(
2023 &ka->master_kernel_ns,
2024 &ka->master_cycle_now);
2025
2026 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2027 && !ka->backwards_tsc_observed
2028 && !ka->boot_vcpu_runs_old_kvmclock;
2029
2030 if (ka->use_master_clock)
2031 atomic_set(&kvm_guest_has_master_clock, 1);
2032
2033 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2034 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2035 vcpus_matched);
2036 #endif
2037 }
2038
2039 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2040 {
2041 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2042 }
2043
2044 static void kvm_gen_update_masterclock(struct kvm *kvm)
2045 {
2046 #ifdef CONFIG_X86_64
2047 int i;
2048 struct kvm_vcpu *vcpu;
2049 struct kvm_arch *ka = &kvm->arch;
2050
2051 spin_lock(&ka->pvclock_gtod_sync_lock);
2052 kvm_make_mclock_inprogress_request(kvm);
2053 /* no guest entries from this point */
2054 pvclock_update_vm_gtod_copy(kvm);
2055
2056 kvm_for_each_vcpu(i, vcpu, kvm)
2057 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2058
2059 /* guest entries allowed */
2060 kvm_for_each_vcpu(i, vcpu, kvm)
2061 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2062
2063 spin_unlock(&ka->pvclock_gtod_sync_lock);
2064 #endif
2065 }
2066
2067 u64 get_kvmclock_ns(struct kvm *kvm)
2068 {
2069 struct kvm_arch *ka = &kvm->arch;
2070 struct pvclock_vcpu_time_info hv_clock;
2071 u64 ret;
2072
2073 spin_lock(&ka->pvclock_gtod_sync_lock);
2074 if (!ka->use_master_clock) {
2075 spin_unlock(&ka->pvclock_gtod_sync_lock);
2076 return ktime_get_boot_ns() + ka->kvmclock_offset;
2077 }
2078
2079 hv_clock.tsc_timestamp = ka->master_cycle_now;
2080 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2081 spin_unlock(&ka->pvclock_gtod_sync_lock);
2082
2083 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2084 get_cpu();
2085
2086 if (__this_cpu_read(cpu_tsc_khz)) {
2087 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2088 &hv_clock.tsc_shift,
2089 &hv_clock.tsc_to_system_mul);
2090 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2091 } else
2092 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
2093
2094 put_cpu();
2095
2096 return ret;
2097 }
2098
2099 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2100 {
2101 struct kvm_vcpu_arch *vcpu = &v->arch;
2102 struct pvclock_vcpu_time_info guest_hv_clock;
2103
2104 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2105 &guest_hv_clock, sizeof(guest_hv_clock))))
2106 return;
2107
2108 /* This VCPU is paused, but it's legal for a guest to read another
2109 * VCPU's kvmclock, so we really have to follow the specification where
2110 * it says that version is odd if data is being modified, and even after
2111 * it is consistent.
2112 *
2113 * Version field updates must be kept separate. This is because
2114 * kvm_write_guest_cached might use a "rep movs" instruction, and
2115 * writes within a string instruction are weakly ordered. So there
2116 * are three writes overall.
2117 *
2118 * As a small optimization, only write the version field in the first
2119 * and third write. The vcpu->pv_time cache is still valid, because the
2120 * version field is the first in the struct.
2121 */
2122 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2123
2124 if (guest_hv_clock.version & 1)
2125 ++guest_hv_clock.version; /* first time write, random junk */
2126
2127 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2128 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2129 &vcpu->hv_clock,
2130 sizeof(vcpu->hv_clock.version));
2131
2132 smp_wmb();
2133
2134 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2135 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2136
2137 if (vcpu->pvclock_set_guest_stopped_request) {
2138 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2139 vcpu->pvclock_set_guest_stopped_request = false;
2140 }
2141
2142 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2143
2144 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2145 &vcpu->hv_clock,
2146 sizeof(vcpu->hv_clock));
2147
2148 smp_wmb();
2149
2150 vcpu->hv_clock.version++;
2151 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2152 &vcpu->hv_clock,
2153 sizeof(vcpu->hv_clock.version));
2154 }
2155
2156 static int kvm_guest_time_update(struct kvm_vcpu *v)
2157 {
2158 unsigned long flags, tgt_tsc_khz;
2159 struct kvm_vcpu_arch *vcpu = &v->arch;
2160 struct kvm_arch *ka = &v->kvm->arch;
2161 s64 kernel_ns;
2162 u64 tsc_timestamp, host_tsc;
2163 u8 pvclock_flags;
2164 bool use_master_clock;
2165
2166 kernel_ns = 0;
2167 host_tsc = 0;
2168
2169 /*
2170 * If the host uses TSC clock, then passthrough TSC as stable
2171 * to the guest.
2172 */
2173 spin_lock(&ka->pvclock_gtod_sync_lock);
2174 use_master_clock = ka->use_master_clock;
2175 if (use_master_clock) {
2176 host_tsc = ka->master_cycle_now;
2177 kernel_ns = ka->master_kernel_ns;
2178 }
2179 spin_unlock(&ka->pvclock_gtod_sync_lock);
2180
2181 /* Keep irq disabled to prevent changes to the clock */
2182 local_irq_save(flags);
2183 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2184 if (unlikely(tgt_tsc_khz == 0)) {
2185 local_irq_restore(flags);
2186 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2187 return 1;
2188 }
2189 if (!use_master_clock) {
2190 host_tsc = rdtsc();
2191 kernel_ns = ktime_get_boot_ns();
2192 }
2193
2194 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2195
2196 /*
2197 * We may have to catch up the TSC to match elapsed wall clock
2198 * time for two reasons, even if kvmclock is used.
2199 * 1) CPU could have been running below the maximum TSC rate
2200 * 2) Broken TSC compensation resets the base at each VCPU
2201 * entry to avoid unknown leaps of TSC even when running
2202 * again on the same CPU. This may cause apparent elapsed
2203 * time to disappear, and the guest to stand still or run
2204 * very slowly.
2205 */
2206 if (vcpu->tsc_catchup) {
2207 u64 tsc = compute_guest_tsc(v, kernel_ns);
2208 if (tsc > tsc_timestamp) {
2209 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2210 tsc_timestamp = tsc;
2211 }
2212 }
2213
2214 local_irq_restore(flags);
2215
2216 /* With all the info we got, fill in the values */
2217
2218 if (kvm_has_tsc_control)
2219 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2220
2221 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2222 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2223 &vcpu->hv_clock.tsc_shift,
2224 &vcpu->hv_clock.tsc_to_system_mul);
2225 vcpu->hw_tsc_khz = tgt_tsc_khz;
2226 }
2227
2228 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2229 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2230 vcpu->last_guest_tsc = tsc_timestamp;
2231
2232 /* If the host uses TSC clocksource, then it is stable */
2233 pvclock_flags = 0;
2234 if (use_master_clock)
2235 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2236
2237 vcpu->hv_clock.flags = pvclock_flags;
2238
2239 if (vcpu->pv_time_enabled)
2240 kvm_setup_pvclock_page(v);
2241 if (v == kvm_get_vcpu(v->kvm, 0))
2242 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2243 return 0;
2244 }
2245
2246 /*
2247 * kvmclock updates which are isolated to a given vcpu, such as
2248 * vcpu->cpu migration, should not allow system_timestamp from
2249 * the rest of the vcpus to remain static. Otherwise ntp frequency
2250 * correction applies to one vcpu's system_timestamp but not
2251 * the others.
2252 *
2253 * So in those cases, request a kvmclock update for all vcpus.
2254 * We need to rate-limit these requests though, as they can
2255 * considerably slow guests that have a large number of vcpus.
2256 * The time for a remote vcpu to update its kvmclock is bound
2257 * by the delay we use to rate-limit the updates.
2258 */
2259
2260 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2261
2262 static void kvmclock_update_fn(struct work_struct *work)
2263 {
2264 int i;
2265 struct delayed_work *dwork = to_delayed_work(work);
2266 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2267 kvmclock_update_work);
2268 struct kvm *kvm = container_of(ka, struct kvm, arch);
2269 struct kvm_vcpu *vcpu;
2270
2271 kvm_for_each_vcpu(i, vcpu, kvm) {
2272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2273 kvm_vcpu_kick(vcpu);
2274 }
2275 }
2276
2277 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2278 {
2279 struct kvm *kvm = v->kvm;
2280
2281 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2282 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2283 KVMCLOCK_UPDATE_DELAY);
2284 }
2285
2286 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2287
2288 static void kvmclock_sync_fn(struct work_struct *work)
2289 {
2290 struct delayed_work *dwork = to_delayed_work(work);
2291 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2292 kvmclock_sync_work);
2293 struct kvm *kvm = container_of(ka, struct kvm, arch);
2294
2295 if (!kvmclock_periodic_sync)
2296 return;
2297
2298 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2299 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2300 KVMCLOCK_SYNC_PERIOD);
2301 }
2302
2303 /*
2304 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2305 */
2306 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2307 {
2308 /* McStatusWrEn enabled? */
2309 if (guest_cpuid_is_amd(vcpu))
2310 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2311
2312 return false;
2313 }
2314
2315 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2316 {
2317 u64 mcg_cap = vcpu->arch.mcg_cap;
2318 unsigned bank_num = mcg_cap & 0xff;
2319 u32 msr = msr_info->index;
2320 u64 data = msr_info->data;
2321
2322 switch (msr) {
2323 case MSR_IA32_MCG_STATUS:
2324 vcpu->arch.mcg_status = data;
2325 break;
2326 case MSR_IA32_MCG_CTL:
2327 if (!(mcg_cap & MCG_CTL_P) &&
2328 (data || !msr_info->host_initiated))
2329 return 1;
2330 if (data != 0 && data != ~(u64)0)
2331 return 1;
2332 vcpu->arch.mcg_ctl = data;
2333 break;
2334 default:
2335 if (msr >= MSR_IA32_MC0_CTL &&
2336 msr < MSR_IA32_MCx_CTL(bank_num)) {
2337 u32 offset = msr - MSR_IA32_MC0_CTL;
2338 /* only 0 or all 1s can be written to IA32_MCi_CTL
2339 * some Linux kernels though clear bit 10 in bank 4 to
2340 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2341 * this to avoid an uncatched #GP in the guest
2342 */
2343 if ((offset & 0x3) == 0 &&
2344 data != 0 && (data | (1 << 10)) != ~(u64)0)
2345 return -1;
2346
2347 /* MCi_STATUS */
2348 if (!msr_info->host_initiated &&
2349 (offset & 0x3) == 1 && data != 0) {
2350 if (!can_set_mci_status(vcpu))
2351 return -1;
2352 }
2353
2354 vcpu->arch.mce_banks[offset] = data;
2355 break;
2356 }
2357 return 1;
2358 }
2359 return 0;
2360 }
2361
2362 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2363 {
2364 struct kvm *kvm = vcpu->kvm;
2365 int lm = is_long_mode(vcpu);
2366 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2367 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2368 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2369 : kvm->arch.xen_hvm_config.blob_size_32;
2370 u32 page_num = data & ~PAGE_MASK;
2371 u64 page_addr = data & PAGE_MASK;
2372 u8 *page;
2373 int r;
2374
2375 r = -E2BIG;
2376 if (page_num >= blob_size)
2377 goto out;
2378 r = -ENOMEM;
2379 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2380 if (IS_ERR(page)) {
2381 r = PTR_ERR(page);
2382 goto out;
2383 }
2384 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2385 goto out_free;
2386 r = 0;
2387 out_free:
2388 kfree(page);
2389 out:
2390 return r;
2391 }
2392
2393 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2394 {
2395 gpa_t gpa = data & ~0x3f;
2396
2397 /* Bits 3:5 are reserved, Should be zero */
2398 if (data & 0x38)
2399 return 1;
2400
2401 vcpu->arch.apf.msr_val = data;
2402
2403 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2404 kvm_clear_async_pf_completion_queue(vcpu);
2405 kvm_async_pf_hash_reset(vcpu);
2406 return 0;
2407 }
2408
2409 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2410 sizeof(u32)))
2411 return 1;
2412
2413 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2414 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2415 kvm_async_pf_wakeup_all(vcpu);
2416 return 0;
2417 }
2418
2419 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2420 {
2421 vcpu->arch.pv_time_enabled = false;
2422 }
2423
2424 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2425 {
2426 ++vcpu->stat.tlb_flush;
2427 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2428 }
2429
2430 static void record_steal_time(struct kvm_vcpu *vcpu)
2431 {
2432 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2433 return;
2434
2435 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2436 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2437 return;
2438
2439 /*
2440 * Doing a TLB flush here, on the guest's behalf, can avoid
2441 * expensive IPIs.
2442 */
2443 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2444 kvm_vcpu_flush_tlb(vcpu, false);
2445
2446 if (vcpu->arch.st.steal.version & 1)
2447 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2448
2449 vcpu->arch.st.steal.version += 1;
2450
2451 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2452 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2453
2454 smp_wmb();
2455
2456 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2457 vcpu->arch.st.last_steal;
2458 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2459
2460 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2461 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2462
2463 smp_wmb();
2464
2465 vcpu->arch.st.steal.version += 1;
2466
2467 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2468 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2469 }
2470
2471 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2472 {
2473 bool pr = false;
2474 u32 msr = msr_info->index;
2475 u64 data = msr_info->data;
2476
2477 switch (msr) {
2478 case MSR_AMD64_NB_CFG:
2479 case MSR_IA32_UCODE_WRITE:
2480 case MSR_VM_HSAVE_PA:
2481 case MSR_AMD64_PATCH_LOADER:
2482 case MSR_AMD64_BU_CFG2:
2483 case MSR_AMD64_DC_CFG:
2484 case MSR_F15H_EX_CFG:
2485 break;
2486
2487 case MSR_IA32_UCODE_REV:
2488 if (msr_info->host_initiated)
2489 vcpu->arch.microcode_version = data;
2490 break;
2491 case MSR_IA32_ARCH_CAPABILITIES:
2492 if (!msr_info->host_initiated)
2493 return 1;
2494 vcpu->arch.arch_capabilities = data;
2495 break;
2496 case MSR_EFER:
2497 return set_efer(vcpu, msr_info);
2498 case MSR_K7_HWCR:
2499 data &= ~(u64)0x40; /* ignore flush filter disable */
2500 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2501 data &= ~(u64)0x8; /* ignore TLB cache disable */
2502
2503 /* Handle McStatusWrEn */
2504 if (data == BIT_ULL(18)) {
2505 vcpu->arch.msr_hwcr = data;
2506 } else if (data != 0) {
2507 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2508 data);
2509 return 1;
2510 }
2511 break;
2512 case MSR_FAM10H_MMIO_CONF_BASE:
2513 if (data != 0) {
2514 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2515 "0x%llx\n", data);
2516 return 1;
2517 }
2518 break;
2519 case MSR_IA32_DEBUGCTLMSR:
2520 if (!data) {
2521 /* We support the non-activated case already */
2522 break;
2523 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2524 /* Values other than LBR and BTF are vendor-specific,
2525 thus reserved and should throw a #GP */
2526 return 1;
2527 }
2528 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2529 __func__, data);
2530 break;
2531 case 0x200 ... 0x2ff:
2532 return kvm_mtrr_set_msr(vcpu, msr, data);
2533 case MSR_IA32_APICBASE:
2534 return kvm_set_apic_base(vcpu, msr_info);
2535 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2536 return kvm_x2apic_msr_write(vcpu, msr, data);
2537 case MSR_IA32_TSCDEADLINE:
2538 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2539 break;
2540 case MSR_IA32_TSC_ADJUST:
2541 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2542 if (!msr_info->host_initiated) {
2543 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2544 adjust_tsc_offset_guest(vcpu, adj);
2545 }
2546 vcpu->arch.ia32_tsc_adjust_msr = data;
2547 }
2548 break;
2549 case MSR_IA32_MISC_ENABLE:
2550 vcpu->arch.ia32_misc_enable_msr = data;
2551 break;
2552 case MSR_IA32_SMBASE:
2553 if (!msr_info->host_initiated)
2554 return 1;
2555 vcpu->arch.smbase = data;
2556 break;
2557 case MSR_IA32_TSC:
2558 kvm_write_tsc(vcpu, msr_info);
2559 break;
2560 case MSR_SMI_COUNT:
2561 if (!msr_info->host_initiated)
2562 return 1;
2563 vcpu->arch.smi_count = data;
2564 break;
2565 case MSR_KVM_WALL_CLOCK_NEW:
2566 case MSR_KVM_WALL_CLOCK:
2567 vcpu->kvm->arch.wall_clock = data;
2568 kvm_write_wall_clock(vcpu->kvm, data);
2569 break;
2570 case MSR_KVM_SYSTEM_TIME_NEW:
2571 case MSR_KVM_SYSTEM_TIME: {
2572 struct kvm_arch *ka = &vcpu->kvm->arch;
2573
2574 kvmclock_reset(vcpu);
2575
2576 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2577 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2578
2579 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2580 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2581
2582 ka->boot_vcpu_runs_old_kvmclock = tmp;
2583 }
2584
2585 vcpu->arch.time = data;
2586 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2587
2588 /* we verify if the enable bit is set... */
2589 if (!(data & 1))
2590 break;
2591
2592 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2593 &vcpu->arch.pv_time, data & ~1ULL,
2594 sizeof(struct pvclock_vcpu_time_info)))
2595 vcpu->arch.pv_time_enabled = false;
2596 else
2597 vcpu->arch.pv_time_enabled = true;
2598
2599 break;
2600 }
2601 case MSR_KVM_ASYNC_PF_EN:
2602 if (kvm_pv_enable_async_pf(vcpu, data))
2603 return 1;
2604 break;
2605 case MSR_KVM_STEAL_TIME:
2606
2607 if (unlikely(!sched_info_on()))
2608 return 1;
2609
2610 if (data & KVM_STEAL_RESERVED_MASK)
2611 return 1;
2612
2613 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2614 data & KVM_STEAL_VALID_BITS,
2615 sizeof(struct kvm_steal_time)))
2616 return 1;
2617
2618 vcpu->arch.st.msr_val = data;
2619
2620 if (!(data & KVM_MSR_ENABLED))
2621 break;
2622
2623 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2624
2625 break;
2626 case MSR_KVM_PV_EOI_EN:
2627 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2628 return 1;
2629 break;
2630
2631 case MSR_IA32_MCG_CTL:
2632 case MSR_IA32_MCG_STATUS:
2633 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2634 return set_msr_mce(vcpu, msr_info);
2635
2636 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2637 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2638 pr = true; /* fall through */
2639 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2640 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2641 if (kvm_pmu_is_valid_msr(vcpu, msr))
2642 return kvm_pmu_set_msr(vcpu, msr_info);
2643
2644 if (pr || data != 0)
2645 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2646 "0x%x data 0x%llx\n", msr, data);
2647 break;
2648 case MSR_K7_CLK_CTL:
2649 /*
2650 * Ignore all writes to this no longer documented MSR.
2651 * Writes are only relevant for old K7 processors,
2652 * all pre-dating SVM, but a recommended workaround from
2653 * AMD for these chips. It is possible to specify the
2654 * affected processor models on the command line, hence
2655 * the need to ignore the workaround.
2656 */
2657 break;
2658 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2659 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2660 case HV_X64_MSR_CRASH_CTL:
2661 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2662 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2663 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2664 case HV_X64_MSR_TSC_EMULATION_STATUS:
2665 return kvm_hv_set_msr_common(vcpu, msr, data,
2666 msr_info->host_initiated);
2667 case MSR_IA32_BBL_CR_CTL3:
2668 /* Drop writes to this legacy MSR -- see rdmsr
2669 * counterpart for further detail.
2670 */
2671 if (report_ignored_msrs)
2672 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2673 msr, data);
2674 break;
2675 case MSR_AMD64_OSVW_ID_LENGTH:
2676 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2677 return 1;
2678 vcpu->arch.osvw.length = data;
2679 break;
2680 case MSR_AMD64_OSVW_STATUS:
2681 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2682 return 1;
2683 vcpu->arch.osvw.status = data;
2684 break;
2685 case MSR_PLATFORM_INFO:
2686 if (!msr_info->host_initiated ||
2687 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2688 cpuid_fault_enabled(vcpu)))
2689 return 1;
2690 vcpu->arch.msr_platform_info = data;
2691 break;
2692 case MSR_MISC_FEATURES_ENABLES:
2693 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2694 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2695 !supports_cpuid_fault(vcpu)))
2696 return 1;
2697 vcpu->arch.msr_misc_features_enables = data;
2698 break;
2699 default:
2700 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2701 return xen_hvm_config(vcpu, data);
2702 if (kvm_pmu_is_valid_msr(vcpu, msr))
2703 return kvm_pmu_set_msr(vcpu, msr_info);
2704 if (!ignore_msrs) {
2705 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2706 msr, data);
2707 return 1;
2708 } else {
2709 if (report_ignored_msrs)
2710 vcpu_unimpl(vcpu,
2711 "ignored wrmsr: 0x%x data 0x%llx\n",
2712 msr, data);
2713 break;
2714 }
2715 }
2716 return 0;
2717 }
2718 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2719
2720
2721 /*
2722 * Reads an msr value (of 'msr_index') into 'pdata'.
2723 * Returns 0 on success, non-0 otherwise.
2724 * Assumes vcpu_load() was already called.
2725 */
2726 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2727 {
2728 return kvm_x86_ops->get_msr(vcpu, msr);
2729 }
2730 EXPORT_SYMBOL_GPL(kvm_get_msr);
2731
2732 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2733 {
2734 u64 data;
2735 u64 mcg_cap = vcpu->arch.mcg_cap;
2736 unsigned bank_num = mcg_cap & 0xff;
2737
2738 switch (msr) {
2739 case MSR_IA32_P5_MC_ADDR:
2740 case MSR_IA32_P5_MC_TYPE:
2741 data = 0;
2742 break;
2743 case MSR_IA32_MCG_CAP:
2744 data = vcpu->arch.mcg_cap;
2745 break;
2746 case MSR_IA32_MCG_CTL:
2747 if (!(mcg_cap & MCG_CTL_P) && !host)
2748 return 1;
2749 data = vcpu->arch.mcg_ctl;
2750 break;
2751 case MSR_IA32_MCG_STATUS:
2752 data = vcpu->arch.mcg_status;
2753 break;
2754 default:
2755 if (msr >= MSR_IA32_MC0_CTL &&
2756 msr < MSR_IA32_MCx_CTL(bank_num)) {
2757 u32 offset = msr - MSR_IA32_MC0_CTL;
2758 data = vcpu->arch.mce_banks[offset];
2759 break;
2760 }
2761 return 1;
2762 }
2763 *pdata = data;
2764 return 0;
2765 }
2766
2767 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2768 {
2769 switch (msr_info->index) {
2770 case MSR_IA32_PLATFORM_ID:
2771 case MSR_IA32_EBL_CR_POWERON:
2772 case MSR_IA32_DEBUGCTLMSR:
2773 case MSR_IA32_LASTBRANCHFROMIP:
2774 case MSR_IA32_LASTBRANCHTOIP:
2775 case MSR_IA32_LASTINTFROMIP:
2776 case MSR_IA32_LASTINTTOIP:
2777 case MSR_K8_SYSCFG:
2778 case MSR_K8_TSEG_ADDR:
2779 case MSR_K8_TSEG_MASK:
2780 case MSR_VM_HSAVE_PA:
2781 case MSR_K8_INT_PENDING_MSG:
2782 case MSR_AMD64_NB_CFG:
2783 case MSR_FAM10H_MMIO_CONF_BASE:
2784 case MSR_AMD64_BU_CFG2:
2785 case MSR_IA32_PERF_CTL:
2786 case MSR_AMD64_DC_CFG:
2787 case MSR_F15H_EX_CFG:
2788 msr_info->data = 0;
2789 break;
2790 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2791 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2792 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2793 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2794 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2795 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2796 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2797 msr_info->data = 0;
2798 break;
2799 case MSR_IA32_UCODE_REV:
2800 msr_info->data = vcpu->arch.microcode_version;
2801 break;
2802 case MSR_IA32_ARCH_CAPABILITIES:
2803 if (!msr_info->host_initiated &&
2804 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2805 return 1;
2806 msr_info->data = vcpu->arch.arch_capabilities;
2807 break;
2808 case MSR_IA32_TSC:
2809 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2810 break;
2811 case MSR_MTRRcap:
2812 case 0x200 ... 0x2ff:
2813 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2814 case 0xcd: /* fsb frequency */
2815 msr_info->data = 3;
2816 break;
2817 /*
2818 * MSR_EBC_FREQUENCY_ID
2819 * Conservative value valid for even the basic CPU models.
2820 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2821 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2822 * and 266MHz for model 3, or 4. Set Core Clock
2823 * Frequency to System Bus Frequency Ratio to 1 (bits
2824 * 31:24) even though these are only valid for CPU
2825 * models > 2, however guests may end up dividing or
2826 * multiplying by zero otherwise.
2827 */
2828 case MSR_EBC_FREQUENCY_ID:
2829 msr_info->data = 1 << 24;
2830 break;
2831 case MSR_IA32_APICBASE:
2832 msr_info->data = kvm_get_apic_base(vcpu);
2833 break;
2834 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2835 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2836 break;
2837 case MSR_IA32_TSCDEADLINE:
2838 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2839 break;
2840 case MSR_IA32_TSC_ADJUST:
2841 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2842 break;
2843 case MSR_IA32_MISC_ENABLE:
2844 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2845 break;
2846 case MSR_IA32_SMBASE:
2847 if (!msr_info->host_initiated)
2848 return 1;
2849 msr_info->data = vcpu->arch.smbase;
2850 break;
2851 case MSR_SMI_COUNT:
2852 msr_info->data = vcpu->arch.smi_count;
2853 break;
2854 case MSR_IA32_PERF_STATUS:
2855 /* TSC increment by tick */
2856 msr_info->data = 1000ULL;
2857 /* CPU multiplier */
2858 msr_info->data |= (((uint64_t)4ULL) << 40);
2859 break;
2860 case MSR_EFER:
2861 msr_info->data = vcpu->arch.efer;
2862 break;
2863 case MSR_KVM_WALL_CLOCK:
2864 case MSR_KVM_WALL_CLOCK_NEW:
2865 msr_info->data = vcpu->kvm->arch.wall_clock;
2866 break;
2867 case MSR_KVM_SYSTEM_TIME:
2868 case MSR_KVM_SYSTEM_TIME_NEW:
2869 msr_info->data = vcpu->arch.time;
2870 break;
2871 case MSR_KVM_ASYNC_PF_EN:
2872 msr_info->data = vcpu->arch.apf.msr_val;
2873 break;
2874 case MSR_KVM_STEAL_TIME:
2875 msr_info->data = vcpu->arch.st.msr_val;
2876 break;
2877 case MSR_KVM_PV_EOI_EN:
2878 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2879 break;
2880 case MSR_IA32_P5_MC_ADDR:
2881 case MSR_IA32_P5_MC_TYPE:
2882 case MSR_IA32_MCG_CAP:
2883 case MSR_IA32_MCG_CTL:
2884 case MSR_IA32_MCG_STATUS:
2885 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2886 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2887 msr_info->host_initiated);
2888 case MSR_K7_CLK_CTL:
2889 /*
2890 * Provide expected ramp-up count for K7. All other
2891 * are set to zero, indicating minimum divisors for
2892 * every field.
2893 *
2894 * This prevents guest kernels on AMD host with CPU
2895 * type 6, model 8 and higher from exploding due to
2896 * the rdmsr failing.
2897 */
2898 msr_info->data = 0x20000000;
2899 break;
2900 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2901 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2902 case HV_X64_MSR_CRASH_CTL:
2903 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2904 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2905 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2906 case HV_X64_MSR_TSC_EMULATION_STATUS:
2907 return kvm_hv_get_msr_common(vcpu,
2908 msr_info->index, &msr_info->data,
2909 msr_info->host_initiated);
2910 break;
2911 case MSR_IA32_BBL_CR_CTL3:
2912 /* This legacy MSR exists but isn't fully documented in current
2913 * silicon. It is however accessed by winxp in very narrow
2914 * scenarios where it sets bit #19, itself documented as
2915 * a "reserved" bit. Best effort attempt to source coherent
2916 * read data here should the balance of the register be
2917 * interpreted by the guest:
2918 *
2919 * L2 cache control register 3: 64GB range, 256KB size,
2920 * enabled, latency 0x1, configured
2921 */
2922 msr_info->data = 0xbe702111;
2923 break;
2924 case MSR_AMD64_OSVW_ID_LENGTH:
2925 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2926 return 1;
2927 msr_info->data = vcpu->arch.osvw.length;
2928 break;
2929 case MSR_AMD64_OSVW_STATUS:
2930 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2931 return 1;
2932 msr_info->data = vcpu->arch.osvw.status;
2933 break;
2934 case MSR_PLATFORM_INFO:
2935 if (!msr_info->host_initiated &&
2936 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2937 return 1;
2938 msr_info->data = vcpu->arch.msr_platform_info;
2939 break;
2940 case MSR_MISC_FEATURES_ENABLES:
2941 msr_info->data = vcpu->arch.msr_misc_features_enables;
2942 break;
2943 case MSR_K7_HWCR:
2944 msr_info->data = vcpu->arch.msr_hwcr;
2945 break;
2946 default:
2947 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2948 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2949 if (!ignore_msrs) {
2950 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2951 msr_info->index);
2952 return 1;
2953 } else {
2954 if (report_ignored_msrs)
2955 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2956 msr_info->index);
2957 msr_info->data = 0;
2958 }
2959 break;
2960 }
2961 return 0;
2962 }
2963 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2964
2965 /*
2966 * Read or write a bunch of msrs. All parameters are kernel addresses.
2967 *
2968 * @return number of msrs set successfully.
2969 */
2970 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2971 struct kvm_msr_entry *entries,
2972 int (*do_msr)(struct kvm_vcpu *vcpu,
2973 unsigned index, u64 *data))
2974 {
2975 int i;
2976
2977 for (i = 0; i < msrs->nmsrs; ++i)
2978 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2979 break;
2980
2981 return i;
2982 }
2983
2984 /*
2985 * Read or write a bunch of msrs. Parameters are user addresses.
2986 *
2987 * @return number of msrs set successfully.
2988 */
2989 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2990 int (*do_msr)(struct kvm_vcpu *vcpu,
2991 unsigned index, u64 *data),
2992 int writeback)
2993 {
2994 struct kvm_msrs msrs;
2995 struct kvm_msr_entry *entries;
2996 int r, n;
2997 unsigned size;
2998
2999 r = -EFAULT;
3000 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3001 goto out;
3002
3003 r = -E2BIG;
3004 if (msrs.nmsrs >= MAX_IO_MSRS)
3005 goto out;
3006
3007 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3008 entries = memdup_user(user_msrs->entries, size);
3009 if (IS_ERR(entries)) {
3010 r = PTR_ERR(entries);
3011 goto out;
3012 }
3013
3014 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3015 if (r < 0)
3016 goto out_free;
3017
3018 r = -EFAULT;
3019 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3020 goto out_free;
3021
3022 r = n;
3023
3024 out_free:
3025 kfree(entries);
3026 out:
3027 return r;
3028 }
3029
3030 static inline bool kvm_can_mwait_in_guest(void)
3031 {
3032 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3033 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3034 boot_cpu_has(X86_FEATURE_ARAT);
3035 }
3036
3037 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3038 {
3039 int r = 0;
3040
3041 switch (ext) {
3042 case KVM_CAP_IRQCHIP:
3043 case KVM_CAP_HLT:
3044 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3045 case KVM_CAP_SET_TSS_ADDR:
3046 case KVM_CAP_EXT_CPUID:
3047 case KVM_CAP_EXT_EMUL_CPUID:
3048 case KVM_CAP_CLOCKSOURCE:
3049 case KVM_CAP_PIT:
3050 case KVM_CAP_NOP_IO_DELAY:
3051 case KVM_CAP_MP_STATE:
3052 case KVM_CAP_SYNC_MMU:
3053 case KVM_CAP_USER_NMI:
3054 case KVM_CAP_REINJECT_CONTROL:
3055 case KVM_CAP_IRQ_INJECT_STATUS:
3056 case KVM_CAP_IOEVENTFD:
3057 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3058 case KVM_CAP_PIT2:
3059 case KVM_CAP_PIT_STATE2:
3060 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3061 case KVM_CAP_XEN_HVM:
3062 case KVM_CAP_VCPU_EVENTS:
3063 case KVM_CAP_HYPERV:
3064 case KVM_CAP_HYPERV_VAPIC:
3065 case KVM_CAP_HYPERV_SPIN:
3066 case KVM_CAP_HYPERV_SYNIC:
3067 case KVM_CAP_HYPERV_SYNIC2:
3068 case KVM_CAP_HYPERV_VP_INDEX:
3069 case KVM_CAP_HYPERV_EVENTFD:
3070 case KVM_CAP_HYPERV_TLBFLUSH:
3071 case KVM_CAP_HYPERV_SEND_IPI:
3072 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3073 case KVM_CAP_HYPERV_CPUID:
3074 case KVM_CAP_PCI_SEGMENT:
3075 case KVM_CAP_DEBUGREGS:
3076 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3077 case KVM_CAP_XSAVE:
3078 case KVM_CAP_ASYNC_PF:
3079 case KVM_CAP_GET_TSC_KHZ:
3080 case KVM_CAP_KVMCLOCK_CTRL:
3081 case KVM_CAP_READONLY_MEM:
3082 case KVM_CAP_HYPERV_TIME:
3083 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3084 case KVM_CAP_TSC_DEADLINE_TIMER:
3085 case KVM_CAP_DISABLE_QUIRKS:
3086 case KVM_CAP_SET_BOOT_CPU_ID:
3087 case KVM_CAP_SPLIT_IRQCHIP:
3088 case KVM_CAP_IMMEDIATE_EXIT:
3089 case KVM_CAP_GET_MSR_FEATURES:
3090 case KVM_CAP_MSR_PLATFORM_INFO:
3091 case KVM_CAP_EXCEPTION_PAYLOAD:
3092 r = 1;
3093 break;
3094 case KVM_CAP_SYNC_REGS:
3095 r = KVM_SYNC_X86_VALID_FIELDS;
3096 break;
3097 case KVM_CAP_ADJUST_CLOCK:
3098 r = KVM_CLOCK_TSC_STABLE;
3099 break;
3100 case KVM_CAP_X86_DISABLE_EXITS:
3101 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
3102 if(kvm_can_mwait_in_guest())
3103 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3104 break;
3105 case KVM_CAP_X86_SMM:
3106 /* SMBASE is usually relocated above 1M on modern chipsets,
3107 * and SMM handlers might indeed rely on 4G segment limits,
3108 * so do not report SMM to be available if real mode is
3109 * emulated via vm86 mode. Still, do not go to great lengths
3110 * to avoid userspace's usage of the feature, because it is a
3111 * fringe case that is not enabled except via specific settings
3112 * of the module parameters.
3113 */
3114 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3115 break;
3116 case KVM_CAP_VAPIC:
3117 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3118 break;
3119 case KVM_CAP_NR_VCPUS:
3120 r = KVM_SOFT_MAX_VCPUS;
3121 break;
3122 case KVM_CAP_MAX_VCPUS:
3123 r = KVM_MAX_VCPUS;
3124 break;
3125 case KVM_CAP_MAX_VCPU_ID:
3126 r = KVM_MAX_VCPU_ID;
3127 break;
3128 case KVM_CAP_PV_MMU: /* obsolete */
3129 r = 0;
3130 break;
3131 case KVM_CAP_MCE:
3132 r = KVM_MAX_MCE_BANKS;
3133 break;
3134 case KVM_CAP_XCRS:
3135 r = boot_cpu_has(X86_FEATURE_XSAVE);
3136 break;
3137 case KVM_CAP_TSC_CONTROL:
3138 r = kvm_has_tsc_control;
3139 break;
3140 case KVM_CAP_X2APIC_API:
3141 r = KVM_X2APIC_API_VALID_FLAGS;
3142 break;
3143 case KVM_CAP_NESTED_STATE:
3144 r = kvm_x86_ops->get_nested_state ?
3145 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3146 break;
3147 default:
3148 break;
3149 }
3150 return r;
3151
3152 }
3153
3154 long kvm_arch_dev_ioctl(struct file *filp,
3155 unsigned int ioctl, unsigned long arg)
3156 {
3157 void __user *argp = (void __user *)arg;
3158 long r;
3159
3160 switch (ioctl) {
3161 case KVM_GET_MSR_INDEX_LIST: {
3162 struct kvm_msr_list __user *user_msr_list = argp;
3163 struct kvm_msr_list msr_list;
3164 unsigned n;
3165
3166 r = -EFAULT;
3167 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3168 goto out;
3169 n = msr_list.nmsrs;
3170 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3171 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3172 goto out;
3173 r = -E2BIG;
3174 if (n < msr_list.nmsrs)
3175 goto out;
3176 r = -EFAULT;
3177 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3178 num_msrs_to_save * sizeof(u32)))
3179 goto out;
3180 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3181 &emulated_msrs,
3182 num_emulated_msrs * sizeof(u32)))
3183 goto out;
3184 r = 0;
3185 break;
3186 }
3187 case KVM_GET_SUPPORTED_CPUID:
3188 case KVM_GET_EMULATED_CPUID: {
3189 struct kvm_cpuid2 __user *cpuid_arg = argp;
3190 struct kvm_cpuid2 cpuid;
3191
3192 r = -EFAULT;
3193 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3194 goto out;
3195
3196 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3197 ioctl);
3198 if (r)
3199 goto out;
3200
3201 r = -EFAULT;
3202 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3203 goto out;
3204 r = 0;
3205 break;
3206 }
3207 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3208 r = -EFAULT;
3209 if (copy_to_user(argp, &kvm_mce_cap_supported,
3210 sizeof(kvm_mce_cap_supported)))
3211 goto out;
3212 r = 0;
3213 break;
3214 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3215 struct kvm_msr_list __user *user_msr_list = argp;
3216 struct kvm_msr_list msr_list;
3217 unsigned int n;
3218
3219 r = -EFAULT;
3220 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3221 goto out;
3222 n = msr_list.nmsrs;
3223 msr_list.nmsrs = num_msr_based_features;
3224 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3225 goto out;
3226 r = -E2BIG;
3227 if (n < msr_list.nmsrs)
3228 goto out;
3229 r = -EFAULT;
3230 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3231 num_msr_based_features * sizeof(u32)))
3232 goto out;
3233 r = 0;
3234 break;
3235 }
3236 case KVM_GET_MSRS:
3237 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3238 break;
3239 }
3240 default:
3241 r = -EINVAL;
3242 }
3243 out:
3244 return r;
3245 }
3246
3247 static void wbinvd_ipi(void *garbage)
3248 {
3249 wbinvd();
3250 }
3251
3252 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3253 {
3254 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3255 }
3256
3257 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3258 {
3259 /* Address WBINVD may be executed by guest */
3260 if (need_emulate_wbinvd(vcpu)) {
3261 if (kvm_x86_ops->has_wbinvd_exit())
3262 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3263 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3264 smp_call_function_single(vcpu->cpu,
3265 wbinvd_ipi, NULL, 1);
3266 }
3267
3268 kvm_x86_ops->vcpu_load(vcpu, cpu);
3269
3270 /* Apply any externally detected TSC adjustments (due to suspend) */
3271 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3272 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3273 vcpu->arch.tsc_offset_adjustment = 0;
3274 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3275 }
3276
3277 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3278 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3279 rdtsc() - vcpu->arch.last_host_tsc;
3280 if (tsc_delta < 0)
3281 mark_tsc_unstable("KVM discovered backwards TSC");
3282
3283 if (kvm_check_tsc_unstable()) {
3284 u64 offset = kvm_compute_tsc_offset(vcpu,
3285 vcpu->arch.last_guest_tsc);
3286 kvm_vcpu_write_tsc_offset(vcpu, offset);
3287 vcpu->arch.tsc_catchup = 1;
3288 }
3289
3290 if (kvm_lapic_hv_timer_in_use(vcpu))
3291 kvm_lapic_restart_hv_timer(vcpu);
3292
3293 /*
3294 * On a host with synchronized TSC, there is no need to update
3295 * kvmclock on vcpu->cpu migration
3296 */
3297 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3298 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3299 if (vcpu->cpu != cpu)
3300 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3301 vcpu->cpu = cpu;
3302 }
3303
3304 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3305 }
3306
3307 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3308 {
3309 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3310 return;
3311
3312 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3313
3314 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3315 &vcpu->arch.st.steal.preempted,
3316 offsetof(struct kvm_steal_time, preempted),
3317 sizeof(vcpu->arch.st.steal.preempted));
3318 }
3319
3320 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3321 {
3322 int idx;
3323
3324 if (vcpu->preempted)
3325 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3326
3327 /*
3328 * Disable page faults because we're in atomic context here.
3329 * kvm_write_guest_offset_cached() would call might_fault()
3330 * that relies on pagefault_disable() to tell if there's a
3331 * bug. NOTE: the write to guest memory may not go through if
3332 * during postcopy live migration or if there's heavy guest
3333 * paging.
3334 */
3335 pagefault_disable();
3336 /*
3337 * kvm_memslots() will be called by
3338 * kvm_write_guest_offset_cached() so take the srcu lock.
3339 */
3340 idx = srcu_read_lock(&vcpu->kvm->srcu);
3341 kvm_steal_time_set_preempted(vcpu);
3342 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3343 pagefault_enable();
3344 kvm_x86_ops->vcpu_put(vcpu);
3345 vcpu->arch.last_host_tsc = rdtsc();
3346 /*
3347 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3348 * on every vmexit, but if not, we might have a stale dr6 from the
3349 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3350 */
3351 set_debugreg(0, 6);
3352 }
3353
3354 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3355 struct kvm_lapic_state *s)
3356 {
3357 if (vcpu->arch.apicv_active)
3358 kvm_x86_ops->sync_pir_to_irr(vcpu);
3359
3360 return kvm_apic_get_state(vcpu, s);
3361 }
3362
3363 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3364 struct kvm_lapic_state *s)
3365 {
3366 int r;
3367
3368 r = kvm_apic_set_state(vcpu, s);
3369 if (r)
3370 return r;
3371 update_cr8_intercept(vcpu);
3372
3373 return 0;
3374 }
3375
3376 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3377 {
3378 return (!lapic_in_kernel(vcpu) ||
3379 kvm_apic_accept_pic_intr(vcpu));
3380 }
3381
3382 /*
3383 * if userspace requested an interrupt window, check that the
3384 * interrupt window is open.
3385 *
3386 * No need to exit to userspace if we already have an interrupt queued.
3387 */
3388 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3389 {
3390 return kvm_arch_interrupt_allowed(vcpu) &&
3391 !kvm_cpu_has_interrupt(vcpu) &&
3392 !kvm_event_needs_reinjection(vcpu) &&
3393 kvm_cpu_accept_dm_intr(vcpu);
3394 }
3395
3396 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3397 struct kvm_interrupt *irq)
3398 {
3399 if (irq->irq >= KVM_NR_INTERRUPTS)
3400 return -EINVAL;
3401
3402 if (!irqchip_in_kernel(vcpu->kvm)) {
3403 kvm_queue_interrupt(vcpu, irq->irq, false);
3404 kvm_make_request(KVM_REQ_EVENT, vcpu);
3405 return 0;
3406 }
3407
3408 /*
3409 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3410 * fail for in-kernel 8259.
3411 */
3412 if (pic_in_kernel(vcpu->kvm))
3413 return -ENXIO;
3414
3415 if (vcpu->arch.pending_external_vector != -1)
3416 return -EEXIST;
3417
3418 vcpu->arch.pending_external_vector = irq->irq;
3419 kvm_make_request(KVM_REQ_EVENT, vcpu);
3420 return 0;
3421 }
3422
3423 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3424 {
3425 kvm_inject_nmi(vcpu);
3426
3427 return 0;
3428 }
3429
3430 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3431 {
3432 kvm_make_request(KVM_REQ_SMI, vcpu);
3433
3434 return 0;
3435 }
3436
3437 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3438 struct kvm_tpr_access_ctl *tac)
3439 {
3440 if (tac->flags)
3441 return -EINVAL;
3442 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3443 return 0;
3444 }
3445
3446 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3447 u64 mcg_cap)
3448 {
3449 int r;
3450 unsigned bank_num = mcg_cap & 0xff, bank;
3451
3452 r = -EINVAL;
3453 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3454 goto out;
3455 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3456 goto out;
3457 r = 0;
3458 vcpu->arch.mcg_cap = mcg_cap;
3459 /* Init IA32_MCG_CTL to all 1s */
3460 if (mcg_cap & MCG_CTL_P)
3461 vcpu->arch.mcg_ctl = ~(u64)0;
3462 /* Init IA32_MCi_CTL to all 1s */
3463 for (bank = 0; bank < bank_num; bank++)
3464 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3465
3466 if (kvm_x86_ops->setup_mce)
3467 kvm_x86_ops->setup_mce(vcpu);
3468 out:
3469 return r;
3470 }
3471
3472 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3473 struct kvm_x86_mce *mce)
3474 {
3475 u64 mcg_cap = vcpu->arch.mcg_cap;
3476 unsigned bank_num = mcg_cap & 0xff;
3477 u64 *banks = vcpu->arch.mce_banks;
3478
3479 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3480 return -EINVAL;
3481 /*
3482 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3483 * reporting is disabled
3484 */
3485 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3486 vcpu->arch.mcg_ctl != ~(u64)0)
3487 return 0;
3488 banks += 4 * mce->bank;
3489 /*
3490 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3491 * reporting is disabled for the bank
3492 */
3493 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3494 return 0;
3495 if (mce->status & MCI_STATUS_UC) {
3496 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3497 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3498 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3499 return 0;
3500 }
3501 if (banks[1] & MCI_STATUS_VAL)
3502 mce->status |= MCI_STATUS_OVER;
3503 banks[2] = mce->addr;
3504 banks[3] = mce->misc;
3505 vcpu->arch.mcg_status = mce->mcg_status;
3506 banks[1] = mce->status;
3507 kvm_queue_exception(vcpu, MC_VECTOR);
3508 } else if (!(banks[1] & MCI_STATUS_VAL)
3509 || !(banks[1] & MCI_STATUS_UC)) {
3510 if (banks[1] & MCI_STATUS_VAL)
3511 mce->status |= MCI_STATUS_OVER;
3512 banks[2] = mce->addr;
3513 banks[3] = mce->misc;
3514 banks[1] = mce->status;
3515 } else
3516 banks[1] |= MCI_STATUS_OVER;
3517 return 0;
3518 }
3519
3520 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3521 struct kvm_vcpu_events *events)
3522 {
3523 process_nmi(vcpu);
3524
3525 /*
3526 * The API doesn't provide the instruction length for software
3527 * exceptions, so don't report them. As long as the guest RIP
3528 * isn't advanced, we should expect to encounter the exception
3529 * again.
3530 */
3531 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3532 events->exception.injected = 0;
3533 events->exception.pending = 0;
3534 } else {
3535 events->exception.injected = vcpu->arch.exception.injected;
3536 events->exception.pending = vcpu->arch.exception.pending;
3537 /*
3538 * For ABI compatibility, deliberately conflate
3539 * pending and injected exceptions when
3540 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3541 */
3542 if (!vcpu->kvm->arch.exception_payload_enabled)
3543 events->exception.injected |=
3544 vcpu->arch.exception.pending;
3545 }
3546 events->exception.nr = vcpu->arch.exception.nr;
3547 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3548 events->exception.error_code = vcpu->arch.exception.error_code;
3549 events->exception_has_payload = vcpu->arch.exception.has_payload;
3550 events->exception_payload = vcpu->arch.exception.payload;
3551
3552 events->interrupt.injected =
3553 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3554 events->interrupt.nr = vcpu->arch.interrupt.nr;
3555 events->interrupt.soft = 0;
3556 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3557
3558 events->nmi.injected = vcpu->arch.nmi_injected;
3559 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3560 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3561 events->nmi.pad = 0;
3562
3563 events->sipi_vector = 0; /* never valid when reporting to user space */
3564
3565 events->smi.smm = is_smm(vcpu);
3566 events->smi.pending = vcpu->arch.smi_pending;
3567 events->smi.smm_inside_nmi =
3568 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3569 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3570
3571 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3572 | KVM_VCPUEVENT_VALID_SHADOW
3573 | KVM_VCPUEVENT_VALID_SMM);
3574 if (vcpu->kvm->arch.exception_payload_enabled)
3575 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3576
3577 memset(&events->reserved, 0, sizeof(events->reserved));
3578 }
3579
3580 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3581
3582 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3583 struct kvm_vcpu_events *events)
3584 {
3585 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3586 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3587 | KVM_VCPUEVENT_VALID_SHADOW
3588 | KVM_VCPUEVENT_VALID_SMM
3589 | KVM_VCPUEVENT_VALID_PAYLOAD))
3590 return -EINVAL;
3591
3592 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3593 if (!vcpu->kvm->arch.exception_payload_enabled)
3594 return -EINVAL;
3595 if (events->exception.pending)
3596 events->exception.injected = 0;
3597 else
3598 events->exception_has_payload = 0;
3599 } else {
3600 events->exception.pending = 0;
3601 events->exception_has_payload = 0;
3602 }
3603
3604 if ((events->exception.injected || events->exception.pending) &&
3605 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3606 return -EINVAL;
3607
3608 /* INITs are latched while in SMM */
3609 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3610 (events->smi.smm || events->smi.pending) &&
3611 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3612 return -EINVAL;
3613
3614 process_nmi(vcpu);
3615 vcpu->arch.exception.injected = events->exception.injected;
3616 vcpu->arch.exception.pending = events->exception.pending;
3617 vcpu->arch.exception.nr = events->exception.nr;
3618 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3619 vcpu->arch.exception.error_code = events->exception.error_code;
3620 vcpu->arch.exception.has_payload = events->exception_has_payload;
3621 vcpu->arch.exception.payload = events->exception_payload;
3622
3623 vcpu->arch.interrupt.injected = events->interrupt.injected;
3624 vcpu->arch.interrupt.nr = events->interrupt.nr;
3625 vcpu->arch.interrupt.soft = events->interrupt.soft;
3626 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3627 kvm_x86_ops->set_interrupt_shadow(vcpu,
3628 events->interrupt.shadow);
3629
3630 vcpu->arch.nmi_injected = events->nmi.injected;
3631 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3632 vcpu->arch.nmi_pending = events->nmi.pending;
3633 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3634
3635 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3636 lapic_in_kernel(vcpu))
3637 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3638
3639 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3640 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3641 if (events->smi.smm)
3642 vcpu->arch.hflags |= HF_SMM_MASK;
3643 else
3644 vcpu->arch.hflags &= ~HF_SMM_MASK;
3645 kvm_smm_changed(vcpu);
3646 }
3647
3648 vcpu->arch.smi_pending = events->smi.pending;
3649
3650 if (events->smi.smm) {
3651 if (events->smi.smm_inside_nmi)
3652 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3653 else
3654 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3655 if (lapic_in_kernel(vcpu)) {
3656 if (events->smi.latched_init)
3657 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3658 else
3659 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3660 }
3661 }
3662 }
3663
3664 kvm_make_request(KVM_REQ_EVENT, vcpu);
3665
3666 return 0;
3667 }
3668
3669 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3670 struct kvm_debugregs *dbgregs)
3671 {
3672 unsigned long val;
3673
3674 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3675 kvm_get_dr(vcpu, 6, &val);
3676 dbgregs->dr6 = val;
3677 dbgregs->dr7 = vcpu->arch.dr7;
3678 dbgregs->flags = 0;
3679 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3680 }
3681
3682 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3683 struct kvm_debugregs *dbgregs)
3684 {
3685 if (dbgregs->flags)
3686 return -EINVAL;
3687
3688 if (dbgregs->dr6 & ~0xffffffffull)
3689 return -EINVAL;
3690 if (dbgregs->dr7 & ~0xffffffffull)
3691 return -EINVAL;
3692
3693 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3694 kvm_update_dr0123(vcpu);
3695 vcpu->arch.dr6 = dbgregs->dr6;
3696 kvm_update_dr6(vcpu);
3697 vcpu->arch.dr7 = dbgregs->dr7;
3698 kvm_update_dr7(vcpu);
3699
3700 return 0;
3701 }
3702
3703 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3704
3705 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3706 {
3707 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3708 u64 xstate_bv = xsave->header.xfeatures;
3709 u64 valid;
3710
3711 /*
3712 * Copy legacy XSAVE area, to avoid complications with CPUID
3713 * leaves 0 and 1 in the loop below.
3714 */
3715 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3716
3717 /* Set XSTATE_BV */
3718 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3719 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3720
3721 /*
3722 * Copy each region from the possibly compacted offset to the
3723 * non-compacted offset.
3724 */
3725 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3726 while (valid) {
3727 u64 xfeature_mask = valid & -valid;
3728 int xfeature_nr = fls64(xfeature_mask) - 1;
3729 void *src = get_xsave_addr(xsave, xfeature_nr);
3730
3731 if (src) {
3732 u32 size, offset, ecx, edx;
3733 cpuid_count(XSTATE_CPUID, xfeature_nr,
3734 &size, &offset, &ecx, &edx);
3735 if (xfeature_nr == XFEATURE_PKRU)
3736 memcpy(dest + offset, &vcpu->arch.pkru,
3737 sizeof(vcpu->arch.pkru));
3738 else
3739 memcpy(dest + offset, src, size);
3740
3741 }
3742
3743 valid -= xfeature_mask;
3744 }
3745 }
3746
3747 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3748 {
3749 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3750 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3751 u64 valid;
3752
3753 /*
3754 * Copy legacy XSAVE area, to avoid complications with CPUID
3755 * leaves 0 and 1 in the loop below.
3756 */
3757 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3758
3759 /* Set XSTATE_BV and possibly XCOMP_BV. */
3760 xsave->header.xfeatures = xstate_bv;
3761 if (boot_cpu_has(X86_FEATURE_XSAVES))
3762 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3763
3764 /*
3765 * Copy each region from the non-compacted offset to the
3766 * possibly compacted offset.
3767 */
3768 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3769 while (valid) {
3770 u64 xfeature_mask = valid & -valid;
3771 int xfeature_nr = fls64(xfeature_mask) - 1;
3772 void *dest = get_xsave_addr(xsave, xfeature_nr);
3773
3774 if (dest) {
3775 u32 size, offset, ecx, edx;
3776 cpuid_count(XSTATE_CPUID, xfeature_nr,
3777 &size, &offset, &ecx, &edx);
3778 if (xfeature_nr == XFEATURE_PKRU)
3779 memcpy(&vcpu->arch.pkru, src + offset,
3780 sizeof(vcpu->arch.pkru));
3781 else
3782 memcpy(dest, src + offset, size);
3783 }
3784
3785 valid -= xfeature_mask;
3786 }
3787 }
3788
3789 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3790 struct kvm_xsave *guest_xsave)
3791 {
3792 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3793 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3794 fill_xsave((u8 *) guest_xsave->region, vcpu);
3795 } else {
3796 memcpy(guest_xsave->region,
3797 &vcpu->arch.guest_fpu->state.fxsave,
3798 sizeof(struct fxregs_state));
3799 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3800 XFEATURE_MASK_FPSSE;
3801 }
3802 }
3803
3804 #define XSAVE_MXCSR_OFFSET 24
3805
3806 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3807 struct kvm_xsave *guest_xsave)
3808 {
3809 u64 xstate_bv =
3810 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3811 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3812
3813 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3814 /*
3815 * Here we allow setting states that are not present in
3816 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3817 * with old userspace.
3818 */
3819 if (xstate_bv & ~kvm_supported_xcr0() ||
3820 mxcsr & ~mxcsr_feature_mask)
3821 return -EINVAL;
3822 load_xsave(vcpu, (u8 *)guest_xsave->region);
3823 } else {
3824 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3825 mxcsr & ~mxcsr_feature_mask)
3826 return -EINVAL;
3827 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3828 guest_xsave->region, sizeof(struct fxregs_state));
3829 }
3830 return 0;
3831 }
3832
3833 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3834 struct kvm_xcrs *guest_xcrs)
3835 {
3836 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3837 guest_xcrs->nr_xcrs = 0;
3838 return;
3839 }
3840
3841 guest_xcrs->nr_xcrs = 1;
3842 guest_xcrs->flags = 0;
3843 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3844 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3845 }
3846
3847 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3848 struct kvm_xcrs *guest_xcrs)
3849 {
3850 int i, r = 0;
3851
3852 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3853 return -EINVAL;
3854
3855 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3856 return -EINVAL;
3857
3858 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3859 /* Only support XCR0 currently */
3860 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3861 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3862 guest_xcrs->xcrs[i].value);
3863 break;
3864 }
3865 if (r)
3866 r = -EINVAL;
3867 return r;
3868 }
3869
3870 /*
3871 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3872 * stopped by the hypervisor. This function will be called from the host only.
3873 * EINVAL is returned when the host attempts to set the flag for a guest that
3874 * does not support pv clocks.
3875 */
3876 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3877 {
3878 if (!vcpu->arch.pv_time_enabled)
3879 return -EINVAL;
3880 vcpu->arch.pvclock_set_guest_stopped_request = true;
3881 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3882 return 0;
3883 }
3884
3885 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3886 struct kvm_enable_cap *cap)
3887 {
3888 int r;
3889 uint16_t vmcs_version;
3890 void __user *user_ptr;
3891
3892 if (cap->flags)
3893 return -EINVAL;
3894
3895 switch (cap->cap) {
3896 case KVM_CAP_HYPERV_SYNIC2:
3897 if (cap->args[0])
3898 return -EINVAL;
3899 /* fall through */
3900
3901 case KVM_CAP_HYPERV_SYNIC:
3902 if (!irqchip_in_kernel(vcpu->kvm))
3903 return -EINVAL;
3904 return kvm_hv_activate_synic(vcpu, cap->cap ==
3905 KVM_CAP_HYPERV_SYNIC2);
3906 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3907 if (!kvm_x86_ops->nested_enable_evmcs)
3908 return -ENOTTY;
3909 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3910 if (!r) {
3911 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3912 if (copy_to_user(user_ptr, &vmcs_version,
3913 sizeof(vmcs_version)))
3914 r = -EFAULT;
3915 }
3916 return r;
3917
3918 default:
3919 return -EINVAL;
3920 }
3921 }
3922
3923 long kvm_arch_vcpu_ioctl(struct file *filp,
3924 unsigned int ioctl, unsigned long arg)
3925 {
3926 struct kvm_vcpu *vcpu = filp->private_data;
3927 void __user *argp = (void __user *)arg;
3928 int r;
3929 union {
3930 struct kvm_lapic_state *lapic;
3931 struct kvm_xsave *xsave;
3932 struct kvm_xcrs *xcrs;
3933 void *buffer;
3934 } u;
3935
3936 vcpu_load(vcpu);
3937
3938 u.buffer = NULL;
3939 switch (ioctl) {
3940 case KVM_GET_LAPIC: {
3941 r = -EINVAL;
3942 if (!lapic_in_kernel(vcpu))
3943 goto out;
3944 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3945 GFP_KERNEL_ACCOUNT);
3946
3947 r = -ENOMEM;
3948 if (!u.lapic)
3949 goto out;
3950 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3951 if (r)
3952 goto out;
3953 r = -EFAULT;
3954 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3955 goto out;
3956 r = 0;
3957 break;
3958 }
3959 case KVM_SET_LAPIC: {
3960 r = -EINVAL;
3961 if (!lapic_in_kernel(vcpu))
3962 goto out;
3963 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3964 if (IS_ERR(u.lapic)) {
3965 r = PTR_ERR(u.lapic);
3966 goto out_nofree;
3967 }
3968
3969 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3970 break;
3971 }
3972 case KVM_INTERRUPT: {
3973 struct kvm_interrupt irq;
3974
3975 r = -EFAULT;
3976 if (copy_from_user(&irq, argp, sizeof(irq)))
3977 goto out;
3978 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3979 break;
3980 }
3981 case KVM_NMI: {
3982 r = kvm_vcpu_ioctl_nmi(vcpu);
3983 break;
3984 }
3985 case KVM_SMI: {
3986 r = kvm_vcpu_ioctl_smi(vcpu);
3987 break;
3988 }
3989 case KVM_SET_CPUID: {
3990 struct kvm_cpuid __user *cpuid_arg = argp;
3991 struct kvm_cpuid cpuid;
3992
3993 r = -EFAULT;
3994 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3995 goto out;
3996 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3997 break;
3998 }
3999 case KVM_SET_CPUID2: {
4000 struct kvm_cpuid2 __user *cpuid_arg = argp;
4001 struct kvm_cpuid2 cpuid;
4002
4003 r = -EFAULT;
4004 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4005 goto out;
4006 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4007 cpuid_arg->entries);
4008 break;
4009 }
4010 case KVM_GET_CPUID2: {
4011 struct kvm_cpuid2 __user *cpuid_arg = argp;
4012 struct kvm_cpuid2 cpuid;
4013
4014 r = -EFAULT;
4015 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4016 goto out;
4017 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4018 cpuid_arg->entries);
4019 if (r)
4020 goto out;
4021 r = -EFAULT;
4022 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4023 goto out;
4024 r = 0;
4025 break;
4026 }
4027 case KVM_GET_MSRS: {
4028 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4029 r = msr_io(vcpu, argp, do_get_msr, 1);
4030 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4031 break;
4032 }
4033 case KVM_SET_MSRS: {
4034 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4035 r = msr_io(vcpu, argp, do_set_msr, 0);
4036 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4037 break;
4038 }
4039 case KVM_TPR_ACCESS_REPORTING: {
4040 struct kvm_tpr_access_ctl tac;
4041
4042 r = -EFAULT;
4043 if (copy_from_user(&tac, argp, sizeof(tac)))
4044 goto out;
4045 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4046 if (r)
4047 goto out;
4048 r = -EFAULT;
4049 if (copy_to_user(argp, &tac, sizeof(tac)))
4050 goto out;
4051 r = 0;
4052 break;
4053 };
4054 case KVM_SET_VAPIC_ADDR: {
4055 struct kvm_vapic_addr va;
4056 int idx;
4057
4058 r = -EINVAL;
4059 if (!lapic_in_kernel(vcpu))
4060 goto out;
4061 r = -EFAULT;
4062 if (copy_from_user(&va, argp, sizeof(va)))
4063 goto out;
4064 idx = srcu_read_lock(&vcpu->kvm->srcu);
4065 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4066 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4067 break;
4068 }
4069 case KVM_X86_SETUP_MCE: {
4070 u64 mcg_cap;
4071
4072 r = -EFAULT;
4073 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4074 goto out;
4075 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4076 break;
4077 }
4078 case KVM_X86_SET_MCE: {
4079 struct kvm_x86_mce mce;
4080
4081 r = -EFAULT;
4082 if (copy_from_user(&mce, argp, sizeof(mce)))
4083 goto out;
4084 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4085 break;
4086 }
4087 case KVM_GET_VCPU_EVENTS: {
4088 struct kvm_vcpu_events events;
4089
4090 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4091
4092 r = -EFAULT;
4093 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4094 break;
4095 r = 0;
4096 break;
4097 }
4098 case KVM_SET_VCPU_EVENTS: {
4099 struct kvm_vcpu_events events;
4100
4101 r = -EFAULT;
4102 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4103 break;
4104
4105 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4106 break;
4107 }
4108 case KVM_GET_DEBUGREGS: {
4109 struct kvm_debugregs dbgregs;
4110
4111 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4112
4113 r = -EFAULT;
4114 if (copy_to_user(argp, &dbgregs,
4115 sizeof(struct kvm_debugregs)))
4116 break;
4117 r = 0;
4118 break;
4119 }
4120 case KVM_SET_DEBUGREGS: {
4121 struct kvm_debugregs dbgregs;
4122
4123 r = -EFAULT;
4124 if (copy_from_user(&dbgregs, argp,
4125 sizeof(struct kvm_debugregs)))
4126 break;
4127
4128 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4129 break;
4130 }
4131 case KVM_GET_XSAVE: {
4132 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4133 r = -ENOMEM;
4134 if (!u.xsave)
4135 break;
4136
4137 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4138
4139 r = -EFAULT;
4140 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4141 break;
4142 r = 0;
4143 break;
4144 }
4145 case KVM_SET_XSAVE: {
4146 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4147 if (IS_ERR(u.xsave)) {
4148 r = PTR_ERR(u.xsave);
4149 goto out_nofree;
4150 }
4151
4152 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4153 break;
4154 }
4155 case KVM_GET_XCRS: {
4156 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4157 r = -ENOMEM;
4158 if (!u.xcrs)
4159 break;
4160
4161 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4162
4163 r = -EFAULT;
4164 if (copy_to_user(argp, u.xcrs,
4165 sizeof(struct kvm_xcrs)))
4166 break;
4167 r = 0;
4168 break;
4169 }
4170 case KVM_SET_XCRS: {
4171 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4172 if (IS_ERR(u.xcrs)) {
4173 r = PTR_ERR(u.xcrs);
4174 goto out_nofree;
4175 }
4176
4177 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4178 break;
4179 }
4180 case KVM_SET_TSC_KHZ: {
4181 u32 user_tsc_khz;
4182
4183 r = -EINVAL;
4184 user_tsc_khz = (u32)arg;
4185
4186 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4187 goto out;
4188
4189 if (user_tsc_khz == 0)
4190 user_tsc_khz = tsc_khz;
4191
4192 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4193 r = 0;
4194
4195 goto out;
4196 }
4197 case KVM_GET_TSC_KHZ: {
4198 r = vcpu->arch.virtual_tsc_khz;
4199 goto out;
4200 }
4201 case KVM_KVMCLOCK_CTRL: {
4202 r = kvm_set_guest_paused(vcpu);
4203 goto out;
4204 }
4205 case KVM_ENABLE_CAP: {
4206 struct kvm_enable_cap cap;
4207
4208 r = -EFAULT;
4209 if (copy_from_user(&cap, argp, sizeof(cap)))
4210 goto out;
4211 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4212 break;
4213 }
4214 case KVM_GET_NESTED_STATE: {
4215 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4216 u32 user_data_size;
4217
4218 r = -EINVAL;
4219 if (!kvm_x86_ops->get_nested_state)
4220 break;
4221
4222 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4223 r = -EFAULT;
4224 if (get_user(user_data_size, &user_kvm_nested_state->size))
4225 break;
4226
4227 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4228 user_data_size);
4229 if (r < 0)
4230 break;
4231
4232 if (r > user_data_size) {
4233 if (put_user(r, &user_kvm_nested_state->size))
4234 r = -EFAULT;
4235 else
4236 r = -E2BIG;
4237 break;
4238 }
4239
4240 r = 0;
4241 break;
4242 }
4243 case KVM_SET_NESTED_STATE: {
4244 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4245 struct kvm_nested_state kvm_state;
4246
4247 r = -EINVAL;
4248 if (!kvm_x86_ops->set_nested_state)
4249 break;
4250
4251 r = -EFAULT;
4252 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4253 break;
4254
4255 r = -EINVAL;
4256 if (kvm_state.size < sizeof(kvm_state))
4257 break;
4258
4259 if (kvm_state.flags &
4260 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4261 | KVM_STATE_NESTED_EVMCS))
4262 break;
4263
4264 /* nested_run_pending implies guest_mode. */
4265 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4266 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4267 break;
4268
4269 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4270 break;
4271 }
4272 case KVM_GET_SUPPORTED_HV_CPUID: {
4273 struct kvm_cpuid2 __user *cpuid_arg = argp;
4274 struct kvm_cpuid2 cpuid;
4275
4276 r = -EFAULT;
4277 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4278 goto out;
4279
4280 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4281 cpuid_arg->entries);
4282 if (r)
4283 goto out;
4284
4285 r = -EFAULT;
4286 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4287 goto out;
4288 r = 0;
4289 break;
4290 }
4291 default:
4292 r = -EINVAL;
4293 }
4294 out:
4295 kfree(u.buffer);
4296 out_nofree:
4297 vcpu_put(vcpu);
4298 return r;
4299 }
4300
4301 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4302 {
4303 return VM_FAULT_SIGBUS;
4304 }
4305
4306 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4307 {
4308 int ret;
4309
4310 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4311 return -EINVAL;
4312 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4313 return ret;
4314 }
4315
4316 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4317 u64 ident_addr)
4318 {
4319 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4320 }
4321
4322 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4323 unsigned long kvm_nr_mmu_pages)
4324 {
4325 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4326 return -EINVAL;
4327
4328 mutex_lock(&kvm->slots_lock);
4329
4330 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4331 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4332
4333 mutex_unlock(&kvm->slots_lock);
4334 return 0;
4335 }
4336
4337 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4338 {
4339 return kvm->arch.n_max_mmu_pages;
4340 }
4341
4342 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4343 {
4344 struct kvm_pic *pic = kvm->arch.vpic;
4345 int r;
4346
4347 r = 0;
4348 switch (chip->chip_id) {
4349 case KVM_IRQCHIP_PIC_MASTER:
4350 memcpy(&chip->chip.pic, &pic->pics[0],
4351 sizeof(struct kvm_pic_state));
4352 break;
4353 case KVM_IRQCHIP_PIC_SLAVE:
4354 memcpy(&chip->chip.pic, &pic->pics[1],
4355 sizeof(struct kvm_pic_state));
4356 break;
4357 case KVM_IRQCHIP_IOAPIC:
4358 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4359 break;
4360 default:
4361 r = -EINVAL;
4362 break;
4363 }
4364 return r;
4365 }
4366
4367 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4368 {
4369 struct kvm_pic *pic = kvm->arch.vpic;
4370 int r;
4371
4372 r = 0;
4373 switch (chip->chip_id) {
4374 case KVM_IRQCHIP_PIC_MASTER:
4375 spin_lock(&pic->lock);
4376 memcpy(&pic->pics[0], &chip->chip.pic,
4377 sizeof(struct kvm_pic_state));
4378 spin_unlock(&pic->lock);
4379 break;
4380 case KVM_IRQCHIP_PIC_SLAVE:
4381 spin_lock(&pic->lock);
4382 memcpy(&pic->pics[1], &chip->chip.pic,
4383 sizeof(struct kvm_pic_state));
4384 spin_unlock(&pic->lock);
4385 break;
4386 case KVM_IRQCHIP_IOAPIC:
4387 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4388 break;
4389 default:
4390 r = -EINVAL;
4391 break;
4392 }
4393 kvm_pic_update_irq(pic);
4394 return r;
4395 }
4396
4397 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4398 {
4399 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4400
4401 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4402
4403 mutex_lock(&kps->lock);
4404 memcpy(ps, &kps->channels, sizeof(*ps));
4405 mutex_unlock(&kps->lock);
4406 return 0;
4407 }
4408
4409 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4410 {
4411 int i;
4412 struct kvm_pit *pit = kvm->arch.vpit;
4413
4414 mutex_lock(&pit->pit_state.lock);
4415 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4416 for (i = 0; i < 3; i++)
4417 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4418 mutex_unlock(&pit->pit_state.lock);
4419 return 0;
4420 }
4421
4422 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4423 {
4424 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4425 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4426 sizeof(ps->channels));
4427 ps->flags = kvm->arch.vpit->pit_state.flags;
4428 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4429 memset(&ps->reserved, 0, sizeof(ps->reserved));
4430 return 0;
4431 }
4432
4433 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4434 {
4435 int start = 0;
4436 int i;
4437 u32 prev_legacy, cur_legacy;
4438 struct kvm_pit *pit = kvm->arch.vpit;
4439
4440 mutex_lock(&pit->pit_state.lock);
4441 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4442 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4443 if (!prev_legacy && cur_legacy)
4444 start = 1;
4445 memcpy(&pit->pit_state.channels, &ps->channels,
4446 sizeof(pit->pit_state.channels));
4447 pit->pit_state.flags = ps->flags;
4448 for (i = 0; i < 3; i++)
4449 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4450 start && i == 0);
4451 mutex_unlock(&pit->pit_state.lock);
4452 return 0;
4453 }
4454
4455 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4456 struct kvm_reinject_control *control)
4457 {
4458 struct kvm_pit *pit = kvm->arch.vpit;
4459
4460 if (!pit)
4461 return -ENXIO;
4462
4463 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4464 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4465 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4466 */
4467 mutex_lock(&pit->pit_state.lock);
4468 kvm_pit_set_reinject(pit, control->pit_reinject);
4469 mutex_unlock(&pit->pit_state.lock);
4470
4471 return 0;
4472 }
4473
4474 /**
4475 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4476 * @kvm: kvm instance
4477 * @log: slot id and address to which we copy the log
4478 *
4479 * Steps 1-4 below provide general overview of dirty page logging. See
4480 * kvm_get_dirty_log_protect() function description for additional details.
4481 *
4482 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4483 * always flush the TLB (step 4) even if previous step failed and the dirty
4484 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4485 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4486 * writes will be marked dirty for next log read.
4487 *
4488 * 1. Take a snapshot of the bit and clear it if needed.
4489 * 2. Write protect the corresponding page.
4490 * 3. Copy the snapshot to the userspace.
4491 * 4. Flush TLB's if needed.
4492 */
4493 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4494 {
4495 bool flush = false;
4496 int r;
4497
4498 mutex_lock(&kvm->slots_lock);
4499
4500 /*
4501 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4502 */
4503 if (kvm_x86_ops->flush_log_dirty)
4504 kvm_x86_ops->flush_log_dirty(kvm);
4505
4506 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4507
4508 /*
4509 * All the TLBs can be flushed out of mmu lock, see the comments in
4510 * kvm_mmu_slot_remove_write_access().
4511 */
4512 lockdep_assert_held(&kvm->slots_lock);
4513 if (flush)
4514 kvm_flush_remote_tlbs(kvm);
4515
4516 mutex_unlock(&kvm->slots_lock);
4517 return r;
4518 }
4519
4520 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4521 {
4522 bool flush = false;
4523 int r;
4524
4525 mutex_lock(&kvm->slots_lock);
4526
4527 /*
4528 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4529 */
4530 if (kvm_x86_ops->flush_log_dirty)
4531 kvm_x86_ops->flush_log_dirty(kvm);
4532
4533 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4534
4535 /*
4536 * All the TLBs can be flushed out of mmu lock, see the comments in
4537 * kvm_mmu_slot_remove_write_access().
4538 */
4539 lockdep_assert_held(&kvm->slots_lock);
4540 if (flush)
4541 kvm_flush_remote_tlbs(kvm);
4542
4543 mutex_unlock(&kvm->slots_lock);
4544 return r;
4545 }
4546
4547 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4548 bool line_status)
4549 {
4550 if (!irqchip_in_kernel(kvm))
4551 return -ENXIO;
4552
4553 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4554 irq_event->irq, irq_event->level,
4555 line_status);
4556 return 0;
4557 }
4558
4559 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4560 struct kvm_enable_cap *cap)
4561 {
4562 int r;
4563
4564 if (cap->flags)
4565 return -EINVAL;
4566
4567 switch (cap->cap) {
4568 case KVM_CAP_DISABLE_QUIRKS:
4569 kvm->arch.disabled_quirks = cap->args[0];
4570 r = 0;
4571 break;
4572 case KVM_CAP_SPLIT_IRQCHIP: {
4573 mutex_lock(&kvm->lock);
4574 r = -EINVAL;
4575 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4576 goto split_irqchip_unlock;
4577 r = -EEXIST;
4578 if (irqchip_in_kernel(kvm))
4579 goto split_irqchip_unlock;
4580 if (kvm->created_vcpus)
4581 goto split_irqchip_unlock;
4582 r = kvm_setup_empty_irq_routing(kvm);
4583 if (r)
4584 goto split_irqchip_unlock;
4585 /* Pairs with irqchip_in_kernel. */
4586 smp_wmb();
4587 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4588 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4589 r = 0;
4590 split_irqchip_unlock:
4591 mutex_unlock(&kvm->lock);
4592 break;
4593 }
4594 case KVM_CAP_X2APIC_API:
4595 r = -EINVAL;
4596 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4597 break;
4598
4599 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4600 kvm->arch.x2apic_format = true;
4601 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4602 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4603
4604 r = 0;
4605 break;
4606 case KVM_CAP_X86_DISABLE_EXITS:
4607 r = -EINVAL;
4608 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4609 break;
4610
4611 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4612 kvm_can_mwait_in_guest())
4613 kvm->arch.mwait_in_guest = true;
4614 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4615 kvm->arch.hlt_in_guest = true;
4616 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4617 kvm->arch.pause_in_guest = true;
4618 r = 0;
4619 break;
4620 case KVM_CAP_MSR_PLATFORM_INFO:
4621 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4622 r = 0;
4623 break;
4624 case KVM_CAP_EXCEPTION_PAYLOAD:
4625 kvm->arch.exception_payload_enabled = cap->args[0];
4626 r = 0;
4627 break;
4628 default:
4629 r = -EINVAL;
4630 break;
4631 }
4632 return r;
4633 }
4634
4635 long kvm_arch_vm_ioctl(struct file *filp,
4636 unsigned int ioctl, unsigned long arg)
4637 {
4638 struct kvm *kvm = filp->private_data;
4639 void __user *argp = (void __user *)arg;
4640 int r = -ENOTTY;
4641 /*
4642 * This union makes it completely explicit to gcc-3.x
4643 * that these two variables' stack usage should be
4644 * combined, not added together.
4645 */
4646 union {
4647 struct kvm_pit_state ps;
4648 struct kvm_pit_state2 ps2;
4649 struct kvm_pit_config pit_config;
4650 } u;
4651
4652 switch (ioctl) {
4653 case KVM_SET_TSS_ADDR:
4654 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4655 break;
4656 case KVM_SET_IDENTITY_MAP_ADDR: {
4657 u64 ident_addr;
4658
4659 mutex_lock(&kvm->lock);
4660 r = -EINVAL;
4661 if (kvm->created_vcpus)
4662 goto set_identity_unlock;
4663 r = -EFAULT;
4664 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4665 goto set_identity_unlock;
4666 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4667 set_identity_unlock:
4668 mutex_unlock(&kvm->lock);
4669 break;
4670 }
4671 case KVM_SET_NR_MMU_PAGES:
4672 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4673 break;
4674 case KVM_GET_NR_MMU_PAGES:
4675 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4676 break;
4677 case KVM_CREATE_IRQCHIP: {
4678 mutex_lock(&kvm->lock);
4679
4680 r = -EEXIST;
4681 if (irqchip_in_kernel(kvm))
4682 goto create_irqchip_unlock;
4683
4684 r = -EINVAL;
4685 if (kvm->created_vcpus)
4686 goto create_irqchip_unlock;
4687
4688 r = kvm_pic_init(kvm);
4689 if (r)
4690 goto create_irqchip_unlock;
4691
4692 r = kvm_ioapic_init(kvm);
4693 if (r) {
4694 kvm_pic_destroy(kvm);
4695 goto create_irqchip_unlock;
4696 }
4697
4698 r = kvm_setup_default_irq_routing(kvm);
4699 if (r) {
4700 kvm_ioapic_destroy(kvm);
4701 kvm_pic_destroy(kvm);
4702 goto create_irqchip_unlock;
4703 }
4704 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4705 smp_wmb();
4706 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4707 create_irqchip_unlock:
4708 mutex_unlock(&kvm->lock);
4709 break;
4710 }
4711 case KVM_CREATE_PIT:
4712 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4713 goto create_pit;
4714 case KVM_CREATE_PIT2:
4715 r = -EFAULT;
4716 if (copy_from_user(&u.pit_config, argp,
4717 sizeof(struct kvm_pit_config)))
4718 goto out;
4719 create_pit:
4720 mutex_lock(&kvm->lock);
4721 r = -EEXIST;
4722 if (kvm->arch.vpit)
4723 goto create_pit_unlock;
4724 r = -ENOMEM;
4725 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4726 if (kvm->arch.vpit)
4727 r = 0;
4728 create_pit_unlock:
4729 mutex_unlock(&kvm->lock);
4730 break;
4731 case KVM_GET_IRQCHIP: {
4732 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4733 struct kvm_irqchip *chip;
4734
4735 chip = memdup_user(argp, sizeof(*chip));
4736 if (IS_ERR(chip)) {
4737 r = PTR_ERR(chip);
4738 goto out;
4739 }
4740
4741 r = -ENXIO;
4742 if (!irqchip_kernel(kvm))
4743 goto get_irqchip_out;
4744 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4745 if (r)
4746 goto get_irqchip_out;
4747 r = -EFAULT;
4748 if (copy_to_user(argp, chip, sizeof(*chip)))
4749 goto get_irqchip_out;
4750 r = 0;
4751 get_irqchip_out:
4752 kfree(chip);
4753 break;
4754 }
4755 case KVM_SET_IRQCHIP: {
4756 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4757 struct kvm_irqchip *chip;
4758
4759 chip = memdup_user(argp, sizeof(*chip));
4760 if (IS_ERR(chip)) {
4761 r = PTR_ERR(chip);
4762 goto out;
4763 }
4764
4765 r = -ENXIO;
4766 if (!irqchip_kernel(kvm))
4767 goto set_irqchip_out;
4768 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4769 if (r)
4770 goto set_irqchip_out;
4771 r = 0;
4772 set_irqchip_out:
4773 kfree(chip);
4774 break;
4775 }
4776 case KVM_GET_PIT: {
4777 r = -EFAULT;
4778 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4779 goto out;
4780 r = -ENXIO;
4781 if (!kvm->arch.vpit)
4782 goto out;
4783 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4784 if (r)
4785 goto out;
4786 r = -EFAULT;
4787 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4788 goto out;
4789 r = 0;
4790 break;
4791 }
4792 case KVM_SET_PIT: {
4793 r = -EFAULT;
4794 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4795 goto out;
4796 r = -ENXIO;
4797 if (!kvm->arch.vpit)
4798 goto out;
4799 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4800 break;
4801 }
4802 case KVM_GET_PIT2: {
4803 r = -ENXIO;
4804 if (!kvm->arch.vpit)
4805 goto out;
4806 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4807 if (r)
4808 goto out;
4809 r = -EFAULT;
4810 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4811 goto out;
4812 r = 0;
4813 break;
4814 }
4815 case KVM_SET_PIT2: {
4816 r = -EFAULT;
4817 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4818 goto out;
4819 r = -ENXIO;
4820 if (!kvm->arch.vpit)
4821 goto out;
4822 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4823 break;
4824 }
4825 case KVM_REINJECT_CONTROL: {
4826 struct kvm_reinject_control control;
4827 r = -EFAULT;
4828 if (copy_from_user(&control, argp, sizeof(control)))
4829 goto out;
4830 r = kvm_vm_ioctl_reinject(kvm, &control);
4831 break;
4832 }
4833 case KVM_SET_BOOT_CPU_ID:
4834 r = 0;
4835 mutex_lock(&kvm->lock);
4836 if (kvm->created_vcpus)
4837 r = -EBUSY;
4838 else
4839 kvm->arch.bsp_vcpu_id = arg;
4840 mutex_unlock(&kvm->lock);
4841 break;
4842 case KVM_XEN_HVM_CONFIG: {
4843 struct kvm_xen_hvm_config xhc;
4844 r = -EFAULT;
4845 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4846 goto out;
4847 r = -EINVAL;
4848 if (xhc.flags)
4849 goto out;
4850 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4851 r = 0;
4852 break;
4853 }
4854 case KVM_SET_CLOCK: {
4855 struct kvm_clock_data user_ns;
4856 u64 now_ns;
4857
4858 r = -EFAULT;
4859 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4860 goto out;
4861
4862 r = -EINVAL;
4863 if (user_ns.flags)
4864 goto out;
4865
4866 r = 0;
4867 /*
4868 * TODO: userspace has to take care of races with VCPU_RUN, so
4869 * kvm_gen_update_masterclock() can be cut down to locked
4870 * pvclock_update_vm_gtod_copy().
4871 */
4872 kvm_gen_update_masterclock(kvm);
4873 now_ns = get_kvmclock_ns(kvm);
4874 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4875 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4876 break;
4877 }
4878 case KVM_GET_CLOCK: {
4879 struct kvm_clock_data user_ns;
4880 u64 now_ns;
4881
4882 now_ns = get_kvmclock_ns(kvm);
4883 user_ns.clock = now_ns;
4884 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4885 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4886
4887 r = -EFAULT;
4888 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4889 goto out;
4890 r = 0;
4891 break;
4892 }
4893 case KVM_MEMORY_ENCRYPT_OP: {
4894 r = -ENOTTY;
4895 if (kvm_x86_ops->mem_enc_op)
4896 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4897 break;
4898 }
4899 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4900 struct kvm_enc_region region;
4901
4902 r = -EFAULT;
4903 if (copy_from_user(&region, argp, sizeof(region)))
4904 goto out;
4905
4906 r = -ENOTTY;
4907 if (kvm_x86_ops->mem_enc_reg_region)
4908 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4909 break;
4910 }
4911 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4912 struct kvm_enc_region region;
4913
4914 r = -EFAULT;
4915 if (copy_from_user(&region, argp, sizeof(region)))
4916 goto out;
4917
4918 r = -ENOTTY;
4919 if (kvm_x86_ops->mem_enc_unreg_region)
4920 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4921 break;
4922 }
4923 case KVM_HYPERV_EVENTFD: {
4924 struct kvm_hyperv_eventfd hvevfd;
4925
4926 r = -EFAULT;
4927 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4928 goto out;
4929 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4930 break;
4931 }
4932 default:
4933 r = -ENOTTY;
4934 }
4935 out:
4936 return r;
4937 }
4938
4939 static void kvm_init_msr_list(void)
4940 {
4941 u32 dummy[2];
4942 unsigned i, j;
4943
4944 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4945 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4946 continue;
4947
4948 /*
4949 * Even MSRs that are valid in the host may not be exposed
4950 * to the guests in some cases.
4951 */
4952 switch (msrs_to_save[i]) {
4953 case MSR_IA32_BNDCFGS:
4954 if (!kvm_mpx_supported())
4955 continue;
4956 break;
4957 case MSR_TSC_AUX:
4958 if (!kvm_x86_ops->rdtscp_supported())
4959 continue;
4960 break;
4961 case MSR_IA32_RTIT_CTL:
4962 case MSR_IA32_RTIT_STATUS:
4963 if (!kvm_x86_ops->pt_supported())
4964 continue;
4965 break;
4966 case MSR_IA32_RTIT_CR3_MATCH:
4967 if (!kvm_x86_ops->pt_supported() ||
4968 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4969 continue;
4970 break;
4971 case MSR_IA32_RTIT_OUTPUT_BASE:
4972 case MSR_IA32_RTIT_OUTPUT_MASK:
4973 if (!kvm_x86_ops->pt_supported() ||
4974 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4975 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4976 continue;
4977 break;
4978 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4979 if (!kvm_x86_ops->pt_supported() ||
4980 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4981 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4982 continue;
4983 break;
4984 }
4985 default:
4986 break;
4987 }
4988
4989 if (j < i)
4990 msrs_to_save[j] = msrs_to_save[i];
4991 j++;
4992 }
4993 num_msrs_to_save = j;
4994
4995 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4996 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4997 continue;
4998
4999 if (j < i)
5000 emulated_msrs[j] = emulated_msrs[i];
5001 j++;
5002 }
5003 num_emulated_msrs = j;
5004
5005 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5006 struct kvm_msr_entry msr;
5007
5008 msr.index = msr_based_features[i];
5009 if (kvm_get_msr_feature(&msr))
5010 continue;
5011
5012 if (j < i)
5013 msr_based_features[j] = msr_based_features[i];
5014 j++;
5015 }
5016 num_msr_based_features = j;
5017 }
5018
5019 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5020 const void *v)
5021 {
5022 int handled = 0;
5023 int n;
5024
5025 do {
5026 n = min(len, 8);
5027 if (!(lapic_in_kernel(vcpu) &&
5028 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5029 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5030 break;
5031 handled += n;
5032 addr += n;
5033 len -= n;
5034 v += n;
5035 } while (len);
5036
5037 return handled;
5038 }
5039
5040 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5041 {
5042 int handled = 0;
5043 int n;
5044
5045 do {
5046 n = min(len, 8);
5047 if (!(lapic_in_kernel(vcpu) &&
5048 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5049 addr, n, v))
5050 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5051 break;
5052 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5053 handled += n;
5054 addr += n;
5055 len -= n;
5056 v += n;
5057 } while (len);
5058
5059 return handled;
5060 }
5061
5062 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5063 struct kvm_segment *var, int seg)
5064 {
5065 kvm_x86_ops->set_segment(vcpu, var, seg);
5066 }
5067
5068 void kvm_get_segment(struct kvm_vcpu *vcpu,
5069 struct kvm_segment *var, int seg)
5070 {
5071 kvm_x86_ops->get_segment(vcpu, var, seg);
5072 }
5073
5074 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5075 struct x86_exception *exception)
5076 {
5077 gpa_t t_gpa;
5078
5079 BUG_ON(!mmu_is_nested(vcpu));
5080
5081 /* NPT walks are always user-walks */
5082 access |= PFERR_USER_MASK;
5083 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5084
5085 return t_gpa;
5086 }
5087
5088 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5089 struct x86_exception *exception)
5090 {
5091 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5092 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5093 }
5094
5095 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5096 struct x86_exception *exception)
5097 {
5098 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5099 access |= PFERR_FETCH_MASK;
5100 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5101 }
5102
5103 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5104 struct x86_exception *exception)
5105 {
5106 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5107 access |= PFERR_WRITE_MASK;
5108 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5109 }
5110
5111 /* uses this to access any guest's mapped memory without checking CPL */
5112 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5113 struct x86_exception *exception)
5114 {
5115 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5116 }
5117
5118 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5119 struct kvm_vcpu *vcpu, u32 access,
5120 struct x86_exception *exception)
5121 {
5122 void *data = val;
5123 int r = X86EMUL_CONTINUE;
5124
5125 while (bytes) {
5126 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5127 exception);
5128 unsigned offset = addr & (PAGE_SIZE-1);
5129 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5130 int ret;
5131
5132 if (gpa == UNMAPPED_GVA)
5133 return X86EMUL_PROPAGATE_FAULT;
5134 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5135 offset, toread);
5136 if (ret < 0) {
5137 r = X86EMUL_IO_NEEDED;
5138 goto out;
5139 }
5140
5141 bytes -= toread;
5142 data += toread;
5143 addr += toread;
5144 }
5145 out:
5146 return r;
5147 }
5148
5149 /* used for instruction fetching */
5150 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5151 gva_t addr, void *val, unsigned int bytes,
5152 struct x86_exception *exception)
5153 {
5154 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5155 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5156 unsigned offset;
5157 int ret;
5158
5159 /* Inline kvm_read_guest_virt_helper for speed. */
5160 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5161 exception);
5162 if (unlikely(gpa == UNMAPPED_GVA))
5163 return X86EMUL_PROPAGATE_FAULT;
5164
5165 offset = addr & (PAGE_SIZE-1);
5166 if (WARN_ON(offset + bytes > PAGE_SIZE))
5167 bytes = (unsigned)PAGE_SIZE - offset;
5168 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5169 offset, bytes);
5170 if (unlikely(ret < 0))
5171 return X86EMUL_IO_NEEDED;
5172
5173 return X86EMUL_CONTINUE;
5174 }
5175
5176 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5177 gva_t addr, void *val, unsigned int bytes,
5178 struct x86_exception *exception)
5179 {
5180 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5181
5182 /*
5183 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5184 * is returned, but our callers are not ready for that and they blindly
5185 * call kvm_inject_page_fault. Ensure that they at least do not leak
5186 * uninitialized kernel stack memory into cr2 and error code.
5187 */
5188 memset(exception, 0, sizeof(*exception));
5189 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5190 exception);
5191 }
5192 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5193
5194 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5195 gva_t addr, void *val, unsigned int bytes,
5196 struct x86_exception *exception, bool system)
5197 {
5198 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5199 u32 access = 0;
5200
5201 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5202 access |= PFERR_USER_MASK;
5203
5204 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5205 }
5206
5207 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5208 unsigned long addr, void *val, unsigned int bytes)
5209 {
5210 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5211 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5212
5213 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5214 }
5215
5216 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5217 struct kvm_vcpu *vcpu, u32 access,
5218 struct x86_exception *exception)
5219 {
5220 void *data = val;
5221 int r = X86EMUL_CONTINUE;
5222
5223 while (bytes) {
5224 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5225 access,
5226 exception);
5227 unsigned offset = addr & (PAGE_SIZE-1);
5228 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5229 int ret;
5230
5231 if (gpa == UNMAPPED_GVA)
5232 return X86EMUL_PROPAGATE_FAULT;
5233 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5234 if (ret < 0) {
5235 r = X86EMUL_IO_NEEDED;
5236 goto out;
5237 }
5238
5239 bytes -= towrite;
5240 data += towrite;
5241 addr += towrite;
5242 }
5243 out:
5244 return r;
5245 }
5246
5247 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5248 unsigned int bytes, struct x86_exception *exception,
5249 bool system)
5250 {
5251 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5252 u32 access = PFERR_WRITE_MASK;
5253
5254 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5255 access |= PFERR_USER_MASK;
5256
5257 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5258 access, exception);
5259 }
5260
5261 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5262 unsigned int bytes, struct x86_exception *exception)
5263 {
5264 /* kvm_write_guest_virt_system can pull in tons of pages. */
5265 vcpu->arch.l1tf_flush_l1d = true;
5266
5267 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5268 PFERR_WRITE_MASK, exception);
5269 }
5270 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5271
5272 int handle_ud(struct kvm_vcpu *vcpu)
5273 {
5274 int emul_type = EMULTYPE_TRAP_UD;
5275 enum emulation_result er;
5276 char sig[5]; /* ud2; .ascii "kvm" */
5277 struct x86_exception e;
5278
5279 if (force_emulation_prefix &&
5280 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5281 sig, sizeof(sig), &e) == 0 &&
5282 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5283 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5284 emul_type = 0;
5285 }
5286
5287 er = kvm_emulate_instruction(vcpu, emul_type);
5288 if (er == EMULATE_USER_EXIT)
5289 return 0;
5290 if (er != EMULATE_DONE)
5291 kvm_queue_exception(vcpu, UD_VECTOR);
5292 return 1;
5293 }
5294 EXPORT_SYMBOL_GPL(handle_ud);
5295
5296 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5297 gpa_t gpa, bool write)
5298 {
5299 /* For APIC access vmexit */
5300 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5301 return 1;
5302
5303 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5304 trace_vcpu_match_mmio(gva, gpa, write, true);
5305 return 1;
5306 }
5307
5308 return 0;
5309 }
5310
5311 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5312 gpa_t *gpa, struct x86_exception *exception,
5313 bool write)
5314 {
5315 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5316 | (write ? PFERR_WRITE_MASK : 0);
5317
5318 /*
5319 * currently PKRU is only applied to ept enabled guest so
5320 * there is no pkey in EPT page table for L1 guest or EPT
5321 * shadow page table for L2 guest.
5322 */
5323 if (vcpu_match_mmio_gva(vcpu, gva)
5324 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5325 vcpu->arch.access, 0, access)) {
5326 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5327 (gva & (PAGE_SIZE - 1));
5328 trace_vcpu_match_mmio(gva, *gpa, write, false);
5329 return 1;
5330 }
5331
5332 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5333
5334 if (*gpa == UNMAPPED_GVA)
5335 return -1;
5336
5337 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5338 }
5339
5340 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5341 const void *val, int bytes)
5342 {
5343 int ret;
5344
5345 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5346 if (ret < 0)
5347 return 0;
5348 kvm_page_track_write(vcpu, gpa, val, bytes);
5349 return 1;
5350 }
5351
5352 struct read_write_emulator_ops {
5353 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5354 int bytes);
5355 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5356 void *val, int bytes);
5357 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5358 int bytes, void *val);
5359 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5360 void *val, int bytes);
5361 bool write;
5362 };
5363
5364 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5365 {
5366 if (vcpu->mmio_read_completed) {
5367 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5368 vcpu->mmio_fragments[0].gpa, val);
5369 vcpu->mmio_read_completed = 0;
5370 return 1;
5371 }
5372
5373 return 0;
5374 }
5375
5376 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5377 void *val, int bytes)
5378 {
5379 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5380 }
5381
5382 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5383 void *val, int bytes)
5384 {
5385 return emulator_write_phys(vcpu, gpa, val, bytes);
5386 }
5387
5388 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5389 {
5390 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5391 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5392 }
5393
5394 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5395 void *val, int bytes)
5396 {
5397 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5398 return X86EMUL_IO_NEEDED;
5399 }
5400
5401 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5402 void *val, int bytes)
5403 {
5404 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5405
5406 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5407 return X86EMUL_CONTINUE;
5408 }
5409
5410 static const struct read_write_emulator_ops read_emultor = {
5411 .read_write_prepare = read_prepare,
5412 .read_write_emulate = read_emulate,
5413 .read_write_mmio = vcpu_mmio_read,
5414 .read_write_exit_mmio = read_exit_mmio,
5415 };
5416
5417 static const struct read_write_emulator_ops write_emultor = {
5418 .read_write_emulate = write_emulate,
5419 .read_write_mmio = write_mmio,
5420 .read_write_exit_mmio = write_exit_mmio,
5421 .write = true,
5422 };
5423
5424 static int emulator_read_write_onepage(unsigned long addr, void *val,
5425 unsigned int bytes,
5426 struct x86_exception *exception,
5427 struct kvm_vcpu *vcpu,
5428 const struct read_write_emulator_ops *ops)
5429 {
5430 gpa_t gpa;
5431 int handled, ret;
5432 bool write = ops->write;
5433 struct kvm_mmio_fragment *frag;
5434 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5435
5436 /*
5437 * If the exit was due to a NPF we may already have a GPA.
5438 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5439 * Note, this cannot be used on string operations since string
5440 * operation using rep will only have the initial GPA from the NPF
5441 * occurred.
5442 */
5443 if (vcpu->arch.gpa_available &&
5444 emulator_can_use_gpa(ctxt) &&
5445 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5446 gpa = vcpu->arch.gpa_val;
5447 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5448 } else {
5449 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5450 if (ret < 0)
5451 return X86EMUL_PROPAGATE_FAULT;
5452 }
5453
5454 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5455 return X86EMUL_CONTINUE;
5456
5457 /*
5458 * Is this MMIO handled locally?
5459 */
5460 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5461 if (handled == bytes)
5462 return X86EMUL_CONTINUE;
5463
5464 gpa += handled;
5465 bytes -= handled;
5466 val += handled;
5467
5468 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5469 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5470 frag->gpa = gpa;
5471 frag->data = val;
5472 frag->len = bytes;
5473 return X86EMUL_CONTINUE;
5474 }
5475
5476 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5477 unsigned long addr,
5478 void *val, unsigned int bytes,
5479 struct x86_exception *exception,
5480 const struct read_write_emulator_ops *ops)
5481 {
5482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5483 gpa_t gpa;
5484 int rc;
5485
5486 if (ops->read_write_prepare &&
5487 ops->read_write_prepare(vcpu, val, bytes))
5488 return X86EMUL_CONTINUE;
5489
5490 vcpu->mmio_nr_fragments = 0;
5491
5492 /* Crossing a page boundary? */
5493 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5494 int now;
5495
5496 now = -addr & ~PAGE_MASK;
5497 rc = emulator_read_write_onepage(addr, val, now, exception,
5498 vcpu, ops);
5499
5500 if (rc != X86EMUL_CONTINUE)
5501 return rc;
5502 addr += now;
5503 if (ctxt->mode != X86EMUL_MODE_PROT64)
5504 addr = (u32)addr;
5505 val += now;
5506 bytes -= now;
5507 }
5508
5509 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5510 vcpu, ops);
5511 if (rc != X86EMUL_CONTINUE)
5512 return rc;
5513
5514 if (!vcpu->mmio_nr_fragments)
5515 return rc;
5516
5517 gpa = vcpu->mmio_fragments[0].gpa;
5518
5519 vcpu->mmio_needed = 1;
5520 vcpu->mmio_cur_fragment = 0;
5521
5522 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5523 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5524 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5525 vcpu->run->mmio.phys_addr = gpa;
5526
5527 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5528 }
5529
5530 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5531 unsigned long addr,
5532 void *val,
5533 unsigned int bytes,
5534 struct x86_exception *exception)
5535 {
5536 return emulator_read_write(ctxt, addr, val, bytes,
5537 exception, &read_emultor);
5538 }
5539
5540 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5541 unsigned long addr,
5542 const void *val,
5543 unsigned int bytes,
5544 struct x86_exception *exception)
5545 {
5546 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5547 exception, &write_emultor);
5548 }
5549
5550 #define CMPXCHG_TYPE(t, ptr, old, new) \
5551 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5552
5553 #ifdef CONFIG_X86_64
5554 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5555 #else
5556 # define CMPXCHG64(ptr, old, new) \
5557 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5558 #endif
5559
5560 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5561 unsigned long addr,
5562 const void *old,
5563 const void *new,
5564 unsigned int bytes,
5565 struct x86_exception *exception)
5566 {
5567 struct kvm_host_map map;
5568 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5569 gpa_t gpa;
5570 char *kaddr;
5571 bool exchanged;
5572
5573 /* guests cmpxchg8b have to be emulated atomically */
5574 if (bytes > 8 || (bytes & (bytes - 1)))
5575 goto emul_write;
5576
5577 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5578
5579 if (gpa == UNMAPPED_GVA ||
5580 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5581 goto emul_write;
5582
5583 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5584 goto emul_write;
5585
5586 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5587 goto emul_write;
5588
5589 kaddr = map.hva + offset_in_page(gpa);
5590
5591 switch (bytes) {
5592 case 1:
5593 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5594 break;
5595 case 2:
5596 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5597 break;
5598 case 4:
5599 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5600 break;
5601 case 8:
5602 exchanged = CMPXCHG64(kaddr, old, new);
5603 break;
5604 default:
5605 BUG();
5606 }
5607
5608 kvm_vcpu_unmap(vcpu, &map, true);
5609
5610 if (!exchanged)
5611 return X86EMUL_CMPXCHG_FAILED;
5612
5613 kvm_page_track_write(vcpu, gpa, new, bytes);
5614
5615 return X86EMUL_CONTINUE;
5616
5617 emul_write:
5618 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5619
5620 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5621 }
5622
5623 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5624 {
5625 int r = 0, i;
5626
5627 for (i = 0; i < vcpu->arch.pio.count; i++) {
5628 if (vcpu->arch.pio.in)
5629 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5630 vcpu->arch.pio.size, pd);
5631 else
5632 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5633 vcpu->arch.pio.port, vcpu->arch.pio.size,
5634 pd);
5635 if (r)
5636 break;
5637 pd += vcpu->arch.pio.size;
5638 }
5639 return r;
5640 }
5641
5642 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5643 unsigned short port, void *val,
5644 unsigned int count, bool in)
5645 {
5646 vcpu->arch.pio.port = port;
5647 vcpu->arch.pio.in = in;
5648 vcpu->arch.pio.count = count;
5649 vcpu->arch.pio.size = size;
5650
5651 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5652 vcpu->arch.pio.count = 0;
5653 return 1;
5654 }
5655
5656 vcpu->run->exit_reason = KVM_EXIT_IO;
5657 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5658 vcpu->run->io.size = size;
5659 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5660 vcpu->run->io.count = count;
5661 vcpu->run->io.port = port;
5662
5663 return 0;
5664 }
5665
5666 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5667 int size, unsigned short port, void *val,
5668 unsigned int count)
5669 {
5670 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5671 int ret;
5672
5673 if (vcpu->arch.pio.count)
5674 goto data_avail;
5675
5676 memset(vcpu->arch.pio_data, 0, size * count);
5677
5678 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5679 if (ret) {
5680 data_avail:
5681 memcpy(val, vcpu->arch.pio_data, size * count);
5682 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5683 vcpu->arch.pio.count = 0;
5684 return 1;
5685 }
5686
5687 return 0;
5688 }
5689
5690 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5691 int size, unsigned short port,
5692 const void *val, unsigned int count)
5693 {
5694 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5695
5696 memcpy(vcpu->arch.pio_data, val, size * count);
5697 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5698 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5699 }
5700
5701 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5702 {
5703 return kvm_x86_ops->get_segment_base(vcpu, seg);
5704 }
5705
5706 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5707 {
5708 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5709 }
5710
5711 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5712 {
5713 if (!need_emulate_wbinvd(vcpu))
5714 return X86EMUL_CONTINUE;
5715
5716 if (kvm_x86_ops->has_wbinvd_exit()) {
5717 int cpu = get_cpu();
5718
5719 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5720 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5721 wbinvd_ipi, NULL, 1);
5722 put_cpu();
5723 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5724 } else
5725 wbinvd();
5726 return X86EMUL_CONTINUE;
5727 }
5728
5729 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5730 {
5731 kvm_emulate_wbinvd_noskip(vcpu);
5732 return kvm_skip_emulated_instruction(vcpu);
5733 }
5734 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5735
5736
5737
5738 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5739 {
5740 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5741 }
5742
5743 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5744 unsigned long *dest)
5745 {
5746 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5747 }
5748
5749 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5750 unsigned long value)
5751 {
5752
5753 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5754 }
5755
5756 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5757 {
5758 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5759 }
5760
5761 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5762 {
5763 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5764 unsigned long value;
5765
5766 switch (cr) {
5767 case 0:
5768 value = kvm_read_cr0(vcpu);
5769 break;
5770 case 2:
5771 value = vcpu->arch.cr2;
5772 break;
5773 case 3:
5774 value = kvm_read_cr3(vcpu);
5775 break;
5776 case 4:
5777 value = kvm_read_cr4(vcpu);
5778 break;
5779 case 8:
5780 value = kvm_get_cr8(vcpu);
5781 break;
5782 default:
5783 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5784 return 0;
5785 }
5786
5787 return value;
5788 }
5789
5790 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5791 {
5792 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5793 int res = 0;
5794
5795 switch (cr) {
5796 case 0:
5797 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5798 break;
5799 case 2:
5800 vcpu->arch.cr2 = val;
5801 break;
5802 case 3:
5803 res = kvm_set_cr3(vcpu, val);
5804 break;
5805 case 4:
5806 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5807 break;
5808 case 8:
5809 res = kvm_set_cr8(vcpu, val);
5810 break;
5811 default:
5812 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5813 res = -1;
5814 }
5815
5816 return res;
5817 }
5818
5819 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5820 {
5821 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5822 }
5823
5824 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5825 {
5826 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5827 }
5828
5829 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5830 {
5831 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5832 }
5833
5834 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5835 {
5836 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5837 }
5838
5839 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5840 {
5841 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5842 }
5843
5844 static unsigned long emulator_get_cached_segment_base(
5845 struct x86_emulate_ctxt *ctxt, int seg)
5846 {
5847 return get_segment_base(emul_to_vcpu(ctxt), seg);
5848 }
5849
5850 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5851 struct desc_struct *desc, u32 *base3,
5852 int seg)
5853 {
5854 struct kvm_segment var;
5855
5856 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5857 *selector = var.selector;
5858
5859 if (var.unusable) {
5860 memset(desc, 0, sizeof(*desc));
5861 if (base3)
5862 *base3 = 0;
5863 return false;
5864 }
5865
5866 if (var.g)
5867 var.limit >>= 12;
5868 set_desc_limit(desc, var.limit);
5869 set_desc_base(desc, (unsigned long)var.base);
5870 #ifdef CONFIG_X86_64
5871 if (base3)
5872 *base3 = var.base >> 32;
5873 #endif
5874 desc->type = var.type;
5875 desc->s = var.s;
5876 desc->dpl = var.dpl;
5877 desc->p = var.present;
5878 desc->avl = var.avl;
5879 desc->l = var.l;
5880 desc->d = var.db;
5881 desc->g = var.g;
5882
5883 return true;
5884 }
5885
5886 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5887 struct desc_struct *desc, u32 base3,
5888 int seg)
5889 {
5890 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5891 struct kvm_segment var;
5892
5893 var.selector = selector;
5894 var.base = get_desc_base(desc);
5895 #ifdef CONFIG_X86_64
5896 var.base |= ((u64)base3) << 32;
5897 #endif
5898 var.limit = get_desc_limit(desc);
5899 if (desc->g)
5900 var.limit = (var.limit << 12) | 0xfff;
5901 var.type = desc->type;
5902 var.dpl = desc->dpl;
5903 var.db = desc->d;
5904 var.s = desc->s;
5905 var.l = desc->l;
5906 var.g = desc->g;
5907 var.avl = desc->avl;
5908 var.present = desc->p;
5909 var.unusable = !var.present;
5910 var.padding = 0;
5911
5912 kvm_set_segment(vcpu, &var, seg);
5913 return;
5914 }
5915
5916 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5917 u32 msr_index, u64 *pdata)
5918 {
5919 struct msr_data msr;
5920 int r;
5921
5922 msr.index = msr_index;
5923 msr.host_initiated = false;
5924 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5925 if (r)
5926 return r;
5927
5928 *pdata = msr.data;
5929 return 0;
5930 }
5931
5932 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5933 u32 msr_index, u64 data)
5934 {
5935 struct msr_data msr;
5936
5937 msr.data = data;
5938 msr.index = msr_index;
5939 msr.host_initiated = false;
5940 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5941 }
5942
5943 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5944 {
5945 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5946
5947 return vcpu->arch.smbase;
5948 }
5949
5950 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5951 {
5952 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5953
5954 vcpu->arch.smbase = smbase;
5955 }
5956
5957 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5958 u32 pmc)
5959 {
5960 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5961 }
5962
5963 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5964 u32 pmc, u64 *pdata)
5965 {
5966 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5967 }
5968
5969 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5970 {
5971 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5972 }
5973
5974 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5975 struct x86_instruction_info *info,
5976 enum x86_intercept_stage stage)
5977 {
5978 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5979 }
5980
5981 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5982 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5983 {
5984 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5985 }
5986
5987 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5988 {
5989 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5990 }
5991
5992 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5993 {
5994 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5995 }
5996
5997 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5998 {
5999 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6000 }
6001
6002 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6003 {
6004 return emul_to_vcpu(ctxt)->arch.hflags;
6005 }
6006
6007 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6008 {
6009 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6010 }
6011
6012 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6013 const char *smstate)
6014 {
6015 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6016 }
6017
6018 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6019 {
6020 kvm_smm_changed(emul_to_vcpu(ctxt));
6021 }
6022
6023 static const struct x86_emulate_ops emulate_ops = {
6024 .read_gpr = emulator_read_gpr,
6025 .write_gpr = emulator_write_gpr,
6026 .read_std = emulator_read_std,
6027 .write_std = emulator_write_std,
6028 .read_phys = kvm_read_guest_phys_system,
6029 .fetch = kvm_fetch_guest_virt,
6030 .read_emulated = emulator_read_emulated,
6031 .write_emulated = emulator_write_emulated,
6032 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6033 .invlpg = emulator_invlpg,
6034 .pio_in_emulated = emulator_pio_in_emulated,
6035 .pio_out_emulated = emulator_pio_out_emulated,
6036 .get_segment = emulator_get_segment,
6037 .set_segment = emulator_set_segment,
6038 .get_cached_segment_base = emulator_get_cached_segment_base,
6039 .get_gdt = emulator_get_gdt,
6040 .get_idt = emulator_get_idt,
6041 .set_gdt = emulator_set_gdt,
6042 .set_idt = emulator_set_idt,
6043 .get_cr = emulator_get_cr,
6044 .set_cr = emulator_set_cr,
6045 .cpl = emulator_get_cpl,
6046 .get_dr = emulator_get_dr,
6047 .set_dr = emulator_set_dr,
6048 .get_smbase = emulator_get_smbase,
6049 .set_smbase = emulator_set_smbase,
6050 .set_msr = emulator_set_msr,
6051 .get_msr = emulator_get_msr,
6052 .check_pmc = emulator_check_pmc,
6053 .read_pmc = emulator_read_pmc,
6054 .halt = emulator_halt,
6055 .wbinvd = emulator_wbinvd,
6056 .fix_hypercall = emulator_fix_hypercall,
6057 .intercept = emulator_intercept,
6058 .get_cpuid = emulator_get_cpuid,
6059 .set_nmi_mask = emulator_set_nmi_mask,
6060 .get_hflags = emulator_get_hflags,
6061 .set_hflags = emulator_set_hflags,
6062 .pre_leave_smm = emulator_pre_leave_smm,
6063 .post_leave_smm = emulator_post_leave_smm,
6064 };
6065
6066 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6067 {
6068 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6069 /*
6070 * an sti; sti; sequence only disable interrupts for the first
6071 * instruction. So, if the last instruction, be it emulated or
6072 * not, left the system with the INT_STI flag enabled, it
6073 * means that the last instruction is an sti. We should not
6074 * leave the flag on in this case. The same goes for mov ss
6075 */
6076 if (int_shadow & mask)
6077 mask = 0;
6078 if (unlikely(int_shadow || mask)) {
6079 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6080 if (!mask)
6081 kvm_make_request(KVM_REQ_EVENT, vcpu);
6082 }
6083 }
6084
6085 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6086 {
6087 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6088 if (ctxt->exception.vector == PF_VECTOR)
6089 return kvm_propagate_fault(vcpu, &ctxt->exception);
6090
6091 if (ctxt->exception.error_code_valid)
6092 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6093 ctxt->exception.error_code);
6094 else
6095 kvm_queue_exception(vcpu, ctxt->exception.vector);
6096 return false;
6097 }
6098
6099 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6100 {
6101 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6102 int cs_db, cs_l;
6103
6104 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6105
6106 ctxt->eflags = kvm_get_rflags(vcpu);
6107 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6108
6109 ctxt->eip = kvm_rip_read(vcpu);
6110 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6111 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6112 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6113 cs_db ? X86EMUL_MODE_PROT32 :
6114 X86EMUL_MODE_PROT16;
6115 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6116 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6117 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6118
6119 init_decode_cache(ctxt);
6120 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6121 }
6122
6123 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6124 {
6125 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6126 int ret;
6127
6128 init_emulate_ctxt(vcpu);
6129
6130 ctxt->op_bytes = 2;
6131 ctxt->ad_bytes = 2;
6132 ctxt->_eip = ctxt->eip + inc_eip;
6133 ret = emulate_int_real(ctxt, irq);
6134
6135 if (ret != X86EMUL_CONTINUE)
6136 return EMULATE_FAIL;
6137
6138 ctxt->eip = ctxt->_eip;
6139 kvm_rip_write(vcpu, ctxt->eip);
6140 kvm_set_rflags(vcpu, ctxt->eflags);
6141
6142 return EMULATE_DONE;
6143 }
6144 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6145
6146 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6147 {
6148 int r = EMULATE_DONE;
6149
6150 ++vcpu->stat.insn_emulation_fail;
6151 trace_kvm_emulate_insn_failed(vcpu);
6152
6153 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6154 return EMULATE_FAIL;
6155
6156 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6157 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6158 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6159 vcpu->run->internal.ndata = 0;
6160 r = EMULATE_USER_EXIT;
6161 }
6162
6163 kvm_queue_exception(vcpu, UD_VECTOR);
6164
6165 return r;
6166 }
6167
6168 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6169 bool write_fault_to_shadow_pgtable,
6170 int emulation_type)
6171 {
6172 gpa_t gpa = cr2;
6173 kvm_pfn_t pfn;
6174
6175 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6176 return false;
6177
6178 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6179 return false;
6180
6181 if (!vcpu->arch.mmu->direct_map) {
6182 /*
6183 * Write permission should be allowed since only
6184 * write access need to be emulated.
6185 */
6186 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6187
6188 /*
6189 * If the mapping is invalid in guest, let cpu retry
6190 * it to generate fault.
6191 */
6192 if (gpa == UNMAPPED_GVA)
6193 return true;
6194 }
6195
6196 /*
6197 * Do not retry the unhandleable instruction if it faults on the
6198 * readonly host memory, otherwise it will goto a infinite loop:
6199 * retry instruction -> write #PF -> emulation fail -> retry
6200 * instruction -> ...
6201 */
6202 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6203
6204 /*
6205 * If the instruction failed on the error pfn, it can not be fixed,
6206 * report the error to userspace.
6207 */
6208 if (is_error_noslot_pfn(pfn))
6209 return false;
6210
6211 kvm_release_pfn_clean(pfn);
6212
6213 /* The instructions are well-emulated on direct mmu. */
6214 if (vcpu->arch.mmu->direct_map) {
6215 unsigned int indirect_shadow_pages;
6216
6217 spin_lock(&vcpu->kvm->mmu_lock);
6218 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6219 spin_unlock(&vcpu->kvm->mmu_lock);
6220
6221 if (indirect_shadow_pages)
6222 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6223
6224 return true;
6225 }
6226
6227 /*
6228 * if emulation was due to access to shadowed page table
6229 * and it failed try to unshadow page and re-enter the
6230 * guest to let CPU execute the instruction.
6231 */
6232 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6233
6234 /*
6235 * If the access faults on its page table, it can not
6236 * be fixed by unprotecting shadow page and it should
6237 * be reported to userspace.
6238 */
6239 return !write_fault_to_shadow_pgtable;
6240 }
6241
6242 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6243 unsigned long cr2, int emulation_type)
6244 {
6245 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6246 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6247
6248 last_retry_eip = vcpu->arch.last_retry_eip;
6249 last_retry_addr = vcpu->arch.last_retry_addr;
6250
6251 /*
6252 * If the emulation is caused by #PF and it is non-page_table
6253 * writing instruction, it means the VM-EXIT is caused by shadow
6254 * page protected, we can zap the shadow page and retry this
6255 * instruction directly.
6256 *
6257 * Note: if the guest uses a non-page-table modifying instruction
6258 * on the PDE that points to the instruction, then we will unmap
6259 * the instruction and go to an infinite loop. So, we cache the
6260 * last retried eip and the last fault address, if we meet the eip
6261 * and the address again, we can break out of the potential infinite
6262 * loop.
6263 */
6264 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6265
6266 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6267 return false;
6268
6269 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6270 return false;
6271
6272 if (x86_page_table_writing_insn(ctxt))
6273 return false;
6274
6275 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6276 return false;
6277
6278 vcpu->arch.last_retry_eip = ctxt->eip;
6279 vcpu->arch.last_retry_addr = cr2;
6280
6281 if (!vcpu->arch.mmu->direct_map)
6282 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6283
6284 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6285
6286 return true;
6287 }
6288
6289 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6290 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6291
6292 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6293 {
6294 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6295 /* This is a good place to trace that we are exiting SMM. */
6296 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6297
6298 /* Process a latched INIT or SMI, if any. */
6299 kvm_make_request(KVM_REQ_EVENT, vcpu);
6300 }
6301
6302 kvm_mmu_reset_context(vcpu);
6303 }
6304
6305 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6306 unsigned long *db)
6307 {
6308 u32 dr6 = 0;
6309 int i;
6310 u32 enable, rwlen;
6311
6312 enable = dr7;
6313 rwlen = dr7 >> 16;
6314 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6315 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6316 dr6 |= (1 << i);
6317 return dr6;
6318 }
6319
6320 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6321 {
6322 struct kvm_run *kvm_run = vcpu->run;
6323
6324 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6325 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6326 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6327 kvm_run->debug.arch.exception = DB_VECTOR;
6328 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6329 *r = EMULATE_USER_EXIT;
6330 } else {
6331 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6332 }
6333 }
6334
6335 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6336 {
6337 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6338 int r = EMULATE_DONE;
6339
6340 kvm_x86_ops->skip_emulated_instruction(vcpu);
6341
6342 /*
6343 * rflags is the old, "raw" value of the flags. The new value has
6344 * not been saved yet.
6345 *
6346 * This is correct even for TF set by the guest, because "the
6347 * processor will not generate this exception after the instruction
6348 * that sets the TF flag".
6349 */
6350 if (unlikely(rflags & X86_EFLAGS_TF))
6351 kvm_vcpu_do_singlestep(vcpu, &r);
6352 return r == EMULATE_DONE;
6353 }
6354 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6355
6356 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6357 {
6358 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6359 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6360 struct kvm_run *kvm_run = vcpu->run;
6361 unsigned long eip = kvm_get_linear_rip(vcpu);
6362 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6363 vcpu->arch.guest_debug_dr7,
6364 vcpu->arch.eff_db);
6365
6366 if (dr6 != 0) {
6367 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6368 kvm_run->debug.arch.pc = eip;
6369 kvm_run->debug.arch.exception = DB_VECTOR;
6370 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6371 *r = EMULATE_USER_EXIT;
6372 return true;
6373 }
6374 }
6375
6376 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6377 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6378 unsigned long eip = kvm_get_linear_rip(vcpu);
6379 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6380 vcpu->arch.dr7,
6381 vcpu->arch.db);
6382
6383 if (dr6 != 0) {
6384 vcpu->arch.dr6 &= ~15;
6385 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6386 kvm_queue_exception(vcpu, DB_VECTOR);
6387 *r = EMULATE_DONE;
6388 return true;
6389 }
6390 }
6391
6392 return false;
6393 }
6394
6395 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6396 {
6397 switch (ctxt->opcode_len) {
6398 case 1:
6399 switch (ctxt->b) {
6400 case 0xe4: /* IN */
6401 case 0xe5:
6402 case 0xec:
6403 case 0xed:
6404 case 0xe6: /* OUT */
6405 case 0xe7:
6406 case 0xee:
6407 case 0xef:
6408 case 0x6c: /* INS */
6409 case 0x6d:
6410 case 0x6e: /* OUTS */
6411 case 0x6f:
6412 return true;
6413 }
6414 break;
6415 case 2:
6416 switch (ctxt->b) {
6417 case 0x33: /* RDPMC */
6418 return true;
6419 }
6420 break;
6421 }
6422
6423 return false;
6424 }
6425
6426 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6427 unsigned long cr2,
6428 int emulation_type,
6429 void *insn,
6430 int insn_len)
6431 {
6432 int r;
6433 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6434 bool writeback = true;
6435 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6436
6437 vcpu->arch.l1tf_flush_l1d = true;
6438
6439 /*
6440 * Clear write_fault_to_shadow_pgtable here to ensure it is
6441 * never reused.
6442 */
6443 vcpu->arch.write_fault_to_shadow_pgtable = false;
6444 kvm_clear_exception_queue(vcpu);
6445
6446 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6447 init_emulate_ctxt(vcpu);
6448
6449 /*
6450 * We will reenter on the same instruction since
6451 * we do not set complete_userspace_io. This does not
6452 * handle watchpoints yet, those would be handled in
6453 * the emulate_ops.
6454 */
6455 if (!(emulation_type & EMULTYPE_SKIP) &&
6456 kvm_vcpu_check_breakpoint(vcpu, &r))
6457 return r;
6458
6459 ctxt->interruptibility = 0;
6460 ctxt->have_exception = false;
6461 ctxt->exception.vector = -1;
6462 ctxt->perm_ok = false;
6463
6464 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6465
6466 r = x86_decode_insn(ctxt, insn, insn_len);
6467
6468 trace_kvm_emulate_insn_start(vcpu);
6469 ++vcpu->stat.insn_emulation;
6470 if (r != EMULATION_OK) {
6471 if (emulation_type & EMULTYPE_TRAP_UD)
6472 return EMULATE_FAIL;
6473 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6474 emulation_type))
6475 return EMULATE_DONE;
6476 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6477 return EMULATE_DONE;
6478 if (emulation_type & EMULTYPE_SKIP)
6479 return EMULATE_FAIL;
6480 return handle_emulation_failure(vcpu, emulation_type);
6481 }
6482 }
6483
6484 if ((emulation_type & EMULTYPE_VMWARE) &&
6485 !is_vmware_backdoor_opcode(ctxt))
6486 return EMULATE_FAIL;
6487
6488 if (emulation_type & EMULTYPE_SKIP) {
6489 kvm_rip_write(vcpu, ctxt->_eip);
6490 if (ctxt->eflags & X86_EFLAGS_RF)
6491 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6492 return EMULATE_DONE;
6493 }
6494
6495 if (retry_instruction(ctxt, cr2, emulation_type))
6496 return EMULATE_DONE;
6497
6498 /* this is needed for vmware backdoor interface to work since it
6499 changes registers values during IO operation */
6500 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6501 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6502 emulator_invalidate_register_cache(ctxt);
6503 }
6504
6505 restart:
6506 /* Save the faulting GPA (cr2) in the address field */
6507 ctxt->exception.address = cr2;
6508
6509 r = x86_emulate_insn(ctxt);
6510
6511 if (r == EMULATION_INTERCEPTED)
6512 return EMULATE_DONE;
6513
6514 if (r == EMULATION_FAILED) {
6515 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6516 emulation_type))
6517 return EMULATE_DONE;
6518
6519 return handle_emulation_failure(vcpu, emulation_type);
6520 }
6521
6522 if (ctxt->have_exception) {
6523 r = EMULATE_DONE;
6524 if (inject_emulated_exception(vcpu))
6525 return r;
6526 } else if (vcpu->arch.pio.count) {
6527 if (!vcpu->arch.pio.in) {
6528 /* FIXME: return into emulator if single-stepping. */
6529 vcpu->arch.pio.count = 0;
6530 } else {
6531 writeback = false;
6532 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6533 }
6534 r = EMULATE_USER_EXIT;
6535 } else if (vcpu->mmio_needed) {
6536 if (!vcpu->mmio_is_write)
6537 writeback = false;
6538 r = EMULATE_USER_EXIT;
6539 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6540 } else if (r == EMULATION_RESTART)
6541 goto restart;
6542 else
6543 r = EMULATE_DONE;
6544
6545 if (writeback) {
6546 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6547 toggle_interruptibility(vcpu, ctxt->interruptibility);
6548 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6549 kvm_rip_write(vcpu, ctxt->eip);
6550 if (r == EMULATE_DONE && ctxt->tf)
6551 kvm_vcpu_do_singlestep(vcpu, &r);
6552 if (!ctxt->have_exception ||
6553 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6554 __kvm_set_rflags(vcpu, ctxt->eflags);
6555
6556 /*
6557 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6558 * do nothing, and it will be requested again as soon as
6559 * the shadow expires. But we still need to check here,
6560 * because POPF has no interrupt shadow.
6561 */
6562 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6563 kvm_make_request(KVM_REQ_EVENT, vcpu);
6564 } else
6565 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6566
6567 return r;
6568 }
6569
6570 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6571 {
6572 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6573 }
6574 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6575
6576 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6577 void *insn, int insn_len)
6578 {
6579 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6580 }
6581 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6582
6583 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6584 {
6585 vcpu->arch.pio.count = 0;
6586 return 1;
6587 }
6588
6589 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6590 {
6591 vcpu->arch.pio.count = 0;
6592
6593 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6594 return 1;
6595
6596 return kvm_skip_emulated_instruction(vcpu);
6597 }
6598
6599 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6600 unsigned short port)
6601 {
6602 unsigned long val = kvm_rax_read(vcpu);
6603 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6604 size, port, &val, 1);
6605 if (ret)
6606 return ret;
6607
6608 /*
6609 * Workaround userspace that relies on old KVM behavior of %rip being
6610 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6611 */
6612 if (port == 0x7e &&
6613 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6614 vcpu->arch.complete_userspace_io =
6615 complete_fast_pio_out_port_0x7e;
6616 kvm_skip_emulated_instruction(vcpu);
6617 } else {
6618 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6619 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6620 }
6621 return 0;
6622 }
6623
6624 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6625 {
6626 unsigned long val;
6627
6628 /* We should only ever be called with arch.pio.count equal to 1 */
6629 BUG_ON(vcpu->arch.pio.count != 1);
6630
6631 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6632 vcpu->arch.pio.count = 0;
6633 return 1;
6634 }
6635
6636 /* For size less than 4 we merge, else we zero extend */
6637 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6638
6639 /*
6640 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6641 * the copy and tracing
6642 */
6643 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6644 vcpu->arch.pio.port, &val, 1);
6645 kvm_rax_write(vcpu, val);
6646
6647 return kvm_skip_emulated_instruction(vcpu);
6648 }
6649
6650 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6651 unsigned short port)
6652 {
6653 unsigned long val;
6654 int ret;
6655
6656 /* For size less than 4 we merge, else we zero extend */
6657 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6658
6659 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6660 &val, 1);
6661 if (ret) {
6662 kvm_rax_write(vcpu, val);
6663 return ret;
6664 }
6665
6666 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6667 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6668
6669 return 0;
6670 }
6671
6672 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6673 {
6674 int ret;
6675
6676 if (in)
6677 ret = kvm_fast_pio_in(vcpu, size, port);
6678 else
6679 ret = kvm_fast_pio_out(vcpu, size, port);
6680 return ret && kvm_skip_emulated_instruction(vcpu);
6681 }
6682 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6683
6684 static int kvmclock_cpu_down_prep(unsigned int cpu)
6685 {
6686 __this_cpu_write(cpu_tsc_khz, 0);
6687 return 0;
6688 }
6689
6690 static void tsc_khz_changed(void *data)
6691 {
6692 struct cpufreq_freqs *freq = data;
6693 unsigned long khz = 0;
6694
6695 if (data)
6696 khz = freq->new;
6697 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6698 khz = cpufreq_quick_get(raw_smp_processor_id());
6699 if (!khz)
6700 khz = tsc_khz;
6701 __this_cpu_write(cpu_tsc_khz, khz);
6702 }
6703
6704 #ifdef CONFIG_X86_64
6705 static void kvm_hyperv_tsc_notifier(void)
6706 {
6707 struct kvm *kvm;
6708 struct kvm_vcpu *vcpu;
6709 int cpu;
6710
6711 spin_lock(&kvm_lock);
6712 list_for_each_entry(kvm, &vm_list, vm_list)
6713 kvm_make_mclock_inprogress_request(kvm);
6714
6715 hyperv_stop_tsc_emulation();
6716
6717 /* TSC frequency always matches when on Hyper-V */
6718 for_each_present_cpu(cpu)
6719 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6720 kvm_max_guest_tsc_khz = tsc_khz;
6721
6722 list_for_each_entry(kvm, &vm_list, vm_list) {
6723 struct kvm_arch *ka = &kvm->arch;
6724
6725 spin_lock(&ka->pvclock_gtod_sync_lock);
6726
6727 pvclock_update_vm_gtod_copy(kvm);
6728
6729 kvm_for_each_vcpu(cpu, vcpu, kvm)
6730 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6731
6732 kvm_for_each_vcpu(cpu, vcpu, kvm)
6733 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6734
6735 spin_unlock(&ka->pvclock_gtod_sync_lock);
6736 }
6737 spin_unlock(&kvm_lock);
6738 }
6739 #endif
6740
6741 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6742 {
6743 struct kvm *kvm;
6744 struct kvm_vcpu *vcpu;
6745 int i, send_ipi = 0;
6746
6747 /*
6748 * We allow guests to temporarily run on slowing clocks,
6749 * provided we notify them after, or to run on accelerating
6750 * clocks, provided we notify them before. Thus time never
6751 * goes backwards.
6752 *
6753 * However, we have a problem. We can't atomically update
6754 * the frequency of a given CPU from this function; it is
6755 * merely a notifier, which can be called from any CPU.
6756 * Changing the TSC frequency at arbitrary points in time
6757 * requires a recomputation of local variables related to
6758 * the TSC for each VCPU. We must flag these local variables
6759 * to be updated and be sure the update takes place with the
6760 * new frequency before any guests proceed.
6761 *
6762 * Unfortunately, the combination of hotplug CPU and frequency
6763 * change creates an intractable locking scenario; the order
6764 * of when these callouts happen is undefined with respect to
6765 * CPU hotplug, and they can race with each other. As such,
6766 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6767 * undefined; you can actually have a CPU frequency change take
6768 * place in between the computation of X and the setting of the
6769 * variable. To protect against this problem, all updates of
6770 * the per_cpu tsc_khz variable are done in an interrupt
6771 * protected IPI, and all callers wishing to update the value
6772 * must wait for a synchronous IPI to complete (which is trivial
6773 * if the caller is on the CPU already). This establishes the
6774 * necessary total order on variable updates.
6775 *
6776 * Note that because a guest time update may take place
6777 * anytime after the setting of the VCPU's request bit, the
6778 * correct TSC value must be set before the request. However,
6779 * to ensure the update actually makes it to any guest which
6780 * starts running in hardware virtualization between the set
6781 * and the acquisition of the spinlock, we must also ping the
6782 * CPU after setting the request bit.
6783 *
6784 */
6785
6786 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6787
6788 spin_lock(&kvm_lock);
6789 list_for_each_entry(kvm, &vm_list, vm_list) {
6790 kvm_for_each_vcpu(i, vcpu, kvm) {
6791 if (vcpu->cpu != cpu)
6792 continue;
6793 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6794 if (vcpu->cpu != smp_processor_id())
6795 send_ipi = 1;
6796 }
6797 }
6798 spin_unlock(&kvm_lock);
6799
6800 if (freq->old < freq->new && send_ipi) {
6801 /*
6802 * We upscale the frequency. Must make the guest
6803 * doesn't see old kvmclock values while running with
6804 * the new frequency, otherwise we risk the guest sees
6805 * time go backwards.
6806 *
6807 * In case we update the frequency for another cpu
6808 * (which might be in guest context) send an interrupt
6809 * to kick the cpu out of guest context. Next time
6810 * guest context is entered kvmclock will be updated,
6811 * so the guest will not see stale values.
6812 */
6813 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6814 }
6815 }
6816
6817 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6818 void *data)
6819 {
6820 struct cpufreq_freqs *freq = data;
6821 int cpu;
6822
6823 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6824 return 0;
6825 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6826 return 0;
6827
6828 for_each_cpu(cpu, freq->policy->cpus)
6829 __kvmclock_cpufreq_notifier(freq, cpu);
6830
6831 return 0;
6832 }
6833
6834 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6835 .notifier_call = kvmclock_cpufreq_notifier
6836 };
6837
6838 static int kvmclock_cpu_online(unsigned int cpu)
6839 {
6840 tsc_khz_changed(NULL);
6841 return 0;
6842 }
6843
6844 static void kvm_timer_init(void)
6845 {
6846 max_tsc_khz = tsc_khz;
6847
6848 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6849 #ifdef CONFIG_CPU_FREQ
6850 struct cpufreq_policy policy;
6851 int cpu;
6852
6853 memset(&policy, 0, sizeof(policy));
6854 cpu = get_cpu();
6855 cpufreq_get_policy(&policy, cpu);
6856 if (policy.cpuinfo.max_freq)
6857 max_tsc_khz = policy.cpuinfo.max_freq;
6858 put_cpu();
6859 #endif
6860 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6861 CPUFREQ_TRANSITION_NOTIFIER);
6862 }
6863 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6864
6865 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6866 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6867 }
6868
6869 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6870 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6871
6872 int kvm_is_in_guest(void)
6873 {
6874 return __this_cpu_read(current_vcpu) != NULL;
6875 }
6876
6877 static int kvm_is_user_mode(void)
6878 {
6879 int user_mode = 3;
6880
6881 if (__this_cpu_read(current_vcpu))
6882 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6883
6884 return user_mode != 0;
6885 }
6886
6887 static unsigned long kvm_get_guest_ip(void)
6888 {
6889 unsigned long ip = 0;
6890
6891 if (__this_cpu_read(current_vcpu))
6892 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6893
6894 return ip;
6895 }
6896
6897 static void kvm_handle_intel_pt_intr(void)
6898 {
6899 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6900
6901 kvm_make_request(KVM_REQ_PMI, vcpu);
6902 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6903 (unsigned long *)&vcpu->arch.pmu.global_status);
6904 }
6905
6906 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6907 .is_in_guest = kvm_is_in_guest,
6908 .is_user_mode = kvm_is_user_mode,
6909 .get_guest_ip = kvm_get_guest_ip,
6910 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
6911 };
6912
6913 static void kvm_set_mmio_spte_mask(void)
6914 {
6915 u64 mask;
6916 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6917
6918 /*
6919 * Set the reserved bits and the present bit of an paging-structure
6920 * entry to generate page fault with PFER.RSV = 1.
6921 */
6922
6923 /*
6924 * Mask the uppermost physical address bit, which would be reserved as
6925 * long as the supported physical address width is less than 52.
6926 */
6927 mask = 1ull << 51;
6928
6929 /* Set the present bit. */
6930 mask |= 1ull;
6931
6932 /*
6933 * If reserved bit is not supported, clear the present bit to disable
6934 * mmio page fault.
6935 */
6936 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
6937 mask &= ~1ull;
6938
6939 kvm_mmu_set_mmio_spte_mask(mask, mask);
6940 }
6941
6942 #ifdef CONFIG_X86_64
6943 static void pvclock_gtod_update_fn(struct work_struct *work)
6944 {
6945 struct kvm *kvm;
6946
6947 struct kvm_vcpu *vcpu;
6948 int i;
6949
6950 spin_lock(&kvm_lock);
6951 list_for_each_entry(kvm, &vm_list, vm_list)
6952 kvm_for_each_vcpu(i, vcpu, kvm)
6953 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6954 atomic_set(&kvm_guest_has_master_clock, 0);
6955 spin_unlock(&kvm_lock);
6956 }
6957
6958 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6959
6960 /*
6961 * Notification about pvclock gtod data update.
6962 */
6963 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6964 void *priv)
6965 {
6966 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6967 struct timekeeper *tk = priv;
6968
6969 update_pvclock_gtod(tk);
6970
6971 /* disable master clock if host does not trust, or does not
6972 * use, TSC based clocksource.
6973 */
6974 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6975 atomic_read(&kvm_guest_has_master_clock) != 0)
6976 queue_work(system_long_wq, &pvclock_gtod_work);
6977
6978 return 0;
6979 }
6980
6981 static struct notifier_block pvclock_gtod_notifier = {
6982 .notifier_call = pvclock_gtod_notify,
6983 };
6984 #endif
6985
6986 int kvm_arch_init(void *opaque)
6987 {
6988 int r;
6989 struct kvm_x86_ops *ops = opaque;
6990
6991 if (kvm_x86_ops) {
6992 printk(KERN_ERR "kvm: already loaded the other module\n");
6993 r = -EEXIST;
6994 goto out;
6995 }
6996
6997 if (!ops->cpu_has_kvm_support()) {
6998 printk(KERN_ERR "kvm: no hardware support\n");
6999 r = -EOPNOTSUPP;
7000 goto out;
7001 }
7002 if (ops->disabled_by_bios()) {
7003 printk(KERN_ERR "kvm: disabled by bios\n");
7004 r = -EOPNOTSUPP;
7005 goto out;
7006 }
7007
7008 /*
7009 * KVM explicitly assumes that the guest has an FPU and
7010 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7011 * vCPU's FPU state as a fxregs_state struct.
7012 */
7013 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7014 printk(KERN_ERR "kvm: inadequate fpu\n");
7015 r = -EOPNOTSUPP;
7016 goto out;
7017 }
7018
7019 r = -ENOMEM;
7020 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7021 __alignof__(struct fpu), SLAB_ACCOUNT,
7022 NULL);
7023 if (!x86_fpu_cache) {
7024 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7025 goto out;
7026 }
7027
7028 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7029 if (!shared_msrs) {
7030 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7031 goto out_free_x86_fpu_cache;
7032 }
7033
7034 r = kvm_mmu_module_init();
7035 if (r)
7036 goto out_free_percpu;
7037
7038 kvm_set_mmio_spte_mask();
7039
7040 kvm_x86_ops = ops;
7041
7042 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7043 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7044 PT_PRESENT_MASK, 0, sme_me_mask);
7045 kvm_timer_init();
7046
7047 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7048
7049 if (boot_cpu_has(X86_FEATURE_XSAVE))
7050 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7051
7052 kvm_lapic_init();
7053 #ifdef CONFIG_X86_64
7054 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7055
7056 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7057 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7058 #endif
7059
7060 return 0;
7061
7062 out_free_percpu:
7063 free_percpu(shared_msrs);
7064 out_free_x86_fpu_cache:
7065 kmem_cache_destroy(x86_fpu_cache);
7066 out:
7067 return r;
7068 }
7069
7070 void kvm_arch_exit(void)
7071 {
7072 #ifdef CONFIG_X86_64
7073 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7074 clear_hv_tscchange_cb();
7075 #endif
7076 kvm_lapic_exit();
7077 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7078
7079 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7080 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7081 CPUFREQ_TRANSITION_NOTIFIER);
7082 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7083 #ifdef CONFIG_X86_64
7084 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7085 #endif
7086 kvm_x86_ops = NULL;
7087 kvm_mmu_module_exit();
7088 free_percpu(shared_msrs);
7089 kmem_cache_destroy(x86_fpu_cache);
7090 }
7091
7092 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7093 {
7094 ++vcpu->stat.halt_exits;
7095 if (lapic_in_kernel(vcpu)) {
7096 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7097 return 1;
7098 } else {
7099 vcpu->run->exit_reason = KVM_EXIT_HLT;
7100 return 0;
7101 }
7102 }
7103 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7104
7105 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7106 {
7107 int ret = kvm_skip_emulated_instruction(vcpu);
7108 /*
7109 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7110 * KVM_EXIT_DEBUG here.
7111 */
7112 return kvm_vcpu_halt(vcpu) && ret;
7113 }
7114 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7115
7116 #ifdef CONFIG_X86_64
7117 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7118 unsigned long clock_type)
7119 {
7120 struct kvm_clock_pairing clock_pairing;
7121 struct timespec64 ts;
7122 u64 cycle;
7123 int ret;
7124
7125 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7126 return -KVM_EOPNOTSUPP;
7127
7128 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7129 return -KVM_EOPNOTSUPP;
7130
7131 clock_pairing.sec = ts.tv_sec;
7132 clock_pairing.nsec = ts.tv_nsec;
7133 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7134 clock_pairing.flags = 0;
7135 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7136
7137 ret = 0;
7138 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7139 sizeof(struct kvm_clock_pairing)))
7140 ret = -KVM_EFAULT;
7141
7142 return ret;
7143 }
7144 #endif
7145
7146 /*
7147 * kvm_pv_kick_cpu_op: Kick a vcpu.
7148 *
7149 * @apicid - apicid of vcpu to be kicked.
7150 */
7151 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7152 {
7153 struct kvm_lapic_irq lapic_irq;
7154
7155 lapic_irq.shorthand = 0;
7156 lapic_irq.dest_mode = 0;
7157 lapic_irq.level = 0;
7158 lapic_irq.dest_id = apicid;
7159 lapic_irq.msi_redir_hint = false;
7160
7161 lapic_irq.delivery_mode = APIC_DM_REMRD;
7162 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7163 }
7164
7165 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7166 {
7167 if (!lapic_in_kernel(vcpu)) {
7168 WARN_ON_ONCE(vcpu->arch.apicv_active);
7169 return;
7170 }
7171 if (!vcpu->arch.apicv_active)
7172 return;
7173
7174 vcpu->arch.apicv_active = false;
7175 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7176 }
7177
7178 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7179 {
7180 unsigned long nr, a0, a1, a2, a3, ret;
7181 int op_64_bit;
7182
7183 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7184 return kvm_hv_hypercall(vcpu);
7185
7186 nr = kvm_rax_read(vcpu);
7187 a0 = kvm_rbx_read(vcpu);
7188 a1 = kvm_rcx_read(vcpu);
7189 a2 = kvm_rdx_read(vcpu);
7190 a3 = kvm_rsi_read(vcpu);
7191
7192 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7193
7194 op_64_bit = is_64_bit_mode(vcpu);
7195 if (!op_64_bit) {
7196 nr &= 0xFFFFFFFF;
7197 a0 &= 0xFFFFFFFF;
7198 a1 &= 0xFFFFFFFF;
7199 a2 &= 0xFFFFFFFF;
7200 a3 &= 0xFFFFFFFF;
7201 }
7202
7203 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7204 ret = -KVM_EPERM;
7205 goto out;
7206 }
7207
7208 switch (nr) {
7209 case KVM_HC_VAPIC_POLL_IRQ:
7210 ret = 0;
7211 break;
7212 case KVM_HC_KICK_CPU:
7213 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7214 ret = 0;
7215 break;
7216 #ifdef CONFIG_X86_64
7217 case KVM_HC_CLOCK_PAIRING:
7218 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7219 break;
7220 #endif
7221 case KVM_HC_SEND_IPI:
7222 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7223 break;
7224 default:
7225 ret = -KVM_ENOSYS;
7226 break;
7227 }
7228 out:
7229 if (!op_64_bit)
7230 ret = (u32)ret;
7231 kvm_rax_write(vcpu, ret);
7232
7233 ++vcpu->stat.hypercalls;
7234 return kvm_skip_emulated_instruction(vcpu);
7235 }
7236 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7237
7238 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7239 {
7240 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7241 char instruction[3];
7242 unsigned long rip = kvm_rip_read(vcpu);
7243
7244 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7245
7246 return emulator_write_emulated(ctxt, rip, instruction, 3,
7247 &ctxt->exception);
7248 }
7249
7250 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7251 {
7252 return vcpu->run->request_interrupt_window &&
7253 likely(!pic_in_kernel(vcpu->kvm));
7254 }
7255
7256 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7257 {
7258 struct kvm_run *kvm_run = vcpu->run;
7259
7260 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7261 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7262 kvm_run->cr8 = kvm_get_cr8(vcpu);
7263 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7264 kvm_run->ready_for_interrupt_injection =
7265 pic_in_kernel(vcpu->kvm) ||
7266 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7267 }
7268
7269 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7270 {
7271 int max_irr, tpr;
7272
7273 if (!kvm_x86_ops->update_cr8_intercept)
7274 return;
7275
7276 if (!lapic_in_kernel(vcpu))
7277 return;
7278
7279 if (vcpu->arch.apicv_active)
7280 return;
7281
7282 if (!vcpu->arch.apic->vapic_addr)
7283 max_irr = kvm_lapic_find_highest_irr(vcpu);
7284 else
7285 max_irr = -1;
7286
7287 if (max_irr != -1)
7288 max_irr >>= 4;
7289
7290 tpr = kvm_lapic_get_cr8(vcpu);
7291
7292 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7293 }
7294
7295 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7296 {
7297 int r;
7298
7299 /* try to reinject previous events if any */
7300
7301 if (vcpu->arch.exception.injected)
7302 kvm_x86_ops->queue_exception(vcpu);
7303 /*
7304 * Do not inject an NMI or interrupt if there is a pending
7305 * exception. Exceptions and interrupts are recognized at
7306 * instruction boundaries, i.e. the start of an instruction.
7307 * Trap-like exceptions, e.g. #DB, have higher priority than
7308 * NMIs and interrupts, i.e. traps are recognized before an
7309 * NMI/interrupt that's pending on the same instruction.
7310 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7311 * priority, but are only generated (pended) during instruction
7312 * execution, i.e. a pending fault-like exception means the
7313 * fault occurred on the *previous* instruction and must be
7314 * serviced prior to recognizing any new events in order to
7315 * fully complete the previous instruction.
7316 */
7317 else if (!vcpu->arch.exception.pending) {
7318 if (vcpu->arch.nmi_injected)
7319 kvm_x86_ops->set_nmi(vcpu);
7320 else if (vcpu->arch.interrupt.injected)
7321 kvm_x86_ops->set_irq(vcpu);
7322 }
7323
7324 /*
7325 * Call check_nested_events() even if we reinjected a previous event
7326 * in order for caller to determine if it should require immediate-exit
7327 * from L2 to L1 due to pending L1 events which require exit
7328 * from L2 to L1.
7329 */
7330 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7331 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7332 if (r != 0)
7333 return r;
7334 }
7335
7336 /* try to inject new event if pending */
7337 if (vcpu->arch.exception.pending) {
7338 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7339 vcpu->arch.exception.has_error_code,
7340 vcpu->arch.exception.error_code);
7341
7342 WARN_ON_ONCE(vcpu->arch.exception.injected);
7343 vcpu->arch.exception.pending = false;
7344 vcpu->arch.exception.injected = true;
7345
7346 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7347 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7348 X86_EFLAGS_RF);
7349
7350 if (vcpu->arch.exception.nr == DB_VECTOR) {
7351 /*
7352 * This code assumes that nSVM doesn't use
7353 * check_nested_events(). If it does, the
7354 * DR6/DR7 changes should happen before L1
7355 * gets a #VMEXIT for an intercepted #DB in
7356 * L2. (Under VMX, on the other hand, the
7357 * DR6/DR7 changes should not happen in the
7358 * event of a VM-exit to L1 for an intercepted
7359 * #DB in L2.)
7360 */
7361 kvm_deliver_exception_payload(vcpu);
7362 if (vcpu->arch.dr7 & DR7_GD) {
7363 vcpu->arch.dr7 &= ~DR7_GD;
7364 kvm_update_dr7(vcpu);
7365 }
7366 }
7367
7368 kvm_x86_ops->queue_exception(vcpu);
7369 }
7370
7371 /* Don't consider new event if we re-injected an event */
7372 if (kvm_event_needs_reinjection(vcpu))
7373 return 0;
7374
7375 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7376 kvm_x86_ops->smi_allowed(vcpu)) {
7377 vcpu->arch.smi_pending = false;
7378 ++vcpu->arch.smi_count;
7379 enter_smm(vcpu);
7380 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7381 --vcpu->arch.nmi_pending;
7382 vcpu->arch.nmi_injected = true;
7383 kvm_x86_ops->set_nmi(vcpu);
7384 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7385 /*
7386 * Because interrupts can be injected asynchronously, we are
7387 * calling check_nested_events again here to avoid a race condition.
7388 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7389 * proposal and current concerns. Perhaps we should be setting
7390 * KVM_REQ_EVENT only on certain events and not unconditionally?
7391 */
7392 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7393 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7394 if (r != 0)
7395 return r;
7396 }
7397 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7398 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7399 false);
7400 kvm_x86_ops->set_irq(vcpu);
7401 }
7402 }
7403
7404 return 0;
7405 }
7406
7407 static void process_nmi(struct kvm_vcpu *vcpu)
7408 {
7409 unsigned limit = 2;
7410
7411 /*
7412 * x86 is limited to one NMI running, and one NMI pending after it.
7413 * If an NMI is already in progress, limit further NMIs to just one.
7414 * Otherwise, allow two (and we'll inject the first one immediately).
7415 */
7416 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7417 limit = 1;
7418
7419 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7420 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7421 kvm_make_request(KVM_REQ_EVENT, vcpu);
7422 }
7423
7424 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7425 {
7426 u32 flags = 0;
7427 flags |= seg->g << 23;
7428 flags |= seg->db << 22;
7429 flags |= seg->l << 21;
7430 flags |= seg->avl << 20;
7431 flags |= seg->present << 15;
7432 flags |= seg->dpl << 13;
7433 flags |= seg->s << 12;
7434 flags |= seg->type << 8;
7435 return flags;
7436 }
7437
7438 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7439 {
7440 struct kvm_segment seg;
7441 int offset;
7442
7443 kvm_get_segment(vcpu, &seg, n);
7444 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7445
7446 if (n < 3)
7447 offset = 0x7f84 + n * 12;
7448 else
7449 offset = 0x7f2c + (n - 3) * 12;
7450
7451 put_smstate(u32, buf, offset + 8, seg.base);
7452 put_smstate(u32, buf, offset + 4, seg.limit);
7453 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7454 }
7455
7456 #ifdef CONFIG_X86_64
7457 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7458 {
7459 struct kvm_segment seg;
7460 int offset;
7461 u16 flags;
7462
7463 kvm_get_segment(vcpu, &seg, n);
7464 offset = 0x7e00 + n * 16;
7465
7466 flags = enter_smm_get_segment_flags(&seg) >> 8;
7467 put_smstate(u16, buf, offset, seg.selector);
7468 put_smstate(u16, buf, offset + 2, flags);
7469 put_smstate(u32, buf, offset + 4, seg.limit);
7470 put_smstate(u64, buf, offset + 8, seg.base);
7471 }
7472 #endif
7473
7474 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7475 {
7476 struct desc_ptr dt;
7477 struct kvm_segment seg;
7478 unsigned long val;
7479 int i;
7480
7481 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7482 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7483 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7484 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7485
7486 for (i = 0; i < 8; i++)
7487 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7488
7489 kvm_get_dr(vcpu, 6, &val);
7490 put_smstate(u32, buf, 0x7fcc, (u32)val);
7491 kvm_get_dr(vcpu, 7, &val);
7492 put_smstate(u32, buf, 0x7fc8, (u32)val);
7493
7494 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7495 put_smstate(u32, buf, 0x7fc4, seg.selector);
7496 put_smstate(u32, buf, 0x7f64, seg.base);
7497 put_smstate(u32, buf, 0x7f60, seg.limit);
7498 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7499
7500 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7501 put_smstate(u32, buf, 0x7fc0, seg.selector);
7502 put_smstate(u32, buf, 0x7f80, seg.base);
7503 put_smstate(u32, buf, 0x7f7c, seg.limit);
7504 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7505
7506 kvm_x86_ops->get_gdt(vcpu, &dt);
7507 put_smstate(u32, buf, 0x7f74, dt.address);
7508 put_smstate(u32, buf, 0x7f70, dt.size);
7509
7510 kvm_x86_ops->get_idt(vcpu, &dt);
7511 put_smstate(u32, buf, 0x7f58, dt.address);
7512 put_smstate(u32, buf, 0x7f54, dt.size);
7513
7514 for (i = 0; i < 6; i++)
7515 enter_smm_save_seg_32(vcpu, buf, i);
7516
7517 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7518
7519 /* revision id */
7520 put_smstate(u32, buf, 0x7efc, 0x00020000);
7521 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7522 }
7523
7524 #ifdef CONFIG_X86_64
7525 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7526 {
7527 struct desc_ptr dt;
7528 struct kvm_segment seg;
7529 unsigned long val;
7530 int i;
7531
7532 for (i = 0; i < 16; i++)
7533 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7534
7535 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7536 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7537
7538 kvm_get_dr(vcpu, 6, &val);
7539 put_smstate(u64, buf, 0x7f68, val);
7540 kvm_get_dr(vcpu, 7, &val);
7541 put_smstate(u64, buf, 0x7f60, val);
7542
7543 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7544 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7545 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7546
7547 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7548
7549 /* revision id */
7550 put_smstate(u32, buf, 0x7efc, 0x00020064);
7551
7552 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7553
7554 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7555 put_smstate(u16, buf, 0x7e90, seg.selector);
7556 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7557 put_smstate(u32, buf, 0x7e94, seg.limit);
7558 put_smstate(u64, buf, 0x7e98, seg.base);
7559
7560 kvm_x86_ops->get_idt(vcpu, &dt);
7561 put_smstate(u32, buf, 0x7e84, dt.size);
7562 put_smstate(u64, buf, 0x7e88, dt.address);
7563
7564 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7565 put_smstate(u16, buf, 0x7e70, seg.selector);
7566 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7567 put_smstate(u32, buf, 0x7e74, seg.limit);
7568 put_smstate(u64, buf, 0x7e78, seg.base);
7569
7570 kvm_x86_ops->get_gdt(vcpu, &dt);
7571 put_smstate(u32, buf, 0x7e64, dt.size);
7572 put_smstate(u64, buf, 0x7e68, dt.address);
7573
7574 for (i = 0; i < 6; i++)
7575 enter_smm_save_seg_64(vcpu, buf, i);
7576 }
7577 #endif
7578
7579 static void enter_smm(struct kvm_vcpu *vcpu)
7580 {
7581 struct kvm_segment cs, ds;
7582 struct desc_ptr dt;
7583 char buf[512];
7584 u32 cr0;
7585
7586 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7587 memset(buf, 0, 512);
7588 #ifdef CONFIG_X86_64
7589 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7590 enter_smm_save_state_64(vcpu, buf);
7591 else
7592 #endif
7593 enter_smm_save_state_32(vcpu, buf);
7594
7595 /*
7596 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7597 * vCPU state (e.g. leave guest mode) after we've saved the state into
7598 * the SMM state-save area.
7599 */
7600 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7601
7602 vcpu->arch.hflags |= HF_SMM_MASK;
7603 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7604
7605 if (kvm_x86_ops->get_nmi_mask(vcpu))
7606 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7607 else
7608 kvm_x86_ops->set_nmi_mask(vcpu, true);
7609
7610 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7611 kvm_rip_write(vcpu, 0x8000);
7612
7613 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7614 kvm_x86_ops->set_cr0(vcpu, cr0);
7615 vcpu->arch.cr0 = cr0;
7616
7617 kvm_x86_ops->set_cr4(vcpu, 0);
7618
7619 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7620 dt.address = dt.size = 0;
7621 kvm_x86_ops->set_idt(vcpu, &dt);
7622
7623 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7624
7625 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7626 cs.base = vcpu->arch.smbase;
7627
7628 ds.selector = 0;
7629 ds.base = 0;
7630
7631 cs.limit = ds.limit = 0xffffffff;
7632 cs.type = ds.type = 0x3;
7633 cs.dpl = ds.dpl = 0;
7634 cs.db = ds.db = 0;
7635 cs.s = ds.s = 1;
7636 cs.l = ds.l = 0;
7637 cs.g = ds.g = 1;
7638 cs.avl = ds.avl = 0;
7639 cs.present = ds.present = 1;
7640 cs.unusable = ds.unusable = 0;
7641 cs.padding = ds.padding = 0;
7642
7643 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7644 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7645 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7646 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7647 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7648 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7649
7650 #ifdef CONFIG_X86_64
7651 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7652 kvm_x86_ops->set_efer(vcpu, 0);
7653 #endif
7654
7655 kvm_update_cpuid(vcpu);
7656 kvm_mmu_reset_context(vcpu);
7657 }
7658
7659 static void process_smi(struct kvm_vcpu *vcpu)
7660 {
7661 vcpu->arch.smi_pending = true;
7662 kvm_make_request(KVM_REQ_EVENT, vcpu);
7663 }
7664
7665 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7666 {
7667 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7668 }
7669
7670 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7671 {
7672 if (!kvm_apic_present(vcpu))
7673 return;
7674
7675 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7676
7677 if (irqchip_split(vcpu->kvm))
7678 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7679 else {
7680 if (vcpu->arch.apicv_active)
7681 kvm_x86_ops->sync_pir_to_irr(vcpu);
7682 if (ioapic_in_kernel(vcpu->kvm))
7683 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7684 }
7685
7686 if (is_guest_mode(vcpu))
7687 vcpu->arch.load_eoi_exitmap_pending = true;
7688 else
7689 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7690 }
7691
7692 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7693 {
7694 u64 eoi_exit_bitmap[4];
7695
7696 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7697 return;
7698
7699 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7700 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7701 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7702 }
7703
7704 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7705 unsigned long start, unsigned long end,
7706 bool blockable)
7707 {
7708 unsigned long apic_address;
7709
7710 /*
7711 * The physical address of apic access page is stored in the VMCS.
7712 * Update it when it becomes invalid.
7713 */
7714 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7715 if (start <= apic_address && apic_address < end)
7716 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7717
7718 return 0;
7719 }
7720
7721 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7722 {
7723 struct page *page = NULL;
7724
7725 if (!lapic_in_kernel(vcpu))
7726 return;
7727
7728 if (!kvm_x86_ops->set_apic_access_page_addr)
7729 return;
7730
7731 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7732 if (is_error_page(page))
7733 return;
7734 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7735
7736 /*
7737 * Do not pin apic access page in memory, the MMU notifier
7738 * will call us again if it is migrated or swapped out.
7739 */
7740 put_page(page);
7741 }
7742 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7743
7744 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7745 {
7746 smp_send_reschedule(vcpu->cpu);
7747 }
7748 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7749
7750 /*
7751 * Returns 1 to let vcpu_run() continue the guest execution loop without
7752 * exiting to the userspace. Otherwise, the value will be returned to the
7753 * userspace.
7754 */
7755 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7756 {
7757 int r;
7758 bool req_int_win =
7759 dm_request_for_irq_injection(vcpu) &&
7760 kvm_cpu_accept_dm_intr(vcpu);
7761
7762 bool req_immediate_exit = false;
7763
7764 if (kvm_request_pending(vcpu)) {
7765 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7766 kvm_x86_ops->get_vmcs12_pages(vcpu);
7767 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7768 kvm_mmu_unload(vcpu);
7769 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7770 __kvm_migrate_timers(vcpu);
7771 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7772 kvm_gen_update_masterclock(vcpu->kvm);
7773 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7774 kvm_gen_kvmclock_update(vcpu);
7775 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7776 r = kvm_guest_time_update(vcpu);
7777 if (unlikely(r))
7778 goto out;
7779 }
7780 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7781 kvm_mmu_sync_roots(vcpu);
7782 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7783 kvm_mmu_load_cr3(vcpu);
7784 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7785 kvm_vcpu_flush_tlb(vcpu, true);
7786 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7787 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7788 r = 0;
7789 goto out;
7790 }
7791 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7792 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7793 vcpu->mmio_needed = 0;
7794 r = 0;
7795 goto out;
7796 }
7797 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7798 /* Page is swapped out. Do synthetic halt */
7799 vcpu->arch.apf.halted = true;
7800 r = 1;
7801 goto out;
7802 }
7803 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7804 record_steal_time(vcpu);
7805 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7806 process_smi(vcpu);
7807 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7808 process_nmi(vcpu);
7809 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7810 kvm_pmu_handle_event(vcpu);
7811 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7812 kvm_pmu_deliver_pmi(vcpu);
7813 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7814 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7815 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7816 vcpu->arch.ioapic_handled_vectors)) {
7817 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7818 vcpu->run->eoi.vector =
7819 vcpu->arch.pending_ioapic_eoi;
7820 r = 0;
7821 goto out;
7822 }
7823 }
7824 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7825 vcpu_scan_ioapic(vcpu);
7826 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7827 vcpu_load_eoi_exitmap(vcpu);
7828 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7829 kvm_vcpu_reload_apic_access_page(vcpu);
7830 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7831 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7832 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7833 r = 0;
7834 goto out;
7835 }
7836 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7837 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7838 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7839 r = 0;
7840 goto out;
7841 }
7842 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7843 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7844 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7845 r = 0;
7846 goto out;
7847 }
7848
7849 /*
7850 * KVM_REQ_HV_STIMER has to be processed after
7851 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7852 * depend on the guest clock being up-to-date
7853 */
7854 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7855 kvm_hv_process_stimers(vcpu);
7856 }
7857
7858 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7859 ++vcpu->stat.req_event;
7860 kvm_apic_accept_events(vcpu);
7861 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7862 r = 1;
7863 goto out;
7864 }
7865
7866 if (inject_pending_event(vcpu, req_int_win) != 0)
7867 req_immediate_exit = true;
7868 else {
7869 /* Enable SMI/NMI/IRQ window open exits if needed.
7870 *
7871 * SMIs have three cases:
7872 * 1) They can be nested, and then there is nothing to
7873 * do here because RSM will cause a vmexit anyway.
7874 * 2) There is an ISA-specific reason why SMI cannot be
7875 * injected, and the moment when this changes can be
7876 * intercepted.
7877 * 3) Or the SMI can be pending because
7878 * inject_pending_event has completed the injection
7879 * of an IRQ or NMI from the previous vmexit, and
7880 * then we request an immediate exit to inject the
7881 * SMI.
7882 */
7883 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7884 if (!kvm_x86_ops->enable_smi_window(vcpu))
7885 req_immediate_exit = true;
7886 if (vcpu->arch.nmi_pending)
7887 kvm_x86_ops->enable_nmi_window(vcpu);
7888 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7889 kvm_x86_ops->enable_irq_window(vcpu);
7890 WARN_ON(vcpu->arch.exception.pending);
7891 }
7892
7893 if (kvm_lapic_enabled(vcpu)) {
7894 update_cr8_intercept(vcpu);
7895 kvm_lapic_sync_to_vapic(vcpu);
7896 }
7897 }
7898
7899 r = kvm_mmu_reload(vcpu);
7900 if (unlikely(r)) {
7901 goto cancel_injection;
7902 }
7903
7904 preempt_disable();
7905
7906 kvm_x86_ops->prepare_guest_switch(vcpu);
7907
7908 /*
7909 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7910 * IPI are then delayed after guest entry, which ensures that they
7911 * result in virtual interrupt delivery.
7912 */
7913 local_irq_disable();
7914 vcpu->mode = IN_GUEST_MODE;
7915
7916 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7917
7918 /*
7919 * 1) We should set ->mode before checking ->requests. Please see
7920 * the comment in kvm_vcpu_exiting_guest_mode().
7921 *
7922 * 2) For APICv, we should set ->mode before checking PID.ON. This
7923 * pairs with the memory barrier implicit in pi_test_and_set_on
7924 * (see vmx_deliver_posted_interrupt).
7925 *
7926 * 3) This also orders the write to mode from any reads to the page
7927 * tables done while the VCPU is running. Please see the comment
7928 * in kvm_flush_remote_tlbs.
7929 */
7930 smp_mb__after_srcu_read_unlock();
7931
7932 /*
7933 * This handles the case where a posted interrupt was
7934 * notified with kvm_vcpu_kick.
7935 */
7936 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7937 kvm_x86_ops->sync_pir_to_irr(vcpu);
7938
7939 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7940 || need_resched() || signal_pending(current)) {
7941 vcpu->mode = OUTSIDE_GUEST_MODE;
7942 smp_wmb();
7943 local_irq_enable();
7944 preempt_enable();
7945 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7946 r = 1;
7947 goto cancel_injection;
7948 }
7949
7950 if (req_immediate_exit) {
7951 kvm_make_request(KVM_REQ_EVENT, vcpu);
7952 kvm_x86_ops->request_immediate_exit(vcpu);
7953 }
7954
7955 trace_kvm_entry(vcpu->vcpu_id);
7956 if (lapic_in_kernel(vcpu) &&
7957 vcpu->arch.apic->lapic_timer.timer_advance_ns)
7958 wait_lapic_expire(vcpu);
7959 guest_enter_irqoff();
7960
7961 fpregs_assert_state_consistent();
7962 if (test_thread_flag(TIF_NEED_FPU_LOAD))
7963 switch_fpu_return();
7964
7965 if (unlikely(vcpu->arch.switch_db_regs)) {
7966 set_debugreg(0, 7);
7967 set_debugreg(vcpu->arch.eff_db[0], 0);
7968 set_debugreg(vcpu->arch.eff_db[1], 1);
7969 set_debugreg(vcpu->arch.eff_db[2], 2);
7970 set_debugreg(vcpu->arch.eff_db[3], 3);
7971 set_debugreg(vcpu->arch.dr6, 6);
7972 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7973 }
7974
7975 kvm_x86_ops->run(vcpu);
7976
7977 /*
7978 * Do this here before restoring debug registers on the host. And
7979 * since we do this before handling the vmexit, a DR access vmexit
7980 * can (a) read the correct value of the debug registers, (b) set
7981 * KVM_DEBUGREG_WONT_EXIT again.
7982 */
7983 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7984 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7985 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7986 kvm_update_dr0123(vcpu);
7987 kvm_update_dr6(vcpu);
7988 kvm_update_dr7(vcpu);
7989 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7990 }
7991
7992 /*
7993 * If the guest has used debug registers, at least dr7
7994 * will be disabled while returning to the host.
7995 * If we don't have active breakpoints in the host, we don't
7996 * care about the messed up debug address registers. But if
7997 * we have some of them active, restore the old state.
7998 */
7999 if (hw_breakpoint_active())
8000 hw_breakpoint_restore();
8001
8002 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8003
8004 vcpu->mode = OUTSIDE_GUEST_MODE;
8005 smp_wmb();
8006
8007 kvm_before_interrupt(vcpu);
8008 kvm_x86_ops->handle_external_intr(vcpu);
8009 kvm_after_interrupt(vcpu);
8010
8011 ++vcpu->stat.exits;
8012
8013 guest_exit_irqoff();
8014
8015 local_irq_enable();
8016 preempt_enable();
8017
8018 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8019
8020 /*
8021 * Profile KVM exit RIPs:
8022 */
8023 if (unlikely(prof_on == KVM_PROFILING)) {
8024 unsigned long rip = kvm_rip_read(vcpu);
8025 profile_hit(KVM_PROFILING, (void *)rip);
8026 }
8027
8028 if (unlikely(vcpu->arch.tsc_always_catchup))
8029 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8030
8031 if (vcpu->arch.apic_attention)
8032 kvm_lapic_sync_from_vapic(vcpu);
8033
8034 vcpu->arch.gpa_available = false;
8035 r = kvm_x86_ops->handle_exit(vcpu);
8036 return r;
8037
8038 cancel_injection:
8039 kvm_x86_ops->cancel_injection(vcpu);
8040 if (unlikely(vcpu->arch.apic_attention))
8041 kvm_lapic_sync_from_vapic(vcpu);
8042 out:
8043 return r;
8044 }
8045
8046 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8047 {
8048 if (!kvm_arch_vcpu_runnable(vcpu) &&
8049 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8050 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8051 kvm_vcpu_block(vcpu);
8052 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8053
8054 if (kvm_x86_ops->post_block)
8055 kvm_x86_ops->post_block(vcpu);
8056
8057 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8058 return 1;
8059 }
8060
8061 kvm_apic_accept_events(vcpu);
8062 switch(vcpu->arch.mp_state) {
8063 case KVM_MP_STATE_HALTED:
8064 vcpu->arch.pv.pv_unhalted = false;
8065 vcpu->arch.mp_state =
8066 KVM_MP_STATE_RUNNABLE;
8067 /* fall through */
8068 case KVM_MP_STATE_RUNNABLE:
8069 vcpu->arch.apf.halted = false;
8070 break;
8071 case KVM_MP_STATE_INIT_RECEIVED:
8072 break;
8073 default:
8074 return -EINTR;
8075 break;
8076 }
8077 return 1;
8078 }
8079
8080 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8081 {
8082 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8083 kvm_x86_ops->check_nested_events(vcpu, false);
8084
8085 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8086 !vcpu->arch.apf.halted);
8087 }
8088
8089 static int vcpu_run(struct kvm_vcpu *vcpu)
8090 {
8091 int r;
8092 struct kvm *kvm = vcpu->kvm;
8093
8094 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8095 vcpu->arch.l1tf_flush_l1d = true;
8096
8097 for (;;) {
8098 if (kvm_vcpu_running(vcpu)) {
8099 r = vcpu_enter_guest(vcpu);
8100 } else {
8101 r = vcpu_block(kvm, vcpu);
8102 }
8103
8104 if (r <= 0)
8105 break;
8106
8107 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8108 if (kvm_cpu_has_pending_timer(vcpu))
8109 kvm_inject_pending_timer_irqs(vcpu);
8110
8111 if (dm_request_for_irq_injection(vcpu) &&
8112 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8113 r = 0;
8114 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8115 ++vcpu->stat.request_irq_exits;
8116 break;
8117 }
8118
8119 kvm_check_async_pf_completion(vcpu);
8120
8121 if (signal_pending(current)) {
8122 r = -EINTR;
8123 vcpu->run->exit_reason = KVM_EXIT_INTR;
8124 ++vcpu->stat.signal_exits;
8125 break;
8126 }
8127 if (need_resched()) {
8128 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8129 cond_resched();
8130 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8131 }
8132 }
8133
8134 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8135
8136 return r;
8137 }
8138
8139 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8140 {
8141 int r;
8142 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8143 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8144 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8145 if (r != EMULATE_DONE)
8146 return 0;
8147 return 1;
8148 }
8149
8150 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8151 {
8152 BUG_ON(!vcpu->arch.pio.count);
8153
8154 return complete_emulated_io(vcpu);
8155 }
8156
8157 /*
8158 * Implements the following, as a state machine:
8159 *
8160 * read:
8161 * for each fragment
8162 * for each mmio piece in the fragment
8163 * write gpa, len
8164 * exit
8165 * copy data
8166 * execute insn
8167 *
8168 * write:
8169 * for each fragment
8170 * for each mmio piece in the fragment
8171 * write gpa, len
8172 * copy data
8173 * exit
8174 */
8175 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8176 {
8177 struct kvm_run *run = vcpu->run;
8178 struct kvm_mmio_fragment *frag;
8179 unsigned len;
8180
8181 BUG_ON(!vcpu->mmio_needed);
8182
8183 /* Complete previous fragment */
8184 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8185 len = min(8u, frag->len);
8186 if (!vcpu->mmio_is_write)
8187 memcpy(frag->data, run->mmio.data, len);
8188
8189 if (frag->len <= 8) {
8190 /* Switch to the next fragment. */
8191 frag++;
8192 vcpu->mmio_cur_fragment++;
8193 } else {
8194 /* Go forward to the next mmio piece. */
8195 frag->data += len;
8196 frag->gpa += len;
8197 frag->len -= len;
8198 }
8199
8200 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8201 vcpu->mmio_needed = 0;
8202
8203 /* FIXME: return into emulator if single-stepping. */
8204 if (vcpu->mmio_is_write)
8205 return 1;
8206 vcpu->mmio_read_completed = 1;
8207 return complete_emulated_io(vcpu);
8208 }
8209
8210 run->exit_reason = KVM_EXIT_MMIO;
8211 run->mmio.phys_addr = frag->gpa;
8212 if (vcpu->mmio_is_write)
8213 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8214 run->mmio.len = min(8u, frag->len);
8215 run->mmio.is_write = vcpu->mmio_is_write;
8216 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8217 return 0;
8218 }
8219
8220 /* Swap (qemu) user FPU context for the guest FPU context. */
8221 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8222 {
8223 fpregs_lock();
8224
8225 copy_fpregs_to_fpstate(&current->thread.fpu);
8226 /* PKRU is separately restored in kvm_x86_ops->run. */
8227 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8228 ~XFEATURE_MASK_PKRU);
8229
8230 fpregs_mark_activate();
8231 fpregs_unlock();
8232
8233 trace_kvm_fpu(1);
8234 }
8235
8236 /* When vcpu_run ends, restore user space FPU context. */
8237 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8238 {
8239 fpregs_lock();
8240
8241 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8242 copy_kernel_to_fpregs(&current->thread.fpu.state);
8243
8244 fpregs_mark_activate();
8245 fpregs_unlock();
8246
8247 ++vcpu->stat.fpu_reload;
8248 trace_kvm_fpu(0);
8249 }
8250
8251 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8252 {
8253 int r;
8254
8255 vcpu_load(vcpu);
8256 kvm_sigset_activate(vcpu);
8257 kvm_load_guest_fpu(vcpu);
8258
8259 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8260 if (kvm_run->immediate_exit) {
8261 r = -EINTR;
8262 goto out;
8263 }
8264 kvm_vcpu_block(vcpu);
8265 kvm_apic_accept_events(vcpu);
8266 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8267 r = -EAGAIN;
8268 if (signal_pending(current)) {
8269 r = -EINTR;
8270 vcpu->run->exit_reason = KVM_EXIT_INTR;
8271 ++vcpu->stat.signal_exits;
8272 }
8273 goto out;
8274 }
8275
8276 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8277 r = -EINVAL;
8278 goto out;
8279 }
8280
8281 if (vcpu->run->kvm_dirty_regs) {
8282 r = sync_regs(vcpu);
8283 if (r != 0)
8284 goto out;
8285 }
8286
8287 /* re-sync apic's tpr */
8288 if (!lapic_in_kernel(vcpu)) {
8289 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8290 r = -EINVAL;
8291 goto out;
8292 }
8293 }
8294
8295 if (unlikely(vcpu->arch.complete_userspace_io)) {
8296 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8297 vcpu->arch.complete_userspace_io = NULL;
8298 r = cui(vcpu);
8299 if (r <= 0)
8300 goto out;
8301 } else
8302 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8303
8304 if (kvm_run->immediate_exit)
8305 r = -EINTR;
8306 else
8307 r = vcpu_run(vcpu);
8308
8309 out:
8310 kvm_put_guest_fpu(vcpu);
8311 if (vcpu->run->kvm_valid_regs)
8312 store_regs(vcpu);
8313 post_kvm_run_save(vcpu);
8314 kvm_sigset_deactivate(vcpu);
8315
8316 vcpu_put(vcpu);
8317 return r;
8318 }
8319
8320 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8321 {
8322 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8323 /*
8324 * We are here if userspace calls get_regs() in the middle of
8325 * instruction emulation. Registers state needs to be copied
8326 * back from emulation context to vcpu. Userspace shouldn't do
8327 * that usually, but some bad designed PV devices (vmware
8328 * backdoor interface) need this to work
8329 */
8330 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8331 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8332 }
8333 regs->rax = kvm_rax_read(vcpu);
8334 regs->rbx = kvm_rbx_read(vcpu);
8335 regs->rcx = kvm_rcx_read(vcpu);
8336 regs->rdx = kvm_rdx_read(vcpu);
8337 regs->rsi = kvm_rsi_read(vcpu);
8338 regs->rdi = kvm_rdi_read(vcpu);
8339 regs->rsp = kvm_rsp_read(vcpu);
8340 regs->rbp = kvm_rbp_read(vcpu);
8341 #ifdef CONFIG_X86_64
8342 regs->r8 = kvm_r8_read(vcpu);
8343 regs->r9 = kvm_r9_read(vcpu);
8344 regs->r10 = kvm_r10_read(vcpu);
8345 regs->r11 = kvm_r11_read(vcpu);
8346 regs->r12 = kvm_r12_read(vcpu);
8347 regs->r13 = kvm_r13_read(vcpu);
8348 regs->r14 = kvm_r14_read(vcpu);
8349 regs->r15 = kvm_r15_read(vcpu);
8350 #endif
8351
8352 regs->rip = kvm_rip_read(vcpu);
8353 regs->rflags = kvm_get_rflags(vcpu);
8354 }
8355
8356 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8357 {
8358 vcpu_load(vcpu);
8359 __get_regs(vcpu, regs);
8360 vcpu_put(vcpu);
8361 return 0;
8362 }
8363
8364 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8365 {
8366 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8367 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8368
8369 kvm_rax_write(vcpu, regs->rax);
8370 kvm_rbx_write(vcpu, regs->rbx);
8371 kvm_rcx_write(vcpu, regs->rcx);
8372 kvm_rdx_write(vcpu, regs->rdx);
8373 kvm_rsi_write(vcpu, regs->rsi);
8374 kvm_rdi_write(vcpu, regs->rdi);
8375 kvm_rsp_write(vcpu, regs->rsp);
8376 kvm_rbp_write(vcpu, regs->rbp);
8377 #ifdef CONFIG_X86_64
8378 kvm_r8_write(vcpu, regs->r8);
8379 kvm_r9_write(vcpu, regs->r9);
8380 kvm_r10_write(vcpu, regs->r10);
8381 kvm_r11_write(vcpu, regs->r11);
8382 kvm_r12_write(vcpu, regs->r12);
8383 kvm_r13_write(vcpu, regs->r13);
8384 kvm_r14_write(vcpu, regs->r14);
8385 kvm_r15_write(vcpu, regs->r15);
8386 #endif
8387
8388 kvm_rip_write(vcpu, regs->rip);
8389 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8390
8391 vcpu->arch.exception.pending = false;
8392
8393 kvm_make_request(KVM_REQ_EVENT, vcpu);
8394 }
8395
8396 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8397 {
8398 vcpu_load(vcpu);
8399 __set_regs(vcpu, regs);
8400 vcpu_put(vcpu);
8401 return 0;
8402 }
8403
8404 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8405 {
8406 struct kvm_segment cs;
8407
8408 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8409 *db = cs.db;
8410 *l = cs.l;
8411 }
8412 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8413
8414 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8415 {
8416 struct desc_ptr dt;
8417
8418 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8419 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8420 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8421 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8422 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8423 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8424
8425 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8426 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8427
8428 kvm_x86_ops->get_idt(vcpu, &dt);
8429 sregs->idt.limit = dt.size;
8430 sregs->idt.base = dt.address;
8431 kvm_x86_ops->get_gdt(vcpu, &dt);
8432 sregs->gdt.limit = dt.size;
8433 sregs->gdt.base = dt.address;
8434
8435 sregs->cr0 = kvm_read_cr0(vcpu);
8436 sregs->cr2 = vcpu->arch.cr2;
8437 sregs->cr3 = kvm_read_cr3(vcpu);
8438 sregs->cr4 = kvm_read_cr4(vcpu);
8439 sregs->cr8 = kvm_get_cr8(vcpu);
8440 sregs->efer = vcpu->arch.efer;
8441 sregs->apic_base = kvm_get_apic_base(vcpu);
8442
8443 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8444
8445 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8446 set_bit(vcpu->arch.interrupt.nr,
8447 (unsigned long *)sregs->interrupt_bitmap);
8448 }
8449
8450 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8451 struct kvm_sregs *sregs)
8452 {
8453 vcpu_load(vcpu);
8454 __get_sregs(vcpu, sregs);
8455 vcpu_put(vcpu);
8456 return 0;
8457 }
8458
8459 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8460 struct kvm_mp_state *mp_state)
8461 {
8462 vcpu_load(vcpu);
8463
8464 kvm_apic_accept_events(vcpu);
8465 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8466 vcpu->arch.pv.pv_unhalted)
8467 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8468 else
8469 mp_state->mp_state = vcpu->arch.mp_state;
8470
8471 vcpu_put(vcpu);
8472 return 0;
8473 }
8474
8475 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8476 struct kvm_mp_state *mp_state)
8477 {
8478 int ret = -EINVAL;
8479
8480 vcpu_load(vcpu);
8481
8482 if (!lapic_in_kernel(vcpu) &&
8483 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8484 goto out;
8485
8486 /* INITs are latched while in SMM */
8487 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8488 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8489 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8490 goto out;
8491
8492 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8493 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8494 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8495 } else
8496 vcpu->arch.mp_state = mp_state->mp_state;
8497 kvm_make_request(KVM_REQ_EVENT, vcpu);
8498
8499 ret = 0;
8500 out:
8501 vcpu_put(vcpu);
8502 return ret;
8503 }
8504
8505 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8506 int reason, bool has_error_code, u32 error_code)
8507 {
8508 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8509 int ret;
8510
8511 init_emulate_ctxt(vcpu);
8512
8513 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8514 has_error_code, error_code);
8515
8516 if (ret)
8517 return EMULATE_FAIL;
8518
8519 kvm_rip_write(vcpu, ctxt->eip);
8520 kvm_set_rflags(vcpu, ctxt->eflags);
8521 kvm_make_request(KVM_REQ_EVENT, vcpu);
8522 return EMULATE_DONE;
8523 }
8524 EXPORT_SYMBOL_GPL(kvm_task_switch);
8525
8526 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8527 {
8528 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8529 (sregs->cr4 & X86_CR4_OSXSAVE))
8530 return -EINVAL;
8531
8532 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8533 /*
8534 * When EFER.LME and CR0.PG are set, the processor is in
8535 * 64-bit mode (though maybe in a 32-bit code segment).
8536 * CR4.PAE and EFER.LMA must be set.
8537 */
8538 if (!(sregs->cr4 & X86_CR4_PAE)
8539 || !(sregs->efer & EFER_LMA))
8540 return -EINVAL;
8541 } else {
8542 /*
8543 * Not in 64-bit mode: EFER.LMA is clear and the code
8544 * segment cannot be 64-bit.
8545 */
8546 if (sregs->efer & EFER_LMA || sregs->cs.l)
8547 return -EINVAL;
8548 }
8549
8550 return 0;
8551 }
8552
8553 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8554 {
8555 struct msr_data apic_base_msr;
8556 int mmu_reset_needed = 0;
8557 int cpuid_update_needed = 0;
8558 int pending_vec, max_bits, idx;
8559 struct desc_ptr dt;
8560 int ret = -EINVAL;
8561
8562 if (kvm_valid_sregs(vcpu, sregs))
8563 goto out;
8564
8565 apic_base_msr.data = sregs->apic_base;
8566 apic_base_msr.host_initiated = true;
8567 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8568 goto out;
8569
8570 dt.size = sregs->idt.limit;
8571 dt.address = sregs->idt.base;
8572 kvm_x86_ops->set_idt(vcpu, &dt);
8573 dt.size = sregs->gdt.limit;
8574 dt.address = sregs->gdt.base;
8575 kvm_x86_ops->set_gdt(vcpu, &dt);
8576
8577 vcpu->arch.cr2 = sregs->cr2;
8578 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8579 vcpu->arch.cr3 = sregs->cr3;
8580 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8581
8582 kvm_set_cr8(vcpu, sregs->cr8);
8583
8584 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8585 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8586
8587 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8588 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8589 vcpu->arch.cr0 = sregs->cr0;
8590
8591 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8592 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8593 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8594 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8595 if (cpuid_update_needed)
8596 kvm_update_cpuid(vcpu);
8597
8598 idx = srcu_read_lock(&vcpu->kvm->srcu);
8599 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
8600 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8601 mmu_reset_needed = 1;
8602 }
8603 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8604
8605 if (mmu_reset_needed)
8606 kvm_mmu_reset_context(vcpu);
8607
8608 max_bits = KVM_NR_INTERRUPTS;
8609 pending_vec = find_first_bit(
8610 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8611 if (pending_vec < max_bits) {
8612 kvm_queue_interrupt(vcpu, pending_vec, false);
8613 pr_debug("Set back pending irq %d\n", pending_vec);
8614 }
8615
8616 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8617 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8618 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8619 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8620 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8621 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8622
8623 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8624 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8625
8626 update_cr8_intercept(vcpu);
8627
8628 /* Older userspace won't unhalt the vcpu on reset. */
8629 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8630 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8631 !is_protmode(vcpu))
8632 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8633
8634 kvm_make_request(KVM_REQ_EVENT, vcpu);
8635
8636 ret = 0;
8637 out:
8638 return ret;
8639 }
8640
8641 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8642 struct kvm_sregs *sregs)
8643 {
8644 int ret;
8645
8646 vcpu_load(vcpu);
8647 ret = __set_sregs(vcpu, sregs);
8648 vcpu_put(vcpu);
8649 return ret;
8650 }
8651
8652 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8653 struct kvm_guest_debug *dbg)
8654 {
8655 unsigned long rflags;
8656 int i, r;
8657
8658 vcpu_load(vcpu);
8659
8660 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8661 r = -EBUSY;
8662 if (vcpu->arch.exception.pending)
8663 goto out;
8664 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8665 kvm_queue_exception(vcpu, DB_VECTOR);
8666 else
8667 kvm_queue_exception(vcpu, BP_VECTOR);
8668 }
8669
8670 /*
8671 * Read rflags as long as potentially injected trace flags are still
8672 * filtered out.
8673 */
8674 rflags = kvm_get_rflags(vcpu);
8675
8676 vcpu->guest_debug = dbg->control;
8677 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8678 vcpu->guest_debug = 0;
8679
8680 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8681 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8682 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8683 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8684 } else {
8685 for (i = 0; i < KVM_NR_DB_REGS; i++)
8686 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8687 }
8688 kvm_update_dr7(vcpu);
8689
8690 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8691 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8692 get_segment_base(vcpu, VCPU_SREG_CS);
8693
8694 /*
8695 * Trigger an rflags update that will inject or remove the trace
8696 * flags.
8697 */
8698 kvm_set_rflags(vcpu, rflags);
8699
8700 kvm_x86_ops->update_bp_intercept(vcpu);
8701
8702 r = 0;
8703
8704 out:
8705 vcpu_put(vcpu);
8706 return r;
8707 }
8708
8709 /*
8710 * Translate a guest virtual address to a guest physical address.
8711 */
8712 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8713 struct kvm_translation *tr)
8714 {
8715 unsigned long vaddr = tr->linear_address;
8716 gpa_t gpa;
8717 int idx;
8718
8719 vcpu_load(vcpu);
8720
8721 idx = srcu_read_lock(&vcpu->kvm->srcu);
8722 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8723 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8724 tr->physical_address = gpa;
8725 tr->valid = gpa != UNMAPPED_GVA;
8726 tr->writeable = 1;
8727 tr->usermode = 0;
8728
8729 vcpu_put(vcpu);
8730 return 0;
8731 }
8732
8733 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8734 {
8735 struct fxregs_state *fxsave;
8736
8737 vcpu_load(vcpu);
8738
8739 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8740 memcpy(fpu->fpr, fxsave->st_space, 128);
8741 fpu->fcw = fxsave->cwd;
8742 fpu->fsw = fxsave->swd;
8743 fpu->ftwx = fxsave->twd;
8744 fpu->last_opcode = fxsave->fop;
8745 fpu->last_ip = fxsave->rip;
8746 fpu->last_dp = fxsave->rdp;
8747 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8748
8749 vcpu_put(vcpu);
8750 return 0;
8751 }
8752
8753 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8754 {
8755 struct fxregs_state *fxsave;
8756
8757 vcpu_load(vcpu);
8758
8759 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8760
8761 memcpy(fxsave->st_space, fpu->fpr, 128);
8762 fxsave->cwd = fpu->fcw;
8763 fxsave->swd = fpu->fsw;
8764 fxsave->twd = fpu->ftwx;
8765 fxsave->fop = fpu->last_opcode;
8766 fxsave->rip = fpu->last_ip;
8767 fxsave->rdp = fpu->last_dp;
8768 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8769
8770 vcpu_put(vcpu);
8771 return 0;
8772 }
8773
8774 static void store_regs(struct kvm_vcpu *vcpu)
8775 {
8776 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8777
8778 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8779 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8780
8781 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8782 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8783
8784 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8785 kvm_vcpu_ioctl_x86_get_vcpu_events(
8786 vcpu, &vcpu->run->s.regs.events);
8787 }
8788
8789 static int sync_regs(struct kvm_vcpu *vcpu)
8790 {
8791 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8792 return -EINVAL;
8793
8794 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8795 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8796 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8797 }
8798 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8799 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8800 return -EINVAL;
8801 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8802 }
8803 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8804 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8805 vcpu, &vcpu->run->s.regs.events))
8806 return -EINVAL;
8807 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8808 }
8809
8810 return 0;
8811 }
8812
8813 static void fx_init(struct kvm_vcpu *vcpu)
8814 {
8815 fpstate_init(&vcpu->arch.guest_fpu->state);
8816 if (boot_cpu_has(X86_FEATURE_XSAVES))
8817 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8818 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8819
8820 /*
8821 * Ensure guest xcr0 is valid for loading
8822 */
8823 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8824
8825 vcpu->arch.cr0 |= X86_CR0_ET;
8826 }
8827
8828 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8829 {
8830 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8831
8832 kvmclock_reset(vcpu);
8833
8834 kvm_x86_ops->vcpu_free(vcpu);
8835 free_cpumask_var(wbinvd_dirty_mask);
8836 }
8837
8838 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8839 unsigned int id)
8840 {
8841 struct kvm_vcpu *vcpu;
8842
8843 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8844 printk_once(KERN_WARNING
8845 "kvm: SMP vm created on host with unstable TSC; "
8846 "guest TSC will not be reliable\n");
8847
8848 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8849
8850 return vcpu;
8851 }
8852
8853 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8854 {
8855 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
8856 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8857 kvm_vcpu_mtrr_init(vcpu);
8858 vcpu_load(vcpu);
8859 kvm_vcpu_reset(vcpu, false);
8860 kvm_init_mmu(vcpu, false);
8861 vcpu_put(vcpu);
8862 return 0;
8863 }
8864
8865 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8866 {
8867 struct msr_data msr;
8868 struct kvm *kvm = vcpu->kvm;
8869
8870 kvm_hv_vcpu_postcreate(vcpu);
8871
8872 if (mutex_lock_killable(&vcpu->mutex))
8873 return;
8874 vcpu_load(vcpu);
8875 msr.data = 0x0;
8876 msr.index = MSR_IA32_TSC;
8877 msr.host_initiated = true;
8878 kvm_write_tsc(vcpu, &msr);
8879 vcpu_put(vcpu);
8880 mutex_unlock(&vcpu->mutex);
8881
8882 if (!kvmclock_periodic_sync)
8883 return;
8884
8885 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8886 KVMCLOCK_SYNC_PERIOD);
8887 }
8888
8889 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8890 {
8891 vcpu->arch.apf.msr_val = 0;
8892
8893 vcpu_load(vcpu);
8894 kvm_mmu_unload(vcpu);
8895 vcpu_put(vcpu);
8896
8897 kvm_x86_ops->vcpu_free(vcpu);
8898 }
8899
8900 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8901 {
8902 kvm_lapic_reset(vcpu, init_event);
8903
8904 vcpu->arch.hflags = 0;
8905
8906 vcpu->arch.smi_pending = 0;
8907 vcpu->arch.smi_count = 0;
8908 atomic_set(&vcpu->arch.nmi_queued, 0);
8909 vcpu->arch.nmi_pending = 0;
8910 vcpu->arch.nmi_injected = false;
8911 kvm_clear_interrupt_queue(vcpu);
8912 kvm_clear_exception_queue(vcpu);
8913 vcpu->arch.exception.pending = false;
8914
8915 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8916 kvm_update_dr0123(vcpu);
8917 vcpu->arch.dr6 = DR6_INIT;
8918 kvm_update_dr6(vcpu);
8919 vcpu->arch.dr7 = DR7_FIXED_1;
8920 kvm_update_dr7(vcpu);
8921
8922 vcpu->arch.cr2 = 0;
8923
8924 kvm_make_request(KVM_REQ_EVENT, vcpu);
8925 vcpu->arch.apf.msr_val = 0;
8926 vcpu->arch.st.msr_val = 0;
8927
8928 kvmclock_reset(vcpu);
8929
8930 kvm_clear_async_pf_completion_queue(vcpu);
8931 kvm_async_pf_hash_reset(vcpu);
8932 vcpu->arch.apf.halted = false;
8933
8934 if (kvm_mpx_supported()) {
8935 void *mpx_state_buffer;
8936
8937 /*
8938 * To avoid have the INIT path from kvm_apic_has_events() that be
8939 * called with loaded FPU and does not let userspace fix the state.
8940 */
8941 if (init_event)
8942 kvm_put_guest_fpu(vcpu);
8943 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8944 XFEATURE_BNDREGS);
8945 if (mpx_state_buffer)
8946 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8947 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8948 XFEATURE_BNDCSR);
8949 if (mpx_state_buffer)
8950 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
8951 if (init_event)
8952 kvm_load_guest_fpu(vcpu);
8953 }
8954
8955 if (!init_event) {
8956 kvm_pmu_reset(vcpu);
8957 vcpu->arch.smbase = 0x30000;
8958
8959 vcpu->arch.msr_misc_features_enables = 0;
8960
8961 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8962 }
8963
8964 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8965 vcpu->arch.regs_avail = ~0;
8966 vcpu->arch.regs_dirty = ~0;
8967
8968 vcpu->arch.ia32_xss = 0;
8969
8970 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8971 }
8972
8973 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8974 {
8975 struct kvm_segment cs;
8976
8977 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8978 cs.selector = vector << 8;
8979 cs.base = vector << 12;
8980 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8981 kvm_rip_write(vcpu, 0);
8982 }
8983
8984 int kvm_arch_hardware_enable(void)
8985 {
8986 struct kvm *kvm;
8987 struct kvm_vcpu *vcpu;
8988 int i;
8989 int ret;
8990 u64 local_tsc;
8991 u64 max_tsc = 0;
8992 bool stable, backwards_tsc = false;
8993
8994 kvm_shared_msr_cpu_online();
8995 ret = kvm_x86_ops->hardware_enable();
8996 if (ret != 0)
8997 return ret;
8998
8999 local_tsc = rdtsc();
9000 stable = !kvm_check_tsc_unstable();
9001 list_for_each_entry(kvm, &vm_list, vm_list) {
9002 kvm_for_each_vcpu(i, vcpu, kvm) {
9003 if (!stable && vcpu->cpu == smp_processor_id())
9004 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9005 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9006 backwards_tsc = true;
9007 if (vcpu->arch.last_host_tsc > max_tsc)
9008 max_tsc = vcpu->arch.last_host_tsc;
9009 }
9010 }
9011 }
9012
9013 /*
9014 * Sometimes, even reliable TSCs go backwards. This happens on
9015 * platforms that reset TSC during suspend or hibernate actions, but
9016 * maintain synchronization. We must compensate. Fortunately, we can
9017 * detect that condition here, which happens early in CPU bringup,
9018 * before any KVM threads can be running. Unfortunately, we can't
9019 * bring the TSCs fully up to date with real time, as we aren't yet far
9020 * enough into CPU bringup that we know how much real time has actually
9021 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
9022 * variables that haven't been updated yet.
9023 *
9024 * So we simply find the maximum observed TSC above, then record the
9025 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9026 * the adjustment will be applied. Note that we accumulate
9027 * adjustments, in case multiple suspend cycles happen before some VCPU
9028 * gets a chance to run again. In the event that no KVM threads get a
9029 * chance to run, we will miss the entire elapsed period, as we'll have
9030 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9031 * loose cycle time. This isn't too big a deal, since the loss will be
9032 * uniform across all VCPUs (not to mention the scenario is extremely
9033 * unlikely). It is possible that a second hibernate recovery happens
9034 * much faster than a first, causing the observed TSC here to be
9035 * smaller; this would require additional padding adjustment, which is
9036 * why we set last_host_tsc to the local tsc observed here.
9037 *
9038 * N.B. - this code below runs only on platforms with reliable TSC,
9039 * as that is the only way backwards_tsc is set above. Also note
9040 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9041 * have the same delta_cyc adjustment applied if backwards_tsc
9042 * is detected. Note further, this adjustment is only done once,
9043 * as we reset last_host_tsc on all VCPUs to stop this from being
9044 * called multiple times (one for each physical CPU bringup).
9045 *
9046 * Platforms with unreliable TSCs don't have to deal with this, they
9047 * will be compensated by the logic in vcpu_load, which sets the TSC to
9048 * catchup mode. This will catchup all VCPUs to real time, but cannot
9049 * guarantee that they stay in perfect synchronization.
9050 */
9051 if (backwards_tsc) {
9052 u64 delta_cyc = max_tsc - local_tsc;
9053 list_for_each_entry(kvm, &vm_list, vm_list) {
9054 kvm->arch.backwards_tsc_observed = true;
9055 kvm_for_each_vcpu(i, vcpu, kvm) {
9056 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9057 vcpu->arch.last_host_tsc = local_tsc;
9058 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9059 }
9060
9061 /*
9062 * We have to disable TSC offset matching.. if you were
9063 * booting a VM while issuing an S4 host suspend....
9064 * you may have some problem. Solving this issue is
9065 * left as an exercise to the reader.
9066 */
9067 kvm->arch.last_tsc_nsec = 0;
9068 kvm->arch.last_tsc_write = 0;
9069 }
9070
9071 }
9072 return 0;
9073 }
9074
9075 void kvm_arch_hardware_disable(void)
9076 {
9077 kvm_x86_ops->hardware_disable();
9078 drop_user_return_notifiers();
9079 }
9080
9081 int kvm_arch_hardware_setup(void)
9082 {
9083 int r;
9084
9085 r = kvm_x86_ops->hardware_setup();
9086 if (r != 0)
9087 return r;
9088
9089 if (kvm_has_tsc_control) {
9090 /*
9091 * Make sure the user can only configure tsc_khz values that
9092 * fit into a signed integer.
9093 * A min value is not calculated because it will always
9094 * be 1 on all machines.
9095 */
9096 u64 max = min(0x7fffffffULL,
9097 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9098 kvm_max_guest_tsc_khz = max;
9099
9100 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9101 }
9102
9103 kvm_init_msr_list();
9104 return 0;
9105 }
9106
9107 void kvm_arch_hardware_unsetup(void)
9108 {
9109 kvm_x86_ops->hardware_unsetup();
9110 }
9111
9112 void kvm_arch_check_processor_compat(void *rtn)
9113 {
9114 kvm_x86_ops->check_processor_compatibility(rtn);
9115 }
9116
9117 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9118 {
9119 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9120 }
9121 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9122
9123 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9124 {
9125 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9126 }
9127
9128 struct static_key kvm_no_apic_vcpu __read_mostly;
9129 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9130
9131 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9132 {
9133 struct page *page;
9134 int r;
9135
9136 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9137 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9138 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9139 else
9140 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9141
9142 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9143 if (!page) {
9144 r = -ENOMEM;
9145 goto fail;
9146 }
9147 vcpu->arch.pio_data = page_address(page);
9148
9149 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9150
9151 r = kvm_mmu_create(vcpu);
9152 if (r < 0)
9153 goto fail_free_pio_data;
9154
9155 if (irqchip_in_kernel(vcpu->kvm)) {
9156 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9157 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9158 if (r < 0)
9159 goto fail_mmu_destroy;
9160 } else
9161 static_key_slow_inc(&kvm_no_apic_vcpu);
9162
9163 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9164 GFP_KERNEL_ACCOUNT);
9165 if (!vcpu->arch.mce_banks) {
9166 r = -ENOMEM;
9167 goto fail_free_lapic;
9168 }
9169 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9170
9171 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9172 GFP_KERNEL_ACCOUNT)) {
9173 r = -ENOMEM;
9174 goto fail_free_mce_banks;
9175 }
9176
9177 fx_init(vcpu);
9178
9179 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9180
9181 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9182
9183 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9184
9185 kvm_async_pf_hash_reset(vcpu);
9186 kvm_pmu_init(vcpu);
9187
9188 vcpu->arch.pending_external_vector = -1;
9189 vcpu->arch.preempted_in_kernel = false;
9190
9191 kvm_hv_vcpu_init(vcpu);
9192
9193 return 0;
9194
9195 fail_free_mce_banks:
9196 kfree(vcpu->arch.mce_banks);
9197 fail_free_lapic:
9198 kvm_free_lapic(vcpu);
9199 fail_mmu_destroy:
9200 kvm_mmu_destroy(vcpu);
9201 fail_free_pio_data:
9202 free_page((unsigned long)vcpu->arch.pio_data);
9203 fail:
9204 return r;
9205 }
9206
9207 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9208 {
9209 int idx;
9210
9211 kvm_hv_vcpu_uninit(vcpu);
9212 kvm_pmu_destroy(vcpu);
9213 kfree(vcpu->arch.mce_banks);
9214 kvm_free_lapic(vcpu);
9215 idx = srcu_read_lock(&vcpu->kvm->srcu);
9216 kvm_mmu_destroy(vcpu);
9217 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9218 free_page((unsigned long)vcpu->arch.pio_data);
9219 if (!lapic_in_kernel(vcpu))
9220 static_key_slow_dec(&kvm_no_apic_vcpu);
9221 }
9222
9223 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9224 {
9225 vcpu->arch.l1tf_flush_l1d = true;
9226 kvm_x86_ops->sched_in(vcpu, cpu);
9227 }
9228
9229 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9230 {
9231 if (type)
9232 return -EINVAL;
9233
9234 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9235 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9236 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9237 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9238
9239 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9240 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9241 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9242 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9243 &kvm->arch.irq_sources_bitmap);
9244
9245 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9246 mutex_init(&kvm->arch.apic_map_lock);
9247 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9248
9249 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
9250 pvclock_update_vm_gtod_copy(kvm);
9251
9252 kvm->arch.guest_can_read_msr_platform_info = true;
9253
9254 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9255 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9256
9257 kvm_hv_init_vm(kvm);
9258 kvm_page_track_init(kvm);
9259 kvm_mmu_init_vm(kvm);
9260
9261 if (kvm_x86_ops->vm_init)
9262 return kvm_x86_ops->vm_init(kvm);
9263
9264 return 0;
9265 }
9266
9267 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9268 {
9269 vcpu_load(vcpu);
9270 kvm_mmu_unload(vcpu);
9271 vcpu_put(vcpu);
9272 }
9273
9274 static void kvm_free_vcpus(struct kvm *kvm)
9275 {
9276 unsigned int i;
9277 struct kvm_vcpu *vcpu;
9278
9279 /*
9280 * Unpin any mmu pages first.
9281 */
9282 kvm_for_each_vcpu(i, vcpu, kvm) {
9283 kvm_clear_async_pf_completion_queue(vcpu);
9284 kvm_unload_vcpu_mmu(vcpu);
9285 }
9286 kvm_for_each_vcpu(i, vcpu, kvm)
9287 kvm_arch_vcpu_free(vcpu);
9288
9289 mutex_lock(&kvm->lock);
9290 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9291 kvm->vcpus[i] = NULL;
9292
9293 atomic_set(&kvm->online_vcpus, 0);
9294 mutex_unlock(&kvm->lock);
9295 }
9296
9297 void kvm_arch_sync_events(struct kvm *kvm)
9298 {
9299 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9300 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9301 kvm_free_pit(kvm);
9302 }
9303
9304 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9305 {
9306 int i, r;
9307 unsigned long hva;
9308 struct kvm_memslots *slots = kvm_memslots(kvm);
9309 struct kvm_memory_slot *slot, old;
9310
9311 /* Called with kvm->slots_lock held. */
9312 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9313 return -EINVAL;
9314
9315 slot = id_to_memslot(slots, id);
9316 if (size) {
9317 if (slot->npages)
9318 return -EEXIST;
9319
9320 /*
9321 * MAP_SHARED to prevent internal slot pages from being moved
9322 * by fork()/COW.
9323 */
9324 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9325 MAP_SHARED | MAP_ANONYMOUS, 0);
9326 if (IS_ERR((void *)hva))
9327 return PTR_ERR((void *)hva);
9328 } else {
9329 if (!slot->npages)
9330 return 0;
9331
9332 hva = 0;
9333 }
9334
9335 old = *slot;
9336 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9337 struct kvm_userspace_memory_region m;
9338
9339 m.slot = id | (i << 16);
9340 m.flags = 0;
9341 m.guest_phys_addr = gpa;
9342 m.userspace_addr = hva;
9343 m.memory_size = size;
9344 r = __kvm_set_memory_region(kvm, &m);
9345 if (r < 0)
9346 return r;
9347 }
9348
9349 if (!size)
9350 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9351
9352 return 0;
9353 }
9354 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9355
9356 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9357 {
9358 int r;
9359
9360 mutex_lock(&kvm->slots_lock);
9361 r = __x86_set_memory_region(kvm, id, gpa, size);
9362 mutex_unlock(&kvm->slots_lock);
9363
9364 return r;
9365 }
9366 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9367
9368 void kvm_arch_destroy_vm(struct kvm *kvm)
9369 {
9370 if (current->mm == kvm->mm) {
9371 /*
9372 * Free memory regions allocated on behalf of userspace,
9373 * unless the the memory map has changed due to process exit
9374 * or fd copying.
9375 */
9376 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9377 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9378 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9379 }
9380 if (kvm_x86_ops->vm_destroy)
9381 kvm_x86_ops->vm_destroy(kvm);
9382 kvm_pic_destroy(kvm);
9383 kvm_ioapic_destroy(kvm);
9384 kvm_free_vcpus(kvm);
9385 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9386 kvm_mmu_uninit_vm(kvm);
9387 kvm_page_track_cleanup(kvm);
9388 kvm_hv_destroy_vm(kvm);
9389 }
9390
9391 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9392 struct kvm_memory_slot *dont)
9393 {
9394 int i;
9395
9396 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9397 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9398 kvfree(free->arch.rmap[i]);
9399 free->arch.rmap[i] = NULL;
9400 }
9401 if (i == 0)
9402 continue;
9403
9404 if (!dont || free->arch.lpage_info[i - 1] !=
9405 dont->arch.lpage_info[i - 1]) {
9406 kvfree(free->arch.lpage_info[i - 1]);
9407 free->arch.lpage_info[i - 1] = NULL;
9408 }
9409 }
9410
9411 kvm_page_track_free_memslot(free, dont);
9412 }
9413
9414 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9415 unsigned long npages)
9416 {
9417 int i;
9418
9419 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9420 struct kvm_lpage_info *linfo;
9421 unsigned long ugfn;
9422 int lpages;
9423 int level = i + 1;
9424
9425 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9426 slot->base_gfn, level) + 1;
9427
9428 slot->arch.rmap[i] =
9429 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9430 GFP_KERNEL_ACCOUNT);
9431 if (!slot->arch.rmap[i])
9432 goto out_free;
9433 if (i == 0)
9434 continue;
9435
9436 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9437 if (!linfo)
9438 goto out_free;
9439
9440 slot->arch.lpage_info[i - 1] = linfo;
9441
9442 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9443 linfo[0].disallow_lpage = 1;
9444 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9445 linfo[lpages - 1].disallow_lpage = 1;
9446 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9447 /*
9448 * If the gfn and userspace address are not aligned wrt each
9449 * other, or if explicitly asked to, disable large page
9450 * support for this slot
9451 */
9452 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9453 !kvm_largepages_enabled()) {
9454 unsigned long j;
9455
9456 for (j = 0; j < lpages; ++j)
9457 linfo[j].disallow_lpage = 1;
9458 }
9459 }
9460
9461 if (kvm_page_track_create_memslot(slot, npages))
9462 goto out_free;
9463
9464 return 0;
9465
9466 out_free:
9467 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9468 kvfree(slot->arch.rmap[i]);
9469 slot->arch.rmap[i] = NULL;
9470 if (i == 0)
9471 continue;
9472
9473 kvfree(slot->arch.lpage_info[i - 1]);
9474 slot->arch.lpage_info[i - 1] = NULL;
9475 }
9476 return -ENOMEM;
9477 }
9478
9479 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9480 {
9481 /*
9482 * memslots->generation has been incremented.
9483 * mmio generation may have reached its maximum value.
9484 */
9485 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9486 }
9487
9488 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9489 struct kvm_memory_slot *memslot,
9490 const struct kvm_userspace_memory_region *mem,
9491 enum kvm_mr_change change)
9492 {
9493 return 0;
9494 }
9495
9496 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9497 struct kvm_memory_slot *new)
9498 {
9499 /* Still write protect RO slot */
9500 if (new->flags & KVM_MEM_READONLY) {
9501 kvm_mmu_slot_remove_write_access(kvm, new);
9502 return;
9503 }
9504
9505 /*
9506 * Call kvm_x86_ops dirty logging hooks when they are valid.
9507 *
9508 * kvm_x86_ops->slot_disable_log_dirty is called when:
9509 *
9510 * - KVM_MR_CREATE with dirty logging is disabled
9511 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9512 *
9513 * The reason is, in case of PML, we need to set D-bit for any slots
9514 * with dirty logging disabled in order to eliminate unnecessary GPA
9515 * logging in PML buffer (and potential PML buffer full VMEXT). This
9516 * guarantees leaving PML enabled during guest's lifetime won't have
9517 * any additional overhead from PML when guest is running with dirty
9518 * logging disabled for memory slots.
9519 *
9520 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9521 * to dirty logging mode.
9522 *
9523 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9524 *
9525 * In case of write protect:
9526 *
9527 * Write protect all pages for dirty logging.
9528 *
9529 * All the sptes including the large sptes which point to this
9530 * slot are set to readonly. We can not create any new large
9531 * spte on this slot until the end of the logging.
9532 *
9533 * See the comments in fast_page_fault().
9534 */
9535 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9536 if (kvm_x86_ops->slot_enable_log_dirty)
9537 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9538 else
9539 kvm_mmu_slot_remove_write_access(kvm, new);
9540 } else {
9541 if (kvm_x86_ops->slot_disable_log_dirty)
9542 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9543 }
9544 }
9545
9546 void kvm_arch_commit_memory_region(struct kvm *kvm,
9547 const struct kvm_userspace_memory_region *mem,
9548 const struct kvm_memory_slot *old,
9549 const struct kvm_memory_slot *new,
9550 enum kvm_mr_change change)
9551 {
9552 if (!kvm->arch.n_requested_mmu_pages)
9553 kvm_mmu_change_mmu_pages(kvm,
9554 kvm_mmu_calculate_default_mmu_pages(kvm));
9555
9556 /*
9557 * Dirty logging tracks sptes in 4k granularity, meaning that large
9558 * sptes have to be split. If live migration is successful, the guest
9559 * in the source machine will be destroyed and large sptes will be
9560 * created in the destination. However, if the guest continues to run
9561 * in the source machine (for example if live migration fails), small
9562 * sptes will remain around and cause bad performance.
9563 *
9564 * Scan sptes if dirty logging has been stopped, dropping those
9565 * which can be collapsed into a single large-page spte. Later
9566 * page faults will create the large-page sptes.
9567 */
9568 if ((change != KVM_MR_DELETE) &&
9569 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9570 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9571 kvm_mmu_zap_collapsible_sptes(kvm, new);
9572
9573 /*
9574 * Set up write protection and/or dirty logging for the new slot.
9575 *
9576 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9577 * been zapped so no dirty logging staff is needed for old slot. For
9578 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9579 * new and it's also covered when dealing with the new slot.
9580 *
9581 * FIXME: const-ify all uses of struct kvm_memory_slot.
9582 */
9583 if (change != KVM_MR_DELETE)
9584 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9585 }
9586
9587 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9588 {
9589 kvm_mmu_zap_all(kvm);
9590 }
9591
9592 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9593 struct kvm_memory_slot *slot)
9594 {
9595 kvm_page_track_flush_slot(kvm, slot);
9596 }
9597
9598 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9599 {
9600 return (is_guest_mode(vcpu) &&
9601 kvm_x86_ops->guest_apic_has_interrupt &&
9602 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9603 }
9604
9605 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9606 {
9607 if (!list_empty_careful(&vcpu->async_pf.done))
9608 return true;
9609
9610 if (kvm_apic_has_events(vcpu))
9611 return true;
9612
9613 if (vcpu->arch.pv.pv_unhalted)
9614 return true;
9615
9616 if (vcpu->arch.exception.pending)
9617 return true;
9618
9619 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9620 (vcpu->arch.nmi_pending &&
9621 kvm_x86_ops->nmi_allowed(vcpu)))
9622 return true;
9623
9624 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9625 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9626 return true;
9627
9628 if (kvm_arch_interrupt_allowed(vcpu) &&
9629 (kvm_cpu_has_interrupt(vcpu) ||
9630 kvm_guest_apic_has_interrupt(vcpu)))
9631 return true;
9632
9633 if (kvm_hv_has_stimer_pending(vcpu))
9634 return true;
9635
9636 return false;
9637 }
9638
9639 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9640 {
9641 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9642 }
9643
9644 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9645 {
9646 return vcpu->arch.preempted_in_kernel;
9647 }
9648
9649 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9650 {
9651 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9652 }
9653
9654 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9655 {
9656 return kvm_x86_ops->interrupt_allowed(vcpu);
9657 }
9658
9659 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9660 {
9661 if (is_64_bit_mode(vcpu))
9662 return kvm_rip_read(vcpu);
9663 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9664 kvm_rip_read(vcpu));
9665 }
9666 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9667
9668 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9669 {
9670 return kvm_get_linear_rip(vcpu) == linear_rip;
9671 }
9672 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9673
9674 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9675 {
9676 unsigned long rflags;
9677
9678 rflags = kvm_x86_ops->get_rflags(vcpu);
9679 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9680 rflags &= ~X86_EFLAGS_TF;
9681 return rflags;
9682 }
9683 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9684
9685 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9686 {
9687 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9688 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9689 rflags |= X86_EFLAGS_TF;
9690 kvm_x86_ops->set_rflags(vcpu, rflags);
9691 }
9692
9693 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9694 {
9695 __kvm_set_rflags(vcpu, rflags);
9696 kvm_make_request(KVM_REQ_EVENT, vcpu);
9697 }
9698 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9699
9700 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9701 {
9702 int r;
9703
9704 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9705 work->wakeup_all)
9706 return;
9707
9708 r = kvm_mmu_reload(vcpu);
9709 if (unlikely(r))
9710 return;
9711
9712 if (!vcpu->arch.mmu->direct_map &&
9713 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9714 return;
9715
9716 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9717 }
9718
9719 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9720 {
9721 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9722 }
9723
9724 static inline u32 kvm_async_pf_next_probe(u32 key)
9725 {
9726 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9727 }
9728
9729 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9730 {
9731 u32 key = kvm_async_pf_hash_fn(gfn);
9732
9733 while (vcpu->arch.apf.gfns[key] != ~0)
9734 key = kvm_async_pf_next_probe(key);
9735
9736 vcpu->arch.apf.gfns[key] = gfn;
9737 }
9738
9739 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9740 {
9741 int i;
9742 u32 key = kvm_async_pf_hash_fn(gfn);
9743
9744 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9745 (vcpu->arch.apf.gfns[key] != gfn &&
9746 vcpu->arch.apf.gfns[key] != ~0); i++)
9747 key = kvm_async_pf_next_probe(key);
9748
9749 return key;
9750 }
9751
9752 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9753 {
9754 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9755 }
9756
9757 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9758 {
9759 u32 i, j, k;
9760
9761 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9762 while (true) {
9763 vcpu->arch.apf.gfns[i] = ~0;
9764 do {
9765 j = kvm_async_pf_next_probe(j);
9766 if (vcpu->arch.apf.gfns[j] == ~0)
9767 return;
9768 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9769 /*
9770 * k lies cyclically in ]i,j]
9771 * | i.k.j |
9772 * |....j i.k.| or |.k..j i...|
9773 */
9774 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9775 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9776 i = j;
9777 }
9778 }
9779
9780 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9781 {
9782
9783 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9784 sizeof(val));
9785 }
9786
9787 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9788 {
9789
9790 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9791 sizeof(u32));
9792 }
9793
9794 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9795 struct kvm_async_pf *work)
9796 {
9797 struct x86_exception fault;
9798
9799 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9800 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9801
9802 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9803 (vcpu->arch.apf.send_user_only &&
9804 kvm_x86_ops->get_cpl(vcpu) == 0))
9805 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9806 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9807 fault.vector = PF_VECTOR;
9808 fault.error_code_valid = true;
9809 fault.error_code = 0;
9810 fault.nested_page_fault = false;
9811 fault.address = work->arch.token;
9812 fault.async_page_fault = true;
9813 kvm_inject_page_fault(vcpu, &fault);
9814 }
9815 }
9816
9817 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9818 struct kvm_async_pf *work)
9819 {
9820 struct x86_exception fault;
9821 u32 val;
9822
9823 if (work->wakeup_all)
9824 work->arch.token = ~0; /* broadcast wakeup */
9825 else
9826 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9827 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9828
9829 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9830 !apf_get_user(vcpu, &val)) {
9831 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9832 vcpu->arch.exception.pending &&
9833 vcpu->arch.exception.nr == PF_VECTOR &&
9834 !apf_put_user(vcpu, 0)) {
9835 vcpu->arch.exception.injected = false;
9836 vcpu->arch.exception.pending = false;
9837 vcpu->arch.exception.nr = 0;
9838 vcpu->arch.exception.has_error_code = false;
9839 vcpu->arch.exception.error_code = 0;
9840 vcpu->arch.exception.has_payload = false;
9841 vcpu->arch.exception.payload = 0;
9842 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9843 fault.vector = PF_VECTOR;
9844 fault.error_code_valid = true;
9845 fault.error_code = 0;
9846 fault.nested_page_fault = false;
9847 fault.address = work->arch.token;
9848 fault.async_page_fault = true;
9849 kvm_inject_page_fault(vcpu, &fault);
9850 }
9851 }
9852 vcpu->arch.apf.halted = false;
9853 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9854 }
9855
9856 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9857 {
9858 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9859 return true;
9860 else
9861 return kvm_can_do_async_pf(vcpu);
9862 }
9863
9864 void kvm_arch_start_assignment(struct kvm *kvm)
9865 {
9866 atomic_inc(&kvm->arch.assigned_device_count);
9867 }
9868 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9869
9870 void kvm_arch_end_assignment(struct kvm *kvm)
9871 {
9872 atomic_dec(&kvm->arch.assigned_device_count);
9873 }
9874 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9875
9876 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9877 {
9878 return atomic_read(&kvm->arch.assigned_device_count);
9879 }
9880 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9881
9882 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9883 {
9884 atomic_inc(&kvm->arch.noncoherent_dma_count);
9885 }
9886 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9887
9888 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9889 {
9890 atomic_dec(&kvm->arch.noncoherent_dma_count);
9891 }
9892 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9893
9894 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9895 {
9896 return atomic_read(&kvm->arch.noncoherent_dma_count);
9897 }
9898 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9899
9900 bool kvm_arch_has_irq_bypass(void)
9901 {
9902 return kvm_x86_ops->update_pi_irte != NULL;
9903 }
9904
9905 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9906 struct irq_bypass_producer *prod)
9907 {
9908 struct kvm_kernel_irqfd *irqfd =
9909 container_of(cons, struct kvm_kernel_irqfd, consumer);
9910
9911 irqfd->producer = prod;
9912
9913 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9914 prod->irq, irqfd->gsi, 1);
9915 }
9916
9917 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9918 struct irq_bypass_producer *prod)
9919 {
9920 int ret;
9921 struct kvm_kernel_irqfd *irqfd =
9922 container_of(cons, struct kvm_kernel_irqfd, consumer);
9923
9924 WARN_ON(irqfd->producer != prod);
9925 irqfd->producer = NULL;
9926
9927 /*
9928 * When producer of consumer is unregistered, we change back to
9929 * remapped mode, so we can re-use the current implementation
9930 * when the irq is masked/disabled or the consumer side (KVM
9931 * int this case doesn't want to receive the interrupts.
9932 */
9933 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9934 if (ret)
9935 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9936 " fails: %d\n", irqfd->consumer.token, ret);
9937 }
9938
9939 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9940 uint32_t guest_irq, bool set)
9941 {
9942 if (!kvm_x86_ops->update_pi_irte)
9943 return -EINVAL;
9944
9945 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9946 }
9947
9948 bool kvm_vector_hashing_enabled(void)
9949 {
9950 return vector_hashing;
9951 }
9952 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9953
9954 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9955 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9956 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9957 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9958 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9959 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9960 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9961 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9962 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9963 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9964 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9965 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9966 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9967 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9968 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9969 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9970 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9971 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9972 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git