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Merge tag 'drm/tegra/for-5.1-rc5' of git://anongit.freedesktop.org/tegra/linux into...
[thirdparty/kernel/stable.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <drm/drm_cache.h>
25 #include "amdgpu.h"
26 #include "gmc_v9_0.h"
27 #include "amdgpu_atomfirmware.h"
28 #include "amdgpu_gem.h"
29
30 #include "hdp/hdp_4_0_offset.h"
31 #include "hdp/hdp_4_0_sh_mask.h"
32 #include "gc/gc_9_0_sh_mask.h"
33 #include "dce/dce_12_0_offset.h"
34 #include "dce/dce_12_0_sh_mask.h"
35 #include "vega10_enum.h"
36 #include "mmhub/mmhub_1_0_offset.h"
37 #include "athub/athub_1_0_offset.h"
38 #include "oss/osssys_4_0_offset.h"
39
40 #include "soc15.h"
41 #include "soc15_common.h"
42 #include "umc/umc_6_0_sh_mask.h"
43
44 #include "gfxhub_v1_0.h"
45 #include "mmhub_v1_0.h"
46 #include "gfxhub_v1_1.h"
47
48 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
49
50 /* add these here since we already include dce12 headers and these are for DCN */
51 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
52 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
53 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
54 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
55 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
56 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
57
58 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
59 #define AMDGPU_NUM_OF_VMIDS 8
60
61 static const u32 golden_settings_vega10_hdp[] =
62 {
63 0xf64, 0x0fffffff, 0x00000000,
64 0xf65, 0x0fffffff, 0x00000000,
65 0xf66, 0x0fffffff, 0x00000000,
66 0xf67, 0x0fffffff, 0x00000000,
67 0xf68, 0x0fffffff, 0x00000000,
68 0xf6a, 0x0fffffff, 0x00000000,
69 0xf6b, 0x0fffffff, 0x00000000,
70 0xf6c, 0x0fffffff, 0x00000000,
71 0xf6d, 0x0fffffff, 0x00000000,
72 0xf6e, 0x0fffffff, 0x00000000,
73 };
74
75 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
76 {
77 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
78 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
79 };
80
81 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
82 {
83 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
84 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
85 };
86
87 /* Ecc related register addresses, (BASE + reg offset) */
88 /* Universal Memory Controller caps (may be fused). */
89 /* UMCCH:UmcLocalCap */
90 #define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000)
91 #define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800)
92 #define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000)
93 #define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800)
94 #define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000)
95 #define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800)
96 #define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000)
97 #define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800)
98 #define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000)
99 #define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800)
100 #define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000)
101 #define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800)
102 #define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000)
103 #define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800)
104 #define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000)
105 #define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800)
106
107 /* Universal Memory Controller Channel config. */
108 /* UMCCH:UMC_CONFIG */
109 #define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000)
110 #define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800)
111 #define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000)
112 #define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800)
113 #define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000)
114 #define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800)
115 #define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000)
116 #define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800)
117 #define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000)
118 #define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800)
119 #define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
120 #define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
121 #define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
122 #define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
123 #define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
124 #define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
125
126 /* Universal Memory Controller Channel Ecc config. */
127 /* UMCCH:EccCtrl */
128 #define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000)
129 #define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800)
130 #define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000)
131 #define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800)
132 #define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000)
133 #define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800)
134 #define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000)
135 #define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800)
136 #define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000)
137 #define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800)
138 #define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000)
139 #define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800)
140 #define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000)
141 #define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800)
142 #define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000)
143 #define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800)
144
145 static const uint32_t ecc_umclocalcap_addrs[] = {
146 UMCLOCALCAPS_ADDR0,
147 UMCLOCALCAPS_ADDR1,
148 UMCLOCALCAPS_ADDR2,
149 UMCLOCALCAPS_ADDR3,
150 UMCLOCALCAPS_ADDR4,
151 UMCLOCALCAPS_ADDR5,
152 UMCLOCALCAPS_ADDR6,
153 UMCLOCALCAPS_ADDR7,
154 UMCLOCALCAPS_ADDR8,
155 UMCLOCALCAPS_ADDR9,
156 UMCLOCALCAPS_ADDR10,
157 UMCLOCALCAPS_ADDR11,
158 UMCLOCALCAPS_ADDR12,
159 UMCLOCALCAPS_ADDR13,
160 UMCLOCALCAPS_ADDR14,
161 UMCLOCALCAPS_ADDR15,
162 };
163
164 static const uint32_t ecc_umcch_umc_config_addrs[] = {
165 UMCCH_UMC_CONFIG_ADDR0,
166 UMCCH_UMC_CONFIG_ADDR1,
167 UMCCH_UMC_CONFIG_ADDR2,
168 UMCCH_UMC_CONFIG_ADDR3,
169 UMCCH_UMC_CONFIG_ADDR4,
170 UMCCH_UMC_CONFIG_ADDR5,
171 UMCCH_UMC_CONFIG_ADDR6,
172 UMCCH_UMC_CONFIG_ADDR7,
173 UMCCH_UMC_CONFIG_ADDR8,
174 UMCCH_UMC_CONFIG_ADDR9,
175 UMCCH_UMC_CONFIG_ADDR10,
176 UMCCH_UMC_CONFIG_ADDR11,
177 UMCCH_UMC_CONFIG_ADDR12,
178 UMCCH_UMC_CONFIG_ADDR13,
179 UMCCH_UMC_CONFIG_ADDR14,
180 UMCCH_UMC_CONFIG_ADDR15,
181 };
182
183 static const uint32_t ecc_umcch_eccctrl_addrs[] = {
184 UMCCH_ECCCTRL_ADDR0,
185 UMCCH_ECCCTRL_ADDR1,
186 UMCCH_ECCCTRL_ADDR2,
187 UMCCH_ECCCTRL_ADDR3,
188 UMCCH_ECCCTRL_ADDR4,
189 UMCCH_ECCCTRL_ADDR5,
190 UMCCH_ECCCTRL_ADDR6,
191 UMCCH_ECCCTRL_ADDR7,
192 UMCCH_ECCCTRL_ADDR8,
193 UMCCH_ECCCTRL_ADDR9,
194 UMCCH_ECCCTRL_ADDR10,
195 UMCCH_ECCCTRL_ADDR11,
196 UMCCH_ECCCTRL_ADDR12,
197 UMCCH_ECCCTRL_ADDR13,
198 UMCCH_ECCCTRL_ADDR14,
199 UMCCH_ECCCTRL_ADDR15,
200 };
201
202 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
203 struct amdgpu_irq_src *src,
204 unsigned type,
205 enum amdgpu_interrupt_state state)
206 {
207 struct amdgpu_vmhub *hub;
208 u32 tmp, reg, bits, i, j;
209
210 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
211 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
212 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
213 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
214 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
215 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
216 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
217
218 switch (state) {
219 case AMDGPU_IRQ_STATE_DISABLE:
220 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
221 hub = &adev->vmhub[j];
222 for (i = 0; i < 16; i++) {
223 reg = hub->vm_context0_cntl + i;
224 tmp = RREG32(reg);
225 tmp &= ~bits;
226 WREG32(reg, tmp);
227 }
228 }
229 break;
230 case AMDGPU_IRQ_STATE_ENABLE:
231 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
232 hub = &adev->vmhub[j];
233 for (i = 0; i < 16; i++) {
234 reg = hub->vm_context0_cntl + i;
235 tmp = RREG32(reg);
236 tmp |= bits;
237 WREG32(reg, tmp);
238 }
239 }
240 default:
241 break;
242 }
243
244 return 0;
245 }
246
247 /**
248 * vega10_ih_prescreen_iv - prescreen an interrupt vector
249 *
250 * @adev: amdgpu_device pointer
251 *
252 * Returns true if the interrupt vector should be further processed.
253 */
254 static bool gmc_v9_0_prescreen_iv(struct amdgpu_device *adev,
255 struct amdgpu_iv_entry *entry,
256 uint64_t addr)
257 {
258 struct amdgpu_vm *vm;
259 u64 key;
260 int r;
261
262 /* No PASID, can't identify faulting process */
263 if (!entry->pasid)
264 return true;
265
266 /* Not a retry fault */
267 if (!(entry->src_data[1] & 0x80))
268 return true;
269
270 /* Track retry faults in per-VM fault FIFO. */
271 spin_lock(&adev->vm_manager.pasid_lock);
272 vm = idr_find(&adev->vm_manager.pasid_idr, entry->pasid);
273 if (!vm) {
274 /* VM not found, process it normally */
275 spin_unlock(&adev->vm_manager.pasid_lock);
276 return true;
277 }
278
279 key = AMDGPU_VM_FAULT(entry->pasid, addr);
280 r = amdgpu_vm_add_fault(vm->fault_hash, key);
281
282 /* Hash table is full or the fault is already being processed,
283 * ignore further page faults
284 */
285 if (r != 0) {
286 spin_unlock(&adev->vm_manager.pasid_lock);
287 return false;
288 }
289 /* No locking required with single writer and single reader */
290 r = kfifo_put(&vm->faults, key);
291 if (!r) {
292 /* FIFO is full. Ignore it until there is space */
293 amdgpu_vm_clear_fault(vm->fault_hash, key);
294 spin_unlock(&adev->vm_manager.pasid_lock);
295 return false;
296 }
297
298 spin_unlock(&adev->vm_manager.pasid_lock);
299 /* It's the first fault for this address, process it normally */
300 return true;
301 }
302
303 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
304 struct amdgpu_irq_src *source,
305 struct amdgpu_iv_entry *entry)
306 {
307 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
308 bool retry_fault = !!(entry->src_data[1] & 0x80);
309 uint32_t status = 0;
310 u64 addr;
311
312 addr = (u64)entry->src_data[0] << 12;
313 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
314
315 if (!gmc_v9_0_prescreen_iv(adev, entry, addr))
316 return 1; /* This also prevents sending it to KFD */
317
318 if (!amdgpu_sriov_vf(adev)) {
319 status = RREG32(hub->vm_l2_pro_fault_status);
320 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
321 }
322
323 if (printk_ratelimit()) {
324 struct amdgpu_task_info task_info;
325
326 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
327 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
328
329 dev_err(adev->dev,
330 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
331 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
332 entry->vmid_src ? "mmhub" : "gfxhub",
333 retry_fault ? "retry" : "no-retry",
334 entry->src_id, entry->ring_id, entry->vmid,
335 entry->pasid, task_info.process_name, task_info.tgid,
336 task_info.task_name, task_info.pid);
337 dev_err(adev->dev, " in page starting at address 0x%016llx from %d\n",
338 addr, entry->client_id);
339 if (!amdgpu_sriov_vf(adev))
340 dev_err(adev->dev,
341 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
342 status);
343 }
344
345 return 0;
346 }
347
348 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
349 .set = gmc_v9_0_vm_fault_interrupt_state,
350 .process = gmc_v9_0_process_interrupt,
351 };
352
353 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
354 {
355 adev->gmc.vm_fault.num_types = 1;
356 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
357 }
358
359 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
360 uint32_t flush_type)
361 {
362 u32 req = 0;
363
364 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
365 PER_VMID_INVALIDATE_REQ, 1 << vmid);
366 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
367 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
368 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
369 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
370 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
371 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
372 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
373 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
374
375 return req;
376 }
377
378 /*
379 * GART
380 * VMID 0 is the physical GPU addresses as used by the kernel.
381 * VMIDs 1-15 are used for userspace clients and are handled
382 * by the amdgpu vm/hsa code.
383 */
384
385 /**
386 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
387 *
388 * @adev: amdgpu_device pointer
389 * @vmid: vm instance to flush
390 * @flush_type: the flush type
391 *
392 * Flush the TLB for the requested page table using certain type.
393 */
394 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
395 uint32_t vmid, uint32_t flush_type)
396 {
397 const unsigned eng = 17;
398 unsigned i, j;
399
400 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
401 struct amdgpu_vmhub *hub = &adev->vmhub[i];
402 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
403
404 /* This is necessary for a HW workaround under SRIOV as well
405 * as GFXOFF under bare metal
406 */
407 if (adev->gfx.kiq.ring.sched.ready &&
408 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
409 !adev->in_gpu_reset) {
410 uint32_t req = hub->vm_inv_eng0_req + eng;
411 uint32_t ack = hub->vm_inv_eng0_ack + eng;
412
413 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
414 1 << vmid);
415 continue;
416 }
417
418 spin_lock(&adev->gmc.invalidate_lock);
419 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
420 for (j = 0; j < adev->usec_timeout; j++) {
421 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
422 if (tmp & (1 << vmid))
423 break;
424 udelay(1);
425 }
426 spin_unlock(&adev->gmc.invalidate_lock);
427 if (j < adev->usec_timeout)
428 continue;
429
430 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
431 }
432 }
433
434 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
435 unsigned vmid, uint64_t pd_addr)
436 {
437 struct amdgpu_device *adev = ring->adev;
438 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
439 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
440 unsigned eng = ring->vm_inv_eng;
441
442 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
443 lower_32_bits(pd_addr));
444
445 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
446 upper_32_bits(pd_addr));
447
448 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
449 hub->vm_inv_eng0_ack + eng,
450 req, 1 << vmid);
451
452 return pd_addr;
453 }
454
455 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
456 unsigned pasid)
457 {
458 struct amdgpu_device *adev = ring->adev;
459 uint32_t reg;
460
461 if (ring->funcs->vmhub == AMDGPU_GFXHUB)
462 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
463 else
464 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
465
466 amdgpu_ring_emit_wreg(ring, reg, pasid);
467 }
468
469 /**
470 * gmc_v9_0_set_pte_pde - update the page tables using MMIO
471 *
472 * @adev: amdgpu_device pointer
473 * @cpu_pt_addr: cpu address of the page table
474 * @gpu_page_idx: entry in the page table to update
475 * @addr: dst addr to write into pte/pde
476 * @flags: access flags
477 *
478 * Update the page tables using the CPU.
479 */
480 static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
481 uint32_t gpu_page_idx, uint64_t addr,
482 uint64_t flags)
483 {
484 void __iomem *ptr = (void *)cpu_pt_addr;
485 uint64_t value;
486
487 /*
488 * PTE format on VEGA 10:
489 * 63:59 reserved
490 * 58:57 mtype
491 * 56 F
492 * 55 L
493 * 54 P
494 * 53 SW
495 * 52 T
496 * 50:48 reserved
497 * 47:12 4k physical page base address
498 * 11:7 fragment
499 * 6 write
500 * 5 read
501 * 4 exe
502 * 3 Z
503 * 2 snooped
504 * 1 system
505 * 0 valid
506 *
507 * PDE format on VEGA 10:
508 * 63:59 block fragment size
509 * 58:55 reserved
510 * 54 P
511 * 53:48 reserved
512 * 47:6 physical base address of PD or PTE
513 * 5:3 reserved
514 * 2 C
515 * 1 system
516 * 0 valid
517 */
518
519 /*
520 * The following is for PTE only. GART does not have PDEs.
521 */
522 value = addr & 0x0000FFFFFFFFF000ULL;
523 value |= flags;
524 writeq(value, ptr + (gpu_page_idx * 8));
525 return 0;
526 }
527
528 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
529 uint32_t flags)
530
531 {
532 uint64_t pte_flag = 0;
533
534 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
535 pte_flag |= AMDGPU_PTE_EXECUTABLE;
536 if (flags & AMDGPU_VM_PAGE_READABLE)
537 pte_flag |= AMDGPU_PTE_READABLE;
538 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
539 pte_flag |= AMDGPU_PTE_WRITEABLE;
540
541 switch (flags & AMDGPU_VM_MTYPE_MASK) {
542 case AMDGPU_VM_MTYPE_DEFAULT:
543 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
544 break;
545 case AMDGPU_VM_MTYPE_NC:
546 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
547 break;
548 case AMDGPU_VM_MTYPE_WC:
549 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
550 break;
551 case AMDGPU_VM_MTYPE_CC:
552 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
553 break;
554 case AMDGPU_VM_MTYPE_UC:
555 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
556 break;
557 default:
558 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
559 break;
560 }
561
562 if (flags & AMDGPU_VM_PAGE_PRT)
563 pte_flag |= AMDGPU_PTE_PRT;
564
565 return pte_flag;
566 }
567
568 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
569 uint64_t *addr, uint64_t *flags)
570 {
571 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
572 *addr = adev->vm_manager.vram_base_offset + *addr -
573 adev->gmc.vram_start;
574 BUG_ON(*addr & 0xFFFF00000000003FULL);
575
576 if (!adev->gmc.translate_further)
577 return;
578
579 if (level == AMDGPU_VM_PDB1) {
580 /* Set the block fragment size */
581 if (!(*flags & AMDGPU_PDE_PTE))
582 *flags |= AMDGPU_PDE_BFS(0x9);
583
584 } else if (level == AMDGPU_VM_PDB0) {
585 if (*flags & AMDGPU_PDE_PTE)
586 *flags &= ~AMDGPU_PDE_PTE;
587 else
588 *flags |= AMDGPU_PTE_TF;
589 }
590 }
591
592 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
593 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
594 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
595 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
596 .set_pte_pde = gmc_v9_0_set_pte_pde,
597 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
598 .get_vm_pde = gmc_v9_0_get_vm_pde
599 };
600
601 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
602 {
603 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
604 }
605
606 static int gmc_v9_0_early_init(void *handle)
607 {
608 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
609
610 gmc_v9_0_set_gmc_funcs(adev);
611 gmc_v9_0_set_irq_funcs(adev);
612
613 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
614 adev->gmc.shared_aperture_end =
615 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
616 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
617 adev->gmc.private_aperture_end =
618 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
619
620 return 0;
621 }
622
623 static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
624 {
625 uint32_t reg_val;
626 uint32_t reg_addr;
627 uint32_t field_val;
628 size_t i;
629 uint32_t fv2;
630 size_t lost_sheep;
631
632 DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
633
634 lost_sheep = 0;
635 for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
636 reg_addr = ecc_umclocalcap_addrs[i];
637 DRM_DEBUG("ecc: "
638 "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
639 i, reg_addr);
640 reg_val = RREG32(reg_addr);
641 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
642 EccDis);
643 DRM_DEBUG("ecc: "
644 "reg_val: 0x%08x, "
645 "EccDis: 0x%08x, ",
646 reg_val, field_val);
647 if (field_val) {
648 DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
649 ++lost_sheep;
650 }
651 }
652
653 for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
654 reg_addr = ecc_umcch_umc_config_addrs[i];
655 DRM_DEBUG("ecc: "
656 "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
657 i, reg_addr);
658 reg_val = RREG32(reg_addr);
659 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
660 DramReady);
661 DRM_DEBUG("ecc: "
662 "reg_val: 0x%08x, "
663 "DramReady: 0x%08x\n",
664 reg_val, field_val);
665
666 if (!field_val) {
667 DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
668 ++lost_sheep;
669 }
670 }
671
672 for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
673 reg_addr = ecc_umcch_eccctrl_addrs[i];
674 DRM_DEBUG("ecc: "
675 "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
676 i, reg_addr);
677 reg_val = RREG32(reg_addr);
678 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
679 WrEccEn);
680 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
681 RdEccEn);
682 DRM_DEBUG("ecc: "
683 "reg_val: 0x%08x, "
684 "WrEccEn: 0x%08x, "
685 "RdEccEn: 0x%08x\n",
686 reg_val, field_val, fv2);
687
688 if (!field_val) {
689 DRM_DEBUG("ecc: WrEccEn is not set\n");
690 ++lost_sheep;
691 }
692 if (!fv2) {
693 DRM_DEBUG("ecc: RdEccEn is not set\n");
694 ++lost_sheep;
695 }
696 }
697
698 DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
699 return lost_sheep == 0;
700 }
701
702 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
703 {
704
705 /*
706 * TODO:
707 * Currently there is a bug where some memory client outside
708 * of the driver writes to first 8M of VRAM on S3 resume,
709 * this overrides GART which by default gets placed in first 8M and
710 * causes VM_FAULTS once GTT is accessed.
711 * Keep the stolen memory reservation until the while this is not solved.
712 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
713 */
714 switch (adev->asic_type) {
715 case CHIP_VEGA10:
716 return true;
717 case CHIP_RAVEN:
718 case CHIP_VEGA12:
719 case CHIP_VEGA20:
720 default:
721 return false;
722 }
723 }
724
725 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
726 {
727 struct amdgpu_ring *ring;
728 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
729 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP};
730 unsigned i;
731 unsigned vmhub, inv_eng;
732
733 for (i = 0; i < adev->num_rings; ++i) {
734 ring = adev->rings[i];
735 vmhub = ring->funcs->vmhub;
736
737 inv_eng = ffs(vm_inv_engs[vmhub]);
738 if (!inv_eng) {
739 dev_err(adev->dev, "no VM inv eng for ring %s\n",
740 ring->name);
741 return -EINVAL;
742 }
743
744 ring->vm_inv_eng = inv_eng - 1;
745 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
746
747 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
748 ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
749 }
750
751 return 0;
752 }
753
754 static int gmc_v9_0_late_init(void *handle)
755 {
756 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
757 int r;
758
759 if (!gmc_v9_0_keep_stolen_memory(adev))
760 amdgpu_bo_late_init(adev);
761
762 r = gmc_v9_0_allocate_vm_inv_eng(adev);
763 if (r)
764 return r;
765
766 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
767 r = gmc_v9_0_ecc_available(adev);
768 if (r == 1) {
769 DRM_INFO("ECC is active.\n");
770 } else if (r == 0) {
771 DRM_INFO("ECC is not present.\n");
772 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
773 } else {
774 DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
775 return r;
776 }
777 }
778
779 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
780 }
781
782 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
783 struct amdgpu_gmc *mc)
784 {
785 u64 base = 0;
786 if (!amdgpu_sriov_vf(adev))
787 base = mmhub_v1_0_get_fb_location(adev);
788 /* add the xgmi offset of the physical node */
789 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
790 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
791 amdgpu_gmc_gart_location(adev, mc);
792 if (!amdgpu_sriov_vf(adev))
793 amdgpu_gmc_agp_location(adev, mc);
794 /* base offset of vram pages */
795 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
796
797 /* XXX: add the xgmi offset of the physical node? */
798 adev->vm_manager.vram_base_offset +=
799 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
800 }
801
802 /**
803 * gmc_v9_0_mc_init - initialize the memory controller driver params
804 *
805 * @adev: amdgpu_device pointer
806 *
807 * Look up the amount of vram, vram width, and decide how to place
808 * vram and gart within the GPU's physical address space.
809 * Returns 0 for success.
810 */
811 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
812 {
813 int chansize, numchan;
814 int r;
815
816 if (amdgpu_emu_mode != 1)
817 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
818 if (!adev->gmc.vram_width) {
819 /* hbm memory channel size */
820 if (adev->flags & AMD_IS_APU)
821 chansize = 64;
822 else
823 chansize = 128;
824
825 numchan = adev->df_funcs->get_hbm_channel_number(adev);
826 adev->gmc.vram_width = numchan * chansize;
827 }
828
829 /* size in MB on si */
830 adev->gmc.mc_vram_size =
831 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
832 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
833
834 if (!(adev->flags & AMD_IS_APU)) {
835 r = amdgpu_device_resize_fb_bar(adev);
836 if (r)
837 return r;
838 }
839 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
840 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
841
842 #ifdef CONFIG_X86_64
843 if (adev->flags & AMD_IS_APU) {
844 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
845 adev->gmc.aper_size = adev->gmc.real_vram_size;
846 }
847 #endif
848 /* In case the PCI BAR is larger than the actual amount of vram */
849 adev->gmc.visible_vram_size = adev->gmc.aper_size;
850 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
851 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
852
853 /* set the gart size */
854 if (amdgpu_gart_size == -1) {
855 switch (adev->asic_type) {
856 case CHIP_VEGA10: /* all engines support GPUVM */
857 case CHIP_VEGA12: /* all engines support GPUVM */
858 case CHIP_VEGA20:
859 default:
860 adev->gmc.gart_size = 512ULL << 20;
861 break;
862 case CHIP_RAVEN: /* DCE SG support */
863 adev->gmc.gart_size = 1024ULL << 20;
864 break;
865 }
866 } else {
867 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
868 }
869
870 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
871
872 return 0;
873 }
874
875 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
876 {
877 int r;
878
879 if (adev->gart.bo) {
880 WARN(1, "VEGA10 PCIE GART already initialized\n");
881 return 0;
882 }
883 /* Initialize common gart structure */
884 r = amdgpu_gart_init(adev);
885 if (r)
886 return r;
887 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
888 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
889 AMDGPU_PTE_EXECUTABLE;
890 return amdgpu_gart_table_vram_alloc(adev);
891 }
892
893 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
894 {
895 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
896 unsigned size;
897
898 /*
899 * TODO Remove once GART corruption is resolved
900 * Check related code in gmc_v9_0_sw_fini
901 * */
902 if (gmc_v9_0_keep_stolen_memory(adev))
903 return 9 * 1024 * 1024;
904
905 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
906 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
907 } else {
908 u32 viewport;
909
910 switch (adev->asic_type) {
911 case CHIP_RAVEN:
912 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
913 size = (REG_GET_FIELD(viewport,
914 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
915 REG_GET_FIELD(viewport,
916 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
917 4);
918 break;
919 case CHIP_VEGA10:
920 case CHIP_VEGA12:
921 case CHIP_VEGA20:
922 default:
923 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
924 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
925 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
926 4);
927 break;
928 }
929 }
930 /* return 0 if the pre-OS buffer uses up most of vram */
931 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
932 return 0;
933
934 return size;
935 }
936
937 static int gmc_v9_0_sw_init(void *handle)
938 {
939 int r;
940 int dma_bits;
941 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
942
943 gfxhub_v1_0_init(adev);
944 mmhub_v1_0_init(adev);
945
946 spin_lock_init(&adev->gmc.invalidate_lock);
947
948 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
949 switch (adev->asic_type) {
950 case CHIP_RAVEN:
951 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
952 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
953 } else {
954 /* vm_size is 128TB + 512GB for legacy 3-level page support */
955 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
956 adev->gmc.translate_further =
957 adev->vm_manager.num_level > 1;
958 }
959 break;
960 case CHIP_VEGA10:
961 case CHIP_VEGA12:
962 case CHIP_VEGA20:
963 /*
964 * To fulfill 4-level page support,
965 * vm size is 256TB (48bit), maximum size of Vega10,
966 * block size 512 (9bit)
967 */
968 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
969 if (amdgpu_sriov_vf(adev))
970 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
971 else
972 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
973 break;
974 default:
975 break;
976 }
977
978 /* This interrupt is VMC page fault.*/
979 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
980 &adev->gmc.vm_fault);
981 if (r)
982 return r;
983
984 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
985 &adev->gmc.vm_fault);
986
987 if (r)
988 return r;
989
990 /* Set the internal MC address mask
991 * This is the max address of the GPU's
992 * internal address space.
993 */
994 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
995
996 /* set DMA mask + need_dma32 flags.
997 * PCIE - can handle 44-bits.
998 * IGP - can handle 44-bits
999 * PCI - dma32 for legacy pci gart, 44 bits on vega10
1000 */
1001 adev->need_dma32 = false;
1002 dma_bits = adev->need_dma32 ? 32 : 44;
1003 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1004 if (r) {
1005 adev->need_dma32 = true;
1006 dma_bits = 32;
1007 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1008 }
1009 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1010 if (r) {
1011 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1012 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
1013 }
1014 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
1015
1016 if (adev->gmc.xgmi.supported) {
1017 r = gfxhub_v1_1_get_xgmi_info(adev);
1018 if (r)
1019 return r;
1020 }
1021
1022 r = gmc_v9_0_mc_init(adev);
1023 if (r)
1024 return r;
1025
1026 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1027
1028 /* Memory manager */
1029 r = amdgpu_bo_init(adev);
1030 if (r)
1031 return r;
1032
1033 r = gmc_v9_0_gart_init(adev);
1034 if (r)
1035 return r;
1036
1037 /*
1038 * number of VMs
1039 * VMID 0 is reserved for System
1040 * amdgpu graphics/compute will use VMIDs 1-7
1041 * amdkfd will use VMIDs 8-15
1042 */
1043 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
1044 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
1045
1046 amdgpu_vm_manager_init(adev);
1047
1048 return 0;
1049 }
1050
1051 static int gmc_v9_0_sw_fini(void *handle)
1052 {
1053 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054
1055 amdgpu_gem_force_release(adev);
1056 amdgpu_vm_manager_fini(adev);
1057
1058 if (gmc_v9_0_keep_stolen_memory(adev))
1059 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1060
1061 amdgpu_gart_table_vram_free(adev);
1062 amdgpu_bo_fini(adev);
1063 amdgpu_gart_fini(adev);
1064
1065 return 0;
1066 }
1067
1068 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1069 {
1070
1071 switch (adev->asic_type) {
1072 case CHIP_VEGA10:
1073 case CHIP_VEGA20:
1074 soc15_program_register_sequence(adev,
1075 golden_settings_mmhub_1_0_0,
1076 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1077 soc15_program_register_sequence(adev,
1078 golden_settings_athub_1_0_0,
1079 ARRAY_SIZE(golden_settings_athub_1_0_0));
1080 break;
1081 case CHIP_VEGA12:
1082 break;
1083 case CHIP_RAVEN:
1084 soc15_program_register_sequence(adev,
1085 golden_settings_athub_1_0_0,
1086 ARRAY_SIZE(golden_settings_athub_1_0_0));
1087 break;
1088 default:
1089 break;
1090 }
1091 }
1092
1093 /**
1094 * gmc_v9_0_gart_enable - gart enable
1095 *
1096 * @adev: amdgpu_device pointer
1097 */
1098 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1099 {
1100 int r;
1101 bool value;
1102 u32 tmp;
1103
1104 amdgpu_device_program_register_sequence(adev,
1105 golden_settings_vega10_hdp,
1106 ARRAY_SIZE(golden_settings_vega10_hdp));
1107
1108 if (adev->gart.bo == NULL) {
1109 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1110 return -EINVAL;
1111 }
1112 r = amdgpu_gart_table_vram_pin(adev);
1113 if (r)
1114 return r;
1115
1116 switch (adev->asic_type) {
1117 case CHIP_RAVEN:
1118 mmhub_v1_0_update_power_gating(adev, true);
1119 break;
1120 default:
1121 break;
1122 }
1123
1124 r = gfxhub_v1_0_gart_enable(adev);
1125 if (r)
1126 return r;
1127
1128 r = mmhub_v1_0_gart_enable(adev);
1129 if (r)
1130 return r;
1131
1132 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1133
1134 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1135 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1136
1137 /* After HDP is initialized, flush HDP.*/
1138 adev->nbio_funcs->hdp_flush(adev, NULL);
1139
1140 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1141 value = false;
1142 else
1143 value = true;
1144
1145 gfxhub_v1_0_set_fault_enable_default(adev, value);
1146 mmhub_v1_0_set_fault_enable_default(adev, value);
1147 gmc_v9_0_flush_gpu_tlb(adev, 0, 0);
1148
1149 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1150 (unsigned)(adev->gmc.gart_size >> 20),
1151 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1152 adev->gart.ready = true;
1153 return 0;
1154 }
1155
1156 static int gmc_v9_0_hw_init(void *handle)
1157 {
1158 int r;
1159 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1160
1161 /* The sequence of these two function calls matters.*/
1162 gmc_v9_0_init_golden_registers(adev);
1163
1164 if (adev->mode_info.num_crtc) {
1165 /* Lockout access through VGA aperture*/
1166 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1167
1168 /* disable VGA render */
1169 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1170 }
1171
1172 r = gmc_v9_0_gart_enable(adev);
1173
1174 return r;
1175 }
1176
1177 /**
1178 * gmc_v9_0_gart_disable - gart disable
1179 *
1180 * @adev: amdgpu_device pointer
1181 *
1182 * This disables all VM page table.
1183 */
1184 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1185 {
1186 gfxhub_v1_0_gart_disable(adev);
1187 mmhub_v1_0_gart_disable(adev);
1188 amdgpu_gart_table_vram_unpin(adev);
1189 }
1190
1191 static int gmc_v9_0_hw_fini(void *handle)
1192 {
1193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194
1195 if (amdgpu_sriov_vf(adev)) {
1196 /* full access mode, so don't touch any GMC register */
1197 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1198 return 0;
1199 }
1200
1201 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1202 gmc_v9_0_gart_disable(adev);
1203
1204 return 0;
1205 }
1206
1207 static int gmc_v9_0_suspend(void *handle)
1208 {
1209 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1210
1211 return gmc_v9_0_hw_fini(adev);
1212 }
1213
1214 static int gmc_v9_0_resume(void *handle)
1215 {
1216 int r;
1217 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218
1219 r = gmc_v9_0_hw_init(adev);
1220 if (r)
1221 return r;
1222
1223 amdgpu_vmid_reset_all(adev);
1224
1225 return 0;
1226 }
1227
1228 static bool gmc_v9_0_is_idle(void *handle)
1229 {
1230 /* MC is always ready in GMC v9.*/
1231 return true;
1232 }
1233
1234 static int gmc_v9_0_wait_for_idle(void *handle)
1235 {
1236 /* There is no need to wait for MC idle in GMC v9.*/
1237 return 0;
1238 }
1239
1240 static int gmc_v9_0_soft_reset(void *handle)
1241 {
1242 /* XXX for emulation.*/
1243 return 0;
1244 }
1245
1246 static int gmc_v9_0_set_clockgating_state(void *handle,
1247 enum amd_clockgating_state state)
1248 {
1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250
1251 return mmhub_v1_0_set_clockgating(adev, state);
1252 }
1253
1254 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1255 {
1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1257
1258 mmhub_v1_0_get_clockgating(adev, flags);
1259 }
1260
1261 static int gmc_v9_0_set_powergating_state(void *handle,
1262 enum amd_powergating_state state)
1263 {
1264 return 0;
1265 }
1266
1267 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1268 .name = "gmc_v9_0",
1269 .early_init = gmc_v9_0_early_init,
1270 .late_init = gmc_v9_0_late_init,
1271 .sw_init = gmc_v9_0_sw_init,
1272 .sw_fini = gmc_v9_0_sw_fini,
1273 .hw_init = gmc_v9_0_hw_init,
1274 .hw_fini = gmc_v9_0_hw_fini,
1275 .suspend = gmc_v9_0_suspend,
1276 .resume = gmc_v9_0_resume,
1277 .is_idle = gmc_v9_0_is_idle,
1278 .wait_for_idle = gmc_v9_0_wait_for_idle,
1279 .soft_reset = gmc_v9_0_soft_reset,
1280 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1281 .set_powergating_state = gmc_v9_0_set_powergating_state,
1282 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1283 };
1284
1285 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1286 {
1287 .type = AMD_IP_BLOCK_TYPE_GMC,
1288 .major = 9,
1289 .minor = 0,
1290 .rev = 0,
1291 .funcs = &gmc_v9_0_ip_funcs,
1292 };
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git