2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/reservation.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/i915_drm.h>
48 #include "i915_trace.h"
49 #include "intel_acpi.h"
50 #include "intel_atomic.h"
51 #include "intel_atomic_plane.h"
53 #include "intel_color.h"
54 #include "intel_cdclk.h"
55 #include "intel_crt.h"
56 #include "intel_ddi.h"
58 #include "intel_drv.h"
59 #include "intel_dsi.h"
60 #include "intel_dvo.h"
61 #include "intel_fbc.h"
62 #include "intel_fbdev.h"
63 #include "intel_fifo_underrun.h"
64 #include "intel_frontbuffer.h"
65 #include "intel_gmbus.h"
66 #include "intel_hdcp.h"
67 #include "intel_hdmi.h"
68 #include "intel_hotplug.h"
69 #include "intel_lvds.h"
70 #include "intel_overlay.h"
71 #include "intel_pipe_crc.h"
73 #include "intel_psr.h"
74 #include "intel_quirks.h"
75 #include "intel_sdvo.h"
76 #include "intel_sideband.h"
77 #include "intel_sprite.h"
79 #include "intel_vdsc.h"
81 /* Primary plane formats for gen <= 3 */
82 static const u32 i8xx_primary_formats
[] = {
89 /* Primary plane formats for gen >= 4 */
90 static const u32 i965_primary_formats
[] = {
95 DRM_FORMAT_XRGB2101010
,
96 DRM_FORMAT_XBGR2101010
,
99 static const u64 i9xx_format_modifiers
[] = {
100 I915_FORMAT_MOD_X_TILED
,
101 DRM_FORMAT_MOD_LINEAR
,
102 DRM_FORMAT_MOD_INVALID
106 static const u32 intel_cursor_formats
[] = {
110 static const u64 cursor_format_modifiers
[] = {
111 DRM_FORMAT_MOD_LINEAR
,
112 DRM_FORMAT_MOD_INVALID
115 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
116 struct intel_crtc_state
*pipe_config
);
117 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
118 struct intel_crtc_state
*pipe_config
);
120 static int intel_framebuffer_init(struct intel_framebuffer
*ifb
,
121 struct drm_i915_gem_object
*obj
,
122 struct drm_mode_fb_cmd2
*mode_cmd
);
123 static void intel_set_pipe_timings(const struct intel_crtc_state
*crtc_state
);
124 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
);
125 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
126 const struct intel_link_m_n
*m_n
,
127 const struct intel_link_m_n
*m2_n2
);
128 static void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
129 static void ironlake_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
130 static void haswell_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
131 static void bdw_set_pipemisc(const struct intel_crtc_state
*crtc_state
);
132 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
133 const struct intel_crtc_state
*pipe_config
);
134 static void chv_prepare_pll(struct intel_crtc
*crtc
,
135 const struct intel_crtc_state
*pipe_config
);
136 static void intel_begin_crtc_commit(struct intel_atomic_state
*, struct intel_crtc
*);
137 static void intel_finish_crtc_commit(struct intel_atomic_state
*, struct intel_crtc
*);
138 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
139 struct intel_crtc_state
*crtc_state
);
140 static void skylake_pfit_enable(const struct intel_crtc_state
*crtc_state
);
141 static void ironlake_pfit_disable(const struct intel_crtc_state
*old_crtc_state
);
142 static void ironlake_pfit_enable(const struct intel_crtc_state
*crtc_state
);
143 static void intel_modeset_setup_hw_state(struct drm_device
*dev
,
144 struct drm_modeset_acquire_ctx
*ctx
);
145 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
150 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
154 int p2_slow
, p2_fast
;
158 /* returns HPLL frequency in kHz */
159 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
)
161 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
163 /* Obtain SKU information */
164 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
165 CCK_FUSE_HPLL_FREQ_MASK
;
167 return vco_freq
[hpll_freq
] * 1000;
170 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
171 const char *name
, u32 reg
, int ref_freq
)
176 val
= vlv_cck_read(dev_priv
, reg
);
177 divider
= val
& CCK_FREQUENCY_VALUES
;
179 WARN((val
& CCK_FREQUENCY_STATUS
) !=
180 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
181 "%s change in progress\n", name
);
183 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
186 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
187 const char *name
, u32 reg
)
191 vlv_cck_get(dev_priv
);
193 if (dev_priv
->hpll_freq
== 0)
194 dev_priv
->hpll_freq
= vlv_get_hpll_vco(dev_priv
);
196 hpll
= vlv_get_cck_clock(dev_priv
, name
, reg
, dev_priv
->hpll_freq
);
198 vlv_cck_put(dev_priv
);
203 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
205 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
208 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
209 CCK_CZ_CLOCK_CONTROL
);
211 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
214 static inline u32
/* units of 100MHz */
215 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
216 const struct intel_crtc_state
*pipe_config
)
218 if (HAS_DDI(dev_priv
))
219 return pipe_config
->port_clock
; /* SPLL */
221 return dev_priv
->fdi_pll_freq
;
224 static const struct intel_limit intel_limits_i8xx_dac
= {
225 .dot
= { .min
= 25000, .max
= 350000 },
226 .vco
= { .min
= 908000, .max
= 1512000 },
227 .n
= { .min
= 2, .max
= 16 },
228 .m
= { .min
= 96, .max
= 140 },
229 .m1
= { .min
= 18, .max
= 26 },
230 .m2
= { .min
= 6, .max
= 16 },
231 .p
= { .min
= 4, .max
= 128 },
232 .p1
= { .min
= 2, .max
= 33 },
233 .p2
= { .dot_limit
= 165000,
234 .p2_slow
= 4, .p2_fast
= 2 },
237 static const struct intel_limit intel_limits_i8xx_dvo
= {
238 .dot
= { .min
= 25000, .max
= 350000 },
239 .vco
= { .min
= 908000, .max
= 1512000 },
240 .n
= { .min
= 2, .max
= 16 },
241 .m
= { .min
= 96, .max
= 140 },
242 .m1
= { .min
= 18, .max
= 26 },
243 .m2
= { .min
= 6, .max
= 16 },
244 .p
= { .min
= 4, .max
= 128 },
245 .p1
= { .min
= 2, .max
= 33 },
246 .p2
= { .dot_limit
= 165000,
247 .p2_slow
= 4, .p2_fast
= 4 },
250 static const struct intel_limit intel_limits_i8xx_lvds
= {
251 .dot
= { .min
= 25000, .max
= 350000 },
252 .vco
= { .min
= 908000, .max
= 1512000 },
253 .n
= { .min
= 2, .max
= 16 },
254 .m
= { .min
= 96, .max
= 140 },
255 .m1
= { .min
= 18, .max
= 26 },
256 .m2
= { .min
= 6, .max
= 16 },
257 .p
= { .min
= 4, .max
= 128 },
258 .p1
= { .min
= 1, .max
= 6 },
259 .p2
= { .dot_limit
= 165000,
260 .p2_slow
= 14, .p2_fast
= 7 },
263 static const struct intel_limit intel_limits_i9xx_sdvo
= {
264 .dot
= { .min
= 20000, .max
= 400000 },
265 .vco
= { .min
= 1400000, .max
= 2800000 },
266 .n
= { .min
= 1, .max
= 6 },
267 .m
= { .min
= 70, .max
= 120 },
268 .m1
= { .min
= 8, .max
= 18 },
269 .m2
= { .min
= 3, .max
= 7 },
270 .p
= { .min
= 5, .max
= 80 },
271 .p1
= { .min
= 1, .max
= 8 },
272 .p2
= { .dot_limit
= 200000,
273 .p2_slow
= 10, .p2_fast
= 5 },
276 static const struct intel_limit intel_limits_i9xx_lvds
= {
277 .dot
= { .min
= 20000, .max
= 400000 },
278 .vco
= { .min
= 1400000, .max
= 2800000 },
279 .n
= { .min
= 1, .max
= 6 },
280 .m
= { .min
= 70, .max
= 120 },
281 .m1
= { .min
= 8, .max
= 18 },
282 .m2
= { .min
= 3, .max
= 7 },
283 .p
= { .min
= 7, .max
= 98 },
284 .p1
= { .min
= 1, .max
= 8 },
285 .p2
= { .dot_limit
= 112000,
286 .p2_slow
= 14, .p2_fast
= 7 },
290 static const struct intel_limit intel_limits_g4x_sdvo
= {
291 .dot
= { .min
= 25000, .max
= 270000 },
292 .vco
= { .min
= 1750000, .max
= 3500000},
293 .n
= { .min
= 1, .max
= 4 },
294 .m
= { .min
= 104, .max
= 138 },
295 .m1
= { .min
= 17, .max
= 23 },
296 .m2
= { .min
= 5, .max
= 11 },
297 .p
= { .min
= 10, .max
= 30 },
298 .p1
= { .min
= 1, .max
= 3},
299 .p2
= { .dot_limit
= 270000,
305 static const struct intel_limit intel_limits_g4x_hdmi
= {
306 .dot
= { .min
= 22000, .max
= 400000 },
307 .vco
= { .min
= 1750000, .max
= 3500000},
308 .n
= { .min
= 1, .max
= 4 },
309 .m
= { .min
= 104, .max
= 138 },
310 .m1
= { .min
= 16, .max
= 23 },
311 .m2
= { .min
= 5, .max
= 11 },
312 .p
= { .min
= 5, .max
= 80 },
313 .p1
= { .min
= 1, .max
= 8},
314 .p2
= { .dot_limit
= 165000,
315 .p2_slow
= 10, .p2_fast
= 5 },
318 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
319 .dot
= { .min
= 20000, .max
= 115000 },
320 .vco
= { .min
= 1750000, .max
= 3500000 },
321 .n
= { .min
= 1, .max
= 3 },
322 .m
= { .min
= 104, .max
= 138 },
323 .m1
= { .min
= 17, .max
= 23 },
324 .m2
= { .min
= 5, .max
= 11 },
325 .p
= { .min
= 28, .max
= 112 },
326 .p1
= { .min
= 2, .max
= 8 },
327 .p2
= { .dot_limit
= 0,
328 .p2_slow
= 14, .p2_fast
= 14
332 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
333 .dot
= { .min
= 80000, .max
= 224000 },
334 .vco
= { .min
= 1750000, .max
= 3500000 },
335 .n
= { .min
= 1, .max
= 3 },
336 .m
= { .min
= 104, .max
= 138 },
337 .m1
= { .min
= 17, .max
= 23 },
338 .m2
= { .min
= 5, .max
= 11 },
339 .p
= { .min
= 14, .max
= 42 },
340 .p1
= { .min
= 2, .max
= 6 },
341 .p2
= { .dot_limit
= 0,
342 .p2_slow
= 7, .p2_fast
= 7
346 static const struct intel_limit intel_limits_pineview_sdvo
= {
347 .dot
= { .min
= 20000, .max
= 400000},
348 .vco
= { .min
= 1700000, .max
= 3500000 },
349 /* Pineview's Ncounter is a ring counter */
350 .n
= { .min
= 3, .max
= 6 },
351 .m
= { .min
= 2, .max
= 256 },
352 /* Pineview only has one combined m divider, which we treat as m2. */
353 .m1
= { .min
= 0, .max
= 0 },
354 .m2
= { .min
= 0, .max
= 254 },
355 .p
= { .min
= 5, .max
= 80 },
356 .p1
= { .min
= 1, .max
= 8 },
357 .p2
= { .dot_limit
= 200000,
358 .p2_slow
= 10, .p2_fast
= 5 },
361 static const struct intel_limit intel_limits_pineview_lvds
= {
362 .dot
= { .min
= 20000, .max
= 400000 },
363 .vco
= { .min
= 1700000, .max
= 3500000 },
364 .n
= { .min
= 3, .max
= 6 },
365 .m
= { .min
= 2, .max
= 256 },
366 .m1
= { .min
= 0, .max
= 0 },
367 .m2
= { .min
= 0, .max
= 254 },
368 .p
= { .min
= 7, .max
= 112 },
369 .p1
= { .min
= 1, .max
= 8 },
370 .p2
= { .dot_limit
= 112000,
371 .p2_slow
= 14, .p2_fast
= 14 },
374 /* Ironlake / Sandybridge
376 * We calculate clock using (register_value + 2) for N/M1/M2, so here
377 * the range value for them is (actual_value - 2).
379 static const struct intel_limit intel_limits_ironlake_dac
= {
380 .dot
= { .min
= 25000, .max
= 350000 },
381 .vco
= { .min
= 1760000, .max
= 3510000 },
382 .n
= { .min
= 1, .max
= 5 },
383 .m
= { .min
= 79, .max
= 127 },
384 .m1
= { .min
= 12, .max
= 22 },
385 .m2
= { .min
= 5, .max
= 9 },
386 .p
= { .min
= 5, .max
= 80 },
387 .p1
= { .min
= 1, .max
= 8 },
388 .p2
= { .dot_limit
= 225000,
389 .p2_slow
= 10, .p2_fast
= 5 },
392 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
393 .dot
= { .min
= 25000, .max
= 350000 },
394 .vco
= { .min
= 1760000, .max
= 3510000 },
395 .n
= { .min
= 1, .max
= 3 },
396 .m
= { .min
= 79, .max
= 118 },
397 .m1
= { .min
= 12, .max
= 22 },
398 .m2
= { .min
= 5, .max
= 9 },
399 .p
= { .min
= 28, .max
= 112 },
400 .p1
= { .min
= 2, .max
= 8 },
401 .p2
= { .dot_limit
= 225000,
402 .p2_slow
= 14, .p2_fast
= 14 },
405 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
406 .dot
= { .min
= 25000, .max
= 350000 },
407 .vco
= { .min
= 1760000, .max
= 3510000 },
408 .n
= { .min
= 1, .max
= 3 },
409 .m
= { .min
= 79, .max
= 127 },
410 .m1
= { .min
= 12, .max
= 22 },
411 .m2
= { .min
= 5, .max
= 9 },
412 .p
= { .min
= 14, .max
= 56 },
413 .p1
= { .min
= 2, .max
= 8 },
414 .p2
= { .dot_limit
= 225000,
415 .p2_slow
= 7, .p2_fast
= 7 },
418 /* LVDS 100mhz refclk limits. */
419 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
420 .dot
= { .min
= 25000, .max
= 350000 },
421 .vco
= { .min
= 1760000, .max
= 3510000 },
422 .n
= { .min
= 1, .max
= 2 },
423 .m
= { .min
= 79, .max
= 126 },
424 .m1
= { .min
= 12, .max
= 22 },
425 .m2
= { .min
= 5, .max
= 9 },
426 .p
= { .min
= 28, .max
= 112 },
427 .p1
= { .min
= 2, .max
= 8 },
428 .p2
= { .dot_limit
= 225000,
429 .p2_slow
= 14, .p2_fast
= 14 },
432 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
433 .dot
= { .min
= 25000, .max
= 350000 },
434 .vco
= { .min
= 1760000, .max
= 3510000 },
435 .n
= { .min
= 1, .max
= 3 },
436 .m
= { .min
= 79, .max
= 126 },
437 .m1
= { .min
= 12, .max
= 22 },
438 .m2
= { .min
= 5, .max
= 9 },
439 .p
= { .min
= 14, .max
= 42 },
440 .p1
= { .min
= 2, .max
= 6 },
441 .p2
= { .dot_limit
= 225000,
442 .p2_slow
= 7, .p2_fast
= 7 },
445 static const struct intel_limit intel_limits_vlv
= {
447 * These are the data rate limits (measured in fast clocks)
448 * since those are the strictest limits we have. The fast
449 * clock and actual rate limits are more relaxed, so checking
450 * them would make no difference.
452 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
453 .vco
= { .min
= 4000000, .max
= 6000000 },
454 .n
= { .min
= 1, .max
= 7 },
455 .m1
= { .min
= 2, .max
= 3 },
456 .m2
= { .min
= 11, .max
= 156 },
457 .p1
= { .min
= 2, .max
= 3 },
458 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
461 static const struct intel_limit intel_limits_chv
= {
463 * These are the data rate limits (measured in fast clocks)
464 * since those are the strictest limits we have. The fast
465 * clock and actual rate limits are more relaxed, so checking
466 * them would make no difference.
468 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
469 .vco
= { .min
= 4800000, .max
= 6480000 },
470 .n
= { .min
= 1, .max
= 1 },
471 .m1
= { .min
= 2, .max
= 2 },
472 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
473 .p1
= { .min
= 2, .max
= 4 },
474 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
477 static const struct intel_limit intel_limits_bxt
= {
478 /* FIXME: find real dot limits */
479 .dot
= { .min
= 0, .max
= INT_MAX
},
480 .vco
= { .min
= 4800000, .max
= 6700000 },
481 .n
= { .min
= 1, .max
= 1 },
482 .m1
= { .min
= 2, .max
= 2 },
483 /* FIXME: find real m2 limits */
484 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
485 .p1
= { .min
= 2, .max
= 4 },
486 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
489 /* WA Display #0827: Gen9:all */
491 skl_wa_827(struct drm_i915_private
*dev_priv
, int pipe
, bool enable
)
494 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
495 I915_READ(CLKGATE_DIS_PSL(pipe
)) |
496 DUPS1_GATING_DIS
| DUPS2_GATING_DIS
);
498 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
499 I915_READ(CLKGATE_DIS_PSL(pipe
)) &
500 ~(DUPS1_GATING_DIS
| DUPS2_GATING_DIS
));
503 /* Wa_2006604312:icl */
505 icl_wa_scalerclkgating(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
509 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
510 I915_READ(CLKGATE_DIS_PSL(pipe
)) | DPFR_GATING_DIS
);
512 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
513 I915_READ(CLKGATE_DIS_PSL(pipe
)) & ~DPFR_GATING_DIS
);
517 needs_modeset(const struct drm_crtc_state
*state
)
519 return drm_atomic_crtc_needs_modeset(state
);
523 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
524 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
525 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
526 * The helpers' return value is the rate of the clock that is fed to the
527 * display engine's pipe which can be the above fast dot clock rate or a
528 * divided-down version of it.
530 /* m1 is reserved as 0 in Pineview, n is a ring counter */
531 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
533 clock
->m
= clock
->m2
+ 2;
534 clock
->p
= clock
->p1
* clock
->p2
;
535 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
537 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
538 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
543 static u32
i9xx_dpll_compute_m(struct dpll
*dpll
)
545 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
548 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
550 clock
->m
= i9xx_dpll_compute_m(clock
);
551 clock
->p
= clock
->p1
* clock
->p2
;
552 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
554 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
555 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
560 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
562 clock
->m
= clock
->m1
* clock
->m2
;
563 clock
->p
= clock
->p1
* clock
->p2
;
564 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
566 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
567 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
569 return clock
->dot
/ 5;
572 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
574 clock
->m
= clock
->m1
* clock
->m2
;
575 clock
->p
= clock
->p1
* clock
->p2
;
576 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
578 clock
->vco
= DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk
, clock
->m
),
580 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
582 return clock
->dot
/ 5;
585 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
588 * Returns whether the given set of divisors are valid for a given refclk with
589 * the given connectors.
591 static bool intel_PLL_is_valid(struct drm_i915_private
*dev_priv
,
592 const struct intel_limit
*limit
,
593 const struct dpll
*clock
)
595 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
596 INTELPllInvalid("n out of range\n");
597 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
598 INTELPllInvalid("p1 out of range\n");
599 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
600 INTELPllInvalid("m2 out of range\n");
601 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
602 INTELPllInvalid("m1 out of range\n");
604 if (!IS_PINEVIEW(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
605 !IS_CHERRYVIEW(dev_priv
) && !IS_GEN9_LP(dev_priv
))
606 if (clock
->m1
<= clock
->m2
)
607 INTELPllInvalid("m1 <= m2\n");
609 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
610 !IS_GEN9_LP(dev_priv
)) {
611 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
612 INTELPllInvalid("p out of range\n");
613 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
614 INTELPllInvalid("m out of range\n");
617 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
618 INTELPllInvalid("vco out of range\n");
619 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
620 * connector, etc., rather than just a single range.
622 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
623 INTELPllInvalid("dot out of range\n");
629 i9xx_select_p2_div(const struct intel_limit
*limit
,
630 const struct intel_crtc_state
*crtc_state
,
633 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
635 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
641 if (intel_is_dual_link_lvds(dev_priv
))
642 return limit
->p2
.p2_fast
;
644 return limit
->p2
.p2_slow
;
646 if (target
< limit
->p2
.dot_limit
)
647 return limit
->p2
.p2_slow
;
649 return limit
->p2
.p2_fast
;
654 * Returns a set of divisors for the desired target clock with the given
655 * refclk, or FALSE. The returned values represent the clock equation:
656 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
658 * Target and reference clocks are specified in kHz.
660 * If match_clock is provided, then best_clock P divider must match the P
661 * divider from @match_clock used for LVDS downclocking.
664 i9xx_find_best_dpll(const struct intel_limit
*limit
,
665 struct intel_crtc_state
*crtc_state
,
666 int target
, int refclk
, struct dpll
*match_clock
,
667 struct dpll
*best_clock
)
669 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
673 memset(best_clock
, 0, sizeof(*best_clock
));
675 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
677 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
679 for (clock
.m2
= limit
->m2
.min
;
680 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
681 if (clock
.m2
>= clock
.m1
)
683 for (clock
.n
= limit
->n
.min
;
684 clock
.n
<= limit
->n
.max
; clock
.n
++) {
685 for (clock
.p1
= limit
->p1
.min
;
686 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
689 i9xx_calc_dpll_params(refclk
, &clock
);
690 if (!intel_PLL_is_valid(to_i915(dev
),
695 clock
.p
!= match_clock
->p
)
698 this_err
= abs(clock
.dot
- target
);
699 if (this_err
< err
) {
708 return (err
!= target
);
712 * Returns a set of divisors for the desired target clock with the given
713 * refclk, or FALSE. The returned values represent the clock equation:
714 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
716 * Target and reference clocks are specified in kHz.
718 * If match_clock is provided, then best_clock P divider must match the P
719 * divider from @match_clock used for LVDS downclocking.
722 pnv_find_best_dpll(const struct intel_limit
*limit
,
723 struct intel_crtc_state
*crtc_state
,
724 int target
, int refclk
, struct dpll
*match_clock
,
725 struct dpll
*best_clock
)
727 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
731 memset(best_clock
, 0, sizeof(*best_clock
));
733 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
735 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
737 for (clock
.m2
= limit
->m2
.min
;
738 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
739 for (clock
.n
= limit
->n
.min
;
740 clock
.n
<= limit
->n
.max
; clock
.n
++) {
741 for (clock
.p1
= limit
->p1
.min
;
742 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
745 pnv_calc_dpll_params(refclk
, &clock
);
746 if (!intel_PLL_is_valid(to_i915(dev
),
751 clock
.p
!= match_clock
->p
)
754 this_err
= abs(clock
.dot
- target
);
755 if (this_err
< err
) {
764 return (err
!= target
);
768 * Returns a set of divisors for the desired target clock with the given
769 * refclk, or FALSE. The returned values represent the clock equation:
770 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
772 * Target and reference clocks are specified in kHz.
774 * If match_clock is provided, then best_clock P divider must match the P
775 * divider from @match_clock used for LVDS downclocking.
778 g4x_find_best_dpll(const struct intel_limit
*limit
,
779 struct intel_crtc_state
*crtc_state
,
780 int target
, int refclk
, struct dpll
*match_clock
,
781 struct dpll
*best_clock
)
783 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
787 /* approximately equals target * 0.00585 */
788 int err_most
= (target
>> 8) + (target
>> 9);
790 memset(best_clock
, 0, sizeof(*best_clock
));
792 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
794 max_n
= limit
->n
.max
;
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
797 /* based on hardware requirement, prefere larger m1,m2 */
798 for (clock
.m1
= limit
->m1
.max
;
799 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
800 for (clock
.m2
= limit
->m2
.max
;
801 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
802 for (clock
.p1
= limit
->p1
.max
;
803 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
806 i9xx_calc_dpll_params(refclk
, &clock
);
807 if (!intel_PLL_is_valid(to_i915(dev
),
812 this_err
= abs(clock
.dot
- target
);
813 if (this_err
< err_most
) {
827 * Check if the calculated PLL configuration is more optimal compared to the
828 * best configuration and error found so far. Return the calculated error.
830 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
831 const struct dpll
*calculated_clock
,
832 const struct dpll
*best_clock
,
833 unsigned int best_error_ppm
,
834 unsigned int *error_ppm
)
837 * For CHV ignore the error and consider only the P value.
838 * Prefer a bigger P value based on HW requirements.
840 if (IS_CHERRYVIEW(to_i915(dev
))) {
843 return calculated_clock
->p
> best_clock
->p
;
846 if (WARN_ON_ONCE(!target_freq
))
849 *error_ppm
= div_u64(1000000ULL *
850 abs(target_freq
- calculated_clock
->dot
),
853 * Prefer a better P value over a better (smaller) error if the error
854 * is small. Ensure this preference for future configurations too by
855 * setting the error to 0.
857 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
863 return *error_ppm
+ 10 < best_error_ppm
;
867 * Returns a set of divisors for the desired target clock with the given
868 * refclk, or FALSE. The returned values represent the clock equation:
869 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
872 vlv_find_best_dpll(const struct intel_limit
*limit
,
873 struct intel_crtc_state
*crtc_state
,
874 int target
, int refclk
, struct dpll
*match_clock
,
875 struct dpll
*best_clock
)
877 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
878 struct drm_device
*dev
= crtc
->base
.dev
;
880 unsigned int bestppm
= 1000000;
881 /* min update 19.2 MHz */
882 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
885 target
*= 5; /* fast clock */
887 memset(best_clock
, 0, sizeof(*best_clock
));
889 /* based on hardware requirement, prefer smaller n to precision */
890 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
891 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
892 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
893 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
894 clock
.p
= clock
.p1
* clock
.p2
;
895 /* based on hardware requirement, prefer bigger m1,m2 values */
896 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
899 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
902 vlv_calc_dpll_params(refclk
, &clock
);
904 if (!intel_PLL_is_valid(to_i915(dev
),
909 if (!vlv_PLL_is_optimal(dev
, target
,
927 * Returns a set of divisors for the desired target clock with the given
928 * refclk, or FALSE. The returned values represent the clock equation:
929 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
932 chv_find_best_dpll(const struct intel_limit
*limit
,
933 struct intel_crtc_state
*crtc_state
,
934 int target
, int refclk
, struct dpll
*match_clock
,
935 struct dpll
*best_clock
)
937 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
938 struct drm_device
*dev
= crtc
->base
.dev
;
939 unsigned int best_error_ppm
;
944 memset(best_clock
, 0, sizeof(*best_clock
));
945 best_error_ppm
= 1000000;
948 * Based on hardware doc, the n always set to 1, and m1 always
949 * set to 2. If requires to support 200Mhz refclk, we need to
950 * revisit this because n may not 1 anymore.
952 clock
.n
= 1, clock
.m1
= 2;
953 target
*= 5; /* fast clock */
955 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
956 for (clock
.p2
= limit
->p2
.p2_fast
;
957 clock
.p2
>= limit
->p2
.p2_slow
;
958 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
959 unsigned int error_ppm
;
961 clock
.p
= clock
.p1
* clock
.p2
;
963 m2
= DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target
, clock
.p
* clock
.n
) << 22,
966 if (m2
> INT_MAX
/clock
.m1
)
971 chv_calc_dpll_params(refclk
, &clock
);
973 if (!intel_PLL_is_valid(to_i915(dev
), limit
, &clock
))
976 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
977 best_error_ppm
, &error_ppm
))
981 best_error_ppm
= error_ppm
;
989 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
,
990 struct dpll
*best_clock
)
993 const struct intel_limit
*limit
= &intel_limits_bxt
;
995 return chv_find_best_dpll(limit
, crtc_state
,
996 crtc_state
->port_clock
, refclk
,
1000 bool intel_crtc_active(struct intel_crtc
*crtc
)
1002 /* Be paranoid as we can arrive here with only partial
1003 * state retrieved from the hardware during setup.
1005 * We can ditch the adjusted_mode.crtc_clock check as soon
1006 * as Haswell has gained clock readout/fastboot support.
1008 * We can ditch the crtc->primary->state->fb check as soon as we can
1009 * properly reconstruct framebuffers.
1011 * FIXME: The intel_crtc->active here should be switched to
1012 * crtc->state->active once we have proper CRTC states wired up
1015 return crtc
->active
&& crtc
->base
.primary
->state
->fb
&&
1016 crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1019 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1022 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1024 return crtc
->config
->cpu_transcoder
;
1027 static bool pipe_scanline_is_moving(struct drm_i915_private
*dev_priv
,
1030 i915_reg_t reg
= PIPEDSL(pipe
);
1034 if (IS_GEN(dev_priv
, 2))
1035 line_mask
= DSL_LINEMASK_GEN2
;
1037 line_mask
= DSL_LINEMASK_GEN3
;
1039 line1
= I915_READ(reg
) & line_mask
;
1041 line2
= I915_READ(reg
) & line_mask
;
1043 return line1
!= line2
;
1046 static void wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
, bool state
)
1048 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1049 enum pipe pipe
= crtc
->pipe
;
1051 /* Wait for the display line to settle/start moving */
1052 if (wait_for(pipe_scanline_is_moving(dev_priv
, pipe
) == state
, 100))
1053 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1054 pipe_name(pipe
), onoff(state
));
1057 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc
*crtc
)
1059 wait_for_pipe_scanline_moving(crtc
, false);
1062 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
)
1064 wait_for_pipe_scanline_moving(crtc
, true);
1068 intel_wait_for_pipe_off(const struct intel_crtc_state
*old_crtc_state
)
1070 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1071 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1073 if (INTEL_GEN(dev_priv
) >= 4) {
1074 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
1075 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1077 /* Wait for the Pipe State to go off */
1078 if (intel_wait_for_register(&dev_priv
->uncore
,
1079 reg
, I965_PIPECONF_ACTIVE
, 0,
1081 WARN(1, "pipe_off wait timed out\n");
1083 intel_wait_for_pipe_scanline_stopped(crtc
);
1087 /* Only for pre-ILK configs */
1088 void assert_pll(struct drm_i915_private
*dev_priv
,
1089 enum pipe pipe
, bool state
)
1094 val
= I915_READ(DPLL(pipe
));
1095 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1096 I915_STATE_WARN(cur_state
!= state
,
1097 "PLL state assertion failure (expected %s, current %s)\n",
1098 onoff(state
), onoff(cur_state
));
1101 /* XXX: the dsi pll is shared between MIPI DSI ports */
1102 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1107 vlv_cck_get(dev_priv
);
1108 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1109 vlv_cck_put(dev_priv
);
1111 cur_state
= val
& DSI_PLL_VCO_EN
;
1112 I915_STATE_WARN(cur_state
!= state
,
1113 "DSI PLL state assertion failure (expected %s, current %s)\n",
1114 onoff(state
), onoff(cur_state
));
1117 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1118 enum pipe pipe
, bool state
)
1121 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1124 if (HAS_DDI(dev_priv
)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1127 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1129 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1130 cur_state
= !!(val
& FDI_TX_ENABLE
);
1132 I915_STATE_WARN(cur_state
!= state
,
1133 "FDI TX state assertion failure (expected %s, current %s)\n",
1134 onoff(state
), onoff(cur_state
));
1136 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1137 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1139 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1140 enum pipe pipe
, bool state
)
1145 val
= I915_READ(FDI_RX_CTL(pipe
));
1146 cur_state
= !!(val
& FDI_RX_ENABLE
);
1147 I915_STATE_WARN(cur_state
!= state
,
1148 "FDI RX state assertion failure (expected %s, current %s)\n",
1149 onoff(state
), onoff(cur_state
));
1151 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1152 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1159 /* ILK FDI PLL is always enabled */
1160 if (IS_GEN(dev_priv
, 5))
1163 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1164 if (HAS_DDI(dev_priv
))
1167 val
= I915_READ(FDI_TX_CTL(pipe
));
1168 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1171 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1172 enum pipe pipe
, bool state
)
1177 val
= I915_READ(FDI_RX_CTL(pipe
));
1178 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1179 I915_STATE_WARN(cur_state
!= state
,
1180 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1181 onoff(state
), onoff(cur_state
));
1184 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1188 enum pipe panel_pipe
= INVALID_PIPE
;
1191 if (WARN_ON(HAS_DDI(dev_priv
)))
1194 if (HAS_PCH_SPLIT(dev_priv
)) {
1197 pp_reg
= PP_CONTROL(0);
1198 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1201 case PANEL_PORT_SELECT_LVDS
:
1202 intel_lvds_port_enabled(dev_priv
, PCH_LVDS
, &panel_pipe
);
1204 case PANEL_PORT_SELECT_DPA
:
1205 intel_dp_port_enabled(dev_priv
, DP_A
, PORT_A
, &panel_pipe
);
1207 case PANEL_PORT_SELECT_DPC
:
1208 intel_dp_port_enabled(dev_priv
, PCH_DP_C
, PORT_C
, &panel_pipe
);
1210 case PANEL_PORT_SELECT_DPD
:
1211 intel_dp_port_enabled(dev_priv
, PCH_DP_D
, PORT_D
, &panel_pipe
);
1214 MISSING_CASE(port_sel
);
1217 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg
= PP_CONTROL(pipe
);
1224 pp_reg
= PP_CONTROL(0);
1225 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1227 WARN_ON(port_sel
!= PANEL_PORT_SELECT_LVDS
);
1228 intel_lvds_port_enabled(dev_priv
, LVDS
, &panel_pipe
);
1231 val
= I915_READ(pp_reg
);
1232 if (!(val
& PANEL_POWER_ON
) ||
1233 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1236 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1237 "panel assertion failure, pipe %c regs locked\n",
1241 void assert_pipe(struct drm_i915_private
*dev_priv
,
1242 enum pipe pipe
, bool state
)
1245 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1247 enum intel_display_power_domain power_domain
;
1248 intel_wakeref_t wakeref
;
1250 /* we keep both pipes enabled on 830 */
1251 if (IS_I830(dev_priv
))
1254 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1255 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
1257 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1258 cur_state
= !!(val
& PIPECONF_ENABLE
);
1260 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
1265 I915_STATE_WARN(cur_state
!= state
,
1266 "pipe %c assertion failure (expected %s, current %s)\n",
1267 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1270 static void assert_plane(struct intel_plane
*plane
, bool state
)
1275 cur_state
= plane
->get_hw_state(plane
, &pipe
);
1277 I915_STATE_WARN(cur_state
!= state
,
1278 "%s assertion failure (expected %s, current %s)\n",
1279 plane
->base
.name
, onoff(state
), onoff(cur_state
));
1282 #define assert_plane_enabled(p) assert_plane(p, true)
1283 #define assert_plane_disabled(p) assert_plane(p, false)
1285 static void assert_planes_disabled(struct intel_crtc
*crtc
)
1287 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1288 struct intel_plane
*plane
;
1290 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
)
1291 assert_plane_disabled(plane
);
1294 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1296 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1297 drm_crtc_vblank_put(crtc
);
1300 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1306 val
= I915_READ(PCH_TRANSCONF(pipe
));
1307 enabled
= !!(val
& TRANS_ENABLE
);
1308 I915_STATE_WARN(enabled
,
1309 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1313 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1314 enum pipe pipe
, enum port port
,
1317 enum pipe port_pipe
;
1320 state
= intel_dp_port_enabled(dev_priv
, dp_reg
, port
, &port_pipe
);
1322 I915_STATE_WARN(state
&& port_pipe
== pipe
,
1323 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1324 port_name(port
), pipe_name(pipe
));
1326 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && !state
&& port_pipe
== PIPE_B
,
1327 "IBX PCH DP %c still using transcoder B\n",
1331 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1332 enum pipe pipe
, enum port port
,
1333 i915_reg_t hdmi_reg
)
1335 enum pipe port_pipe
;
1338 state
= intel_sdvo_port_enabled(dev_priv
, hdmi_reg
, &port_pipe
);
1340 I915_STATE_WARN(state
&& port_pipe
== pipe
,
1341 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1342 port_name(port
), pipe_name(pipe
));
1344 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && !state
&& port_pipe
== PIPE_B
,
1345 "IBX PCH HDMI %c still using transcoder B\n",
1349 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1352 enum pipe port_pipe
;
1354 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_B
, PCH_DP_B
);
1355 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_C
, PCH_DP_C
);
1356 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_D
, PCH_DP_D
);
1358 I915_STATE_WARN(intel_crt_port_enabled(dev_priv
, PCH_ADPA
, &port_pipe
) &&
1360 "PCH VGA enabled on transcoder %c, should be disabled\n",
1363 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv
, PCH_LVDS
, &port_pipe
) &&
1365 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1368 /* PCH SDVOB multiplex with HDMIB */
1369 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_B
, PCH_HDMIB
);
1370 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_C
, PCH_HDMIC
);
1371 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_D
, PCH_HDMID
);
1374 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1375 const struct intel_crtc_state
*pipe_config
)
1377 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1378 enum pipe pipe
= crtc
->pipe
;
1380 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1381 POSTING_READ(DPLL(pipe
));
1384 if (intel_wait_for_register(&dev_priv
->uncore
,
1389 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1392 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1393 const struct intel_crtc_state
*pipe_config
)
1395 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1396 enum pipe pipe
= crtc
->pipe
;
1398 assert_pipe_disabled(dev_priv
, pipe
);
1400 /* PLL is protected by panel, make sure we can write it */
1401 assert_panel_unlocked(dev_priv
, pipe
);
1403 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1404 _vlv_enable_pll(crtc
, pipe_config
);
1406 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1407 POSTING_READ(DPLL_MD(pipe
));
1411 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1412 const struct intel_crtc_state
*pipe_config
)
1414 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1415 enum pipe pipe
= crtc
->pipe
;
1416 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1419 vlv_dpio_get(dev_priv
);
1421 /* Enable back the 10bit clock to display controller */
1422 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1423 tmp
|= DPIO_DCLKP_EN
;
1424 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1426 vlv_dpio_put(dev_priv
);
1429 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1434 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1436 /* Check PLL is locked */
1437 if (intel_wait_for_register(&dev_priv
->uncore
,
1438 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1440 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1443 static void chv_enable_pll(struct intel_crtc
*crtc
,
1444 const struct intel_crtc_state
*pipe_config
)
1446 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1447 enum pipe pipe
= crtc
->pipe
;
1449 assert_pipe_disabled(dev_priv
, pipe
);
1451 /* PLL is protected by panel, make sure we can write it */
1452 assert_panel_unlocked(dev_priv
, pipe
);
1454 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1455 _chv_enable_pll(crtc
, pipe_config
);
1457 if (pipe
!= PIPE_A
) {
1459 * WaPixelRepeatModeFixForC0:chv
1461 * DPLLCMD is AWOL. Use chicken bits to propagate
1462 * the value from DPLLBMD to either pipe B or C.
1464 I915_WRITE(CBR4_VLV
, CBR_DPLLBMD_PIPE(pipe
));
1465 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1466 I915_WRITE(CBR4_VLV
, 0);
1467 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1470 * DPLLB VGA mode also seems to cause problems.
1471 * We should always have it disabled.
1473 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1475 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1476 POSTING_READ(DPLL_MD(pipe
));
1480 static bool i9xx_has_pps(struct drm_i915_private
*dev_priv
)
1482 if (IS_I830(dev_priv
))
1485 return IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
1488 static void i9xx_enable_pll(struct intel_crtc
*crtc
,
1489 const struct intel_crtc_state
*crtc_state
)
1491 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1492 i915_reg_t reg
= DPLL(crtc
->pipe
);
1493 u32 dpll
= crtc_state
->dpll_hw_state
.dpll
;
1496 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1498 /* PLL is protected by panel, make sure we can write it */
1499 if (i9xx_has_pps(dev_priv
))
1500 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1503 * Apparently we need to have VGA mode enabled prior to changing
1504 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1505 * dividers, even though the register value does change.
1507 I915_WRITE(reg
, dpll
& ~DPLL_VGA_MODE_DIS
);
1508 I915_WRITE(reg
, dpll
);
1510 /* Wait for the clocks to stabilize. */
1514 if (INTEL_GEN(dev_priv
) >= 4) {
1515 I915_WRITE(DPLL_MD(crtc
->pipe
),
1516 crtc_state
->dpll_hw_state
.dpll_md
);
1518 /* The pixel multiplier can only be updated once the
1519 * DPLL is enabled and the clocks are stable.
1521 * So write it again.
1523 I915_WRITE(reg
, dpll
);
1526 /* We do this three times for luck */
1527 for (i
= 0; i
< 3; i
++) {
1528 I915_WRITE(reg
, dpll
);
1530 udelay(150); /* wait for warmup */
1534 static void i9xx_disable_pll(const struct intel_crtc_state
*crtc_state
)
1536 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1537 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1538 enum pipe pipe
= crtc
->pipe
;
1540 /* Don't disable pipe or pipe PLLs if needed */
1541 if (IS_I830(dev_priv
))
1544 /* Make sure the pipe isn't still relying on us */
1545 assert_pipe_disabled(dev_priv
, pipe
);
1547 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1548 POSTING_READ(DPLL(pipe
));
1551 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1555 /* Make sure the pipe isn't still relying on us */
1556 assert_pipe_disabled(dev_priv
, pipe
);
1558 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1559 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1561 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1563 I915_WRITE(DPLL(pipe
), val
);
1564 POSTING_READ(DPLL(pipe
));
1567 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1569 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1572 /* Make sure the pipe isn't still relying on us */
1573 assert_pipe_disabled(dev_priv
, pipe
);
1575 val
= DPLL_SSC_REF_CLK_CHV
|
1576 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1578 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1580 I915_WRITE(DPLL(pipe
), val
);
1581 POSTING_READ(DPLL(pipe
));
1583 vlv_dpio_get(dev_priv
);
1585 /* Disable 10bit clock to display controller */
1586 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1587 val
&= ~DPIO_DCLKP_EN
;
1588 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1590 vlv_dpio_put(dev_priv
);
1593 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1594 struct intel_digital_port
*dport
,
1595 unsigned int expected_mask
)
1598 i915_reg_t dpll_reg
;
1600 switch (dport
->base
.port
) {
1602 port_mask
= DPLL_PORTB_READY_MASK
;
1606 port_mask
= DPLL_PORTC_READY_MASK
;
1608 expected_mask
<<= 4;
1611 port_mask
= DPLL_PORTD_READY_MASK
;
1612 dpll_reg
= DPIO_PHY_STATUS
;
1618 if (intel_wait_for_register(&dev_priv
->uncore
,
1619 dpll_reg
, port_mask
, expected_mask
,
1621 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1622 port_name(dport
->base
.port
),
1623 I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1626 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state
*crtc_state
)
1628 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1629 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1630 enum pipe pipe
= crtc
->pipe
;
1632 u32 val
, pipeconf_val
;
1634 /* Make sure PCH DPLL is enabled */
1635 assert_shared_dpll_enabled(dev_priv
, crtc_state
->shared_dpll
);
1637 /* FDI must be feeding us bits for PCH ports */
1638 assert_fdi_tx_enabled(dev_priv
, pipe
);
1639 assert_fdi_rx_enabled(dev_priv
, pipe
);
1641 if (HAS_PCH_CPT(dev_priv
)) {
1642 /* Workaround: Set the timing override bit before enabling the
1643 * pch transcoder. */
1644 reg
= TRANS_CHICKEN2(pipe
);
1645 val
= I915_READ(reg
);
1646 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1647 I915_WRITE(reg
, val
);
1650 reg
= PCH_TRANSCONF(pipe
);
1651 val
= I915_READ(reg
);
1652 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1654 if (HAS_PCH_IBX(dev_priv
)) {
1656 * Make the BPC in transcoder be consistent with
1657 * that in pipeconf reg. For HDMI we must use 8bpc
1658 * here for both 8bpc and 12bpc.
1660 val
&= ~PIPECONF_BPC_MASK
;
1661 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
1662 val
|= PIPECONF_8BPC
;
1664 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1667 val
&= ~TRANS_INTERLACE_MASK
;
1668 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
) {
1669 if (HAS_PCH_IBX(dev_priv
) &&
1670 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
1671 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1673 val
|= TRANS_INTERLACED
;
1675 val
|= TRANS_PROGRESSIVE
;
1678 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1679 if (intel_wait_for_register(&dev_priv
->uncore
,
1680 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1682 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1685 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1686 enum transcoder cpu_transcoder
)
1688 u32 val
, pipeconf_val
;
1690 /* FDI must be feeding us bits for PCH ports */
1691 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1692 assert_fdi_rx_enabled(dev_priv
, PIPE_A
);
1694 /* Workaround: set timing override bit. */
1695 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1696 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1697 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1700 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1702 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1703 PIPECONF_INTERLACED_ILK
)
1704 val
|= TRANS_INTERLACED
;
1706 val
|= TRANS_PROGRESSIVE
;
1708 I915_WRITE(LPT_TRANSCONF
, val
);
1709 if (intel_wait_for_register(&dev_priv
->uncore
,
1714 DRM_ERROR("Failed to enable PCH transcoder\n");
1717 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1723 /* FDI relies on the transcoder */
1724 assert_fdi_tx_disabled(dev_priv
, pipe
);
1725 assert_fdi_rx_disabled(dev_priv
, pipe
);
1727 /* Ports must be off as well */
1728 assert_pch_ports_disabled(dev_priv
, pipe
);
1730 reg
= PCH_TRANSCONF(pipe
);
1731 val
= I915_READ(reg
);
1732 val
&= ~TRANS_ENABLE
;
1733 I915_WRITE(reg
, val
);
1734 /* wait for PCH transcoder off, transcoder state */
1735 if (intel_wait_for_register(&dev_priv
->uncore
,
1736 reg
, TRANS_STATE_ENABLE
, 0,
1738 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1740 if (HAS_PCH_CPT(dev_priv
)) {
1741 /* Workaround: Clear the timing override chicken bit again. */
1742 reg
= TRANS_CHICKEN2(pipe
);
1743 val
= I915_READ(reg
);
1744 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1745 I915_WRITE(reg
, val
);
1749 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1753 val
= I915_READ(LPT_TRANSCONF
);
1754 val
&= ~TRANS_ENABLE
;
1755 I915_WRITE(LPT_TRANSCONF
, val
);
1756 /* wait for PCH transcoder off, transcoder state */
1757 if (intel_wait_for_register(&dev_priv
->uncore
,
1758 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1760 DRM_ERROR("Failed to disable PCH transcoder\n");
1762 /* Workaround: clear timing override bit. */
1763 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1764 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1765 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1768 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
)
1770 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1772 if (HAS_PCH_LPT(dev_priv
))
1778 static u32
intel_crtc_max_vblank_count(const struct intel_crtc_state
*crtc_state
)
1780 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1783 * On i965gm the hardware frame counter reads
1784 * zero when the TV encoder is enabled :(
1786 if (IS_I965GM(dev_priv
) &&
1787 (crtc_state
->output_types
& BIT(INTEL_OUTPUT_TVOUT
)))
1790 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1791 return 0xffffffff; /* full 32 bit counter */
1792 else if (INTEL_GEN(dev_priv
) >= 3)
1793 return 0xffffff; /* only 24 bits of frame count */
1795 return 0; /* Gen2 doesn't have a hardware frame counter */
1798 static void intel_crtc_vblank_on(const struct intel_crtc_state
*crtc_state
)
1800 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1802 drm_crtc_set_max_vblank_count(&crtc
->base
,
1803 intel_crtc_max_vblank_count(crtc_state
));
1804 drm_crtc_vblank_on(&crtc
->base
);
1807 static void intel_enable_pipe(const struct intel_crtc_state
*new_crtc_state
)
1809 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
1810 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1811 enum transcoder cpu_transcoder
= new_crtc_state
->cpu_transcoder
;
1812 enum pipe pipe
= crtc
->pipe
;
1816 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1818 assert_planes_disabled(crtc
);
1821 * A pipe without a PLL won't actually be able to drive bits from
1822 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1825 if (HAS_GMCH(dev_priv
)) {
1826 if (intel_crtc_has_type(new_crtc_state
, INTEL_OUTPUT_DSI
))
1827 assert_dsi_pll_enabled(dev_priv
);
1829 assert_pll_enabled(dev_priv
, pipe
);
1831 if (new_crtc_state
->has_pch_encoder
) {
1832 /* if driving the PCH, we need FDI enabled */
1833 assert_fdi_rx_pll_enabled(dev_priv
,
1834 intel_crtc_pch_transcoder(crtc
));
1835 assert_fdi_tx_pll_enabled(dev_priv
,
1836 (enum pipe
) cpu_transcoder
);
1838 /* FIXME: assert CPU port conditions for SNB+ */
1841 trace_intel_pipe_enable(dev_priv
, pipe
);
1843 reg
= PIPECONF(cpu_transcoder
);
1844 val
= I915_READ(reg
);
1845 if (val
& PIPECONF_ENABLE
) {
1846 /* we keep both pipes enabled on 830 */
1847 WARN_ON(!IS_I830(dev_priv
));
1851 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1855 * Until the pipe starts PIPEDSL reads will return a stale value,
1856 * which causes an apparent vblank timestamp jump when PIPEDSL
1857 * resets to its proper value. That also messes up the frame count
1858 * when it's derived from the timestamps. So let's wait for the
1859 * pipe to start properly before we call drm_crtc_vblank_on()
1861 if (intel_crtc_max_vblank_count(new_crtc_state
) == 0)
1862 intel_wait_for_pipe_scanline_moving(crtc
);
1865 static void intel_disable_pipe(const struct intel_crtc_state
*old_crtc_state
)
1867 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1868 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1869 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
1870 enum pipe pipe
= crtc
->pipe
;
1874 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
1877 * Make sure planes won't keep trying to pump pixels to us,
1878 * or we might hang the display.
1880 assert_planes_disabled(crtc
);
1882 trace_intel_pipe_disable(dev_priv
, pipe
);
1884 reg
= PIPECONF(cpu_transcoder
);
1885 val
= I915_READ(reg
);
1886 if ((val
& PIPECONF_ENABLE
) == 0)
1890 * Double wide has implications for planes
1891 * so best keep it disabled when not needed.
1893 if (old_crtc_state
->double_wide
)
1894 val
&= ~PIPECONF_DOUBLE_WIDE
;
1896 /* Don't disable pipe or pipe PLLs if needed */
1897 if (!IS_I830(dev_priv
))
1898 val
&= ~PIPECONF_ENABLE
;
1900 I915_WRITE(reg
, val
);
1901 if ((val
& PIPECONF_ENABLE
) == 0)
1902 intel_wait_for_pipe_off(old_crtc_state
);
1905 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
1907 return IS_GEN(dev_priv
, 2) ? 2048 : 4096;
1911 intel_tile_width_bytes(const struct drm_framebuffer
*fb
, int color_plane
)
1913 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
1914 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
1916 switch (fb
->modifier
) {
1917 case DRM_FORMAT_MOD_LINEAR
:
1918 return intel_tile_size(dev_priv
);
1919 case I915_FORMAT_MOD_X_TILED
:
1920 if (IS_GEN(dev_priv
, 2))
1924 case I915_FORMAT_MOD_Y_TILED_CCS
:
1925 if (color_plane
== 1)
1928 case I915_FORMAT_MOD_Y_TILED
:
1929 if (IS_GEN(dev_priv
, 2) || HAS_128_BYTE_Y_TILING(dev_priv
))
1933 case I915_FORMAT_MOD_Yf_TILED_CCS
:
1934 if (color_plane
== 1)
1937 case I915_FORMAT_MOD_Yf_TILED
:
1953 MISSING_CASE(fb
->modifier
);
1959 intel_tile_height(const struct drm_framebuffer
*fb
, int color_plane
)
1961 return intel_tile_size(to_i915(fb
->dev
)) /
1962 intel_tile_width_bytes(fb
, color_plane
);
1965 /* Return the tile dimensions in pixel units */
1966 static void intel_tile_dims(const struct drm_framebuffer
*fb
, int color_plane
,
1967 unsigned int *tile_width
,
1968 unsigned int *tile_height
)
1970 unsigned int tile_width_bytes
= intel_tile_width_bytes(fb
, color_plane
);
1971 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
1973 *tile_width
= tile_width_bytes
/ cpp
;
1974 *tile_height
= intel_tile_size(to_i915(fb
->dev
)) / tile_width_bytes
;
1978 intel_fb_align_height(const struct drm_framebuffer
*fb
,
1979 int color_plane
, unsigned int height
)
1981 unsigned int tile_height
= intel_tile_height(fb
, color_plane
);
1983 return ALIGN(height
, tile_height
);
1986 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
1988 unsigned int size
= 0;
1991 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
1992 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
1997 unsigned int intel_remapped_info_size(const struct intel_remapped_info
*rem_info
)
1999 unsigned int size
= 0;
2002 for (i
= 0 ; i
< ARRAY_SIZE(rem_info
->plane
); i
++)
2003 size
+= rem_info
->plane
[i
].width
* rem_info
->plane
[i
].height
;
2009 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2010 const struct drm_framebuffer
*fb
,
2011 unsigned int rotation
)
2013 view
->type
= I915_GGTT_VIEW_NORMAL
;
2014 if (drm_rotation_90_or_270(rotation
)) {
2015 view
->type
= I915_GGTT_VIEW_ROTATED
;
2016 view
->rotated
= to_intel_framebuffer(fb
)->rot_info
;
2020 static unsigned int intel_cursor_alignment(const struct drm_i915_private
*dev_priv
)
2022 if (IS_I830(dev_priv
))
2024 else if (IS_I85X(dev_priv
))
2026 else if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
2032 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2034 if (INTEL_GEN(dev_priv
) >= 9)
2036 else if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
) ||
2037 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2039 else if (INTEL_GEN(dev_priv
) >= 4)
2045 static unsigned int intel_surf_alignment(const struct drm_framebuffer
*fb
,
2048 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2050 /* AUX_DIST needs only 4K alignment */
2051 if (color_plane
== 1)
2054 switch (fb
->modifier
) {
2055 case DRM_FORMAT_MOD_LINEAR
:
2056 return intel_linear_alignment(dev_priv
);
2057 case I915_FORMAT_MOD_X_TILED
:
2058 if (INTEL_GEN(dev_priv
) >= 9)
2061 case I915_FORMAT_MOD_Y_TILED_CCS
:
2062 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2063 case I915_FORMAT_MOD_Y_TILED
:
2064 case I915_FORMAT_MOD_Yf_TILED
:
2065 return 1 * 1024 * 1024;
2067 MISSING_CASE(fb
->modifier
);
2072 static bool intel_plane_uses_fence(const struct intel_plane_state
*plane_state
)
2074 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2075 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
2077 return INTEL_GEN(dev_priv
) < 4 ||
2079 plane_state
->view
.type
== I915_GGTT_VIEW_NORMAL
);
2083 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
2084 const struct i915_ggtt_view
*view
,
2086 unsigned long *out_flags
)
2088 struct drm_device
*dev
= fb
->dev
;
2089 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2090 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2091 intel_wakeref_t wakeref
;
2092 struct i915_vma
*vma
;
2093 unsigned int pinctl
;
2096 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2098 alignment
= intel_surf_alignment(fb
, 0);
2100 /* Note that the w/a also requires 64 PTE of padding following the
2101 * bo. We currently fill all unused PTE with the shadow page and so
2102 * we should always have valid PTE following the scanout preventing
2105 if (intel_scanout_needs_vtd_wa(dev_priv
) && alignment
< 256 * 1024)
2106 alignment
= 256 * 1024;
2109 * Global gtt pte registers are special registers which actually forward
2110 * writes to a chunk of system memory. Which means that there is no risk
2111 * that the register values disappear as soon as we call
2112 * intel_runtime_pm_put(), so it is correct to wrap only the
2113 * pin/unpin/fence and not more.
2115 wakeref
= intel_runtime_pm_get(dev_priv
);
2116 i915_gem_object_lock(obj
);
2118 atomic_inc(&dev_priv
->gpu_error
.pending_fb_pin
);
2122 /* Valleyview is definitely limited to scanning out the first
2123 * 512MiB. Lets presume this behaviour was inherited from the
2124 * g4x display engine and that all earlier gen are similarly
2125 * limited. Testing suggests that it is a little more
2126 * complicated than this. For example, Cherryview appears quite
2127 * happy to scanout from anywhere within its global aperture.
2129 if (HAS_GMCH(dev_priv
))
2130 pinctl
|= PIN_MAPPABLE
;
2132 vma
= i915_gem_object_pin_to_display_plane(obj
,
2133 alignment
, view
, pinctl
);
2137 if (uses_fence
&& i915_vma_is_map_and_fenceable(vma
)) {
2140 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2141 * fence, whereas 965+ only requires a fence if using
2142 * framebuffer compression. For simplicity, we always, when
2143 * possible, install a fence as the cost is not that onerous.
2145 * If we fail to fence the tiled scanout, then either the
2146 * modeset will reject the change (which is highly unlikely as
2147 * the affected systems, all but one, do not have unmappable
2148 * space) or we will not be able to enable full powersaving
2149 * techniques (also likely not to apply due to various limits
2150 * FBC and the like impose on the size of the buffer, which
2151 * presumably we violated anyway with this unmappable buffer).
2152 * Anyway, it is presumably better to stumble onwards with
2153 * something and try to run the system in a "less than optimal"
2154 * mode that matches the user configuration.
2156 ret
= i915_vma_pin_fence(vma
);
2157 if (ret
!= 0 && INTEL_GEN(dev_priv
) < 4) {
2158 i915_gem_object_unpin_from_display_plane(vma
);
2163 if (ret
== 0 && vma
->fence
)
2164 *out_flags
|= PLANE_HAS_FENCE
;
2169 atomic_dec(&dev_priv
->gpu_error
.pending_fb_pin
);
2171 i915_gem_object_unlock(obj
);
2172 intel_runtime_pm_put(dev_priv
, wakeref
);
2176 void intel_unpin_fb_vma(struct i915_vma
*vma
, unsigned long flags
)
2178 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
2180 i915_gem_object_lock(vma
->obj
);
2181 if (flags
& PLANE_HAS_FENCE
)
2182 i915_vma_unpin_fence(vma
);
2183 i915_gem_object_unpin_from_display_plane(vma
);
2184 i915_gem_object_unlock(vma
->obj
);
2189 static int intel_fb_pitch(const struct drm_framebuffer
*fb
, int color_plane
,
2190 unsigned int rotation
)
2192 if (drm_rotation_90_or_270(rotation
))
2193 return to_intel_framebuffer(fb
)->rotated
[color_plane
].pitch
;
2195 return fb
->pitches
[color_plane
];
2199 * Convert the x/y offsets into a linear offset.
2200 * Only valid with 0/180 degree rotation, which is fine since linear
2201 * offset is only used with linear buffers on pre-hsw and tiled buffers
2202 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2204 u32
intel_fb_xy_to_linear(int x
, int y
,
2205 const struct intel_plane_state
*state
,
2208 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2209 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2210 unsigned int pitch
= state
->color_plane
[color_plane
].stride
;
2212 return y
* pitch
+ x
* cpp
;
2216 * Add the x/y offsets derived from fb->offsets[] to the user
2217 * specified plane src x/y offsets. The resulting x/y offsets
2218 * specify the start of scanout from the beginning of the gtt mapping.
2220 void intel_add_fb_offsets(int *x
, int *y
,
2221 const struct intel_plane_state
*state
,
2225 *x
+= state
->color_plane
[color_plane
].x
;
2226 *y
+= state
->color_plane
[color_plane
].y
;
2229 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2230 unsigned int tile_width
,
2231 unsigned int tile_height
,
2232 unsigned int tile_size
,
2233 unsigned int pitch_tiles
,
2237 unsigned int pitch_pixels
= pitch_tiles
* tile_width
;
2240 WARN_ON(old_offset
& (tile_size
- 1));
2241 WARN_ON(new_offset
& (tile_size
- 1));
2242 WARN_ON(new_offset
> old_offset
);
2244 tiles
= (old_offset
- new_offset
) / tile_size
;
2246 *y
+= tiles
/ pitch_tiles
* tile_height
;
2247 *x
+= tiles
% pitch_tiles
* tile_width
;
2249 /* minimize x in case it got needlessly big */
2250 *y
+= *x
/ pitch_pixels
* tile_height
;
2256 static bool is_surface_linear(u64 modifier
, int color_plane
)
2258 return modifier
== DRM_FORMAT_MOD_LINEAR
;
2261 static u32
intel_adjust_aligned_offset(int *x
, int *y
,
2262 const struct drm_framebuffer
*fb
,
2264 unsigned int rotation
,
2266 u32 old_offset
, u32 new_offset
)
2268 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2269 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2271 WARN_ON(new_offset
> old_offset
);
2273 if (!is_surface_linear(fb
->modifier
, color_plane
)) {
2274 unsigned int tile_size
, tile_width
, tile_height
;
2275 unsigned int pitch_tiles
;
2277 tile_size
= intel_tile_size(dev_priv
);
2278 intel_tile_dims(fb
, color_plane
, &tile_width
, &tile_height
);
2280 if (drm_rotation_90_or_270(rotation
)) {
2281 pitch_tiles
= pitch
/ tile_height
;
2282 swap(tile_width
, tile_height
);
2284 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2287 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2288 tile_size
, pitch_tiles
,
2289 old_offset
, new_offset
);
2291 old_offset
+= *y
* pitch
+ *x
* cpp
;
2293 *y
= (old_offset
- new_offset
) / pitch
;
2294 *x
= ((old_offset
- new_offset
) - *y
* pitch
) / cpp
;
2301 * Adjust the tile offset by moving the difference into
2304 static u32
intel_plane_adjust_aligned_offset(int *x
, int *y
,
2305 const struct intel_plane_state
*state
,
2307 u32 old_offset
, u32 new_offset
)
2309 return intel_adjust_aligned_offset(x
, y
, state
->base
.fb
, color_plane
,
2310 state
->base
.rotation
,
2311 state
->color_plane
[color_plane
].stride
,
2312 old_offset
, new_offset
);
2316 * Computes the aligned offset to the base tile and adjusts
2317 * x, y. bytes per pixel is assumed to be a power-of-two.
2319 * In the 90/270 rotated case, x and y are assumed
2320 * to be already rotated to match the rotated GTT view, and
2321 * pitch is the tile_height aligned framebuffer height.
2323 * This function is used when computing the derived information
2324 * under intel_framebuffer, so using any of that information
2325 * here is not allowed. Anything under drm_framebuffer can be
2326 * used. This is why the user has to pass in the pitch since it
2327 * is specified in the rotated orientation.
2329 static u32
intel_compute_aligned_offset(struct drm_i915_private
*dev_priv
,
2331 const struct drm_framebuffer
*fb
,
2334 unsigned int rotation
,
2337 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2338 u32 offset
, offset_aligned
;
2343 if (!is_surface_linear(fb
->modifier
, color_plane
)) {
2344 unsigned int tile_size
, tile_width
, tile_height
;
2345 unsigned int tile_rows
, tiles
, pitch_tiles
;
2347 tile_size
= intel_tile_size(dev_priv
);
2348 intel_tile_dims(fb
, color_plane
, &tile_width
, &tile_height
);
2350 if (drm_rotation_90_or_270(rotation
)) {
2351 pitch_tiles
= pitch
/ tile_height
;
2352 swap(tile_width
, tile_height
);
2354 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2357 tile_rows
= *y
/ tile_height
;
2360 tiles
= *x
/ tile_width
;
2363 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2364 offset_aligned
= offset
& ~alignment
;
2366 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2367 tile_size
, pitch_tiles
,
2368 offset
, offset_aligned
);
2370 offset
= *y
* pitch
+ *x
* cpp
;
2371 offset_aligned
= offset
& ~alignment
;
2373 *y
= (offset
& alignment
) / pitch
;
2374 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2377 return offset_aligned
;
2380 static u32
intel_plane_compute_aligned_offset(int *x
, int *y
,
2381 const struct intel_plane_state
*state
,
2384 struct intel_plane
*intel_plane
= to_intel_plane(state
->base
.plane
);
2385 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
2386 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2387 unsigned int rotation
= state
->base
.rotation
;
2388 int pitch
= state
->color_plane
[color_plane
].stride
;
2391 if (intel_plane
->id
== PLANE_CURSOR
)
2392 alignment
= intel_cursor_alignment(dev_priv
);
2394 alignment
= intel_surf_alignment(fb
, color_plane
);
2396 return intel_compute_aligned_offset(dev_priv
, x
, y
, fb
, color_plane
,
2397 pitch
, rotation
, alignment
);
2400 /* Convert the fb->offset[] into x/y offsets */
2401 static int intel_fb_offset_to_xy(int *x
, int *y
,
2402 const struct drm_framebuffer
*fb
,
2405 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2406 unsigned int height
;
2408 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
&&
2409 fb
->offsets
[color_plane
] % intel_tile_size(dev_priv
)) {
2410 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2411 fb
->offsets
[color_plane
], color_plane
);
2415 height
= drm_framebuffer_plane_height(fb
->height
, fb
, color_plane
);
2416 height
= ALIGN(height
, intel_tile_height(fb
, color_plane
));
2418 /* Catch potential overflows early */
2419 if (add_overflows_t(u32
, mul_u32_u32(height
, fb
->pitches
[color_plane
]),
2420 fb
->offsets
[color_plane
])) {
2421 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2422 fb
->offsets
[color_plane
], fb
->pitches
[color_plane
],
2430 intel_adjust_aligned_offset(x
, y
,
2431 fb
, color_plane
, DRM_MODE_ROTATE_0
,
2432 fb
->pitches
[color_plane
],
2433 fb
->offsets
[color_plane
], 0);
2438 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier
)
2440 switch (fb_modifier
) {
2441 case I915_FORMAT_MOD_X_TILED
:
2442 return I915_TILING_X
;
2443 case I915_FORMAT_MOD_Y_TILED
:
2444 case I915_FORMAT_MOD_Y_TILED_CCS
:
2445 return I915_TILING_Y
;
2447 return I915_TILING_NONE
;
2452 * From the Sky Lake PRM:
2453 * "The Color Control Surface (CCS) contains the compression status of
2454 * the cache-line pairs. The compression state of the cache-line pair
2455 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2456 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2457 * cache-line-pairs. CCS is always Y tiled."
2459 * Since cache line pairs refers to horizontally adjacent cache lines,
2460 * each cache line in the CCS corresponds to an area of 32x16 cache
2461 * lines on the main surface. Since each pixel is 4 bytes, this gives
2462 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2465 static const struct drm_format_info ccs_formats
[] = {
2466 { .format
= DRM_FORMAT_XRGB8888
, .depth
= 24, .num_planes
= 2,
2467 .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2468 { .format
= DRM_FORMAT_XBGR8888
, .depth
= 24, .num_planes
= 2,
2469 .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2470 { .format
= DRM_FORMAT_ARGB8888
, .depth
= 32, .num_planes
= 2,
2471 .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, .has_alpha
= true, },
2472 { .format
= DRM_FORMAT_ABGR8888
, .depth
= 32, .num_planes
= 2,
2473 .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, .has_alpha
= true, },
2476 static const struct drm_format_info
*
2477 lookup_format_info(const struct drm_format_info formats
[],
2478 int num_formats
, u32 format
)
2482 for (i
= 0; i
< num_formats
; i
++) {
2483 if (formats
[i
].format
== format
)
2490 static const struct drm_format_info
*
2491 intel_get_format_info(const struct drm_mode_fb_cmd2
*cmd
)
2493 switch (cmd
->modifier
[0]) {
2494 case I915_FORMAT_MOD_Y_TILED_CCS
:
2495 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2496 return lookup_format_info(ccs_formats
,
2497 ARRAY_SIZE(ccs_formats
),
2504 bool is_ccs_modifier(u64 modifier
)
2506 return modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
2507 modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
;
2510 u32
intel_plane_fb_max_stride(struct drm_i915_private
*dev_priv
,
2511 u32 pixel_format
, u64 modifier
)
2513 struct intel_crtc
*crtc
;
2514 struct intel_plane
*plane
;
2517 * We assume the primary plane for pipe A has
2518 * the highest stride limits of them all.
2520 crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_A
);
2521 plane
= to_intel_plane(crtc
->base
.primary
);
2523 return plane
->max_stride(plane
, pixel_format
, modifier
,
2528 u32
intel_fb_max_stride(struct drm_i915_private
*dev_priv
,
2529 u32 pixel_format
, u64 modifier
)
2532 * Arbitrary limit for gen4+ chosen to match the
2533 * render engine max stride.
2535 * The new CCS hash mode makes remapping impossible
2537 if (!is_ccs_modifier(modifier
)) {
2538 if (INTEL_GEN(dev_priv
) >= 7)
2540 else if (INTEL_GEN(dev_priv
) >= 4)
2544 return intel_plane_fb_max_stride(dev_priv
, pixel_format
, modifier
);
2548 intel_fb_stride_alignment(const struct drm_framebuffer
*fb
, int color_plane
)
2550 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2552 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
) {
2553 u32 max_stride
= intel_plane_fb_max_stride(dev_priv
,
2558 * To make remapping with linear generally feasible
2559 * we need the stride to be page aligned.
2561 if (fb
->pitches
[color_plane
] > max_stride
)
2562 return intel_tile_size(dev_priv
);
2566 return intel_tile_width_bytes(fb
, color_plane
);
2570 bool intel_plane_can_remap(const struct intel_plane_state
*plane_state
)
2572 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2573 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
2574 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2577 /* We don't want to deal with remapping with cursors */
2578 if (plane
->id
== PLANE_CURSOR
)
2582 * The display engine limits already match/exceed the
2583 * render engine limits, so not much point in remapping.
2584 * Would also need to deal with the fence POT alignment
2585 * and gen2 2KiB GTT tile size.
2587 if (INTEL_GEN(dev_priv
) < 4)
2591 * The new CCS hash mode isn't compatible with remapping as
2592 * the virtual address of the pages affects the compressed data.
2594 if (is_ccs_modifier(fb
->modifier
))
2597 /* Linear needs a page aligned stride for remapping */
2598 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
) {
2599 unsigned int alignment
= intel_tile_size(dev_priv
) - 1;
2601 for (i
= 0; i
< fb
->format
->num_planes
; i
++) {
2602 if (fb
->pitches
[i
] & alignment
)
2610 static bool intel_plane_needs_remap(const struct intel_plane_state
*plane_state
)
2612 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2613 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2614 unsigned int rotation
= plane_state
->base
.rotation
;
2615 u32 stride
, max_stride
;
2618 * No remapping for invisible planes since we don't have
2619 * an actual source viewport to remap.
2621 if (!plane_state
->base
.visible
)
2624 if (!intel_plane_can_remap(plane_state
))
2628 * FIXME: aux plane limits on gen9+ are
2629 * unclear in Bspec, for now no checking.
2631 stride
= intel_fb_pitch(fb
, 0, rotation
);
2632 max_stride
= plane
->max_stride(plane
, fb
->format
->format
,
2633 fb
->modifier
, rotation
);
2635 return stride
> max_stride
;
2639 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2640 struct drm_framebuffer
*fb
)
2642 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2643 struct intel_rotation_info
*rot_info
= &intel_fb
->rot_info
;
2644 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2645 u32 gtt_offset_rotated
= 0;
2646 unsigned int max_size
= 0;
2647 int i
, num_planes
= fb
->format
->num_planes
;
2648 unsigned int tile_size
= intel_tile_size(dev_priv
);
2650 for (i
= 0; i
< num_planes
; i
++) {
2651 unsigned int width
, height
;
2652 unsigned int cpp
, size
;
2657 cpp
= fb
->format
->cpp
[i
];
2658 width
= drm_framebuffer_plane_width(fb
->width
, fb
, i
);
2659 height
= drm_framebuffer_plane_height(fb
->height
, fb
, i
);
2661 ret
= intel_fb_offset_to_xy(&x
, &y
, fb
, i
);
2663 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2668 if (is_ccs_modifier(fb
->modifier
) && i
== 1) {
2669 int hsub
= fb
->format
->hsub
;
2670 int vsub
= fb
->format
->vsub
;
2671 int tile_width
, tile_height
;
2675 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2677 tile_height
*= vsub
;
2679 ccs_x
= (x
* hsub
) % tile_width
;
2680 ccs_y
= (y
* vsub
) % tile_height
;
2681 main_x
= intel_fb
->normal
[0].x
% tile_width
;
2682 main_y
= intel_fb
->normal
[0].y
% tile_height
;
2685 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2686 * x/y offsets must match between CCS and the main surface.
2688 if (main_x
!= ccs_x
|| main_y
!= ccs_y
) {
2689 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2692 intel_fb
->normal
[0].x
,
2693 intel_fb
->normal
[0].y
,
2700 * The fence (if used) is aligned to the start of the object
2701 * so having the framebuffer wrap around across the edge of the
2702 * fenced region doesn't really work. We have no API to configure
2703 * the fence start offset within the object (nor could we probably
2704 * on gen2/3). So it's just easier if we just require that the
2705 * fb layout agrees with the fence layout. We already check that the
2706 * fb stride matches the fence stride elsewhere.
2708 if (i
== 0 && i915_gem_object_is_tiled(obj
) &&
2709 (x
+ width
) * cpp
> fb
->pitches
[i
]) {
2710 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2716 * First pixel of the framebuffer from
2717 * the start of the normal gtt mapping.
2719 intel_fb
->normal
[i
].x
= x
;
2720 intel_fb
->normal
[i
].y
= y
;
2722 offset
= intel_compute_aligned_offset(dev_priv
, &x
, &y
, fb
, i
,
2726 offset
/= tile_size
;
2728 if (!is_surface_linear(fb
->modifier
, i
)) {
2729 unsigned int tile_width
, tile_height
;
2730 unsigned int pitch_tiles
;
2733 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2735 rot_info
->plane
[i
].offset
= offset
;
2736 rot_info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
], tile_width
* cpp
);
2737 rot_info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2738 rot_info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2740 intel_fb
->rotated
[i
].pitch
=
2741 rot_info
->plane
[i
].height
* tile_height
;
2743 /* how many tiles does this plane need */
2744 size
= rot_info
->plane
[i
].stride
* rot_info
->plane
[i
].height
;
2746 * If the plane isn't horizontally tile aligned,
2747 * we need one more tile.
2752 /* rotate the x/y offsets to match the GTT view */
2758 rot_info
->plane
[i
].width
* tile_width
,
2759 rot_info
->plane
[i
].height
* tile_height
,
2760 DRM_MODE_ROTATE_270
);
2764 /* rotate the tile dimensions to match the GTT view */
2765 pitch_tiles
= intel_fb
->rotated
[i
].pitch
/ tile_height
;
2766 swap(tile_width
, tile_height
);
2769 * We only keep the x/y offsets, so push all of the
2770 * gtt offset into the x/y offsets.
2772 intel_adjust_tile_offset(&x
, &y
,
2773 tile_width
, tile_height
,
2774 tile_size
, pitch_tiles
,
2775 gtt_offset_rotated
* tile_size
, 0);
2777 gtt_offset_rotated
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2780 * First pixel of the framebuffer from
2781 * the start of the rotated gtt mapping.
2783 intel_fb
->rotated
[i
].x
= x
;
2784 intel_fb
->rotated
[i
].y
= y
;
2786 size
= DIV_ROUND_UP((y
+ height
) * fb
->pitches
[i
] +
2787 x
* cpp
, tile_size
);
2790 /* how many tiles in total needed in the bo */
2791 max_size
= max(max_size
, offset
+ size
);
2794 if (mul_u32_u32(max_size
, tile_size
) > obj
->base
.size
) {
2795 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2796 mul_u32_u32(max_size
, tile_size
), obj
->base
.size
);
2804 intel_plane_remap_gtt(struct intel_plane_state
*plane_state
)
2806 struct drm_i915_private
*dev_priv
=
2807 to_i915(plane_state
->base
.plane
->dev
);
2808 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2809 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2810 struct intel_rotation_info
*info
= &plane_state
->view
.rotated
;
2811 unsigned int rotation
= plane_state
->base
.rotation
;
2812 int i
, num_planes
= fb
->format
->num_planes
;
2813 unsigned int tile_size
= intel_tile_size(dev_priv
);
2814 unsigned int src_x
, src_y
;
2815 unsigned int src_w
, src_h
;
2818 memset(&plane_state
->view
, 0, sizeof(plane_state
->view
));
2819 plane_state
->view
.type
= drm_rotation_90_or_270(rotation
) ?
2820 I915_GGTT_VIEW_ROTATED
: I915_GGTT_VIEW_REMAPPED
;
2822 src_x
= plane_state
->base
.src
.x1
>> 16;
2823 src_y
= plane_state
->base
.src
.y1
>> 16;
2824 src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
2825 src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
2827 WARN_ON(is_ccs_modifier(fb
->modifier
));
2829 /* Make src coordinates relative to the viewport */
2830 drm_rect_translate(&plane_state
->base
.src
,
2831 -(src_x
<< 16), -(src_y
<< 16));
2833 /* Rotate src coordinates to match rotated GTT view */
2834 if (drm_rotation_90_or_270(rotation
))
2835 drm_rect_rotate(&plane_state
->base
.src
,
2836 src_w
<< 16, src_h
<< 16,
2837 DRM_MODE_ROTATE_270
);
2839 for (i
= 0; i
< num_planes
; i
++) {
2840 unsigned int hsub
= i
? fb
->format
->hsub
: 1;
2841 unsigned int vsub
= i
? fb
->format
->vsub
: 1;
2842 unsigned int cpp
= fb
->format
->cpp
[i
];
2843 unsigned int tile_width
, tile_height
;
2844 unsigned int width
, height
;
2845 unsigned int pitch_tiles
;
2849 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2853 width
= src_w
/ hsub
;
2854 height
= src_h
/ vsub
;
2857 * First pixel of the src viewport from the
2858 * start of the normal gtt mapping.
2860 x
+= intel_fb
->normal
[i
].x
;
2861 y
+= intel_fb
->normal
[i
].y
;
2863 offset
= intel_compute_aligned_offset(dev_priv
, &x
, &y
,
2864 fb
, i
, fb
->pitches
[i
],
2865 DRM_MODE_ROTATE_0
, tile_size
);
2866 offset
/= tile_size
;
2868 info
->plane
[i
].offset
= offset
;
2869 info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
],
2871 info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2872 info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2874 if (drm_rotation_90_or_270(rotation
)) {
2877 /* rotate the x/y offsets to match the GTT view */
2883 info
->plane
[i
].width
* tile_width
,
2884 info
->plane
[i
].height
* tile_height
,
2885 DRM_MODE_ROTATE_270
);
2889 pitch_tiles
= info
->plane
[i
].height
;
2890 plane_state
->color_plane
[i
].stride
= pitch_tiles
* tile_height
;
2892 /* rotate the tile dimensions to match the GTT view */
2893 swap(tile_width
, tile_height
);
2895 pitch_tiles
= info
->plane
[i
].width
;
2896 plane_state
->color_plane
[i
].stride
= pitch_tiles
* tile_width
* cpp
;
2900 * We only keep the x/y offsets, so push all of the
2901 * gtt offset into the x/y offsets.
2903 intel_adjust_tile_offset(&x
, &y
,
2904 tile_width
, tile_height
,
2905 tile_size
, pitch_tiles
,
2906 gtt_offset
* tile_size
, 0);
2908 gtt_offset
+= info
->plane
[i
].width
* info
->plane
[i
].height
;
2910 plane_state
->color_plane
[i
].offset
= 0;
2911 plane_state
->color_plane
[i
].x
= x
;
2912 plane_state
->color_plane
[i
].y
= y
;
2917 intel_plane_compute_gtt(struct intel_plane_state
*plane_state
)
2919 const struct intel_framebuffer
*fb
=
2920 to_intel_framebuffer(plane_state
->base
.fb
);
2921 unsigned int rotation
= plane_state
->base
.rotation
;
2927 num_planes
= fb
->base
.format
->num_planes
;
2929 if (intel_plane_needs_remap(plane_state
)) {
2930 intel_plane_remap_gtt(plane_state
);
2933 * Sometimes even remapping can't overcome
2934 * the stride limitations :( Can happen with
2935 * big plane sizes and suitably misaligned
2938 return intel_plane_check_stride(plane_state
);
2941 intel_fill_fb_ggtt_view(&plane_state
->view
, &fb
->base
, rotation
);
2943 for (i
= 0; i
< num_planes
; i
++) {
2944 plane_state
->color_plane
[i
].stride
= intel_fb_pitch(&fb
->base
, i
, rotation
);
2945 plane_state
->color_plane
[i
].offset
= 0;
2947 if (drm_rotation_90_or_270(rotation
)) {
2948 plane_state
->color_plane
[i
].x
= fb
->rotated
[i
].x
;
2949 plane_state
->color_plane
[i
].y
= fb
->rotated
[i
].y
;
2951 plane_state
->color_plane
[i
].x
= fb
->normal
[i
].x
;
2952 plane_state
->color_plane
[i
].y
= fb
->normal
[i
].y
;
2956 /* Rotate src coordinates to match rotated GTT view */
2957 if (drm_rotation_90_or_270(rotation
))
2958 drm_rect_rotate(&plane_state
->base
.src
,
2959 fb
->base
.width
<< 16, fb
->base
.height
<< 16,
2960 DRM_MODE_ROTATE_270
);
2962 return intel_plane_check_stride(plane_state
);
2965 static int i9xx_format_to_fourcc(int format
)
2968 case DISPPLANE_8BPP
:
2969 return DRM_FORMAT_C8
;
2970 case DISPPLANE_BGRX555
:
2971 return DRM_FORMAT_XRGB1555
;
2972 case DISPPLANE_BGRX565
:
2973 return DRM_FORMAT_RGB565
;
2975 case DISPPLANE_BGRX888
:
2976 return DRM_FORMAT_XRGB8888
;
2977 case DISPPLANE_RGBX888
:
2978 return DRM_FORMAT_XBGR8888
;
2979 case DISPPLANE_BGRX101010
:
2980 return DRM_FORMAT_XRGB2101010
;
2981 case DISPPLANE_RGBX101010
:
2982 return DRM_FORMAT_XBGR2101010
;
2986 int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2989 case PLANE_CTL_FORMAT_RGB_565
:
2990 return DRM_FORMAT_RGB565
;
2991 case PLANE_CTL_FORMAT_NV12
:
2992 return DRM_FORMAT_NV12
;
2993 case PLANE_CTL_FORMAT_P010
:
2994 return DRM_FORMAT_P010
;
2995 case PLANE_CTL_FORMAT_P012
:
2996 return DRM_FORMAT_P012
;
2997 case PLANE_CTL_FORMAT_P016
:
2998 return DRM_FORMAT_P016
;
2999 case PLANE_CTL_FORMAT_Y210
:
3000 return DRM_FORMAT_Y210
;
3001 case PLANE_CTL_FORMAT_Y212
:
3002 return DRM_FORMAT_Y212
;
3003 case PLANE_CTL_FORMAT_Y216
:
3004 return DRM_FORMAT_Y216
;
3005 case PLANE_CTL_FORMAT_Y410
:
3006 return DRM_FORMAT_XVYU2101010
;
3007 case PLANE_CTL_FORMAT_Y412
:
3008 return DRM_FORMAT_XVYU12_16161616
;
3009 case PLANE_CTL_FORMAT_Y416
:
3010 return DRM_FORMAT_XVYU16161616
;
3012 case PLANE_CTL_FORMAT_XRGB_8888
:
3015 return DRM_FORMAT_ABGR8888
;
3017 return DRM_FORMAT_XBGR8888
;
3020 return DRM_FORMAT_ARGB8888
;
3022 return DRM_FORMAT_XRGB8888
;
3024 case PLANE_CTL_FORMAT_XRGB_2101010
:
3026 return DRM_FORMAT_XBGR2101010
;
3028 return DRM_FORMAT_XRGB2101010
;
3029 case PLANE_CTL_FORMAT_XRGB_16161616F
:
3032 return DRM_FORMAT_ABGR16161616F
;
3034 return DRM_FORMAT_XBGR16161616F
;
3037 return DRM_FORMAT_ARGB16161616F
;
3039 return DRM_FORMAT_XRGB16161616F
;
3045 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
3046 struct intel_initial_plane_config
*plane_config
)
3048 struct drm_device
*dev
= crtc
->base
.dev
;
3049 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3050 struct drm_i915_gem_object
*obj
= NULL
;
3051 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
3052 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
3053 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
3054 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
3057 size_aligned
-= base_aligned
;
3059 if (plane_config
->size
== 0)
3062 /* If the FB is too big, just don't use it since fbdev is not very
3063 * important and we should probably use that space with FBC or other
3065 if (size_aligned
* 2 > dev_priv
->stolen_usable_size
)
3068 switch (fb
->modifier
) {
3069 case DRM_FORMAT_MOD_LINEAR
:
3070 case I915_FORMAT_MOD_X_TILED
:
3071 case I915_FORMAT_MOD_Y_TILED
:
3074 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3079 mutex_lock(&dev
->struct_mutex
);
3080 obj
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
3084 mutex_unlock(&dev
->struct_mutex
);
3088 switch (plane_config
->tiling
) {
3089 case I915_TILING_NONE
:
3093 obj
->tiling_and_stride
= fb
->pitches
[0] | plane_config
->tiling
;
3096 MISSING_CASE(plane_config
->tiling
);
3100 mode_cmd
.pixel_format
= fb
->format
->format
;
3101 mode_cmd
.width
= fb
->width
;
3102 mode_cmd
.height
= fb
->height
;
3103 mode_cmd
.pitches
[0] = fb
->pitches
[0];
3104 mode_cmd
.modifier
[0] = fb
->modifier
;
3105 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
3107 if (intel_framebuffer_init(to_intel_framebuffer(fb
), obj
, &mode_cmd
)) {
3108 DRM_DEBUG_KMS("intel fb init failed\n");
3113 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
3117 i915_gem_object_put(obj
);
3122 intel_set_plane_visible(struct intel_crtc_state
*crtc_state
,
3123 struct intel_plane_state
*plane_state
,
3126 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
3128 plane_state
->base
.visible
= visible
;
3131 crtc_state
->base
.plane_mask
|= drm_plane_mask(&plane
->base
);
3133 crtc_state
->base
.plane_mask
&= ~drm_plane_mask(&plane
->base
);
3136 static void fixup_active_planes(struct intel_crtc_state
*crtc_state
)
3138 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
3139 struct drm_plane
*plane
;
3142 * Active_planes aliases if multiple "primary" or cursor planes
3143 * have been used on the same (or wrong) pipe. plane_mask uses
3144 * unique ids, hence we can use that to reconstruct active_planes.
3146 crtc_state
->active_planes
= 0;
3148 drm_for_each_plane_mask(plane
, &dev_priv
->drm
,
3149 crtc_state
->base
.plane_mask
)
3150 crtc_state
->active_planes
|= BIT(to_intel_plane(plane
)->id
);
3153 static void intel_plane_disable_noatomic(struct intel_crtc
*crtc
,
3154 struct intel_plane
*plane
)
3156 struct intel_crtc_state
*crtc_state
=
3157 to_intel_crtc_state(crtc
->base
.state
);
3158 struct intel_plane_state
*plane_state
=
3159 to_intel_plane_state(plane
->base
.state
);
3161 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3162 plane
->base
.base
.id
, plane
->base
.name
,
3163 crtc
->base
.base
.id
, crtc
->base
.name
);
3165 intel_set_plane_visible(crtc_state
, plane_state
, false);
3166 fixup_active_planes(crtc_state
);
3167 crtc_state
->data_rate
[plane
->id
] = 0;
3169 if (plane
->id
== PLANE_PRIMARY
)
3170 intel_pre_disable_primary_noatomic(&crtc
->base
);
3172 intel_disable_plane(plane
, crtc_state
);
3176 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
3177 struct intel_initial_plane_config
*plane_config
)
3179 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3180 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3182 struct drm_i915_gem_object
*obj
;
3183 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
3184 struct drm_plane_state
*plane_state
= primary
->state
;
3185 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
3186 struct intel_plane_state
*intel_state
=
3187 to_intel_plane_state(plane_state
);
3188 struct drm_framebuffer
*fb
;
3190 if (!plane_config
->fb
)
3193 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
3194 fb
= &plane_config
->fb
->base
;
3198 kfree(plane_config
->fb
);
3201 * Failed to alloc the obj, check to see if we should share
3202 * an fb with another CRTC instead
3204 for_each_crtc(dev
, c
) {
3205 struct intel_plane_state
*state
;
3207 if (c
== &intel_crtc
->base
)
3210 if (!to_intel_crtc(c
)->active
)
3213 state
= to_intel_plane_state(c
->primary
->state
);
3217 if (intel_plane_ggtt_offset(state
) == plane_config
->base
) {
3218 fb
= state
->base
.fb
;
3219 drm_framebuffer_get(fb
);
3225 * We've failed to reconstruct the BIOS FB. Current display state
3226 * indicates that the primary plane is visible, but has a NULL FB,
3227 * which will lead to problems later if we don't fix it up. The
3228 * simplest solution is to just disable the primary plane now and
3229 * pretend the BIOS never had it enabled.
3231 intel_plane_disable_noatomic(intel_crtc
, intel_plane
);
3236 intel_state
->base
.rotation
= plane_config
->rotation
;
3237 intel_fill_fb_ggtt_view(&intel_state
->view
, fb
,
3238 intel_state
->base
.rotation
);
3239 intel_state
->color_plane
[0].stride
=
3240 intel_fb_pitch(fb
, 0, intel_state
->base
.rotation
);
3242 mutex_lock(&dev
->struct_mutex
);
3244 intel_pin_and_fence_fb_obj(fb
,
3246 intel_plane_uses_fence(intel_state
),
3247 &intel_state
->flags
);
3248 mutex_unlock(&dev
->struct_mutex
);
3249 if (IS_ERR(intel_state
->vma
)) {
3250 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3251 intel_crtc
->pipe
, PTR_ERR(intel_state
->vma
));
3253 intel_state
->vma
= NULL
;
3254 drm_framebuffer_put(fb
);
3258 obj
= intel_fb_obj(fb
);
3259 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
3261 plane_state
->src_x
= 0;
3262 plane_state
->src_y
= 0;
3263 plane_state
->src_w
= fb
->width
<< 16;
3264 plane_state
->src_h
= fb
->height
<< 16;
3266 plane_state
->crtc_x
= 0;
3267 plane_state
->crtc_y
= 0;
3268 plane_state
->crtc_w
= fb
->width
;
3269 plane_state
->crtc_h
= fb
->height
;
3271 intel_state
->base
.src
= drm_plane_state_src(plane_state
);
3272 intel_state
->base
.dst
= drm_plane_state_dest(plane_state
);
3274 if (i915_gem_object_is_tiled(obj
))
3275 dev_priv
->preserve_bios_swizzle
= true;
3277 plane_state
->fb
= fb
;
3278 plane_state
->crtc
= &intel_crtc
->base
;
3280 atomic_or(to_intel_plane(primary
)->frontbuffer_bit
,
3281 &obj
->frontbuffer_bits
);
3284 static int skl_max_plane_width(const struct drm_framebuffer
*fb
,
3286 unsigned int rotation
)
3288 int cpp
= fb
->format
->cpp
[color_plane
];
3290 switch (fb
->modifier
) {
3291 case DRM_FORMAT_MOD_LINEAR
:
3292 case I915_FORMAT_MOD_X_TILED
:
3294 case I915_FORMAT_MOD_Y_TILED_CCS
:
3295 case I915_FORMAT_MOD_Yf_TILED_CCS
:
3296 /* FIXME AUX plane? */
3297 case I915_FORMAT_MOD_Y_TILED
:
3298 case I915_FORMAT_MOD_Yf_TILED
:
3304 MISSING_CASE(fb
->modifier
);
3309 static int glk_max_plane_width(const struct drm_framebuffer
*fb
,
3311 unsigned int rotation
)
3313 int cpp
= fb
->format
->cpp
[color_plane
];
3315 switch (fb
->modifier
) {
3316 case DRM_FORMAT_MOD_LINEAR
:
3317 case I915_FORMAT_MOD_X_TILED
:
3322 case I915_FORMAT_MOD_Y_TILED_CCS
:
3323 case I915_FORMAT_MOD_Yf_TILED_CCS
:
3324 /* FIXME AUX plane? */
3325 case I915_FORMAT_MOD_Y_TILED
:
3326 case I915_FORMAT_MOD_Yf_TILED
:
3332 MISSING_CASE(fb
->modifier
);
3337 static int icl_max_plane_width(const struct drm_framebuffer
*fb
,
3339 unsigned int rotation
)
3344 static bool skl_check_main_ccs_coordinates(struct intel_plane_state
*plane_state
,
3345 int main_x
, int main_y
, u32 main_offset
)
3347 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3348 int hsub
= fb
->format
->hsub
;
3349 int vsub
= fb
->format
->vsub
;
3350 int aux_x
= plane_state
->color_plane
[1].x
;
3351 int aux_y
= plane_state
->color_plane
[1].y
;
3352 u32 aux_offset
= plane_state
->color_plane
[1].offset
;
3353 u32 alignment
= intel_surf_alignment(fb
, 1);
3355 while (aux_offset
>= main_offset
&& aux_y
<= main_y
) {
3358 if (aux_x
== main_x
&& aux_y
== main_y
)
3361 if (aux_offset
== 0)
3366 aux_offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 1,
3367 aux_offset
, aux_offset
- alignment
);
3368 aux_x
= x
* hsub
+ aux_x
% hsub
;
3369 aux_y
= y
* vsub
+ aux_y
% vsub
;
3372 if (aux_x
!= main_x
|| aux_y
!= main_y
)
3375 plane_state
->color_plane
[1].offset
= aux_offset
;
3376 plane_state
->color_plane
[1].x
= aux_x
;
3377 plane_state
->color_plane
[1].y
= aux_y
;
3382 static int skl_check_main_surface(struct intel_plane_state
*plane_state
)
3384 struct drm_i915_private
*dev_priv
= to_i915(plane_state
->base
.plane
->dev
);
3385 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3386 unsigned int rotation
= plane_state
->base
.rotation
;
3387 int x
= plane_state
->base
.src
.x1
>> 16;
3388 int y
= plane_state
->base
.src
.y1
>> 16;
3389 int w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3390 int h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3392 int max_height
= 4096;
3393 u32 alignment
, offset
, aux_offset
= plane_state
->color_plane
[1].offset
;
3395 if (INTEL_GEN(dev_priv
) >= 11)
3396 max_width
= icl_max_plane_width(fb
, 0, rotation
);
3397 else if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
3398 max_width
= glk_max_plane_width(fb
, 0, rotation
);
3400 max_width
= skl_max_plane_width(fb
, 0, rotation
);
3402 if (w
> max_width
|| h
> max_height
) {
3403 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3404 w
, h
, max_width
, max_height
);
3408 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3409 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 0);
3410 alignment
= intel_surf_alignment(fb
, 0);
3413 * AUX surface offset is specified as the distance from the
3414 * main surface offset, and it must be non-negative. Make
3415 * sure that is what we will get.
3417 if (offset
> aux_offset
)
3418 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3419 offset
, aux_offset
& ~(alignment
- 1));
3422 * When using an X-tiled surface, the plane blows up
3423 * if the x offset + width exceed the stride.
3425 * TODO: linear and Y-tiled seem fine, Yf untested,
3427 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
) {
3428 int cpp
= fb
->format
->cpp
[0];
3430 while ((x
+ w
) * cpp
> plane_state
->color_plane
[0].stride
) {
3432 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3436 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3437 offset
, offset
- alignment
);
3442 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3443 * they match with the main surface x/y offsets.
3445 if (is_ccs_modifier(fb
->modifier
)) {
3446 while (!skl_check_main_ccs_coordinates(plane_state
, x
, y
, offset
)) {
3450 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3451 offset
, offset
- alignment
);
3454 if (x
!= plane_state
->color_plane
[1].x
|| y
!= plane_state
->color_plane
[1].y
) {
3455 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3460 plane_state
->color_plane
[0].offset
= offset
;
3461 plane_state
->color_plane
[0].x
= x
;
3462 plane_state
->color_plane
[0].y
= y
;
3465 * Put the final coordinates back so that the src
3466 * coordinate checks will see the right values.
3468 drm_rect_translate(&plane_state
->base
.src
,
3469 (x
<< 16) - plane_state
->base
.src
.x1
,
3470 (y
<< 16) - plane_state
->base
.src
.y1
);
3475 static int skl_check_nv12_aux_surface(struct intel_plane_state
*plane_state
)
3477 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3478 unsigned int rotation
= plane_state
->base
.rotation
;
3479 int max_width
= skl_max_plane_width(fb
, 1, rotation
);
3480 int max_height
= 4096;
3481 int x
= plane_state
->base
.src
.x1
>> 17;
3482 int y
= plane_state
->base
.src
.y1
>> 17;
3483 int w
= drm_rect_width(&plane_state
->base
.src
) >> 17;
3484 int h
= drm_rect_height(&plane_state
->base
.src
) >> 17;
3487 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3488 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 1);
3490 /* FIXME not quite sure how/if these apply to the chroma plane */
3491 if (w
> max_width
|| h
> max_height
) {
3492 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3493 w
, h
, max_width
, max_height
);
3497 plane_state
->color_plane
[1].offset
= offset
;
3498 plane_state
->color_plane
[1].x
= x
;
3499 plane_state
->color_plane
[1].y
= y
;
3504 static int skl_check_ccs_aux_surface(struct intel_plane_state
*plane_state
)
3506 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3507 int src_x
= plane_state
->base
.src
.x1
>> 16;
3508 int src_y
= plane_state
->base
.src
.y1
>> 16;
3509 int hsub
= fb
->format
->hsub
;
3510 int vsub
= fb
->format
->vsub
;
3511 int x
= src_x
/ hsub
;
3512 int y
= src_y
/ vsub
;
3515 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3516 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 1);
3518 plane_state
->color_plane
[1].offset
= offset
;
3519 plane_state
->color_plane
[1].x
= x
* hsub
+ src_x
% hsub
;
3520 plane_state
->color_plane
[1].y
= y
* vsub
+ src_y
% vsub
;
3525 int skl_check_plane_surface(struct intel_plane_state
*plane_state
)
3527 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3530 ret
= intel_plane_compute_gtt(plane_state
);
3534 if (!plane_state
->base
.visible
)
3538 * Handle the AUX surface first since
3539 * the main surface setup depends on it.
3541 if (is_planar_yuv_format(fb
->format
->format
)) {
3542 ret
= skl_check_nv12_aux_surface(plane_state
);
3545 } else if (is_ccs_modifier(fb
->modifier
)) {
3546 ret
= skl_check_ccs_aux_surface(plane_state
);
3550 plane_state
->color_plane
[1].offset
= ~0xfff;
3551 plane_state
->color_plane
[1].x
= 0;
3552 plane_state
->color_plane
[1].y
= 0;
3555 ret
= skl_check_main_surface(plane_state
);
3563 i9xx_plane_max_stride(struct intel_plane
*plane
,
3564 u32 pixel_format
, u64 modifier
,
3565 unsigned int rotation
)
3567 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3569 if (!HAS_GMCH(dev_priv
)) {
3571 } else if (INTEL_GEN(dev_priv
) >= 4) {
3572 if (modifier
== I915_FORMAT_MOD_X_TILED
)
3576 } else if (INTEL_GEN(dev_priv
) >= 3) {
3577 if (modifier
== I915_FORMAT_MOD_X_TILED
)
3582 if (plane
->i9xx_plane
== PLANE_C
)
3589 static u32
i9xx_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
3591 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3592 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3595 if (crtc_state
->gamma_enable
)
3596 dspcntr
|= DISPPLANE_GAMMA_ENABLE
;
3598 if (crtc_state
->csc_enable
)
3599 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
3601 if (INTEL_GEN(dev_priv
) < 5)
3602 dspcntr
|= DISPPLANE_SEL_PIPE(crtc
->pipe
);
3607 static u32
i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3608 const struct intel_plane_state
*plane_state
)
3610 struct drm_i915_private
*dev_priv
=
3611 to_i915(plane_state
->base
.plane
->dev
);
3612 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3613 unsigned int rotation
= plane_state
->base
.rotation
;
3616 dspcntr
= DISPLAY_PLANE_ENABLE
;
3618 if (IS_G4X(dev_priv
) || IS_GEN(dev_priv
, 5) ||
3619 IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
))
3620 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3622 switch (fb
->format
->format
) {
3624 dspcntr
|= DISPPLANE_8BPP
;
3626 case DRM_FORMAT_XRGB1555
:
3627 dspcntr
|= DISPPLANE_BGRX555
;
3629 case DRM_FORMAT_RGB565
:
3630 dspcntr
|= DISPPLANE_BGRX565
;
3632 case DRM_FORMAT_XRGB8888
:
3633 dspcntr
|= DISPPLANE_BGRX888
;
3635 case DRM_FORMAT_XBGR8888
:
3636 dspcntr
|= DISPPLANE_RGBX888
;
3638 case DRM_FORMAT_XRGB2101010
:
3639 dspcntr
|= DISPPLANE_BGRX101010
;
3641 case DRM_FORMAT_XBGR2101010
:
3642 dspcntr
|= DISPPLANE_RGBX101010
;
3645 MISSING_CASE(fb
->format
->format
);
3649 if (INTEL_GEN(dev_priv
) >= 4 &&
3650 fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3651 dspcntr
|= DISPPLANE_TILED
;
3653 if (rotation
& DRM_MODE_ROTATE_180
)
3654 dspcntr
|= DISPPLANE_ROTATE_180
;
3656 if (rotation
& DRM_MODE_REFLECT_X
)
3657 dspcntr
|= DISPPLANE_MIRROR
;
3662 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
)
3664 struct drm_i915_private
*dev_priv
=
3665 to_i915(plane_state
->base
.plane
->dev
);
3670 ret
= intel_plane_compute_gtt(plane_state
);
3674 if (!plane_state
->base
.visible
)
3677 src_x
= plane_state
->base
.src
.x1
>> 16;
3678 src_y
= plane_state
->base
.src
.y1
>> 16;
3680 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
3682 if (INTEL_GEN(dev_priv
) >= 4)
3683 offset
= intel_plane_compute_aligned_offset(&src_x
, &src_y
,
3689 * Put the final coordinates back so that the src
3690 * coordinate checks will see the right values.
3692 drm_rect_translate(&plane_state
->base
.src
,
3693 (src_x
<< 16) - plane_state
->base
.src
.x1
,
3694 (src_y
<< 16) - plane_state
->base
.src
.y1
);
3696 /* HSW/BDW do this automagically in hardware */
3697 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
)) {
3698 unsigned int rotation
= plane_state
->base
.rotation
;
3699 int src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3700 int src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3702 if (rotation
& DRM_MODE_ROTATE_180
) {
3705 } else if (rotation
& DRM_MODE_REFLECT_X
) {
3710 plane_state
->color_plane
[0].offset
= offset
;
3711 plane_state
->color_plane
[0].x
= src_x
;
3712 plane_state
->color_plane
[0].y
= src_y
;
3718 i9xx_plane_check(struct intel_crtc_state
*crtc_state
,
3719 struct intel_plane_state
*plane_state
)
3723 ret
= chv_plane_check_rotation(plane_state
);
3727 ret
= drm_atomic_helper_check_plane_state(&plane_state
->base
,
3729 DRM_PLANE_HELPER_NO_SCALING
,
3730 DRM_PLANE_HELPER_NO_SCALING
,
3735 ret
= i9xx_check_plane_surface(plane_state
);
3739 if (!plane_state
->base
.visible
)
3742 ret
= intel_plane_check_src_coordinates(plane_state
);
3746 plane_state
->ctl
= i9xx_plane_ctl(crtc_state
, plane_state
);
3751 static void i9xx_update_plane(struct intel_plane
*plane
,
3752 const struct intel_crtc_state
*crtc_state
,
3753 const struct intel_plane_state
*plane_state
)
3755 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3756 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3758 int x
= plane_state
->color_plane
[0].x
;
3759 int y
= plane_state
->color_plane
[0].y
;
3760 unsigned long irqflags
;
3764 dspcntr
= plane_state
->ctl
| i9xx_plane_ctl_crtc(crtc_state
);
3766 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3768 if (INTEL_GEN(dev_priv
) >= 4)
3769 dspaddr_offset
= plane_state
->color_plane
[0].offset
;
3771 dspaddr_offset
= linear_offset
;
3773 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3775 I915_WRITE_FW(DSPSTRIDE(i9xx_plane
), plane_state
->color_plane
[0].stride
);
3777 if (INTEL_GEN(dev_priv
) < 4) {
3778 /* pipesrc and dspsize control the size that is scaled from,
3779 * which should always be the user's requested size.
3781 I915_WRITE_FW(DSPPOS(i9xx_plane
), 0);
3782 I915_WRITE_FW(DSPSIZE(i9xx_plane
),
3783 ((crtc_state
->pipe_src_h
- 1) << 16) |
3784 (crtc_state
->pipe_src_w
- 1));
3785 } else if (IS_CHERRYVIEW(dev_priv
) && i9xx_plane
== PLANE_B
) {
3786 I915_WRITE_FW(PRIMPOS(i9xx_plane
), 0);
3787 I915_WRITE_FW(PRIMSIZE(i9xx_plane
),
3788 ((crtc_state
->pipe_src_h
- 1) << 16) |
3789 (crtc_state
->pipe_src_w
- 1));
3790 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane
), 0);
3793 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3794 I915_WRITE_FW(DSPOFFSET(i9xx_plane
), (y
<< 16) | x
);
3795 } else if (INTEL_GEN(dev_priv
) >= 4) {
3796 I915_WRITE_FW(DSPLINOFF(i9xx_plane
), linear_offset
);
3797 I915_WRITE_FW(DSPTILEOFF(i9xx_plane
), (y
<< 16) | x
);
3801 * The control register self-arms if the plane was previously
3802 * disabled. Try to make the plane enable atomic by writing
3803 * the control register just before the surface register.
3805 I915_WRITE_FW(DSPCNTR(i9xx_plane
), dspcntr
);
3806 if (INTEL_GEN(dev_priv
) >= 4)
3807 I915_WRITE_FW(DSPSURF(i9xx_plane
),
3808 intel_plane_ggtt_offset(plane_state
) +
3811 I915_WRITE_FW(DSPADDR(i9xx_plane
),
3812 intel_plane_ggtt_offset(plane_state
) +
3815 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3818 static void i9xx_disable_plane(struct intel_plane
*plane
,
3819 const struct intel_crtc_state
*crtc_state
)
3821 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3822 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3823 unsigned long irqflags
;
3827 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3828 * enable on ilk+ affect the pipe bottom color as
3829 * well, so we must configure them even if the plane
3832 * On pre-g4x there is no way to gamma correct the
3833 * pipe bottom color but we'll keep on doing this
3834 * anyway so that the crtc state readout works correctly.
3836 dspcntr
= i9xx_plane_ctl_crtc(crtc_state
);
3838 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3840 I915_WRITE_FW(DSPCNTR(i9xx_plane
), dspcntr
);
3841 if (INTEL_GEN(dev_priv
) >= 4)
3842 I915_WRITE_FW(DSPSURF(i9xx_plane
), 0);
3844 I915_WRITE_FW(DSPADDR(i9xx_plane
), 0);
3846 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3849 static bool i9xx_plane_get_hw_state(struct intel_plane
*plane
,
3852 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3853 enum intel_display_power_domain power_domain
;
3854 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3855 intel_wakeref_t wakeref
;
3860 * Not 100% correct for planes that can move between pipes,
3861 * but that's only the case for gen2-4 which don't have any
3862 * display power wells.
3864 power_domain
= POWER_DOMAIN_PIPE(plane
->pipe
);
3865 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
3869 val
= I915_READ(DSPCNTR(i9xx_plane
));
3871 ret
= val
& DISPLAY_PLANE_ENABLE
;
3873 if (INTEL_GEN(dev_priv
) >= 5)
3874 *pipe
= plane
->pipe
;
3876 *pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
3877 DISPPLANE_SEL_PIPE_SHIFT
;
3879 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
3884 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
3886 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3887 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3889 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
3890 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
3891 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
3895 * This function detaches (aka. unbinds) unused scalers in hardware
3897 static void skl_detach_scalers(const struct intel_crtc_state
*crtc_state
)
3899 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3900 const struct intel_crtc_scaler_state
*scaler_state
=
3901 &crtc_state
->scaler_state
;
3904 /* loop through and disable scalers that aren't in use */
3905 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
3906 if (!scaler_state
->scalers
[i
].in_use
)
3907 skl_detach_scaler(intel_crtc
, i
);
3911 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer
*fb
,
3912 int color_plane
, unsigned int rotation
)
3915 * The stride is either expressed as a multiple of 64 bytes chunks for
3916 * linear buffers or in number of tiles for tiled buffers.
3918 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
3920 else if (drm_rotation_90_or_270(rotation
))
3921 return intel_tile_height(fb
, color_plane
);
3923 return intel_tile_width_bytes(fb
, color_plane
);
3926 u32
skl_plane_stride(const struct intel_plane_state
*plane_state
,
3929 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3930 unsigned int rotation
= plane_state
->base
.rotation
;
3931 u32 stride
= plane_state
->color_plane
[color_plane
].stride
;
3933 if (color_plane
>= fb
->format
->num_planes
)
3936 return stride
/ skl_plane_stride_mult(fb
, color_plane
, rotation
);
3939 static u32
skl_plane_ctl_format(u32 pixel_format
)
3941 switch (pixel_format
) {
3943 return PLANE_CTL_FORMAT_INDEXED
;
3944 case DRM_FORMAT_RGB565
:
3945 return PLANE_CTL_FORMAT_RGB_565
;
3946 case DRM_FORMAT_XBGR8888
:
3947 case DRM_FORMAT_ABGR8888
:
3948 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
3949 case DRM_FORMAT_XRGB8888
:
3950 case DRM_FORMAT_ARGB8888
:
3951 return PLANE_CTL_FORMAT_XRGB_8888
;
3952 case DRM_FORMAT_XRGB2101010
:
3953 return PLANE_CTL_FORMAT_XRGB_2101010
;
3954 case DRM_FORMAT_XBGR2101010
:
3955 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3956 case DRM_FORMAT_XBGR16161616F
:
3957 case DRM_FORMAT_ABGR16161616F
:
3958 return PLANE_CTL_FORMAT_XRGB_16161616F
| PLANE_CTL_ORDER_RGBX
;
3959 case DRM_FORMAT_XRGB16161616F
:
3960 case DRM_FORMAT_ARGB16161616F
:
3961 return PLANE_CTL_FORMAT_XRGB_16161616F
;
3962 case DRM_FORMAT_YUYV
:
3963 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3964 case DRM_FORMAT_YVYU
:
3965 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3966 case DRM_FORMAT_UYVY
:
3967 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3968 case DRM_FORMAT_VYUY
:
3969 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3970 case DRM_FORMAT_NV12
:
3971 return PLANE_CTL_FORMAT_NV12
;
3972 case DRM_FORMAT_P010
:
3973 return PLANE_CTL_FORMAT_P010
;
3974 case DRM_FORMAT_P012
:
3975 return PLANE_CTL_FORMAT_P012
;
3976 case DRM_FORMAT_P016
:
3977 return PLANE_CTL_FORMAT_P016
;
3978 case DRM_FORMAT_Y210
:
3979 return PLANE_CTL_FORMAT_Y210
;
3980 case DRM_FORMAT_Y212
:
3981 return PLANE_CTL_FORMAT_Y212
;
3982 case DRM_FORMAT_Y216
:
3983 return PLANE_CTL_FORMAT_Y216
;
3984 case DRM_FORMAT_XVYU2101010
:
3985 return PLANE_CTL_FORMAT_Y410
;
3986 case DRM_FORMAT_XVYU12_16161616
:
3987 return PLANE_CTL_FORMAT_Y412
;
3988 case DRM_FORMAT_XVYU16161616
:
3989 return PLANE_CTL_FORMAT_Y416
;
3991 MISSING_CASE(pixel_format
);
3997 static u32
skl_plane_ctl_alpha(const struct intel_plane_state
*plane_state
)
3999 if (!plane_state
->base
.fb
->format
->has_alpha
)
4000 return PLANE_CTL_ALPHA_DISABLE
;
4002 switch (plane_state
->base
.pixel_blend_mode
) {
4003 case DRM_MODE_BLEND_PIXEL_NONE
:
4004 return PLANE_CTL_ALPHA_DISABLE
;
4005 case DRM_MODE_BLEND_PREMULTI
:
4006 return PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
4007 case DRM_MODE_BLEND_COVERAGE
:
4008 return PLANE_CTL_ALPHA_HW_PREMULTIPLY
;
4010 MISSING_CASE(plane_state
->base
.pixel_blend_mode
);
4011 return PLANE_CTL_ALPHA_DISABLE
;
4015 static u32
glk_plane_color_ctl_alpha(const struct intel_plane_state
*plane_state
)
4017 if (!plane_state
->base
.fb
->format
->has_alpha
)
4018 return PLANE_COLOR_ALPHA_DISABLE
;
4020 switch (plane_state
->base
.pixel_blend_mode
) {
4021 case DRM_MODE_BLEND_PIXEL_NONE
:
4022 return PLANE_COLOR_ALPHA_DISABLE
;
4023 case DRM_MODE_BLEND_PREMULTI
:
4024 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY
;
4025 case DRM_MODE_BLEND_COVERAGE
:
4026 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY
;
4028 MISSING_CASE(plane_state
->base
.pixel_blend_mode
);
4029 return PLANE_COLOR_ALPHA_DISABLE
;
4033 static u32
skl_plane_ctl_tiling(u64 fb_modifier
)
4035 switch (fb_modifier
) {
4036 case DRM_FORMAT_MOD_LINEAR
:
4038 case I915_FORMAT_MOD_X_TILED
:
4039 return PLANE_CTL_TILED_X
;
4040 case I915_FORMAT_MOD_Y_TILED
:
4041 return PLANE_CTL_TILED_Y
;
4042 case I915_FORMAT_MOD_Y_TILED_CCS
:
4043 return PLANE_CTL_TILED_Y
| PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
;
4044 case I915_FORMAT_MOD_Yf_TILED
:
4045 return PLANE_CTL_TILED_YF
;
4046 case I915_FORMAT_MOD_Yf_TILED_CCS
:
4047 return PLANE_CTL_TILED_YF
| PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
;
4049 MISSING_CASE(fb_modifier
);
4055 static u32
skl_plane_ctl_rotate(unsigned int rotate
)
4058 case DRM_MODE_ROTATE_0
:
4061 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4062 * while i915 HW rotation is clockwise, thats why this swapping.
4064 case DRM_MODE_ROTATE_90
:
4065 return PLANE_CTL_ROTATE_270
;
4066 case DRM_MODE_ROTATE_180
:
4067 return PLANE_CTL_ROTATE_180
;
4068 case DRM_MODE_ROTATE_270
:
4069 return PLANE_CTL_ROTATE_90
;
4071 MISSING_CASE(rotate
);
4077 static u32
cnl_plane_ctl_flip(unsigned int reflect
)
4082 case DRM_MODE_REFLECT_X
:
4083 return PLANE_CTL_FLIP_HORIZONTAL
;
4084 case DRM_MODE_REFLECT_Y
:
4086 MISSING_CASE(reflect
);
4092 u32
skl_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
4094 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
4097 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
4100 if (crtc_state
->gamma_enable
)
4101 plane_ctl
|= PLANE_CTL_PIPE_GAMMA_ENABLE
;
4103 if (crtc_state
->csc_enable
)
4104 plane_ctl
|= PLANE_CTL_PIPE_CSC_ENABLE
;
4109 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
4110 const struct intel_plane_state
*plane_state
)
4112 struct drm_i915_private
*dev_priv
=
4113 to_i915(plane_state
->base
.plane
->dev
);
4114 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4115 unsigned int rotation
= plane_state
->base
.rotation
;
4116 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
4119 plane_ctl
= PLANE_CTL_ENABLE
;
4121 if (INTEL_GEN(dev_priv
) < 10 && !IS_GEMINILAKE(dev_priv
)) {
4122 plane_ctl
|= skl_plane_ctl_alpha(plane_state
);
4123 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
4125 if (plane_state
->base
.color_encoding
== DRM_COLOR_YCBCR_BT709
)
4126 plane_ctl
|= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709
;
4128 if (plane_state
->base
.color_range
== DRM_COLOR_YCBCR_FULL_RANGE
)
4129 plane_ctl
|= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE
;
4132 plane_ctl
|= skl_plane_ctl_format(fb
->format
->format
);
4133 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
);
4134 plane_ctl
|= skl_plane_ctl_rotate(rotation
& DRM_MODE_ROTATE_MASK
);
4136 if (INTEL_GEN(dev_priv
) >= 10)
4137 plane_ctl
|= cnl_plane_ctl_flip(rotation
&
4138 DRM_MODE_REFLECT_MASK
);
4140 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
4141 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
4142 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
4143 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
4148 u32
glk_plane_color_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
4150 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
4151 u32 plane_color_ctl
= 0;
4153 if (INTEL_GEN(dev_priv
) >= 11)
4154 return plane_color_ctl
;
4156 if (crtc_state
->gamma_enable
)
4157 plane_color_ctl
|= PLANE_COLOR_PIPE_GAMMA_ENABLE
;
4159 if (crtc_state
->csc_enable
)
4160 plane_color_ctl
|= PLANE_COLOR_PIPE_CSC_ENABLE
;
4162 return plane_color_ctl
;
4165 u32
glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state
,
4166 const struct intel_plane_state
*plane_state
)
4168 struct drm_i915_private
*dev_priv
=
4169 to_i915(plane_state
->base
.plane
->dev
);
4170 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4171 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
4172 u32 plane_color_ctl
= 0;
4174 plane_color_ctl
|= PLANE_COLOR_PLANE_GAMMA_DISABLE
;
4175 plane_color_ctl
|= glk_plane_color_ctl_alpha(plane_state
);
4177 if (fb
->format
->is_yuv
&& !icl_is_hdr_plane(dev_priv
, plane
->id
)) {
4178 if (plane_state
->base
.color_encoding
== DRM_COLOR_YCBCR_BT709
)
4179 plane_color_ctl
|= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709
;
4181 plane_color_ctl
|= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709
;
4183 if (plane_state
->base
.color_range
== DRM_COLOR_YCBCR_FULL_RANGE
)
4184 plane_color_ctl
|= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE
;
4185 } else if (fb
->format
->is_yuv
) {
4186 plane_color_ctl
|= PLANE_COLOR_INPUT_CSC_ENABLE
;
4189 return plane_color_ctl
;
4193 __intel_display_resume(struct drm_device
*dev
,
4194 struct drm_atomic_state
*state
,
4195 struct drm_modeset_acquire_ctx
*ctx
)
4197 struct drm_crtc_state
*crtc_state
;
4198 struct drm_crtc
*crtc
;
4201 intel_modeset_setup_hw_state(dev
, ctx
);
4202 i915_redisable_vga(to_i915(dev
));
4208 * We've duplicated the state, pointers to the old state are invalid.
4210 * Don't attempt to use the old state until we commit the duplicated state.
4212 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
4214 * Force recalculation even if we restore
4215 * current state. With fast modeset this may not result
4216 * in a modeset when the state is compatible.
4218 crtc_state
->mode_changed
= true;
4221 /* ignore any reset values/BIOS leftovers in the WM registers */
4222 if (!HAS_GMCH(to_i915(dev
)))
4223 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
4225 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
4227 WARN_ON(ret
== -EDEADLK
);
4231 static bool gpu_reset_clobbers_display(struct drm_i915_private
*dev_priv
)
4233 return (INTEL_INFO(dev_priv
)->gpu_reset_clobbers_display
&&
4234 intel_has_gpu_reset(dev_priv
));
4237 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
4239 struct drm_device
*dev
= &dev_priv
->drm
;
4240 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
4241 struct drm_atomic_state
*state
;
4244 /* reset doesn't touch the display */
4245 if (!i915_modparams
.force_reset_modeset_test
&&
4246 !gpu_reset_clobbers_display(dev_priv
))
4249 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4250 set_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
4251 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
4253 if (atomic_read(&dev_priv
->gpu_error
.pending_fb_pin
)) {
4254 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4255 i915_gem_set_wedged(dev_priv
);
4259 * Need mode_config.mutex so that we don't
4260 * trample ongoing ->detect() and whatnot.
4262 mutex_lock(&dev
->mode_config
.mutex
);
4263 drm_modeset_acquire_init(ctx
, 0);
4265 ret
= drm_modeset_lock_all_ctx(dev
, ctx
);
4266 if (ret
!= -EDEADLK
)
4269 drm_modeset_backoff(ctx
);
4272 * Disabling the crtcs gracefully seems nicer. Also the
4273 * g33 docs say we should at least disable all the planes.
4275 state
= drm_atomic_helper_duplicate_state(dev
, ctx
);
4276 if (IS_ERR(state
)) {
4277 ret
= PTR_ERR(state
);
4278 DRM_ERROR("Duplicating state failed with %i\n", ret
);
4282 ret
= drm_atomic_helper_disable_all(dev
, ctx
);
4284 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
4285 drm_atomic_state_put(state
);
4289 dev_priv
->modeset_restore_state
= state
;
4290 state
->acquire_ctx
= ctx
;
4293 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
4295 struct drm_device
*dev
= &dev_priv
->drm
;
4296 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
4297 struct drm_atomic_state
*state
;
4300 /* reset doesn't touch the display */
4301 if (!test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
4304 state
= fetch_and_zero(&dev_priv
->modeset_restore_state
);
4308 /* reset doesn't touch the display */
4309 if (!gpu_reset_clobbers_display(dev_priv
)) {
4310 /* for testing only restore the display */
4311 ret
= __intel_display_resume(dev
, state
, ctx
);
4313 DRM_ERROR("Restoring old state failed with %i\n", ret
);
4316 * The display has been reset as well,
4317 * so need a full re-initialization.
4319 intel_pps_unlock_regs_wa(dev_priv
);
4320 intel_modeset_init_hw(dev
);
4321 intel_init_clock_gating(dev_priv
);
4323 spin_lock_irq(&dev_priv
->irq_lock
);
4324 if (dev_priv
->display
.hpd_irq_setup
)
4325 dev_priv
->display
.hpd_irq_setup(dev_priv
);
4326 spin_unlock_irq(&dev_priv
->irq_lock
);
4328 ret
= __intel_display_resume(dev
, state
, ctx
);
4330 DRM_ERROR("Restoring old state failed with %i\n", ret
);
4332 intel_hpd_init(dev_priv
);
4335 drm_atomic_state_put(state
);
4337 drm_modeset_drop_locks(ctx
);
4338 drm_modeset_acquire_fini(ctx
);
4339 mutex_unlock(&dev
->mode_config
.mutex
);
4341 clear_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
4344 static void icl_set_pipe_chicken(struct intel_crtc
*crtc
)
4346 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4347 enum pipe pipe
= crtc
->pipe
;
4350 tmp
= I915_READ(PIPE_CHICKEN(pipe
));
4353 * Display WA #1153: icl
4354 * enable hardware to bypass the alpha math
4355 * and rounding for per-pixel values 00 and 0xff
4357 tmp
|= PER_PIXEL_ALPHA_BYPASS_EN
;
4359 * Display WA # 1605353570: icl
4360 * Set the pixel rounding bit to 1 for allowing
4361 * passthrough of Frame buffer pixels unmodified
4364 tmp
|= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU
;
4365 I915_WRITE(PIPE_CHICKEN(pipe
), tmp
);
4368 static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state
,
4369 const struct intel_crtc_state
*new_crtc_state
)
4371 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
4372 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4374 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
4375 crtc
->base
.mode
= new_crtc_state
->base
.mode
;
4378 * Update pipe size and adjust fitter if needed: the reason for this is
4379 * that in compute_mode_changes we check the native mode (not the pfit
4380 * mode) to see if we can flip rather than do a full mode set. In the
4381 * fastboot case, we'll flip, but if we don't update the pipesrc and
4382 * pfit state, we'll end up with a big fb scanned out into the wrong
4386 I915_WRITE(PIPESRC(crtc
->pipe
),
4387 ((new_crtc_state
->pipe_src_w
- 1) << 16) |
4388 (new_crtc_state
->pipe_src_h
- 1));
4390 /* on skylake this is done by detaching scalers */
4391 if (INTEL_GEN(dev_priv
) >= 9) {
4392 skl_detach_scalers(new_crtc_state
);
4394 if (new_crtc_state
->pch_pfit
.enabled
)
4395 skylake_pfit_enable(new_crtc_state
);
4396 } else if (HAS_PCH_SPLIT(dev_priv
)) {
4397 if (new_crtc_state
->pch_pfit
.enabled
)
4398 ironlake_pfit_enable(new_crtc_state
);
4399 else if (old_crtc_state
->pch_pfit
.enabled
)
4400 ironlake_pfit_disable(old_crtc_state
);
4403 if (INTEL_GEN(dev_priv
) >= 11)
4404 icl_set_pipe_chicken(crtc
);
4407 static void intel_fdi_normal_train(struct intel_crtc
*crtc
)
4409 struct drm_device
*dev
= crtc
->base
.dev
;
4410 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4411 int pipe
= crtc
->pipe
;
4415 /* enable normal train */
4416 reg
= FDI_TX_CTL(pipe
);
4417 temp
= I915_READ(reg
);
4418 if (IS_IVYBRIDGE(dev_priv
)) {
4419 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4420 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
4422 temp
&= ~FDI_LINK_TRAIN_NONE
;
4423 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
4425 I915_WRITE(reg
, temp
);
4427 reg
= FDI_RX_CTL(pipe
);
4428 temp
= I915_READ(reg
);
4429 if (HAS_PCH_CPT(dev_priv
)) {
4430 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4431 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
4433 temp
&= ~FDI_LINK_TRAIN_NONE
;
4434 temp
|= FDI_LINK_TRAIN_NONE
;
4436 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
4438 /* wait one idle pattern time */
4442 /* IVB wants error correction enabled */
4443 if (IS_IVYBRIDGE(dev_priv
))
4444 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
4445 FDI_FE_ERRC_ENABLE
);
4448 /* The FDI link training functions for ILK/Ibexpeak. */
4449 static void ironlake_fdi_link_train(struct intel_crtc
*crtc
,
4450 const struct intel_crtc_state
*crtc_state
)
4452 struct drm_device
*dev
= crtc
->base
.dev
;
4453 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4454 int pipe
= crtc
->pipe
;
4458 /* FDI needs bits from pipe first */
4459 assert_pipe_enabled(dev_priv
, pipe
);
4461 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4463 reg
= FDI_RX_IMR(pipe
);
4464 temp
= I915_READ(reg
);
4465 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4466 temp
&= ~FDI_RX_BIT_LOCK
;
4467 I915_WRITE(reg
, temp
);
4471 /* enable CPU FDI TX and PCH FDI RX */
4472 reg
= FDI_TX_CTL(pipe
);
4473 temp
= I915_READ(reg
);
4474 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4475 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4476 temp
&= ~FDI_LINK_TRAIN_NONE
;
4477 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4478 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4480 reg
= FDI_RX_CTL(pipe
);
4481 temp
= I915_READ(reg
);
4482 temp
&= ~FDI_LINK_TRAIN_NONE
;
4483 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4484 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4489 /* Ironlake workaround, enable clock pointer after FDI enable*/
4490 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4491 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
4492 FDI_RX_PHASE_SYNC_POINTER_EN
);
4494 reg
= FDI_RX_IIR(pipe
);
4495 for (tries
= 0; tries
< 5; tries
++) {
4496 temp
= I915_READ(reg
);
4497 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4499 if ((temp
& FDI_RX_BIT_LOCK
)) {
4500 DRM_DEBUG_KMS("FDI train 1 done.\n");
4501 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4506 DRM_ERROR("FDI train 1 fail!\n");
4509 reg
= FDI_TX_CTL(pipe
);
4510 temp
= I915_READ(reg
);
4511 temp
&= ~FDI_LINK_TRAIN_NONE
;
4512 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4513 I915_WRITE(reg
, temp
);
4515 reg
= FDI_RX_CTL(pipe
);
4516 temp
= I915_READ(reg
);
4517 temp
&= ~FDI_LINK_TRAIN_NONE
;
4518 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4519 I915_WRITE(reg
, temp
);
4524 reg
= FDI_RX_IIR(pipe
);
4525 for (tries
= 0; tries
< 5; tries
++) {
4526 temp
= I915_READ(reg
);
4527 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4529 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4530 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4531 DRM_DEBUG_KMS("FDI train 2 done.\n");
4536 DRM_ERROR("FDI train 2 fail!\n");
4538 DRM_DEBUG_KMS("FDI train done\n");
4542 static const int snb_b_fdi_train_param
[] = {
4543 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
4544 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
4545 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
4546 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
4549 /* The FDI link training functions for SNB/Cougarpoint. */
4550 static void gen6_fdi_link_train(struct intel_crtc
*crtc
,
4551 const struct intel_crtc_state
*crtc_state
)
4553 struct drm_device
*dev
= crtc
->base
.dev
;
4554 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4555 int pipe
= crtc
->pipe
;
4559 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4561 reg
= FDI_RX_IMR(pipe
);
4562 temp
= I915_READ(reg
);
4563 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4564 temp
&= ~FDI_RX_BIT_LOCK
;
4565 I915_WRITE(reg
, temp
);
4570 /* enable CPU FDI TX and PCH FDI RX */
4571 reg
= FDI_TX_CTL(pipe
);
4572 temp
= I915_READ(reg
);
4573 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4574 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4575 temp
&= ~FDI_LINK_TRAIN_NONE
;
4576 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4577 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4579 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4580 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4582 I915_WRITE(FDI_RX_MISC(pipe
),
4583 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4585 reg
= FDI_RX_CTL(pipe
);
4586 temp
= I915_READ(reg
);
4587 if (HAS_PCH_CPT(dev_priv
)) {
4588 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4589 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4591 temp
&= ~FDI_LINK_TRAIN_NONE
;
4592 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4594 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4599 for (i
= 0; i
< 4; i
++) {
4600 reg
= FDI_TX_CTL(pipe
);
4601 temp
= I915_READ(reg
);
4602 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4603 temp
|= snb_b_fdi_train_param
[i
];
4604 I915_WRITE(reg
, temp
);
4609 for (retry
= 0; retry
< 5; retry
++) {
4610 reg
= FDI_RX_IIR(pipe
);
4611 temp
= I915_READ(reg
);
4612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4613 if (temp
& FDI_RX_BIT_LOCK
) {
4614 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4615 DRM_DEBUG_KMS("FDI train 1 done.\n");
4624 DRM_ERROR("FDI train 1 fail!\n");
4627 reg
= FDI_TX_CTL(pipe
);
4628 temp
= I915_READ(reg
);
4629 temp
&= ~FDI_LINK_TRAIN_NONE
;
4630 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4631 if (IS_GEN(dev_priv
, 6)) {
4632 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4634 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4636 I915_WRITE(reg
, temp
);
4638 reg
= FDI_RX_CTL(pipe
);
4639 temp
= I915_READ(reg
);
4640 if (HAS_PCH_CPT(dev_priv
)) {
4641 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4642 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4644 temp
&= ~FDI_LINK_TRAIN_NONE
;
4645 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4647 I915_WRITE(reg
, temp
);
4652 for (i
= 0; i
< 4; i
++) {
4653 reg
= FDI_TX_CTL(pipe
);
4654 temp
= I915_READ(reg
);
4655 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4656 temp
|= snb_b_fdi_train_param
[i
];
4657 I915_WRITE(reg
, temp
);
4662 for (retry
= 0; retry
< 5; retry
++) {
4663 reg
= FDI_RX_IIR(pipe
);
4664 temp
= I915_READ(reg
);
4665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4666 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4667 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4668 DRM_DEBUG_KMS("FDI train 2 done.\n");
4677 DRM_ERROR("FDI train 2 fail!\n");
4679 DRM_DEBUG_KMS("FDI train done.\n");
4682 /* Manual link training for Ivy Bridge A0 parts */
4683 static void ivb_manual_fdi_link_train(struct intel_crtc
*crtc
,
4684 const struct intel_crtc_state
*crtc_state
)
4686 struct drm_device
*dev
= crtc
->base
.dev
;
4687 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4688 int pipe
= crtc
->pipe
;
4692 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4694 reg
= FDI_RX_IMR(pipe
);
4695 temp
= I915_READ(reg
);
4696 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4697 temp
&= ~FDI_RX_BIT_LOCK
;
4698 I915_WRITE(reg
, temp
);
4703 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4704 I915_READ(FDI_RX_IIR(pipe
)));
4706 /* Try each vswing and preemphasis setting twice before moving on */
4707 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
4708 /* disable first in case we need to retry */
4709 reg
= FDI_TX_CTL(pipe
);
4710 temp
= I915_READ(reg
);
4711 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
4712 temp
&= ~FDI_TX_ENABLE
;
4713 I915_WRITE(reg
, temp
);
4715 reg
= FDI_RX_CTL(pipe
);
4716 temp
= I915_READ(reg
);
4717 temp
&= ~FDI_LINK_TRAIN_AUTO
;
4718 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4719 temp
&= ~FDI_RX_ENABLE
;
4720 I915_WRITE(reg
, temp
);
4722 /* enable CPU FDI TX and PCH FDI RX */
4723 reg
= FDI_TX_CTL(pipe
);
4724 temp
= I915_READ(reg
);
4725 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4726 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4727 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
4728 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4729 temp
|= snb_b_fdi_train_param
[j
/2];
4730 temp
|= FDI_COMPOSITE_SYNC
;
4731 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4733 I915_WRITE(FDI_RX_MISC(pipe
),
4734 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4736 reg
= FDI_RX_CTL(pipe
);
4737 temp
= I915_READ(reg
);
4738 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4739 temp
|= FDI_COMPOSITE_SYNC
;
4740 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4743 udelay(1); /* should be 0.5us */
4745 for (i
= 0; i
< 4; i
++) {
4746 reg
= FDI_RX_IIR(pipe
);
4747 temp
= I915_READ(reg
);
4748 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4750 if (temp
& FDI_RX_BIT_LOCK
||
4751 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
4752 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4753 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4757 udelay(1); /* should be 0.5us */
4760 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
4765 reg
= FDI_TX_CTL(pipe
);
4766 temp
= I915_READ(reg
);
4767 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4768 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
4769 I915_WRITE(reg
, temp
);
4771 reg
= FDI_RX_CTL(pipe
);
4772 temp
= I915_READ(reg
);
4773 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4774 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4775 I915_WRITE(reg
, temp
);
4778 udelay(2); /* should be 1.5us */
4780 for (i
= 0; i
< 4; i
++) {
4781 reg
= FDI_RX_IIR(pipe
);
4782 temp
= I915_READ(reg
);
4783 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4785 if (temp
& FDI_RX_SYMBOL_LOCK
||
4786 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
4787 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4788 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4792 udelay(2); /* should be 1.5us */
4795 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
4799 DRM_DEBUG_KMS("FDI train done.\n");
4802 static void ironlake_fdi_pll_enable(const struct intel_crtc_state
*crtc_state
)
4804 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4805 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
4806 int pipe
= intel_crtc
->pipe
;
4810 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4811 reg
= FDI_RX_CTL(pipe
);
4812 temp
= I915_READ(reg
);
4813 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
4814 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4815 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4816 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
4821 /* Switch from Rawclk to PCDclk */
4822 temp
= I915_READ(reg
);
4823 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
4828 /* Enable CPU FDI TX PLL, always on for Ironlake */
4829 reg
= FDI_TX_CTL(pipe
);
4830 temp
= I915_READ(reg
);
4831 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
4832 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
4839 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
4841 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4842 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4843 int pipe
= intel_crtc
->pipe
;
4847 /* Switch from PCDclk to Rawclk */
4848 reg
= FDI_RX_CTL(pipe
);
4849 temp
= I915_READ(reg
);
4850 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
4852 /* Disable CPU FDI TX PLL */
4853 reg
= FDI_TX_CTL(pipe
);
4854 temp
= I915_READ(reg
);
4855 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
4860 reg
= FDI_RX_CTL(pipe
);
4861 temp
= I915_READ(reg
);
4862 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
4864 /* Wait for the clocks to turn off. */
4869 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
4871 struct drm_device
*dev
= crtc
->dev
;
4872 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4873 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4874 int pipe
= intel_crtc
->pipe
;
4878 /* disable CPU FDI tx and PCH FDI rx */
4879 reg
= FDI_TX_CTL(pipe
);
4880 temp
= I915_READ(reg
);
4881 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
4884 reg
= FDI_RX_CTL(pipe
);
4885 temp
= I915_READ(reg
);
4886 temp
&= ~(0x7 << 16);
4887 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4888 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
4893 /* Ironlake workaround, disable clock pointer after downing FDI */
4894 if (HAS_PCH_IBX(dev_priv
))
4895 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4897 /* still set train pattern 1 */
4898 reg
= FDI_TX_CTL(pipe
);
4899 temp
= I915_READ(reg
);
4900 temp
&= ~FDI_LINK_TRAIN_NONE
;
4901 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4902 I915_WRITE(reg
, temp
);
4904 reg
= FDI_RX_CTL(pipe
);
4905 temp
= I915_READ(reg
);
4906 if (HAS_PCH_CPT(dev_priv
)) {
4907 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4908 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4910 temp
&= ~FDI_LINK_TRAIN_NONE
;
4911 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4913 /* BPC in FDI rx is consistent with that in PIPECONF */
4914 temp
&= ~(0x07 << 16);
4915 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4916 I915_WRITE(reg
, temp
);
4922 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
4924 struct drm_crtc
*crtc
;
4927 drm_for_each_crtc(crtc
, &dev_priv
->drm
) {
4928 struct drm_crtc_commit
*commit
;
4929 spin_lock(&crtc
->commit_lock
);
4930 commit
= list_first_entry_or_null(&crtc
->commit_list
,
4931 struct drm_crtc_commit
, commit_entry
);
4932 cleanup_done
= commit
?
4933 try_wait_for_completion(&commit
->cleanup_done
) : true;
4934 spin_unlock(&crtc
->commit_lock
);
4939 drm_crtc_wait_one_vblank(crtc
);
4947 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
4951 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
4953 mutex_lock(&dev_priv
->sb_lock
);
4955 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4956 temp
|= SBI_SSCCTL_DISABLE
;
4957 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4959 mutex_unlock(&dev_priv
->sb_lock
);
4962 /* Program iCLKIP clock to the desired frequency */
4963 static void lpt_program_iclkip(const struct intel_crtc_state
*crtc_state
)
4965 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4966 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4967 int clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
4968 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
4971 lpt_disable_iclkip(dev_priv
);
4973 /* The iCLK virtual clock root frequency is in MHz,
4974 * but the adjusted_mode->crtc_clock in in KHz. To get the
4975 * divisors, it is necessary to divide one by another, so we
4976 * convert the virtual clock precision to KHz here for higher
4979 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
4980 u32 iclk_virtual_root_freq
= 172800 * 1000;
4981 u32 iclk_pi_range
= 64;
4982 u32 desired_divisor
;
4984 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4986 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
4987 phaseinc
= desired_divisor
% iclk_pi_range
;
4990 * Near 20MHz is a corner case which is
4991 * out of range for the 7-bit divisor
4997 /* This should not happen with any sane values */
4998 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4999 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
5000 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
5001 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
5003 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5010 mutex_lock(&dev_priv
->sb_lock
);
5012 /* Program SSCDIVINTPHASE6 */
5013 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
5014 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
5015 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
5016 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
5017 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
5018 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
5019 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
5020 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
5022 /* Program SSCAUXDIV */
5023 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
5024 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5025 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
5026 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
5028 /* Enable modulator and associated divider */
5029 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
5030 temp
&= ~SBI_SSCCTL_DISABLE
;
5031 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
5033 mutex_unlock(&dev_priv
->sb_lock
);
5035 /* Wait for initialization time */
5038 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
5041 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
5043 u32 divsel
, phaseinc
, auxdiv
;
5044 u32 iclk_virtual_root_freq
= 172800 * 1000;
5045 u32 iclk_pi_range
= 64;
5046 u32 desired_divisor
;
5049 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
5052 mutex_lock(&dev_priv
->sb_lock
);
5054 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
5055 if (temp
& SBI_SSCCTL_DISABLE
) {
5056 mutex_unlock(&dev_priv
->sb_lock
);
5060 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
5061 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
5062 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
5063 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
5064 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
5066 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
5067 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
5068 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
5070 mutex_unlock(&dev_priv
->sb_lock
);
5072 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
5074 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
5075 desired_divisor
<< auxdiv
);
5078 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state
*crtc_state
,
5079 enum pipe pch_transcoder
)
5081 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5082 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5083 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
5085 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
5086 I915_READ(HTOTAL(cpu_transcoder
)));
5087 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
5088 I915_READ(HBLANK(cpu_transcoder
)));
5089 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
5090 I915_READ(HSYNC(cpu_transcoder
)));
5092 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
5093 I915_READ(VTOTAL(cpu_transcoder
)));
5094 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
5095 I915_READ(VBLANK(cpu_transcoder
)));
5096 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
5097 I915_READ(VSYNC(cpu_transcoder
)));
5098 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
5099 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
5102 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private
*dev_priv
, bool enable
)
5106 temp
= I915_READ(SOUTH_CHICKEN1
);
5107 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
5110 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5111 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5113 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
5115 temp
|= FDI_BC_BIFURCATION_SELECT
;
5117 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
5118 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5119 POSTING_READ(SOUTH_CHICKEN1
);
5122 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state
*crtc_state
)
5124 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5125 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5127 switch (crtc
->pipe
) {
5131 if (crtc_state
->fdi_lanes
> 2)
5132 cpt_set_fdi_bc_bifurcation(dev_priv
, false);
5134 cpt_set_fdi_bc_bifurcation(dev_priv
, true);
5138 cpt_set_fdi_bc_bifurcation(dev_priv
, true);
5147 * Finds the encoder associated with the given CRTC. This can only be
5148 * used when we know that the CRTC isn't feeding multiple encoders!
5150 static struct intel_encoder
*
5151 intel_get_crtc_new_encoder(const struct intel_atomic_state
*state
,
5152 const struct intel_crtc_state
*crtc_state
)
5154 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5155 const struct drm_connector_state
*connector_state
;
5156 const struct drm_connector
*connector
;
5157 struct intel_encoder
*encoder
= NULL
;
5158 int num_encoders
= 0;
5161 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
5162 if (connector_state
->crtc
!= &crtc
->base
)
5165 encoder
= to_intel_encoder(connector_state
->best_encoder
);
5169 WARN(num_encoders
!= 1, "%d encoders for pipe %c\n",
5170 num_encoders
, pipe_name(crtc
->pipe
));
5176 * Enable PCH resources required for PCH ports:
5178 * - FDI training & RX/TX
5179 * - update transcoder timings
5180 * - DP transcoding bits
5183 static void ironlake_pch_enable(const struct intel_atomic_state
*state
,
5184 const struct intel_crtc_state
*crtc_state
)
5186 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5187 struct drm_device
*dev
= crtc
->base
.dev
;
5188 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5189 int pipe
= crtc
->pipe
;
5192 assert_pch_transcoder_disabled(dev_priv
, pipe
);
5194 if (IS_IVYBRIDGE(dev_priv
))
5195 ivybridge_update_fdi_bc_bifurcation(crtc_state
);
5197 /* Write the TU size bits before fdi link training, so that error
5198 * detection works. */
5199 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
5200 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
5202 /* For PCH output, training FDI link */
5203 dev_priv
->display
.fdi_link_train(crtc
, crtc_state
);
5205 /* We need to program the right clock selection before writing the pixel
5206 * mutliplier into the DPLL. */
5207 if (HAS_PCH_CPT(dev_priv
)) {
5210 temp
= I915_READ(PCH_DPLL_SEL
);
5211 temp
|= TRANS_DPLL_ENABLE(pipe
);
5212 sel
= TRANS_DPLLB_SEL(pipe
);
5213 if (crtc_state
->shared_dpll
==
5214 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
5218 I915_WRITE(PCH_DPLL_SEL
, temp
);
5221 /* XXX: pch pll's can be enabled any time before we enable the PCH
5222 * transcoder, and we actually should do this to not upset any PCH
5223 * transcoder that already use the clock when we share it.
5225 * Note that enable_shared_dpll tries to do the right thing, but
5226 * get_shared_dpll unconditionally resets the pll - we need that to have
5227 * the right LVDS enable sequence. */
5228 intel_enable_shared_dpll(crtc_state
);
5230 /* set transcoder timing, panel must allow it */
5231 assert_panel_unlocked(dev_priv
, pipe
);
5232 ironlake_pch_transcoder_set_timings(crtc_state
, pipe
);
5234 intel_fdi_normal_train(crtc
);
5236 /* For PCH DP, enable TRANS_DP_CTL */
5237 if (HAS_PCH_CPT(dev_priv
) &&
5238 intel_crtc_has_dp_encoder(crtc_state
)) {
5239 const struct drm_display_mode
*adjusted_mode
=
5240 &crtc_state
->base
.adjusted_mode
;
5241 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
5242 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
5245 temp
= I915_READ(reg
);
5246 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
5247 TRANS_DP_SYNC_MASK
|
5249 temp
|= TRANS_DP_OUTPUT_ENABLE
;
5250 temp
|= bpc
<< 9; /* same format but at 11:9 */
5252 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
5253 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
5254 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
5255 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
5257 port
= intel_get_crtc_new_encoder(state
, crtc_state
)->port
;
5258 WARN_ON(port
< PORT_B
|| port
> PORT_D
);
5259 temp
|= TRANS_DP_PORT_SEL(port
);
5261 I915_WRITE(reg
, temp
);
5264 ironlake_enable_pch_transcoder(crtc_state
);
5267 static void lpt_pch_enable(const struct intel_atomic_state
*state
,
5268 const struct intel_crtc_state
*crtc_state
)
5270 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5271 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5272 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
5274 assert_pch_transcoder_disabled(dev_priv
, PIPE_A
);
5276 lpt_program_iclkip(crtc_state
);
5278 /* Set transcoder timing. */
5279 ironlake_pch_transcoder_set_timings(crtc_state
, PIPE_A
);
5281 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
5284 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
5286 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5287 i915_reg_t dslreg
= PIPEDSL(pipe
);
5290 temp
= I915_READ(dslreg
);
5292 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
5293 if (wait_for(I915_READ(dslreg
) != temp
, 5))
5294 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
5299 * The hardware phase 0.0 refers to the center of the pixel.
5300 * We want to start from the top/left edge which is phase
5301 * -0.5. That matches how the hardware calculates the scaling
5302 * factors (from top-left of the first pixel to bottom-right
5303 * of the last pixel, as opposed to the pixel centers).
5305 * For 4:2:0 subsampled chroma planes we obviously have to
5306 * adjust that so that the chroma sample position lands in
5309 * Note that for packed YCbCr 4:2:2 formats there is no way to
5310 * control chroma siting. The hardware simply replicates the
5311 * chroma samples for both of the luma samples, and thus we don't
5312 * actually get the expected MPEG2 chroma siting convention :(
5313 * The same behaviour is observed on pre-SKL platforms as well.
5315 * Theory behind the formula (note that we ignore sub-pixel
5316 * source coordinates):
5317 * s = source sample position
5318 * d = destination sample position
5323 * | | 1.5 (initial phase)
5331 * | -0.375 (initial phase)
5338 u16
skl_scaler_calc_phase(int sub
, int scale
, bool chroma_cosited
)
5340 int phase
= -0x8000;
5344 phase
+= (sub
- 1) * 0x8000 / sub
;
5346 phase
+= scale
/ (2 * sub
);
5349 * Hardware initial phase limited to [-0.5:1.5].
5350 * Since the max hardware scale factor is 3.0, we
5351 * should never actually excdeed 1.0 here.
5353 WARN_ON(phase
< -0x8000 || phase
> 0x18000);
5356 phase
= 0x10000 + phase
;
5358 trip
= PS_PHASE_TRIP
;
5360 return ((phase
>> 2) & PS_PHASE_MASK
) | trip
;
5363 #define SKL_MIN_SRC_W 8
5364 #define SKL_MAX_SRC_W 4096
5365 #define SKL_MIN_SRC_H 8
5366 #define SKL_MAX_SRC_H 4096
5367 #define SKL_MIN_DST_W 8
5368 #define SKL_MAX_DST_W 4096
5369 #define SKL_MIN_DST_H 8
5370 #define SKL_MAX_DST_H 4096
5371 #define ICL_MAX_SRC_W 5120
5372 #define ICL_MAX_SRC_H 4096
5373 #define ICL_MAX_DST_W 5120
5374 #define ICL_MAX_DST_H 4096
5375 #define SKL_MIN_YUV_420_SRC_W 16
5376 #define SKL_MIN_YUV_420_SRC_H 16
5379 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
5380 unsigned int scaler_user
, int *scaler_id
,
5381 int src_w
, int src_h
, int dst_w
, int dst_h
,
5382 const struct drm_format_info
*format
, bool need_scaler
)
5384 struct intel_crtc_scaler_state
*scaler_state
=
5385 &crtc_state
->scaler_state
;
5386 struct intel_crtc
*intel_crtc
=
5387 to_intel_crtc(crtc_state
->base
.crtc
);
5388 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
5389 const struct drm_display_mode
*adjusted_mode
=
5390 &crtc_state
->base
.adjusted_mode
;
5393 * Src coordinates are already rotated by 270 degrees for
5394 * the 90/270 degree plane rotation cases (to match the
5395 * GTT mapping), hence no need to account for rotation here.
5397 if (src_w
!= dst_w
|| src_h
!= dst_h
)
5401 * Scaling/fitting not supported in IF-ID mode in GEN9+
5402 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5403 * Once NV12 is enabled, handle it here while allocating scaler
5406 if (INTEL_GEN(dev_priv
) >= 9 && crtc_state
->base
.enable
&&
5407 need_scaler
&& adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5408 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5413 * if plane is being disabled or scaler is no more required or force detach
5414 * - free scaler binded to this plane/crtc
5415 * - in order to do this, update crtc->scaler_usage
5417 * Here scaler state in crtc_state is set free so that
5418 * scaler can be assigned to other user. Actual register
5419 * update to free the scaler is done in plane/panel-fit programming.
5420 * For this purpose crtc/plane_state->scaler_id isn't reset here.
5422 if (force_detach
|| !need_scaler
) {
5423 if (*scaler_id
>= 0) {
5424 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
5425 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
5427 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5428 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5429 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
5430 scaler_state
->scaler_users
);
5436 if (format
&& is_planar_yuv_format(format
->format
) &&
5437 (src_h
< SKL_MIN_YUV_420_SRC_H
|| src_w
< SKL_MIN_YUV_420_SRC_W
)) {
5438 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5443 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
5444 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
5445 (INTEL_GEN(dev_priv
) >= 11 &&
5446 (src_w
> ICL_MAX_SRC_W
|| src_h
> ICL_MAX_SRC_H
||
5447 dst_w
> ICL_MAX_DST_W
|| dst_h
> ICL_MAX_DST_H
)) ||
5448 (INTEL_GEN(dev_priv
) < 11 &&
5449 (src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
5450 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
))) {
5451 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5452 "size is out of scaler range\n",
5453 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
5457 /* mark this plane as a scaler user in crtc_state */
5458 scaler_state
->scaler_users
|= (1 << scaler_user
);
5459 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5460 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5461 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
5462 scaler_state
->scaler_users
);
5468 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5470 * @state: crtc's scaler state
5473 * 0 - scaler_usage updated successfully
5474 * error - requested scaling cannot be supported or other error condition
5476 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
5478 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
5479 bool need_scaler
= false;
5481 if (state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
5484 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
5485 &state
->scaler_state
.scaler_id
,
5486 state
->pipe_src_w
, state
->pipe_src_h
,
5487 adjusted_mode
->crtc_hdisplay
,
5488 adjusted_mode
->crtc_vdisplay
, NULL
, need_scaler
);
5492 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5493 * @crtc_state: crtc's scaler state
5494 * @plane_state: atomic plane state to update
5497 * 0 - scaler_usage updated successfully
5498 * error - requested scaling cannot be supported or other error condition
5500 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
5501 struct intel_plane_state
*plane_state
)
5503 struct intel_plane
*intel_plane
=
5504 to_intel_plane(plane_state
->base
.plane
);
5505 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
5506 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
5508 bool force_detach
= !fb
|| !plane_state
->base
.visible
;
5509 bool need_scaler
= false;
5511 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5512 if (!icl_is_hdr_plane(dev_priv
, intel_plane
->id
) &&
5513 fb
&& is_planar_yuv_format(fb
->format
->format
))
5516 ret
= skl_update_scaler(crtc_state
, force_detach
,
5517 drm_plane_index(&intel_plane
->base
),
5518 &plane_state
->scaler_id
,
5519 drm_rect_width(&plane_state
->base
.src
) >> 16,
5520 drm_rect_height(&plane_state
->base
.src
) >> 16,
5521 drm_rect_width(&plane_state
->base
.dst
),
5522 drm_rect_height(&plane_state
->base
.dst
),
5523 fb
? fb
->format
: NULL
, need_scaler
);
5525 if (ret
|| plane_state
->scaler_id
< 0)
5528 /* check colorkey */
5529 if (plane_state
->ckey
.flags
) {
5530 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5531 intel_plane
->base
.base
.id
,
5532 intel_plane
->base
.name
);
5536 /* Check src format */
5537 switch (fb
->format
->format
) {
5538 case DRM_FORMAT_RGB565
:
5539 case DRM_FORMAT_XBGR8888
:
5540 case DRM_FORMAT_XRGB8888
:
5541 case DRM_FORMAT_ABGR8888
:
5542 case DRM_FORMAT_ARGB8888
:
5543 case DRM_FORMAT_XRGB2101010
:
5544 case DRM_FORMAT_XBGR2101010
:
5545 case DRM_FORMAT_XBGR16161616F
:
5546 case DRM_FORMAT_ABGR16161616F
:
5547 case DRM_FORMAT_XRGB16161616F
:
5548 case DRM_FORMAT_ARGB16161616F
:
5549 case DRM_FORMAT_YUYV
:
5550 case DRM_FORMAT_YVYU
:
5551 case DRM_FORMAT_UYVY
:
5552 case DRM_FORMAT_VYUY
:
5553 case DRM_FORMAT_NV12
:
5554 case DRM_FORMAT_P010
:
5555 case DRM_FORMAT_P012
:
5556 case DRM_FORMAT_P016
:
5557 case DRM_FORMAT_Y210
:
5558 case DRM_FORMAT_Y212
:
5559 case DRM_FORMAT_Y216
:
5560 case DRM_FORMAT_XVYU2101010
:
5561 case DRM_FORMAT_XVYU12_16161616
:
5562 case DRM_FORMAT_XVYU16161616
:
5565 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5566 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
5567 fb
->base
.id
, fb
->format
->format
);
5574 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
5578 for (i
= 0; i
< crtc
->num_scalers
; i
++)
5579 skl_detach_scaler(crtc
, i
);
5582 static void skylake_pfit_enable(const struct intel_crtc_state
*crtc_state
)
5584 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5585 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5586 enum pipe pipe
= crtc
->pipe
;
5587 const struct intel_crtc_scaler_state
*scaler_state
=
5588 &crtc_state
->scaler_state
;
5590 if (crtc_state
->pch_pfit
.enabled
) {
5591 u16 uv_rgb_hphase
, uv_rgb_vphase
;
5592 int pfit_w
, pfit_h
, hscale
, vscale
;
5595 if (WARN_ON(crtc_state
->scaler_state
.scaler_id
< 0))
5598 pfit_w
= (crtc_state
->pch_pfit
.size
>> 16) & 0xFFFF;
5599 pfit_h
= crtc_state
->pch_pfit
.size
& 0xFFFF;
5601 hscale
= (crtc_state
->pipe_src_w
<< 16) / pfit_w
;
5602 vscale
= (crtc_state
->pipe_src_h
<< 16) / pfit_h
;
5604 uv_rgb_hphase
= skl_scaler_calc_phase(1, hscale
, false);
5605 uv_rgb_vphase
= skl_scaler_calc_phase(1, vscale
, false);
5607 id
= scaler_state
->scaler_id
;
5608 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
5609 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
5610 I915_WRITE_FW(SKL_PS_VPHASE(pipe
, id
),
5611 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase
));
5612 I915_WRITE_FW(SKL_PS_HPHASE(pipe
, id
),
5613 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase
));
5614 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc_state
->pch_pfit
.pos
);
5615 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc_state
->pch_pfit
.size
);
5619 static void ironlake_pfit_enable(const struct intel_crtc_state
*crtc_state
)
5621 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5622 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5623 int pipe
= crtc
->pipe
;
5625 if (crtc_state
->pch_pfit
.enabled
) {
5626 /* Force use of hard-coded filter coefficients
5627 * as some pre-programmed values are broken,
5630 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
5631 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
5632 PF_PIPE_SEL_IVB(pipe
));
5634 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
5635 I915_WRITE(PF_WIN_POS(pipe
), crtc_state
->pch_pfit
.pos
);
5636 I915_WRITE(PF_WIN_SZ(pipe
), crtc_state
->pch_pfit
.size
);
5640 void hsw_enable_ips(const struct intel_crtc_state
*crtc_state
)
5642 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5643 struct drm_device
*dev
= crtc
->base
.dev
;
5644 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5646 if (!crtc_state
->ips_enabled
)
5650 * We can only enable IPS after we enable a plane and wait for a vblank
5651 * This function is called from post_plane_update, which is run after
5654 WARN_ON(!(crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)));
5656 if (IS_BROADWELL(dev_priv
)) {
5657 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
,
5658 IPS_ENABLE
| IPS_PCODE_CONTROL
));
5659 /* Quoting Art Runyan: "its not safe to expect any particular
5660 * value in IPS_CTL bit 31 after enabling IPS through the
5661 * mailbox." Moreover, the mailbox may return a bogus state,
5662 * so we need to just enable it and continue on.
5665 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
5666 /* The bit only becomes 1 in the next vblank, so this wait here
5667 * is essentially intel_wait_for_vblank. If we don't have this
5668 * and don't wait for vblanks until the end of crtc_enable, then
5669 * the HW state readout code will complain that the expected
5670 * IPS_CTL value is not the one we read. */
5671 if (intel_wait_for_register(&dev_priv
->uncore
,
5672 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
5674 DRM_ERROR("Timed out waiting for IPS enable\n");
5678 void hsw_disable_ips(const struct intel_crtc_state
*crtc_state
)
5680 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5681 struct drm_device
*dev
= crtc
->base
.dev
;
5682 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5684 if (!crtc_state
->ips_enabled
)
5687 if (IS_BROADWELL(dev_priv
)) {
5688 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
5690 * Wait for PCODE to finish disabling IPS. The BSpec specified
5691 * 42ms timeout value leads to occasional timeouts so use 100ms
5694 if (intel_wait_for_register(&dev_priv
->uncore
,
5695 IPS_CTL
, IPS_ENABLE
, 0,
5697 DRM_ERROR("Timed out waiting for IPS disable\n");
5699 I915_WRITE(IPS_CTL
, 0);
5700 POSTING_READ(IPS_CTL
);
5703 /* We need to wait for a vblank before we can disable the plane. */
5704 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5707 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
5709 if (intel_crtc
->overlay
) {
5710 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5712 mutex_lock(&dev
->struct_mutex
);
5713 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
5714 mutex_unlock(&dev
->struct_mutex
);
5717 /* Let userspace switch the overlay on again. In most cases userspace
5718 * has to recompute where to put it anyway.
5723 * intel_post_enable_primary - Perform operations after enabling primary plane
5724 * @crtc: the CRTC whose primary plane was just enabled
5725 * @new_crtc_state: the enabling state
5727 * Performs potentially sleeping operations that must be done after the primary
5728 * plane is enabled, such as updating FBC and IPS. Note that this may be
5729 * called due to an explicit primary plane update, or due to an implicit
5730 * re-enable that is caused when a sprite plane is updated to no longer
5731 * completely hide the primary plane.
5734 intel_post_enable_primary(struct drm_crtc
*crtc
,
5735 const struct intel_crtc_state
*new_crtc_state
)
5737 struct drm_device
*dev
= crtc
->dev
;
5738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5740 int pipe
= intel_crtc
->pipe
;
5743 * Gen2 reports pipe underruns whenever all planes are disabled.
5744 * So don't enable underrun reporting before at least some planes
5746 * FIXME: Need to fix the logic to work when we turn off all planes
5747 * but leave the pipe running.
5749 if (IS_GEN(dev_priv
, 2))
5750 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5752 /* Underruns don't always raise interrupts, so check manually. */
5753 intel_check_cpu_fifo_underruns(dev_priv
);
5754 intel_check_pch_fifo_underruns(dev_priv
);
5757 /* FIXME get rid of this and use pre_plane_update */
5759 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
5761 struct drm_device
*dev
= crtc
->dev
;
5762 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5763 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5764 int pipe
= intel_crtc
->pipe
;
5767 * Gen2 reports pipe underruns whenever all planes are disabled.
5768 * So disable underrun reporting before all the planes get disabled.
5770 if (IS_GEN(dev_priv
, 2))
5771 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5773 hsw_disable_ips(to_intel_crtc_state(crtc
->state
));
5776 * Vblank time updates from the shadow to live plane control register
5777 * are blocked if the memory self-refresh mode is active at that
5778 * moment. So to make sure the plane gets truly disabled, disable
5779 * first the self-refresh mode. The self-refresh enable bit in turn
5780 * will be checked/applied by the HW only at the next frame start
5781 * event which is after the vblank start event, so we need to have a
5782 * wait-for-vblank between disabling the plane and the pipe.
5784 if (HAS_GMCH(dev_priv
) &&
5785 intel_set_memory_cxsr(dev_priv
, false))
5786 intel_wait_for_vblank(dev_priv
, pipe
);
5789 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state
*old_crtc_state
,
5790 const struct intel_crtc_state
*new_crtc_state
)
5792 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
5793 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5795 if (!old_crtc_state
->ips_enabled
)
5798 if (needs_modeset(&new_crtc_state
->base
))
5802 * Workaround : Do not read or write the pipe palette/gamma data while
5803 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5805 * Disable IPS before we program the LUT.
5807 if (IS_HASWELL(dev_priv
) &&
5808 (new_crtc_state
->base
.color_mgmt_changed
||
5809 new_crtc_state
->update_pipe
) &&
5810 new_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)
5813 return !new_crtc_state
->ips_enabled
;
5816 static bool hsw_post_update_enable_ips(const struct intel_crtc_state
*old_crtc_state
,
5817 const struct intel_crtc_state
*new_crtc_state
)
5819 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
5820 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5822 if (!new_crtc_state
->ips_enabled
)
5825 if (needs_modeset(&new_crtc_state
->base
))
5829 * Workaround : Do not read or write the pipe palette/gamma data while
5830 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5832 * Re-enable IPS after the LUT has been programmed.
5834 if (IS_HASWELL(dev_priv
) &&
5835 (new_crtc_state
->base
.color_mgmt_changed
||
5836 new_crtc_state
->update_pipe
) &&
5837 new_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)
5841 * We can't read out IPS on broadwell, assume the worst and
5842 * forcibly enable IPS on the first fastset.
5844 if (new_crtc_state
->update_pipe
&&
5845 old_crtc_state
->base
.adjusted_mode
.private_flags
& I915_MODE_FLAG_INHERITED
)
5848 return !old_crtc_state
->ips_enabled
;
5851 static bool needs_nv12_wa(struct drm_i915_private
*dev_priv
,
5852 const struct intel_crtc_state
*crtc_state
)
5854 if (!crtc_state
->nv12_planes
)
5857 /* WA Display #0827: Gen9:all */
5858 if (IS_GEN(dev_priv
, 9) && !IS_GEMINILAKE(dev_priv
))
5864 static bool needs_scalerclk_wa(struct drm_i915_private
*dev_priv
,
5865 const struct intel_crtc_state
*crtc_state
)
5867 /* Wa_2006604312:icl */
5868 if (crtc_state
->scaler_state
.scaler_users
> 0 && IS_ICELAKE(dev_priv
))
5874 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
5876 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5877 struct drm_device
*dev
= crtc
->base
.dev
;
5878 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5879 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5880 struct intel_crtc_state
*pipe_config
=
5881 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state
),
5883 struct drm_plane
*primary
= crtc
->base
.primary
;
5884 struct drm_plane_state
*old_primary_state
=
5885 drm_atomic_get_old_plane_state(old_state
, primary
);
5887 intel_frontbuffer_flip(to_i915(crtc
->base
.dev
), pipe_config
->fb_bits
);
5889 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
5890 intel_update_watermarks(crtc
);
5892 if (hsw_post_update_enable_ips(old_crtc_state
, pipe_config
))
5893 hsw_enable_ips(pipe_config
);
5895 if (old_primary_state
) {
5896 struct drm_plane_state
*new_primary_state
=
5897 drm_atomic_get_new_plane_state(old_state
, primary
);
5899 intel_fbc_post_update(crtc
);
5901 if (new_primary_state
->visible
&&
5902 (needs_modeset(&pipe_config
->base
) ||
5903 !old_primary_state
->visible
))
5904 intel_post_enable_primary(&crtc
->base
, pipe_config
);
5907 if (needs_nv12_wa(dev_priv
, old_crtc_state
) &&
5908 !needs_nv12_wa(dev_priv
, pipe_config
))
5909 skl_wa_827(dev_priv
, crtc
->pipe
, false);
5911 if (needs_scalerclk_wa(dev_priv
, old_crtc_state
) &&
5912 !needs_scalerclk_wa(dev_priv
, pipe_config
))
5913 icl_wa_scalerclkgating(dev_priv
, crtc
->pipe
, false);
5916 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
,
5917 struct intel_crtc_state
*pipe_config
)
5919 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5920 struct drm_device
*dev
= crtc
->base
.dev
;
5921 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5922 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5923 struct drm_plane
*primary
= crtc
->base
.primary
;
5924 struct drm_plane_state
*old_primary_state
=
5925 drm_atomic_get_old_plane_state(old_state
, primary
);
5926 bool modeset
= needs_modeset(&pipe_config
->base
);
5927 struct intel_atomic_state
*old_intel_state
=
5928 to_intel_atomic_state(old_state
);
5930 if (hsw_pre_update_disable_ips(old_crtc_state
, pipe_config
))
5931 hsw_disable_ips(old_crtc_state
);
5933 if (old_primary_state
) {
5934 struct intel_plane_state
*new_primary_state
=
5935 intel_atomic_get_new_plane_state(old_intel_state
,
5936 to_intel_plane(primary
));
5938 intel_fbc_pre_update(crtc
, pipe_config
, new_primary_state
);
5940 * Gen2 reports pipe underruns whenever all planes are disabled.
5941 * So disable underrun reporting before all the planes get disabled.
5943 if (IS_GEN(dev_priv
, 2) && old_primary_state
->visible
&&
5944 (modeset
|| !new_primary_state
->base
.visible
))
5945 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
5948 /* Display WA 827 */
5949 if (!needs_nv12_wa(dev_priv
, old_crtc_state
) &&
5950 needs_nv12_wa(dev_priv
, pipe_config
))
5951 skl_wa_827(dev_priv
, crtc
->pipe
, true);
5953 /* Wa_2006604312:icl */
5954 if (!needs_scalerclk_wa(dev_priv
, old_crtc_state
) &&
5955 needs_scalerclk_wa(dev_priv
, pipe_config
))
5956 icl_wa_scalerclkgating(dev_priv
, crtc
->pipe
, true);
5959 * Vblank time updates from the shadow to live plane control register
5960 * are blocked if the memory self-refresh mode is active at that
5961 * moment. So to make sure the plane gets truly disabled, disable
5962 * first the self-refresh mode. The self-refresh enable bit in turn
5963 * will be checked/applied by the HW only at the next frame start
5964 * event which is after the vblank start event, so we need to have a
5965 * wait-for-vblank between disabling the plane and the pipe.
5967 if (HAS_GMCH(dev_priv
) && old_crtc_state
->base
.active
&&
5968 pipe_config
->disable_cxsr
&& intel_set_memory_cxsr(dev_priv
, false))
5969 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5972 * IVB workaround: must disable low power watermarks for at least
5973 * one frame before enabling scaling. LP watermarks can be re-enabled
5974 * when scaling is disabled.
5976 * WaCxSRDisabledForSpriteScaling:ivb
5978 if (pipe_config
->disable_lp_wm
&& ilk_disable_lp_wm(dev
) &&
5979 old_crtc_state
->base
.active
)
5980 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5983 * If we're doing a modeset, we're done. No need to do any pre-vblank
5984 * watermark programming here.
5986 if (needs_modeset(&pipe_config
->base
))
5990 * For platforms that support atomic watermarks, program the
5991 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5992 * will be the intermediate values that are safe for both pre- and
5993 * post- vblank; when vblank happens, the 'active' values will be set
5994 * to the final 'target' values and we'll do this again to get the
5995 * optimal watermarks. For gen9+ platforms, the values we program here
5996 * will be the final target values which will get automatically latched
5997 * at vblank time; no further programming will be necessary.
5999 * If a platform hasn't been transitioned to atomic watermarks yet,
6000 * we'll continue to update watermarks the old way, if flags tell
6003 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6004 dev_priv
->display
.initial_watermarks(old_intel_state
,
6006 else if (pipe_config
->update_wm_pre
)
6007 intel_update_watermarks(crtc
);
6010 static void intel_crtc_disable_planes(struct intel_atomic_state
*state
,
6011 struct intel_crtc
*crtc
)
6013 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6014 const struct intel_crtc_state
*new_crtc_state
=
6015 intel_atomic_get_new_crtc_state(state
, crtc
);
6016 unsigned int update_mask
= new_crtc_state
->update_planes
;
6017 const struct intel_plane_state
*old_plane_state
;
6018 struct intel_plane
*plane
;
6019 unsigned fb_bits
= 0;
6022 intel_crtc_dpms_overlay_disable(crtc
);
6024 for_each_old_intel_plane_in_state(state
, plane
, old_plane_state
, i
) {
6025 if (crtc
->pipe
!= plane
->pipe
||
6026 !(update_mask
& BIT(plane
->id
)))
6029 intel_disable_plane(plane
, new_crtc_state
);
6031 if (old_plane_state
->base
.visible
)
6032 fb_bits
|= plane
->frontbuffer_bit
;
6035 intel_frontbuffer_flip(dev_priv
, fb_bits
);
6038 static void intel_encoders_pre_pll_enable(struct drm_crtc
*crtc
,
6039 struct intel_crtc_state
*crtc_state
,
6040 struct drm_atomic_state
*old_state
)
6042 struct drm_connector_state
*conn_state
;
6043 struct drm_connector
*conn
;
6046 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
6047 struct intel_encoder
*encoder
=
6048 to_intel_encoder(conn_state
->best_encoder
);
6050 if (conn_state
->crtc
!= crtc
)
6053 if (encoder
->pre_pll_enable
)
6054 encoder
->pre_pll_enable(encoder
, crtc_state
, conn_state
);
6058 static void intel_encoders_pre_enable(struct drm_crtc
*crtc
,
6059 struct intel_crtc_state
*crtc_state
,
6060 struct drm_atomic_state
*old_state
)
6062 struct drm_connector_state
*conn_state
;
6063 struct drm_connector
*conn
;
6066 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
6067 struct intel_encoder
*encoder
=
6068 to_intel_encoder(conn_state
->best_encoder
);
6070 if (conn_state
->crtc
!= crtc
)
6073 if (encoder
->pre_enable
)
6074 encoder
->pre_enable(encoder
, crtc_state
, conn_state
);
6078 static void intel_encoders_enable(struct drm_crtc
*crtc
,
6079 struct intel_crtc_state
*crtc_state
,
6080 struct drm_atomic_state
*old_state
)
6082 struct drm_connector_state
*conn_state
;
6083 struct drm_connector
*conn
;
6086 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
6087 struct intel_encoder
*encoder
=
6088 to_intel_encoder(conn_state
->best_encoder
);
6090 if (conn_state
->crtc
!= crtc
)
6093 if (encoder
->enable
)
6094 encoder
->enable(encoder
, crtc_state
, conn_state
);
6095 intel_opregion_notify_encoder(encoder
, true);
6099 static void intel_encoders_disable(struct drm_crtc
*crtc
,
6100 struct intel_crtc_state
*old_crtc_state
,
6101 struct drm_atomic_state
*old_state
)
6103 struct drm_connector_state
*old_conn_state
;
6104 struct drm_connector
*conn
;
6107 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
6108 struct intel_encoder
*encoder
=
6109 to_intel_encoder(old_conn_state
->best_encoder
);
6111 if (old_conn_state
->crtc
!= crtc
)
6114 intel_opregion_notify_encoder(encoder
, false);
6115 if (encoder
->disable
)
6116 encoder
->disable(encoder
, old_crtc_state
, old_conn_state
);
6120 static void intel_encoders_post_disable(struct drm_crtc
*crtc
,
6121 struct intel_crtc_state
*old_crtc_state
,
6122 struct drm_atomic_state
*old_state
)
6124 struct drm_connector_state
*old_conn_state
;
6125 struct drm_connector
*conn
;
6128 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
6129 struct intel_encoder
*encoder
=
6130 to_intel_encoder(old_conn_state
->best_encoder
);
6132 if (old_conn_state
->crtc
!= crtc
)
6135 if (encoder
->post_disable
)
6136 encoder
->post_disable(encoder
, old_crtc_state
, old_conn_state
);
6140 static void intel_encoders_post_pll_disable(struct drm_crtc
*crtc
,
6141 struct intel_crtc_state
*old_crtc_state
,
6142 struct drm_atomic_state
*old_state
)
6144 struct drm_connector_state
*old_conn_state
;
6145 struct drm_connector
*conn
;
6148 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
6149 struct intel_encoder
*encoder
=
6150 to_intel_encoder(old_conn_state
->best_encoder
);
6152 if (old_conn_state
->crtc
!= crtc
)
6155 if (encoder
->post_pll_disable
)
6156 encoder
->post_pll_disable(encoder
, old_crtc_state
, old_conn_state
);
6160 static void intel_encoders_update_pipe(struct drm_crtc
*crtc
,
6161 struct intel_crtc_state
*crtc_state
,
6162 struct drm_atomic_state
*old_state
)
6164 struct drm_connector_state
*conn_state
;
6165 struct drm_connector
*conn
;
6168 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
6169 struct intel_encoder
*encoder
=
6170 to_intel_encoder(conn_state
->best_encoder
);
6172 if (conn_state
->crtc
!= crtc
)
6175 if (encoder
->update_pipe
)
6176 encoder
->update_pipe(encoder
, crtc_state
, conn_state
);
6180 static void intel_disable_primary_plane(const struct intel_crtc_state
*crtc_state
)
6182 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6183 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
6185 plane
->disable_plane(plane
, crtc_state
);
6188 static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config
,
6189 struct drm_atomic_state
*old_state
)
6191 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6192 struct drm_device
*dev
= crtc
->dev
;
6193 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6195 int pipe
= intel_crtc
->pipe
;
6196 struct intel_atomic_state
*old_intel_state
=
6197 to_intel_atomic_state(old_state
);
6199 if (WARN_ON(intel_crtc
->active
))
6203 * Sometimes spurious CPU pipe underruns happen during FDI
6204 * training, at least with VGA+HDMI cloning. Suppress them.
6206 * On ILK we get an occasional spurious CPU pipe underruns
6207 * between eDP port A enable and vdd enable. Also PCH port
6208 * enable seems to result in the occasional CPU pipe underrun.
6210 * Spurious PCH underruns also occur during PCH enabling.
6212 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6213 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
6215 if (pipe_config
->has_pch_encoder
)
6216 intel_prepare_shared_dpll(pipe_config
);
6218 if (intel_crtc_has_dp_encoder(pipe_config
))
6219 intel_dp_set_m_n(pipe_config
, M1_N1
);
6221 intel_set_pipe_timings(pipe_config
);
6222 intel_set_pipe_src_size(pipe_config
);
6224 if (pipe_config
->has_pch_encoder
) {
6225 intel_cpu_transcoder_set_m_n(pipe_config
,
6226 &pipe_config
->fdi_m_n
, NULL
);
6229 ironlake_set_pipeconf(pipe_config
);
6231 intel_crtc
->active
= true;
6233 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6235 if (pipe_config
->has_pch_encoder
) {
6236 /* Note: FDI PLL enabling _must_ be done before we enable the
6237 * cpu pipes, hence this is separate from all the other fdi/pch
6239 ironlake_fdi_pll_enable(pipe_config
);
6241 assert_fdi_tx_disabled(dev_priv
, pipe
);
6242 assert_fdi_rx_disabled(dev_priv
, pipe
);
6245 ironlake_pfit_enable(pipe_config
);
6248 * On ILK+ LUT must be loaded before the pipe is running but with
6251 intel_color_load_luts(pipe_config
);
6252 intel_color_commit(pipe_config
);
6253 /* update DSPCNTR to configure gamma for pipe bottom color */
6254 intel_disable_primary_plane(pipe_config
);
6256 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6257 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
6258 intel_enable_pipe(pipe_config
);
6260 if (pipe_config
->has_pch_encoder
)
6261 ironlake_pch_enable(old_intel_state
, pipe_config
);
6263 assert_vblank_disabled(crtc
);
6264 intel_crtc_vblank_on(pipe_config
);
6266 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6268 if (HAS_PCH_CPT(dev_priv
))
6269 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
6272 * Must wait for vblank to avoid spurious PCH FIFO underruns.
6273 * And a second vblank wait is needed at least on ILK with
6274 * some interlaced HDMI modes. Let's do the double wait always
6275 * in case there are more corner cases we don't know about.
6277 if (pipe_config
->has_pch_encoder
) {
6278 intel_wait_for_vblank(dev_priv
, pipe
);
6279 intel_wait_for_vblank(dev_priv
, pipe
);
6281 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6282 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
6285 /* IPS only exists on ULT machines and is tied to pipe A. */
6286 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
6288 return HAS_IPS(to_i915(crtc
->base
.dev
)) && crtc
->pipe
== PIPE_A
;
6291 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private
*dev_priv
,
6292 enum pipe pipe
, bool apply
)
6294 u32 val
= I915_READ(CLKGATE_DIS_PSL(pipe
));
6295 u32 mask
= DPF_GATING_DIS
| DPF_RAM_GATING_DIS
| DPFR_GATING_DIS
;
6302 I915_WRITE(CLKGATE_DIS_PSL(pipe
), val
);
6305 static void icl_pipe_mbus_enable(struct intel_crtc
*crtc
)
6307 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6308 enum pipe pipe
= crtc
->pipe
;
6311 val
= MBUS_DBOX_A_CREDIT(2);
6312 val
|= MBUS_DBOX_BW_CREDIT(1);
6313 val
|= MBUS_DBOX_B_CREDIT(8);
6315 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe
), val
);
6318 static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config
,
6319 struct drm_atomic_state
*old_state
)
6321 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6322 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6323 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6324 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
6325 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6326 struct intel_atomic_state
*old_intel_state
=
6327 to_intel_atomic_state(old_state
);
6328 bool psl_clkgate_wa
;
6330 if (WARN_ON(intel_crtc
->active
))
6333 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
6335 if (pipe_config
->shared_dpll
)
6336 intel_enable_shared_dpll(pipe_config
);
6338 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6340 if (intel_crtc_has_dp_encoder(pipe_config
))
6341 intel_dp_set_m_n(pipe_config
, M1_N1
);
6343 if (!transcoder_is_dsi(cpu_transcoder
))
6344 intel_set_pipe_timings(pipe_config
);
6346 intel_set_pipe_src_size(pipe_config
);
6348 if (cpu_transcoder
!= TRANSCODER_EDP
&&
6349 !transcoder_is_dsi(cpu_transcoder
)) {
6350 I915_WRITE(PIPE_MULT(cpu_transcoder
),
6351 pipe_config
->pixel_multiplier
- 1);
6354 if (pipe_config
->has_pch_encoder
) {
6355 intel_cpu_transcoder_set_m_n(pipe_config
,
6356 &pipe_config
->fdi_m_n
, NULL
);
6359 if (!transcoder_is_dsi(cpu_transcoder
))
6360 haswell_set_pipeconf(pipe_config
);
6362 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
6363 bdw_set_pipemisc(pipe_config
);
6365 intel_crtc
->active
= true;
6367 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6368 psl_clkgate_wa
= (IS_GEMINILAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) &&
6369 pipe_config
->pch_pfit
.enabled
;
6371 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, true);
6373 if (INTEL_GEN(dev_priv
) >= 9)
6374 skylake_pfit_enable(pipe_config
);
6376 ironlake_pfit_enable(pipe_config
);
6379 * On ILK+ LUT must be loaded before the pipe is running but with
6382 intel_color_load_luts(pipe_config
);
6383 intel_color_commit(pipe_config
);
6384 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6385 if (INTEL_GEN(dev_priv
) < 9)
6386 intel_disable_primary_plane(pipe_config
);
6388 if (INTEL_GEN(dev_priv
) >= 11)
6389 icl_set_pipe_chicken(intel_crtc
);
6391 intel_ddi_set_pipe_settings(pipe_config
);
6392 if (!transcoder_is_dsi(cpu_transcoder
))
6393 intel_ddi_enable_transcoder_func(pipe_config
);
6395 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6396 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
6398 if (INTEL_GEN(dev_priv
) >= 11)
6399 icl_pipe_mbus_enable(intel_crtc
);
6401 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6402 if (!transcoder_is_dsi(cpu_transcoder
))
6403 intel_enable_pipe(pipe_config
);
6405 if (pipe_config
->has_pch_encoder
)
6406 lpt_pch_enable(old_intel_state
, pipe_config
);
6408 if (intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DP_MST
))
6409 intel_ddi_set_vc_payload_alloc(pipe_config
, true);
6411 assert_vblank_disabled(crtc
);
6412 intel_crtc_vblank_on(pipe_config
);
6414 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6416 if (psl_clkgate_wa
) {
6417 intel_wait_for_vblank(dev_priv
, pipe
);
6418 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, false);
6421 /* If we change the relative order between pipe/planes enabling, we need
6422 * to change the workaround. */
6423 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
6424 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
6425 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
6426 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
6430 static void ironlake_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
6432 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
6433 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6434 enum pipe pipe
= crtc
->pipe
;
6436 /* To avoid upsetting the power well on haswell only disable the pfit if
6437 * it's in use. The hw state code will make sure we get this right. */
6438 if (old_crtc_state
->pch_pfit
.enabled
) {
6439 I915_WRITE(PF_CTL(pipe
), 0);
6440 I915_WRITE(PF_WIN_POS(pipe
), 0);
6441 I915_WRITE(PF_WIN_SZ(pipe
), 0);
6445 static void ironlake_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6446 struct drm_atomic_state
*old_state
)
6448 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6449 struct drm_device
*dev
= crtc
->dev
;
6450 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6451 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6452 int pipe
= intel_crtc
->pipe
;
6455 * Sometimes spurious CPU pipe underruns happen when the
6456 * pipe is already disabled, but FDI RX/TX is still enabled.
6457 * Happens at least with VGA+HDMI cloning. Suppress them.
6459 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6460 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
6462 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6464 drm_crtc_vblank_off(crtc
);
6465 assert_vblank_disabled(crtc
);
6467 intel_disable_pipe(old_crtc_state
);
6469 ironlake_pfit_disable(old_crtc_state
);
6471 if (old_crtc_state
->has_pch_encoder
)
6472 ironlake_fdi_disable(crtc
);
6474 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6476 if (old_crtc_state
->has_pch_encoder
) {
6477 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
6479 if (HAS_PCH_CPT(dev_priv
)) {
6483 /* disable TRANS_DP_CTL */
6484 reg
= TRANS_DP_CTL(pipe
);
6485 temp
= I915_READ(reg
);
6486 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
6487 TRANS_DP_PORT_SEL_MASK
);
6488 temp
|= TRANS_DP_PORT_SEL_NONE
;
6489 I915_WRITE(reg
, temp
);
6491 /* disable DPLL_SEL */
6492 temp
= I915_READ(PCH_DPLL_SEL
);
6493 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
6494 I915_WRITE(PCH_DPLL_SEL
, temp
);
6497 ironlake_fdi_pll_disable(intel_crtc
);
6500 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6501 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
6504 static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6505 struct drm_atomic_state
*old_state
)
6507 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6508 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6509 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6510 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
6512 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6514 drm_crtc_vblank_off(crtc
);
6515 assert_vblank_disabled(crtc
);
6517 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6518 if (!transcoder_is_dsi(cpu_transcoder
))
6519 intel_disable_pipe(old_crtc_state
);
6521 if (intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DP_MST
))
6522 intel_ddi_set_vc_payload_alloc(old_crtc_state
, false);
6524 if (!transcoder_is_dsi(cpu_transcoder
))
6525 intel_ddi_disable_transcoder_func(old_crtc_state
);
6527 intel_dsc_disable(old_crtc_state
);
6529 if (INTEL_GEN(dev_priv
) >= 9)
6530 skylake_scaler_disable(intel_crtc
);
6532 ironlake_pfit_disable(old_crtc_state
);
6534 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6536 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6539 static void i9xx_pfit_enable(const struct intel_crtc_state
*crtc_state
)
6541 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6542 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6544 if (!crtc_state
->gmch_pfit
.control
)
6548 * The panel fitter should only be adjusted whilst the pipe is disabled,
6549 * according to register description and PRM.
6551 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
6552 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6554 I915_WRITE(PFIT_PGM_RATIOS
, crtc_state
->gmch_pfit
.pgm_ratios
);
6555 I915_WRITE(PFIT_CONTROL
, crtc_state
->gmch_pfit
.control
);
6557 /* Border color in case we don't scale up to the full screen. Black by
6558 * default, change to something else for debugging. */
6559 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
6562 bool intel_port_is_combophy(struct drm_i915_private
*dev_priv
, enum port port
)
6564 if (port
== PORT_NONE
)
6567 if (IS_ELKHARTLAKE(dev_priv
))
6568 return port
<= PORT_C
;
6570 if (INTEL_GEN(dev_priv
) >= 11)
6571 return port
<= PORT_B
;
6576 bool intel_port_is_tc(struct drm_i915_private
*dev_priv
, enum port port
)
6578 if (INTEL_GEN(dev_priv
) >= 11 && !IS_ELKHARTLAKE(dev_priv
))
6579 return port
>= PORT_C
&& port
<= PORT_F
;
6584 enum tc_port
intel_port_to_tc(struct drm_i915_private
*dev_priv
, enum port port
)
6586 if (!intel_port_is_tc(dev_priv
, port
))
6587 return PORT_TC_NONE
;
6589 return port
- PORT_C
;
6592 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
)
6596 return POWER_DOMAIN_PORT_DDI_A_LANES
;
6598 return POWER_DOMAIN_PORT_DDI_B_LANES
;
6600 return POWER_DOMAIN_PORT_DDI_C_LANES
;
6602 return POWER_DOMAIN_PORT_DDI_D_LANES
;
6604 return POWER_DOMAIN_PORT_DDI_E_LANES
;
6606 return POWER_DOMAIN_PORT_DDI_F_LANES
;
6609 return POWER_DOMAIN_PORT_OTHER
;
6613 enum intel_display_power_domain
6614 intel_aux_power_domain(struct intel_digital_port
*dig_port
)
6616 switch (dig_port
->aux_ch
) {
6618 return POWER_DOMAIN_AUX_A
;
6620 return POWER_DOMAIN_AUX_B
;
6622 return POWER_DOMAIN_AUX_C
;
6624 return POWER_DOMAIN_AUX_D
;
6626 return POWER_DOMAIN_AUX_E
;
6628 return POWER_DOMAIN_AUX_F
;
6630 MISSING_CASE(dig_port
->aux_ch
);
6631 return POWER_DOMAIN_AUX_A
;
6635 static u64
get_crtc_power_domains(struct drm_crtc
*crtc
,
6636 struct intel_crtc_state
*crtc_state
)
6638 struct drm_device
*dev
= crtc
->dev
;
6639 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6640 struct drm_encoder
*encoder
;
6641 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6642 enum pipe pipe
= intel_crtc
->pipe
;
6644 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
6646 if (!crtc_state
->base
.active
)
6649 mask
= BIT_ULL(POWER_DOMAIN_PIPE(pipe
));
6650 mask
|= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder
));
6651 if (crtc_state
->pch_pfit
.enabled
||
6652 crtc_state
->pch_pfit
.force_thru
)
6653 mask
|= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
6655 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
6656 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6658 mask
|= BIT_ULL(intel_encoder
->power_domain
);
6661 if (HAS_DDI(dev_priv
) && crtc_state
->has_audio
)
6662 mask
|= BIT_ULL(POWER_DOMAIN_AUDIO
);
6664 if (crtc_state
->shared_dpll
)
6665 mask
|= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE
);
6671 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
6672 struct intel_crtc_state
*crtc_state
)
6674 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6675 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6676 enum intel_display_power_domain domain
;
6677 u64 domains
, new_domains
, old_domains
;
6679 old_domains
= intel_crtc
->enabled_power_domains
;
6680 intel_crtc
->enabled_power_domains
= new_domains
=
6681 get_crtc_power_domains(crtc
, crtc_state
);
6683 domains
= new_domains
& ~old_domains
;
6685 for_each_power_domain(domain
, domains
)
6686 intel_display_power_get(dev_priv
, domain
);
6688 return old_domains
& ~new_domains
;
6691 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
6694 enum intel_display_power_domain domain
;
6696 for_each_power_domain(domain
, domains
)
6697 intel_display_power_put_unchecked(dev_priv
, domain
);
6700 static void valleyview_crtc_enable(struct intel_crtc_state
*pipe_config
,
6701 struct drm_atomic_state
*old_state
)
6703 struct intel_atomic_state
*old_intel_state
=
6704 to_intel_atomic_state(old_state
);
6705 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6706 struct drm_device
*dev
= crtc
->dev
;
6707 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6709 int pipe
= intel_crtc
->pipe
;
6711 if (WARN_ON(intel_crtc
->active
))
6714 if (intel_crtc_has_dp_encoder(pipe_config
))
6715 intel_dp_set_m_n(pipe_config
, M1_N1
);
6717 intel_set_pipe_timings(pipe_config
);
6718 intel_set_pipe_src_size(pipe_config
);
6720 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
6721 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6722 I915_WRITE(CHV_CANVAS(pipe
), 0);
6725 i9xx_set_pipeconf(pipe_config
);
6727 intel_crtc
->active
= true;
6729 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6731 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
6733 if (IS_CHERRYVIEW(dev_priv
)) {
6734 chv_prepare_pll(intel_crtc
, pipe_config
);
6735 chv_enable_pll(intel_crtc
, pipe_config
);
6737 vlv_prepare_pll(intel_crtc
, pipe_config
);
6738 vlv_enable_pll(intel_crtc
, pipe_config
);
6741 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6743 i9xx_pfit_enable(pipe_config
);
6745 intel_color_load_luts(pipe_config
);
6746 intel_color_commit(pipe_config
);
6747 /* update DSPCNTR to configure gamma for pipe bottom color */
6748 intel_disable_primary_plane(pipe_config
);
6750 dev_priv
->display
.initial_watermarks(old_intel_state
,
6752 intel_enable_pipe(pipe_config
);
6754 assert_vblank_disabled(crtc
);
6755 intel_crtc_vblank_on(pipe_config
);
6757 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6760 static void i9xx_set_pll_dividers(const struct intel_crtc_state
*crtc_state
)
6762 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6763 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6765 I915_WRITE(FP0(crtc
->pipe
), crtc_state
->dpll_hw_state
.fp0
);
6766 I915_WRITE(FP1(crtc
->pipe
), crtc_state
->dpll_hw_state
.fp1
);
6769 static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config
,
6770 struct drm_atomic_state
*old_state
)
6772 struct intel_atomic_state
*old_intel_state
=
6773 to_intel_atomic_state(old_state
);
6774 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6775 struct drm_device
*dev
= crtc
->dev
;
6776 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6777 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6778 enum pipe pipe
= intel_crtc
->pipe
;
6780 if (WARN_ON(intel_crtc
->active
))
6783 i9xx_set_pll_dividers(pipe_config
);
6785 if (intel_crtc_has_dp_encoder(pipe_config
))
6786 intel_dp_set_m_n(pipe_config
, M1_N1
);
6788 intel_set_pipe_timings(pipe_config
);
6789 intel_set_pipe_src_size(pipe_config
);
6791 i9xx_set_pipeconf(pipe_config
);
6793 intel_crtc
->active
= true;
6795 if (!IS_GEN(dev_priv
, 2))
6796 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6798 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6800 i9xx_enable_pll(intel_crtc
, pipe_config
);
6802 i9xx_pfit_enable(pipe_config
);
6804 intel_color_load_luts(pipe_config
);
6805 intel_color_commit(pipe_config
);
6806 /* update DSPCNTR to configure gamma for pipe bottom color */
6807 intel_disable_primary_plane(pipe_config
);
6809 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6810 dev_priv
->display
.initial_watermarks(old_intel_state
,
6813 intel_update_watermarks(intel_crtc
);
6814 intel_enable_pipe(pipe_config
);
6816 assert_vblank_disabled(crtc
);
6817 intel_crtc_vblank_on(pipe_config
);
6819 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6822 static void i9xx_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
6824 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
6825 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6827 if (!old_crtc_state
->gmch_pfit
.control
)
6830 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6832 DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6833 I915_READ(PFIT_CONTROL
));
6834 I915_WRITE(PFIT_CONTROL
, 0);
6837 static void i9xx_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6838 struct drm_atomic_state
*old_state
)
6840 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6841 struct drm_device
*dev
= crtc
->dev
;
6842 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6843 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6844 int pipe
= intel_crtc
->pipe
;
6847 * On gen2 planes are double buffered but the pipe isn't, so we must
6848 * wait for planes to fully turn off before disabling the pipe.
6850 if (IS_GEN(dev_priv
, 2))
6851 intel_wait_for_vblank(dev_priv
, pipe
);
6853 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6855 drm_crtc_vblank_off(crtc
);
6856 assert_vblank_disabled(crtc
);
6858 intel_disable_pipe(old_crtc_state
);
6860 i9xx_pfit_disable(old_crtc_state
);
6862 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6864 if (!intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DSI
)) {
6865 if (IS_CHERRYVIEW(dev_priv
))
6866 chv_disable_pll(dev_priv
, pipe
);
6867 else if (IS_VALLEYVIEW(dev_priv
))
6868 vlv_disable_pll(dev_priv
, pipe
);
6870 i9xx_disable_pll(old_crtc_state
);
6873 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6875 if (!IS_GEN(dev_priv
, 2))
6876 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6878 if (!dev_priv
->display
.initial_watermarks
)
6879 intel_update_watermarks(intel_crtc
);
6881 /* clock the pipe down to 640x480@60 to potentially save power */
6882 if (IS_I830(dev_priv
))
6883 i830_enable_pipe(dev_priv
, pipe
);
6886 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
,
6887 struct drm_modeset_acquire_ctx
*ctx
)
6889 struct intel_encoder
*encoder
;
6890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6891 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6892 struct intel_bw_state
*bw_state
=
6893 to_intel_bw_state(dev_priv
->bw_obj
.state
);
6894 enum intel_display_power_domain domain
;
6895 struct intel_plane
*plane
;
6897 struct drm_atomic_state
*state
;
6898 struct intel_crtc_state
*crtc_state
;
6901 if (!intel_crtc
->active
)
6904 for_each_intel_plane_on_crtc(&dev_priv
->drm
, intel_crtc
, plane
) {
6905 const struct intel_plane_state
*plane_state
=
6906 to_intel_plane_state(plane
->base
.state
);
6908 if (plane_state
->base
.visible
)
6909 intel_plane_disable_noatomic(intel_crtc
, plane
);
6912 state
= drm_atomic_state_alloc(crtc
->dev
);
6914 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6915 crtc
->base
.id
, crtc
->name
);
6919 state
->acquire_ctx
= ctx
;
6921 /* Everything's already locked, -EDEADLK can't happen. */
6922 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
6923 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
6925 WARN_ON(IS_ERR(crtc_state
) || ret
);
6927 dev_priv
->display
.crtc_disable(crtc_state
, state
);
6929 drm_atomic_state_put(state
);
6931 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6932 crtc
->base
.id
, crtc
->name
);
6934 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6935 crtc
->state
->active
= false;
6936 intel_crtc
->active
= false;
6937 crtc
->enabled
= false;
6938 crtc
->state
->connector_mask
= 0;
6939 crtc
->state
->encoder_mask
= 0;
6941 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6942 encoder
->base
.crtc
= NULL
;
6944 intel_fbc_disable(intel_crtc
);
6945 intel_update_watermarks(intel_crtc
);
6946 intel_disable_shared_dpll(to_intel_crtc_state(crtc
->state
));
6948 domains
= intel_crtc
->enabled_power_domains
;
6949 for_each_power_domain(domain
, domains
)
6950 intel_display_power_put_unchecked(dev_priv
, domain
);
6951 intel_crtc
->enabled_power_domains
= 0;
6953 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6954 dev_priv
->min_cdclk
[intel_crtc
->pipe
] = 0;
6955 dev_priv
->min_voltage_level
[intel_crtc
->pipe
] = 0;
6957 bw_state
->data_rate
[intel_crtc
->pipe
] = 0;
6958 bw_state
->num_active_planes
[intel_crtc
->pipe
] = 0;
6962 * turn all crtc's off, but do not adjust state
6963 * This has to be paired with a call to intel_modeset_setup_hw_state.
6965 int intel_display_suspend(struct drm_device
*dev
)
6967 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6968 struct drm_atomic_state
*state
;
6971 state
= drm_atomic_helper_suspend(dev
);
6972 ret
= PTR_ERR_OR_ZERO(state
);
6974 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6976 dev_priv
->modeset_restore_state
= state
;
6980 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6982 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6984 drm_encoder_cleanup(encoder
);
6985 kfree(intel_encoder
);
6988 /* Cross check the actual hw state with our own modeset state tracking (and it's
6989 * internal consistency). */
6990 static void intel_connector_verify_state(struct drm_crtc_state
*crtc_state
,
6991 struct drm_connector_state
*conn_state
)
6993 struct intel_connector
*connector
= to_intel_connector(conn_state
->connector
);
6995 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6996 connector
->base
.base
.id
,
6997 connector
->base
.name
);
6999 if (connector
->get_hw_state(connector
)) {
7000 struct intel_encoder
*encoder
= connector
->encoder
;
7002 I915_STATE_WARN(!crtc_state
,
7003 "connector enabled without attached crtc\n");
7008 I915_STATE_WARN(!crtc_state
->active
,
7009 "connector is active, but attached crtc isn't\n");
7011 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
7014 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
7015 "atomic encoder doesn't match attached encoder\n");
7017 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
7018 "attached encoder crtc differs from connector crtc\n");
7020 I915_STATE_WARN(crtc_state
&& crtc_state
->active
,
7021 "attached crtc is active, but connector isn't\n");
7022 I915_STATE_WARN(!crtc_state
&& conn_state
->best_encoder
,
7023 "best encoder set without crtc!\n");
7027 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
7029 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
7030 return crtc_state
->fdi_lanes
;
7035 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
7036 struct intel_crtc_state
*pipe_config
)
7038 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7039 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
7040 struct intel_crtc
*other_crtc
;
7041 struct intel_crtc_state
*other_crtc_state
;
7043 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7044 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7045 if (pipe_config
->fdi_lanes
> 4) {
7046 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7047 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7051 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
7052 if (pipe_config
->fdi_lanes
> 2) {
7053 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7054 pipe_config
->fdi_lanes
);
7061 if (INTEL_INFO(dev_priv
)->num_pipes
== 2)
7064 /* Ivybridge 3 pipe is really complicated */
7069 if (pipe_config
->fdi_lanes
<= 2)
7072 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_C
);
7074 intel_atomic_get_crtc_state(state
, other_crtc
);
7075 if (IS_ERR(other_crtc_state
))
7076 return PTR_ERR(other_crtc_state
);
7078 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
7079 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7080 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7085 if (pipe_config
->fdi_lanes
> 2) {
7086 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7087 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7091 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_B
);
7093 intel_atomic_get_crtc_state(state
, other_crtc
);
7094 if (IS_ERR(other_crtc_state
))
7095 return PTR_ERR(other_crtc_state
);
7097 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
7098 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7108 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
7109 struct intel_crtc_state
*pipe_config
)
7111 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7112 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
7113 int lane
, link_bw
, fdi_dotclock
, ret
;
7114 bool needs_recompute
= false;
7117 /* FDI is a binary signal running at ~2.7GHz, encoding
7118 * each output octet as 10 bits. The actual frequency
7119 * is stored as a divider into a 100MHz clock, and the
7120 * mode pixel clock is stored in units of 1KHz.
7121 * Hence the bw of each lane in terms of the mode signal
7124 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
7126 fdi_dotclock
= adjusted_mode
->crtc_clock
;
7128 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
7129 pipe_config
->pipe_bpp
);
7131 pipe_config
->fdi_lanes
= lane
;
7133 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
7134 link_bw
, &pipe_config
->fdi_m_n
, false);
7136 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
7137 if (ret
== -EDEADLK
)
7140 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
7141 pipe_config
->pipe_bpp
-= 2*3;
7142 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7143 pipe_config
->pipe_bpp
);
7144 needs_recompute
= true;
7145 pipe_config
->bw_constrained
= true;
7150 if (needs_recompute
)
7156 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state
*crtc_state
)
7158 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7159 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7161 /* IPS only exists on ULT machines and is tied to pipe A. */
7162 if (!hsw_crtc_supports_ips(crtc
))
7165 if (!i915_modparams
.enable_ips
)
7168 if (crtc_state
->pipe_bpp
> 24)
7172 * We compare against max which means we must take
7173 * the increased cdclk requirement into account when
7174 * calculating the new cdclk.
7176 * Should measure whether using a lower cdclk w/o IPS
7178 if (IS_BROADWELL(dev_priv
) &&
7179 crtc_state
->pixel_rate
> dev_priv
->max_cdclk_freq
* 95 / 100)
7185 static bool hsw_compute_ips_config(struct intel_crtc_state
*crtc_state
)
7187 struct drm_i915_private
*dev_priv
=
7188 to_i915(crtc_state
->base
.crtc
->dev
);
7189 struct intel_atomic_state
*intel_state
=
7190 to_intel_atomic_state(crtc_state
->base
.state
);
7192 if (!hsw_crtc_state_ips_capable(crtc_state
))
7196 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7197 * enabled and disabled dynamically based on package C states,
7198 * user space can't make reliable use of the CRCs, so let's just
7199 * completely disable it.
7201 if (crtc_state
->crc_enabled
)
7204 /* IPS should be fine as long as at least one plane is enabled. */
7205 if (!(crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)))
7208 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7209 if (IS_BROADWELL(dev_priv
) &&
7210 crtc_state
->pixel_rate
> intel_state
->cdclk
.logical
.cdclk
* 95 / 100)
7216 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
7218 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7220 /* GDG double wide on either pipe, otherwise pipe A only */
7221 return INTEL_GEN(dev_priv
) < 4 &&
7222 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
7225 static u32
ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
7229 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7232 * We only use IF-ID interlacing. If we ever use
7233 * PF-ID we'll need to adjust the pixel_rate here.
7236 if (pipe_config
->pch_pfit
.enabled
) {
7237 u64 pipe_w
, pipe_h
, pfit_w
, pfit_h
;
7238 u32 pfit_size
= pipe_config
->pch_pfit
.size
;
7240 pipe_w
= pipe_config
->pipe_src_w
;
7241 pipe_h
= pipe_config
->pipe_src_h
;
7243 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
7244 pfit_h
= pfit_size
& 0xFFFF;
7245 if (pipe_w
< pfit_w
)
7247 if (pipe_h
< pfit_h
)
7250 if (WARN_ON(!pfit_w
|| !pfit_h
))
7253 pixel_rate
= div_u64(mul_u32_u32(pixel_rate
, pipe_w
* pipe_h
),
7260 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state
*crtc_state
)
7262 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
7264 if (HAS_GMCH(dev_priv
))
7265 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7266 crtc_state
->pixel_rate
=
7267 crtc_state
->base
.adjusted_mode
.crtc_clock
;
7269 crtc_state
->pixel_rate
=
7270 ilk_pipe_pixel_rate(crtc_state
);
7273 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
7274 struct intel_crtc_state
*pipe_config
)
7276 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7277 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
7278 int clock_limit
= dev_priv
->max_dotclk_freq
;
7280 if (INTEL_GEN(dev_priv
) < 4) {
7281 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
7284 * Enable double wide mode when the dot clock
7285 * is > 90% of the (display) core speed.
7287 if (intel_crtc_supports_double_wide(crtc
) &&
7288 adjusted_mode
->crtc_clock
> clock_limit
) {
7289 clock_limit
= dev_priv
->max_dotclk_freq
;
7290 pipe_config
->double_wide
= true;
7294 if (adjusted_mode
->crtc_clock
> clock_limit
) {
7295 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7296 adjusted_mode
->crtc_clock
, clock_limit
,
7297 yesno(pipe_config
->double_wide
));
7301 if ((pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
7302 pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
) &&
7303 pipe_config
->base
.ctm
) {
7305 * There is only one pipe CSC unit per pipe, and we need that
7306 * for output conversion from RGB->YCBCR. So if CTM is already
7307 * applied we can't support YCBCR420 output.
7309 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7314 * Pipe horizontal size must be even in:
7316 * - LVDS dual channel mode
7317 * - Double wide pipe
7319 if (pipe_config
->pipe_src_w
& 1) {
7320 if (pipe_config
->double_wide
) {
7321 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7325 if (intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
7326 intel_is_dual_link_lvds(dev_priv
)) {
7327 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7332 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7333 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7335 if ((INTEL_GEN(dev_priv
) > 4 || IS_G4X(dev_priv
)) &&
7336 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
7339 intel_crtc_compute_pixel_rate(pipe_config
);
7341 if (pipe_config
->has_pch_encoder
)
7342 return ironlake_fdi_compute_config(crtc
, pipe_config
);
7348 intel_reduce_m_n_ratio(u32
*num
, u32
*den
)
7350 while (*num
> DATA_LINK_M_N_MASK
||
7351 *den
> DATA_LINK_M_N_MASK
) {
7357 static void compute_m_n(unsigned int m
, unsigned int n
,
7358 u32
*ret_m
, u32
*ret_n
,
7362 * Several DP dongles in particular seem to be fussy about
7363 * too large link M/N values. Give N value as 0x8000 that
7364 * should be acceptable by specific devices. 0x8000 is the
7365 * specified fixed N value for asynchronous clock mode,
7366 * which the devices expect also in synchronous clock mode.
7371 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7373 *ret_m
= div_u64(mul_u32_u32(m
, *ret_n
), n
);
7374 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7378 intel_link_compute_m_n(u16 bits_per_pixel
, int nlanes
,
7379 int pixel_clock
, int link_clock
,
7380 struct intel_link_m_n
*m_n
,
7385 compute_m_n(bits_per_pixel
* pixel_clock
,
7386 link_clock
* nlanes
* 8,
7387 &m_n
->gmch_m
, &m_n
->gmch_n
,
7390 compute_m_n(pixel_clock
, link_clock
,
7391 &m_n
->link_m
, &m_n
->link_n
,
7395 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7397 if (i915_modparams
.panel_use_ssc
>= 0)
7398 return i915_modparams
.panel_use_ssc
!= 0;
7399 return dev_priv
->vbt
.lvds_use_ssc
7400 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7403 static u32
pnv_dpll_compute_fp(struct dpll
*dpll
)
7405 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7408 static u32
i9xx_dpll_compute_fp(struct dpll
*dpll
)
7410 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7413 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7414 struct intel_crtc_state
*crtc_state
,
7415 struct dpll
*reduced_clock
)
7417 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7420 if (IS_PINEVIEW(dev_priv
)) {
7421 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7423 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7425 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7427 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7430 crtc_state
->dpll_hw_state
.fp0
= fp
;
7432 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7434 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7436 crtc_state
->dpll_hw_state
.fp1
= fp
;
7440 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7446 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7447 * and set it to a reasonable value instead.
7449 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7450 reg_val
&= 0xffffff00;
7451 reg_val
|= 0x00000030;
7452 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7454 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7455 reg_val
&= 0x00ffffff;
7456 reg_val
|= 0x8c000000;
7457 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7459 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7460 reg_val
&= 0xffffff00;
7461 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7463 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7464 reg_val
&= 0x00ffffff;
7465 reg_val
|= 0xb0000000;
7466 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7469 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
7470 const struct intel_link_m_n
*m_n
)
7472 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7473 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7474 enum pipe pipe
= crtc
->pipe
;
7476 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7477 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7478 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7479 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7482 static bool transcoder_has_m2_n2(struct drm_i915_private
*dev_priv
,
7483 enum transcoder transcoder
)
7485 if (IS_HASWELL(dev_priv
))
7486 return transcoder
== TRANSCODER_EDP
;
7489 * Strictly speaking some registers are available before
7490 * gen7, but we only support DRRS on gen7+
7492 return IS_GEN(dev_priv
, 7) || IS_CHERRYVIEW(dev_priv
);
7495 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
7496 const struct intel_link_m_n
*m_n
,
7497 const struct intel_link_m_n
*m2_n2
)
7499 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7500 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7501 enum pipe pipe
= crtc
->pipe
;
7502 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
7504 if (INTEL_GEN(dev_priv
) >= 5) {
7505 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7506 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7507 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7508 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7510 * M2_N2 registers are set only if DRRS is supported
7511 * (to make sure the registers are not unnecessarily accessed).
7513 if (m2_n2
&& crtc_state
->has_drrs
&&
7514 transcoder_has_m2_n2(dev_priv
, transcoder
)) {
7515 I915_WRITE(PIPE_DATA_M2(transcoder
),
7516 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7517 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7518 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7519 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7522 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7523 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7524 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7525 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7529 void intel_dp_set_m_n(const struct intel_crtc_state
*crtc_state
, enum link_m_n_set m_n
)
7531 const struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7534 dp_m_n
= &crtc_state
->dp_m_n
;
7535 dp_m2_n2
= &crtc_state
->dp_m2_n2
;
7536 } else if (m_n
== M2_N2
) {
7539 * M2_N2 registers are not supported. Hence m2_n2 divider value
7540 * needs to be programmed into M1_N1.
7542 dp_m_n
= &crtc_state
->dp_m2_n2
;
7544 DRM_ERROR("Unsupported divider value\n");
7548 if (crtc_state
->has_pch_encoder
)
7549 intel_pch_transcoder_set_m_n(crtc_state
, &crtc_state
->dp_m_n
);
7551 intel_cpu_transcoder_set_m_n(crtc_state
, dp_m_n
, dp_m2_n2
);
7554 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7555 struct intel_crtc_state
*pipe_config
)
7557 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7558 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7559 if (crtc
->pipe
!= PIPE_A
)
7560 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7562 /* DPLL not used with DSI, but still need the rest set up */
7563 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7564 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7565 DPLL_EXT_BUFFER_ENABLE_VLV
;
7567 pipe_config
->dpll_hw_state
.dpll_md
=
7568 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7571 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7572 struct intel_crtc_state
*pipe_config
)
7574 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7575 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7576 if (crtc
->pipe
!= PIPE_A
)
7577 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7579 /* DPLL not used with DSI, but still need the rest set up */
7580 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7581 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7583 pipe_config
->dpll_hw_state
.dpll_md
=
7584 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7587 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7588 const struct intel_crtc_state
*pipe_config
)
7590 struct drm_device
*dev
= crtc
->base
.dev
;
7591 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7592 enum pipe pipe
= crtc
->pipe
;
7594 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7595 u32 coreclk
, reg_val
;
7598 I915_WRITE(DPLL(pipe
),
7599 pipe_config
->dpll_hw_state
.dpll
&
7600 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7602 /* No need to actually set up the DPLL with DSI */
7603 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7606 vlv_dpio_get(dev_priv
);
7608 bestn
= pipe_config
->dpll
.n
;
7609 bestm1
= pipe_config
->dpll
.m1
;
7610 bestm2
= pipe_config
->dpll
.m2
;
7611 bestp1
= pipe_config
->dpll
.p1
;
7612 bestp2
= pipe_config
->dpll
.p2
;
7614 /* See eDP HDMI DPIO driver vbios notes doc */
7616 /* PLL B needs special handling */
7618 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7620 /* Set up Tx target for periodic Rcomp update */
7621 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7623 /* Disable target IRef on PLL */
7624 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7625 reg_val
&= 0x00ffffff;
7626 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7628 /* Disable fast lock */
7629 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7631 /* Set idtafcrecal before PLL is enabled */
7632 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7633 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7634 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7635 mdiv
|= (1 << DPIO_K_SHIFT
);
7638 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7639 * but we don't support that).
7640 * Note: don't use the DAC post divider as it seems unstable.
7642 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7643 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7645 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7646 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7648 /* Set HBR and RBR LPF coefficients */
7649 if (pipe_config
->port_clock
== 162000 ||
7650 intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_ANALOG
) ||
7651 intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_HDMI
))
7652 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7655 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7658 if (intel_crtc_has_dp_encoder(pipe_config
)) {
7659 /* Use SSC source */
7661 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7664 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7666 } else { /* HDMI or VGA */
7667 /* Use bend source */
7669 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7672 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7676 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7677 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7678 if (intel_crtc_has_dp_encoder(pipe_config
))
7679 coreclk
|= 0x01000000;
7680 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7682 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7684 vlv_dpio_put(dev_priv
);
7687 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7688 const struct intel_crtc_state
*pipe_config
)
7690 struct drm_device
*dev
= crtc
->base
.dev
;
7691 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7692 enum pipe pipe
= crtc
->pipe
;
7693 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7694 u32 loopfilter
, tribuf_calcntr
;
7695 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7699 /* Enable Refclk and SSC */
7700 I915_WRITE(DPLL(pipe
),
7701 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7703 /* No need to actually set up the DPLL with DSI */
7704 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7707 bestn
= pipe_config
->dpll
.n
;
7708 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7709 bestm1
= pipe_config
->dpll
.m1
;
7710 bestm2
= pipe_config
->dpll
.m2
>> 22;
7711 bestp1
= pipe_config
->dpll
.p1
;
7712 bestp2
= pipe_config
->dpll
.p2
;
7713 vco
= pipe_config
->dpll
.vco
;
7717 vlv_dpio_get(dev_priv
);
7719 /* p1 and p2 divider */
7720 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7721 5 << DPIO_CHV_S1_DIV_SHIFT
|
7722 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7723 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7724 1 << DPIO_CHV_K_DIV_SHIFT
);
7726 /* Feedback post-divider - m2 */
7727 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7729 /* Feedback refclk divider - n and m1 */
7730 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7731 DPIO_CHV_M1_DIV_BY_2
|
7732 1 << DPIO_CHV_N_DIV_SHIFT
);
7734 /* M2 fraction division */
7735 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7737 /* M2 fraction division enable */
7738 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7739 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7740 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7742 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7743 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7745 /* Program digital lock detect threshold */
7746 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7747 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7748 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7749 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7751 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7752 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7755 if (vco
== 5400000) {
7756 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7757 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7758 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7759 tribuf_calcntr
= 0x9;
7760 } else if (vco
<= 6200000) {
7761 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7762 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7763 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7764 tribuf_calcntr
= 0x9;
7765 } else if (vco
<= 6480000) {
7766 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7767 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7768 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7769 tribuf_calcntr
= 0x8;
7771 /* Not supported. Apply the same limits as in the max case */
7772 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7773 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7774 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7777 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7779 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7780 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7781 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7782 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7785 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7786 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7789 vlv_dpio_put(dev_priv
);
7793 * vlv_force_pll_on - forcibly enable just the PLL
7794 * @dev_priv: i915 private structure
7795 * @pipe: pipe PLL to enable
7796 * @dpll: PLL configuration
7798 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7799 * in cases where we need the PLL enabled even when @pipe is not going to
7802 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
7803 const struct dpll
*dpll
)
7805 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
7806 struct intel_crtc_state
*pipe_config
;
7808 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7812 pipe_config
->base
.crtc
= &crtc
->base
;
7813 pipe_config
->pixel_multiplier
= 1;
7814 pipe_config
->dpll
= *dpll
;
7816 if (IS_CHERRYVIEW(dev_priv
)) {
7817 chv_compute_dpll(crtc
, pipe_config
);
7818 chv_prepare_pll(crtc
, pipe_config
);
7819 chv_enable_pll(crtc
, pipe_config
);
7821 vlv_compute_dpll(crtc
, pipe_config
);
7822 vlv_prepare_pll(crtc
, pipe_config
);
7823 vlv_enable_pll(crtc
, pipe_config
);
7832 * vlv_force_pll_off - forcibly disable just the PLL
7833 * @dev_priv: i915 private structure
7834 * @pipe: pipe PLL to disable
7836 * Disable the PLL for @pipe. To be used in cases where we need
7837 * the PLL enabled even when @pipe is not going to be enabled.
7839 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
7841 if (IS_CHERRYVIEW(dev_priv
))
7842 chv_disable_pll(dev_priv
, pipe
);
7844 vlv_disable_pll(dev_priv
, pipe
);
7847 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7848 struct intel_crtc_state
*crtc_state
,
7849 struct dpll
*reduced_clock
)
7851 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7853 struct dpll
*clock
= &crtc_state
->dpll
;
7855 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7857 dpll
= DPLL_VGA_MODE_DIS
;
7859 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7860 dpll
|= DPLLB_MODE_LVDS
;
7862 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7864 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
7865 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
7866 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7867 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7870 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7871 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
7872 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7874 if (intel_crtc_has_dp_encoder(crtc_state
))
7875 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7877 /* compute bitmask from p1 value */
7878 if (IS_PINEVIEW(dev_priv
))
7879 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7881 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7882 if (IS_G4X(dev_priv
) && reduced_clock
)
7883 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7885 switch (clock
->p2
) {
7887 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7890 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7893 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7896 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7899 if (INTEL_GEN(dev_priv
) >= 4)
7900 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7902 if (crtc_state
->sdvo_tv_clock
)
7903 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7904 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7905 intel_panel_use_ssc(dev_priv
))
7906 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7908 dpll
|= PLL_REF_INPUT_DREFCLK
;
7910 dpll
|= DPLL_VCO_ENABLE
;
7911 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7913 if (INTEL_GEN(dev_priv
) >= 4) {
7914 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7915 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7916 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7920 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7921 struct intel_crtc_state
*crtc_state
,
7922 struct dpll
*reduced_clock
)
7924 struct drm_device
*dev
= crtc
->base
.dev
;
7925 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7927 struct dpll
*clock
= &crtc_state
->dpll
;
7929 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7931 dpll
= DPLL_VGA_MODE_DIS
;
7933 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7934 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7937 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7939 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7941 dpll
|= PLL_P2_DIVIDE_BY_4
;
7946 * "[Almador Errata}: For the correct operation of the muxed DVO pins
7947 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
7948 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
7949 * Enable) must be set to “1” in both the DPLL A Control Register
7950 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
7952 * For simplicity We simply keep both bits always enabled in
7953 * both DPLLS. The spec says we should disable the DVO 2X clock
7954 * when not needed, but this seems to work fine in practice.
7956 if (IS_I830(dev_priv
) ||
7957 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
7958 dpll
|= DPLL_DVO_2X_MODE
;
7960 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7961 intel_panel_use_ssc(dev_priv
))
7962 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7964 dpll
|= PLL_REF_INPUT_DREFCLK
;
7966 dpll
|= DPLL_VCO_ENABLE
;
7967 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7970 static void intel_set_pipe_timings(const struct intel_crtc_state
*crtc_state
)
7972 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7973 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7974 enum pipe pipe
= crtc
->pipe
;
7975 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
7976 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
7977 u32 crtc_vtotal
, crtc_vblank_end
;
7980 /* We need to be careful not to changed the adjusted mode, for otherwise
7981 * the hw state checker will get angry at the mismatch. */
7982 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7983 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7985 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7986 /* the chip adds 2 halflines automatically */
7988 crtc_vblank_end
-= 1;
7990 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
7991 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7993 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7994 adjusted_mode
->crtc_htotal
/ 2;
7996 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7999 if (INTEL_GEN(dev_priv
) > 3)
8000 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
8002 I915_WRITE(HTOTAL(cpu_transcoder
),
8003 (adjusted_mode
->crtc_hdisplay
- 1) |
8004 ((adjusted_mode
->crtc_htotal
- 1) << 16));
8005 I915_WRITE(HBLANK(cpu_transcoder
),
8006 (adjusted_mode
->crtc_hblank_start
- 1) |
8007 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
8008 I915_WRITE(HSYNC(cpu_transcoder
),
8009 (adjusted_mode
->crtc_hsync_start
- 1) |
8010 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
8012 I915_WRITE(VTOTAL(cpu_transcoder
),
8013 (adjusted_mode
->crtc_vdisplay
- 1) |
8014 ((crtc_vtotal
- 1) << 16));
8015 I915_WRITE(VBLANK(cpu_transcoder
),
8016 (adjusted_mode
->crtc_vblank_start
- 1) |
8017 ((crtc_vblank_end
- 1) << 16));
8018 I915_WRITE(VSYNC(cpu_transcoder
),
8019 (adjusted_mode
->crtc_vsync_start
- 1) |
8020 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
8022 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8023 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8024 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8026 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
8027 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
8028 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
8032 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
)
8034 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8035 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8036 enum pipe pipe
= crtc
->pipe
;
8038 /* pipesrc controls the size that is scaled from, which should
8039 * always be the user's requested size.
8041 I915_WRITE(PIPESRC(pipe
),
8042 ((crtc_state
->pipe_src_w
- 1) << 16) |
8043 (crtc_state
->pipe_src_h
- 1));
8046 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
8047 struct intel_crtc_state
*pipe_config
)
8049 struct drm_device
*dev
= crtc
->base
.dev
;
8050 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8051 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
8054 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
8055 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
8056 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
8058 if (!transcoder_is_dsi(cpu_transcoder
)) {
8059 tmp
= I915_READ(HBLANK(cpu_transcoder
));
8060 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
=
8062 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
=
8063 ((tmp
>> 16) & 0xffff) + 1;
8065 tmp
= I915_READ(HSYNC(cpu_transcoder
));
8066 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
8067 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
8069 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
8070 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
8071 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
8073 if (!transcoder_is_dsi(cpu_transcoder
)) {
8074 tmp
= I915_READ(VBLANK(cpu_transcoder
));
8075 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
=
8077 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
=
8078 ((tmp
>> 16) & 0xffff) + 1;
8080 tmp
= I915_READ(VSYNC(cpu_transcoder
));
8081 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
8082 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
8084 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
8085 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
8086 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
8087 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
8091 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
8092 struct intel_crtc_state
*pipe_config
)
8094 struct drm_device
*dev
= crtc
->base
.dev
;
8095 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8098 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
8099 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
8100 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
8102 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
8103 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
8106 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
8107 struct intel_crtc_state
*pipe_config
)
8109 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
8110 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
8111 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
8112 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
8114 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
8115 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
8116 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
8117 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
8119 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
8120 mode
->type
= DRM_MODE_TYPE_DRIVER
;
8122 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
8124 mode
->hsync
= drm_mode_hsync(mode
);
8125 mode
->vrefresh
= drm_mode_vrefresh(mode
);
8126 drm_mode_set_name(mode
);
8129 static void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
8131 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8132 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8137 /* we keep both pipes enabled on 830 */
8138 if (IS_I830(dev_priv
))
8139 pipeconf
|= I915_READ(PIPECONF(crtc
->pipe
)) & PIPECONF_ENABLE
;
8141 if (crtc_state
->double_wide
)
8142 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
8144 /* only g4x and later have fancy bpc/dither controls */
8145 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8146 IS_CHERRYVIEW(dev_priv
)) {
8147 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8148 if (crtc_state
->dither
&& crtc_state
->pipe_bpp
!= 30)
8149 pipeconf
|= PIPECONF_DITHER_EN
|
8150 PIPECONF_DITHER_TYPE_SP
;
8152 switch (crtc_state
->pipe_bpp
) {
8154 pipeconf
|= PIPECONF_6BPC
;
8157 pipeconf
|= PIPECONF_8BPC
;
8160 pipeconf
|= PIPECONF_10BPC
;
8163 /* Case prevented by intel_choose_pipe_bpp_dither. */
8168 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
8169 if (INTEL_GEN(dev_priv
) < 4 ||
8170 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
8171 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
8173 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
8175 pipeconf
|= PIPECONF_PROGRESSIVE
;
8178 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8179 crtc_state
->limited_color_range
)
8180 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
8182 pipeconf
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
8184 I915_WRITE(PIPECONF(crtc
->pipe
), pipeconf
);
8185 POSTING_READ(PIPECONF(crtc
->pipe
));
8188 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8189 struct intel_crtc_state
*crtc_state
)
8191 struct drm_device
*dev
= crtc
->base
.dev
;
8192 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8193 const struct intel_limit
*limit
;
8196 memset(&crtc_state
->dpll_hw_state
, 0,
8197 sizeof(crtc_state
->dpll_hw_state
));
8199 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8200 if (intel_panel_use_ssc(dev_priv
)) {
8201 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8202 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8205 limit
= &intel_limits_i8xx_lvds
;
8206 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
8207 limit
= &intel_limits_i8xx_dvo
;
8209 limit
= &intel_limits_i8xx_dac
;
8212 if (!crtc_state
->clock_set
&&
8213 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8214 refclk
, NULL
, &crtc_state
->dpll
)) {
8215 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8219 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
8224 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
8225 struct intel_crtc_state
*crtc_state
)
8227 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8228 const struct intel_limit
*limit
;
8231 memset(&crtc_state
->dpll_hw_state
, 0,
8232 sizeof(crtc_state
->dpll_hw_state
));
8234 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8235 if (intel_panel_use_ssc(dev_priv
)) {
8236 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8237 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8240 if (intel_is_dual_link_lvds(dev_priv
))
8241 limit
= &intel_limits_g4x_dual_channel_lvds
;
8243 limit
= &intel_limits_g4x_single_channel_lvds
;
8244 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
8245 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
8246 limit
= &intel_limits_g4x_hdmi
;
8247 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
8248 limit
= &intel_limits_g4x_sdvo
;
8250 /* The option is for other outputs */
8251 limit
= &intel_limits_i9xx_sdvo
;
8254 if (!crtc_state
->clock_set
&&
8255 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8256 refclk
, NULL
, &crtc_state
->dpll
)) {
8257 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8261 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8266 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
8267 struct intel_crtc_state
*crtc_state
)
8269 struct drm_device
*dev
= crtc
->base
.dev
;
8270 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8271 const struct intel_limit
*limit
;
8274 memset(&crtc_state
->dpll_hw_state
, 0,
8275 sizeof(crtc_state
->dpll_hw_state
));
8277 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8278 if (intel_panel_use_ssc(dev_priv
)) {
8279 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8280 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8283 limit
= &intel_limits_pineview_lvds
;
8285 limit
= &intel_limits_pineview_sdvo
;
8288 if (!crtc_state
->clock_set
&&
8289 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8290 refclk
, NULL
, &crtc_state
->dpll
)) {
8291 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8295 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8300 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8301 struct intel_crtc_state
*crtc_state
)
8303 struct drm_device
*dev
= crtc
->base
.dev
;
8304 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8305 const struct intel_limit
*limit
;
8308 memset(&crtc_state
->dpll_hw_state
, 0,
8309 sizeof(crtc_state
->dpll_hw_state
));
8311 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8312 if (intel_panel_use_ssc(dev_priv
)) {
8313 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8314 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8317 limit
= &intel_limits_i9xx_lvds
;
8319 limit
= &intel_limits_i9xx_sdvo
;
8322 if (!crtc_state
->clock_set
&&
8323 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8324 refclk
, NULL
, &crtc_state
->dpll
)) {
8325 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8329 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8334 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
8335 struct intel_crtc_state
*crtc_state
)
8337 int refclk
= 100000;
8338 const struct intel_limit
*limit
= &intel_limits_chv
;
8340 memset(&crtc_state
->dpll_hw_state
, 0,
8341 sizeof(crtc_state
->dpll_hw_state
));
8343 if (!crtc_state
->clock_set
&&
8344 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8345 refclk
, NULL
, &crtc_state
->dpll
)) {
8346 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8350 chv_compute_dpll(crtc
, crtc_state
);
8355 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
8356 struct intel_crtc_state
*crtc_state
)
8358 int refclk
= 100000;
8359 const struct intel_limit
*limit
= &intel_limits_vlv
;
8361 memset(&crtc_state
->dpll_hw_state
, 0,
8362 sizeof(crtc_state
->dpll_hw_state
));
8364 if (!crtc_state
->clock_set
&&
8365 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8366 refclk
, NULL
, &crtc_state
->dpll
)) {
8367 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8371 vlv_compute_dpll(crtc
, crtc_state
);
8376 static bool i9xx_has_pfit(struct drm_i915_private
*dev_priv
)
8378 if (IS_I830(dev_priv
))
8381 return INTEL_GEN(dev_priv
) >= 4 ||
8382 IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
8385 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8386 struct intel_crtc_state
*pipe_config
)
8388 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8391 if (!i9xx_has_pfit(dev_priv
))
8394 tmp
= I915_READ(PFIT_CONTROL
);
8395 if (!(tmp
& PFIT_ENABLE
))
8398 /* Check whether the pfit is attached to our pipe. */
8399 if (INTEL_GEN(dev_priv
) < 4) {
8400 if (crtc
->pipe
!= PIPE_B
)
8403 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8407 pipe_config
->gmch_pfit
.control
= tmp
;
8408 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8411 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8412 struct intel_crtc_state
*pipe_config
)
8414 struct drm_device
*dev
= crtc
->base
.dev
;
8415 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8416 int pipe
= pipe_config
->cpu_transcoder
;
8419 int refclk
= 100000;
8421 /* In case of DSI, DPLL will not be used */
8422 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8425 vlv_dpio_get(dev_priv
);
8426 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8427 vlv_dpio_put(dev_priv
);
8429 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8430 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8431 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8432 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8433 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8435 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8439 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8440 struct intel_initial_plane_config
*plane_config
)
8442 struct drm_device
*dev
= crtc
->base
.dev
;
8443 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8444 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
8445 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
8447 u32 val
, base
, offset
;
8448 int fourcc
, pixel_format
;
8449 unsigned int aligned_height
;
8450 struct drm_framebuffer
*fb
;
8451 struct intel_framebuffer
*intel_fb
;
8453 if (!plane
->get_hw_state(plane
, &pipe
))
8456 WARN_ON(pipe
!= crtc
->pipe
);
8458 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8460 DRM_DEBUG_KMS("failed to alloc fb\n");
8464 fb
= &intel_fb
->base
;
8468 val
= I915_READ(DSPCNTR(i9xx_plane
));
8470 if (INTEL_GEN(dev_priv
) >= 4) {
8471 if (val
& DISPPLANE_TILED
) {
8472 plane_config
->tiling
= I915_TILING_X
;
8473 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8476 if (val
& DISPPLANE_ROTATE_180
)
8477 plane_config
->rotation
= DRM_MODE_ROTATE_180
;
8480 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
&&
8481 val
& DISPPLANE_MIRROR
)
8482 plane_config
->rotation
|= DRM_MODE_REFLECT_X
;
8484 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8485 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8486 fb
->format
= drm_format_info(fourcc
);
8488 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
8489 offset
= I915_READ(DSPOFFSET(i9xx_plane
));
8490 base
= I915_READ(DSPSURF(i9xx_plane
)) & 0xfffff000;
8491 } else if (INTEL_GEN(dev_priv
) >= 4) {
8492 if (plane_config
->tiling
)
8493 offset
= I915_READ(DSPTILEOFF(i9xx_plane
));
8495 offset
= I915_READ(DSPLINOFF(i9xx_plane
));
8496 base
= I915_READ(DSPSURF(i9xx_plane
)) & 0xfffff000;
8498 base
= I915_READ(DSPADDR(i9xx_plane
));
8500 plane_config
->base
= base
;
8502 val
= I915_READ(PIPESRC(pipe
));
8503 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8504 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8506 val
= I915_READ(DSPSTRIDE(i9xx_plane
));
8507 fb
->pitches
[0] = val
& 0xffffffc0;
8509 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
8511 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8513 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8514 crtc
->base
.name
, plane
->base
.name
, fb
->width
, fb
->height
,
8515 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
8516 plane_config
->size
);
8518 plane_config
->fb
= intel_fb
;
8521 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8522 struct intel_crtc_state
*pipe_config
)
8524 struct drm_device
*dev
= crtc
->base
.dev
;
8525 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8526 int pipe
= pipe_config
->cpu_transcoder
;
8527 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8529 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8530 int refclk
= 100000;
8532 /* In case of DSI, DPLL will not be used */
8533 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8536 vlv_dpio_get(dev_priv
);
8537 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8538 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8539 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8540 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8541 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8542 vlv_dpio_put(dev_priv
);
8544 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8545 clock
.m2
= (pll_dw0
& 0xff) << 22;
8546 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8547 clock
.m2
|= pll_dw2
& 0x3fffff;
8548 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8549 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8550 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8552 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8555 static void intel_get_crtc_ycbcr_config(struct intel_crtc
*crtc
,
8556 struct intel_crtc_state
*pipe_config
)
8558 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8559 enum intel_output_format output
= INTEL_OUTPUT_FORMAT_RGB
;
8561 pipe_config
->lspcon_downsampling
= false;
8563 if (IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9) {
8564 u32 tmp
= I915_READ(PIPEMISC(crtc
->pipe
));
8566 if (tmp
& PIPEMISC_OUTPUT_COLORSPACE_YUV
) {
8567 bool ycbcr420_enabled
= tmp
& PIPEMISC_YUV420_ENABLE
;
8568 bool blend
= tmp
& PIPEMISC_YUV420_MODE_FULL_BLEND
;
8570 if (ycbcr420_enabled
) {
8571 /* We support 4:2:0 in full blend mode only */
8573 output
= INTEL_OUTPUT_FORMAT_INVALID
;
8574 else if (!(IS_GEMINILAKE(dev_priv
) ||
8575 INTEL_GEN(dev_priv
) >= 10))
8576 output
= INTEL_OUTPUT_FORMAT_INVALID
;
8578 output
= INTEL_OUTPUT_FORMAT_YCBCR420
;
8581 * Currently there is no interface defined to
8582 * check user preference between RGB/YCBCR444
8583 * or YCBCR420. So the only possible case for
8584 * YCBCR444 usage is driving YCBCR420 output
8585 * with LSPCON, when pipe is configured for
8586 * YCBCR444 output and LSPCON takes care of
8589 pipe_config
->lspcon_downsampling
= true;
8590 output
= INTEL_OUTPUT_FORMAT_YCBCR444
;
8595 pipe_config
->output_format
= output
;
8598 static void i9xx_get_pipe_color_config(struct intel_crtc_state
*crtc_state
)
8600 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8601 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
8602 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8603 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
8606 tmp
= I915_READ(DSPCNTR(i9xx_plane
));
8608 if (tmp
& DISPPLANE_GAMMA_ENABLE
)
8609 crtc_state
->gamma_enable
= true;
8611 if (!HAS_GMCH(dev_priv
) &&
8612 tmp
& DISPPLANE_PIPE_CSC_ENABLE
)
8613 crtc_state
->csc_enable
= true;
8616 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8617 struct intel_crtc_state
*pipe_config
)
8619 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8620 enum intel_display_power_domain power_domain
;
8621 intel_wakeref_t wakeref
;
8625 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8626 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
8630 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
8631 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8632 pipe_config
->shared_dpll
= NULL
;
8636 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8637 if (!(tmp
& PIPECONF_ENABLE
))
8640 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8641 IS_CHERRYVIEW(dev_priv
)) {
8642 switch (tmp
& PIPECONF_BPC_MASK
) {
8644 pipe_config
->pipe_bpp
= 18;
8647 pipe_config
->pipe_bpp
= 24;
8649 case PIPECONF_10BPC
:
8650 pipe_config
->pipe_bpp
= 30;
8657 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8658 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8659 pipe_config
->limited_color_range
= true;
8661 pipe_config
->gamma_mode
= (tmp
& PIPECONF_GAMMA_MODE_MASK_I9XX
) >>
8662 PIPECONF_GAMMA_MODE_SHIFT
;
8664 if (IS_CHERRYVIEW(dev_priv
))
8665 pipe_config
->cgm_mode
= I915_READ(CGM_PIPE_MODE(crtc
->pipe
));
8667 i9xx_get_pipe_color_config(pipe_config
);
8668 intel_color_get_config(pipe_config
);
8670 if (INTEL_GEN(dev_priv
) < 4)
8671 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8673 intel_get_pipe_timings(crtc
, pipe_config
);
8674 intel_get_pipe_src_size(crtc
, pipe_config
);
8676 i9xx_get_pfit_config(crtc
, pipe_config
);
8678 if (INTEL_GEN(dev_priv
) >= 4) {
8679 /* No way to read it out on pipes B and C */
8680 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
8681 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8683 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8684 pipe_config
->pixel_multiplier
=
8685 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8686 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8687 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8688 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
8689 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
8690 tmp
= I915_READ(DPLL(crtc
->pipe
));
8691 pipe_config
->pixel_multiplier
=
8692 ((tmp
& SDVO_MULTIPLIER_MASK
)
8693 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8695 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8696 * port and will be fixed up in the encoder->get_config
8698 pipe_config
->pixel_multiplier
= 1;
8700 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8701 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
8702 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8703 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8705 /* Mask out read-only status bits. */
8706 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8707 DPLL_PORTC_READY_MASK
|
8708 DPLL_PORTB_READY_MASK
);
8711 if (IS_CHERRYVIEW(dev_priv
))
8712 chv_crtc_clock_get(crtc
, pipe_config
);
8713 else if (IS_VALLEYVIEW(dev_priv
))
8714 vlv_crtc_clock_get(crtc
, pipe_config
);
8716 i9xx_crtc_clock_get(crtc
, pipe_config
);
8719 * Normally the dotclock is filled in by the encoder .get_config()
8720 * but in case the pipe is enabled w/o any ports we need a sane
8723 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8724 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8729 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
8734 static void ironlake_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8736 struct intel_encoder
*encoder
;
8739 bool has_lvds
= false;
8740 bool has_cpu_edp
= false;
8741 bool has_panel
= false;
8742 bool has_ck505
= false;
8743 bool can_ssc
= false;
8744 bool using_ssc_source
= false;
8746 /* We need to take the global config into account */
8747 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8748 switch (encoder
->type
) {
8749 case INTEL_OUTPUT_LVDS
:
8753 case INTEL_OUTPUT_EDP
:
8755 if (encoder
->port
== PORT_A
)
8763 if (HAS_PCH_IBX(dev_priv
)) {
8764 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8765 can_ssc
= has_ck505
;
8771 /* Check if any DPLLs are using the SSC source */
8772 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8773 u32 temp
= I915_READ(PCH_DPLL(i
));
8775 if (!(temp
& DPLL_VCO_ENABLE
))
8778 if ((temp
& PLL_REF_INPUT_MASK
) ==
8779 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
8780 using_ssc_source
= true;
8785 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8786 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
8788 /* Ironlake: try to setup display ref clock before DPLL
8789 * enabling. This is only under driver's control after
8790 * PCH B stepping, previous chipset stepping should be
8791 * ignoring this setting.
8793 val
= I915_READ(PCH_DREF_CONTROL
);
8795 /* As we must carefully and slowly disable/enable each source in turn,
8796 * compute the final state we want first and check if we need to
8797 * make any changes at all.
8800 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8802 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8804 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8806 final
&= ~DREF_SSC_SOURCE_MASK
;
8807 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8808 final
&= ~DREF_SSC1_ENABLE
;
8811 final
|= DREF_SSC_SOURCE_ENABLE
;
8813 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8814 final
|= DREF_SSC1_ENABLE
;
8817 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8818 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8820 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8822 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8823 } else if (using_ssc_source
) {
8824 final
|= DREF_SSC_SOURCE_ENABLE
;
8825 final
|= DREF_SSC1_ENABLE
;
8831 /* Always enable nonspread source */
8832 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8835 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8837 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8840 val
&= ~DREF_SSC_SOURCE_MASK
;
8841 val
|= DREF_SSC_SOURCE_ENABLE
;
8843 /* SSC must be turned on before enabling the CPU output */
8844 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8845 DRM_DEBUG_KMS("Using SSC on panel\n");
8846 val
|= DREF_SSC1_ENABLE
;
8848 val
&= ~DREF_SSC1_ENABLE
;
8850 /* Get SSC going before enabling the outputs */
8851 I915_WRITE(PCH_DREF_CONTROL
, val
);
8852 POSTING_READ(PCH_DREF_CONTROL
);
8855 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8857 /* Enable CPU source on CPU attached eDP */
8859 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8860 DRM_DEBUG_KMS("Using SSC on eDP\n");
8861 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8863 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8865 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8867 I915_WRITE(PCH_DREF_CONTROL
, val
);
8868 POSTING_READ(PCH_DREF_CONTROL
);
8871 DRM_DEBUG_KMS("Disabling CPU source output\n");
8873 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8875 /* Turn off CPU output */
8876 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8878 I915_WRITE(PCH_DREF_CONTROL
, val
);
8879 POSTING_READ(PCH_DREF_CONTROL
);
8882 if (!using_ssc_source
) {
8883 DRM_DEBUG_KMS("Disabling SSC source\n");
8885 /* Turn off the SSC source */
8886 val
&= ~DREF_SSC_SOURCE_MASK
;
8887 val
|= DREF_SSC_SOURCE_DISABLE
;
8890 val
&= ~DREF_SSC1_ENABLE
;
8892 I915_WRITE(PCH_DREF_CONTROL
, val
);
8893 POSTING_READ(PCH_DREF_CONTROL
);
8898 BUG_ON(val
!= final
);
8901 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8905 tmp
= I915_READ(SOUTH_CHICKEN2
);
8906 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8907 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8909 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
8910 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8911 DRM_ERROR("FDI mPHY reset assert timeout\n");
8913 tmp
= I915_READ(SOUTH_CHICKEN2
);
8914 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8915 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8917 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
8918 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8919 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8922 /* WaMPhyProgramming:hsw */
8923 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8927 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8928 tmp
&= ~(0xFF << 24);
8929 tmp
|= (0x12 << 24);
8930 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8932 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8934 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8936 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8938 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8940 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8941 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8942 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8944 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8945 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8946 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8948 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8951 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8953 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8956 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8958 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8961 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8963 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8966 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8968 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8969 tmp
&= ~(0xFF << 16);
8970 tmp
|= (0x1C << 16);
8971 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8973 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8974 tmp
&= ~(0xFF << 16);
8975 tmp
|= (0x1C << 16);
8976 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8978 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8980 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8982 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8984 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8986 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8987 tmp
&= ~(0xF << 28);
8989 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8991 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8992 tmp
&= ~(0xF << 28);
8994 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8997 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8998 * Programming" based on the parameters passed:
8999 * - Sequence to enable CLKOUT_DP
9000 * - Sequence to enable CLKOUT_DP without spread
9001 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9003 static void lpt_enable_clkout_dp(struct drm_i915_private
*dev_priv
,
9004 bool with_spread
, bool with_fdi
)
9008 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
9010 if (WARN(HAS_PCH_LPT_LP(dev_priv
) &&
9011 with_fdi
, "LP PCH doesn't have FDI\n"))
9014 mutex_lock(&dev_priv
->sb_lock
);
9016 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9017 tmp
&= ~SBI_SSCCTL_DISABLE
;
9018 tmp
|= SBI_SSCCTL_PATHALT
;
9019 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9024 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9025 tmp
&= ~SBI_SSCCTL_PATHALT
;
9026 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9029 lpt_reset_fdi_mphy(dev_priv
);
9030 lpt_program_fdi_mphy(dev_priv
);
9034 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
9035 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
9036 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
9037 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
9039 mutex_unlock(&dev_priv
->sb_lock
);
9042 /* Sequence to disable CLKOUT_DP */
9043 void lpt_disable_clkout_dp(struct drm_i915_private
*dev_priv
)
9047 mutex_lock(&dev_priv
->sb_lock
);
9049 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
9050 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
9051 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
9052 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
9054 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9055 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
9056 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
9057 tmp
|= SBI_SSCCTL_PATHALT
;
9058 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9061 tmp
|= SBI_SSCCTL_DISABLE
;
9062 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9065 mutex_unlock(&dev_priv
->sb_lock
);
9068 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9070 static const u16 sscdivintphase
[] = {
9071 [BEND_IDX( 50)] = 0x3B23,
9072 [BEND_IDX( 45)] = 0x3B23,
9073 [BEND_IDX( 40)] = 0x3C23,
9074 [BEND_IDX( 35)] = 0x3C23,
9075 [BEND_IDX( 30)] = 0x3D23,
9076 [BEND_IDX( 25)] = 0x3D23,
9077 [BEND_IDX( 20)] = 0x3E23,
9078 [BEND_IDX( 15)] = 0x3E23,
9079 [BEND_IDX( 10)] = 0x3F23,
9080 [BEND_IDX( 5)] = 0x3F23,
9081 [BEND_IDX( 0)] = 0x0025,
9082 [BEND_IDX( -5)] = 0x0025,
9083 [BEND_IDX(-10)] = 0x0125,
9084 [BEND_IDX(-15)] = 0x0125,
9085 [BEND_IDX(-20)] = 0x0225,
9086 [BEND_IDX(-25)] = 0x0225,
9087 [BEND_IDX(-30)] = 0x0325,
9088 [BEND_IDX(-35)] = 0x0325,
9089 [BEND_IDX(-40)] = 0x0425,
9090 [BEND_IDX(-45)] = 0x0425,
9091 [BEND_IDX(-50)] = 0x0525,
9096 * steps -50 to 50 inclusive, in steps of 5
9097 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9098 * change in clock period = -(steps / 10) * 5.787 ps
9100 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
9103 int idx
= BEND_IDX(steps
);
9105 if (WARN_ON(steps
% 5 != 0))
9108 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
9111 mutex_lock(&dev_priv
->sb_lock
);
9113 if (steps
% 10 != 0)
9117 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
9119 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
9121 tmp
|= sscdivintphase
[idx
];
9122 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
9124 mutex_unlock(&dev_priv
->sb_lock
);
9129 static void lpt_init_pch_refclk(struct drm_i915_private
*dev_priv
)
9131 struct intel_encoder
*encoder
;
9132 bool has_vga
= false;
9134 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
9135 switch (encoder
->type
) {
9136 case INTEL_OUTPUT_ANALOG
:
9145 lpt_bend_clkout_dp(dev_priv
, 0);
9146 lpt_enable_clkout_dp(dev_priv
, true, true);
9148 lpt_disable_clkout_dp(dev_priv
);
9153 * Initialize reference clocks when the driver loads
9155 void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
)
9157 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
))
9158 ironlake_init_pch_refclk(dev_priv
);
9159 else if (HAS_PCH_LPT(dev_priv
))
9160 lpt_init_pch_refclk(dev_priv
);
9163 static void ironlake_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
9165 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
9166 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9167 enum pipe pipe
= crtc
->pipe
;
9172 switch (crtc_state
->pipe_bpp
) {
9174 val
|= PIPECONF_6BPC
;
9177 val
|= PIPECONF_8BPC
;
9180 val
|= PIPECONF_10BPC
;
9183 val
|= PIPECONF_12BPC
;
9186 /* Case prevented by intel_choose_pipe_bpp_dither. */
9190 if (crtc_state
->dither
)
9191 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
9193 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
9194 val
|= PIPECONF_INTERLACED_ILK
;
9196 val
|= PIPECONF_PROGRESSIVE
;
9198 if (crtc_state
->limited_color_range
)
9199 val
|= PIPECONF_COLOR_RANGE_SELECT
;
9201 val
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
9203 I915_WRITE(PIPECONF(pipe
), val
);
9204 POSTING_READ(PIPECONF(pipe
));
9207 static void haswell_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
9209 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
9210 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9211 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
9214 if (IS_HASWELL(dev_priv
) && crtc_state
->dither
)
9215 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
9217 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
9218 val
|= PIPECONF_INTERLACED_ILK
;
9220 val
|= PIPECONF_PROGRESSIVE
;
9222 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
9223 POSTING_READ(PIPECONF(cpu_transcoder
));
9226 static void bdw_set_pipemisc(const struct intel_crtc_state
*crtc_state
)
9228 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
9229 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9232 switch (crtc_state
->pipe_bpp
) {
9234 val
|= PIPEMISC_DITHER_6_BPC
;
9237 val
|= PIPEMISC_DITHER_8_BPC
;
9240 val
|= PIPEMISC_DITHER_10_BPC
;
9243 val
|= PIPEMISC_DITHER_12_BPC
;
9246 MISSING_CASE(crtc_state
->pipe_bpp
);
9250 if (crtc_state
->dither
)
9251 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
9253 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
9254 crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
)
9255 val
|= PIPEMISC_OUTPUT_COLORSPACE_YUV
;
9257 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
9258 val
|= PIPEMISC_YUV420_ENABLE
|
9259 PIPEMISC_YUV420_MODE_FULL_BLEND
;
9261 if (INTEL_GEN(dev_priv
) >= 11 &&
9262 (crtc_state
->active_planes
& ~(icl_hdr_plane_mask() |
9263 BIT(PLANE_CURSOR
))) == 0)
9264 val
|= PIPEMISC_HDR_MODE_PRECISION
;
9266 I915_WRITE(PIPEMISC(crtc
->pipe
), val
);
9269 int bdw_get_pipemisc_bpp(struct intel_crtc
*crtc
)
9271 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9274 tmp
= I915_READ(PIPEMISC(crtc
->pipe
));
9276 switch (tmp
& PIPEMISC_DITHER_BPC_MASK
) {
9277 case PIPEMISC_DITHER_6_BPC
:
9279 case PIPEMISC_DITHER_8_BPC
:
9281 case PIPEMISC_DITHER_10_BPC
:
9283 case PIPEMISC_DITHER_12_BPC
:
9291 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
9294 * Account for spread spectrum to avoid
9295 * oversubscribing the link. Max center spread
9296 * is 2.5%; use 5% for safety's sake.
9298 u32 bps
= target_clock
* bpp
* 21 / 20;
9299 return DIV_ROUND_UP(bps
, link_bw
* 8);
9302 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
9304 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
9307 static void ironlake_compute_dpll(struct intel_crtc
*crtc
,
9308 struct intel_crtc_state
*crtc_state
,
9309 struct dpll
*reduced_clock
)
9311 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9315 /* Enable autotuning of the PLL clock (if permissible) */
9317 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9318 if ((intel_panel_use_ssc(dev_priv
) &&
9319 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
9320 (HAS_PCH_IBX(dev_priv
) &&
9321 intel_is_dual_link_lvds(dev_priv
)))
9323 } else if (crtc_state
->sdvo_tv_clock
) {
9327 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
9329 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
9332 if (reduced_clock
) {
9333 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
9335 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
9343 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
9344 dpll
|= DPLLB_MODE_LVDS
;
9346 dpll
|= DPLLB_MODE_DAC_SERIAL
;
9348 dpll
|= (crtc_state
->pixel_multiplier
- 1)
9349 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
9351 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
9352 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
9353 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9355 if (intel_crtc_has_dp_encoder(crtc_state
))
9356 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9359 * The high speed IO clock is only really required for
9360 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9361 * possible to share the DPLL between CRT and HDMI. Enabling
9362 * the clock needlessly does no real harm, except use up a
9363 * bit of power potentially.
9365 * We'll limit this to IVB with 3 pipes, since it has only two
9366 * DPLLs and so DPLL sharing is the only way to get three pipes
9367 * driving PCH ports at the same time. On SNB we could do this,
9368 * and potentially avoid enabling the second DPLL, but it's not
9369 * clear if it''s a win or loss power wise. No point in doing
9370 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9372 if (INTEL_INFO(dev_priv
)->num_pipes
== 3 &&
9373 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
))
9374 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9376 /* compute bitmask from p1 value */
9377 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
9379 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
9381 switch (crtc_state
->dpll
.p2
) {
9383 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
9386 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
9389 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
9392 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
9396 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9397 intel_panel_use_ssc(dev_priv
))
9398 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
9400 dpll
|= PLL_REF_INPUT_DREFCLK
;
9402 dpll
|= DPLL_VCO_ENABLE
;
9404 crtc_state
->dpll_hw_state
.dpll
= dpll
;
9405 crtc_state
->dpll_hw_state
.fp0
= fp
;
9406 crtc_state
->dpll_hw_state
.fp1
= fp2
;
9409 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
9410 struct intel_crtc_state
*crtc_state
)
9412 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9413 const struct intel_limit
*limit
;
9414 int refclk
= 120000;
9416 memset(&crtc_state
->dpll_hw_state
, 0,
9417 sizeof(crtc_state
->dpll_hw_state
));
9419 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9420 if (!crtc_state
->has_pch_encoder
)
9423 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9424 if (intel_panel_use_ssc(dev_priv
)) {
9425 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9426 dev_priv
->vbt
.lvds_ssc_freq
);
9427 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
9430 if (intel_is_dual_link_lvds(dev_priv
)) {
9431 if (refclk
== 100000)
9432 limit
= &intel_limits_ironlake_dual_lvds_100m
;
9434 limit
= &intel_limits_ironlake_dual_lvds
;
9436 if (refclk
== 100000)
9437 limit
= &intel_limits_ironlake_single_lvds_100m
;
9439 limit
= &intel_limits_ironlake_single_lvds
;
9442 limit
= &intel_limits_ironlake_dac
;
9445 if (!crtc_state
->clock_set
&&
9446 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
9447 refclk
, NULL
, &crtc_state
->dpll
)) {
9448 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9452 ironlake_compute_dpll(crtc
, crtc_state
, NULL
);
9454 if (!intel_get_shared_dpll(crtc_state
, NULL
)) {
9455 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9456 pipe_name(crtc
->pipe
));
9463 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9464 struct intel_link_m_n
*m_n
)
9466 struct drm_device
*dev
= crtc
->base
.dev
;
9467 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9468 enum pipe pipe
= crtc
->pipe
;
9470 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9471 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9472 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9474 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9475 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9476 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9479 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9480 enum transcoder transcoder
,
9481 struct intel_link_m_n
*m_n
,
9482 struct intel_link_m_n
*m2_n2
)
9484 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9485 enum pipe pipe
= crtc
->pipe
;
9487 if (INTEL_GEN(dev_priv
) >= 5) {
9488 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9489 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9490 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9492 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9493 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9494 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9496 if (m2_n2
&& transcoder_has_m2_n2(dev_priv
, transcoder
)) {
9497 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9498 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9499 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9501 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9502 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9503 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9506 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9507 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9508 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9510 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9511 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9512 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9516 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9517 struct intel_crtc_state
*pipe_config
)
9519 if (pipe_config
->has_pch_encoder
)
9520 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9522 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9523 &pipe_config
->dp_m_n
,
9524 &pipe_config
->dp_m2_n2
);
9527 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9528 struct intel_crtc_state
*pipe_config
)
9530 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9531 &pipe_config
->fdi_m_n
, NULL
);
9534 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9535 struct intel_crtc_state
*pipe_config
)
9537 struct drm_device
*dev
= crtc
->base
.dev
;
9538 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9539 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9544 /* find scaler attached to this pipe */
9545 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9546 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9547 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9549 pipe_config
->pch_pfit
.enabled
= true;
9550 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9551 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9552 scaler_state
->scalers
[i
].in_use
= true;
9557 scaler_state
->scaler_id
= id
;
9559 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9561 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9566 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9567 struct intel_initial_plane_config
*plane_config
)
9569 struct drm_device
*dev
= crtc
->base
.dev
;
9570 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9571 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
9572 enum plane_id plane_id
= plane
->id
;
9574 u32 val
, base
, offset
, stride_mult
, tiling
, alpha
;
9575 int fourcc
, pixel_format
;
9576 unsigned int aligned_height
;
9577 struct drm_framebuffer
*fb
;
9578 struct intel_framebuffer
*intel_fb
;
9580 if (!plane
->get_hw_state(plane
, &pipe
))
9583 WARN_ON(pipe
!= crtc
->pipe
);
9585 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9587 DRM_DEBUG_KMS("failed to alloc fb\n");
9591 fb
= &intel_fb
->base
;
9595 val
= I915_READ(PLANE_CTL(pipe
, plane_id
));
9597 if (INTEL_GEN(dev_priv
) >= 11)
9598 pixel_format
= val
& ICL_PLANE_CTL_FORMAT_MASK
;
9600 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9602 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)) {
9603 alpha
= I915_READ(PLANE_COLOR_CTL(pipe
, plane_id
));
9604 alpha
&= PLANE_COLOR_ALPHA_MASK
;
9606 alpha
= val
& PLANE_CTL_ALPHA_MASK
;
9609 fourcc
= skl_format_to_fourcc(pixel_format
,
9610 val
& PLANE_CTL_ORDER_RGBX
, alpha
);
9611 fb
->format
= drm_format_info(fourcc
);
9613 tiling
= val
& PLANE_CTL_TILED_MASK
;
9615 case PLANE_CTL_TILED_LINEAR
:
9616 fb
->modifier
= DRM_FORMAT_MOD_LINEAR
;
9618 case PLANE_CTL_TILED_X
:
9619 plane_config
->tiling
= I915_TILING_X
;
9620 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
9622 case PLANE_CTL_TILED_Y
:
9623 plane_config
->tiling
= I915_TILING_Y
;
9624 if (val
& PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
)
9625 fb
->modifier
= I915_FORMAT_MOD_Y_TILED_CCS
;
9627 fb
->modifier
= I915_FORMAT_MOD_Y_TILED
;
9629 case PLANE_CTL_TILED_YF
:
9630 if (val
& PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
)
9631 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED_CCS
;
9633 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED
;
9636 MISSING_CASE(tiling
);
9641 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9642 * while i915 HW rotation is clockwise, thats why this swapping.
9644 switch (val
& PLANE_CTL_ROTATE_MASK
) {
9645 case PLANE_CTL_ROTATE_0
:
9646 plane_config
->rotation
= DRM_MODE_ROTATE_0
;
9648 case PLANE_CTL_ROTATE_90
:
9649 plane_config
->rotation
= DRM_MODE_ROTATE_270
;
9651 case PLANE_CTL_ROTATE_180
:
9652 plane_config
->rotation
= DRM_MODE_ROTATE_180
;
9654 case PLANE_CTL_ROTATE_270
:
9655 plane_config
->rotation
= DRM_MODE_ROTATE_90
;
9659 if (INTEL_GEN(dev_priv
) >= 10 &&
9660 val
& PLANE_CTL_FLIP_HORIZONTAL
)
9661 plane_config
->rotation
|= DRM_MODE_REFLECT_X
;
9663 base
= I915_READ(PLANE_SURF(pipe
, plane_id
)) & 0xfffff000;
9664 plane_config
->base
= base
;
9666 offset
= I915_READ(PLANE_OFFSET(pipe
, plane_id
));
9668 val
= I915_READ(PLANE_SIZE(pipe
, plane_id
));
9669 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9670 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9672 val
= I915_READ(PLANE_STRIDE(pipe
, plane_id
));
9673 stride_mult
= skl_plane_stride_mult(fb
, 0, DRM_MODE_ROTATE_0
);
9674 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9676 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
9678 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9680 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9681 crtc
->base
.name
, plane
->base
.name
, fb
->width
, fb
->height
,
9682 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
9683 plane_config
->size
);
9685 plane_config
->fb
= intel_fb
;
9692 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9693 struct intel_crtc_state
*pipe_config
)
9695 struct drm_device
*dev
= crtc
->base
.dev
;
9696 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9699 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9701 if (tmp
& PF_ENABLE
) {
9702 pipe_config
->pch_pfit
.enabled
= true;
9703 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9704 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9706 /* We currently do not free assignements of panel fitters on
9707 * ivb/hsw (since we don't use the higher upscaling modes which
9708 * differentiates them) so just WARN about this case for now. */
9709 if (IS_GEN(dev_priv
, 7)) {
9710 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9711 PF_PIPE_SEL_IVB(crtc
->pipe
));
9716 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9717 struct intel_crtc_state
*pipe_config
)
9719 struct drm_device
*dev
= crtc
->base
.dev
;
9720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9721 enum intel_display_power_domain power_domain
;
9722 intel_wakeref_t wakeref
;
9726 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9727 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
9731 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
9732 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9733 pipe_config
->shared_dpll
= NULL
;
9736 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9737 if (!(tmp
& PIPECONF_ENABLE
))
9740 switch (tmp
& PIPECONF_BPC_MASK
) {
9742 pipe_config
->pipe_bpp
= 18;
9745 pipe_config
->pipe_bpp
= 24;
9747 case PIPECONF_10BPC
:
9748 pipe_config
->pipe_bpp
= 30;
9750 case PIPECONF_12BPC
:
9751 pipe_config
->pipe_bpp
= 36;
9757 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9758 pipe_config
->limited_color_range
= true;
9760 pipe_config
->gamma_mode
= (tmp
& PIPECONF_GAMMA_MODE_MASK_ILK
) >>
9761 PIPECONF_GAMMA_MODE_SHIFT
;
9763 pipe_config
->csc_mode
= I915_READ(PIPE_CSC_MODE(crtc
->pipe
));
9765 i9xx_get_pipe_color_config(pipe_config
);
9766 intel_color_get_config(pipe_config
);
9768 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9769 struct intel_shared_dpll
*pll
;
9770 enum intel_dpll_id pll_id
;
9772 pipe_config
->has_pch_encoder
= true;
9774 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9775 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9776 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9778 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9780 if (HAS_PCH_IBX(dev_priv
)) {
9782 * The pipe->pch transcoder and pch transcoder->pll
9785 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9787 tmp
= I915_READ(PCH_DPLL_SEL
);
9788 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9789 pll_id
= DPLL_ID_PCH_PLL_B
;
9791 pll_id
= DPLL_ID_PCH_PLL_A
;
9794 pipe_config
->shared_dpll
=
9795 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9796 pll
= pipe_config
->shared_dpll
;
9798 WARN_ON(!pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
9799 &pipe_config
->dpll_hw_state
));
9801 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9802 pipe_config
->pixel_multiplier
=
9803 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9804 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9806 ironlake_pch_clock_get(crtc
, pipe_config
);
9808 pipe_config
->pixel_multiplier
= 1;
9811 intel_get_pipe_timings(crtc
, pipe_config
);
9812 intel_get_pipe_src_size(crtc
, pipe_config
);
9814 ironlake_get_pfit_config(crtc
, pipe_config
);
9819 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
9823 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9824 struct intel_crtc_state
*crtc_state
)
9826 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9827 struct intel_atomic_state
*state
=
9828 to_intel_atomic_state(crtc_state
->base
.state
);
9830 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
) ||
9831 INTEL_GEN(dev_priv
) >= 11) {
9832 struct intel_encoder
*encoder
=
9833 intel_get_crtc_new_encoder(state
, crtc_state
);
9835 if (!intel_get_shared_dpll(crtc_state
, encoder
)) {
9836 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9837 pipe_name(crtc
->pipe
));
9845 static void cannonlake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9847 struct intel_crtc_state
*pipe_config
)
9849 enum intel_dpll_id id
;
9852 temp
= I915_READ(DPCLKA_CFGCR0
) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
9853 id
= temp
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port
);
9855 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL2
))
9858 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9861 static void icelake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9863 struct intel_crtc_state
*pipe_config
)
9865 enum intel_dpll_id id
;
9868 /* TODO: TBT pll not implemented. */
9869 if (intel_port_is_combophy(dev_priv
, port
)) {
9870 temp
= I915_READ(DPCLKA_CFGCR0_ICL
) &
9871 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
9872 id
= temp
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port
);
9873 } else if (intel_port_is_tc(dev_priv
, port
)) {
9874 id
= icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv
, port
));
9876 WARN(1, "Invalid port %x\n", port
);
9880 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9883 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9885 struct intel_crtc_state
*pipe_config
)
9887 enum intel_dpll_id id
;
9891 id
= DPLL_ID_SKL_DPLL0
;
9894 id
= DPLL_ID_SKL_DPLL1
;
9897 id
= DPLL_ID_SKL_DPLL2
;
9900 DRM_ERROR("Incorrect port type\n");
9904 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9907 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9909 struct intel_crtc_state
*pipe_config
)
9911 enum intel_dpll_id id
;
9914 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9915 id
= temp
>> (port
* 3 + 1);
9917 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL3
))
9920 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9923 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9925 struct intel_crtc_state
*pipe_config
)
9927 enum intel_dpll_id id
;
9928 u32 ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9930 switch (ddi_pll_sel
) {
9931 case PORT_CLK_SEL_WRPLL1
:
9932 id
= DPLL_ID_WRPLL1
;
9934 case PORT_CLK_SEL_WRPLL2
:
9935 id
= DPLL_ID_WRPLL2
;
9937 case PORT_CLK_SEL_SPLL
:
9940 case PORT_CLK_SEL_LCPLL_810
:
9941 id
= DPLL_ID_LCPLL_810
;
9943 case PORT_CLK_SEL_LCPLL_1350
:
9944 id
= DPLL_ID_LCPLL_1350
;
9946 case PORT_CLK_SEL_LCPLL_2700
:
9947 id
= DPLL_ID_LCPLL_2700
;
9950 MISSING_CASE(ddi_pll_sel
);
9952 case PORT_CLK_SEL_NONE
:
9956 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9959 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9960 struct intel_crtc_state
*pipe_config
,
9961 u64
*power_domain_mask
,
9962 intel_wakeref_t
*wakerefs
)
9964 struct drm_device
*dev
= crtc
->base
.dev
;
9965 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9966 enum intel_display_power_domain power_domain
;
9967 unsigned long panel_transcoder_mask
= 0;
9968 unsigned long enabled_panel_transcoders
= 0;
9969 enum transcoder panel_transcoder
;
9973 if (INTEL_GEN(dev_priv
) >= 11)
9974 panel_transcoder_mask
|=
9975 BIT(TRANSCODER_DSI_0
) | BIT(TRANSCODER_DSI_1
);
9977 if (HAS_TRANSCODER_EDP(dev_priv
))
9978 panel_transcoder_mask
|= BIT(TRANSCODER_EDP
);
9981 * The pipe->transcoder mapping is fixed with the exception of the eDP
9982 * and DSI transcoders handled below.
9984 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9987 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9988 * consistency and less surprising code; it's in always on power).
9990 for_each_set_bit(panel_transcoder
,
9991 &panel_transcoder_mask
,
9992 ARRAY_SIZE(INTEL_INFO(dev_priv
)->trans_offsets
)) {
9993 bool force_thru
= false;
9994 enum pipe trans_pipe
;
9996 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder
));
9997 if (!(tmp
& TRANS_DDI_FUNC_ENABLE
))
10001 * Log all enabled ones, only use the first one.
10003 * FIXME: This won't work for two separate DSI displays.
10005 enabled_panel_transcoders
|= BIT(panel_transcoder
);
10006 if (enabled_panel_transcoders
!= BIT(panel_transcoder
))
10009 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
10011 WARN(1, "unknown pipe linked to transcoder %s\n",
10012 transcoder_name(panel_transcoder
));
10014 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
10017 case TRANS_DDI_EDP_INPUT_A_ON
:
10018 trans_pipe
= PIPE_A
;
10020 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
10021 trans_pipe
= PIPE_B
;
10023 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
10024 trans_pipe
= PIPE_C
;
10028 if (trans_pipe
== crtc
->pipe
) {
10029 pipe_config
->cpu_transcoder
= panel_transcoder
;
10030 pipe_config
->pch_pfit
.force_thru
= force_thru
;
10035 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10037 WARN_ON((enabled_panel_transcoders
& BIT(TRANSCODER_EDP
)) &&
10038 enabled_panel_transcoders
!= BIT(TRANSCODER_EDP
));
10040 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
10041 WARN_ON(*power_domain_mask
& BIT_ULL(power_domain
));
10043 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10047 wakerefs
[power_domain
] = wf
;
10048 *power_domain_mask
|= BIT_ULL(power_domain
);
10050 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
10052 return tmp
& PIPECONF_ENABLE
;
10055 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
10056 struct intel_crtc_state
*pipe_config
,
10057 u64
*power_domain_mask
,
10058 intel_wakeref_t
*wakerefs
)
10060 struct drm_device
*dev
= crtc
->base
.dev
;
10061 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10062 enum intel_display_power_domain power_domain
;
10063 enum transcoder cpu_transcoder
;
10064 intel_wakeref_t wf
;
10068 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
10069 if (port
== PORT_A
)
10070 cpu_transcoder
= TRANSCODER_DSI_A
;
10072 cpu_transcoder
= TRANSCODER_DSI_C
;
10074 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
10075 WARN_ON(*power_domain_mask
& BIT_ULL(power_domain
));
10077 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10081 wakerefs
[power_domain
] = wf
;
10082 *power_domain_mask
|= BIT_ULL(power_domain
);
10085 * The PLL needs to be enabled with a valid divider
10086 * configuration, otherwise accessing DSI registers will hang
10087 * the machine. See BSpec North Display Engine
10088 * registers/MIPI[BXT]. We can break out here early, since we
10089 * need the same DSI PLL to be enabled for both DSI ports.
10091 if (!bxt_dsi_pll_is_enabled(dev_priv
))
10094 /* XXX: this works for video mode only */
10095 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
10096 if (!(tmp
& DPI_ENABLE
))
10099 tmp
= I915_READ(MIPI_CTRL(port
));
10100 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
10103 pipe_config
->cpu_transcoder
= cpu_transcoder
;
10107 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
10110 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
10111 struct intel_crtc_state
*pipe_config
)
10113 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10114 struct intel_shared_dpll
*pll
;
10118 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
10120 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
10122 if (INTEL_GEN(dev_priv
) >= 11)
10123 icelake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10124 else if (IS_CANNONLAKE(dev_priv
))
10125 cannonlake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10126 else if (IS_GEN9_BC(dev_priv
))
10127 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10128 else if (IS_GEN9_LP(dev_priv
))
10129 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
10131 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
10133 pll
= pipe_config
->shared_dpll
;
10135 WARN_ON(!pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
10136 &pipe_config
->dpll_hw_state
));
10140 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10141 * DDI E. So just check whether this pipe is wired to DDI E and whether
10142 * the PCH transcoder is on.
10144 if (INTEL_GEN(dev_priv
) < 9 &&
10145 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
10146 pipe_config
->has_pch_encoder
= true;
10148 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
10149 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
10150 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
10152 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
10156 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
10157 struct intel_crtc_state
*pipe_config
)
10159 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10160 intel_wakeref_t wakerefs
[POWER_DOMAIN_NUM
], wf
;
10161 enum intel_display_power_domain power_domain
;
10162 u64 power_domain_mask
;
10165 intel_crtc_init_scalers(crtc
, pipe_config
);
10167 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
10168 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10172 wakerefs
[power_domain
] = wf
;
10173 power_domain_mask
= BIT_ULL(power_domain
);
10175 pipe_config
->shared_dpll
= NULL
;
10177 active
= hsw_get_transcoder_state(crtc
, pipe_config
,
10178 &power_domain_mask
, wakerefs
);
10180 if (IS_GEN9_LP(dev_priv
) &&
10181 bxt_get_dsi_transcoder_state(crtc
, pipe_config
,
10182 &power_domain_mask
, wakerefs
)) {
10190 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
) ||
10191 INTEL_GEN(dev_priv
) >= 11) {
10192 haswell_get_ddi_port_state(crtc
, pipe_config
);
10193 intel_get_pipe_timings(crtc
, pipe_config
);
10196 intel_get_pipe_src_size(crtc
, pipe_config
);
10197 intel_get_crtc_ycbcr_config(crtc
, pipe_config
);
10199 pipe_config
->gamma_mode
= I915_READ(GAMMA_MODE(crtc
->pipe
));
10201 pipe_config
->csc_mode
= I915_READ(PIPE_CSC_MODE(crtc
->pipe
));
10203 if (INTEL_GEN(dev_priv
) >= 9) {
10204 u32 tmp
= I915_READ(SKL_BOTTOM_COLOR(crtc
->pipe
));
10206 if (tmp
& SKL_BOTTOM_COLOR_GAMMA_ENABLE
)
10207 pipe_config
->gamma_enable
= true;
10209 if (tmp
& SKL_BOTTOM_COLOR_CSC_ENABLE
)
10210 pipe_config
->csc_enable
= true;
10212 i9xx_get_pipe_color_config(pipe_config
);
10215 intel_color_get_config(pipe_config
);
10217 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10218 WARN_ON(power_domain_mask
& BIT_ULL(power_domain
));
10220 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10222 wakerefs
[power_domain
] = wf
;
10223 power_domain_mask
|= BIT_ULL(power_domain
);
10225 if (INTEL_GEN(dev_priv
) >= 9)
10226 skylake_get_pfit_config(crtc
, pipe_config
);
10228 ironlake_get_pfit_config(crtc
, pipe_config
);
10231 if (hsw_crtc_supports_ips(crtc
)) {
10232 if (IS_HASWELL(dev_priv
))
10233 pipe_config
->ips_enabled
= I915_READ(IPS_CTL
) & IPS_ENABLE
;
10236 * We cannot readout IPS state on broadwell, set to
10237 * true so we can set it to a defined state on first
10240 pipe_config
->ips_enabled
= true;
10244 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10245 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10246 pipe_config
->pixel_multiplier
=
10247 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10249 pipe_config
->pixel_multiplier
= 1;
10253 for_each_power_domain(power_domain
, power_domain_mask
)
10254 intel_display_power_put(dev_priv
,
10255 power_domain
, wakerefs
[power_domain
]);
10260 static u32
intel_cursor_base(const struct intel_plane_state
*plane_state
)
10262 struct drm_i915_private
*dev_priv
=
10263 to_i915(plane_state
->base
.plane
->dev
);
10264 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10265 const struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10268 if (INTEL_INFO(dev_priv
)->display
.cursor_needs_physical
)
10269 base
= obj
->phys_handle
->busaddr
;
10271 base
= intel_plane_ggtt_offset(plane_state
);
10273 base
+= plane_state
->color_plane
[0].offset
;
10275 /* ILK+ do this automagically */
10276 if (HAS_GMCH(dev_priv
) &&
10277 plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
10278 base
+= (plane_state
->base
.crtc_h
*
10279 plane_state
->base
.crtc_w
- 1) * fb
->format
->cpp
[0];
10284 static u32
intel_cursor_position(const struct intel_plane_state
*plane_state
)
10286 int x
= plane_state
->base
.crtc_x
;
10287 int y
= plane_state
->base
.crtc_y
;
10291 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10294 pos
|= x
<< CURSOR_X_SHIFT
;
10297 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10300 pos
|= y
<< CURSOR_Y_SHIFT
;
10305 static bool intel_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10307 const struct drm_mode_config
*config
=
10308 &plane_state
->base
.plane
->dev
->mode_config
;
10309 int width
= plane_state
->base
.crtc_w
;
10310 int height
= plane_state
->base
.crtc_h
;
10312 return width
> 0 && width
<= config
->cursor_width
&&
10313 height
> 0 && height
<= config
->cursor_height
;
10316 static int intel_cursor_check_surface(struct intel_plane_state
*plane_state
)
10322 ret
= intel_plane_compute_gtt(plane_state
);
10326 if (!plane_state
->base
.visible
)
10329 src_x
= plane_state
->base
.src_x
>> 16;
10330 src_y
= plane_state
->base
.src_y
>> 16;
10332 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
10333 offset
= intel_plane_compute_aligned_offset(&src_x
, &src_y
,
10336 if (src_x
!= 0 || src_y
!= 0) {
10337 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10341 plane_state
->color_plane
[0].offset
= offset
;
10346 static int intel_check_cursor(struct intel_crtc_state
*crtc_state
,
10347 struct intel_plane_state
*plane_state
)
10349 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10352 if (fb
&& fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
10353 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10357 ret
= drm_atomic_helper_check_plane_state(&plane_state
->base
,
10359 DRM_PLANE_HELPER_NO_SCALING
,
10360 DRM_PLANE_HELPER_NO_SCALING
,
10365 ret
= intel_cursor_check_surface(plane_state
);
10369 if (!plane_state
->base
.visible
)
10372 ret
= intel_plane_check_src_coordinates(plane_state
);
10379 static unsigned int
10380 i845_cursor_max_stride(struct intel_plane
*plane
,
10381 u32 pixel_format
, u64 modifier
,
10382 unsigned int rotation
)
10387 static u32
i845_cursor_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
10391 if (crtc_state
->gamma_enable
)
10392 cntl
|= CURSOR_GAMMA_ENABLE
;
10397 static u32
i845_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
10398 const struct intel_plane_state
*plane_state
)
10400 return CURSOR_ENABLE
|
10401 CURSOR_FORMAT_ARGB
|
10402 CURSOR_STRIDE(plane_state
->color_plane
[0].stride
);
10405 static bool i845_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10407 int width
= plane_state
->base
.crtc_w
;
10410 * 845g/865g are only limited by the width of their cursors,
10411 * the height is arbitrary up to the precision of the register.
10413 return intel_cursor_size_ok(plane_state
) && IS_ALIGNED(width
, 64);
10416 static int i845_check_cursor(struct intel_crtc_state
*crtc_state
,
10417 struct intel_plane_state
*plane_state
)
10419 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10422 ret
= intel_check_cursor(crtc_state
, plane_state
);
10426 /* if we want to turn off the cursor ignore width and height */
10430 /* Check for which cursor types we support */
10431 if (!i845_cursor_size_ok(plane_state
)) {
10432 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10433 plane_state
->base
.crtc_w
,
10434 plane_state
->base
.crtc_h
);
10438 WARN_ON(plane_state
->base
.visible
&&
10439 plane_state
->color_plane
[0].stride
!= fb
->pitches
[0]);
10441 switch (fb
->pitches
[0]) {
10448 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10453 plane_state
->ctl
= i845_cursor_ctl(crtc_state
, plane_state
);
10458 static void i845_update_cursor(struct intel_plane
*plane
,
10459 const struct intel_crtc_state
*crtc_state
,
10460 const struct intel_plane_state
*plane_state
)
10462 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10463 u32 cntl
= 0, base
= 0, pos
= 0, size
= 0;
10464 unsigned long irqflags
;
10466 if (plane_state
&& plane_state
->base
.visible
) {
10467 unsigned int width
= plane_state
->base
.crtc_w
;
10468 unsigned int height
= plane_state
->base
.crtc_h
;
10470 cntl
= plane_state
->ctl
|
10471 i845_cursor_ctl_crtc(crtc_state
);
10473 size
= (height
<< 12) | width
;
10475 base
= intel_cursor_base(plane_state
);
10476 pos
= intel_cursor_position(plane_state
);
10479 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
10481 /* On these chipsets we can only modify the base/size/stride
10482 * whilst the cursor is disabled.
10484 if (plane
->cursor
.base
!= base
||
10485 plane
->cursor
.size
!= size
||
10486 plane
->cursor
.cntl
!= cntl
) {
10487 I915_WRITE_FW(CURCNTR(PIPE_A
), 0);
10488 I915_WRITE_FW(CURBASE(PIPE_A
), base
);
10489 I915_WRITE_FW(CURSIZE
, size
);
10490 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
10491 I915_WRITE_FW(CURCNTR(PIPE_A
), cntl
);
10493 plane
->cursor
.base
= base
;
10494 plane
->cursor
.size
= size
;
10495 plane
->cursor
.cntl
= cntl
;
10497 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
10500 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
10503 static void i845_disable_cursor(struct intel_plane
*plane
,
10504 const struct intel_crtc_state
*crtc_state
)
10506 i845_update_cursor(plane
, crtc_state
, NULL
);
10509 static bool i845_cursor_get_hw_state(struct intel_plane
*plane
,
10512 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10513 enum intel_display_power_domain power_domain
;
10514 intel_wakeref_t wakeref
;
10517 power_domain
= POWER_DOMAIN_PIPE(PIPE_A
);
10518 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10522 ret
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
10526 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
10531 static unsigned int
10532 i9xx_cursor_max_stride(struct intel_plane
*plane
,
10533 u32 pixel_format
, u64 modifier
,
10534 unsigned int rotation
)
10536 return plane
->base
.dev
->mode_config
.cursor_width
* 4;
10539 static u32
i9xx_cursor_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
10541 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
10542 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10545 if (INTEL_GEN(dev_priv
) >= 11)
10548 if (crtc_state
->gamma_enable
)
10549 cntl
= MCURSOR_GAMMA_ENABLE
;
10551 if (crtc_state
->csc_enable
)
10552 cntl
|= MCURSOR_PIPE_CSC_ENABLE
;
10554 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
10555 cntl
|= MCURSOR_PIPE_SELECT(crtc
->pipe
);
10560 static u32
i9xx_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
10561 const struct intel_plane_state
*plane_state
)
10563 struct drm_i915_private
*dev_priv
=
10564 to_i915(plane_state
->base
.plane
->dev
);
10567 if (IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
))
10568 cntl
|= MCURSOR_TRICKLE_FEED_DISABLE
;
10570 switch (plane_state
->base
.crtc_w
) {
10572 cntl
|= MCURSOR_MODE_64_ARGB_AX
;
10575 cntl
|= MCURSOR_MODE_128_ARGB_AX
;
10578 cntl
|= MCURSOR_MODE_256_ARGB_AX
;
10581 MISSING_CASE(plane_state
->base
.crtc_w
);
10585 if (plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
10586 cntl
|= MCURSOR_ROTATE_180
;
10591 static bool i9xx_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10593 struct drm_i915_private
*dev_priv
=
10594 to_i915(plane_state
->base
.plane
->dev
);
10595 int width
= plane_state
->base
.crtc_w
;
10596 int height
= plane_state
->base
.crtc_h
;
10598 if (!intel_cursor_size_ok(plane_state
))
10601 /* Cursor width is limited to a few power-of-two sizes */
10612 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10613 * height from 8 lines up to the cursor width, when the
10614 * cursor is not rotated. Everything else requires square
10617 if (HAS_CUR_FBC(dev_priv
) &&
10618 plane_state
->base
.rotation
& DRM_MODE_ROTATE_0
) {
10619 if (height
< 8 || height
> width
)
10622 if (height
!= width
)
10629 static int i9xx_check_cursor(struct intel_crtc_state
*crtc_state
,
10630 struct intel_plane_state
*plane_state
)
10632 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
10633 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10634 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10635 enum pipe pipe
= plane
->pipe
;
10638 ret
= intel_check_cursor(crtc_state
, plane_state
);
10642 /* if we want to turn off the cursor ignore width and height */
10646 /* Check for which cursor types we support */
10647 if (!i9xx_cursor_size_ok(plane_state
)) {
10648 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10649 plane_state
->base
.crtc_w
,
10650 plane_state
->base
.crtc_h
);
10654 WARN_ON(plane_state
->base
.visible
&&
10655 plane_state
->color_plane
[0].stride
!= fb
->pitches
[0]);
10657 if (fb
->pitches
[0] != plane_state
->base
.crtc_w
* fb
->format
->cpp
[0]) {
10658 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10659 fb
->pitches
[0], plane_state
->base
.crtc_w
);
10664 * There's something wrong with the cursor on CHV pipe C.
10665 * If it straddles the left edge of the screen then
10666 * moving it away from the edge or disabling it often
10667 * results in a pipe underrun, and often that can lead to
10668 * dead pipe (constant underrun reported, and it scans
10669 * out just a solid color). To recover from that, the
10670 * display power well must be turned off and on again.
10671 * Refuse the put the cursor into that compromised position.
10673 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_C
&&
10674 plane_state
->base
.visible
&& plane_state
->base
.crtc_x
< 0) {
10675 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10679 plane_state
->ctl
= i9xx_cursor_ctl(crtc_state
, plane_state
);
10684 static void i9xx_update_cursor(struct intel_plane
*plane
,
10685 const struct intel_crtc_state
*crtc_state
,
10686 const struct intel_plane_state
*plane_state
)
10688 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10689 enum pipe pipe
= plane
->pipe
;
10690 u32 cntl
= 0, base
= 0, pos
= 0, fbc_ctl
= 0;
10691 unsigned long irqflags
;
10693 if (plane_state
&& plane_state
->base
.visible
) {
10694 cntl
= plane_state
->ctl
|
10695 i9xx_cursor_ctl_crtc(crtc_state
);
10697 if (plane_state
->base
.crtc_h
!= plane_state
->base
.crtc_w
)
10698 fbc_ctl
= CUR_FBC_CTL_EN
| (plane_state
->base
.crtc_h
- 1);
10700 base
= intel_cursor_base(plane_state
);
10701 pos
= intel_cursor_position(plane_state
);
10704 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
10707 * On some platforms writing CURCNTR first will also
10708 * cause CURPOS to be armed by the CURBASE write.
10709 * Without the CURCNTR write the CURPOS write would
10710 * arm itself. Thus we always update CURCNTR before
10713 * On other platforms CURPOS always requires the
10714 * CURBASE write to arm the update. Additonally
10715 * a write to any of the cursor register will cancel
10716 * an already armed cursor update. Thus leaving out
10717 * the CURBASE write after CURPOS could lead to a
10718 * cursor that doesn't appear to move, or even change
10719 * shape. Thus we always write CURBASE.
10721 * The other registers are armed by by the CURBASE write
10722 * except when the plane is getting enabled at which time
10723 * the CURCNTR write arms the update.
10726 if (INTEL_GEN(dev_priv
) >= 9)
10727 skl_write_cursor_wm(plane
, crtc_state
);
10729 if (plane
->cursor
.base
!= base
||
10730 plane
->cursor
.size
!= fbc_ctl
||
10731 plane
->cursor
.cntl
!= cntl
) {
10732 if (HAS_CUR_FBC(dev_priv
))
10733 I915_WRITE_FW(CUR_FBC_CTL(pipe
), fbc_ctl
);
10734 I915_WRITE_FW(CURCNTR(pipe
), cntl
);
10735 I915_WRITE_FW(CURPOS(pipe
), pos
);
10736 I915_WRITE_FW(CURBASE(pipe
), base
);
10738 plane
->cursor
.base
= base
;
10739 plane
->cursor
.size
= fbc_ctl
;
10740 plane
->cursor
.cntl
= cntl
;
10742 I915_WRITE_FW(CURPOS(pipe
), pos
);
10743 I915_WRITE_FW(CURBASE(pipe
), base
);
10746 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
10749 static void i9xx_disable_cursor(struct intel_plane
*plane
,
10750 const struct intel_crtc_state
*crtc_state
)
10752 i9xx_update_cursor(plane
, crtc_state
, NULL
);
10755 static bool i9xx_cursor_get_hw_state(struct intel_plane
*plane
,
10758 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10759 enum intel_display_power_domain power_domain
;
10760 intel_wakeref_t wakeref
;
10765 * Not 100% correct for planes that can move between pipes,
10766 * but that's only the case for gen2-3 which don't have any
10767 * display power wells.
10769 power_domain
= POWER_DOMAIN_PIPE(plane
->pipe
);
10770 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10774 val
= I915_READ(CURCNTR(plane
->pipe
));
10776 ret
= val
& MCURSOR_MODE
;
10778 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
10779 *pipe
= plane
->pipe
;
10781 *pipe
= (val
& MCURSOR_PIPE_SELECT_MASK
) >>
10782 MCURSOR_PIPE_SELECT_SHIFT
;
10784 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
10789 /* VESA 640x480x72Hz mode to set on the pipe */
10790 static const struct drm_display_mode load_detect_mode
= {
10791 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10792 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10795 struct drm_framebuffer
*
10796 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
10797 struct drm_mode_fb_cmd2
*mode_cmd
)
10799 struct intel_framebuffer
*intel_fb
;
10802 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10804 return ERR_PTR(-ENOMEM
);
10806 ret
= intel_framebuffer_init(intel_fb
, obj
, mode_cmd
);
10810 return &intel_fb
->base
;
10814 return ERR_PTR(ret
);
10817 static int intel_modeset_disable_planes(struct drm_atomic_state
*state
,
10818 struct drm_crtc
*crtc
)
10820 struct drm_plane
*plane
;
10821 struct drm_plane_state
*plane_state
;
10824 ret
= drm_atomic_add_affected_planes(state
, crtc
);
10828 for_each_new_plane_in_state(state
, plane
, plane_state
, i
) {
10829 if (plane_state
->crtc
!= crtc
)
10832 ret
= drm_atomic_set_crtc_for_plane(plane_state
, NULL
);
10836 drm_atomic_set_fb_for_plane(plane_state
, NULL
);
10842 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
10843 const struct drm_display_mode
*mode
,
10844 struct intel_load_detect_pipe
*old
,
10845 struct drm_modeset_acquire_ctx
*ctx
)
10847 struct intel_crtc
*intel_crtc
;
10848 struct intel_encoder
*intel_encoder
=
10849 intel_attached_encoder(connector
);
10850 struct drm_crtc
*possible_crtc
;
10851 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10852 struct drm_crtc
*crtc
= NULL
;
10853 struct drm_device
*dev
= encoder
->dev
;
10854 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10855 struct drm_mode_config
*config
= &dev
->mode_config
;
10856 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
10857 struct drm_connector_state
*connector_state
;
10858 struct intel_crtc_state
*crtc_state
;
10861 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10862 connector
->base
.id
, connector
->name
,
10863 encoder
->base
.id
, encoder
->name
);
10865 old
->restore_state
= NULL
;
10867 WARN_ON(!drm_modeset_is_locked(&config
->connection_mutex
));
10870 * Algorithm gets a little messy:
10872 * - if the connector already has an assigned crtc, use it (but make
10873 * sure it's on first)
10875 * - try to find the first unused crtc that can drive this connector,
10876 * and use that if we find one
10879 /* See if we already have a CRTC for this connector */
10880 if (connector
->state
->crtc
) {
10881 crtc
= connector
->state
->crtc
;
10883 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10887 /* Make sure the crtc and connector are running */
10891 /* Find an unused one (if possible) */
10892 for_each_crtc(dev
, possible_crtc
) {
10894 if (!(encoder
->possible_crtcs
& (1 << i
)))
10897 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
10901 if (possible_crtc
->state
->enable
) {
10902 drm_modeset_unlock(&possible_crtc
->mutex
);
10906 crtc
= possible_crtc
;
10911 * If we didn't find an unused CRTC, don't use any.
10914 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10920 intel_crtc
= to_intel_crtc(crtc
);
10922 state
= drm_atomic_state_alloc(dev
);
10923 restore_state
= drm_atomic_state_alloc(dev
);
10924 if (!state
|| !restore_state
) {
10929 state
->acquire_ctx
= ctx
;
10930 restore_state
->acquire_ctx
= ctx
;
10932 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10933 if (IS_ERR(connector_state
)) {
10934 ret
= PTR_ERR(connector_state
);
10938 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
10942 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10943 if (IS_ERR(crtc_state
)) {
10944 ret
= PTR_ERR(crtc_state
);
10948 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10951 mode
= &load_detect_mode
;
10953 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10957 ret
= intel_modeset_disable_planes(state
, crtc
);
10961 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10963 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10965 ret
= drm_atomic_add_affected_planes(restore_state
, crtc
);
10967 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10971 ret
= drm_atomic_commit(state
);
10973 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10977 old
->restore_state
= restore_state
;
10978 drm_atomic_state_put(state
);
10980 /* let the connector get through one full cycle before testing */
10981 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
10986 drm_atomic_state_put(state
);
10989 if (restore_state
) {
10990 drm_atomic_state_put(restore_state
);
10991 restore_state
= NULL
;
10994 if (ret
== -EDEADLK
)
11000 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
11001 struct intel_load_detect_pipe
*old
,
11002 struct drm_modeset_acquire_ctx
*ctx
)
11004 struct intel_encoder
*intel_encoder
=
11005 intel_attached_encoder(connector
);
11006 struct drm_encoder
*encoder
= &intel_encoder
->base
;
11007 struct drm_atomic_state
*state
= old
->restore_state
;
11010 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11011 connector
->base
.id
, connector
->name
,
11012 encoder
->base
.id
, encoder
->name
);
11017 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
11019 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
11020 drm_atomic_state_put(state
);
11023 static int i9xx_pll_refclk(struct drm_device
*dev
,
11024 const struct intel_crtc_state
*pipe_config
)
11026 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11027 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
11029 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
11030 return dev_priv
->vbt
.lvds_ssc_freq
;
11031 else if (HAS_PCH_SPLIT(dev_priv
))
11033 else if (!IS_GEN(dev_priv
, 2))
11039 /* Returns the clock of the currently programmed mode of the given pipe. */
11040 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
11041 struct intel_crtc_state
*pipe_config
)
11043 struct drm_device
*dev
= crtc
->base
.dev
;
11044 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11045 int pipe
= pipe_config
->cpu_transcoder
;
11046 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
11050 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
11052 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
11053 fp
= pipe_config
->dpll_hw_state
.fp0
;
11055 fp
= pipe_config
->dpll_hw_state
.fp1
;
11057 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
11058 if (IS_PINEVIEW(dev_priv
)) {
11059 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
11060 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
11062 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
11063 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
11066 if (!IS_GEN(dev_priv
, 2)) {
11067 if (IS_PINEVIEW(dev_priv
))
11068 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
11069 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
11071 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
11072 DPLL_FPA01_P1_POST_DIV_SHIFT
);
11074 switch (dpll
& DPLL_MODE_MASK
) {
11075 case DPLLB_MODE_DAC_SERIAL
:
11076 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
11079 case DPLLB_MODE_LVDS
:
11080 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
11084 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11085 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
11089 if (IS_PINEVIEW(dev_priv
))
11090 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
11092 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
11094 u32 lvds
= IS_I830(dev_priv
) ? 0 : I915_READ(LVDS
);
11095 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
11098 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
11099 DPLL_FPA01_P1_POST_DIV_SHIFT
);
11101 if (lvds
& LVDS_CLKB_POWER_UP
)
11106 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
11109 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
11110 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
11112 if (dpll
& PLL_P2_DIVIDE_BY_4
)
11118 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
11122 * This value includes pixel_multiplier. We will use
11123 * port_clock to compute adjusted_mode.crtc_clock in the
11124 * encoder's get_config() function.
11126 pipe_config
->port_clock
= port_clock
;
11129 int intel_dotclock_calculate(int link_freq
,
11130 const struct intel_link_m_n
*m_n
)
11133 * The calculation for the data clock is:
11134 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11135 * But we want to avoid losing precison if possible, so:
11136 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11138 * and the link clock is simpler:
11139 * link_clock = (m * link_clock) / n
11145 return div_u64(mul_u32_u32(m_n
->link_m
, link_freq
), m_n
->link_n
);
11148 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
11149 struct intel_crtc_state
*pipe_config
)
11151 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11153 /* read out port_clock from the DPLL */
11154 i9xx_crtc_clock_get(crtc
, pipe_config
);
11157 * In case there is an active pipe without active ports,
11158 * we may need some idea for the dotclock anyway.
11159 * Calculate one based on the FDI configuration.
11161 pipe_config
->base
.adjusted_mode
.crtc_clock
=
11162 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
11163 &pipe_config
->fdi_m_n
);
11166 /* Returns the currently programmed mode of the given encoder. */
11167 struct drm_display_mode
*
11168 intel_encoder_current_mode(struct intel_encoder
*encoder
)
11170 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
11171 struct intel_crtc_state
*crtc_state
;
11172 struct drm_display_mode
*mode
;
11173 struct intel_crtc
*crtc
;
11176 if (!encoder
->get_hw_state(encoder
, &pipe
))
11179 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
11181 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
11185 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
11191 crtc_state
->base
.crtc
= &crtc
->base
;
11193 if (!dev_priv
->display
.get_pipe_config(crtc
, crtc_state
)) {
11199 encoder
->get_config(encoder
, crtc_state
);
11201 intel_mode_from_pipe_config(mode
, crtc_state
);
11208 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
11210 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11212 drm_crtc_cleanup(crtc
);
11217 * intel_wm_need_update - Check whether watermarks need updating
11218 * @cur: current plane state
11219 * @new: new plane state
11221 * Check current plane state versus the new one to determine whether
11222 * watermarks need to be recalculated.
11224 * Returns true or false.
11226 static bool intel_wm_need_update(struct intel_plane_state
*cur
,
11227 struct intel_plane_state
*new)
11229 /* Update watermarks on tiling or size changes. */
11230 if (new->base
.visible
!= cur
->base
.visible
)
11233 if (!cur
->base
.fb
|| !new->base
.fb
)
11236 if (cur
->base
.fb
->modifier
!= new->base
.fb
->modifier
||
11237 cur
->base
.rotation
!= new->base
.rotation
||
11238 drm_rect_width(&new->base
.src
) != drm_rect_width(&cur
->base
.src
) ||
11239 drm_rect_height(&new->base
.src
) != drm_rect_height(&cur
->base
.src
) ||
11240 drm_rect_width(&new->base
.dst
) != drm_rect_width(&cur
->base
.dst
) ||
11241 drm_rect_height(&new->base
.dst
) != drm_rect_height(&cur
->base
.dst
))
11247 static bool needs_scaling(const struct intel_plane_state
*state
)
11249 int src_w
= drm_rect_width(&state
->base
.src
) >> 16;
11250 int src_h
= drm_rect_height(&state
->base
.src
) >> 16;
11251 int dst_w
= drm_rect_width(&state
->base
.dst
);
11252 int dst_h
= drm_rect_height(&state
->base
.dst
);
11254 return (src_w
!= dst_w
|| src_h
!= dst_h
);
11257 int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state
,
11258 struct drm_crtc_state
*crtc_state
,
11259 const struct intel_plane_state
*old_plane_state
,
11260 struct drm_plane_state
*plane_state
)
11262 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
11263 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11264 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11265 struct intel_plane
*plane
= to_intel_plane(plane_state
->plane
);
11266 struct drm_device
*dev
= crtc
->dev
;
11267 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11268 bool mode_changed
= needs_modeset(crtc_state
);
11269 bool was_crtc_enabled
= old_crtc_state
->base
.active
;
11270 bool is_crtc_enabled
= crtc_state
->active
;
11271 bool turn_off
, turn_on
, visible
, was_visible
;
11272 struct drm_framebuffer
*fb
= plane_state
->fb
;
11275 if (INTEL_GEN(dev_priv
) >= 9 && plane
->id
!= PLANE_CURSOR
) {
11276 ret
= skl_update_scaler_plane(
11277 to_intel_crtc_state(crtc_state
),
11278 to_intel_plane_state(plane_state
));
11283 was_visible
= old_plane_state
->base
.visible
;
11284 visible
= plane_state
->visible
;
11286 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11287 was_visible
= false;
11290 * Visibility is calculated as if the crtc was on, but
11291 * after scaler setup everything depends on it being off
11292 * when the crtc isn't active.
11294 * FIXME this is wrong for watermarks. Watermarks should also
11295 * be computed as if the pipe would be active. Perhaps move
11296 * per-plane wm computation to the .check_plane() hook, and
11297 * only combine the results from all planes in the current place?
11299 if (!is_crtc_enabled
) {
11300 plane_state
->visible
= visible
= false;
11301 to_intel_crtc_state(crtc_state
)->active_planes
&= ~BIT(plane
->id
);
11302 to_intel_crtc_state(crtc_state
)->data_rate
[plane
->id
] = 0;
11305 if (!was_visible
&& !visible
)
11308 if (fb
!= old_plane_state
->base
.fb
)
11309 pipe_config
->fb_changed
= true;
11311 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11312 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11314 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11315 intel_crtc
->base
.base
.id
, intel_crtc
->base
.name
,
11316 plane
->base
.base
.id
, plane
->base
.name
,
11317 fb
? fb
->base
.id
: -1);
11319 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11320 plane
->base
.base
.id
, plane
->base
.name
,
11321 was_visible
, visible
,
11322 turn_off
, turn_on
, mode_changed
);
11325 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11326 pipe_config
->update_wm_pre
= true;
11328 /* must disable cxsr around plane enable/disable */
11329 if (plane
->id
!= PLANE_CURSOR
)
11330 pipe_config
->disable_cxsr
= true;
11331 } else if (turn_off
) {
11332 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11333 pipe_config
->update_wm_post
= true;
11335 /* must disable cxsr around plane enable/disable */
11336 if (plane
->id
!= PLANE_CURSOR
)
11337 pipe_config
->disable_cxsr
= true;
11338 } else if (intel_wm_need_update(to_intel_plane_state(plane
->base
.state
),
11339 to_intel_plane_state(plane_state
))) {
11340 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
)) {
11341 /* FIXME bollocks */
11342 pipe_config
->update_wm_pre
= true;
11343 pipe_config
->update_wm_post
= true;
11347 if (visible
|| was_visible
)
11348 pipe_config
->fb_bits
|= plane
->frontbuffer_bit
;
11351 * ILK/SNB DVSACNTR/Sprite Enable
11352 * IVB SPR_CTL/Sprite Enable
11353 * "When in Self Refresh Big FIFO mode, a write to enable the
11354 * plane will be internally buffered and delayed while Big FIFO
11355 * mode is exiting."
11357 * Which means that enabling the sprite can take an extra frame
11358 * when we start in big FIFO mode (LP1+). Thus we need to drop
11359 * down to LP0 and wait for vblank in order to make sure the
11360 * sprite gets enabled on the next vblank after the register write.
11361 * Doing otherwise would risk enabling the sprite one frame after
11362 * we've already signalled flip completion. We can resume LP1+
11363 * once the sprite has been enabled.
11366 * WaCxSRDisabledForSpriteScaling:ivb
11367 * IVB SPR_SCALE/Scaling Enable
11368 * "Low Power watermarks must be disabled for at least one
11369 * frame before enabling sprite scaling, and kept disabled
11370 * until sprite scaling is disabled."
11372 * ILK/SNB DVSASCALE/Scaling Enable
11373 * "When in Self Refresh Big FIFO mode, scaling enable will be
11374 * masked off while Big FIFO mode is exiting."
11376 * Despite the w/a only being listed for IVB we assume that
11377 * the ILK/SNB note has similar ramifications, hence we apply
11378 * the w/a on all three platforms.
11380 * With experimental results seems this is needed also for primary
11381 * plane, not only sprite plane.
11383 if (plane
->id
!= PLANE_CURSOR
&&
11384 (IS_GEN_RANGE(dev_priv
, 5, 6) ||
11385 IS_IVYBRIDGE(dev_priv
)) &&
11386 (turn_on
|| (!needs_scaling(old_plane_state
) &&
11387 needs_scaling(to_intel_plane_state(plane_state
)))))
11388 pipe_config
->disable_lp_wm
= true;
11393 static bool encoders_cloneable(const struct intel_encoder
*a
,
11394 const struct intel_encoder
*b
)
11396 /* masks could be asymmetric, so check both ways */
11397 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11398 b
->cloneable
& (1 << a
->type
));
11401 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11402 struct intel_crtc
*crtc
,
11403 struct intel_encoder
*encoder
)
11405 struct intel_encoder
*source_encoder
;
11406 struct drm_connector
*connector
;
11407 struct drm_connector_state
*connector_state
;
11410 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11411 if (connector_state
->crtc
!= &crtc
->base
)
11415 to_intel_encoder(connector_state
->best_encoder
);
11416 if (!encoders_cloneable(encoder
, source_encoder
))
11423 static int icl_add_linked_planes(struct intel_atomic_state
*state
)
11425 struct intel_plane
*plane
, *linked
;
11426 struct intel_plane_state
*plane_state
, *linked_plane_state
;
11429 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11430 linked
= plane_state
->linked_plane
;
11435 linked_plane_state
= intel_atomic_get_plane_state(state
, linked
);
11436 if (IS_ERR(linked_plane_state
))
11437 return PTR_ERR(linked_plane_state
);
11439 WARN_ON(linked_plane_state
->linked_plane
!= plane
);
11440 WARN_ON(linked_plane_state
->slave
== plane_state
->slave
);
11446 static int icl_check_nv12_planes(struct intel_crtc_state
*crtc_state
)
11448 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
11449 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11450 struct intel_atomic_state
*state
= to_intel_atomic_state(crtc_state
->base
.state
);
11451 struct intel_plane
*plane
, *linked
;
11452 struct intel_plane_state
*plane_state
;
11455 if (INTEL_GEN(dev_priv
) < 11)
11459 * Destroy all old plane links and make the slave plane invisible
11460 * in the crtc_state->active_planes mask.
11462 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11463 if (plane
->pipe
!= crtc
->pipe
|| !plane_state
->linked_plane
)
11466 plane_state
->linked_plane
= NULL
;
11467 if (plane_state
->slave
&& !plane_state
->base
.visible
) {
11468 crtc_state
->active_planes
&= ~BIT(plane
->id
);
11469 crtc_state
->update_planes
|= BIT(plane
->id
);
11472 plane_state
->slave
= false;
11475 if (!crtc_state
->nv12_planes
)
11478 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11479 struct intel_plane_state
*linked_state
= NULL
;
11481 if (plane
->pipe
!= crtc
->pipe
||
11482 !(crtc_state
->nv12_planes
& BIT(plane
->id
)))
11485 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, linked
) {
11486 if (!icl_is_nv12_y_plane(linked
->id
))
11489 if (crtc_state
->active_planes
& BIT(linked
->id
))
11492 linked_state
= intel_atomic_get_plane_state(state
, linked
);
11493 if (IS_ERR(linked_state
))
11494 return PTR_ERR(linked_state
);
11499 if (!linked_state
) {
11500 DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11501 hweight8(crtc_state
->nv12_planes
));
11506 plane_state
->linked_plane
= linked
;
11508 linked_state
->slave
= true;
11509 linked_state
->linked_plane
= plane
;
11510 crtc_state
->active_planes
|= BIT(linked
->id
);
11511 crtc_state
->update_planes
|= BIT(linked
->id
);
11512 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked
->base
.name
, plane
->base
.name
);
11518 static bool c8_planes_changed(const struct intel_crtc_state
*new_crtc_state
)
11520 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
11521 struct intel_atomic_state
*state
=
11522 to_intel_atomic_state(new_crtc_state
->base
.state
);
11523 const struct intel_crtc_state
*old_crtc_state
=
11524 intel_atomic_get_old_crtc_state(state
, crtc
);
11526 return !old_crtc_state
->c8_planes
!= !new_crtc_state
->c8_planes
;
11529 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11530 struct drm_crtc_state
*crtc_state
)
11532 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
11533 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11534 struct intel_crtc_state
*pipe_config
=
11535 to_intel_crtc_state(crtc_state
);
11537 bool mode_changed
= needs_modeset(crtc_state
);
11539 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
) &&
11540 mode_changed
&& !crtc_state
->active
)
11541 pipe_config
->update_wm_post
= true;
11543 if (mode_changed
&& crtc_state
->enable
&&
11544 dev_priv
->display
.crtc_compute_clock
&&
11545 !WARN_ON(pipe_config
->shared_dpll
)) {
11546 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11553 * May need to update pipe gamma enable bits
11554 * when C8 planes are getting enabled/disabled.
11556 if (c8_planes_changed(pipe_config
))
11557 crtc_state
->color_mgmt_changed
= true;
11559 if (mode_changed
|| pipe_config
->update_pipe
||
11560 crtc_state
->color_mgmt_changed
) {
11561 ret
= intel_color_check(pipe_config
);
11567 if (dev_priv
->display
.compute_pipe_wm
) {
11568 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
11570 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11575 if (dev_priv
->display
.compute_intermediate_wm
) {
11576 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
11580 * Calculate 'intermediate' watermarks that satisfy both the
11581 * old state and the new state. We can program these
11584 ret
= dev_priv
->display
.compute_intermediate_wm(pipe_config
);
11586 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11591 if (INTEL_GEN(dev_priv
) >= 9) {
11592 if (mode_changed
|| pipe_config
->update_pipe
)
11593 ret
= skl_update_scaler_crtc(pipe_config
);
11596 ret
= icl_check_nv12_planes(pipe_config
);
11598 ret
= skl_check_pipe_max_pixel_rate(intel_crtc
,
11601 ret
= intel_atomic_setup_scalers(dev_priv
, intel_crtc
,
11605 if (HAS_IPS(dev_priv
))
11606 pipe_config
->ips_enabled
= hsw_compute_ips_config(pipe_config
);
11611 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11612 .atomic_check
= intel_crtc_atomic_check
,
11615 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11617 struct intel_connector
*connector
;
11618 struct drm_connector_list_iter conn_iter
;
11620 drm_connector_list_iter_begin(dev
, &conn_iter
);
11621 for_each_intel_connector_iter(connector
, &conn_iter
) {
11622 if (connector
->base
.state
->crtc
)
11623 drm_connector_put(&connector
->base
);
11625 if (connector
->base
.encoder
) {
11626 connector
->base
.state
->best_encoder
=
11627 connector
->base
.encoder
;
11628 connector
->base
.state
->crtc
=
11629 connector
->base
.encoder
->crtc
;
11631 drm_connector_get(&connector
->base
);
11633 connector
->base
.state
->best_encoder
= NULL
;
11634 connector
->base
.state
->crtc
= NULL
;
11637 drm_connector_list_iter_end(&conn_iter
);
11641 compute_sink_pipe_bpp(const struct drm_connector_state
*conn_state
,
11642 struct intel_crtc_state
*pipe_config
)
11644 struct drm_connector
*connector
= conn_state
->connector
;
11645 const struct drm_display_info
*info
= &connector
->display_info
;
11648 switch (conn_state
->max_bpc
) {
11665 if (bpp
< pipe_config
->pipe_bpp
) {
11666 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
11667 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
11668 connector
->base
.id
, connector
->name
,
11669 bpp
, 3 * info
->bpc
, 3 * conn_state
->max_requested_bpc
,
11670 pipe_config
->pipe_bpp
);
11672 pipe_config
->pipe_bpp
= bpp
;
11679 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11680 struct intel_crtc_state
*pipe_config
)
11682 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11683 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
11684 struct drm_connector
*connector
;
11685 struct drm_connector_state
*connector_state
;
11688 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
11689 IS_CHERRYVIEW(dev_priv
)))
11691 else if (INTEL_GEN(dev_priv
) >= 5)
11696 pipe_config
->pipe_bpp
= bpp
;
11698 /* Clamp display bpp to connector max bpp */
11699 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11702 if (connector_state
->crtc
!= &crtc
->base
)
11705 ret
= compute_sink_pipe_bpp(connector_state
, pipe_config
);
11713 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11715 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11716 "type: 0x%x flags: 0x%x\n",
11718 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11719 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11720 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11721 mode
->crtc_vsync_end
, mode
->crtc_vtotal
,
11722 mode
->type
, mode
->flags
);
11726 intel_dump_m_n_config(const struct intel_crtc_state
*pipe_config
,
11727 const char *id
, unsigned int lane_count
,
11728 const struct intel_link_m_n
*m_n
)
11730 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11732 m_n
->gmch_m
, m_n
->gmch_n
,
11733 m_n
->link_m
, m_n
->link_n
, m_n
->tu
);
11737 intel_dump_infoframe(struct drm_i915_private
*dev_priv
,
11738 const union hdmi_infoframe
*frame
)
11740 if ((drm_debug
& DRM_UT_KMS
) == 0)
11743 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, frame
);
11746 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11748 static const char * const output_type_str
[] = {
11749 OUTPUT_TYPE(UNUSED
),
11750 OUTPUT_TYPE(ANALOG
),
11754 OUTPUT_TYPE(TVOUT
),
11760 OUTPUT_TYPE(DP_MST
),
11765 static void snprintf_output_types(char *buf
, size_t len
,
11766 unsigned int output_types
)
11773 for (i
= 0; i
< ARRAY_SIZE(output_type_str
); i
++) {
11776 if ((output_types
& BIT(i
)) == 0)
11779 r
= snprintf(str
, len
, "%s%s",
11780 str
!= buf
? "," : "", output_type_str
[i
]);
11786 output_types
&= ~BIT(i
);
11789 WARN_ON_ONCE(output_types
!= 0);
11792 static const char * const output_format_str
[] = {
11793 [INTEL_OUTPUT_FORMAT_INVALID
] = "Invalid",
11794 [INTEL_OUTPUT_FORMAT_RGB
] = "RGB",
11795 [INTEL_OUTPUT_FORMAT_YCBCR420
] = "YCBCR4:2:0",
11796 [INTEL_OUTPUT_FORMAT_YCBCR444
] = "YCBCR4:4:4",
11799 static const char *output_formats(enum intel_output_format format
)
11801 if (format
>= ARRAY_SIZE(output_format_str
))
11802 format
= INTEL_OUTPUT_FORMAT_INVALID
;
11803 return output_format_str
[format
];
11806 static void intel_dump_plane_state(const struct intel_plane_state
*plane_state
)
11808 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
11809 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
11810 struct drm_format_name_buf format_name
;
11813 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
11814 plane
->base
.base
.id
, plane
->base
.name
,
11815 yesno(plane_state
->base
.visible
));
11819 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
11820 plane
->base
.base
.id
, plane
->base
.name
,
11821 fb
->base
.id
, fb
->width
, fb
->height
,
11822 drm_get_format_name(fb
->format
->format
, &format_name
),
11823 yesno(plane_state
->base
.visible
));
11824 DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
11825 plane_state
->base
.rotation
, plane_state
->scaler_id
);
11826 if (plane_state
->base
.visible
)
11827 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT
" dst: " DRM_RECT_FMT
"\n",
11828 DRM_RECT_FP_ARG(&plane_state
->base
.src
),
11829 DRM_RECT_ARG(&plane_state
->base
.dst
));
11832 static void intel_dump_pipe_config(const struct intel_crtc_state
*pipe_config
,
11833 struct intel_atomic_state
*state
,
11834 const char *context
)
11836 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
11837 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11838 const struct intel_plane_state
*plane_state
;
11839 struct intel_plane
*plane
;
11843 DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
11844 crtc
->base
.base
.id
, crtc
->base
.name
,
11845 yesno(pipe_config
->base
.enable
), context
);
11847 if (!pipe_config
->base
.enable
)
11850 snprintf_output_types(buf
, sizeof(buf
), pipe_config
->output_types
);
11851 DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
11852 yesno(pipe_config
->base
.active
),
11853 buf
, pipe_config
->output_types
,
11854 output_formats(pipe_config
->output_format
));
11856 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11857 transcoder_name(pipe_config
->cpu_transcoder
),
11858 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11860 if (pipe_config
->has_pch_encoder
)
11861 intel_dump_m_n_config(pipe_config
, "fdi",
11862 pipe_config
->fdi_lanes
,
11863 &pipe_config
->fdi_m_n
);
11865 if (intel_crtc_has_dp_encoder(pipe_config
)) {
11866 intel_dump_m_n_config(pipe_config
, "dp m_n",
11867 pipe_config
->lane_count
, &pipe_config
->dp_m_n
);
11868 if (pipe_config
->has_drrs
)
11869 intel_dump_m_n_config(pipe_config
, "dp m2_n2",
11870 pipe_config
->lane_count
,
11871 &pipe_config
->dp_m2_n2
);
11874 DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
11875 pipe_config
->has_audio
, pipe_config
->has_infoframe
,
11876 pipe_config
->infoframes
.enable
);
11878 if (pipe_config
->infoframes
.enable
&
11879 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
))
11880 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config
->infoframes
.gcp
);
11881 if (pipe_config
->infoframes
.enable
&
11882 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI
))
11883 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.avi
);
11884 if (pipe_config
->infoframes
.enable
&
11885 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD
))
11886 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.spd
);
11887 if (pipe_config
->infoframes
.enable
&
11888 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR
))
11889 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.hdmi
);
11891 DRM_DEBUG_KMS("requested mode:\n");
11892 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11893 DRM_DEBUG_KMS("adjusted mode:\n");
11894 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11895 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11896 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11897 pipe_config
->port_clock
,
11898 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
11899 pipe_config
->pixel_rate
);
11901 if (INTEL_GEN(dev_priv
) >= 9)
11902 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11904 pipe_config
->scaler_state
.scaler_users
,
11905 pipe_config
->scaler_state
.scaler_id
);
11907 if (HAS_GMCH(dev_priv
))
11908 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11909 pipe_config
->gmch_pfit
.control
,
11910 pipe_config
->gmch_pfit
.pgm_ratios
,
11911 pipe_config
->gmch_pfit
.lvds_border_bits
);
11913 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
11914 pipe_config
->pch_pfit
.pos
,
11915 pipe_config
->pch_pfit
.size
,
11916 enableddisabled(pipe_config
->pch_pfit
.enabled
),
11917 yesno(pipe_config
->pch_pfit
.force_thru
));
11919 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11920 pipe_config
->ips_enabled
, pipe_config
->double_wide
);
11922 intel_dpll_dump_hw_state(dev_priv
, &pipe_config
->dpll_hw_state
);
11928 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11929 if (plane
->pipe
== crtc
->pipe
)
11930 intel_dump_plane_state(plane_state
);
11934 static bool check_digital_port_conflicts(struct intel_atomic_state
*state
)
11936 struct drm_device
*dev
= state
->base
.dev
;
11937 struct drm_connector
*connector
;
11938 struct drm_connector_list_iter conn_iter
;
11939 unsigned int used_ports
= 0;
11940 unsigned int used_mst_ports
= 0;
11944 * Walk the connector list instead of the encoder
11945 * list to detect the problem on ddi platforms
11946 * where there's just one encoder per digital port.
11948 drm_connector_list_iter_begin(dev
, &conn_iter
);
11949 drm_for_each_connector_iter(connector
, &conn_iter
) {
11950 struct drm_connector_state
*connector_state
;
11951 struct intel_encoder
*encoder
;
11954 drm_atomic_get_new_connector_state(&state
->base
,
11956 if (!connector_state
)
11957 connector_state
= connector
->state
;
11959 if (!connector_state
->best_encoder
)
11962 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11964 WARN_ON(!connector_state
->crtc
);
11966 switch (encoder
->type
) {
11967 unsigned int port_mask
;
11968 case INTEL_OUTPUT_DDI
:
11969 if (WARN_ON(!HAS_DDI(to_i915(dev
))))
11971 /* else: fall through */
11972 case INTEL_OUTPUT_DP
:
11973 case INTEL_OUTPUT_HDMI
:
11974 case INTEL_OUTPUT_EDP
:
11975 port_mask
= 1 << encoder
->port
;
11977 /* the same port mustn't appear more than once */
11978 if (used_ports
& port_mask
)
11981 used_ports
|= port_mask
;
11983 case INTEL_OUTPUT_DP_MST
:
11985 1 << encoder
->port
;
11991 drm_connector_list_iter_end(&conn_iter
);
11993 /* can't mix MST and SST/HDMI on the same port */
11994 if (used_ports
& used_mst_ports
)
12001 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12003 struct drm_i915_private
*dev_priv
=
12004 to_i915(crtc_state
->base
.crtc
->dev
);
12005 struct intel_crtc_state
*saved_state
;
12007 saved_state
= kzalloc(sizeof(*saved_state
), GFP_KERNEL
);
12011 /* FIXME: before the switch to atomic started, a new pipe_config was
12012 * kzalloc'd. Code that depends on any field being zero should be
12013 * fixed, so that the crtc_state can be safely duplicated. For now,
12014 * only fields that are know to not cause problems are preserved. */
12016 saved_state
->scaler_state
= crtc_state
->scaler_state
;
12017 saved_state
->shared_dpll
= crtc_state
->shared_dpll
;
12018 saved_state
->dpll_hw_state
= crtc_state
->dpll_hw_state
;
12019 saved_state
->crc_enabled
= crtc_state
->crc_enabled
;
12020 if (IS_G4X(dev_priv
) ||
12021 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
12022 saved_state
->wm
= crtc_state
->wm
;
12024 /* Keep base drm_crtc_state intact, only clear our extended struct */
12025 BUILD_BUG_ON(offsetof(struct intel_crtc_state
, base
));
12026 memcpy(&crtc_state
->base
+ 1, &saved_state
->base
+ 1,
12027 sizeof(*crtc_state
) - sizeof(crtc_state
->base
));
12029 kfree(saved_state
);
12034 intel_modeset_pipe_config(struct intel_crtc_state
*pipe_config
)
12036 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
12037 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12038 struct intel_encoder
*encoder
;
12039 struct drm_connector
*connector
;
12040 struct drm_connector_state
*connector_state
;
12045 ret
= clear_intel_crtc_state(pipe_config
);
12049 pipe_config
->cpu_transcoder
=
12050 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12053 * Sanitize sync polarity flags based on requested ones. If neither
12054 * positive or negative polarity is requested, treat this as meaning
12055 * negative polarity.
12057 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12058 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12059 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12061 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12062 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12063 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12065 ret
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12070 base_bpp
= pipe_config
->pipe_bpp
;
12073 * Determine the real pipe dimensions. Note that stereo modes can
12074 * increase the actual pipe size due to the frame doubling and
12075 * insertion of additional space for blanks between the frame. This
12076 * is stored in the crtc timings. We use the requested mode to do this
12077 * computation to clearly distinguish it from the adjusted mode, which
12078 * can be changed by the connectors in the below retry loop.
12080 drm_mode_get_hv_timing(&pipe_config
->base
.mode
,
12081 &pipe_config
->pipe_src_w
,
12082 &pipe_config
->pipe_src_h
);
12084 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
12085 if (connector_state
->crtc
!= crtc
)
12088 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12090 if (!check_single_encoder_cloning(state
, to_intel_crtc(crtc
), encoder
)) {
12091 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12096 * Determine output_types before calling the .compute_config()
12097 * hooks so that the hooks can use this information safely.
12099 if (encoder
->compute_output_type
)
12100 pipe_config
->output_types
|=
12101 BIT(encoder
->compute_output_type(encoder
, pipe_config
,
12104 pipe_config
->output_types
|= BIT(encoder
->type
);
12108 /* Ensure the port clock defaults are reset when retrying. */
12109 pipe_config
->port_clock
= 0;
12110 pipe_config
->pixel_multiplier
= 1;
12112 /* Fill in default crtc timings, allow encoders to overwrite them. */
12113 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12114 CRTC_STEREO_DOUBLE
);
12116 /* Pass our mode to the connectors and the CRTC to give them a chance to
12117 * adjust it according to limitations or connector properties, and also
12118 * a chance to reject the mode entirely.
12120 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
12121 if (connector_state
->crtc
!= crtc
)
12124 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12125 ret
= encoder
->compute_config(encoder
, pipe_config
,
12128 if (ret
!= -EDEADLK
)
12129 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12135 /* Set default port clock if not overwritten by the encoder. Needs to be
12136 * done afterwards in case the encoder adjusts the mode. */
12137 if (!pipe_config
->port_clock
)
12138 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12139 * pipe_config
->pixel_multiplier
;
12141 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12142 if (ret
== -EDEADLK
)
12145 DRM_DEBUG_KMS("CRTC fixup failed\n");
12149 if (ret
== RETRY
) {
12150 if (WARN(!retry
, "loop in pipe configuration computation\n"))
12153 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12155 goto encoder_retry
;
12158 /* Dithering seems to not pass-through bits correctly when it should, so
12159 * only enable it on 6bpc panels and when its not a compliance
12160 * test requesting 6bpc video pattern.
12162 pipe_config
->dither
= (pipe_config
->pipe_bpp
== 6*3) &&
12163 !pipe_config
->dither_force_disable
;
12164 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12165 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12170 bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12174 if (clock1
== clock2
)
12177 if (!clock1
|| !clock2
)
12180 diff
= abs(clock1
- clock2
);
12182 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12189 intel_compare_m_n(unsigned int m
, unsigned int n
,
12190 unsigned int m2
, unsigned int n2
,
12193 if (m
== m2
&& n
== n2
)
12196 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12199 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12206 } else if (n
< n2
) {
12216 return intel_fuzzy_clock_check(m
, m2
);
12220 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12221 struct intel_link_m_n
*m2_n2
,
12224 if (m_n
->tu
== m2_n2
->tu
&&
12225 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12226 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12227 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12228 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12239 intel_compare_infoframe(const union hdmi_infoframe
*a
,
12240 const union hdmi_infoframe
*b
)
12242 return memcmp(a
, b
, sizeof(*a
)) == 0;
12246 pipe_config_infoframe_err(struct drm_i915_private
*dev_priv
,
12247 bool adjust
, const char *name
,
12248 const union hdmi_infoframe
*a
,
12249 const union hdmi_infoframe
*b
)
12252 if ((drm_debug
& DRM_UT_KMS
) == 0)
12255 drm_dbg(DRM_UT_KMS
, "mismatch in %s infoframe", name
);
12256 drm_dbg(DRM_UT_KMS
, "expected:");
12257 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, a
);
12258 drm_dbg(DRM_UT_KMS
, "found");
12259 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, b
);
12261 drm_err("mismatch in %s infoframe", name
);
12262 drm_err("expected:");
12263 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, a
);
12265 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, b
);
12269 static void __printf(3, 4)
12270 pipe_config_err(bool adjust
, const char *name
, const char *format
, ...)
12272 struct va_format vaf
;
12275 va_start(args
, format
);
12280 drm_dbg(DRM_UT_KMS
, "mismatch in %s %pV", name
, &vaf
);
12282 drm_err("mismatch in %s %pV", name
, &vaf
);
12287 static bool fastboot_enabled(struct drm_i915_private
*dev_priv
)
12289 if (i915_modparams
.fastboot
!= -1)
12290 return i915_modparams
.fastboot
;
12292 /* Enable fastboot by default on Skylake and newer */
12293 if (INTEL_GEN(dev_priv
) >= 9)
12296 /* Enable fastboot by default on VLV and CHV */
12297 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
12300 /* Disabled by default on all others */
12305 intel_pipe_config_compare(struct drm_i915_private
*dev_priv
,
12306 struct intel_crtc_state
*current_config
,
12307 struct intel_crtc_state
*pipe_config
,
12311 bool fixup_inherited
= adjust
&&
12312 (current_config
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
) &&
12313 !(pipe_config
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
);
12315 if (fixup_inherited
&& !fastboot_enabled(dev_priv
)) {
12316 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12320 #define PIPE_CONF_CHECK_X(name) do { \
12321 if (current_config->name != pipe_config->name) { \
12322 pipe_config_err(adjust, __stringify(name), \
12323 "(expected 0x%08x, found 0x%08x)\n", \
12324 current_config->name, \
12325 pipe_config->name); \
12330 #define PIPE_CONF_CHECK_I(name) do { \
12331 if (current_config->name != pipe_config->name) { \
12332 pipe_config_err(adjust, __stringify(name), \
12333 "(expected %i, found %i)\n", \
12334 current_config->name, \
12335 pipe_config->name); \
12340 #define PIPE_CONF_CHECK_BOOL(name) do { \
12341 if (current_config->name != pipe_config->name) { \
12342 pipe_config_err(adjust, __stringify(name), \
12343 "(expected %s, found %s)\n", \
12344 yesno(current_config->name), \
12345 yesno(pipe_config->name)); \
12351 * Checks state where we only read out the enabling, but not the entire
12352 * state itself (like full infoframes or ELD for audio). These states
12353 * require a full modeset on bootup to fix up.
12355 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12356 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12357 PIPE_CONF_CHECK_BOOL(name); \
12359 pipe_config_err(adjust, __stringify(name), \
12360 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
12361 yesno(current_config->name), \
12362 yesno(pipe_config->name)); \
12367 #define PIPE_CONF_CHECK_P(name) do { \
12368 if (current_config->name != pipe_config->name) { \
12369 pipe_config_err(adjust, __stringify(name), \
12370 "(expected %p, found %p)\n", \
12371 current_config->name, \
12372 pipe_config->name); \
12377 #define PIPE_CONF_CHECK_M_N(name) do { \
12378 if (!intel_compare_link_m_n(¤t_config->name, \
12379 &pipe_config->name,\
12381 pipe_config_err(adjust, __stringify(name), \
12382 "(expected tu %i gmch %i/%i link %i/%i, " \
12383 "found tu %i, gmch %i/%i link %i/%i)\n", \
12384 current_config->name.tu, \
12385 current_config->name.gmch_m, \
12386 current_config->name.gmch_n, \
12387 current_config->name.link_m, \
12388 current_config->name.link_n, \
12389 pipe_config->name.tu, \
12390 pipe_config->name.gmch_m, \
12391 pipe_config->name.gmch_n, \
12392 pipe_config->name.link_m, \
12393 pipe_config->name.link_n); \
12398 /* This is required for BDW+ where there is only one set of registers for
12399 * switching between high and low RR.
12400 * This macro can be used whenever a comparison has to be made between one
12401 * hw state and multiple sw state variables.
12403 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12404 if (!intel_compare_link_m_n(¤t_config->name, \
12405 &pipe_config->name, adjust) && \
12406 !intel_compare_link_m_n(¤t_config->alt_name, \
12407 &pipe_config->name, adjust)) { \
12408 pipe_config_err(adjust, __stringify(name), \
12409 "(expected tu %i gmch %i/%i link %i/%i, " \
12410 "or tu %i gmch %i/%i link %i/%i, " \
12411 "found tu %i, gmch %i/%i link %i/%i)\n", \
12412 current_config->name.tu, \
12413 current_config->name.gmch_m, \
12414 current_config->name.gmch_n, \
12415 current_config->name.link_m, \
12416 current_config->name.link_n, \
12417 current_config->alt_name.tu, \
12418 current_config->alt_name.gmch_m, \
12419 current_config->alt_name.gmch_n, \
12420 current_config->alt_name.link_m, \
12421 current_config->alt_name.link_n, \
12422 pipe_config->name.tu, \
12423 pipe_config->name.gmch_m, \
12424 pipe_config->name.gmch_n, \
12425 pipe_config->name.link_m, \
12426 pipe_config->name.link_n); \
12431 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
12432 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12433 pipe_config_err(adjust, __stringify(name), \
12434 "(%x) (expected %i, found %i)\n", \
12436 current_config->name & (mask), \
12437 pipe_config->name & (mask)); \
12442 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
12443 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12444 pipe_config_err(adjust, __stringify(name), \
12445 "(expected %i, found %i)\n", \
12446 current_config->name, \
12447 pipe_config->name); \
12452 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
12453 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
12454 &pipe_config->infoframes.name)) { \
12455 pipe_config_infoframe_err(dev_priv, adjust, __stringify(name), \
12456 ¤t_config->infoframes.name, \
12457 &pipe_config->infoframes.name); \
12462 #define PIPE_CONF_QUIRK(quirk) \
12463 ((current_config->quirks | pipe_config->quirks) & (quirk))
12465 PIPE_CONF_CHECK_I(cpu_transcoder
);
12467 PIPE_CONF_CHECK_BOOL(has_pch_encoder
);
12468 PIPE_CONF_CHECK_I(fdi_lanes
);
12469 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12471 PIPE_CONF_CHECK_I(lane_count
);
12472 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
12474 if (INTEL_GEN(dev_priv
) < 8) {
12475 PIPE_CONF_CHECK_M_N(dp_m_n
);
12477 if (current_config
->has_drrs
)
12478 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12480 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12482 PIPE_CONF_CHECK_X(output_types
);
12484 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12485 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12486 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12487 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12488 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12489 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12491 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12492 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12493 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12494 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12495 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12496 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12498 PIPE_CONF_CHECK_I(pixel_multiplier
);
12499 PIPE_CONF_CHECK_I(output_format
);
12500 PIPE_CONF_CHECK_BOOL(has_hdmi_sink
);
12501 if ((INTEL_GEN(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
12502 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
12503 PIPE_CONF_CHECK_BOOL(limited_color_range
);
12505 PIPE_CONF_CHECK_BOOL(hdmi_scrambling
);
12506 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio
);
12507 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe
);
12509 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio
);
12511 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12512 DRM_MODE_FLAG_INTERLACE
);
12514 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12515 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12516 DRM_MODE_FLAG_PHSYNC
);
12517 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12518 DRM_MODE_FLAG_NHSYNC
);
12519 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12520 DRM_MODE_FLAG_PVSYNC
);
12521 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12522 DRM_MODE_FLAG_NVSYNC
);
12525 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12526 /* pfit ratios are autocomputed by the hw on gen4+ */
12527 if (INTEL_GEN(dev_priv
) < 4)
12528 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
12529 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12532 * Changing the EDP transcoder input mux
12533 * (A_ONOFF vs. A_ON) requires a full modeset.
12535 PIPE_CONF_CHECK_BOOL(pch_pfit
.force_thru
);
12538 PIPE_CONF_CHECK_I(pipe_src_w
);
12539 PIPE_CONF_CHECK_I(pipe_src_h
);
12541 PIPE_CONF_CHECK_BOOL(pch_pfit
.enabled
);
12542 if (current_config
->pch_pfit
.enabled
) {
12543 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12544 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12547 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12548 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate
);
12550 PIPE_CONF_CHECK_X(gamma_mode
);
12551 if (IS_CHERRYVIEW(dev_priv
))
12552 PIPE_CONF_CHECK_X(cgm_mode
);
12554 PIPE_CONF_CHECK_X(csc_mode
);
12555 PIPE_CONF_CHECK_BOOL(gamma_enable
);
12556 PIPE_CONF_CHECK_BOOL(csc_enable
);
12559 PIPE_CONF_CHECK_BOOL(double_wide
);
12561 PIPE_CONF_CHECK_P(shared_dpll
);
12562 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12563 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12564 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12565 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12566 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12567 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12568 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12569 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12570 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12571 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr0
);
12572 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb0
);
12573 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb4
);
12574 PIPE_CONF_CHECK_X(dpll_hw_state
.pll0
);
12575 PIPE_CONF_CHECK_X(dpll_hw_state
.pll1
);
12576 PIPE_CONF_CHECK_X(dpll_hw_state
.pll2
);
12577 PIPE_CONF_CHECK_X(dpll_hw_state
.pll3
);
12578 PIPE_CONF_CHECK_X(dpll_hw_state
.pll6
);
12579 PIPE_CONF_CHECK_X(dpll_hw_state
.pll8
);
12580 PIPE_CONF_CHECK_X(dpll_hw_state
.pll9
);
12581 PIPE_CONF_CHECK_X(dpll_hw_state
.pll10
);
12582 PIPE_CONF_CHECK_X(dpll_hw_state
.pcsdw12
);
12583 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_refclkin_ctl
);
12584 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_clktop2_coreclkctl1
);
12585 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_clktop2_hsclkctl
);
12586 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_div0
);
12587 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_div1
);
12588 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_lf
);
12589 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_frac_lock
);
12590 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_ssc
);
12591 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_bias
);
12592 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_tdc_coldst_bias
);
12594 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
12595 PIPE_CONF_CHECK_X(dsi_pll
.div
);
12597 if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5)
12598 PIPE_CONF_CHECK_I(pipe_bpp
);
12600 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12601 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12603 PIPE_CONF_CHECK_I(min_voltage_level
);
12605 PIPE_CONF_CHECK_X(infoframes
.enable
);
12606 PIPE_CONF_CHECK_X(infoframes
.gcp
);
12607 PIPE_CONF_CHECK_INFOFRAME(avi
);
12608 PIPE_CONF_CHECK_INFOFRAME(spd
);
12609 PIPE_CONF_CHECK_INFOFRAME(hdmi
);
12610 PIPE_CONF_CHECK_INFOFRAME(drm
);
12612 #undef PIPE_CONF_CHECK_X
12613 #undef PIPE_CONF_CHECK_I
12614 #undef PIPE_CONF_CHECK_BOOL
12615 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
12616 #undef PIPE_CONF_CHECK_P
12617 #undef PIPE_CONF_CHECK_FLAGS
12618 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12619 #undef PIPE_CONF_QUIRK
12624 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
12625 const struct intel_crtc_state
*pipe_config
)
12627 if (pipe_config
->has_pch_encoder
) {
12628 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
12629 &pipe_config
->fdi_m_n
);
12630 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
12633 * FDI already provided one idea for the dotclock.
12634 * Yell if the encoder disagrees.
12636 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
12637 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12638 fdi_dotclock
, dotclock
);
12642 static void verify_wm_state(struct drm_crtc
*crtc
,
12643 struct drm_crtc_state
*new_state
)
12645 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
12646 struct skl_hw_state
{
12647 struct skl_ddb_entry ddb_y
[I915_MAX_PLANES
];
12648 struct skl_ddb_entry ddb_uv
[I915_MAX_PLANES
];
12649 struct skl_ddb_allocation ddb
;
12650 struct skl_pipe_wm wm
;
12652 struct skl_ddb_allocation
*sw_ddb
;
12653 struct skl_pipe_wm
*sw_wm
;
12654 struct skl_ddb_entry
*hw_ddb_entry
, *sw_ddb_entry
;
12655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12656 const enum pipe pipe
= intel_crtc
->pipe
;
12657 int plane
, level
, max_level
= ilk_wm_max_level(dev_priv
);
12659 if (INTEL_GEN(dev_priv
) < 9 || !new_state
->active
)
12662 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
12666 skl_pipe_wm_get_hw_state(intel_crtc
, &hw
->wm
);
12667 sw_wm
= &to_intel_crtc_state(new_state
)->wm
.skl
.optimal
;
12669 skl_pipe_ddb_get_hw_state(intel_crtc
, hw
->ddb_y
, hw
->ddb_uv
);
12671 skl_ddb_get_hw_state(dev_priv
, &hw
->ddb
);
12672 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12674 if (INTEL_GEN(dev_priv
) >= 11 &&
12675 hw
->ddb
.enabled_slices
!= sw_ddb
->enabled_slices
)
12676 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
12677 sw_ddb
->enabled_slices
,
12678 hw
->ddb
.enabled_slices
);
12681 for_each_universal_plane(dev_priv
, pipe
, plane
) {
12682 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
12684 hw_plane_wm
= &hw
->wm
.planes
[plane
];
12685 sw_plane_wm
= &sw_wm
->planes
[plane
];
12688 for (level
= 0; level
<= max_level
; level
++) {
12689 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
12690 &sw_plane_wm
->wm
[level
]))
12693 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12694 pipe_name(pipe
), plane
+ 1, level
,
12695 sw_plane_wm
->wm
[level
].plane_en
,
12696 sw_plane_wm
->wm
[level
].plane_res_b
,
12697 sw_plane_wm
->wm
[level
].plane_res_l
,
12698 hw_plane_wm
->wm
[level
].plane_en
,
12699 hw_plane_wm
->wm
[level
].plane_res_b
,
12700 hw_plane_wm
->wm
[level
].plane_res_l
);
12703 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
12704 &sw_plane_wm
->trans_wm
)) {
12705 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12706 pipe_name(pipe
), plane
+ 1,
12707 sw_plane_wm
->trans_wm
.plane_en
,
12708 sw_plane_wm
->trans_wm
.plane_res_b
,
12709 sw_plane_wm
->trans_wm
.plane_res_l
,
12710 hw_plane_wm
->trans_wm
.plane_en
,
12711 hw_plane_wm
->trans_wm
.plane_res_b
,
12712 hw_plane_wm
->trans_wm
.plane_res_l
);
12716 hw_ddb_entry
= &hw
->ddb_y
[plane
];
12717 sw_ddb_entry
= &to_intel_crtc_state(new_state
)->wm
.skl
.plane_ddb_y
[plane
];
12719 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
12720 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12721 pipe_name(pipe
), plane
+ 1,
12722 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
12723 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
12729 * If the cursor plane isn't active, we may not have updated it's ddb
12730 * allocation. In that case since the ddb allocation will be updated
12731 * once the plane becomes visible, we can skip this check
12734 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
12736 hw_plane_wm
= &hw
->wm
.planes
[PLANE_CURSOR
];
12737 sw_plane_wm
= &sw_wm
->planes
[PLANE_CURSOR
];
12740 for (level
= 0; level
<= max_level
; level
++) {
12741 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
12742 &sw_plane_wm
->wm
[level
]))
12745 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12746 pipe_name(pipe
), level
,
12747 sw_plane_wm
->wm
[level
].plane_en
,
12748 sw_plane_wm
->wm
[level
].plane_res_b
,
12749 sw_plane_wm
->wm
[level
].plane_res_l
,
12750 hw_plane_wm
->wm
[level
].plane_en
,
12751 hw_plane_wm
->wm
[level
].plane_res_b
,
12752 hw_plane_wm
->wm
[level
].plane_res_l
);
12755 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
12756 &sw_plane_wm
->trans_wm
)) {
12757 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12759 sw_plane_wm
->trans_wm
.plane_en
,
12760 sw_plane_wm
->trans_wm
.plane_res_b
,
12761 sw_plane_wm
->trans_wm
.plane_res_l
,
12762 hw_plane_wm
->trans_wm
.plane_en
,
12763 hw_plane_wm
->trans_wm
.plane_res_b
,
12764 hw_plane_wm
->trans_wm
.plane_res_l
);
12768 hw_ddb_entry
= &hw
->ddb_y
[PLANE_CURSOR
];
12769 sw_ddb_entry
= &to_intel_crtc_state(new_state
)->wm
.skl
.plane_ddb_y
[PLANE_CURSOR
];
12771 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
12772 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12774 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
12775 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
12783 verify_connector_state(struct drm_device
*dev
,
12784 struct drm_atomic_state
*state
,
12785 struct drm_crtc
*crtc
)
12787 struct drm_connector
*connector
;
12788 struct drm_connector_state
*new_conn_state
;
12791 for_each_new_connector_in_state(state
, connector
, new_conn_state
, i
) {
12792 struct drm_encoder
*encoder
= connector
->encoder
;
12793 struct drm_crtc_state
*crtc_state
= NULL
;
12795 if (new_conn_state
->crtc
!= crtc
)
12799 crtc_state
= drm_atomic_get_new_crtc_state(state
, new_conn_state
->crtc
);
12801 intel_connector_verify_state(crtc_state
, new_conn_state
);
12803 I915_STATE_WARN(new_conn_state
->best_encoder
!= encoder
,
12804 "connector's atomic encoder doesn't match legacy encoder\n");
12809 verify_encoder_state(struct drm_device
*dev
, struct drm_atomic_state
*state
)
12811 struct intel_encoder
*encoder
;
12812 struct drm_connector
*connector
;
12813 struct drm_connector_state
*old_conn_state
, *new_conn_state
;
12816 for_each_intel_encoder(dev
, encoder
) {
12817 bool enabled
= false, found
= false;
12820 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12821 encoder
->base
.base
.id
,
12822 encoder
->base
.name
);
12824 for_each_oldnew_connector_in_state(state
, connector
, old_conn_state
,
12825 new_conn_state
, i
) {
12826 if (old_conn_state
->best_encoder
== &encoder
->base
)
12829 if (new_conn_state
->best_encoder
!= &encoder
->base
)
12831 found
= enabled
= true;
12833 I915_STATE_WARN(new_conn_state
->crtc
!=
12834 encoder
->base
.crtc
,
12835 "connector's crtc doesn't match encoder crtc\n");
12841 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12842 "encoder's enabled state mismatch "
12843 "(expected %i, found %i)\n",
12844 !!encoder
->base
.crtc
, enabled
);
12846 if (!encoder
->base
.crtc
) {
12849 active
= encoder
->get_hw_state(encoder
, &pipe
);
12850 I915_STATE_WARN(active
,
12851 "encoder detached but still enabled on pipe %c.\n",
12858 verify_crtc_state(struct drm_crtc
*crtc
,
12859 struct drm_crtc_state
*old_crtc_state
,
12860 struct drm_crtc_state
*new_crtc_state
)
12862 struct drm_device
*dev
= crtc
->dev
;
12863 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12864 struct intel_encoder
*encoder
;
12865 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12866 struct intel_crtc_state
*pipe_config
, *sw_config
;
12867 struct drm_atomic_state
*old_state
;
12870 old_state
= old_crtc_state
->state
;
12871 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
12872 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12873 memset(pipe_config
, 0, sizeof(*pipe_config
));
12874 pipe_config
->base
.crtc
= crtc
;
12875 pipe_config
->base
.state
= old_state
;
12877 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
12879 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
12881 /* we keep both pipes enabled on 830 */
12882 if (IS_I830(dev_priv
))
12883 active
= new_crtc_state
->active
;
12885 I915_STATE_WARN(new_crtc_state
->active
!= active
,
12886 "crtc active state doesn't match with hw state "
12887 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
12889 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
12890 "transitional active state does not match atomic hw state "
12891 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
12893 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12896 active
= encoder
->get_hw_state(encoder
, &pipe
);
12897 I915_STATE_WARN(active
!= new_crtc_state
->active
,
12898 "[ENCODER:%i] active %i with crtc active %i\n",
12899 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
12901 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
12902 "Encoder connected to wrong pipe %c\n",
12906 encoder
->get_config(encoder
, pipe_config
);
12909 intel_crtc_compute_pixel_rate(pipe_config
);
12911 if (!new_crtc_state
->active
)
12914 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
12916 sw_config
= to_intel_crtc_state(new_crtc_state
);
12917 if (!intel_pipe_config_compare(dev_priv
, sw_config
,
12918 pipe_config
, false)) {
12919 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12920 intel_dump_pipe_config(pipe_config
, NULL
, "[hw state]");
12921 intel_dump_pipe_config(sw_config
, NULL
, "[sw state]");
12926 intel_verify_planes(struct intel_atomic_state
*state
)
12928 struct intel_plane
*plane
;
12929 const struct intel_plane_state
*plane_state
;
12932 for_each_new_intel_plane_in_state(state
, plane
,
12934 assert_plane(plane
, plane_state
->slave
||
12935 plane_state
->base
.visible
);
12939 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
12940 struct intel_shared_dpll
*pll
,
12941 struct drm_crtc
*crtc
,
12942 struct drm_crtc_state
*new_state
)
12944 struct intel_dpll_hw_state dpll_hw_state
;
12945 unsigned int crtc_mask
;
12948 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12950 DRM_DEBUG_KMS("%s\n", pll
->info
->name
);
12952 active
= pll
->info
->funcs
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12954 if (!(pll
->info
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
12955 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
12956 "pll in active use but not on in sw tracking\n");
12957 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
12958 "pll is on but not used by any active crtc\n");
12959 I915_STATE_WARN(pll
->on
!= active
,
12960 "pll on state mismatch (expected %i, found %i)\n",
12965 I915_STATE_WARN(pll
->active_mask
& ~pll
->state
.crtc_mask
,
12966 "more active pll users than references: %x vs %x\n",
12967 pll
->active_mask
, pll
->state
.crtc_mask
);
12972 crtc_mask
= drm_crtc_mask(crtc
);
12974 if (new_state
->active
)
12975 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
12976 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12977 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12979 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
12980 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12981 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12983 I915_STATE_WARN(!(pll
->state
.crtc_mask
& crtc_mask
),
12984 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12985 crtc_mask
, pll
->state
.crtc_mask
);
12987 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->state
.hw_state
,
12989 sizeof(dpll_hw_state
)),
12990 "pll hw state mismatch\n");
12994 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
12995 struct drm_crtc_state
*old_crtc_state
,
12996 struct drm_crtc_state
*new_crtc_state
)
12998 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12999 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
13000 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
13002 if (new_state
->shared_dpll
)
13003 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
13005 if (old_state
->shared_dpll
&&
13006 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
13007 unsigned int crtc_mask
= drm_crtc_mask(crtc
);
13008 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
13010 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13011 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13012 pipe_name(drm_crtc_index(crtc
)));
13013 I915_STATE_WARN(pll
->state
.crtc_mask
& crtc_mask
,
13014 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13015 pipe_name(drm_crtc_index(crtc
)));
13020 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
13021 struct drm_atomic_state
*state
,
13022 struct drm_crtc_state
*old_state
,
13023 struct drm_crtc_state
*new_state
)
13025 if (!needs_modeset(new_state
) &&
13026 !to_intel_crtc_state(new_state
)->update_pipe
)
13029 verify_wm_state(crtc
, new_state
);
13030 verify_connector_state(crtc
->dev
, state
, crtc
);
13031 verify_crtc_state(crtc
, old_state
, new_state
);
13032 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
13036 verify_disabled_dpll_state(struct drm_device
*dev
)
13038 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13041 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
13042 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
13046 intel_modeset_verify_disabled(struct drm_device
*dev
,
13047 struct drm_atomic_state
*state
)
13049 verify_encoder_state(dev
, state
);
13050 verify_connector_state(dev
, state
, NULL
);
13051 verify_disabled_dpll_state(dev
);
13054 static void update_scanline_offset(const struct intel_crtc_state
*crtc_state
)
13056 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
13057 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
13060 * The scanline counter increments at the leading edge of hsync.
13062 * On most platforms it starts counting from vtotal-1 on the
13063 * first active line. That means the scanline counter value is
13064 * always one less than what we would expect. Ie. just after
13065 * start of vblank, which also occurs at start of hsync (on the
13066 * last active line), the scanline counter will read vblank_start-1.
13068 * On gen2 the scanline counter starts counting from 1 instead
13069 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13070 * to keep the value positive), instead of adding one.
13072 * On HSW+ the behaviour of the scanline counter depends on the output
13073 * type. For DP ports it behaves like most other platforms, but on HDMI
13074 * there's an extra 1 line difference. So we need to add two instead of
13075 * one to the value.
13077 * On VLV/CHV DSI the scanline counter would appear to increment
13078 * approx. 1/3 of a scanline before start of vblank. Unfortunately
13079 * that means we can't tell whether we're in vblank or not while
13080 * we're on that particular line. We must still set scanline_offset
13081 * to 1 so that the vblank timestamps come out correct when we query
13082 * the scanline counter from within the vblank interrupt handler.
13083 * However if queried just before the start of vblank we'll get an
13084 * answer that's slightly in the future.
13086 if (IS_GEN(dev_priv
, 2)) {
13087 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
13090 vtotal
= adjusted_mode
->crtc_vtotal
;
13091 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13094 crtc
->scanline_offset
= vtotal
- 1;
13095 } else if (HAS_DDI(dev_priv
) &&
13096 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
)) {
13097 crtc
->scanline_offset
= 2;
13099 crtc
->scanline_offset
= 1;
13102 static void intel_modeset_clear_plls(struct intel_atomic_state
*state
)
13104 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
13105 struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
13106 struct intel_crtc
*crtc
;
13109 if (!dev_priv
->display
.crtc_compute_clock
)
13112 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
13113 new_crtc_state
, i
) {
13114 struct intel_shared_dpll
*old_dpll
=
13115 old_crtc_state
->shared_dpll
;
13117 if (!needs_modeset(&new_crtc_state
->base
))
13120 new_crtc_state
->shared_dpll
= NULL
;
13125 intel_release_shared_dpll(old_dpll
, crtc
, &state
->base
);
13130 * This implements the workaround described in the "notes" section of the mode
13131 * set sequence documentation. When going from no pipes or single pipe to
13132 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13133 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13135 static int haswell_mode_set_planes_workaround(struct intel_atomic_state
*state
)
13137 struct intel_crtc_state
*crtc_state
;
13138 struct intel_crtc
*crtc
;
13139 struct intel_crtc_state
*first_crtc_state
= NULL
;
13140 struct intel_crtc_state
*other_crtc_state
= NULL
;
13141 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13144 /* look at all crtc's that are going to be enabled in during modeset */
13145 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13146 if (!crtc_state
->base
.active
||
13147 !needs_modeset(&crtc_state
->base
))
13150 if (first_crtc_state
) {
13151 other_crtc_state
= crtc_state
;
13154 first_crtc_state
= crtc_state
;
13155 first_pipe
= crtc
->pipe
;
13159 /* No workaround needed? */
13160 if (!first_crtc_state
)
13163 /* w/a possibly needed, check how many crtc's are already enabled. */
13164 for_each_intel_crtc(state
->base
.dev
, crtc
) {
13165 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
13166 if (IS_ERR(crtc_state
))
13167 return PTR_ERR(crtc_state
);
13169 crtc_state
->hsw_workaround_pipe
= INVALID_PIPE
;
13171 if (!crtc_state
->base
.active
||
13172 needs_modeset(&crtc_state
->base
))
13175 /* 2 or more enabled crtcs means no need for w/a */
13176 if (enabled_pipe
!= INVALID_PIPE
)
13179 enabled_pipe
= crtc
->pipe
;
13182 if (enabled_pipe
!= INVALID_PIPE
)
13183 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13184 else if (other_crtc_state
)
13185 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13190 static int intel_lock_all_pipes(struct drm_atomic_state
*state
)
13192 struct drm_crtc
*crtc
;
13194 /* Add all pipes to the state */
13195 for_each_crtc(state
->dev
, crtc
) {
13196 struct drm_crtc_state
*crtc_state
;
13198 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13199 if (IS_ERR(crtc_state
))
13200 return PTR_ERR(crtc_state
);
13206 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13208 struct drm_crtc
*crtc
;
13211 * Add all pipes to the state, and force
13212 * a modeset on all the active ones.
13214 for_each_crtc(state
->dev
, crtc
) {
13215 struct drm_crtc_state
*crtc_state
;
13218 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13219 if (IS_ERR(crtc_state
))
13220 return PTR_ERR(crtc_state
);
13222 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13225 crtc_state
->mode_changed
= true;
13227 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13231 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13239 static int intel_modeset_checks(struct intel_atomic_state
*state
)
13241 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
13242 struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
13243 struct intel_crtc
*crtc
;
13246 if (!check_digital_port_conflicts(state
)) {
13247 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13251 /* keep the current setting */
13252 if (!state
->cdclk
.force_min_cdclk_changed
)
13253 state
->cdclk
.force_min_cdclk
= dev_priv
->cdclk
.force_min_cdclk
;
13255 state
->modeset
= true;
13256 state
->active_crtcs
= dev_priv
->active_crtcs
;
13257 state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
13258 state
->cdclk
.actual
= dev_priv
->cdclk
.actual
;
13259 state
->cdclk
.pipe
= INVALID_PIPE
;
13261 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
13262 new_crtc_state
, i
) {
13263 if (new_crtc_state
->base
.active
)
13264 state
->active_crtcs
|= 1 << i
;
13266 state
->active_crtcs
&= ~(1 << i
);
13268 if (old_crtc_state
->base
.active
!= new_crtc_state
->base
.active
)
13269 state
->active_pipe_changes
|= drm_crtc_mask(&crtc
->base
);
13273 * See if the config requires any additional preparation, e.g.
13274 * to adjust global state with pipes off. We need to do this
13275 * here so we can get the modeset_pipe updated config for the new
13276 * mode set on this crtc. For other crtcs we need to use the
13277 * adjusted_mode bits in the crtc directly.
13279 if (dev_priv
->display
.modeset_calc_cdclk
) {
13282 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13287 * Writes to dev_priv->cdclk.logical must protected by
13288 * holding all the crtc locks, even if we don't end up
13289 * touching the hardware
13291 if (intel_cdclk_changed(&dev_priv
->cdclk
.logical
,
13292 &state
->cdclk
.logical
)) {
13293 ret
= intel_lock_all_pipes(&state
->base
);
13298 if (is_power_of_2(state
->active_crtcs
)) {
13299 struct drm_crtc
*crtc
;
13300 struct drm_crtc_state
*crtc_state
;
13302 pipe
= ilog2(state
->active_crtcs
);
13303 crtc
= &intel_get_crtc_for_pipe(dev_priv
, pipe
)->base
;
13304 crtc_state
= drm_atomic_get_new_crtc_state(&state
->base
, crtc
);
13305 if (crtc_state
&& needs_modeset(crtc_state
))
13306 pipe
= INVALID_PIPE
;
13308 pipe
= INVALID_PIPE
;
13311 /* All pipes must be switched off while we change the cdclk. */
13312 if (pipe
!= INVALID_PIPE
&&
13313 intel_cdclk_needs_cd2x_update(dev_priv
,
13314 &dev_priv
->cdclk
.actual
,
13315 &state
->cdclk
.actual
)) {
13316 ret
= intel_lock_all_pipes(&state
->base
);
13320 state
->cdclk
.pipe
= pipe
;
13321 } else if (intel_cdclk_needs_modeset(&dev_priv
->cdclk
.actual
,
13322 &state
->cdclk
.actual
)) {
13323 ret
= intel_modeset_all_pipes(&state
->base
);
13327 state
->cdclk
.pipe
= INVALID_PIPE
;
13330 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
13331 state
->cdclk
.logical
.cdclk
,
13332 state
->cdclk
.actual
.cdclk
);
13333 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
13334 state
->cdclk
.logical
.voltage_level
,
13335 state
->cdclk
.actual
.voltage_level
);
13338 intel_modeset_clear_plls(state
);
13340 if (IS_HASWELL(dev_priv
))
13341 return haswell_mode_set_planes_workaround(state
);
13347 * Handle calculation of various watermark data at the end of the atomic check
13348 * phase. The code here should be run after the per-crtc and per-plane 'check'
13349 * handlers to ensure that all derived state has been updated.
13351 static int calc_watermark_data(struct intel_atomic_state
*state
)
13353 struct drm_device
*dev
= state
->base
.dev
;
13354 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13356 /* Is there platform-specific watermark information to calculate? */
13357 if (dev_priv
->display
.compute_global_watermarks
)
13358 return dev_priv
->display
.compute_global_watermarks(state
);
13364 * intel_atomic_check - validate state object
13366 * @state: state to validate
13368 static int intel_atomic_check(struct drm_device
*dev
,
13369 struct drm_atomic_state
*_state
)
13371 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13372 struct intel_atomic_state
*state
= to_intel_atomic_state(_state
);
13373 struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
13374 struct intel_crtc
*crtc
;
13376 bool any_ms
= state
->cdclk
.force_min_cdclk_changed
;
13378 /* Catch I915_MODE_FLAG_INHERITED */
13379 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
13380 new_crtc_state
, i
) {
13381 if (new_crtc_state
->base
.mode
.private_flags
!=
13382 old_crtc_state
->base
.mode
.private_flags
)
13383 new_crtc_state
->base
.mode_changed
= true;
13386 ret
= drm_atomic_helper_check_modeset(dev
, &state
->base
);
13390 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
13391 new_crtc_state
, i
) {
13392 if (!needs_modeset(&new_crtc_state
->base
))
13395 if (!new_crtc_state
->base
.enable
) {
13400 ret
= intel_modeset_pipe_config(new_crtc_state
);
13404 if (intel_pipe_config_compare(dev_priv
, old_crtc_state
,
13405 new_crtc_state
, true)) {
13406 new_crtc_state
->base
.mode_changed
= false;
13407 new_crtc_state
->update_pipe
= true;
13410 if (needs_modeset(&new_crtc_state
->base
))
13414 ret
= drm_dp_mst_atomic_check(&state
->base
);
13419 ret
= intel_modeset_checks(state
);
13423 state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
13426 ret
= icl_add_linked_planes(state
);
13430 ret
= drm_atomic_helper_check_planes(dev
, &state
->base
);
13434 intel_fbc_choose_crtc(dev_priv
, state
);
13435 ret
= calc_watermark_data(state
);
13439 ret
= intel_bw_atomic_check(state
);
13443 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
13444 new_crtc_state
, i
) {
13445 if (!needs_modeset(&new_crtc_state
->base
) &&
13446 !new_crtc_state
->update_pipe
)
13449 intel_dump_pipe_config(new_crtc_state
, state
,
13450 needs_modeset(&new_crtc_state
->base
) ?
13451 "[modeset]" : "[fastset]");
13457 if (ret
== -EDEADLK
)
13461 * FIXME would probably be nice to know which crtc specifically
13462 * caused the failure, in cases where we can pinpoint it.
13464 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
13466 intel_dump_pipe_config(new_crtc_state
, state
, "[failed]");
13471 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
13472 struct drm_atomic_state
*state
)
13474 return drm_atomic_helper_prepare_planes(dev
, state
);
13477 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
13479 struct drm_device
*dev
= crtc
->base
.dev
;
13480 struct drm_vblank_crtc
*vblank
= &dev
->vblank
[drm_crtc_index(&crtc
->base
)];
13482 if (!vblank
->max_vblank_count
)
13483 return (u32
)drm_crtc_accurate_vblank_count(&crtc
->base
);
13485 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
13488 static void intel_update_crtc(struct drm_crtc
*crtc
,
13489 struct drm_atomic_state
*state
,
13490 struct drm_crtc_state
*old_crtc_state
,
13491 struct drm_crtc_state
*new_crtc_state
)
13493 struct drm_device
*dev
= crtc
->dev
;
13494 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13495 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13496 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(new_crtc_state
);
13497 bool modeset
= needs_modeset(new_crtc_state
);
13498 struct intel_plane_state
*new_plane_state
=
13499 intel_atomic_get_new_plane_state(to_intel_atomic_state(state
),
13500 to_intel_plane(crtc
->primary
));
13503 update_scanline_offset(pipe_config
);
13504 dev_priv
->display
.crtc_enable(pipe_config
, state
);
13506 /* vblanks work again, re-enable pipe CRC. */
13507 intel_crtc_enable_pipe_crc(intel_crtc
);
13509 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
),
13512 if (pipe_config
->update_pipe
)
13513 intel_encoders_update_pipe(crtc
, pipe_config
, state
);
13516 if (pipe_config
->update_pipe
&& !pipe_config
->enable_fbc
)
13517 intel_fbc_disable(intel_crtc
);
13518 else if (new_plane_state
)
13519 intel_fbc_enable(intel_crtc
, pipe_config
, new_plane_state
);
13521 intel_begin_crtc_commit(to_intel_atomic_state(state
), intel_crtc
);
13523 if (INTEL_GEN(dev_priv
) >= 9)
13524 skl_update_planes_on_crtc(to_intel_atomic_state(state
), intel_crtc
);
13526 i9xx_update_planes_on_crtc(to_intel_atomic_state(state
), intel_crtc
);
13528 intel_finish_crtc_commit(to_intel_atomic_state(state
), intel_crtc
);
13531 static void intel_update_crtcs(struct drm_atomic_state
*state
)
13533 struct drm_crtc
*crtc
;
13534 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13537 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13538 if (!new_crtc_state
->active
)
13541 intel_update_crtc(crtc
, state
, old_crtc_state
,
13546 static void skl_update_crtcs(struct drm_atomic_state
*state
)
13548 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13549 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13550 struct drm_crtc
*crtc
;
13551 struct intel_crtc
*intel_crtc
;
13552 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13553 struct intel_crtc_state
*cstate
;
13554 unsigned int updated
= 0;
13558 u8 hw_enabled_slices
= dev_priv
->wm
.skl_hw
.ddb
.enabled_slices
;
13559 u8 required_slices
= intel_state
->wm_results
.ddb
.enabled_slices
;
13560 struct skl_ddb_entry entries
[I915_MAX_PIPES
] = {};
13562 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
)
13563 /* ignore allocations for crtc's that have been turned off. */
13564 if (new_crtc_state
->active
)
13565 entries
[i
] = to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
;
13567 /* If 2nd DBuf slice required, enable it here */
13568 if (INTEL_GEN(dev_priv
) >= 11 && required_slices
> hw_enabled_slices
)
13569 icl_dbuf_slices_update(dev_priv
, required_slices
);
13572 * Whenever the number of active pipes changes, we need to make sure we
13573 * update the pipes in the right order so that their ddb allocations
13574 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
13575 * cause pipe underruns and other bad stuff.
13580 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13581 bool vbl_wait
= false;
13582 unsigned int cmask
= drm_crtc_mask(crtc
);
13584 intel_crtc
= to_intel_crtc(crtc
);
13585 cstate
= to_intel_crtc_state(new_crtc_state
);
13586 pipe
= intel_crtc
->pipe
;
13588 if (updated
& cmask
|| !cstate
->base
.active
)
13591 if (skl_ddb_allocation_overlaps(&cstate
->wm
.skl
.ddb
,
13593 INTEL_INFO(dev_priv
)->num_pipes
, i
))
13597 entries
[i
] = cstate
->wm
.skl
.ddb
;
13600 * If this is an already active pipe, it's DDB changed,
13601 * and this isn't the last pipe that needs updating
13602 * then we need to wait for a vblank to pass for the
13603 * new ddb allocation to take effect.
13605 if (!skl_ddb_entry_equal(&cstate
->wm
.skl
.ddb
,
13606 &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
) &&
13607 !new_crtc_state
->active_changed
&&
13608 intel_state
->wm_results
.dirty_pipes
!= updated
)
13611 intel_update_crtc(crtc
, state
, old_crtc_state
,
13615 intel_wait_for_vblank(dev_priv
, pipe
);
13619 } while (progress
);
13621 /* If 2nd DBuf slice is no more required disable it */
13622 if (INTEL_GEN(dev_priv
) >= 11 && required_slices
< hw_enabled_slices
)
13623 icl_dbuf_slices_update(dev_priv
, required_slices
);
13626 static void intel_atomic_helper_free_state(struct drm_i915_private
*dev_priv
)
13628 struct intel_atomic_state
*state
, *next
;
13629 struct llist_node
*freed
;
13631 freed
= llist_del_all(&dev_priv
->atomic_helper
.free_list
);
13632 llist_for_each_entry_safe(state
, next
, freed
, freed
)
13633 drm_atomic_state_put(&state
->base
);
13636 static void intel_atomic_helper_free_state_worker(struct work_struct
*work
)
13638 struct drm_i915_private
*dev_priv
=
13639 container_of(work
, typeof(*dev_priv
), atomic_helper
.free_work
);
13641 intel_atomic_helper_free_state(dev_priv
);
13644 static void intel_atomic_commit_fence_wait(struct intel_atomic_state
*intel_state
)
13646 struct wait_queue_entry wait_fence
, wait_reset
;
13647 struct drm_i915_private
*dev_priv
= to_i915(intel_state
->base
.dev
);
13649 init_wait_entry(&wait_fence
, 0);
13650 init_wait_entry(&wait_reset
, 0);
13652 prepare_to_wait(&intel_state
->commit_ready
.wait
,
13653 &wait_fence
, TASK_UNINTERRUPTIBLE
);
13654 prepare_to_wait(&dev_priv
->gpu_error
.wait_queue
,
13655 &wait_reset
, TASK_UNINTERRUPTIBLE
);
13658 if (i915_sw_fence_done(&intel_state
->commit_ready
)
13659 || test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
13664 finish_wait(&intel_state
->commit_ready
.wait
, &wait_fence
);
13665 finish_wait(&dev_priv
->gpu_error
.wait_queue
, &wait_reset
);
13668 static void intel_atomic_cleanup_work(struct work_struct
*work
)
13670 struct drm_atomic_state
*state
=
13671 container_of(work
, struct drm_atomic_state
, commit_work
);
13672 struct drm_i915_private
*i915
= to_i915(state
->dev
);
13674 drm_atomic_helper_cleanup_planes(&i915
->drm
, state
);
13675 drm_atomic_helper_commit_cleanup_done(state
);
13676 drm_atomic_state_put(state
);
13678 intel_atomic_helper_free_state(i915
);
13681 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
13683 struct drm_device
*dev
= state
->dev
;
13684 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13685 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13686 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13687 struct intel_crtc_state
*new_intel_crtc_state
, *old_intel_crtc_state
;
13688 struct drm_crtc
*crtc
;
13689 struct intel_crtc
*intel_crtc
;
13690 u64 put_domains
[I915_MAX_PIPES
] = {};
13691 intel_wakeref_t wakeref
= 0;
13694 intel_atomic_commit_fence_wait(intel_state
);
13696 drm_atomic_helper_wait_for_dependencies(state
);
13698 if (intel_state
->modeset
)
13699 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
13701 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13702 old_intel_crtc_state
= to_intel_crtc_state(old_crtc_state
);
13703 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13704 intel_crtc
= to_intel_crtc(crtc
);
13706 if (needs_modeset(new_crtc_state
) ||
13707 to_intel_crtc_state(new_crtc_state
)->update_pipe
) {
13709 put_domains
[intel_crtc
->pipe
] =
13710 modeset_get_crtc_power_domains(crtc
,
13711 new_intel_crtc_state
);
13714 if (!needs_modeset(new_crtc_state
))
13717 intel_pre_plane_update(old_intel_crtc_state
, new_intel_crtc_state
);
13719 if (old_crtc_state
->active
) {
13720 intel_crtc_disable_planes(intel_state
, intel_crtc
);
13723 * We need to disable pipe CRC before disabling the pipe,
13724 * or we race against vblank off.
13726 intel_crtc_disable_pipe_crc(intel_crtc
);
13728 dev_priv
->display
.crtc_disable(old_intel_crtc_state
, state
);
13729 intel_crtc
->active
= false;
13730 intel_fbc_disable(intel_crtc
);
13731 intel_disable_shared_dpll(old_intel_crtc_state
);
13734 * Underruns don't always raise
13735 * interrupts, so check manually.
13737 intel_check_cpu_fifo_underruns(dev_priv
);
13738 intel_check_pch_fifo_underruns(dev_priv
);
13740 /* FIXME unify this for all platforms */
13741 if (!new_crtc_state
->active
&&
13742 !HAS_GMCH(dev_priv
) &&
13743 dev_priv
->display
.initial_watermarks
)
13744 dev_priv
->display
.initial_watermarks(intel_state
,
13745 new_intel_crtc_state
);
13749 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
13750 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
13751 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(new_crtc_state
);
13753 if (intel_state
->modeset
) {
13754 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13756 intel_set_cdclk_pre_plane_update(dev_priv
,
13757 &intel_state
->cdclk
.actual
,
13758 &dev_priv
->cdclk
.actual
,
13759 intel_state
->cdclk
.pipe
);
13762 * SKL workaround: bspec recommends we disable the SAGV when we
13763 * have more then one pipe enabled
13765 if (!intel_can_enable_sagv(state
))
13766 intel_disable_sagv(dev_priv
);
13768 intel_modeset_verify_disabled(dev
, state
);
13771 /* Complete the events for pipes that have now been disabled */
13772 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13773 bool modeset
= needs_modeset(new_crtc_state
);
13775 /* Complete events for now disable pipes here. */
13776 if (modeset
&& !new_crtc_state
->active
&& new_crtc_state
->event
) {
13777 spin_lock_irq(&dev
->event_lock
);
13778 drm_crtc_send_vblank_event(crtc
, new_crtc_state
->event
);
13779 spin_unlock_irq(&dev
->event_lock
);
13781 new_crtc_state
->event
= NULL
;
13785 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13786 dev_priv
->display
.update_crtcs(state
);
13788 if (intel_state
->modeset
)
13789 intel_set_cdclk_post_plane_update(dev_priv
,
13790 &intel_state
->cdclk
.actual
,
13791 &dev_priv
->cdclk
.actual
,
13792 intel_state
->cdclk
.pipe
);
13794 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13795 * already, but still need the state for the delayed optimization. To
13797 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13798 * - schedule that vblank worker _before_ calling hw_done
13799 * - at the start of commit_tail, cancel it _synchrously
13800 * - switch over to the vblank wait helper in the core after that since
13801 * we don't need out special handling any more.
13803 drm_atomic_helper_wait_for_flip_done(dev
, state
);
13805 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13806 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13808 if (new_crtc_state
->active
&&
13809 !needs_modeset(new_crtc_state
) &&
13810 (new_intel_crtc_state
->base
.color_mgmt_changed
||
13811 new_intel_crtc_state
->update_pipe
))
13812 intel_color_load_luts(new_intel_crtc_state
);
13816 * Now that the vblank has passed, we can go ahead and program the
13817 * optimal watermarks on platforms that need two-step watermark
13820 * TODO: Move this (and other cleanup) to an async worker eventually.
13822 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13823 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13825 if (dev_priv
->display
.optimize_watermarks
)
13826 dev_priv
->display
.optimize_watermarks(intel_state
,
13827 new_intel_crtc_state
);
13830 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13831 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
13833 if (put_domains
[i
])
13834 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
13836 intel_modeset_verify_crtc(crtc
, state
, old_crtc_state
, new_crtc_state
);
13839 if (intel_state
->modeset
)
13840 intel_verify_planes(intel_state
);
13842 if (intel_state
->modeset
&& intel_can_enable_sagv(state
))
13843 intel_enable_sagv(dev_priv
);
13845 drm_atomic_helper_commit_hw_done(state
);
13847 if (intel_state
->modeset
) {
13848 /* As one of the primary mmio accessors, KMS has a high
13849 * likelihood of triggering bugs in unclaimed access. After we
13850 * finish modesetting, see if an error has been flagged, and if
13851 * so enable debugging for the next modeset - and hope we catch
13854 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv
->uncore
);
13855 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
, wakeref
);
13857 intel_runtime_pm_put(dev_priv
, intel_state
->wakeref
);
13860 * Defer the cleanup of the old state to a separate worker to not
13861 * impede the current task (userspace for blocking modesets) that
13862 * are executed inline. For out-of-line asynchronous modesets/flips,
13863 * deferring to a new worker seems overkill, but we would place a
13864 * schedule point (cond_resched()) here anyway to keep latencies
13867 INIT_WORK(&state
->commit_work
, intel_atomic_cleanup_work
);
13868 queue_work(system_highpri_wq
, &state
->commit_work
);
13871 static void intel_atomic_commit_work(struct work_struct
*work
)
13873 struct drm_atomic_state
*state
=
13874 container_of(work
, struct drm_atomic_state
, commit_work
);
13876 intel_atomic_commit_tail(state
);
13879 static int __i915_sw_fence_call
13880 intel_atomic_commit_ready(struct i915_sw_fence
*fence
,
13881 enum i915_sw_fence_notify notify
)
13883 struct intel_atomic_state
*state
=
13884 container_of(fence
, struct intel_atomic_state
, commit_ready
);
13887 case FENCE_COMPLETE
:
13888 /* we do blocking waits in the worker, nothing to do here */
13892 struct intel_atomic_helper
*helper
=
13893 &to_i915(state
->base
.dev
)->atomic_helper
;
13895 if (llist_add(&state
->freed
, &helper
->free_list
))
13896 schedule_work(&helper
->free_work
);
13901 return NOTIFY_DONE
;
13904 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
13906 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
13907 struct drm_plane
*plane
;
13910 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
)
13911 i915_gem_track_fb(intel_fb_obj(old_plane_state
->fb
),
13912 intel_fb_obj(new_plane_state
->fb
),
13913 to_intel_plane(plane
)->frontbuffer_bit
);
13917 * intel_atomic_commit - commit validated state object
13919 * @state: the top-level driver state object
13920 * @nonblock: nonblocking commit
13922 * This function commits a top-level state object that has been validated
13923 * with drm_atomic_helper_check().
13926 * Zero for success or -errno.
13928 static int intel_atomic_commit(struct drm_device
*dev
,
13929 struct drm_atomic_state
*state
,
13932 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13933 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13936 intel_state
->wakeref
= intel_runtime_pm_get(dev_priv
);
13938 drm_atomic_state_get(state
);
13939 i915_sw_fence_init(&intel_state
->commit_ready
,
13940 intel_atomic_commit_ready
);
13943 * The intel_legacy_cursor_update() fast path takes care
13944 * of avoiding the vblank waits for simple cursor
13945 * movement and flips. For cursor on/off and size changes,
13946 * we want to perform the vblank waits so that watermark
13947 * updates happen during the correct frames. Gen9+ have
13948 * double buffered watermarks and so shouldn't need this.
13950 * Unset state->legacy_cursor_update before the call to
13951 * drm_atomic_helper_setup_commit() because otherwise
13952 * drm_atomic_helper_wait_for_flip_done() is a noop and
13953 * we get FIFO underruns because we didn't wait
13956 * FIXME doing watermarks and fb cleanup from a vblank worker
13957 * (assuming we had any) would solve these problems.
13959 if (INTEL_GEN(dev_priv
) < 9 && state
->legacy_cursor_update
) {
13960 struct intel_crtc_state
*new_crtc_state
;
13961 struct intel_crtc
*crtc
;
13964 for_each_new_intel_crtc_in_state(intel_state
, crtc
, new_crtc_state
, i
)
13965 if (new_crtc_state
->wm
.need_postvbl_update
||
13966 new_crtc_state
->update_wm_post
)
13967 state
->legacy_cursor_update
= false;
13970 ret
= intel_atomic_prepare_commit(dev
, state
);
13972 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
13973 i915_sw_fence_commit(&intel_state
->commit_ready
);
13974 intel_runtime_pm_put(dev_priv
, intel_state
->wakeref
);
13978 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
13980 ret
= drm_atomic_helper_swap_state(state
, true);
13983 i915_sw_fence_commit(&intel_state
->commit_ready
);
13985 drm_atomic_helper_cleanup_planes(dev
, state
);
13986 intel_runtime_pm_put(dev_priv
, intel_state
->wakeref
);
13989 dev_priv
->wm
.distrust_bios_wm
= false;
13990 intel_shared_dpll_swap_state(state
);
13991 intel_atomic_track_fbs(state
);
13993 if (intel_state
->modeset
) {
13994 memcpy(dev_priv
->min_cdclk
, intel_state
->min_cdclk
,
13995 sizeof(intel_state
->min_cdclk
));
13996 memcpy(dev_priv
->min_voltage_level
,
13997 intel_state
->min_voltage_level
,
13998 sizeof(intel_state
->min_voltage_level
));
13999 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
14000 dev_priv
->cdclk
.force_min_cdclk
=
14001 intel_state
->cdclk
.force_min_cdclk
;
14003 intel_cdclk_swap_state(intel_state
);
14006 drm_atomic_state_get(state
);
14007 INIT_WORK(&state
->commit_work
, intel_atomic_commit_work
);
14009 i915_sw_fence_commit(&intel_state
->commit_ready
);
14010 if (nonblock
&& intel_state
->modeset
) {
14011 queue_work(dev_priv
->modeset_wq
, &state
->commit_work
);
14012 } else if (nonblock
) {
14013 queue_work(system_unbound_wq
, &state
->commit_work
);
14015 if (intel_state
->modeset
)
14016 flush_workqueue(dev_priv
->modeset_wq
);
14017 intel_atomic_commit_tail(state
);
14023 static const struct drm_crtc_funcs intel_crtc_funcs
= {
14024 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
14025 .set_config
= drm_atomic_helper_set_config
,
14026 .destroy
= intel_crtc_destroy
,
14027 .page_flip
= drm_atomic_helper_page_flip
,
14028 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
14029 .atomic_destroy_state
= intel_crtc_destroy_state
,
14030 .set_crc_source
= intel_crtc_set_crc_source
,
14031 .verify_crc_source
= intel_crtc_verify_crc_source
,
14032 .get_crc_sources
= intel_crtc_get_crc_sources
,
14035 struct wait_rps_boost
{
14036 struct wait_queue_entry wait
;
14038 struct drm_crtc
*crtc
;
14039 struct i915_request
*request
;
14042 static int do_rps_boost(struct wait_queue_entry
*_wait
,
14043 unsigned mode
, int sync
, void *key
)
14045 struct wait_rps_boost
*wait
= container_of(_wait
, typeof(*wait
), wait
);
14046 struct i915_request
*rq
= wait
->request
;
14049 * If we missed the vblank, but the request is already running it
14050 * is reasonable to assume that it will complete before the next
14051 * vblank without our intervention, so leave RPS alone.
14053 if (!i915_request_started(rq
))
14054 gen6_rps_boost(rq
);
14055 i915_request_put(rq
);
14057 drm_crtc_vblank_put(wait
->crtc
);
14059 list_del(&wait
->wait
.entry
);
14064 static void add_rps_boost_after_vblank(struct drm_crtc
*crtc
,
14065 struct dma_fence
*fence
)
14067 struct wait_rps_boost
*wait
;
14069 if (!dma_fence_is_i915(fence
))
14072 if (INTEL_GEN(to_i915(crtc
->dev
)) < 6)
14075 if (drm_crtc_vblank_get(crtc
))
14078 wait
= kmalloc(sizeof(*wait
), GFP_KERNEL
);
14080 drm_crtc_vblank_put(crtc
);
14084 wait
->request
= to_request(dma_fence_get(fence
));
14087 wait
->wait
.func
= do_rps_boost
;
14088 wait
->wait
.flags
= 0;
14090 add_wait_queue(drm_crtc_vblank_waitqueue(crtc
), &wait
->wait
);
14093 static int intel_plane_pin_fb(struct intel_plane_state
*plane_state
)
14095 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
14096 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
14097 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
14098 struct i915_vma
*vma
;
14100 if (plane
->id
== PLANE_CURSOR
&&
14101 INTEL_INFO(dev_priv
)->display
.cursor_needs_physical
) {
14102 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14103 const int align
= intel_cursor_alignment(dev_priv
);
14106 err
= i915_gem_object_attach_phys(obj
, align
);
14111 vma
= intel_pin_and_fence_fb_obj(fb
,
14112 &plane_state
->view
,
14113 intel_plane_uses_fence(plane_state
),
14114 &plane_state
->flags
);
14116 return PTR_ERR(vma
);
14118 plane_state
->vma
= vma
;
14123 static void intel_plane_unpin_fb(struct intel_plane_state
*old_plane_state
)
14125 struct i915_vma
*vma
;
14127 vma
= fetch_and_zero(&old_plane_state
->vma
);
14129 intel_unpin_fb_vma(vma
, old_plane_state
->flags
);
14132 static void fb_obj_bump_render_priority(struct drm_i915_gem_object
*obj
)
14134 struct i915_sched_attr attr
= {
14135 .priority
= I915_PRIORITY_DISPLAY
,
14138 i915_gem_object_wait_priority(obj
, 0, &attr
);
14142 * intel_prepare_plane_fb - Prepare fb for usage on plane
14143 * @plane: drm plane to prepare for
14144 * @new_state: the plane state being prepared
14146 * Prepares a framebuffer for usage on a display plane. Generally this
14147 * involves pinning the underlying object and updating the frontbuffer tracking
14148 * bits. Some older platforms need special physical address handling for
14151 * Must be called with struct_mutex held.
14153 * Returns 0 on success, negative error code on failure.
14156 intel_prepare_plane_fb(struct drm_plane
*plane
,
14157 struct drm_plane_state
*new_state
)
14159 struct intel_atomic_state
*intel_state
=
14160 to_intel_atomic_state(new_state
->state
);
14161 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14162 struct drm_framebuffer
*fb
= new_state
->fb
;
14163 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14164 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
14168 struct drm_crtc_state
*crtc_state
=
14169 drm_atomic_get_new_crtc_state(new_state
->state
,
14170 plane
->state
->crtc
);
14172 /* Big Hammer, we also need to ensure that any pending
14173 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14174 * current scanout is retired before unpinning the old
14175 * framebuffer. Note that we rely on userspace rendering
14176 * into the buffer attached to the pipe they are waiting
14177 * on. If not, userspace generates a GPU hang with IPEHR
14178 * point to the MI_WAIT_FOR_EVENT.
14180 * This should only fail upon a hung GPU, in which case we
14181 * can safely continue.
14183 if (needs_modeset(crtc_state
)) {
14184 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14185 old_obj
->resv
, NULL
,
14193 if (new_state
->fence
) { /* explicit fencing */
14194 ret
= i915_sw_fence_await_dma_fence(&intel_state
->commit_ready
,
14196 I915_FENCE_TIMEOUT
,
14205 ret
= i915_gem_object_pin_pages(obj
);
14209 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
14211 i915_gem_object_unpin_pages(obj
);
14215 ret
= intel_plane_pin_fb(to_intel_plane_state(new_state
));
14217 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14218 i915_gem_object_unpin_pages(obj
);
14222 fb_obj_bump_render_priority(obj
);
14223 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
14225 if (!new_state
->fence
) { /* implicit fencing */
14226 struct dma_fence
*fence
;
14228 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14230 false, I915_FENCE_TIMEOUT
,
14235 fence
= reservation_object_get_excl_rcu(obj
->resv
);
14237 add_rps_boost_after_vblank(new_state
->crtc
, fence
);
14238 dma_fence_put(fence
);
14241 add_rps_boost_after_vblank(new_state
->crtc
, new_state
->fence
);
14245 * We declare pageflips to be interactive and so merit a small bias
14246 * towards upclocking to deliver the frame on time. By only changing
14247 * the RPS thresholds to sample more regularly and aim for higher
14248 * clocks we can hopefully deliver low power workloads (like kodi)
14249 * that are not quite steady state without resorting to forcing
14250 * maximum clocks following a vblank miss (see do_rps_boost()).
14252 if (!intel_state
->rps_interactive
) {
14253 intel_rps_mark_interactive(dev_priv
, true);
14254 intel_state
->rps_interactive
= true;
14261 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14262 * @plane: drm plane to clean up for
14263 * @old_state: the state from the previous modeset
14265 * Cleans up a framebuffer that has just been removed from a plane.
14267 * Must be called with struct_mutex held.
14270 intel_cleanup_plane_fb(struct drm_plane
*plane
,
14271 struct drm_plane_state
*old_state
)
14273 struct intel_atomic_state
*intel_state
=
14274 to_intel_atomic_state(old_state
->state
);
14275 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14277 if (intel_state
->rps_interactive
) {
14278 intel_rps_mark_interactive(dev_priv
, false);
14279 intel_state
->rps_interactive
= false;
14282 /* Should only be called after a successful intel_prepare_plane_fb()! */
14283 mutex_lock(&dev_priv
->drm
.struct_mutex
);
14284 intel_plane_unpin_fb(to_intel_plane_state(old_state
));
14285 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14289 skl_max_scale(const struct intel_crtc_state
*crtc_state
,
14292 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
14293 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14294 int max_scale
, mult
;
14295 int crtc_clock
, max_dotclk
, tmpclk1
, tmpclk2
;
14297 if (!crtc_state
->base
.enable
)
14298 return DRM_PLANE_HELPER_NO_SCALING
;
14300 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
14301 max_dotclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
.logical
.cdclk
;
14303 if (IS_GEMINILAKE(dev_priv
) || INTEL_GEN(dev_priv
) >= 10)
14306 if (WARN_ON_ONCE(!crtc_clock
|| max_dotclk
< crtc_clock
))
14307 return DRM_PLANE_HELPER_NO_SCALING
;
14310 * skl max scale is lower of:
14311 * close to 3 but not 3, -1 is for that purpose
14315 mult
= is_planar_yuv_format(pixel_format
) ? 2 : 3;
14316 tmpclk1
= (1 << 16) * mult
- 1;
14317 tmpclk2
= (1 << 8) * ((max_dotclk
<< 8) / crtc_clock
);
14318 max_scale
= min(tmpclk1
, tmpclk2
);
14323 static void intel_begin_crtc_commit(struct intel_atomic_state
*state
,
14324 struct intel_crtc
*crtc
)
14326 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14327 struct intel_crtc_state
*old_crtc_state
=
14328 intel_atomic_get_old_crtc_state(state
, crtc
);
14329 struct intel_crtc_state
*new_crtc_state
=
14330 intel_atomic_get_new_crtc_state(state
, crtc
);
14331 bool modeset
= needs_modeset(&new_crtc_state
->base
);
14333 /* Perform vblank evasion around commit operation */
14334 intel_pipe_update_start(new_crtc_state
);
14339 if (new_crtc_state
->base
.color_mgmt_changed
||
14340 new_crtc_state
->update_pipe
)
14341 intel_color_commit(new_crtc_state
);
14343 if (new_crtc_state
->update_pipe
)
14344 intel_update_pipe_config(old_crtc_state
, new_crtc_state
);
14345 else if (INTEL_GEN(dev_priv
) >= 9)
14346 skl_detach_scalers(new_crtc_state
);
14348 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
14349 bdw_set_pipemisc(new_crtc_state
);
14352 if (dev_priv
->display
.atomic_update_watermarks
)
14353 dev_priv
->display
.atomic_update_watermarks(state
,
14357 void intel_crtc_arm_fifo_underrun(struct intel_crtc
*crtc
,
14358 struct intel_crtc_state
*crtc_state
)
14360 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14362 if (!IS_GEN(dev_priv
, 2))
14363 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
14365 if (crtc_state
->has_pch_encoder
) {
14366 enum pipe pch_transcoder
=
14367 intel_crtc_pch_transcoder(crtc
);
14369 intel_set_pch_fifo_underrun_reporting(dev_priv
, pch_transcoder
, true);
14373 static void intel_finish_crtc_commit(struct intel_atomic_state
*state
,
14374 struct intel_crtc
*crtc
)
14376 struct intel_crtc_state
*old_crtc_state
=
14377 intel_atomic_get_old_crtc_state(state
, crtc
);
14378 struct intel_crtc_state
*new_crtc_state
=
14379 intel_atomic_get_new_crtc_state(state
, crtc
);
14381 intel_pipe_update_end(new_crtc_state
);
14383 if (new_crtc_state
->update_pipe
&&
14384 !needs_modeset(&new_crtc_state
->base
) &&
14385 old_crtc_state
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
)
14386 intel_crtc_arm_fifo_underrun(crtc
, new_crtc_state
);
14390 * intel_plane_destroy - destroy a plane
14391 * @plane: plane to destroy
14393 * Common destruction function for all types of planes (primary, cursor,
14396 void intel_plane_destroy(struct drm_plane
*plane
)
14398 drm_plane_cleanup(plane
);
14399 kfree(to_intel_plane(plane
));
14402 static bool i8xx_plane_format_mod_supported(struct drm_plane
*_plane
,
14403 u32 format
, u64 modifier
)
14405 switch (modifier
) {
14406 case DRM_FORMAT_MOD_LINEAR
:
14407 case I915_FORMAT_MOD_X_TILED
:
14414 case DRM_FORMAT_C8
:
14415 case DRM_FORMAT_RGB565
:
14416 case DRM_FORMAT_XRGB1555
:
14417 case DRM_FORMAT_XRGB8888
:
14418 return modifier
== DRM_FORMAT_MOD_LINEAR
||
14419 modifier
== I915_FORMAT_MOD_X_TILED
;
14425 static bool i965_plane_format_mod_supported(struct drm_plane
*_plane
,
14426 u32 format
, u64 modifier
)
14428 switch (modifier
) {
14429 case DRM_FORMAT_MOD_LINEAR
:
14430 case I915_FORMAT_MOD_X_TILED
:
14437 case DRM_FORMAT_C8
:
14438 case DRM_FORMAT_RGB565
:
14439 case DRM_FORMAT_XRGB8888
:
14440 case DRM_FORMAT_XBGR8888
:
14441 case DRM_FORMAT_XRGB2101010
:
14442 case DRM_FORMAT_XBGR2101010
:
14443 return modifier
== DRM_FORMAT_MOD_LINEAR
||
14444 modifier
== I915_FORMAT_MOD_X_TILED
;
14450 static bool intel_cursor_format_mod_supported(struct drm_plane
*_plane
,
14451 u32 format
, u64 modifier
)
14453 return modifier
== DRM_FORMAT_MOD_LINEAR
&&
14454 format
== DRM_FORMAT_ARGB8888
;
14457 static const struct drm_plane_funcs i965_plane_funcs
= {
14458 .update_plane
= drm_atomic_helper_update_plane
,
14459 .disable_plane
= drm_atomic_helper_disable_plane
,
14460 .destroy
= intel_plane_destroy
,
14461 .atomic_get_property
= intel_plane_atomic_get_property
,
14462 .atomic_set_property
= intel_plane_atomic_set_property
,
14463 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14464 .atomic_destroy_state
= intel_plane_destroy_state
,
14465 .format_mod_supported
= i965_plane_format_mod_supported
,
14468 static const struct drm_plane_funcs i8xx_plane_funcs
= {
14469 .update_plane
= drm_atomic_helper_update_plane
,
14470 .disable_plane
= drm_atomic_helper_disable_plane
,
14471 .destroy
= intel_plane_destroy
,
14472 .atomic_get_property
= intel_plane_atomic_get_property
,
14473 .atomic_set_property
= intel_plane_atomic_set_property
,
14474 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14475 .atomic_destroy_state
= intel_plane_destroy_state
,
14476 .format_mod_supported
= i8xx_plane_format_mod_supported
,
14480 intel_legacy_cursor_update(struct drm_plane
*plane
,
14481 struct drm_crtc
*crtc
,
14482 struct drm_framebuffer
*fb
,
14483 int crtc_x
, int crtc_y
,
14484 unsigned int crtc_w
, unsigned int crtc_h
,
14485 u32 src_x
, u32 src_y
,
14486 u32 src_w
, u32 src_h
,
14487 struct drm_modeset_acquire_ctx
*ctx
)
14489 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
14491 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
14492 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
14493 struct drm_framebuffer
*old_fb
;
14494 struct intel_crtc_state
*crtc_state
=
14495 to_intel_crtc_state(crtc
->state
);
14496 struct intel_crtc_state
*new_crtc_state
;
14499 * When crtc is inactive or there is a modeset pending,
14500 * wait for it to complete in the slowpath
14502 if (!crtc_state
->base
.active
|| needs_modeset(&crtc_state
->base
) ||
14503 crtc_state
->update_pipe
)
14506 old_plane_state
= plane
->state
;
14508 * Don't do an async update if there is an outstanding commit modifying
14509 * the plane. This prevents our async update's changes from getting
14510 * overridden by a previous synchronous update's state.
14512 if (old_plane_state
->commit
&&
14513 !try_wait_for_completion(&old_plane_state
->commit
->hw_done
))
14517 * If any parameters change that may affect watermarks,
14518 * take the slowpath. Only changing fb or position should be
14521 if (old_plane_state
->crtc
!= crtc
||
14522 old_plane_state
->src_w
!= src_w
||
14523 old_plane_state
->src_h
!= src_h
||
14524 old_plane_state
->crtc_w
!= crtc_w
||
14525 old_plane_state
->crtc_h
!= crtc_h
||
14526 !old_plane_state
->fb
!= !fb
)
14529 new_plane_state
= intel_plane_duplicate_state(plane
);
14530 if (!new_plane_state
)
14533 new_crtc_state
= to_intel_crtc_state(intel_crtc_duplicate_state(crtc
));
14534 if (!new_crtc_state
) {
14539 drm_atomic_set_fb_for_plane(new_plane_state
, fb
);
14541 new_plane_state
->src_x
= src_x
;
14542 new_plane_state
->src_y
= src_y
;
14543 new_plane_state
->src_w
= src_w
;
14544 new_plane_state
->src_h
= src_h
;
14545 new_plane_state
->crtc_x
= crtc_x
;
14546 new_plane_state
->crtc_y
= crtc_y
;
14547 new_plane_state
->crtc_w
= crtc_w
;
14548 new_plane_state
->crtc_h
= crtc_h
;
14550 ret
= intel_plane_atomic_check_with_state(crtc_state
, new_crtc_state
,
14551 to_intel_plane_state(old_plane_state
),
14552 to_intel_plane_state(new_plane_state
));
14556 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
14560 ret
= intel_plane_pin_fb(to_intel_plane_state(new_plane_state
));
14564 intel_fb_obj_flush(intel_fb_obj(fb
), ORIGIN_FLIP
);
14566 old_fb
= old_plane_state
->fb
;
14567 i915_gem_track_fb(intel_fb_obj(old_fb
), intel_fb_obj(fb
),
14568 intel_plane
->frontbuffer_bit
);
14570 /* Swap plane state */
14571 plane
->state
= new_plane_state
;
14574 * We cannot swap crtc_state as it may be in use by an atomic commit or
14575 * page flip that's running simultaneously. If we swap crtc_state and
14576 * destroy the old state, we will cause a use-after-free there.
14578 * Only update active_planes, which is needed for our internal
14579 * bookkeeping. Either value will do the right thing when updating
14580 * planes atomically. If the cursor was part of the atomic update then
14581 * we would have taken the slowpath.
14583 crtc_state
->active_planes
= new_crtc_state
->active_planes
;
14585 if (plane
->state
->visible
)
14586 intel_update_plane(intel_plane
, crtc_state
,
14587 to_intel_plane_state(plane
->state
));
14589 intel_disable_plane(intel_plane
, crtc_state
);
14591 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state
));
14594 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14596 if (new_crtc_state
)
14597 intel_crtc_destroy_state(crtc
, &new_crtc_state
->base
);
14599 intel_plane_destroy_state(plane
, new_plane_state
);
14601 intel_plane_destroy_state(plane
, old_plane_state
);
14605 return drm_atomic_helper_update_plane(plane
, crtc
, fb
,
14606 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
14607 src_x
, src_y
, src_w
, src_h
, ctx
);
14610 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
14611 .update_plane
= intel_legacy_cursor_update
,
14612 .disable_plane
= drm_atomic_helper_disable_plane
,
14613 .destroy
= intel_plane_destroy
,
14614 .atomic_get_property
= intel_plane_atomic_get_property
,
14615 .atomic_set_property
= intel_plane_atomic_set_property
,
14616 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14617 .atomic_destroy_state
= intel_plane_destroy_state
,
14618 .format_mod_supported
= intel_cursor_format_mod_supported
,
14621 static bool i9xx_plane_has_fbc(struct drm_i915_private
*dev_priv
,
14622 enum i9xx_plane_id i9xx_plane
)
14624 if (!HAS_FBC(dev_priv
))
14627 if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
14628 return i9xx_plane
== PLANE_A
; /* tied to pipe A */
14629 else if (IS_IVYBRIDGE(dev_priv
))
14630 return i9xx_plane
== PLANE_A
|| i9xx_plane
== PLANE_B
||
14631 i9xx_plane
== PLANE_C
;
14632 else if (INTEL_GEN(dev_priv
) >= 4)
14633 return i9xx_plane
== PLANE_A
|| i9xx_plane
== PLANE_B
;
14635 return i9xx_plane
== PLANE_A
;
14638 static struct intel_plane
*
14639 intel_primary_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14641 struct intel_plane
*plane
;
14642 const struct drm_plane_funcs
*plane_funcs
;
14643 unsigned int supported_rotations
;
14644 unsigned int possible_crtcs
;
14645 const u64
*modifiers
;
14646 const u32
*formats
;
14650 if (INTEL_GEN(dev_priv
) >= 9)
14651 return skl_universal_plane_create(dev_priv
, pipe
,
14654 plane
= intel_plane_alloc();
14658 plane
->pipe
= pipe
;
14660 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14661 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14663 if (HAS_FBC(dev_priv
) && INTEL_GEN(dev_priv
) < 4)
14664 plane
->i9xx_plane
= (enum i9xx_plane_id
) !pipe
;
14666 plane
->i9xx_plane
= (enum i9xx_plane_id
) pipe
;
14667 plane
->id
= PLANE_PRIMARY
;
14668 plane
->frontbuffer_bit
= INTEL_FRONTBUFFER(pipe
, plane
->id
);
14670 plane
->has_fbc
= i9xx_plane_has_fbc(dev_priv
, plane
->i9xx_plane
);
14671 if (plane
->has_fbc
) {
14672 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
14674 fbc
->possible_framebuffer_bits
|= plane
->frontbuffer_bit
;
14677 if (INTEL_GEN(dev_priv
) >= 4) {
14678 formats
= i965_primary_formats
;
14679 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14680 modifiers
= i9xx_format_modifiers
;
14682 plane
->max_stride
= i9xx_plane_max_stride
;
14683 plane
->update_plane
= i9xx_update_plane
;
14684 plane
->disable_plane
= i9xx_disable_plane
;
14685 plane
->get_hw_state
= i9xx_plane_get_hw_state
;
14686 plane
->check_plane
= i9xx_plane_check
;
14688 plane_funcs
= &i965_plane_funcs
;
14690 formats
= i8xx_primary_formats
;
14691 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
14692 modifiers
= i9xx_format_modifiers
;
14694 plane
->max_stride
= i9xx_plane_max_stride
;
14695 plane
->update_plane
= i9xx_update_plane
;
14696 plane
->disable_plane
= i9xx_disable_plane
;
14697 plane
->get_hw_state
= i9xx_plane_get_hw_state
;
14698 plane
->check_plane
= i9xx_plane_check
;
14700 plane_funcs
= &i8xx_plane_funcs
;
14703 possible_crtcs
= BIT(pipe
);
14705 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
14706 ret
= drm_universal_plane_init(&dev_priv
->drm
, &plane
->base
,
14707 possible_crtcs
, plane_funcs
,
14708 formats
, num_formats
, modifiers
,
14709 DRM_PLANE_TYPE_PRIMARY
,
14710 "primary %c", pipe_name(pipe
));
14712 ret
= drm_universal_plane_init(&dev_priv
->drm
, &plane
->base
,
14713 possible_crtcs
, plane_funcs
,
14714 formats
, num_formats
, modifiers
,
14715 DRM_PLANE_TYPE_PRIMARY
,
14717 plane_name(plane
->i9xx_plane
));
14721 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
14722 supported_rotations
=
14723 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
|
14724 DRM_MODE_REFLECT_X
;
14725 } else if (INTEL_GEN(dev_priv
) >= 4) {
14726 supported_rotations
=
14727 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
;
14729 supported_rotations
= DRM_MODE_ROTATE_0
;
14732 if (INTEL_GEN(dev_priv
) >= 4)
14733 drm_plane_create_rotation_property(&plane
->base
,
14735 supported_rotations
);
14737 drm_plane_helper_add(&plane
->base
, &intel_plane_helper_funcs
);
14742 intel_plane_free(plane
);
14744 return ERR_PTR(ret
);
14747 static struct intel_plane
*
14748 intel_cursor_plane_create(struct drm_i915_private
*dev_priv
,
14751 unsigned int possible_crtcs
;
14752 struct intel_plane
*cursor
;
14755 cursor
= intel_plane_alloc();
14756 if (IS_ERR(cursor
))
14759 cursor
->pipe
= pipe
;
14760 cursor
->i9xx_plane
= (enum i9xx_plane_id
) pipe
;
14761 cursor
->id
= PLANE_CURSOR
;
14762 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER(pipe
, cursor
->id
);
14764 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
14765 cursor
->max_stride
= i845_cursor_max_stride
;
14766 cursor
->update_plane
= i845_update_cursor
;
14767 cursor
->disable_plane
= i845_disable_cursor
;
14768 cursor
->get_hw_state
= i845_cursor_get_hw_state
;
14769 cursor
->check_plane
= i845_check_cursor
;
14771 cursor
->max_stride
= i9xx_cursor_max_stride
;
14772 cursor
->update_plane
= i9xx_update_cursor
;
14773 cursor
->disable_plane
= i9xx_disable_cursor
;
14774 cursor
->get_hw_state
= i9xx_cursor_get_hw_state
;
14775 cursor
->check_plane
= i9xx_check_cursor
;
14778 cursor
->cursor
.base
= ~0;
14779 cursor
->cursor
.cntl
= ~0;
14781 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
) || HAS_CUR_FBC(dev_priv
))
14782 cursor
->cursor
.size
= ~0;
14784 possible_crtcs
= BIT(pipe
);
14786 ret
= drm_universal_plane_init(&dev_priv
->drm
, &cursor
->base
,
14787 possible_crtcs
, &intel_cursor_plane_funcs
,
14788 intel_cursor_formats
,
14789 ARRAY_SIZE(intel_cursor_formats
),
14790 cursor_format_modifiers
,
14791 DRM_PLANE_TYPE_CURSOR
,
14792 "cursor %c", pipe_name(pipe
));
14796 if (INTEL_GEN(dev_priv
) >= 4)
14797 drm_plane_create_rotation_property(&cursor
->base
,
14799 DRM_MODE_ROTATE_0
|
14800 DRM_MODE_ROTATE_180
);
14802 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14807 intel_plane_free(cursor
);
14809 return ERR_PTR(ret
);
14812 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
14813 struct intel_crtc_state
*crtc_state
)
14815 struct intel_crtc_scaler_state
*scaler_state
=
14816 &crtc_state
->scaler_state
;
14817 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14820 crtc
->num_scalers
= RUNTIME_INFO(dev_priv
)->num_scalers
[crtc
->pipe
];
14821 if (!crtc
->num_scalers
)
14824 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
14825 struct intel_scaler
*scaler
= &scaler_state
->scalers
[i
];
14827 scaler
->in_use
= 0;
14831 scaler_state
->scaler_id
= -1;
14834 static int intel_crtc_init(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14836 struct intel_crtc
*intel_crtc
;
14837 struct intel_crtc_state
*crtc_state
= NULL
;
14838 struct intel_plane
*primary
= NULL
;
14839 struct intel_plane
*cursor
= NULL
;
14842 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14846 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14851 __drm_atomic_helper_crtc_reset(&intel_crtc
->base
, &crtc_state
->base
);
14852 intel_crtc
->config
= crtc_state
;
14854 primary
= intel_primary_plane_create(dev_priv
, pipe
);
14855 if (IS_ERR(primary
)) {
14856 ret
= PTR_ERR(primary
);
14859 intel_crtc
->plane_ids_mask
|= BIT(primary
->id
);
14861 for_each_sprite(dev_priv
, pipe
, sprite
) {
14862 struct intel_plane
*plane
;
14864 plane
= intel_sprite_plane_create(dev_priv
, pipe
, sprite
);
14865 if (IS_ERR(plane
)) {
14866 ret
= PTR_ERR(plane
);
14869 intel_crtc
->plane_ids_mask
|= BIT(plane
->id
);
14872 cursor
= intel_cursor_plane_create(dev_priv
, pipe
);
14873 if (IS_ERR(cursor
)) {
14874 ret
= PTR_ERR(cursor
);
14877 intel_crtc
->plane_ids_mask
|= BIT(cursor
->id
);
14879 ret
= drm_crtc_init_with_planes(&dev_priv
->drm
, &intel_crtc
->base
,
14880 &primary
->base
, &cursor
->base
,
14882 "pipe %c", pipe_name(pipe
));
14886 intel_crtc
->pipe
= pipe
;
14888 /* initialize shared scalers */
14889 intel_crtc_init_scalers(intel_crtc
, crtc_state
);
14891 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->pipe_to_crtc_mapping
) ||
14892 dev_priv
->pipe_to_crtc_mapping
[pipe
] != NULL
);
14893 dev_priv
->pipe_to_crtc_mapping
[pipe
] = intel_crtc
;
14895 if (INTEL_GEN(dev_priv
) < 9) {
14896 enum i9xx_plane_id i9xx_plane
= primary
->i9xx_plane
;
14898 BUG_ON(i9xx_plane
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14899 dev_priv
->plane_to_crtc_mapping
[i9xx_plane
] != NULL
);
14900 dev_priv
->plane_to_crtc_mapping
[i9xx_plane
] = intel_crtc
;
14903 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14905 intel_color_init(intel_crtc
);
14907 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14913 * drm_mode_config_cleanup() will free up any
14914 * crtcs/planes already initialized.
14922 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device
*dev
, void *data
,
14923 struct drm_file
*file
)
14925 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14926 struct drm_crtc
*drmmode_crtc
;
14927 struct intel_crtc
*crtc
;
14929 drmmode_crtc
= drm_crtc_find(dev
, file
, pipe_from_crtc_id
->crtc_id
);
14933 crtc
= to_intel_crtc(drmmode_crtc
);
14934 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14939 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14941 struct drm_device
*dev
= encoder
->base
.dev
;
14942 struct intel_encoder
*source_encoder
;
14943 int index_mask
= 0;
14946 for_each_intel_encoder(dev
, source_encoder
) {
14947 if (encoders_cloneable(encoder
, source_encoder
))
14948 index_mask
|= (1 << entry
);
14956 static bool ilk_has_edp_a(struct drm_i915_private
*dev_priv
)
14958 if (!IS_MOBILE(dev_priv
))
14961 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14964 if (IS_GEN(dev_priv
, 5) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14970 static bool intel_ddi_crt_present(struct drm_i915_private
*dev_priv
)
14972 if (INTEL_GEN(dev_priv
) >= 9)
14975 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
14978 if (HAS_PCH_LPT_H(dev_priv
) &&
14979 I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
14982 /* DDI E can't be used if DDI A requires 4 lanes */
14983 if (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
14986 if (!dev_priv
->vbt
.int_crt_support
)
14992 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
)
14997 if (HAS_DDI(dev_priv
))
15000 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15001 * everywhere where registers can be write protected.
15003 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15008 for (pps_idx
= 0; pps_idx
< pps_num
; pps_idx
++) {
15009 u32 val
= I915_READ(PP_CONTROL(pps_idx
));
15011 val
= (val
& ~PANEL_UNLOCK_MASK
) | PANEL_UNLOCK_REGS
;
15012 I915_WRITE(PP_CONTROL(pps_idx
), val
);
15016 static void intel_pps_init(struct drm_i915_private
*dev_priv
)
15018 if (HAS_PCH_SPLIT(dev_priv
) || IS_GEN9_LP(dev_priv
))
15019 dev_priv
->pps_mmio_base
= PCH_PPS_BASE
;
15020 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15021 dev_priv
->pps_mmio_base
= VLV_PPS_BASE
;
15023 dev_priv
->pps_mmio_base
= PPS_BASE
;
15025 intel_pps_unlock_regs_wa(dev_priv
);
15028 static void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
15030 struct intel_encoder
*encoder
;
15031 bool dpd_is_edp
= false;
15033 intel_pps_init(dev_priv
);
15035 if (!HAS_DISPLAY(dev_priv
))
15038 if (IS_ELKHARTLAKE(dev_priv
)) {
15039 intel_ddi_init(dev_priv
, PORT_A
);
15040 intel_ddi_init(dev_priv
, PORT_B
);
15041 intel_ddi_init(dev_priv
, PORT_C
);
15042 icl_dsi_init(dev_priv
);
15043 } else if (INTEL_GEN(dev_priv
) >= 11) {
15044 intel_ddi_init(dev_priv
, PORT_A
);
15045 intel_ddi_init(dev_priv
, PORT_B
);
15046 intel_ddi_init(dev_priv
, PORT_C
);
15047 intel_ddi_init(dev_priv
, PORT_D
);
15048 intel_ddi_init(dev_priv
, PORT_E
);
15050 * On some ICL SKUs port F is not present. No strap bits for
15051 * this, so rely on VBT.
15052 * Work around broken VBTs on SKUs known to have no port F.
15054 if (IS_ICL_WITH_PORT_F(dev_priv
) &&
15055 intel_bios_is_port_present(dev_priv
, PORT_F
))
15056 intel_ddi_init(dev_priv
, PORT_F
);
15058 icl_dsi_init(dev_priv
);
15059 } else if (IS_GEN9_LP(dev_priv
)) {
15061 * FIXME: Broxton doesn't support port detection via the
15062 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15063 * detect the ports.
15065 intel_ddi_init(dev_priv
, PORT_A
);
15066 intel_ddi_init(dev_priv
, PORT_B
);
15067 intel_ddi_init(dev_priv
, PORT_C
);
15069 vlv_dsi_init(dev_priv
);
15070 } else if (HAS_DDI(dev_priv
)) {
15073 if (intel_ddi_crt_present(dev_priv
))
15074 intel_crt_init(dev_priv
);
15077 * Haswell uses DDI functions to detect digital outputs.
15078 * On SKL pre-D0 the strap isn't connected, so we assume
15081 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
15082 /* WaIgnoreDDIAStrap: skl */
15083 if (found
|| IS_GEN9_BC(dev_priv
))
15084 intel_ddi_init(dev_priv
, PORT_A
);
15086 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
15088 found
= I915_READ(SFUSE_STRAP
);
15090 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
15091 intel_ddi_init(dev_priv
, PORT_B
);
15092 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
15093 intel_ddi_init(dev_priv
, PORT_C
);
15094 if (found
& SFUSE_STRAP_DDID_DETECTED
)
15095 intel_ddi_init(dev_priv
, PORT_D
);
15096 if (found
& SFUSE_STRAP_DDIF_DETECTED
)
15097 intel_ddi_init(dev_priv
, PORT_F
);
15099 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15101 if (IS_GEN9_BC(dev_priv
) &&
15102 intel_bios_is_port_present(dev_priv
, PORT_E
))
15103 intel_ddi_init(dev_priv
, PORT_E
);
15105 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15109 * intel_edp_init_connector() depends on this completing first,
15110 * to prevent the registration of both eDP and LVDS and the
15111 * incorrect sharing of the PPS.
15113 intel_lvds_init(dev_priv
);
15114 intel_crt_init(dev_priv
);
15116 dpd_is_edp
= intel_dp_is_port_edp(dev_priv
, PORT_D
);
15118 if (ilk_has_edp_a(dev_priv
))
15119 intel_dp_init(dev_priv
, DP_A
, PORT_A
);
15121 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
15122 /* PCH SDVOB multiplex with HDMIB */
15123 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
15125 intel_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
15126 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
15127 intel_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
15130 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
15131 intel_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
15133 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
15134 intel_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
15136 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
15137 intel_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
15139 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
15140 intel_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
15141 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15142 bool has_edp
, has_port
;
15144 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->vbt
.int_crt_support
)
15145 intel_crt_init(dev_priv
);
15148 * The DP_DETECTED bit is the latched state of the DDC
15149 * SDA pin at boot. However since eDP doesn't require DDC
15150 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15151 * eDP ports may have been muxed to an alternate function.
15152 * Thus we can't rely on the DP_DETECTED bit alone to detect
15153 * eDP ports. Consult the VBT as well as DP_DETECTED to
15154 * detect eDP ports.
15156 * Sadly the straps seem to be missing sometimes even for HDMI
15157 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15158 * and VBT for the presence of the port. Additionally we can't
15159 * trust the port type the VBT declares as we've seen at least
15160 * HDMI ports that the VBT claim are DP or eDP.
15162 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_B
);
15163 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
15164 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
15165 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
15166 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
15167 intel_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
15169 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_C
);
15170 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
15171 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
15172 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
15173 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
15174 intel_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
15176 if (IS_CHERRYVIEW(dev_priv
)) {
15178 * eDP not supported on port D,
15179 * so no need to worry about it
15181 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
15182 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
15183 intel_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
15184 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
15185 intel_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
15188 vlv_dsi_init(dev_priv
);
15189 } else if (IS_PINEVIEW(dev_priv
)) {
15190 intel_lvds_init(dev_priv
);
15191 intel_crt_init(dev_priv
);
15192 } else if (IS_GEN_RANGE(dev_priv
, 3, 4)) {
15193 bool found
= false;
15195 if (IS_MOBILE(dev_priv
))
15196 intel_lvds_init(dev_priv
);
15198 intel_crt_init(dev_priv
);
15200 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15201 DRM_DEBUG_KMS("probing SDVOB\n");
15202 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
15203 if (!found
&& IS_G4X(dev_priv
)) {
15204 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15205 intel_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
15208 if (!found
&& IS_G4X(dev_priv
))
15209 intel_dp_init(dev_priv
, DP_B
, PORT_B
);
15212 /* Before G4X SDVOC doesn't have its own detect register */
15214 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15215 DRM_DEBUG_KMS("probing SDVOC\n");
15216 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
15219 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
15221 if (IS_G4X(dev_priv
)) {
15222 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15223 intel_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
15225 if (IS_G4X(dev_priv
))
15226 intel_dp_init(dev_priv
, DP_C
, PORT_C
);
15229 if (IS_G4X(dev_priv
) && (I915_READ(DP_D
) & DP_DETECTED
))
15230 intel_dp_init(dev_priv
, DP_D
, PORT_D
);
15232 if (SUPPORTS_TV(dev_priv
))
15233 intel_tv_init(dev_priv
);
15234 } else if (IS_GEN(dev_priv
, 2)) {
15235 if (IS_I85X(dev_priv
))
15236 intel_lvds_init(dev_priv
);
15238 intel_crt_init(dev_priv
);
15239 intel_dvo_init(dev_priv
);
15242 intel_psr_init(dev_priv
);
15244 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
15245 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
15246 encoder
->base
.possible_clones
=
15247 intel_encoder_clones(encoder
);
15250 intel_init_pch_refclk(dev_priv
);
15252 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
15255 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
15257 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15258 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15260 drm_framebuffer_cleanup(fb
);
15262 i915_gem_object_lock(obj
);
15263 WARN_ON(!obj
->framebuffer_references
--);
15264 i915_gem_object_unlock(obj
);
15266 i915_gem_object_put(obj
);
15271 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
15272 struct drm_file
*file
,
15273 unsigned int *handle
)
15275 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15277 if (obj
->userptr
.mm
) {
15278 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15282 return drm_gem_handle_create(file
, &obj
->base
, handle
);
15285 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
15286 struct drm_file
*file
,
15287 unsigned flags
, unsigned color
,
15288 struct drm_clip_rect
*clips
,
15289 unsigned num_clips
)
15291 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15293 i915_gem_object_flush_if_display(obj
);
15294 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
15299 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
15300 .destroy
= intel_user_framebuffer_destroy
,
15301 .create_handle
= intel_user_framebuffer_create_handle
,
15302 .dirty
= intel_user_framebuffer_dirty
,
15305 static int intel_framebuffer_init(struct intel_framebuffer
*intel_fb
,
15306 struct drm_i915_gem_object
*obj
,
15307 struct drm_mode_fb_cmd2
*mode_cmd
)
15309 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
15310 struct drm_framebuffer
*fb
= &intel_fb
->base
;
15312 unsigned int tiling
, stride
;
15316 i915_gem_object_lock(obj
);
15317 obj
->framebuffer_references
++;
15318 tiling
= i915_gem_object_get_tiling(obj
);
15319 stride
= i915_gem_object_get_stride(obj
);
15320 i915_gem_object_unlock(obj
);
15322 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
15324 * If there's a fence, enforce that
15325 * the fb modifier and tiling mode match.
15327 if (tiling
!= I915_TILING_NONE
&&
15328 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15329 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
15333 if (tiling
== I915_TILING_X
) {
15334 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
15335 } else if (tiling
== I915_TILING_Y
) {
15336 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
15341 if (!drm_any_plane_has_format(&dev_priv
->drm
,
15342 mode_cmd
->pixel_format
,
15343 mode_cmd
->modifier
[0])) {
15344 struct drm_format_name_buf format_name
;
15346 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
15347 drm_get_format_name(mode_cmd
->pixel_format
,
15349 mode_cmd
->modifier
[0]);
15354 * gen2/3 display engine uses the fence if present,
15355 * so the tiling mode must match the fb modifier exactly.
15357 if (INTEL_GEN(dev_priv
) < 4 &&
15358 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15359 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
15363 max_stride
= intel_fb_max_stride(dev_priv
, mode_cmd
->pixel_format
,
15364 mode_cmd
->modifier
[0]);
15365 if (mode_cmd
->pitches
[0] > max_stride
) {
15366 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
15367 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_LINEAR
?
15368 "tiled" : "linear",
15369 mode_cmd
->pitches
[0], max_stride
);
15374 * If there's a fence, enforce that
15375 * the fb pitch and fence stride match.
15377 if (tiling
!= I915_TILING_NONE
&& mode_cmd
->pitches
[0] != stride
) {
15378 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
15379 mode_cmd
->pitches
[0], stride
);
15383 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15384 if (mode_cmd
->offsets
[0] != 0)
15387 drm_helper_mode_fill_fb_struct(&dev_priv
->drm
, fb
, mode_cmd
);
15389 for (i
= 0; i
< fb
->format
->num_planes
; i
++) {
15390 u32 stride_alignment
;
15392 if (mode_cmd
->handles
[i
] != mode_cmd
->handles
[0]) {
15393 DRM_DEBUG_KMS("bad plane %d handle\n", i
);
15397 stride_alignment
= intel_fb_stride_alignment(fb
, i
);
15400 * Display WA #0531: skl,bxt,kbl,glk
15402 * Render decompression and plane width > 3840
15403 * combined with horizontal panning requires the
15404 * plane stride to be a multiple of 4. We'll just
15405 * require the entire fb to accommodate that to avoid
15406 * potential runtime errors at plane configuration time.
15408 if (IS_GEN(dev_priv
, 9) && i
== 0 && fb
->width
> 3840 &&
15409 is_ccs_modifier(fb
->modifier
))
15410 stride_alignment
*= 4;
15412 if (fb
->pitches
[i
] & (stride_alignment
- 1)) {
15413 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
15414 i
, fb
->pitches
[i
], stride_alignment
);
15418 fb
->obj
[i
] = &obj
->base
;
15421 ret
= intel_fill_fb_info(dev_priv
, fb
);
15425 ret
= drm_framebuffer_init(&dev_priv
->drm
, fb
, &intel_fb_funcs
);
15427 DRM_ERROR("framebuffer init failed %d\n", ret
);
15434 i915_gem_object_lock(obj
);
15435 obj
->framebuffer_references
--;
15436 i915_gem_object_unlock(obj
);
15440 static struct drm_framebuffer
*
15441 intel_user_framebuffer_create(struct drm_device
*dev
,
15442 struct drm_file
*filp
,
15443 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
15445 struct drm_framebuffer
*fb
;
15446 struct drm_i915_gem_object
*obj
;
15447 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
15449 obj
= i915_gem_object_lookup(filp
, mode_cmd
.handles
[0]);
15451 return ERR_PTR(-ENOENT
);
15453 fb
= intel_framebuffer_create(obj
, &mode_cmd
);
15455 i915_gem_object_put(obj
);
15460 static void intel_atomic_state_free(struct drm_atomic_state
*state
)
15462 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
15464 drm_atomic_state_default_release(state
);
15466 i915_sw_fence_fini(&intel_state
->commit_ready
);
15471 static enum drm_mode_status
15472 intel_mode_valid(struct drm_device
*dev
,
15473 const struct drm_display_mode
*mode
)
15475 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15476 int hdisplay_max
, htotal_max
;
15477 int vdisplay_max
, vtotal_max
;
15480 * Can't reject DBLSCAN here because Xorg ddxen can add piles
15481 * of DBLSCAN modes to the output's mode list when they detect
15482 * the scaling mode property on the connector. And they don't
15483 * ask the kernel to validate those modes in any way until
15484 * modeset time at which point the client gets a protocol error.
15485 * So in order to not upset those clients we silently ignore the
15486 * DBLSCAN flag on such connectors. For other connectors we will
15487 * reject modes with the DBLSCAN flag in encoder->compute_config().
15488 * And we always reject DBLSCAN modes in connector->mode_valid()
15489 * as we never want such modes on the connector's mode list.
15492 if (mode
->vscan
> 1)
15493 return MODE_NO_VSCAN
;
15495 if (mode
->flags
& DRM_MODE_FLAG_HSKEW
)
15496 return MODE_H_ILLEGAL
;
15498 if (mode
->flags
& (DRM_MODE_FLAG_CSYNC
|
15499 DRM_MODE_FLAG_NCSYNC
|
15500 DRM_MODE_FLAG_PCSYNC
))
15503 if (mode
->flags
& (DRM_MODE_FLAG_BCAST
|
15504 DRM_MODE_FLAG_PIXMUX
|
15505 DRM_MODE_FLAG_CLKDIV2
))
15508 if (INTEL_GEN(dev_priv
) >= 9 ||
15509 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
)) {
15510 hdisplay_max
= 8192; /* FDI max 4096 handled elsewhere */
15511 vdisplay_max
= 4096;
15514 } else if (INTEL_GEN(dev_priv
) >= 3) {
15515 hdisplay_max
= 4096;
15516 vdisplay_max
= 4096;
15520 hdisplay_max
= 2048;
15521 vdisplay_max
= 2048;
15526 if (mode
->hdisplay
> hdisplay_max
||
15527 mode
->hsync_start
> htotal_max
||
15528 mode
->hsync_end
> htotal_max
||
15529 mode
->htotal
> htotal_max
)
15530 return MODE_H_ILLEGAL
;
15532 if (mode
->vdisplay
> vdisplay_max
||
15533 mode
->vsync_start
> vtotal_max
||
15534 mode
->vsync_end
> vtotal_max
||
15535 mode
->vtotal
> vtotal_max
)
15536 return MODE_V_ILLEGAL
;
15541 static const struct drm_mode_config_funcs intel_mode_funcs
= {
15542 .fb_create
= intel_user_framebuffer_create
,
15543 .get_format_info
= intel_get_format_info
,
15544 .output_poll_changed
= intel_fbdev_output_poll_changed
,
15545 .mode_valid
= intel_mode_valid
,
15546 .atomic_check
= intel_atomic_check
,
15547 .atomic_commit
= intel_atomic_commit
,
15548 .atomic_state_alloc
= intel_atomic_state_alloc
,
15549 .atomic_state_clear
= intel_atomic_state_clear
,
15550 .atomic_state_free
= intel_atomic_state_free
,
15554 * intel_init_display_hooks - initialize the display modesetting hooks
15555 * @dev_priv: device private
15557 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
15559 intel_init_cdclk_hooks(dev_priv
);
15561 if (INTEL_GEN(dev_priv
) >= 9) {
15562 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15563 dev_priv
->display
.get_initial_plane_config
=
15564 skylake_get_initial_plane_config
;
15565 dev_priv
->display
.crtc_compute_clock
=
15566 haswell_crtc_compute_clock
;
15567 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15568 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15569 } else if (HAS_DDI(dev_priv
)) {
15570 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15571 dev_priv
->display
.get_initial_plane_config
=
15572 i9xx_get_initial_plane_config
;
15573 dev_priv
->display
.crtc_compute_clock
=
15574 haswell_crtc_compute_clock
;
15575 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15576 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15577 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15578 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
15579 dev_priv
->display
.get_initial_plane_config
=
15580 i9xx_get_initial_plane_config
;
15581 dev_priv
->display
.crtc_compute_clock
=
15582 ironlake_crtc_compute_clock
;
15583 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
15584 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
15585 } else if (IS_CHERRYVIEW(dev_priv
)) {
15586 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15587 dev_priv
->display
.get_initial_plane_config
=
15588 i9xx_get_initial_plane_config
;
15589 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
15590 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15591 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15592 } else if (IS_VALLEYVIEW(dev_priv
)) {
15593 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15594 dev_priv
->display
.get_initial_plane_config
=
15595 i9xx_get_initial_plane_config
;
15596 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
15597 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15598 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15599 } else if (IS_G4X(dev_priv
)) {
15600 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15601 dev_priv
->display
.get_initial_plane_config
=
15602 i9xx_get_initial_plane_config
;
15603 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
15604 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15605 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15606 } else if (IS_PINEVIEW(dev_priv
)) {
15607 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15608 dev_priv
->display
.get_initial_plane_config
=
15609 i9xx_get_initial_plane_config
;
15610 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
15611 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15612 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15613 } else if (!IS_GEN(dev_priv
, 2)) {
15614 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15615 dev_priv
->display
.get_initial_plane_config
=
15616 i9xx_get_initial_plane_config
;
15617 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
15618 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15619 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15621 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15622 dev_priv
->display
.get_initial_plane_config
=
15623 i9xx_get_initial_plane_config
;
15624 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
15625 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15626 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15629 if (IS_GEN(dev_priv
, 5)) {
15630 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
15631 } else if (IS_GEN(dev_priv
, 6)) {
15632 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
15633 } else if (IS_IVYBRIDGE(dev_priv
)) {
15634 /* FIXME: detect B0+ stepping and use auto training */
15635 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
15636 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
15637 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
15640 if (INTEL_GEN(dev_priv
) >= 9)
15641 dev_priv
->display
.update_crtcs
= skl_update_crtcs
;
15643 dev_priv
->display
.update_crtcs
= intel_update_crtcs
;
15646 static i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
15648 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15649 return VLV_VGACNTRL
;
15650 else if (INTEL_GEN(dev_priv
) >= 5)
15651 return CPU_VGACNTRL
;
15656 /* Disable the VGA plane that we never use */
15657 static void i915_disable_vga(struct drm_i915_private
*dev_priv
)
15659 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
15661 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
15663 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15664 vga_get_uninterruptible(pdev
, VGA_RSRC_LEGACY_IO
);
15665 outb(SR01
, VGA_SR_INDEX
);
15666 sr1
= inb(VGA_SR_DATA
);
15667 outb(sr1
| 1<<5, VGA_SR_DATA
);
15668 vga_put(pdev
, VGA_RSRC_LEGACY_IO
);
15671 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15672 POSTING_READ(vga_reg
);
15675 void intel_modeset_init_hw(struct drm_device
*dev
)
15677 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15679 intel_update_cdclk(dev_priv
);
15680 intel_dump_cdclk_state(&dev_priv
->cdclk
.hw
, "Current CDCLK");
15681 dev_priv
->cdclk
.logical
= dev_priv
->cdclk
.actual
= dev_priv
->cdclk
.hw
;
15685 * Calculate what we think the watermarks should be for the state we've read
15686 * out of the hardware and then immediately program those watermarks so that
15687 * we ensure the hardware settings match our internal state.
15689 * We can calculate what we think WM's should be by creating a duplicate of the
15690 * current state (which was constructed during hardware readout) and running it
15691 * through the atomic check code to calculate new watermark values in the
15694 static void sanitize_watermarks(struct drm_device
*dev
)
15696 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15697 struct drm_atomic_state
*state
;
15698 struct intel_atomic_state
*intel_state
;
15699 struct drm_crtc
*crtc
;
15700 struct drm_crtc_state
*cstate
;
15701 struct drm_modeset_acquire_ctx ctx
;
15705 /* Only supported on platforms that use atomic watermark design */
15706 if (!dev_priv
->display
.optimize_watermarks
)
15710 * We need to hold connection_mutex before calling duplicate_state so
15711 * that the connector loop is protected.
15713 drm_modeset_acquire_init(&ctx
, 0);
15715 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15716 if (ret
== -EDEADLK
) {
15717 drm_modeset_backoff(&ctx
);
15719 } else if (WARN_ON(ret
)) {
15723 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
15724 if (WARN_ON(IS_ERR(state
)))
15727 intel_state
= to_intel_atomic_state(state
);
15730 * Hardware readout is the only time we don't want to calculate
15731 * intermediate watermarks (since we don't trust the current
15734 if (!HAS_GMCH(dev_priv
))
15735 intel_state
->skip_intermediate_wm
= true;
15737 ret
= intel_atomic_check(dev
, state
);
15740 * If we fail here, it means that the hardware appears to be
15741 * programmed in a way that shouldn't be possible, given our
15742 * understanding of watermark requirements. This might mean a
15743 * mistake in the hardware readout code or a mistake in the
15744 * watermark calculations for a given platform. Raise a WARN
15745 * so that this is noticeable.
15747 * If this actually happens, we'll have to just leave the
15748 * BIOS-programmed watermarks untouched and hope for the best.
15750 WARN(true, "Could not determine valid watermarks for inherited state\n");
15754 /* Write calculated watermark values back */
15755 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
15756 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
15758 cs
->wm
.need_postvbl_update
= true;
15759 dev_priv
->display
.optimize_watermarks(intel_state
, cs
);
15761 to_intel_crtc_state(crtc
->state
)->wm
= cs
->wm
;
15765 drm_atomic_state_put(state
);
15767 drm_modeset_drop_locks(&ctx
);
15768 drm_modeset_acquire_fini(&ctx
);
15771 static void intel_update_fdi_pll_freq(struct drm_i915_private
*dev_priv
)
15773 if (IS_GEN(dev_priv
, 5)) {
15775 I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
;
15777 dev_priv
->fdi_pll_freq
= (fdi_pll_clk
+ 2) * 10000;
15778 } else if (IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
)) {
15779 dev_priv
->fdi_pll_freq
= 270000;
15784 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv
->fdi_pll_freq
);
15787 static int intel_initial_commit(struct drm_device
*dev
)
15789 struct drm_atomic_state
*state
= NULL
;
15790 struct drm_modeset_acquire_ctx ctx
;
15791 struct drm_crtc
*crtc
;
15792 struct drm_crtc_state
*crtc_state
;
15795 state
= drm_atomic_state_alloc(dev
);
15799 drm_modeset_acquire_init(&ctx
, 0);
15802 state
->acquire_ctx
= &ctx
;
15804 drm_for_each_crtc(crtc
, dev
) {
15805 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
15806 if (IS_ERR(crtc_state
)) {
15807 ret
= PTR_ERR(crtc_state
);
15811 if (crtc_state
->active
) {
15812 ret
= drm_atomic_add_affected_planes(state
, crtc
);
15817 * FIXME hack to force a LUT update to avoid the
15818 * plane update forcing the pipe gamma on without
15819 * having a proper LUT loaded. Remove once we
15820 * have readout for pipe gamma enable.
15822 crtc_state
->color_mgmt_changed
= true;
15826 ret
= drm_atomic_commit(state
);
15829 if (ret
== -EDEADLK
) {
15830 drm_atomic_state_clear(state
);
15831 drm_modeset_backoff(&ctx
);
15835 drm_atomic_state_put(state
);
15837 drm_modeset_drop_locks(&ctx
);
15838 drm_modeset_acquire_fini(&ctx
);
15843 int intel_modeset_init(struct drm_device
*dev
)
15845 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15846 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
15848 struct intel_crtc
*crtc
;
15851 dev_priv
->modeset_wq
= alloc_ordered_workqueue("i915_modeset", 0);
15853 drm_mode_config_init(dev
);
15855 ret
= intel_bw_init(dev_priv
);
15859 dev
->mode_config
.min_width
= 0;
15860 dev
->mode_config
.min_height
= 0;
15862 dev
->mode_config
.preferred_depth
= 24;
15863 dev
->mode_config
.prefer_shadow
= 1;
15865 dev
->mode_config
.allow_fb_modifiers
= true;
15867 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15869 init_llist_head(&dev_priv
->atomic_helper
.free_list
);
15870 INIT_WORK(&dev_priv
->atomic_helper
.free_work
,
15871 intel_atomic_helper_free_state_worker
);
15873 intel_init_quirks(dev_priv
);
15875 intel_fbc_init(dev_priv
);
15877 intel_init_pm(dev_priv
);
15880 * There may be no VBT; and if the BIOS enabled SSC we can
15881 * just keep using it to avoid unnecessary flicker. Whereas if the
15882 * BIOS isn't using it, don't assume it will work even if the VBT
15883 * indicates as much.
15885 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
15886 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15889 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
15890 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15891 bios_lvds_use_ssc
? "en" : "dis",
15892 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
15893 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
15898 * Maximum framebuffer dimensions, chosen to match
15899 * the maximum render engine surface size on gen4+.
15901 if (INTEL_GEN(dev_priv
) >= 7) {
15902 dev
->mode_config
.max_width
= 16384;
15903 dev
->mode_config
.max_height
= 16384;
15904 } else if (INTEL_GEN(dev_priv
) >= 4) {
15905 dev
->mode_config
.max_width
= 8192;
15906 dev
->mode_config
.max_height
= 8192;
15907 } else if (IS_GEN(dev_priv
, 3)) {
15908 dev
->mode_config
.max_width
= 4096;
15909 dev
->mode_config
.max_height
= 4096;
15911 dev
->mode_config
.max_width
= 2048;
15912 dev
->mode_config
.max_height
= 2048;
15915 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
15916 dev
->mode_config
.cursor_width
= IS_I845G(dev_priv
) ? 64 : 512;
15917 dev
->mode_config
.cursor_height
= 1023;
15918 } else if (IS_GEN(dev_priv
, 2)) {
15919 dev
->mode_config
.cursor_width
= 64;
15920 dev
->mode_config
.cursor_height
= 64;
15922 dev
->mode_config
.cursor_width
= 256;
15923 dev
->mode_config
.cursor_height
= 256;
15926 dev
->mode_config
.fb_base
= ggtt
->gmadr
.start
;
15928 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15929 INTEL_INFO(dev_priv
)->num_pipes
,
15930 INTEL_INFO(dev_priv
)->num_pipes
> 1 ? "s" : "");
15932 for_each_pipe(dev_priv
, pipe
) {
15933 ret
= intel_crtc_init(dev_priv
, pipe
);
15935 drm_mode_config_cleanup(dev
);
15940 intel_shared_dpll_init(dev
);
15941 intel_update_fdi_pll_freq(dev_priv
);
15943 intel_update_czclk(dev_priv
);
15944 intel_modeset_init_hw(dev
);
15946 intel_hdcp_component_init(dev_priv
);
15948 if (dev_priv
->max_cdclk_freq
== 0)
15949 intel_update_max_cdclk(dev_priv
);
15951 /* Just disable it once at startup */
15952 i915_disable_vga(dev_priv
);
15953 intel_setup_outputs(dev_priv
);
15955 drm_modeset_lock_all(dev
);
15956 intel_modeset_setup_hw_state(dev
, dev
->mode_config
.acquire_ctx
);
15957 drm_modeset_unlock_all(dev
);
15959 for_each_intel_crtc(dev
, crtc
) {
15960 struct intel_initial_plane_config plane_config
= {};
15966 * Note that reserving the BIOS fb up front prevents us
15967 * from stuffing other stolen allocations like the ring
15968 * on top. This prevents some ugliness at boot time, and
15969 * can even allow for smooth boot transitions if the BIOS
15970 * fb is large enough for the active pipe configuration.
15972 dev_priv
->display
.get_initial_plane_config(crtc
,
15976 * If the fb is shared between multiple heads, we'll
15977 * just get the first one.
15979 intel_find_initial_plane_obj(crtc
, &plane_config
);
15983 * Make sure hardware watermarks really match the state we read out.
15984 * Note that we need to do this after reconstructing the BIOS fb's
15985 * since the watermark calculation done here will use pstate->fb.
15987 if (!HAS_GMCH(dev_priv
))
15988 sanitize_watermarks(dev
);
15991 * Force all active planes to recompute their states. So that on
15992 * mode_setcrtc after probe, all the intel_plane_state variables
15993 * are already calculated and there is no assert_plane warnings
15996 ret
= intel_initial_commit(dev
);
15998 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
16003 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
16005 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16006 /* 640x480@60Hz, ~25175 kHz */
16007 struct dpll clock
= {
16017 WARN_ON(i9xx_calc_dpll_params(48000, &clock
) != 25154);
16019 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
16020 pipe_name(pipe
), clock
.vco
, clock
.dot
);
16022 fp
= i9xx_dpll_compute_fp(&clock
);
16023 dpll
= DPLL_DVO_2X_MODE
|
16024 DPLL_VGA_MODE_DIS
|
16025 ((clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
) |
16026 PLL_P2_DIVIDE_BY_4
|
16027 PLL_REF_INPUT_DREFCLK
|
16030 I915_WRITE(FP0(pipe
), fp
);
16031 I915_WRITE(FP1(pipe
), fp
);
16033 I915_WRITE(HTOTAL(pipe
), (640 - 1) | ((800 - 1) << 16));
16034 I915_WRITE(HBLANK(pipe
), (640 - 1) | ((800 - 1) << 16));
16035 I915_WRITE(HSYNC(pipe
), (656 - 1) | ((752 - 1) << 16));
16036 I915_WRITE(VTOTAL(pipe
), (480 - 1) | ((525 - 1) << 16));
16037 I915_WRITE(VBLANK(pipe
), (480 - 1) | ((525 - 1) << 16));
16038 I915_WRITE(VSYNC(pipe
), (490 - 1) | ((492 - 1) << 16));
16039 I915_WRITE(PIPESRC(pipe
), ((640 - 1) << 16) | (480 - 1));
16042 * Apparently we need to have VGA mode enabled prior to changing
16043 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
16044 * dividers, even though the register value does change.
16046 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VGA_MODE_DIS
);
16047 I915_WRITE(DPLL(pipe
), dpll
);
16049 /* Wait for the clocks to stabilize. */
16050 POSTING_READ(DPLL(pipe
));
16053 /* The pixel multiplier can only be updated once the
16054 * DPLL is enabled and the clocks are stable.
16056 * So write it again.
16058 I915_WRITE(DPLL(pipe
), dpll
);
16060 /* We do this three times for luck */
16061 for (i
= 0; i
< 3 ; i
++) {
16062 I915_WRITE(DPLL(pipe
), dpll
);
16063 POSTING_READ(DPLL(pipe
));
16064 udelay(150); /* wait for warmup */
16067 I915_WRITE(PIPECONF(pipe
), PIPECONF_ENABLE
| PIPECONF_PROGRESSIVE
);
16068 POSTING_READ(PIPECONF(pipe
));
16070 intel_wait_for_pipe_scanline_moving(crtc
);
16073 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
16075 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16077 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
16080 WARN_ON(I915_READ(DSPCNTR(PLANE_A
)) & DISPLAY_PLANE_ENABLE
);
16081 WARN_ON(I915_READ(DSPCNTR(PLANE_B
)) & DISPLAY_PLANE_ENABLE
);
16082 WARN_ON(I915_READ(DSPCNTR(PLANE_C
)) & DISPLAY_PLANE_ENABLE
);
16083 WARN_ON(I915_READ(CURCNTR(PIPE_A
)) & MCURSOR_MODE
);
16084 WARN_ON(I915_READ(CURCNTR(PIPE_B
)) & MCURSOR_MODE
);
16086 I915_WRITE(PIPECONF(pipe
), 0);
16087 POSTING_READ(PIPECONF(pipe
));
16089 intel_wait_for_pipe_scanline_stopped(crtc
);
16091 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
16092 POSTING_READ(DPLL(pipe
));
16096 intel_sanitize_plane_mapping(struct drm_i915_private
*dev_priv
)
16098 struct intel_crtc
*crtc
;
16100 if (INTEL_GEN(dev_priv
) >= 4)
16103 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16104 struct intel_plane
*plane
=
16105 to_intel_plane(crtc
->base
.primary
);
16106 struct intel_crtc
*plane_crtc
;
16109 if (!plane
->get_hw_state(plane
, &pipe
))
16112 if (pipe
== crtc
->pipe
)
16115 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
16116 plane
->base
.base
.id
, plane
->base
.name
);
16118 plane_crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16119 intel_plane_disable_noatomic(plane_crtc
, plane
);
16123 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
16125 struct drm_device
*dev
= crtc
->base
.dev
;
16126 struct intel_encoder
*encoder
;
16128 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
16134 static struct intel_connector
*intel_encoder_find_connector(struct intel_encoder
*encoder
)
16136 struct drm_device
*dev
= encoder
->base
.dev
;
16137 struct intel_connector
*connector
;
16139 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
16145 static bool has_pch_trancoder(struct drm_i915_private
*dev_priv
,
16146 enum pipe pch_transcoder
)
16148 return HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
16149 (HAS_PCH_LPT_H(dev_priv
) && pch_transcoder
== PIPE_A
);
16152 static void intel_sanitize_crtc(struct intel_crtc
*crtc
,
16153 struct drm_modeset_acquire_ctx
*ctx
)
16155 struct drm_device
*dev
= crtc
->base
.dev
;
16156 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16157 struct intel_crtc_state
*crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16158 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
16160 /* Clear any frame start delays used for debugging left by the BIOS */
16161 if (crtc
->active
&& !transcoder_is_dsi(cpu_transcoder
)) {
16162 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
16165 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
16168 if (crtc_state
->base
.active
) {
16169 struct intel_plane
*plane
;
16171 /* Disable everything but the primary plane */
16172 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
16173 const struct intel_plane_state
*plane_state
=
16174 to_intel_plane_state(plane
->base
.state
);
16176 if (plane_state
->base
.visible
&&
16177 plane
->base
.type
!= DRM_PLANE_TYPE_PRIMARY
)
16178 intel_plane_disable_noatomic(crtc
, plane
);
16182 * Disable any background color set by the BIOS, but enable the
16183 * gamma and CSC to match how we program our planes.
16185 if (INTEL_GEN(dev_priv
) >= 9)
16186 I915_WRITE(SKL_BOTTOM_COLOR(crtc
->pipe
),
16187 SKL_BOTTOM_COLOR_GAMMA_ENABLE
|
16188 SKL_BOTTOM_COLOR_CSC_ENABLE
);
16191 /* Adjust the state of the output pipe according to whether we
16192 * have active connectors/encoders. */
16193 if (crtc_state
->base
.active
&& !intel_crtc_has_encoders(crtc
))
16194 intel_crtc_disable_noatomic(&crtc
->base
, ctx
);
16196 if (crtc_state
->base
.active
|| HAS_GMCH(dev_priv
)) {
16198 * We start out with underrun reporting disabled to avoid races.
16199 * For correct bookkeeping mark this on active crtcs.
16201 * Also on gmch platforms we dont have any hardware bits to
16202 * disable the underrun reporting. Which means we need to start
16203 * out with underrun reporting disabled also on inactive pipes,
16204 * since otherwise we'll complain about the garbage we read when
16205 * e.g. coming up after runtime pm.
16207 * No protection against concurrent access is required - at
16208 * worst a fifo underrun happens which also sets this to false.
16210 crtc
->cpu_fifo_underrun_disabled
= true;
16212 * We track the PCH trancoder underrun reporting state
16213 * within the crtc. With crtc for pipe A housing the underrun
16214 * reporting state for PCH transcoder A, crtc for pipe B housing
16215 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16216 * and marking underrun reporting as disabled for the non-existing
16217 * PCH transcoders B and C would prevent enabling the south
16218 * error interrupt (see cpt_can_enable_serr_int()).
16220 if (has_pch_trancoder(dev_priv
, crtc
->pipe
))
16221 crtc
->pch_fifo_underrun_disabled
= true;
16225 static bool has_bogus_dpll_config(const struct intel_crtc_state
*crtc_state
)
16227 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
16230 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
16231 * the hardware when a high res displays plugged in. DPLL P
16232 * divider is zero, and the pipe timings are bonkers. We'll
16233 * try to disable everything in that case.
16235 * FIXME would be nice to be able to sanitize this state
16236 * without several WARNs, but for now let's take the easy
16239 return IS_GEN(dev_priv
, 6) &&
16240 crtc_state
->base
.active
&&
16241 crtc_state
->shared_dpll
&&
16242 crtc_state
->port_clock
== 0;
16245 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
16247 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
16248 struct intel_connector
*connector
;
16249 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
16250 struct intel_crtc_state
*crtc_state
= crtc
?
16251 to_intel_crtc_state(crtc
->base
.state
) : NULL
;
16253 /* We need to check both for a crtc link (meaning that the
16254 * encoder is active and trying to read from a pipe) and the
16255 * pipe itself being active. */
16256 bool has_active_crtc
= crtc_state
&&
16257 crtc_state
->base
.active
;
16259 if (crtc_state
&& has_bogus_dpll_config(crtc_state
)) {
16260 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
16261 pipe_name(crtc
->pipe
));
16262 has_active_crtc
= false;
16265 connector
= intel_encoder_find_connector(encoder
);
16266 if (connector
&& !has_active_crtc
) {
16267 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16268 encoder
->base
.base
.id
,
16269 encoder
->base
.name
);
16271 /* Connector is active, but has no active pipe. This is
16272 * fallout from our resume register restoring. Disable
16273 * the encoder manually again. */
16275 struct drm_encoder
*best_encoder
;
16277 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16278 encoder
->base
.base
.id
,
16279 encoder
->base
.name
);
16281 /* avoid oopsing in case the hooks consult best_encoder */
16282 best_encoder
= connector
->base
.state
->best_encoder
;
16283 connector
->base
.state
->best_encoder
= &encoder
->base
;
16285 if (encoder
->disable
)
16286 encoder
->disable(encoder
, crtc_state
,
16287 connector
->base
.state
);
16288 if (encoder
->post_disable
)
16289 encoder
->post_disable(encoder
, crtc_state
,
16290 connector
->base
.state
);
16292 connector
->base
.state
->best_encoder
= best_encoder
;
16294 encoder
->base
.crtc
= NULL
;
16296 /* Inconsistent output/port/pipe state happens presumably due to
16297 * a bug in one of the get_hw_state functions. Or someplace else
16298 * in our code, like the register restore mess on resume. Clamp
16299 * things to off as a safer default. */
16301 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16302 connector
->base
.encoder
= NULL
;
16305 /* notify opregion of the sanitized encoder state */
16306 intel_opregion_notify_encoder(encoder
, connector
&& has_active_crtc
);
16308 if (INTEL_GEN(dev_priv
) >= 11)
16309 icl_sanitize_encoder_pll_mapping(encoder
);
16312 void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
)
16314 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
16316 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
16317 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16318 i915_disable_vga(dev_priv
);
16322 void i915_redisable_vga(struct drm_i915_private
*dev_priv
)
16324 intel_wakeref_t wakeref
;
16327 * This function can be called both from intel_modeset_setup_hw_state or
16328 * at a very early point in our resume sequence, where the power well
16329 * structures are not yet restored. Since this function is at a very
16330 * paranoid "someone might have enabled VGA while we were not looking"
16331 * level, just check if the power well is enabled instead of trying to
16332 * follow the "don't touch the power well if we don't need it" policy
16333 * the rest of the driver uses.
16335 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
16340 i915_redisable_vga_power_on(dev_priv
);
16342 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
, wakeref
);
16345 /* FIXME read out full plane state for all planes */
16346 static void readout_plane_state(struct drm_i915_private
*dev_priv
)
16348 struct intel_plane
*plane
;
16349 struct intel_crtc
*crtc
;
16351 for_each_intel_plane(&dev_priv
->drm
, plane
) {
16352 struct intel_plane_state
*plane_state
=
16353 to_intel_plane_state(plane
->base
.state
);
16354 struct intel_crtc_state
*crtc_state
;
16355 enum pipe pipe
= PIPE_A
;
16358 visible
= plane
->get_hw_state(plane
, &pipe
);
16360 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16361 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16363 intel_set_plane_visible(crtc_state
, plane_state
, visible
);
16365 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
16366 plane
->base
.base
.id
, plane
->base
.name
,
16367 enableddisabled(visible
), pipe_name(pipe
));
16370 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16371 struct intel_crtc_state
*crtc_state
=
16372 to_intel_crtc_state(crtc
->base
.state
);
16374 fixup_active_planes(crtc_state
);
16378 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
16380 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16382 struct intel_crtc
*crtc
;
16383 struct intel_encoder
*encoder
;
16384 struct intel_connector
*connector
;
16385 struct drm_connector_list_iter conn_iter
;
16388 dev_priv
->active_crtcs
= 0;
16390 for_each_intel_crtc(dev
, crtc
) {
16391 struct intel_crtc_state
*crtc_state
=
16392 to_intel_crtc_state(crtc
->base
.state
);
16394 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
16395 memset(crtc_state
, 0, sizeof(*crtc_state
));
16396 __drm_atomic_helper_crtc_reset(&crtc
->base
, &crtc_state
->base
);
16398 crtc_state
->base
.active
= crtc_state
->base
.enable
=
16399 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
16401 crtc
->base
.enabled
= crtc_state
->base
.enable
;
16402 crtc
->active
= crtc_state
->base
.active
;
16404 if (crtc_state
->base
.active
)
16405 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
16407 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16408 crtc
->base
.base
.id
, crtc
->base
.name
,
16409 enableddisabled(crtc_state
->base
.active
));
16412 readout_plane_state(dev_priv
);
16414 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16415 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16417 pll
->on
= pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
16418 &pll
->state
.hw_state
);
16419 pll
->state
.crtc_mask
= 0;
16420 for_each_intel_crtc(dev
, crtc
) {
16421 struct intel_crtc_state
*crtc_state
=
16422 to_intel_crtc_state(crtc
->base
.state
);
16424 if (crtc_state
->base
.active
&&
16425 crtc_state
->shared_dpll
== pll
)
16426 pll
->state
.crtc_mask
|= 1 << crtc
->pipe
;
16428 pll
->active_mask
= pll
->state
.crtc_mask
;
16430 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16431 pll
->info
->name
, pll
->state
.crtc_mask
, pll
->on
);
16434 for_each_intel_encoder(dev
, encoder
) {
16437 if (encoder
->get_hw_state(encoder
, &pipe
)) {
16438 struct intel_crtc_state
*crtc_state
;
16440 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16441 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16443 encoder
->base
.crtc
= &crtc
->base
;
16444 encoder
->get_config(encoder
, crtc_state
);
16446 encoder
->base
.crtc
= NULL
;
16449 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16450 encoder
->base
.base
.id
, encoder
->base
.name
,
16451 enableddisabled(encoder
->base
.crtc
),
16455 drm_connector_list_iter_begin(dev
, &conn_iter
);
16456 for_each_intel_connector_iter(connector
, &conn_iter
) {
16457 if (connector
->get_hw_state(connector
)) {
16458 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
16460 encoder
= connector
->encoder
;
16461 connector
->base
.encoder
= &encoder
->base
;
16463 if (encoder
->base
.crtc
&&
16464 encoder
->base
.crtc
->state
->active
) {
16466 * This has to be done during hardware readout
16467 * because anything calling .crtc_disable may
16468 * rely on the connector_mask being accurate.
16470 encoder
->base
.crtc
->state
->connector_mask
|=
16471 drm_connector_mask(&connector
->base
);
16472 encoder
->base
.crtc
->state
->encoder_mask
|=
16473 drm_encoder_mask(&encoder
->base
);
16477 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16478 connector
->base
.encoder
= NULL
;
16480 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16481 connector
->base
.base
.id
, connector
->base
.name
,
16482 enableddisabled(connector
->base
.encoder
));
16484 drm_connector_list_iter_end(&conn_iter
);
16486 for_each_intel_crtc(dev
, crtc
) {
16487 struct intel_bw_state
*bw_state
=
16488 to_intel_bw_state(dev_priv
->bw_obj
.state
);
16489 struct intel_crtc_state
*crtc_state
=
16490 to_intel_crtc_state(crtc
->base
.state
);
16491 struct intel_plane
*plane
;
16494 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
16495 if (crtc_state
->base
.active
) {
16496 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc_state
);
16497 crtc
->base
.mode
.hdisplay
= crtc_state
->pipe_src_w
;
16498 crtc
->base
.mode
.vdisplay
= crtc_state
->pipe_src_h
;
16499 intel_mode_from_pipe_config(&crtc_state
->base
.adjusted_mode
, crtc_state
);
16500 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
16503 * The initial mode needs to be set in order to keep
16504 * the atomic core happy. It wants a valid mode if the
16505 * crtc's enabled, so we do the above call.
16507 * But we don't set all the derived state fully, hence
16508 * set a flag to indicate that a full recalculation is
16509 * needed on the next commit.
16511 crtc_state
->base
.mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
16513 intel_crtc_compute_pixel_rate(crtc_state
);
16515 if (dev_priv
->display
.modeset_calc_cdclk
) {
16516 min_cdclk
= intel_crtc_compute_min_cdclk(crtc_state
);
16517 if (WARN_ON(min_cdclk
< 0))
16521 drm_calc_timestamping_constants(&crtc
->base
,
16522 &crtc_state
->base
.adjusted_mode
);
16523 update_scanline_offset(crtc_state
);
16526 dev_priv
->min_cdclk
[crtc
->pipe
] = min_cdclk
;
16527 dev_priv
->min_voltage_level
[crtc
->pipe
] =
16528 crtc_state
->min_voltage_level
;
16530 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
) {
16531 const struct intel_plane_state
*plane_state
=
16532 to_intel_plane_state(plane
->base
.state
);
16535 * FIXME don't have the fb yet, so can't
16536 * use intel_plane_data_rate() :(
16538 if (plane_state
->base
.visible
)
16539 crtc_state
->data_rate
[plane
->id
] =
16540 4 * crtc_state
->pixel_rate
;
16543 intel_bw_crtc_update(bw_state
, crtc_state
);
16545 intel_pipe_config_sanity_check(dev_priv
, crtc_state
);
16550 get_encoder_power_domains(struct drm_i915_private
*dev_priv
)
16552 struct intel_encoder
*encoder
;
16554 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
16555 struct intel_crtc_state
*crtc_state
;
16557 if (!encoder
->get_power_domains
)
16561 * MST-primary and inactive encoders don't have a crtc state
16562 * and neither of these require any power domain references.
16564 if (!encoder
->base
.crtc
)
16567 crtc_state
= to_intel_crtc_state(encoder
->base
.crtc
->state
);
16568 encoder
->get_power_domains(encoder
, crtc_state
);
16572 static void intel_early_display_was(struct drm_i915_private
*dev_priv
)
16574 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
16575 if (IS_CANNONLAKE(dev_priv
) || IS_GEMINILAKE(dev_priv
))
16576 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
16579 if (IS_HASWELL(dev_priv
)) {
16581 * WaRsPkgCStateDisplayPMReq:hsw
16582 * System hang if this isn't done before disabling all planes!
16584 I915_WRITE(CHICKEN_PAR1_1
,
16585 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
16589 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private
*dev_priv
,
16590 enum port port
, i915_reg_t hdmi_reg
)
16592 u32 val
= I915_READ(hdmi_reg
);
16594 if (val
& SDVO_ENABLE
||
16595 (val
& SDVO_PIPE_SEL_MASK
) == SDVO_PIPE_SEL(PIPE_A
))
16598 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
16601 val
&= ~SDVO_PIPE_SEL_MASK
;
16602 val
|= SDVO_PIPE_SEL(PIPE_A
);
16604 I915_WRITE(hdmi_reg
, val
);
16607 static void ibx_sanitize_pch_dp_port(struct drm_i915_private
*dev_priv
,
16608 enum port port
, i915_reg_t dp_reg
)
16610 u32 val
= I915_READ(dp_reg
);
16612 if (val
& DP_PORT_EN
||
16613 (val
& DP_PIPE_SEL_MASK
) == DP_PIPE_SEL(PIPE_A
))
16616 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
16619 val
&= ~DP_PIPE_SEL_MASK
;
16620 val
|= DP_PIPE_SEL(PIPE_A
);
16622 I915_WRITE(dp_reg
, val
);
16625 static void ibx_sanitize_pch_ports(struct drm_i915_private
*dev_priv
)
16628 * The BIOS may select transcoder B on some of the PCH
16629 * ports even it doesn't enable the port. This would trip
16630 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
16631 * Sanitize the transcoder select bits to prevent that. We
16632 * assume that the BIOS never actually enabled the port,
16633 * because if it did we'd actually have to toggle the port
16634 * on and back off to make the transcoder A select stick
16635 * (see. intel_dp_link_down(), intel_disable_hdmi(),
16636 * intel_disable_sdvo()).
16638 ibx_sanitize_pch_dp_port(dev_priv
, PORT_B
, PCH_DP_B
);
16639 ibx_sanitize_pch_dp_port(dev_priv
, PORT_C
, PCH_DP_C
);
16640 ibx_sanitize_pch_dp_port(dev_priv
, PORT_D
, PCH_DP_D
);
16642 /* PCH SDVOB multiplex with HDMIB */
16643 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_B
, PCH_HDMIB
);
16644 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_C
, PCH_HDMIC
);
16645 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_D
, PCH_HDMID
);
16648 /* Scan out the current hw modeset state,
16649 * and sanitizes it to the current state
16652 intel_modeset_setup_hw_state(struct drm_device
*dev
,
16653 struct drm_modeset_acquire_ctx
*ctx
)
16655 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16656 struct intel_crtc_state
*crtc_state
;
16657 struct intel_encoder
*encoder
;
16658 struct intel_crtc
*crtc
;
16659 intel_wakeref_t wakeref
;
16662 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
16664 intel_early_display_was(dev_priv
);
16665 intel_modeset_readout_hw_state(dev
);
16667 /* HW state is read out, now we need to sanitize this mess. */
16668 get_encoder_power_domains(dev_priv
);
16670 if (HAS_PCH_IBX(dev_priv
))
16671 ibx_sanitize_pch_ports(dev_priv
);
16674 * intel_sanitize_plane_mapping() may need to do vblank
16675 * waits, so we need vblank interrupts restored beforehand.
16677 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16678 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16680 drm_crtc_vblank_reset(&crtc
->base
);
16682 if (crtc_state
->base
.active
)
16683 intel_crtc_vblank_on(crtc_state
);
16686 intel_sanitize_plane_mapping(dev_priv
);
16688 for_each_intel_encoder(dev
, encoder
)
16689 intel_sanitize_encoder(encoder
);
16691 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16692 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16693 intel_sanitize_crtc(crtc
, ctx
);
16694 intel_dump_pipe_config(crtc_state
, NULL
, "[setup_hw_state]");
16697 intel_modeset_update_connector_atomic_state(dev
);
16699 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16700 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16702 if (!pll
->on
|| pll
->active_mask
)
16705 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
16708 pll
->info
->funcs
->disable(dev_priv
, pll
);
16712 if (IS_G4X(dev_priv
)) {
16713 g4x_wm_get_hw_state(dev_priv
);
16714 g4x_wm_sanitize(dev_priv
);
16715 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
16716 vlv_wm_get_hw_state(dev_priv
);
16717 vlv_wm_sanitize(dev_priv
);
16718 } else if (INTEL_GEN(dev_priv
) >= 9) {
16719 skl_wm_get_hw_state(dev_priv
);
16720 } else if (HAS_PCH_SPLIT(dev_priv
)) {
16721 ilk_wm_get_hw_state(dev_priv
);
16724 for_each_intel_crtc(dev
, crtc
) {
16727 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16728 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc_state
);
16729 if (WARN_ON(put_domains
))
16730 modeset_put_power_domains(dev_priv
, put_domains
);
16733 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
, wakeref
);
16735 intel_fbc_init_pipe_state(dev_priv
);
16738 void intel_display_resume(struct drm_device
*dev
)
16740 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16741 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
16742 struct drm_modeset_acquire_ctx ctx
;
16745 dev_priv
->modeset_restore_state
= NULL
;
16747 state
->acquire_ctx
= &ctx
;
16749 drm_modeset_acquire_init(&ctx
, 0);
16752 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
16753 if (ret
!= -EDEADLK
)
16756 drm_modeset_backoff(&ctx
);
16760 ret
= __intel_display_resume(dev
, state
, &ctx
);
16762 intel_enable_ipc(dev_priv
);
16763 drm_modeset_drop_locks(&ctx
);
16764 drm_modeset_acquire_fini(&ctx
);
16767 DRM_ERROR("Restoring old state failed with %i\n", ret
);
16769 drm_atomic_state_put(state
);
16772 static void intel_hpd_poll_fini(struct drm_device
*dev
)
16774 struct intel_connector
*connector
;
16775 struct drm_connector_list_iter conn_iter
;
16777 /* Kill all the work that may have been queued by hpd. */
16778 drm_connector_list_iter_begin(dev
, &conn_iter
);
16779 for_each_intel_connector_iter(connector
, &conn_iter
) {
16780 if (connector
->modeset_retry_work
.func
)
16781 cancel_work_sync(&connector
->modeset_retry_work
);
16782 if (connector
->hdcp
.shim
) {
16783 cancel_delayed_work_sync(&connector
->hdcp
.check_work
);
16784 cancel_work_sync(&connector
->hdcp
.prop_work
);
16787 drm_connector_list_iter_end(&conn_iter
);
16790 void intel_modeset_cleanup(struct drm_device
*dev
)
16792 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16794 flush_workqueue(dev_priv
->modeset_wq
);
16796 flush_work(&dev_priv
->atomic_helper
.free_work
);
16797 WARN_ON(!llist_empty(&dev_priv
->atomic_helper
.free_list
));
16800 * Interrupts and polling as the first thing to avoid creating havoc.
16801 * Too much stuff here (turning of connectors, ...) would
16802 * experience fancy races otherwise.
16804 intel_irq_uninstall(dev_priv
);
16807 * Due to the hpd irq storm handling the hotplug work can re-arm the
16808 * poll handlers. Hence disable polling after hpd handling is shut down.
16810 intel_hpd_poll_fini(dev
);
16812 /* poll work can call into fbdev, hence clean that up afterwards */
16813 intel_fbdev_fini(dev_priv
);
16815 intel_unregister_dsm_handler();
16817 intel_fbc_global_disable(dev_priv
);
16819 /* flush any delayed tasks or pending work */
16820 flush_scheduled_work();
16822 intel_hdcp_component_fini(dev_priv
);
16824 drm_mode_config_cleanup(dev
);
16826 intel_overlay_cleanup(dev_priv
);
16828 intel_gmbus_teardown(dev_priv
);
16830 destroy_workqueue(dev_priv
->modeset_wq
);
16832 intel_fbc_cleanup_cfb(dev_priv
);
16836 * set vga decode state - true == enable VGA decode
16838 int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
, bool state
)
16840 unsigned reg
= INTEL_GEN(dev_priv
) >= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
16843 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
16844 DRM_ERROR("failed to read control word\n");
16848 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
16852 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
16854 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
16856 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
16857 DRM_ERROR("failed to write control word\n");
16864 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16866 struct intel_display_error_state
{
16868 u32 power_well_driver
;
16870 struct intel_cursor_error_state
{
16875 } cursor
[I915_MAX_PIPES
];
16877 struct intel_pipe_error_state
{
16878 bool power_domain_on
;
16881 } pipe
[I915_MAX_PIPES
];
16883 struct intel_plane_error_state
{
16891 } plane
[I915_MAX_PIPES
];
16893 struct intel_transcoder_error_state
{
16895 bool power_domain_on
;
16896 enum transcoder cpu_transcoder
;
16909 struct intel_display_error_state
*
16910 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
16912 struct intel_display_error_state
*error
;
16913 int transcoders
[] = {
16921 BUILD_BUG_ON(ARRAY_SIZE(transcoders
) != ARRAY_SIZE(error
->transcoder
));
16923 if (!HAS_DISPLAY(dev_priv
))
16926 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
16930 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16931 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_CTL2
);
16933 for_each_pipe(dev_priv
, i
) {
16934 error
->pipe
[i
].power_domain_on
=
16935 __intel_display_power_is_enabled(dev_priv
,
16936 POWER_DOMAIN_PIPE(i
));
16937 if (!error
->pipe
[i
].power_domain_on
)
16940 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
16941 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
16942 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
16944 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
16945 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
16946 if (INTEL_GEN(dev_priv
) <= 3) {
16947 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
16948 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
16950 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16951 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
16952 if (INTEL_GEN(dev_priv
) >= 4) {
16953 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
16954 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
16957 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
16959 if (HAS_GMCH(dev_priv
))
16960 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
16963 for (i
= 0; i
< ARRAY_SIZE(error
->transcoder
); i
++) {
16964 enum transcoder cpu_transcoder
= transcoders
[i
];
16966 if (!INTEL_INFO(dev_priv
)->trans_offsets
[cpu_transcoder
])
16969 error
->transcoder
[i
].available
= true;
16970 error
->transcoder
[i
].power_domain_on
=
16971 __intel_display_power_is_enabled(dev_priv
,
16972 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
16973 if (!error
->transcoder
[i
].power_domain_on
)
16976 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
16978 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
16979 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
16980 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
16981 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
16982 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
16983 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
16984 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
16990 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16993 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
16994 struct intel_display_error_state
*error
)
16996 struct drm_i915_private
*dev_priv
= m
->i915
;
17002 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev_priv
)->num_pipes
);
17003 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
17004 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
17005 error
->power_well_driver
);
17006 for_each_pipe(dev_priv
, i
) {
17007 err_printf(m
, "Pipe [%d]:\n", i
);
17008 err_printf(m
, " Power: %s\n",
17009 onoff(error
->pipe
[i
].power_domain_on
));
17010 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
17011 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
17013 err_printf(m
, "Plane [%d]:\n", i
);
17014 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
17015 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
17016 if (INTEL_GEN(dev_priv
) <= 3) {
17017 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
17018 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
17020 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
17021 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
17022 if (INTEL_GEN(dev_priv
) >= 4) {
17023 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
17024 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
17027 err_printf(m
, "Cursor [%d]:\n", i
);
17028 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
17029 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
17030 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
17033 for (i
= 0; i
< ARRAY_SIZE(error
->transcoder
); i
++) {
17034 if (!error
->transcoder
[i
].available
)
17037 err_printf(m
, "CPU transcoder: %s\n",
17038 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
17039 err_printf(m
, " Power: %s\n",
17040 onoff(error
->transcoder
[i
].power_domain_on
));
17041 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
17042 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
17043 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
17044 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
17045 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
17046 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
17047 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);