2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_dp_helper.h>
38 #include <drm/drm_edid.h>
39 #include <drm/drm_hdcp.h>
40 #include <drm/drm_probe_helper.h>
41 #include "intel_drv.h"
42 #include <drm/i915_drm.h>
45 #define DP_DPRX_ESI_LEN 14
47 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
48 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
49 #define DP_DSC_MIN_SUPPORTED_BPC 8
50 #define DP_DSC_MAX_SUPPORTED_BPC 10
52 /* DP DSC throughput values used for slice count calculations KPixels/s */
53 #define DP_DSC_PEAK_PIXEL_RATE 2720000
54 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
55 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
57 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
58 #define DP_DSC_FEC_OVERHEAD_FACTOR 976
60 /* Compliance test status bits */
61 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
62 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
63 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
64 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
71 static const struct dp_link_dpll g4x_dpll
[] = {
73 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
75 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
78 static const struct dp_link_dpll pch_dpll
[] = {
80 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
82 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
85 static const struct dp_link_dpll vlv_dpll
[] = {
87 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
89 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
93 * CHV supports eDP 1.4 that have more link rates.
94 * Below only provides the fixed rate but exclude variable rate.
96 static const struct dp_link_dpll chv_dpll
[] = {
98 * CHV requires to program fractional division for m2.
99 * m2 is stored in fixed point format using formula below
100 * (m2_int << 22) | m2_fraction
102 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
103 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
104 { 270000, /* m2_int = 27, m2_fraction = 0 */
105 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
108 /* Constants for DP DSC configurations */
109 static const u8 valid_dsc_bpp
[] = {6, 8, 10, 12, 15};
111 /* With Single pipe configuration, HW is capable of supporting maximum
112 * of 4 slices per line.
114 static const u8 valid_dsc_slicecount
[] = {1, 2, 4};
117 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
118 * @intel_dp: DP struct
120 * If a CPU or PCH DP output is attached to an eDP panel, this function
121 * will return true, and false otherwise.
123 bool intel_dp_is_edp(struct intel_dp
*intel_dp
)
125 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
127 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
130 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
132 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
135 static void intel_dp_link_down(struct intel_encoder
*encoder
,
136 const struct intel_crtc_state
*old_crtc_state
);
137 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
138 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
139 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
140 const struct intel_crtc_state
*crtc_state
);
141 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
143 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
145 /* update sink rates from dpcd */
146 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
148 static const int dp_rates
[] = {
149 162000, 270000, 540000, 810000
153 max_rate
= drm_dp_bw_code_to_link_rate(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
155 for (i
= 0; i
< ARRAY_SIZE(dp_rates
); i
++) {
156 if (dp_rates
[i
] > max_rate
)
158 intel_dp
->sink_rates
[i
] = dp_rates
[i
];
161 intel_dp
->num_sink_rates
= i
;
164 /* Get length of rates array potentially limited by max_rate. */
165 static int intel_dp_rate_limit_len(const int *rates
, int len
, int max_rate
)
169 /* Limit results by potentially reduced max rate */
170 for (i
= 0; i
< len
; i
++) {
171 if (rates
[len
- i
- 1] <= max_rate
)
178 /* Get length of common rates array potentially limited by max_rate. */
179 static int intel_dp_common_len_rate_limit(const struct intel_dp
*intel_dp
,
182 return intel_dp_rate_limit_len(intel_dp
->common_rates
,
183 intel_dp
->num_common_rates
, max_rate
);
186 /* Theoretical max between source and sink */
187 static int intel_dp_max_common_rate(struct intel_dp
*intel_dp
)
189 return intel_dp
->common_rates
[intel_dp
->num_common_rates
- 1];
192 static int intel_dp_get_fia_supported_lane_count(struct intel_dp
*intel_dp
)
194 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
195 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
196 enum tc_port tc_port
= intel_port_to_tc(dev_priv
, dig_port
->base
.port
);
199 if (tc_port
== PORT_TC_NONE
|| dig_port
->tc_type
!= TC_PORT_TYPEC
)
202 lane_info
= (I915_READ(PORT_TX_DFLEXDPSP
) &
203 DP_LANE_ASSIGNMENT_MASK(tc_port
)) >>
204 DP_LANE_ASSIGNMENT_SHIFT(tc_port
);
208 MISSING_CASE(lane_info
);
222 /* Theoretical max between source and sink */
223 static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp
)
225 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
226 int source_max
= intel_dig_port
->max_lanes
;
227 int sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
228 int fia_max
= intel_dp_get_fia_supported_lane_count(intel_dp
);
230 return min3(source_max
, sink_max
, fia_max
);
233 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
235 return intel_dp
->max_link_lane_count
;
239 intel_dp_link_required(int pixel_clock
, int bpp
)
241 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
242 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
246 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
248 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
249 * link rate that is generally expressed in Gbps. Since, 8 bits of data
250 * is transmitted every LS_Clk per lane, there is no need to account for
251 * the channel encoding that is done in the PHY layer here.
254 return max_link_clock
* max_lanes
;
258 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
260 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
261 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
262 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
263 int max_dotclk
= dev_priv
->max_dotclk_freq
;
266 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
268 if (type
!= DP_DS_PORT_TYPE_VGA
)
271 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
272 intel_dp
->downstream_ports
);
274 if (ds_max_dotclk
!= 0)
275 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
280 static int cnl_max_source_rate(struct intel_dp
*intel_dp
)
282 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
283 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
284 enum port port
= dig_port
->base
.port
;
286 u32 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
288 /* Low voltage SKUs are limited to max of 5.4G */
289 if (voltage
== VOLTAGE_INFO_0_85V
)
292 /* For this SKU 8.1G is supported in all ports */
293 if (IS_CNL_WITH_PORT_F(dev_priv
))
296 /* For other SKUs, max rate on ports A and D is 5.4G */
297 if (port
== PORT_A
|| port
== PORT_D
)
303 static int icl_max_source_rate(struct intel_dp
*intel_dp
)
305 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
306 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
307 enum port port
= dig_port
->base
.port
;
309 if (intel_port_is_combophy(dev_priv
, port
) &&
310 !intel_dp_is_edp(intel_dp
))
317 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
319 /* The values must be in increasing order */
320 static const int cnl_rates
[] = {
321 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
323 static const int bxt_rates
[] = {
324 162000, 216000, 243000, 270000, 324000, 432000, 540000
326 static const int skl_rates
[] = {
327 162000, 216000, 270000, 324000, 432000, 540000
329 static const int hsw_rates
[] = {
330 162000, 270000, 540000
332 static const int g4x_rates
[] = {
335 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
336 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
337 const struct ddi_vbt_port_info
*info
=
338 &dev_priv
->vbt
.ddi_port_info
[dig_port
->base
.port
];
339 const int *source_rates
;
340 int size
, max_rate
= 0, vbt_max_rate
= info
->dp_max_link_rate
;
342 /* This should only be done once */
343 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
345 if (INTEL_GEN(dev_priv
) >= 10) {
346 source_rates
= cnl_rates
;
347 size
= ARRAY_SIZE(cnl_rates
);
348 if (IS_GEN(dev_priv
, 10))
349 max_rate
= cnl_max_source_rate(intel_dp
);
351 max_rate
= icl_max_source_rate(intel_dp
);
352 } else if (IS_GEN9_LP(dev_priv
)) {
353 source_rates
= bxt_rates
;
354 size
= ARRAY_SIZE(bxt_rates
);
355 } else if (IS_GEN9_BC(dev_priv
)) {
356 source_rates
= skl_rates
;
357 size
= ARRAY_SIZE(skl_rates
);
358 } else if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
359 IS_BROADWELL(dev_priv
)) {
360 source_rates
= hsw_rates
;
361 size
= ARRAY_SIZE(hsw_rates
);
363 source_rates
= g4x_rates
;
364 size
= ARRAY_SIZE(g4x_rates
);
367 if (max_rate
&& vbt_max_rate
)
368 max_rate
= min(max_rate
, vbt_max_rate
);
369 else if (vbt_max_rate
)
370 max_rate
= vbt_max_rate
;
373 size
= intel_dp_rate_limit_len(source_rates
, size
, max_rate
);
375 intel_dp
->source_rates
= source_rates
;
376 intel_dp
->num_source_rates
= size
;
379 static int intersect_rates(const int *source_rates
, int source_len
,
380 const int *sink_rates
, int sink_len
,
383 int i
= 0, j
= 0, k
= 0;
385 while (i
< source_len
&& j
< sink_len
) {
386 if (source_rates
[i
] == sink_rates
[j
]) {
387 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
389 common_rates
[k
] = source_rates
[i
];
393 } else if (source_rates
[i
] < sink_rates
[j
]) {
402 /* return index of rate in rates array, or -1 if not found */
403 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
407 for (i
= 0; i
< len
; i
++)
408 if (rate
== rates
[i
])
414 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
416 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
418 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
419 intel_dp
->num_source_rates
,
420 intel_dp
->sink_rates
,
421 intel_dp
->num_sink_rates
,
422 intel_dp
->common_rates
);
424 /* Paranoia, there should always be something in common. */
425 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
426 intel_dp
->common_rates
[0] = 162000;
427 intel_dp
->num_common_rates
= 1;
431 static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp
, int link_rate
,
435 * FIXME: we need to synchronize the current link parameters with
436 * hardware readout. Currently fast link training doesn't work on
439 if (link_rate
== 0 ||
440 link_rate
> intel_dp
->max_link_rate
)
443 if (lane_count
== 0 ||
444 lane_count
> intel_dp_max_lane_count(intel_dp
))
450 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp
*intel_dp
,
454 const struct drm_display_mode
*fixed_mode
=
455 intel_dp
->attached_connector
->panel
.fixed_mode
;
456 int mode_rate
, max_rate
;
458 mode_rate
= intel_dp_link_required(fixed_mode
->clock
, 18);
459 max_rate
= intel_dp_max_data_rate(link_rate
, lane_count
);
460 if (mode_rate
> max_rate
)
466 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
467 int link_rate
, u8 lane_count
)
471 index
= intel_dp_rate_index(intel_dp
->common_rates
,
472 intel_dp
->num_common_rates
,
475 if (intel_dp_is_edp(intel_dp
) &&
476 !intel_dp_can_link_train_fallback_for_edp(intel_dp
,
477 intel_dp
->common_rates
[index
- 1],
479 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
482 intel_dp
->max_link_rate
= intel_dp
->common_rates
[index
- 1];
483 intel_dp
->max_link_lane_count
= lane_count
;
484 } else if (lane_count
> 1) {
485 if (intel_dp_is_edp(intel_dp
) &&
486 !intel_dp_can_link_train_fallback_for_edp(intel_dp
,
487 intel_dp_max_common_rate(intel_dp
),
489 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
492 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
493 intel_dp
->max_link_lane_count
= lane_count
>> 1;
495 DRM_ERROR("Link Training Unsuccessful\n");
502 static enum drm_mode_status
503 intel_dp_mode_valid(struct drm_connector
*connector
,
504 struct drm_display_mode
*mode
)
506 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
507 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
508 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
509 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
510 int target_clock
= mode
->clock
;
511 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
513 u16 dsc_max_output_bpp
= 0;
514 u8 dsc_slice_count
= 0;
516 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
517 return MODE_NO_DBLESCAN
;
519 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
521 if (intel_dp_is_edp(intel_dp
) && fixed_mode
) {
522 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
525 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
528 target_clock
= fixed_mode
->clock
;
531 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
532 max_lanes
= intel_dp_max_lane_count(intel_dp
);
534 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
535 mode_rate
= intel_dp_link_required(target_clock
, 18);
538 * Output bpp is stored in 6.4 format so right shift by 4 to get the
539 * integer value since we support only integer values of bpp.
541 if ((INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)) &&
542 drm_dp_sink_supports_dsc(intel_dp
->dsc_dpcd
)) {
543 if (intel_dp_is_edp(intel_dp
)) {
545 drm_edp_dsc_sink_output_bpp(intel_dp
->dsc_dpcd
) >> 4;
547 drm_dp_dsc_sink_max_slice_count(intel_dp
->dsc_dpcd
,
549 } else if (drm_dp_sink_supports_fec(intel_dp
->fec_capable
)) {
551 intel_dp_dsc_get_output_bpp(max_link_clock
,
554 mode
->hdisplay
) >> 4;
556 intel_dp_dsc_get_slice_count(intel_dp
,
562 if ((mode_rate
> max_rate
&& !(dsc_max_output_bpp
&& dsc_slice_count
)) ||
563 target_clock
> max_dotclk
)
564 return MODE_CLOCK_HIGH
;
566 if (mode
->clock
< 10000)
567 return MODE_CLOCK_LOW
;
569 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
570 return MODE_H_ILLEGAL
;
575 u32
intel_dp_pack_aux(const u8
*src
, int src_bytes
)
582 for (i
= 0; i
< src_bytes
; i
++)
583 v
|= ((u32
)src
[i
]) << ((3 - i
) * 8);
587 static void intel_dp_unpack_aux(u32 src
, u8
*dst
, int dst_bytes
)
592 for (i
= 0; i
< dst_bytes
; i
++)
593 dst
[i
] = src
>> ((3-i
) * 8);
597 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
599 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
600 bool force_disable_vdd
);
602 intel_dp_pps_init(struct intel_dp
*intel_dp
);
604 static intel_wakeref_t
605 pps_lock(struct intel_dp
*intel_dp
)
607 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
608 intel_wakeref_t wakeref
;
611 * See intel_power_sequencer_reset() why we need
612 * a power domain reference here.
614 wakeref
= intel_display_power_get(dev_priv
,
615 intel_aux_power_domain(dp_to_dig_port(intel_dp
)));
617 mutex_lock(&dev_priv
->pps_mutex
);
622 static intel_wakeref_t
623 pps_unlock(struct intel_dp
*intel_dp
, intel_wakeref_t wakeref
)
625 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
627 mutex_unlock(&dev_priv
->pps_mutex
);
628 intel_display_power_put(dev_priv
,
629 intel_aux_power_domain(dp_to_dig_port(intel_dp
)),
634 #define with_pps_lock(dp, wf) \
635 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
638 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
640 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
641 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
642 enum pipe pipe
= intel_dp
->pps_pipe
;
643 bool pll_enabled
, release_cl_override
= false;
644 enum dpio_phy phy
= DPIO_PHY(pipe
);
645 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
648 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
649 "skipping pipe %c power sequencer kick due to port %c being active\n",
650 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
)))
653 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
654 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
656 /* Preserve the BIOS-computed detected bit. This is
657 * supposed to be read-only.
659 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
660 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
661 DP
|= DP_PORT_WIDTH(1);
662 DP
|= DP_LINK_TRAIN_PAT_1
;
664 if (IS_CHERRYVIEW(dev_priv
))
665 DP
|= DP_PIPE_SEL_CHV(pipe
);
667 DP
|= DP_PIPE_SEL(pipe
);
669 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
672 * The DPLL for the pipe must be enabled for this to work.
673 * So enable temporarily it if it's not already enabled.
676 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
677 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
679 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
680 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
681 DRM_ERROR("Failed to force on pll for pipe %c!\n",
688 * Similar magic as in intel_dp_enable_port().
689 * We _must_ do this port enable + disable trick
690 * to make this power sequencer lock onto the port.
691 * Otherwise even VDD force bit won't work.
693 I915_WRITE(intel_dp
->output_reg
, DP
);
694 POSTING_READ(intel_dp
->output_reg
);
696 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
697 POSTING_READ(intel_dp
->output_reg
);
699 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
700 POSTING_READ(intel_dp
->output_reg
);
703 vlv_force_pll_off(dev_priv
, pipe
);
705 if (release_cl_override
)
706 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
710 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
712 struct intel_encoder
*encoder
;
713 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
716 * We don't have power sequencer currently.
717 * Pick one that's not used by other ports.
719 for_each_intel_dp(&dev_priv
->drm
, encoder
) {
720 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
722 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
723 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
724 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
726 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
727 pipes
&= ~(1 << intel_dp
->pps_pipe
);
729 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
731 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
732 pipes
&= ~(1 << intel_dp
->active_pipe
);
739 return ffs(pipes
) - 1;
743 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
745 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
746 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
749 lockdep_assert_held(&dev_priv
->pps_mutex
);
751 /* We should never land here with regular DP ports */
752 WARN_ON(!intel_dp_is_edp(intel_dp
));
754 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
755 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
757 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
758 return intel_dp
->pps_pipe
;
760 pipe
= vlv_find_free_pps(dev_priv
);
763 * Didn't find one. This should not happen since there
764 * are two power sequencers and up to two eDP ports.
766 if (WARN_ON(pipe
== INVALID_PIPE
))
769 vlv_steal_power_sequencer(dev_priv
, pipe
);
770 intel_dp
->pps_pipe
= pipe
;
772 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
773 pipe_name(intel_dp
->pps_pipe
),
774 port_name(intel_dig_port
->base
.port
));
776 /* init power sequencer on this pipe and port */
777 intel_dp_init_panel_power_sequencer(intel_dp
);
778 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
781 * Even vdd force doesn't work until we've made
782 * the power sequencer lock in on the port.
784 vlv_power_sequencer_kick(intel_dp
);
786 return intel_dp
->pps_pipe
;
790 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
792 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
793 int backlight_controller
= dev_priv
->vbt
.backlight
.controller
;
795 lockdep_assert_held(&dev_priv
->pps_mutex
);
797 /* We should never land here with regular DP ports */
798 WARN_ON(!intel_dp_is_edp(intel_dp
));
800 if (!intel_dp
->pps_reset
)
801 return backlight_controller
;
803 intel_dp
->pps_reset
= false;
806 * Only the HW needs to be reprogrammed, the SW state is fixed and
807 * has been setup during connector init.
809 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
811 return backlight_controller
;
814 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
817 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
820 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
823 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
826 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
829 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
836 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
838 vlv_pipe_check pipe_check
)
842 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
843 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
844 PANEL_PORT_SELECT_MASK
;
846 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
849 if (!pipe_check(dev_priv
, pipe
))
859 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
861 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
862 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
863 enum port port
= intel_dig_port
->base
.port
;
865 lockdep_assert_held(&dev_priv
->pps_mutex
);
867 /* try to find a pipe with this port selected */
868 /* first pick one where the panel is on */
869 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
871 /* didn't find one? pick one where vdd is on */
872 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
873 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
874 vlv_pipe_has_vdd_on
);
875 /* didn't find one? pick one with just the correct port */
876 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
877 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
880 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
881 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
882 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
887 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
888 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
890 intel_dp_init_panel_power_sequencer(intel_dp
);
891 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
894 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
896 struct intel_encoder
*encoder
;
898 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
899 !IS_GEN9_LP(dev_priv
)))
903 * We can't grab pps_mutex here due to deadlock with power_domain
904 * mutex when power_domain functions are called while holding pps_mutex.
905 * That also means that in order to use pps_pipe the code needs to
906 * hold both a power domain reference and pps_mutex, and the power domain
907 * reference get/put must be done while _not_ holding pps_mutex.
908 * pps_{lock,unlock}() do these steps in the correct order, so one
909 * should use them always.
912 for_each_intel_dp(&dev_priv
->drm
, encoder
) {
913 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
915 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
917 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
920 if (IS_GEN9_LP(dev_priv
))
921 intel_dp
->pps_reset
= true;
923 intel_dp
->pps_pipe
= INVALID_PIPE
;
927 struct pps_registers
{
935 static void intel_pps_get_registers(struct intel_dp
*intel_dp
,
936 struct pps_registers
*regs
)
938 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
941 memset(regs
, 0, sizeof(*regs
));
943 if (IS_GEN9_LP(dev_priv
))
944 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
945 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
946 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
948 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
949 regs
->pp_stat
= PP_STATUS(pps_idx
);
950 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
951 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
952 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
953 !HAS_PCH_ICP(dev_priv
))
954 regs
->pp_div
= PP_DIVISOR(pps_idx
);
958 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
960 struct pps_registers regs
;
962 intel_pps_get_registers(intel_dp
, ®s
);
968 _pp_stat_reg(struct intel_dp
*intel_dp
)
970 struct pps_registers regs
;
972 intel_pps_get_registers(intel_dp
, ®s
);
977 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
978 This function only applicable when panel PM state is not to be tracked */
979 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
982 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
984 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
985 intel_wakeref_t wakeref
;
987 if (!intel_dp_is_edp(intel_dp
) || code
!= SYS_RESTART
)
990 with_pps_lock(intel_dp
, wakeref
) {
991 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
992 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
993 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
996 pp_ctrl_reg
= PP_CONTROL(pipe
);
997 pp_div_reg
= PP_DIVISOR(pipe
);
998 pp_div
= I915_READ(pp_div_reg
);
999 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
1001 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1002 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
1003 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
);
1004 msleep(intel_dp
->panel_power_cycle_delay
);
1011 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
1013 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1015 lockdep_assert_held(&dev_priv
->pps_mutex
);
1017 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
1018 intel_dp
->pps_pipe
== INVALID_PIPE
)
1021 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
1024 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
1026 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1028 lockdep_assert_held(&dev_priv
->pps_mutex
);
1030 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
1031 intel_dp
->pps_pipe
== INVALID_PIPE
)
1034 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
1038 intel_dp_check_edp(struct intel_dp
*intel_dp
)
1040 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1042 if (!intel_dp_is_edp(intel_dp
))
1045 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
1046 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1047 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1048 I915_READ(_pp_stat_reg(intel_dp
)),
1049 I915_READ(_pp_ctrl_reg(intel_dp
)));
1054 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
)
1056 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1057 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
1061 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1062 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
1063 msecs_to_jiffies_timeout(10));
1065 /* just trace the final value */
1066 trace_i915_reg_rw(false, ch_ctl
, status
, sizeof(status
), true);
1069 DRM_ERROR("dp aux hw did not signal timeout!\n");
1075 static u32
g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1077 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1083 * The clock divider is based off the hrawclk, and would like to run at
1084 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1086 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
1089 static u32
ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1091 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1092 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1098 * The clock divider is based off the cdclk or PCH rawclk, and would
1099 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1100 * divide by 2000 and use that
1102 if (dig_port
->aux_ch
== AUX_CH_A
)
1103 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
1105 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
1108 static u32
hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1110 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1111 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1113 if (dig_port
->aux_ch
!= AUX_CH_A
&& HAS_PCH_LPT_H(dev_priv
)) {
1114 /* Workaround for non-ULT HSW */
1122 return ilk_get_aux_clock_divider(intel_dp
, index
);
1125 static u32
skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1128 * SKL doesn't need us to program the AUX clock divider (Hardware will
1129 * derive the clock from CDCLK automatically). We still implement the
1130 * get_aux_clock_divider vfunc to plug-in into the existing code.
1132 return index
? 0 : 1;
1135 static u32
g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1137 u32 aux_clock_divider
)
1139 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1140 struct drm_i915_private
*dev_priv
=
1141 to_i915(intel_dig_port
->base
.base
.dev
);
1142 u32 precharge
, timeout
;
1144 if (IS_GEN(dev_priv
, 6))
1149 if (IS_BROADWELL(dev_priv
))
1150 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
1152 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
1154 return DP_AUX_CH_CTL_SEND_BUSY
|
1155 DP_AUX_CH_CTL_DONE
|
1156 DP_AUX_CH_CTL_INTERRUPT
|
1157 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1159 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1160 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1161 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1162 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1165 static u32
skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1169 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1172 ret
= DP_AUX_CH_CTL_SEND_BUSY
|
1173 DP_AUX_CH_CTL_DONE
|
1174 DP_AUX_CH_CTL_INTERRUPT
|
1175 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1176 DP_AUX_CH_CTL_TIME_OUT_MAX
|
1177 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1178 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1179 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1180 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1182 if (intel_dig_port
->tc_type
== TC_PORT_TBT
)
1183 ret
|= DP_AUX_CH_CTL_TBT_IO
;
1189 intel_dp_aux_xfer(struct intel_dp
*intel_dp
,
1190 const u8
*send
, int send_bytes
,
1191 u8
*recv
, int recv_size
,
1192 u32 aux_send_ctl_flags
)
1194 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1195 struct drm_i915_private
*dev_priv
=
1196 to_i915(intel_dig_port
->base
.base
.dev
);
1197 i915_reg_t ch_ctl
, ch_data
[5];
1198 u32 aux_clock_divider
;
1199 intel_wakeref_t wakeref
;
1200 int i
, ret
, recv_bytes
;
1205 ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
1206 for (i
= 0; i
< ARRAY_SIZE(ch_data
); i
++)
1207 ch_data
[i
] = intel_dp
->aux_ch_data_reg(intel_dp
, i
);
1209 wakeref
= pps_lock(intel_dp
);
1212 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1213 * In such cases we want to leave VDD enabled and it's up to upper layers
1214 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1217 vdd
= edp_panel_vdd_on(intel_dp
);
1219 /* dp aux is extremely sensitive to irq latency, hence request the
1220 * lowest possible wakeup latency and so prevent the cpu from going into
1221 * deep sleep states.
1223 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1225 intel_dp_check_edp(intel_dp
);
1227 /* Try to wait for any previous AUX channel activity */
1228 for (try = 0; try < 3; try++) {
1229 status
= I915_READ_NOTRACE(ch_ctl
);
1230 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1234 /* just trace the final value */
1235 trace_i915_reg_rw(false, ch_ctl
, status
, sizeof(status
), true);
1238 static u32 last_status
= -1;
1239 const u32 status
= I915_READ(ch_ctl
);
1241 if (status
!= last_status
) {
1242 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1244 last_status
= status
;
1251 /* Only 5 data registers! */
1252 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1257 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1258 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1262 send_ctl
|= aux_send_ctl_flags
;
1264 /* Must try at least 3 times according to DP spec */
1265 for (try = 0; try < 5; try++) {
1266 /* Load the send data into the aux channel data registers */
1267 for (i
= 0; i
< send_bytes
; i
+= 4)
1268 I915_WRITE(ch_data
[i
>> 2],
1269 intel_dp_pack_aux(send
+ i
,
1272 /* Send the command and wait for it to complete */
1273 I915_WRITE(ch_ctl
, send_ctl
);
1275 status
= intel_dp_aux_wait_done(intel_dp
);
1277 /* Clear done status and any errors */
1280 DP_AUX_CH_CTL_DONE
|
1281 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1282 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1284 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1285 * 400us delay required for errors and timeouts
1286 * Timeout errors from the HW already meet this
1287 * requirement so skip to next iteration
1289 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1292 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1293 usleep_range(400, 500);
1296 if (status
& DP_AUX_CH_CTL_DONE
)
1301 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1302 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1308 /* Check for timeout or receive error.
1309 * Timeouts occur when the sink is not connected
1311 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1312 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1317 /* Timeouts occur when the device isn't connected, so they're
1318 * "normal" -- don't fill the kernel log with these */
1319 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1320 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1325 /* Unload any bytes sent back from the other side */
1326 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1327 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1330 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1331 * We have no idea of what happened so we return -EBUSY so
1332 * drm layer takes care for the necessary retries.
1334 if (recv_bytes
== 0 || recv_bytes
> 20) {
1335 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1341 if (recv_bytes
> recv_size
)
1342 recv_bytes
= recv_size
;
1344 for (i
= 0; i
< recv_bytes
; i
+= 4)
1345 intel_dp_unpack_aux(I915_READ(ch_data
[i
>> 2]),
1346 recv
+ i
, recv_bytes
- i
);
1350 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1353 edp_panel_vdd_off(intel_dp
, false);
1355 pps_unlock(intel_dp
, wakeref
);
1360 #define BARE_ADDRESS_SIZE 3
1361 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1364 intel_dp_aux_header(u8 txbuf
[HEADER_SIZE
],
1365 const struct drm_dp_aux_msg
*msg
)
1367 txbuf
[0] = (msg
->request
<< 4) | ((msg
->address
>> 16) & 0xf);
1368 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1369 txbuf
[2] = msg
->address
& 0xff;
1370 txbuf
[3] = msg
->size
- 1;
1374 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1376 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1377 u8 txbuf
[20], rxbuf
[20];
1378 size_t txsize
, rxsize
;
1381 intel_dp_aux_header(txbuf
, msg
);
1383 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1384 case DP_AUX_NATIVE_WRITE
:
1385 case DP_AUX_I2C_WRITE
:
1386 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1387 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1388 rxsize
= 2; /* 0 or 1 data bytes */
1390 if (WARN_ON(txsize
> 20))
1393 WARN_ON(!msg
->buffer
!= !msg
->size
);
1396 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1398 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1401 msg
->reply
= rxbuf
[0] >> 4;
1404 /* Number of bytes written in a short write. */
1405 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1407 /* Return payload size. */
1413 case DP_AUX_NATIVE_READ
:
1414 case DP_AUX_I2C_READ
:
1415 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1416 rxsize
= msg
->size
+ 1;
1418 if (WARN_ON(rxsize
> 20))
1421 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1424 msg
->reply
= rxbuf
[0] >> 4;
1426 * Assume happy day, and copy the data. The caller is
1427 * expected to check msg->reply before touching it.
1429 * Return payload size.
1432 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1445 static i915_reg_t
g4x_aux_ctl_reg(struct intel_dp
*intel_dp
)
1447 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1448 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1449 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1455 return DP_AUX_CH_CTL(aux_ch
);
1457 MISSING_CASE(aux_ch
);
1458 return DP_AUX_CH_CTL(AUX_CH_B
);
1462 static i915_reg_t
g4x_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1464 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1465 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1466 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1472 return DP_AUX_CH_DATA(aux_ch
, index
);
1474 MISSING_CASE(aux_ch
);
1475 return DP_AUX_CH_DATA(AUX_CH_B
, index
);
1479 static i915_reg_t
ilk_aux_ctl_reg(struct intel_dp
*intel_dp
)
1481 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1482 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1483 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1487 return DP_AUX_CH_CTL(aux_ch
);
1491 return PCH_DP_AUX_CH_CTL(aux_ch
);
1493 MISSING_CASE(aux_ch
);
1494 return DP_AUX_CH_CTL(AUX_CH_A
);
1498 static i915_reg_t
ilk_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1500 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1501 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1502 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1506 return DP_AUX_CH_DATA(aux_ch
, index
);
1510 return PCH_DP_AUX_CH_DATA(aux_ch
, index
);
1512 MISSING_CASE(aux_ch
);
1513 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1517 static i915_reg_t
skl_aux_ctl_reg(struct intel_dp
*intel_dp
)
1519 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1520 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1521 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1530 return DP_AUX_CH_CTL(aux_ch
);
1532 MISSING_CASE(aux_ch
);
1533 return DP_AUX_CH_CTL(AUX_CH_A
);
1537 static i915_reg_t
skl_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1539 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1540 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1541 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1550 return DP_AUX_CH_DATA(aux_ch
, index
);
1552 MISSING_CASE(aux_ch
);
1553 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1558 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1560 kfree(intel_dp
->aux
.name
);
1564 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1566 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1567 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1568 struct intel_encoder
*encoder
= &dig_port
->base
;
1570 if (INTEL_GEN(dev_priv
) >= 9) {
1571 intel_dp
->aux_ch_ctl_reg
= skl_aux_ctl_reg
;
1572 intel_dp
->aux_ch_data_reg
= skl_aux_data_reg
;
1573 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1574 intel_dp
->aux_ch_ctl_reg
= ilk_aux_ctl_reg
;
1575 intel_dp
->aux_ch_data_reg
= ilk_aux_data_reg
;
1577 intel_dp
->aux_ch_ctl_reg
= g4x_aux_ctl_reg
;
1578 intel_dp
->aux_ch_data_reg
= g4x_aux_data_reg
;
1581 if (INTEL_GEN(dev_priv
) >= 9)
1582 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
1583 else if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
1584 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
1585 else if (HAS_PCH_SPLIT(dev_priv
))
1586 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
1588 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
1590 if (INTEL_GEN(dev_priv
) >= 9)
1591 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
1593 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
1595 drm_dp_aux_init(&intel_dp
->aux
);
1597 /* Failure to allocate our preferred name is not critical */
1598 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c",
1599 port_name(encoder
->port
));
1600 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1603 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1605 int max_rate
= intel_dp
->source_rates
[intel_dp
->num_source_rates
- 1];
1607 return max_rate
>= 540000;
1610 bool intel_dp_source_supports_hbr3(struct intel_dp
*intel_dp
)
1612 int max_rate
= intel_dp
->source_rates
[intel_dp
->num_source_rates
- 1];
1614 return max_rate
>= 810000;
1618 intel_dp_set_clock(struct intel_encoder
*encoder
,
1619 struct intel_crtc_state
*pipe_config
)
1621 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1622 const struct dp_link_dpll
*divisor
= NULL
;
1625 if (IS_G4X(dev_priv
)) {
1627 count
= ARRAY_SIZE(g4x_dpll
);
1628 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1630 count
= ARRAY_SIZE(pch_dpll
);
1631 } else if (IS_CHERRYVIEW(dev_priv
)) {
1633 count
= ARRAY_SIZE(chv_dpll
);
1634 } else if (IS_VALLEYVIEW(dev_priv
)) {
1636 count
= ARRAY_SIZE(vlv_dpll
);
1639 if (divisor
&& count
) {
1640 for (i
= 0; i
< count
; i
++) {
1641 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1642 pipe_config
->dpll
= divisor
[i
].dpll
;
1643 pipe_config
->clock_set
= true;
1650 static void snprintf_int_array(char *str
, size_t len
,
1651 const int *array
, int nelem
)
1657 for (i
= 0; i
< nelem
; i
++) {
1658 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1666 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1668 char str
[128]; /* FIXME: too big for stack? */
1670 if ((drm_debug
& DRM_UT_KMS
) == 0)
1673 snprintf_int_array(str
, sizeof(str
),
1674 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1675 DRM_DEBUG_KMS("source rates: %s\n", str
);
1677 snprintf_int_array(str
, sizeof(str
),
1678 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1679 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1681 snprintf_int_array(str
, sizeof(str
),
1682 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1683 DRM_DEBUG_KMS("common rates: %s\n", str
);
1687 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1691 len
= intel_dp_common_len_rate_limit(intel_dp
, intel_dp
->max_link_rate
);
1692 if (WARN_ON(len
<= 0))
1695 return intel_dp
->common_rates
[len
- 1];
1698 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1700 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1701 intel_dp
->num_sink_rates
, rate
);
1709 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1710 u8
*link_bw
, u8
*rate_select
)
1712 /* eDP 1.4 rate select method. */
1713 if (intel_dp
->use_rate_select
) {
1716 intel_dp_rate_select(intel_dp
, port_clock
);
1718 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1723 struct link_config_limits
{
1724 int min_clock
, max_clock
;
1725 int min_lane_count
, max_lane_count
;
1726 int min_bpp
, max_bpp
;
1729 static bool intel_dp_source_supports_fec(struct intel_dp
*intel_dp
,
1730 const struct intel_crtc_state
*pipe_config
)
1732 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1734 return INTEL_GEN(dev_priv
) >= 11 &&
1735 pipe_config
->cpu_transcoder
!= TRANSCODER_A
;
1738 static bool intel_dp_supports_fec(struct intel_dp
*intel_dp
,
1739 const struct intel_crtc_state
*pipe_config
)
1741 return intel_dp_source_supports_fec(intel_dp
, pipe_config
) &&
1742 drm_dp_sink_supports_fec(intel_dp
->fec_capable
);
1745 static bool intel_dp_source_supports_dsc(struct intel_dp
*intel_dp
,
1746 const struct intel_crtc_state
*pipe_config
)
1748 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1750 return INTEL_GEN(dev_priv
) >= 10 &&
1751 pipe_config
->cpu_transcoder
!= TRANSCODER_A
;
1754 static bool intel_dp_supports_dsc(struct intel_dp
*intel_dp
,
1755 const struct intel_crtc_state
*pipe_config
)
1757 if (!intel_dp_is_edp(intel_dp
) && !pipe_config
->fec_enable
)
1760 return intel_dp_source_supports_dsc(intel_dp
, pipe_config
) &&
1761 drm_dp_sink_supports_dsc(intel_dp
->dsc_dpcd
);
1764 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1765 struct intel_crtc_state
*pipe_config
)
1767 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1768 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1771 bpp
= pipe_config
->pipe_bpp
;
1772 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1775 bpp
= min(bpp
, 3*bpc
);
1777 if (intel_dp_is_edp(intel_dp
)) {
1778 /* Get bpp from vbt only for panels that dont have bpp in edid */
1779 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1780 dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
) {
1781 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1782 dev_priv
->vbt
.edp
.bpp
);
1783 bpp
= dev_priv
->vbt
.edp
.bpp
;
1790 /* Adjust link config limits based on compliance test requests. */
1792 intel_dp_adjust_compliance_config(struct intel_dp
*intel_dp
,
1793 struct intel_crtc_state
*pipe_config
,
1794 struct link_config_limits
*limits
)
1796 /* For DP Compliance we override the computed bpp for the pipe */
1797 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1798 int bpp
= 3 * intel_dp
->compliance
.test_data
.bpc
;
1800 limits
->min_bpp
= limits
->max_bpp
= bpp
;
1801 pipe_config
->dither_force_disable
= bpp
== 6 * 3;
1803 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp
);
1806 /* Use values requested by Compliance Test Request */
1807 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1810 /* Validate the compliance test data since max values
1811 * might have changed due to link train fallback.
1813 if (intel_dp_link_params_valid(intel_dp
, intel_dp
->compliance
.test_link_rate
,
1814 intel_dp
->compliance
.test_lane_count
)) {
1815 index
= intel_dp_rate_index(intel_dp
->common_rates
,
1816 intel_dp
->num_common_rates
,
1817 intel_dp
->compliance
.test_link_rate
);
1819 limits
->min_clock
= limits
->max_clock
= index
;
1820 limits
->min_lane_count
= limits
->max_lane_count
=
1821 intel_dp
->compliance
.test_lane_count
;
1826 /* Optimize link config in order: max bpp, min clock, min lanes */
1828 intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp
,
1829 struct intel_crtc_state
*pipe_config
,
1830 const struct link_config_limits
*limits
)
1832 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1833 int bpp
, clock
, lane_count
;
1834 int mode_rate
, link_clock
, link_avail
;
1836 for (bpp
= limits
->max_bpp
; bpp
>= limits
->min_bpp
; bpp
-= 2 * 3) {
1837 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1840 for (clock
= limits
->min_clock
; clock
<= limits
->max_clock
; clock
++) {
1841 for (lane_count
= limits
->min_lane_count
;
1842 lane_count
<= limits
->max_lane_count
;
1844 link_clock
= intel_dp
->common_rates
[clock
];
1845 link_avail
= intel_dp_max_data_rate(link_clock
,
1848 if (mode_rate
<= link_avail
) {
1849 pipe_config
->lane_count
= lane_count
;
1850 pipe_config
->pipe_bpp
= bpp
;
1851 pipe_config
->port_clock
= link_clock
;
1862 static int intel_dp_dsc_compute_bpp(struct intel_dp
*intel_dp
, u8 dsc_max_bpc
)
1865 u8 dsc_bpc
[3] = {0};
1867 num_bpc
= drm_dp_dsc_sink_supported_input_bpcs(intel_dp
->dsc_dpcd
,
1869 for (i
= 0; i
< num_bpc
; i
++) {
1870 if (dsc_max_bpc
>= dsc_bpc
[i
])
1871 return dsc_bpc
[i
] * 3;
1877 static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp
,
1878 struct intel_crtc_state
*pipe_config
,
1879 struct drm_connector_state
*conn_state
,
1880 struct link_config_limits
*limits
)
1882 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1883 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1884 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1889 if (!intel_dp_supports_dsc(intel_dp
, pipe_config
))
1892 dsc_max_bpc
= min_t(u8
, DP_DSC_MAX_SUPPORTED_BPC
,
1893 conn_state
->max_requested_bpc
);
1895 pipe_bpp
= intel_dp_dsc_compute_bpp(intel_dp
, dsc_max_bpc
);
1896 if (pipe_bpp
< DP_DSC_MIN_SUPPORTED_BPC
* 3) {
1897 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1902 * For now enable DSC for max bpp, max link rate, max lane count.
1903 * Optimize this later for the minimum possible link rate/lane count
1904 * with DSC enabled for the requested mode.
1906 pipe_config
->pipe_bpp
= pipe_bpp
;
1907 pipe_config
->port_clock
= intel_dp
->common_rates
[limits
->max_clock
];
1908 pipe_config
->lane_count
= limits
->max_lane_count
;
1910 if (intel_dp_is_edp(intel_dp
)) {
1911 pipe_config
->dsc_params
.compressed_bpp
=
1912 min_t(u16
, drm_edp_dsc_sink_output_bpp(intel_dp
->dsc_dpcd
) >> 4,
1913 pipe_config
->pipe_bpp
);
1914 pipe_config
->dsc_params
.slice_count
=
1915 drm_dp_dsc_sink_max_slice_count(intel_dp
->dsc_dpcd
,
1918 u16 dsc_max_output_bpp
;
1919 u8 dsc_dp_slice_count
;
1921 dsc_max_output_bpp
=
1922 intel_dp_dsc_get_output_bpp(pipe_config
->port_clock
,
1923 pipe_config
->lane_count
,
1924 adjusted_mode
->crtc_clock
,
1925 adjusted_mode
->crtc_hdisplay
);
1926 dsc_dp_slice_count
=
1927 intel_dp_dsc_get_slice_count(intel_dp
,
1928 adjusted_mode
->crtc_clock
,
1929 adjusted_mode
->crtc_hdisplay
);
1930 if (!dsc_max_output_bpp
|| !dsc_dp_slice_count
) {
1931 DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1934 pipe_config
->dsc_params
.compressed_bpp
= min_t(u16
,
1935 dsc_max_output_bpp
>> 4,
1936 pipe_config
->pipe_bpp
);
1937 pipe_config
->dsc_params
.slice_count
= dsc_dp_slice_count
;
1940 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1941 * is greater than the maximum Cdclock and if slice count is even
1942 * then we need to use 2 VDSC instances.
1944 if (adjusted_mode
->crtc_clock
> dev_priv
->max_cdclk_freq
) {
1945 if (pipe_config
->dsc_params
.slice_count
> 1) {
1946 pipe_config
->dsc_params
.dsc_split
= true;
1948 DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1953 ret
= intel_dp_compute_dsc_params(intel_dp
, pipe_config
);
1955 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1956 "Compressed BPP = %d\n",
1957 pipe_config
->pipe_bpp
,
1958 pipe_config
->dsc_params
.compressed_bpp
);
1962 pipe_config
->dsc_params
.compression_enable
= true;
1963 DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1964 "Compressed Bpp = %d Slice Count = %d\n",
1965 pipe_config
->pipe_bpp
,
1966 pipe_config
->dsc_params
.compressed_bpp
,
1967 pipe_config
->dsc_params
.slice_count
);
1973 intel_dp_compute_link_config(struct intel_encoder
*encoder
,
1974 struct intel_crtc_state
*pipe_config
,
1975 struct drm_connector_state
*conn_state
)
1977 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1978 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1979 struct link_config_limits limits
;
1983 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
1984 intel_dp
->max_link_rate
);
1986 /* No common link rates between source and sink */
1987 WARN_ON(common_len
<= 0);
1989 limits
.min_clock
= 0;
1990 limits
.max_clock
= common_len
- 1;
1992 limits
.min_lane_count
= 1;
1993 limits
.max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1995 limits
.min_bpp
= 6 * 3;
1996 limits
.max_bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1998 if (intel_dp_is_edp(intel_dp
)) {
2000 * Use the maximum clock and number of lanes the eDP panel
2001 * advertizes being capable of. The panels are generally
2002 * designed to support only a single clock and lane
2003 * configuration, and typically these values correspond to the
2004 * native resolution of the panel.
2006 limits
.min_lane_count
= limits
.max_lane_count
;
2007 limits
.min_clock
= limits
.max_clock
;
2010 intel_dp_adjust_compliance_config(intel_dp
, pipe_config
, &limits
);
2012 DRM_DEBUG_KMS("DP link computation with max lane count %i "
2013 "max rate %d max bpp %d pixel clock %iKHz\n",
2014 limits
.max_lane_count
,
2015 intel_dp
->common_rates
[limits
.max_clock
],
2016 limits
.max_bpp
, adjusted_mode
->crtc_clock
);
2019 * Optimize for slow and wide. This is the place to add alternative
2020 * optimization policy.
2022 ret
= intel_dp_compute_link_config_wide(intel_dp
, pipe_config
, &limits
);
2024 /* enable compression if the mode doesn't fit available BW */
2025 DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp
->force_dsc_en
);
2026 if (ret
|| intel_dp
->force_dsc_en
) {
2027 ret
= intel_dp_dsc_compute_config(intel_dp
, pipe_config
,
2028 conn_state
, &limits
);
2033 if (pipe_config
->dsc_params
.compression_enable
) {
2034 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2035 pipe_config
->lane_count
, pipe_config
->port_clock
,
2036 pipe_config
->pipe_bpp
,
2037 pipe_config
->dsc_params
.compressed_bpp
);
2039 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2040 intel_dp_link_required(adjusted_mode
->crtc_clock
,
2041 pipe_config
->dsc_params
.compressed_bpp
),
2042 intel_dp_max_data_rate(pipe_config
->port_clock
,
2043 pipe_config
->lane_count
));
2045 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2046 pipe_config
->lane_count
, pipe_config
->port_clock
,
2047 pipe_config
->pipe_bpp
);
2049 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2050 intel_dp_link_required(adjusted_mode
->crtc_clock
,
2051 pipe_config
->pipe_bpp
),
2052 intel_dp_max_data_rate(pipe_config
->port_clock
,
2053 pipe_config
->lane_count
));
2059 intel_dp_compute_config(struct intel_encoder
*encoder
,
2060 struct intel_crtc_state
*pipe_config
,
2061 struct drm_connector_state
*conn_state
)
2063 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2064 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
2065 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2066 struct intel_lspcon
*lspcon
= enc_to_intel_lspcon(&encoder
->base
);
2067 enum port port
= encoder
->port
;
2068 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2069 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
2070 struct intel_digital_connector_state
*intel_conn_state
=
2071 to_intel_digital_connector_state(conn_state
);
2072 bool constant_n
= drm_dp_has_quirk(&intel_dp
->desc
,
2073 DP_DPCD_QUIRK_CONSTANT_N
);
2076 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
2077 pipe_config
->has_pch_encoder
= true;
2079 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
2081 lspcon_ycbcr420_config(&intel_connector
->base
, pipe_config
);
2083 pipe_config
->has_drrs
= false;
2084 if (IS_G4X(dev_priv
) || port
== PORT_A
)
2085 pipe_config
->has_audio
= false;
2086 else if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
2087 pipe_config
->has_audio
= intel_dp
->has_audio
;
2089 pipe_config
->has_audio
= intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
2091 if (intel_dp_is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2092 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
2095 if (INTEL_GEN(dev_priv
) >= 9) {
2096 ret
= skl_update_scaler_crtc(pipe_config
);
2101 if (HAS_GMCH(dev_priv
))
2102 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
2103 conn_state
->scaling_mode
);
2105 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
2106 conn_state
->scaling_mode
);
2109 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
2112 if (HAS_GMCH(dev_priv
) &&
2113 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2116 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
2119 pipe_config
->fec_enable
= !intel_dp_is_edp(intel_dp
) &&
2120 intel_dp_supports_fec(intel_dp
, pipe_config
);
2122 ret
= intel_dp_compute_link_config(encoder
, pipe_config
, conn_state
);
2126 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
2129 * CEA-861-E - 5.1 Default Encoding Parameters
2130 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2132 pipe_config
->limited_color_range
=
2133 pipe_config
->pipe_bpp
!= 18 &&
2134 drm_default_rgb_quant_range(adjusted_mode
) ==
2135 HDMI_QUANTIZATION_RANGE_LIMITED
;
2137 pipe_config
->limited_color_range
=
2138 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
2141 if (!pipe_config
->dsc_params
.compression_enable
)
2142 intel_link_compute_m_n(pipe_config
->pipe_bpp
,
2143 pipe_config
->lane_count
,
2144 adjusted_mode
->crtc_clock
,
2145 pipe_config
->port_clock
,
2146 &pipe_config
->dp_m_n
,
2149 intel_link_compute_m_n(pipe_config
->dsc_params
.compressed_bpp
,
2150 pipe_config
->lane_count
,
2151 adjusted_mode
->crtc_clock
,
2152 pipe_config
->port_clock
,
2153 &pipe_config
->dp_m_n
,
2156 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
2157 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
2158 pipe_config
->has_drrs
= true;
2159 intel_link_compute_m_n(pipe_config
->pipe_bpp
,
2160 pipe_config
->lane_count
,
2161 intel_connector
->panel
.downclock_mode
->clock
,
2162 pipe_config
->port_clock
,
2163 &pipe_config
->dp_m2_n2
,
2167 if (!HAS_DDI(dev_priv
))
2168 intel_dp_set_clock(encoder
, pipe_config
);
2170 intel_psr_compute_config(intel_dp
, pipe_config
);
2175 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
2176 int link_rate
, u8 lane_count
,
2179 intel_dp
->link_trained
= false;
2180 intel_dp
->link_rate
= link_rate
;
2181 intel_dp
->lane_count
= lane_count
;
2182 intel_dp
->link_mst
= link_mst
;
2185 static void intel_dp_prepare(struct intel_encoder
*encoder
,
2186 const struct intel_crtc_state
*pipe_config
)
2188 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2189 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2190 enum port port
= encoder
->port
;
2191 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2192 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
2194 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
2195 pipe_config
->lane_count
,
2196 intel_crtc_has_type(pipe_config
,
2197 INTEL_OUTPUT_DP_MST
));
2200 * There are four kinds of DP registers:
2207 * IBX PCH and CPU are the same for almost everything,
2208 * except that the CPU DP PLL is configured in this
2211 * CPT PCH is quite different, having many bits moved
2212 * to the TRANS_DP_CTL register instead. That
2213 * configuration happens (oddly) in ironlake_pch_enable
2216 /* Preserve the BIOS-computed detected bit. This is
2217 * supposed to be read-only.
2219 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
2221 /* Handle DP bits in common between all three register formats */
2222 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
2223 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
2225 /* Split out the IBX/CPU vs CPT settings */
2227 if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) {
2228 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
2229 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
2230 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
2231 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
2232 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
2234 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2235 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
2237 intel_dp
->DP
|= DP_PIPE_SEL_IVB(crtc
->pipe
);
2238 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2241 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
2243 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2244 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2245 trans_dp
|= TRANS_DP_ENH_FRAMING
;
2247 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
2248 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
2250 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
2251 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
2253 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
2254 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
2255 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
2256 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
2257 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
2259 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2260 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
2262 if (IS_CHERRYVIEW(dev_priv
))
2263 intel_dp
->DP
|= DP_PIPE_SEL_CHV(crtc
->pipe
);
2265 intel_dp
->DP
|= DP_PIPE_SEL(crtc
->pipe
);
2269 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2270 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2272 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2273 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2275 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2276 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2278 static void intel_pps_verify_state(struct intel_dp
*intel_dp
);
2280 static void wait_panel_status(struct intel_dp
*intel_dp
,
2284 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2285 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2287 lockdep_assert_held(&dev_priv
->pps_mutex
);
2289 intel_pps_verify_state(intel_dp
);
2291 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2292 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2294 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2296 I915_READ(pp_stat_reg
),
2297 I915_READ(pp_ctrl_reg
));
2299 if (intel_wait_for_register(dev_priv
,
2300 pp_stat_reg
, mask
, value
,
2302 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2303 I915_READ(pp_stat_reg
),
2304 I915_READ(pp_ctrl_reg
));
2306 DRM_DEBUG_KMS("Wait complete\n");
2309 static void wait_panel_on(struct intel_dp
*intel_dp
)
2311 DRM_DEBUG_KMS("Wait for panel power on\n");
2312 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
2315 static void wait_panel_off(struct intel_dp
*intel_dp
)
2317 DRM_DEBUG_KMS("Wait for panel power off time\n");
2318 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
2321 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
2323 ktime_t panel_power_on_time
;
2324 s64 panel_power_off_duration
;
2326 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2328 /* take the difference of currrent time and panel power off time
2329 * and then make panel wait for t11_t12 if needed. */
2330 panel_power_on_time
= ktime_get_boottime();
2331 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
2333 /* When we disable the VDD override bit last we have to do the manual
2335 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
2336 wait_remaining_ms_from_jiffies(jiffies
,
2337 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
2339 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
2342 static void wait_backlight_on(struct intel_dp
*intel_dp
)
2344 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
2345 intel_dp
->backlight_on_delay
);
2348 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
2350 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
2351 intel_dp
->backlight_off_delay
);
2354 /* Read the current pp_control value, unlocking the register if it
2358 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2360 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2363 lockdep_assert_held(&dev_priv
->pps_mutex
);
2365 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2366 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2367 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2368 control
&= ~PANEL_UNLOCK_MASK
;
2369 control
|= PANEL_UNLOCK_REGS
;
2375 * Must be paired with edp_panel_vdd_off().
2376 * Must hold pps_mutex around the whole on/off sequence.
2377 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2379 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2381 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2382 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2384 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2385 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2387 lockdep_assert_held(&dev_priv
->pps_mutex
);
2389 if (!intel_dp_is_edp(intel_dp
))
2392 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2393 intel_dp
->want_panel_vdd
= true;
2395 if (edp_have_panel_vdd(intel_dp
))
2396 return need_to_disable
;
2398 intel_display_power_get(dev_priv
,
2399 intel_aux_power_domain(intel_dig_port
));
2401 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2402 port_name(intel_dig_port
->base
.port
));
2404 if (!edp_have_panel_power(intel_dp
))
2405 wait_panel_power_cycle(intel_dp
);
2407 pp
= ironlake_get_pp_control(intel_dp
);
2408 pp
|= EDP_FORCE_VDD
;
2410 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2411 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2413 I915_WRITE(pp_ctrl_reg
, pp
);
2414 POSTING_READ(pp_ctrl_reg
);
2415 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2416 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2418 * If the panel wasn't on, delay before accessing aux channel
2420 if (!edp_have_panel_power(intel_dp
)) {
2421 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2422 port_name(intel_dig_port
->base
.port
));
2423 msleep(intel_dp
->panel_power_up_delay
);
2426 return need_to_disable
;
2430 * Must be paired with intel_edp_panel_vdd_off() or
2431 * intel_edp_panel_off().
2432 * Nested calls to these functions are not allowed since
2433 * we drop the lock. Caller must use some higher level
2434 * locking to prevent nested calls from other threads.
2436 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2438 intel_wakeref_t wakeref
;
2441 if (!intel_dp_is_edp(intel_dp
))
2445 with_pps_lock(intel_dp
, wakeref
)
2446 vdd
= edp_panel_vdd_on(intel_dp
);
2447 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2448 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2451 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2453 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2454 struct intel_digital_port
*intel_dig_port
=
2455 dp_to_dig_port(intel_dp
);
2457 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2459 lockdep_assert_held(&dev_priv
->pps_mutex
);
2461 WARN_ON(intel_dp
->want_panel_vdd
);
2463 if (!edp_have_panel_vdd(intel_dp
))
2466 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2467 port_name(intel_dig_port
->base
.port
));
2469 pp
= ironlake_get_pp_control(intel_dp
);
2470 pp
&= ~EDP_FORCE_VDD
;
2472 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2473 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2475 I915_WRITE(pp_ctrl_reg
, pp
);
2476 POSTING_READ(pp_ctrl_reg
);
2478 /* Make sure sequencer is idle before allowing subsequent activity */
2479 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2480 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2482 if ((pp
& PANEL_POWER_ON
) == 0)
2483 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2485 intel_display_power_put_unchecked(dev_priv
,
2486 intel_aux_power_domain(intel_dig_port
));
2489 static void edp_panel_vdd_work(struct work_struct
*__work
)
2491 struct intel_dp
*intel_dp
=
2492 container_of(to_delayed_work(__work
),
2493 struct intel_dp
, panel_vdd_work
);
2494 intel_wakeref_t wakeref
;
2496 with_pps_lock(intel_dp
, wakeref
) {
2497 if (!intel_dp
->want_panel_vdd
)
2498 edp_panel_vdd_off_sync(intel_dp
);
2502 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2504 unsigned long delay
;
2507 * Queue the timer to fire a long time from now (relative to the power
2508 * down delay) to keep the panel power up across a sequence of
2511 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2512 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2516 * Must be paired with edp_panel_vdd_on().
2517 * Must hold pps_mutex around the whole on/off sequence.
2518 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2520 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2522 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2524 lockdep_assert_held(&dev_priv
->pps_mutex
);
2526 if (!intel_dp_is_edp(intel_dp
))
2529 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2530 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2532 intel_dp
->want_panel_vdd
= false;
2535 edp_panel_vdd_off_sync(intel_dp
);
2537 edp_panel_vdd_schedule_off(intel_dp
);
2540 static void edp_panel_on(struct intel_dp
*intel_dp
)
2542 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2544 i915_reg_t pp_ctrl_reg
;
2546 lockdep_assert_held(&dev_priv
->pps_mutex
);
2548 if (!intel_dp_is_edp(intel_dp
))
2551 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2552 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2554 if (WARN(edp_have_panel_power(intel_dp
),
2555 "eDP port %c panel power already on\n",
2556 port_name(dp_to_dig_port(intel_dp
)->base
.port
)))
2559 wait_panel_power_cycle(intel_dp
);
2561 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2562 pp
= ironlake_get_pp_control(intel_dp
);
2563 if (IS_GEN(dev_priv
, 5)) {
2564 /* ILK workaround: disable reset around power sequence */
2565 pp
&= ~PANEL_POWER_RESET
;
2566 I915_WRITE(pp_ctrl_reg
, pp
);
2567 POSTING_READ(pp_ctrl_reg
);
2570 pp
|= PANEL_POWER_ON
;
2571 if (!IS_GEN(dev_priv
, 5))
2572 pp
|= PANEL_POWER_RESET
;
2574 I915_WRITE(pp_ctrl_reg
, pp
);
2575 POSTING_READ(pp_ctrl_reg
);
2577 wait_panel_on(intel_dp
);
2578 intel_dp
->last_power_on
= jiffies
;
2580 if (IS_GEN(dev_priv
, 5)) {
2581 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2582 I915_WRITE(pp_ctrl_reg
, pp
);
2583 POSTING_READ(pp_ctrl_reg
);
2587 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2589 intel_wakeref_t wakeref
;
2591 if (!intel_dp_is_edp(intel_dp
))
2594 with_pps_lock(intel_dp
, wakeref
)
2595 edp_panel_on(intel_dp
);
2599 static void edp_panel_off(struct intel_dp
*intel_dp
)
2601 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2602 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2604 i915_reg_t pp_ctrl_reg
;
2606 lockdep_assert_held(&dev_priv
->pps_mutex
);
2608 if (!intel_dp_is_edp(intel_dp
))
2611 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2612 port_name(dig_port
->base
.port
));
2614 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2615 port_name(dig_port
->base
.port
));
2617 pp
= ironlake_get_pp_control(intel_dp
);
2618 /* We need to switch off panel power _and_ force vdd, for otherwise some
2619 * panels get very unhappy and cease to work. */
2620 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2623 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2625 intel_dp
->want_panel_vdd
= false;
2627 I915_WRITE(pp_ctrl_reg
, pp
);
2628 POSTING_READ(pp_ctrl_reg
);
2630 wait_panel_off(intel_dp
);
2631 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2633 /* We got a reference when we enabled the VDD. */
2634 intel_display_power_put_unchecked(dev_priv
, intel_aux_power_domain(dig_port
));
2637 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2639 intel_wakeref_t wakeref
;
2641 if (!intel_dp_is_edp(intel_dp
))
2644 with_pps_lock(intel_dp
, wakeref
)
2645 edp_panel_off(intel_dp
);
2648 /* Enable backlight in the panel power control. */
2649 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2651 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2652 intel_wakeref_t wakeref
;
2655 * If we enable the backlight right away following a panel power
2656 * on, we may see slight flicker as the panel syncs with the eDP
2657 * link. So delay a bit to make sure the image is solid before
2658 * allowing it to appear.
2660 wait_backlight_on(intel_dp
);
2662 with_pps_lock(intel_dp
, wakeref
) {
2663 i915_reg_t pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2666 pp
= ironlake_get_pp_control(intel_dp
);
2667 pp
|= EDP_BLC_ENABLE
;
2669 I915_WRITE(pp_ctrl_reg
, pp
);
2670 POSTING_READ(pp_ctrl_reg
);
2674 /* Enable backlight PWM and backlight PP control. */
2675 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
2676 const struct drm_connector_state
*conn_state
)
2678 struct intel_dp
*intel_dp
= enc_to_intel_dp(conn_state
->best_encoder
);
2680 if (!intel_dp_is_edp(intel_dp
))
2683 DRM_DEBUG_KMS("\n");
2685 intel_panel_enable_backlight(crtc_state
, conn_state
);
2686 _intel_edp_backlight_on(intel_dp
);
2689 /* Disable backlight in the panel power control. */
2690 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2692 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2693 intel_wakeref_t wakeref
;
2695 if (!intel_dp_is_edp(intel_dp
))
2698 with_pps_lock(intel_dp
, wakeref
) {
2699 i915_reg_t pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2702 pp
= ironlake_get_pp_control(intel_dp
);
2703 pp
&= ~EDP_BLC_ENABLE
;
2705 I915_WRITE(pp_ctrl_reg
, pp
);
2706 POSTING_READ(pp_ctrl_reg
);
2709 intel_dp
->last_backlight_off
= jiffies
;
2710 edp_wait_backlight_off(intel_dp
);
2713 /* Disable backlight PP control and backlight PWM. */
2714 void intel_edp_backlight_off(const struct drm_connector_state
*old_conn_state
)
2716 struct intel_dp
*intel_dp
= enc_to_intel_dp(old_conn_state
->best_encoder
);
2718 if (!intel_dp_is_edp(intel_dp
))
2721 DRM_DEBUG_KMS("\n");
2723 _intel_edp_backlight_off(intel_dp
);
2724 intel_panel_disable_backlight(old_conn_state
);
2728 * Hook for controlling the panel power control backlight through the bl_power
2729 * sysfs attribute. Take care to handle multiple calls.
2731 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2734 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2735 intel_wakeref_t wakeref
;
2739 with_pps_lock(intel_dp
, wakeref
)
2740 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2741 if (is_enabled
== enable
)
2744 DRM_DEBUG_KMS("panel power control backlight %s\n",
2745 enable
? "enable" : "disable");
2748 _intel_edp_backlight_on(intel_dp
);
2750 _intel_edp_backlight_off(intel_dp
);
2753 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2755 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2756 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2757 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2759 I915_STATE_WARN(cur_state
!= state
,
2760 "DP port %c state assertion failure (expected %s, current %s)\n",
2761 port_name(dig_port
->base
.port
),
2762 onoff(state
), onoff(cur_state
));
2764 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2766 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2768 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2770 I915_STATE_WARN(cur_state
!= state
,
2771 "eDP PLL state assertion failure (expected %s, current %s)\n",
2772 onoff(state
), onoff(cur_state
));
2774 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2775 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2777 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2778 const struct intel_crtc_state
*pipe_config
)
2780 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2781 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2783 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2784 assert_dp_port_disabled(intel_dp
);
2785 assert_edp_pll_disabled(dev_priv
);
2787 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2788 pipe_config
->port_clock
);
2790 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2792 if (pipe_config
->port_clock
== 162000)
2793 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2795 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2797 I915_WRITE(DP_A
, intel_dp
->DP
);
2802 * [DevILK] Work around required when enabling DP PLL
2803 * while a pipe is enabled going to FDI:
2804 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2805 * 2. Program DP PLL enable
2807 if (IS_GEN(dev_priv
, 5))
2808 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2810 intel_dp
->DP
|= DP_PLL_ENABLE
;
2812 I915_WRITE(DP_A
, intel_dp
->DP
);
2817 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
,
2818 const struct intel_crtc_state
*old_crtc_state
)
2820 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
2821 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2823 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2824 assert_dp_port_disabled(intel_dp
);
2825 assert_edp_pll_enabled(dev_priv
);
2827 DRM_DEBUG_KMS("disabling eDP PLL\n");
2829 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2831 I915_WRITE(DP_A
, intel_dp
->DP
);
2836 static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp
)
2839 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2840 * be capable of signalling downstream hpd with a long pulse.
2841 * Whether or not that means D3 is safe to use is not clear,
2842 * but let's assume so until proven otherwise.
2844 * FIXME should really check all downstream ports...
2846 return intel_dp
->dpcd
[DP_DPCD_REV
] == 0x11 &&
2847 intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
&&
2848 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
;
2851 void intel_dp_sink_set_decompression_state(struct intel_dp
*intel_dp
,
2852 const struct intel_crtc_state
*crtc_state
,
2857 if (!crtc_state
->dsc_params
.compression_enable
)
2860 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_DSC_ENABLE
,
2861 enable
? DP_DECOMPRESSION_EN
: 0);
2863 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2864 enable
? "enable" : "disable");
2867 /* If the sink supports it, try to set the power state appropriately */
2868 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2872 /* Should have a valid DPCD by this point */
2873 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2876 if (mode
!= DRM_MODE_DPMS_ON
) {
2877 if (downstream_hpd_needs_d0(intel_dp
))
2880 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2883 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2886 * When turning on, we need to retry for 1ms to give the sink
2889 for (i
= 0; i
< 3; i
++) {
2890 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2897 if (ret
== 1 && lspcon
->active
)
2898 lspcon_wait_pcon_mode(lspcon
);
2902 DRM_DEBUG_KMS("failed to %s sink power state\n",
2903 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2906 static bool cpt_dp_port_selected(struct drm_i915_private
*dev_priv
,
2907 enum port port
, enum pipe
*pipe
)
2911 for_each_pipe(dev_priv
, p
) {
2912 u32 val
= I915_READ(TRANS_DP_CTL(p
));
2914 if ((val
& TRANS_DP_PORT_SEL_MASK
) == TRANS_DP_PORT_SEL(port
)) {
2920 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port
));
2922 /* must initialize pipe to something for the asserts */
2928 bool intel_dp_port_enabled(struct drm_i915_private
*dev_priv
,
2929 i915_reg_t dp_reg
, enum port port
,
2935 val
= I915_READ(dp_reg
);
2937 ret
= val
& DP_PORT_EN
;
2939 /* asserts want to know the pipe even if the port is disabled */
2940 if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
)
2941 *pipe
= (val
& DP_PIPE_SEL_MASK_IVB
) >> DP_PIPE_SEL_SHIFT_IVB
;
2942 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
2943 ret
&= cpt_dp_port_selected(dev_priv
, port
, pipe
);
2944 else if (IS_CHERRYVIEW(dev_priv
))
2945 *pipe
= (val
& DP_PIPE_SEL_MASK_CHV
) >> DP_PIPE_SEL_SHIFT_CHV
;
2947 *pipe
= (val
& DP_PIPE_SEL_MASK
) >> DP_PIPE_SEL_SHIFT
;
2952 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2955 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2956 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2957 intel_wakeref_t wakeref
;
2960 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
2961 encoder
->power_domain
);
2965 ret
= intel_dp_port_enabled(dev_priv
, intel_dp
->output_reg
,
2966 encoder
->port
, pipe
);
2968 intel_display_power_put(dev_priv
, encoder
->power_domain
, wakeref
);
2973 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2974 struct intel_crtc_state
*pipe_config
)
2976 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2977 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2979 enum port port
= encoder
->port
;
2980 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2982 if (encoder
->type
== INTEL_OUTPUT_EDP
)
2983 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_EDP
);
2985 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_DP
);
2987 tmp
= I915_READ(intel_dp
->output_reg
);
2989 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2991 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2992 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2994 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2995 flags
|= DRM_MODE_FLAG_PHSYNC
;
2997 flags
|= DRM_MODE_FLAG_NHSYNC
;
2999 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
3000 flags
|= DRM_MODE_FLAG_PVSYNC
;
3002 flags
|= DRM_MODE_FLAG_NVSYNC
;
3004 if (tmp
& DP_SYNC_HS_HIGH
)
3005 flags
|= DRM_MODE_FLAG_PHSYNC
;
3007 flags
|= DRM_MODE_FLAG_NHSYNC
;
3009 if (tmp
& DP_SYNC_VS_HIGH
)
3010 flags
|= DRM_MODE_FLAG_PVSYNC
;
3012 flags
|= DRM_MODE_FLAG_NVSYNC
;
3015 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
3017 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
3018 pipe_config
->limited_color_range
= true;
3020 pipe_config
->lane_count
=
3021 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
3023 intel_dp_get_m_n(crtc
, pipe_config
);
3025 if (port
== PORT_A
) {
3026 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
3027 pipe_config
->port_clock
= 162000;
3029 pipe_config
->port_clock
= 270000;
3032 pipe_config
->base
.adjusted_mode
.crtc_clock
=
3033 intel_dotclock_calculate(pipe_config
->port_clock
,
3034 &pipe_config
->dp_m_n
);
3036 if (intel_dp_is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
3037 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
3039 * This is a big fat ugly hack.
3041 * Some machines in UEFI boot mode provide us a VBT that has 18
3042 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3043 * unknown we fail to light up. Yet the same BIOS boots up with
3044 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3045 * max, not what it tells us to use.
3047 * Note: This will still be broken if the eDP panel is not lit
3048 * up by the BIOS, and thus we can't get the mode at module
3051 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3052 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
3053 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
3057 static void intel_disable_dp(struct intel_encoder
*encoder
,
3058 const struct intel_crtc_state
*old_crtc_state
,
3059 const struct drm_connector_state
*old_conn_state
)
3061 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3063 intel_dp
->link_trained
= false;
3065 if (old_crtc_state
->has_audio
)
3066 intel_audio_codec_disable(encoder
,
3067 old_crtc_state
, old_conn_state
);
3069 /* Make sure the panel is off before trying to change the mode. But also
3070 * ensure that we have vdd while we switch off the panel. */
3071 intel_edp_panel_vdd_on(intel_dp
);
3072 intel_edp_backlight_off(old_conn_state
);
3073 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
3074 intel_edp_panel_off(intel_dp
);
3077 static void g4x_disable_dp(struct intel_encoder
*encoder
,
3078 const struct intel_crtc_state
*old_crtc_state
,
3079 const struct drm_connector_state
*old_conn_state
)
3081 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
3084 static void vlv_disable_dp(struct intel_encoder
*encoder
,
3085 const struct intel_crtc_state
*old_crtc_state
,
3086 const struct drm_connector_state
*old_conn_state
)
3088 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
3091 static void g4x_post_disable_dp(struct intel_encoder
*encoder
,
3092 const struct intel_crtc_state
*old_crtc_state
,
3093 const struct drm_connector_state
*old_conn_state
)
3095 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3096 enum port port
= encoder
->port
;
3099 * Bspec does not list a specific disable sequence for g4x DP.
3100 * Follow the ilk+ sequence (disable pipe before the port) for
3101 * g4x DP as it does not suffer from underruns like the normal
3102 * g4x modeset sequence (disable pipe after the port).
3104 intel_dp_link_down(encoder
, old_crtc_state
);
3106 /* Only ilk+ has port A */
3108 ironlake_edp_pll_off(intel_dp
, old_crtc_state
);
3111 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
3112 const struct intel_crtc_state
*old_crtc_state
,
3113 const struct drm_connector_state
*old_conn_state
)
3115 intel_dp_link_down(encoder
, old_crtc_state
);
3118 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
3119 const struct intel_crtc_state
*old_crtc_state
,
3120 const struct drm_connector_state
*old_conn_state
)
3122 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3124 intel_dp_link_down(encoder
, old_crtc_state
);
3126 mutex_lock(&dev_priv
->sb_lock
);
3128 /* Assert data lane reset */
3129 chv_data_lane_soft_reset(encoder
, old_crtc_state
, true);
3131 mutex_unlock(&dev_priv
->sb_lock
);
3135 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3139 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3140 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3141 enum port port
= intel_dig_port
->base
.port
;
3142 u8 train_pat_mask
= drm_dp_training_pattern_mask(intel_dp
->dpcd
);
3144 if (dp_train_pat
& train_pat_mask
)
3145 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3146 dp_train_pat
& train_pat_mask
);
3148 if (HAS_DDI(dev_priv
)) {
3149 u32 temp
= I915_READ(DP_TP_CTL(port
));
3151 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
3152 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
3154 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
3156 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3157 switch (dp_train_pat
& train_pat_mask
) {
3158 case DP_TRAINING_PATTERN_DISABLE
:
3159 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
3162 case DP_TRAINING_PATTERN_1
:
3163 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
3165 case DP_TRAINING_PATTERN_2
:
3166 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
3168 case DP_TRAINING_PATTERN_3
:
3169 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
3171 case DP_TRAINING_PATTERN_4
:
3172 temp
|= DP_TP_CTL_LINK_TRAIN_PAT4
;
3175 I915_WRITE(DP_TP_CTL(port
), temp
);
3177 } else if ((IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) ||
3178 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3179 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3181 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
3182 case DP_TRAINING_PATTERN_DISABLE
:
3183 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
3185 case DP_TRAINING_PATTERN_1
:
3186 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
3188 case DP_TRAINING_PATTERN_2
:
3189 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
3191 case DP_TRAINING_PATTERN_3
:
3192 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3193 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
3198 *DP
&= ~DP_LINK_TRAIN_MASK
;
3200 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
3201 case DP_TRAINING_PATTERN_DISABLE
:
3202 *DP
|= DP_LINK_TRAIN_OFF
;
3204 case DP_TRAINING_PATTERN_1
:
3205 *DP
|= DP_LINK_TRAIN_PAT_1
;
3207 case DP_TRAINING_PATTERN_2
:
3208 *DP
|= DP_LINK_TRAIN_PAT_2
;
3210 case DP_TRAINING_PATTERN_3
:
3211 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3212 *DP
|= DP_LINK_TRAIN_PAT_2
;
3218 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
3219 const struct intel_crtc_state
*old_crtc_state
)
3221 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3223 /* enable with pattern 1 (as per spec) */
3225 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
3228 * Magic for VLV/CHV. We _must_ first set up the register
3229 * without actually enabling the port, and then do another
3230 * write to enable the port. Otherwise link training will
3231 * fail when the power sequencer is freshly used for this port.
3233 intel_dp
->DP
|= DP_PORT_EN
;
3234 if (old_crtc_state
->has_audio
)
3235 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
3237 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3238 POSTING_READ(intel_dp
->output_reg
);
3241 static void intel_enable_dp(struct intel_encoder
*encoder
,
3242 const struct intel_crtc_state
*pipe_config
,
3243 const struct drm_connector_state
*conn_state
)
3245 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3246 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3247 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
3248 u32 dp_reg
= I915_READ(intel_dp
->output_reg
);
3249 enum pipe pipe
= crtc
->pipe
;
3250 intel_wakeref_t wakeref
;
3252 if (WARN_ON(dp_reg
& DP_PORT_EN
))
3255 with_pps_lock(intel_dp
, wakeref
) {
3256 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3257 vlv_init_panel_power_sequencer(encoder
, pipe_config
);
3259 intel_dp_enable_port(intel_dp
, pipe_config
);
3261 edp_panel_vdd_on(intel_dp
);
3262 edp_panel_on(intel_dp
);
3263 edp_panel_vdd_off(intel_dp
, true);
3266 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3267 unsigned int lane_mask
= 0x0;
3269 if (IS_CHERRYVIEW(dev_priv
))
3270 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
3272 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
3276 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
3277 intel_dp_start_link_train(intel_dp
);
3278 intel_dp_stop_link_train(intel_dp
);
3280 if (pipe_config
->has_audio
) {
3281 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3283 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
3287 static void g4x_enable_dp(struct intel_encoder
*encoder
,
3288 const struct intel_crtc_state
*pipe_config
,
3289 const struct drm_connector_state
*conn_state
)
3291 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3292 intel_edp_backlight_on(pipe_config
, conn_state
);
3295 static void vlv_enable_dp(struct intel_encoder
*encoder
,
3296 const struct intel_crtc_state
*pipe_config
,
3297 const struct drm_connector_state
*conn_state
)
3299 intel_edp_backlight_on(pipe_config
, conn_state
);
3302 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
3303 const struct intel_crtc_state
*pipe_config
,
3304 const struct drm_connector_state
*conn_state
)
3306 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3307 enum port port
= encoder
->port
;
3309 intel_dp_prepare(encoder
, pipe_config
);
3311 /* Only ilk+ has port A */
3313 ironlake_edp_pll_on(intel_dp
, pipe_config
);
3316 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
3318 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3319 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
3320 enum pipe pipe
= intel_dp
->pps_pipe
;
3321 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
3323 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3325 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
3328 edp_panel_vdd_off_sync(intel_dp
);
3331 * VLV seems to get confused when multiple power sequencers
3332 * have the same port selected (even if only one has power/vdd
3333 * enabled). The failure manifests as vlv_wait_port_ready() failing
3334 * CHV on the other hand doesn't seem to mind having the same port
3335 * selected in multiple power sequencers, but let's clear the
3336 * port select always when logically disconnecting a power sequencer
3339 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3340 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
3341 I915_WRITE(pp_on_reg
, 0);
3342 POSTING_READ(pp_on_reg
);
3344 intel_dp
->pps_pipe
= INVALID_PIPE
;
3347 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
3350 struct intel_encoder
*encoder
;
3352 lockdep_assert_held(&dev_priv
->pps_mutex
);
3354 for_each_intel_dp(&dev_priv
->drm
, encoder
) {
3355 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3356 enum port port
= encoder
->port
;
3358 WARN(intel_dp
->active_pipe
== pipe
,
3359 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3360 pipe_name(pipe
), port_name(port
));
3362 if (intel_dp
->pps_pipe
!= pipe
)
3365 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3366 pipe_name(pipe
), port_name(port
));
3368 /* make sure vdd is off before we steal it */
3369 vlv_detach_power_sequencer(intel_dp
);
3373 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
3374 const struct intel_crtc_state
*crtc_state
)
3376 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3377 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3378 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3380 lockdep_assert_held(&dev_priv
->pps_mutex
);
3382 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3384 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
3385 intel_dp
->pps_pipe
!= crtc
->pipe
) {
3387 * If another power sequencer was being used on this
3388 * port previously make sure to turn off vdd there while
3389 * we still have control of it.
3391 vlv_detach_power_sequencer(intel_dp
);
3395 * We may be stealing the power
3396 * sequencer from another port.
3398 vlv_steal_power_sequencer(dev_priv
, crtc
->pipe
);
3400 intel_dp
->active_pipe
= crtc
->pipe
;
3402 if (!intel_dp_is_edp(intel_dp
))
3405 /* now it's all ours */
3406 intel_dp
->pps_pipe
= crtc
->pipe
;
3408 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3409 pipe_name(intel_dp
->pps_pipe
), port_name(encoder
->port
));
3411 /* init power sequencer on this pipe and port */
3412 intel_dp_init_panel_power_sequencer(intel_dp
);
3413 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
3416 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3417 const struct intel_crtc_state
*pipe_config
,
3418 const struct drm_connector_state
*conn_state
)
3420 vlv_phy_pre_encoder_enable(encoder
, pipe_config
);
3422 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3425 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3426 const struct intel_crtc_state
*pipe_config
,
3427 const struct drm_connector_state
*conn_state
)
3429 intel_dp_prepare(encoder
, pipe_config
);
3431 vlv_phy_pre_pll_enable(encoder
, pipe_config
);
3434 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3435 const struct intel_crtc_state
*pipe_config
,
3436 const struct drm_connector_state
*conn_state
)
3438 chv_phy_pre_encoder_enable(encoder
, pipe_config
);
3440 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3442 /* Second common lane will stay alive on its own now */
3443 chv_phy_release_cl2_override(encoder
);
3446 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3447 const struct intel_crtc_state
*pipe_config
,
3448 const struct drm_connector_state
*conn_state
)
3450 intel_dp_prepare(encoder
, pipe_config
);
3452 chv_phy_pre_pll_enable(encoder
, pipe_config
);
3455 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3456 const struct intel_crtc_state
*old_crtc_state
,
3457 const struct drm_connector_state
*old_conn_state
)
3459 chv_phy_post_pll_disable(encoder
, old_crtc_state
);
3463 * Fetch AUX CH registers 0x202 - 0x207 which contain
3464 * link status information
3467 intel_dp_get_link_status(struct intel_dp
*intel_dp
, u8 link_status
[DP_LINK_STATUS_SIZE
])
3469 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3470 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3473 /* These are source-specific values. */
3475 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3477 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3478 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3479 enum port port
= encoder
->port
;
3481 if (HAS_DDI(dev_priv
))
3482 return intel_ddi_dp_voltage_max(encoder
);
3483 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3484 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3485 else if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
)
3486 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3487 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3488 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3490 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3494 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, u8 voltage_swing
)
3496 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3497 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3498 enum port port
= encoder
->port
;
3500 if (HAS_DDI(dev_priv
)) {
3501 return intel_ddi_dp_pre_emphasis_max(encoder
, voltage_swing
);
3502 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3503 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3504 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3505 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3506 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3507 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3508 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3509 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3510 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3512 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3514 } else if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) {
3515 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3516 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3517 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3518 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3519 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3520 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3522 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3525 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3527 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3529 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3530 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3531 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3534 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3539 static u32
vlv_signal_levels(struct intel_dp
*intel_dp
)
3541 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3542 unsigned long demph_reg_value
, preemph_reg_value
,
3543 uniqtranscale_reg_value
;
3544 u8 train_set
= intel_dp
->train_set
[0];
3546 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3547 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3548 preemph_reg_value
= 0x0004000;
3549 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3550 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3551 demph_reg_value
= 0x2B405555;
3552 uniqtranscale_reg_value
= 0x552AB83A;
3554 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3555 demph_reg_value
= 0x2B404040;
3556 uniqtranscale_reg_value
= 0x5548B83A;
3558 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3559 demph_reg_value
= 0x2B245555;
3560 uniqtranscale_reg_value
= 0x5560B83A;
3562 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3563 demph_reg_value
= 0x2B405555;
3564 uniqtranscale_reg_value
= 0x5598DA3A;
3570 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3571 preemph_reg_value
= 0x0002000;
3572 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3573 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3574 demph_reg_value
= 0x2B404040;
3575 uniqtranscale_reg_value
= 0x5552B83A;
3577 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3578 demph_reg_value
= 0x2B404848;
3579 uniqtranscale_reg_value
= 0x5580B83A;
3581 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3582 demph_reg_value
= 0x2B404040;
3583 uniqtranscale_reg_value
= 0x55ADDA3A;
3589 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3590 preemph_reg_value
= 0x0000000;
3591 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3592 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3593 demph_reg_value
= 0x2B305555;
3594 uniqtranscale_reg_value
= 0x5570B83A;
3596 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3597 demph_reg_value
= 0x2B2B4040;
3598 uniqtranscale_reg_value
= 0x55ADDA3A;
3604 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3605 preemph_reg_value
= 0x0006000;
3606 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3607 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3608 demph_reg_value
= 0x1B405555;
3609 uniqtranscale_reg_value
= 0x55ADDA3A;
3619 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3620 uniqtranscale_reg_value
, 0);
3625 static u32
chv_signal_levels(struct intel_dp
*intel_dp
)
3627 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3628 u32 deemph_reg_value
, margin_reg_value
;
3629 bool uniq_trans_scale
= false;
3630 u8 train_set
= intel_dp
->train_set
[0];
3632 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3633 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3634 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3635 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3636 deemph_reg_value
= 128;
3637 margin_reg_value
= 52;
3639 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3640 deemph_reg_value
= 128;
3641 margin_reg_value
= 77;
3643 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3644 deemph_reg_value
= 128;
3645 margin_reg_value
= 102;
3647 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3648 deemph_reg_value
= 128;
3649 margin_reg_value
= 154;
3650 uniq_trans_scale
= true;
3656 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3657 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3658 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3659 deemph_reg_value
= 85;
3660 margin_reg_value
= 78;
3662 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3663 deemph_reg_value
= 85;
3664 margin_reg_value
= 116;
3666 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3667 deemph_reg_value
= 85;
3668 margin_reg_value
= 154;
3674 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3675 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3676 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3677 deemph_reg_value
= 64;
3678 margin_reg_value
= 104;
3680 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3681 deemph_reg_value
= 64;
3682 margin_reg_value
= 154;
3688 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3689 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3690 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3691 deemph_reg_value
= 43;
3692 margin_reg_value
= 154;
3702 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3703 margin_reg_value
, uniq_trans_scale
);
3709 g4x_signal_levels(u8 train_set
)
3711 u32 signal_levels
= 0;
3713 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3714 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3716 signal_levels
|= DP_VOLTAGE_0_4
;
3718 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3719 signal_levels
|= DP_VOLTAGE_0_6
;
3721 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3722 signal_levels
|= DP_VOLTAGE_0_8
;
3724 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3725 signal_levels
|= DP_VOLTAGE_1_2
;
3728 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3729 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3731 signal_levels
|= DP_PRE_EMPHASIS_0
;
3733 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3734 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3736 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3737 signal_levels
|= DP_PRE_EMPHASIS_6
;
3739 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3740 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3743 return signal_levels
;
3746 /* SNB CPU eDP voltage swing and pre-emphasis control */
3748 snb_cpu_edp_signal_levels(u8 train_set
)
3750 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3751 DP_TRAIN_PRE_EMPHASIS_MASK
);
3752 switch (signal_levels
) {
3753 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3754 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3755 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3756 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3757 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3758 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3759 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3760 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3761 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3762 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3763 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3764 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3765 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3766 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3768 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3769 "0x%x\n", signal_levels
);
3770 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3774 /* IVB CPU eDP voltage swing and pre-emphasis control */
3776 ivb_cpu_edp_signal_levels(u8 train_set
)
3778 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3779 DP_TRAIN_PRE_EMPHASIS_MASK
);
3780 switch (signal_levels
) {
3781 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3782 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3783 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3784 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3785 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3786 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3788 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3789 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3790 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3791 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3793 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3794 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3795 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3796 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3799 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3800 "0x%x\n", signal_levels
);
3801 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3806 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3808 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3809 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3810 enum port port
= intel_dig_port
->base
.port
;
3811 u32 signal_levels
, mask
= 0;
3812 u8 train_set
= intel_dp
->train_set
[0];
3814 if (IS_GEN9_LP(dev_priv
) || INTEL_GEN(dev_priv
) >= 10) {
3815 signal_levels
= bxt_signal_levels(intel_dp
);
3816 } else if (HAS_DDI(dev_priv
)) {
3817 signal_levels
= ddi_signal_levels(intel_dp
);
3818 mask
= DDI_BUF_EMP_MASK
;
3819 } else if (IS_CHERRYVIEW(dev_priv
)) {
3820 signal_levels
= chv_signal_levels(intel_dp
);
3821 } else if (IS_VALLEYVIEW(dev_priv
)) {
3822 signal_levels
= vlv_signal_levels(intel_dp
);
3823 } else if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) {
3824 signal_levels
= ivb_cpu_edp_signal_levels(train_set
);
3825 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3826 } else if (IS_GEN(dev_priv
, 6) && port
== PORT_A
) {
3827 signal_levels
= snb_cpu_edp_signal_levels(train_set
);
3828 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3830 signal_levels
= g4x_signal_levels(train_set
);
3831 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3835 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3837 DRM_DEBUG_KMS("Using vswing level %d\n",
3838 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3839 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3840 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3841 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3843 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3845 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3846 POSTING_READ(intel_dp
->output_reg
);
3850 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3853 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3854 struct drm_i915_private
*dev_priv
=
3855 to_i915(intel_dig_port
->base
.base
.dev
);
3857 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3859 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3860 POSTING_READ(intel_dp
->output_reg
);
3863 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3865 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3866 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3867 enum port port
= intel_dig_port
->base
.port
;
3870 if (!HAS_DDI(dev_priv
))
3873 val
= I915_READ(DP_TP_CTL(port
));
3874 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3875 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3876 I915_WRITE(DP_TP_CTL(port
), val
);
3879 * On PORT_A we can have only eDP in SST mode. There the only reason
3880 * we need to set idle transmission mode is to work around a HW issue
3881 * where we enable the pipe while not in idle link-training mode.
3882 * In this case there is requirement to wait for a minimum number of
3883 * idle patterns to be sent.
3888 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3889 DP_TP_STATUS_IDLE_DONE
,
3890 DP_TP_STATUS_IDLE_DONE
,
3892 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3896 intel_dp_link_down(struct intel_encoder
*encoder
,
3897 const struct intel_crtc_state
*old_crtc_state
)
3899 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3900 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3901 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
3902 enum port port
= encoder
->port
;
3903 u32 DP
= intel_dp
->DP
;
3905 if (WARN_ON(HAS_DDI(dev_priv
)))
3908 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3911 DRM_DEBUG_KMS("\n");
3913 if ((IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) ||
3914 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3915 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3916 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3918 DP
&= ~DP_LINK_TRAIN_MASK
;
3919 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3921 I915_WRITE(intel_dp
->output_reg
, DP
);
3922 POSTING_READ(intel_dp
->output_reg
);
3924 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3925 I915_WRITE(intel_dp
->output_reg
, DP
);
3926 POSTING_READ(intel_dp
->output_reg
);
3929 * HW workaround for IBX, we need to move the port
3930 * to transcoder A after disabling it to allow the
3931 * matching HDMI port to be enabled on transcoder A.
3933 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3935 * We get CPU/PCH FIFO underruns on the other pipe when
3936 * doing the workaround. Sweep them under the rug.
3938 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3939 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3941 /* always enable with pattern 1 (as per spec) */
3942 DP
&= ~(DP_PIPE_SEL_MASK
| DP_LINK_TRAIN_MASK
);
3943 DP
|= DP_PORT_EN
| DP_PIPE_SEL(PIPE_A
) |
3944 DP_LINK_TRAIN_PAT_1
;
3945 I915_WRITE(intel_dp
->output_reg
, DP
);
3946 POSTING_READ(intel_dp
->output_reg
);
3949 I915_WRITE(intel_dp
->output_reg
, DP
);
3950 POSTING_READ(intel_dp
->output_reg
);
3952 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
3953 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3954 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3957 msleep(intel_dp
->panel_power_down_delay
);
3961 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3962 intel_wakeref_t wakeref
;
3964 with_pps_lock(intel_dp
, wakeref
)
3965 intel_dp
->active_pipe
= INVALID_PIPE
;
3970 intel_dp_extended_receiver_capabilities(struct intel_dp
*intel_dp
)
3975 * Prior to DP1.3 the bit represented by
3976 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
3977 * if it is set DP_DPCD_REV at 0000h could be at a value less than
3978 * the true capability of the panel. The only way to check is to
3979 * then compare 0000h and 2200h.
3981 if (!(intel_dp
->dpcd
[DP_TRAINING_AUX_RD_INTERVAL
] &
3982 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT
))
3985 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DP13_DPCD_REV
,
3986 &dpcd_ext
, sizeof(dpcd_ext
)) != sizeof(dpcd_ext
)) {
3987 DRM_ERROR("DPCD failed read at extended capabilities\n");
3991 if (intel_dp
->dpcd
[DP_DPCD_REV
] > dpcd_ext
[DP_DPCD_REV
]) {
3992 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
3996 if (!memcmp(intel_dp
->dpcd
, dpcd_ext
, sizeof(dpcd_ext
)))
3999 DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4000 (int)sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
4002 memcpy(intel_dp
->dpcd
, dpcd_ext
, sizeof(dpcd_ext
));
4006 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
4008 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
4009 sizeof(intel_dp
->dpcd
)) < 0)
4010 return false; /* aux transfer failed */
4012 intel_dp_extended_receiver_capabilities(intel_dp
);
4014 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
4016 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
4019 static void intel_dp_get_dsc_sink_cap(struct intel_dp
*intel_dp
)
4022 * Clear the cached register set to avoid using stale values
4023 * for the sinks that do not support DSC.
4025 memset(intel_dp
->dsc_dpcd
, 0, sizeof(intel_dp
->dsc_dpcd
));
4027 /* Clear fec_capable to avoid using stale values */
4028 intel_dp
->fec_capable
= 0;
4030 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4031 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x14 ||
4032 intel_dp
->edp_dpcd
[0] >= DP_EDP_14
) {
4033 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DSC_SUPPORT
,
4035 sizeof(intel_dp
->dsc_dpcd
)) < 0)
4036 DRM_ERROR("Failed to read DPCD register 0x%x\n",
4039 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4040 (int)sizeof(intel_dp
->dsc_dpcd
),
4041 intel_dp
->dsc_dpcd
);
4043 /* FEC is supported only on DP 1.4 */
4044 if (!intel_dp_is_edp(intel_dp
) &&
4045 drm_dp_dpcd_readb(&intel_dp
->aux
, DP_FEC_CAPABILITY
,
4046 &intel_dp
->fec_capable
) < 0)
4047 DRM_ERROR("Failed to read FEC DPCD register\n");
4049 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp
->fec_capable
);
4054 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
4056 struct drm_i915_private
*dev_priv
=
4057 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
4059 /* this function is meant to be called only once */
4060 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
4062 if (!intel_dp_read_dpcd(intel_dp
))
4065 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
4066 drm_dp_is_branch(intel_dp
->dpcd
));
4068 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4069 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4070 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4073 * Read the eDP display control registers.
4075 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4076 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4077 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4078 * method). The display control registers should read zero if they're
4079 * not supported anyway.
4081 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
4082 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
4083 sizeof(intel_dp
->edp_dpcd
))
4084 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
4085 intel_dp
->edp_dpcd
);
4088 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4089 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4091 intel_psr_init_dpcd(intel_dp
);
4093 /* Read the eDP 1.4+ supported link rates. */
4094 if (intel_dp
->edp_dpcd
[0] >= DP_EDP_14
) {
4095 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
4098 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
4099 sink_rates
, sizeof(sink_rates
));
4101 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
4102 int val
= le16_to_cpu(sink_rates
[i
]);
4107 /* Value read multiplied by 200kHz gives the per-lane
4108 * link rate in kHz. The source rates are, however,
4109 * stored in terms of LS_Clk kHz. The full conversion
4110 * back to symbols is
4111 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4113 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
4115 intel_dp
->num_sink_rates
= i
;
4119 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4120 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4122 if (intel_dp
->num_sink_rates
)
4123 intel_dp
->use_rate_select
= true;
4125 intel_dp_set_sink_rates(intel_dp
);
4127 intel_dp_set_common_rates(intel_dp
);
4129 /* Read the eDP DSC DPCD registers */
4130 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
4131 intel_dp_get_dsc_sink_cap(intel_dp
);
4138 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
4140 if (!intel_dp_read_dpcd(intel_dp
))
4143 /* Don't clobber cached eDP rates. */
4144 if (!intel_dp_is_edp(intel_dp
)) {
4145 intel_dp_set_sink_rates(intel_dp
);
4146 intel_dp_set_common_rates(intel_dp
);
4150 * Some eDP panels do not set a valid value for sink count, that is why
4151 * it don't care about read it here and in intel_edp_init_dpcd().
4153 if (!intel_dp_is_edp(intel_dp
)) {
4157 r
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_SINK_COUNT
, &count
);
4162 * Sink count can change between short pulse hpd hence
4163 * a member variable in intel_dp will track any changes
4164 * between short pulse interrupts.
4166 intel_dp
->sink_count
= DP_GET_SINK_COUNT(count
);
4169 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4170 * a dongle is present but no display. Unless we require to know
4171 * if a dongle is present or not, we don't need to update
4172 * downstream port information. So, an early return here saves
4173 * time from performing other operations which are not required.
4175 if (!intel_dp
->sink_count
)
4179 if (!drm_dp_is_branch(intel_dp
->dpcd
))
4180 return true; /* native DP sink */
4182 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
4183 return true; /* no per-port downstream info */
4185 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
4186 intel_dp
->downstream_ports
,
4187 DP_MAX_DOWNSTREAM_PORTS
) < 0)
4188 return false; /* downstream port status fetch failed */
4194 intel_dp_sink_can_mst(struct intel_dp
*intel_dp
)
4198 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
4201 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_MSTM_CAP
, &mstm_cap
) != 1)
4204 return mstm_cap
& DP_MST_CAP
;
4208 intel_dp_can_mst(struct intel_dp
*intel_dp
)
4210 return i915_modparams
.enable_dp_mst
&&
4211 intel_dp
->can_mst
&&
4212 intel_dp_sink_can_mst(intel_dp
);
4216 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
4218 struct intel_encoder
*encoder
=
4219 &dp_to_dig_port(intel_dp
)->base
;
4220 bool sink_can_mst
= intel_dp_sink_can_mst(intel_dp
);
4222 DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4223 port_name(encoder
->port
), yesno(intel_dp
->can_mst
),
4224 yesno(sink_can_mst
), yesno(i915_modparams
.enable_dp_mst
));
4226 if (!intel_dp
->can_mst
)
4229 intel_dp
->is_mst
= sink_can_mst
&&
4230 i915_modparams
.enable_dp_mst
;
4232 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4237 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4239 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT_ESI
,
4240 sink_irq_vector
, DP_DPRX_ESI_LEN
) ==
4244 u16
intel_dp_dsc_get_output_bpp(int link_clock
, u8 lane_count
,
4245 int mode_clock
, int mode_hdisplay
)
4247 u16 bits_per_pixel
, max_bpp_small_joiner_ram
;
4251 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4252 * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4253 * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4254 * for MST -> TimeSlotsPerMTP has to be calculated
4256 bits_per_pixel
= (link_clock
* lane_count
* 8 *
4257 DP_DSC_FEC_OVERHEAD_FACTOR
) /
4260 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4261 max_bpp_small_joiner_ram
= DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER
/
4265 * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4266 * check, output bpp from small joiner RAM check)
4268 bits_per_pixel
= min(bits_per_pixel
, max_bpp_small_joiner_ram
);
4270 /* Error out if the max bpp is less than smallest allowed valid bpp */
4271 if (bits_per_pixel
< valid_dsc_bpp
[0]) {
4272 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel
);
4276 /* Find the nearest match in the array of known BPPs from VESA */
4277 for (i
= 0; i
< ARRAY_SIZE(valid_dsc_bpp
) - 1; i
++) {
4278 if (bits_per_pixel
< valid_dsc_bpp
[i
+ 1])
4281 bits_per_pixel
= valid_dsc_bpp
[i
];
4284 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4285 * fractional part is 0
4287 return bits_per_pixel
<< 4;
4290 u8
intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp
,
4294 u8 min_slice_count
, i
;
4295 int max_slice_width
;
4297 if (mode_clock
<= DP_DSC_PEAK_PIXEL_RATE
)
4298 min_slice_count
= DIV_ROUND_UP(mode_clock
,
4299 DP_DSC_MAX_ENC_THROUGHPUT_0
);
4301 min_slice_count
= DIV_ROUND_UP(mode_clock
,
4302 DP_DSC_MAX_ENC_THROUGHPUT_1
);
4304 max_slice_width
= drm_dp_dsc_sink_max_slice_width(intel_dp
->dsc_dpcd
);
4305 if (max_slice_width
< DP_DSC_MIN_SLICE_WIDTH_VALUE
) {
4306 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4310 /* Also take into account max slice width */
4311 min_slice_count
= min_t(u8
, min_slice_count
,
4312 DIV_ROUND_UP(mode_hdisplay
,
4315 /* Find the closest match to the valid slice count values */
4316 for (i
= 0; i
< ARRAY_SIZE(valid_dsc_slicecount
); i
++) {
4317 if (valid_dsc_slicecount
[i
] >
4318 drm_dp_dsc_sink_max_slice_count(intel_dp
->dsc_dpcd
,
4321 if (min_slice_count
<= valid_dsc_slicecount
[i
])
4322 return valid_dsc_slicecount
[i
];
4325 DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count
);
4329 static u8
intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4333 u8 test_lane_count
, test_link_bw
;
4337 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4338 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
4342 DRM_DEBUG_KMS("Lane count read failed\n");
4345 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
4347 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
4350 DRM_DEBUG_KMS("Link Rate read failed\n");
4353 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
4355 /* Validate the requested link rate and lane count */
4356 if (!intel_dp_link_params_valid(intel_dp
, test_link_rate
,
4360 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
4361 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4366 static u8
intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4370 __be16 h_width
, v_height
;
4373 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4374 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_PATTERN
,
4377 DRM_DEBUG_KMS("Test pattern read failed\n");
4380 if (test_pattern
!= DP_COLOR_RAMP
)
4383 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4386 DRM_DEBUG_KMS("H Width read failed\n");
4390 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4393 DRM_DEBUG_KMS("V Height read failed\n");
4397 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_MISC0
,
4400 DRM_DEBUG_KMS("TEST MISC read failed\n");
4403 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4405 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4407 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4408 case DP_TEST_BIT_DEPTH_6
:
4409 intel_dp
->compliance
.test_data
.bpc
= 6;
4411 case DP_TEST_BIT_DEPTH_8
:
4412 intel_dp
->compliance
.test_data
.bpc
= 8;
4418 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4419 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4420 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4421 /* Set test active flag here so userspace doesn't interrupt things */
4422 intel_dp
->compliance
.test_active
= 1;
4427 static u8
intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4429 u8 test_result
= DP_TEST_ACK
;
4430 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4431 struct drm_connector
*connector
= &intel_connector
->base
;
4433 if (intel_connector
->detect_edid
== NULL
||
4434 connector
->edid_corrupt
||
4435 intel_dp
->aux
.i2c_defer_count
> 6) {
4436 /* Check EDID read for NACKs, DEFERs and corruption
4437 * (DP CTS 1.2 Core r1.1)
4438 * 4.2.2.4 : Failed EDID read, I2C_NAK
4439 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4440 * 4.2.2.6 : EDID corruption detected
4441 * Use failsafe mode for all cases
4443 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4444 intel_dp
->aux
.i2c_defer_count
> 0)
4445 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4446 intel_dp
->aux
.i2c_nack_count
,
4447 intel_dp
->aux
.i2c_defer_count
);
4448 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4450 struct edid
*block
= intel_connector
->detect_edid
;
4452 /* We have to write the checksum
4453 * of the last block read
4455 block
+= intel_connector
->detect_edid
->extensions
;
4457 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_EDID_CHECKSUM
,
4458 block
->checksum
) <= 0)
4459 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4461 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4462 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4465 /* Set test active flag here so userspace doesn't interrupt things */
4466 intel_dp
->compliance
.test_active
= 1;
4471 static u8
intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4473 u8 test_result
= DP_TEST_NAK
;
4477 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4479 u8 response
= DP_TEST_NAK
;
4483 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4485 DRM_DEBUG_KMS("Could not read test request from sink\n");
4490 case DP_TEST_LINK_TRAINING
:
4491 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4492 response
= intel_dp_autotest_link_training(intel_dp
);
4494 case DP_TEST_LINK_VIDEO_PATTERN
:
4495 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4496 response
= intel_dp_autotest_video_pattern(intel_dp
);
4498 case DP_TEST_LINK_EDID_READ
:
4499 DRM_DEBUG_KMS("EDID test requested\n");
4500 response
= intel_dp_autotest_edid(intel_dp
);
4502 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4503 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4504 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4507 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4511 if (response
& DP_TEST_ACK
)
4512 intel_dp
->compliance
.test_type
= request
;
4515 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4517 DRM_DEBUG_KMS("Could not write test response to sink\n");
4521 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4525 if (intel_dp
->is_mst
) {
4526 u8 esi
[DP_DPRX_ESI_LEN
] = { 0 };
4531 WARN_ON_ONCE(intel_dp
->active_mst_links
< 0);
4532 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4536 /* check link status - esi[10] = 0x200c */
4537 if (intel_dp
->active_mst_links
> 0 &&
4538 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4539 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4540 intel_dp_start_link_train(intel_dp
);
4541 intel_dp_stop_link_train(intel_dp
);
4544 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4545 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4548 for (retry
= 0; retry
< 3; retry
++) {
4550 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4551 DP_SINK_COUNT_ESI
+1,
4558 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4560 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4568 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4569 intel_dp
->is_mst
= false;
4570 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4578 intel_dp_needs_link_retrain(struct intel_dp
*intel_dp
)
4580 u8 link_status
[DP_LINK_STATUS_SIZE
];
4582 if (!intel_dp
->link_trained
)
4586 * While PSR source HW is enabled, it will control main-link sending
4587 * frames, enabling and disabling it so trying to do a retrain will fail
4588 * as the link would or not be on or it could mix training patterns
4589 * and frame data at the same time causing retrain to fail.
4590 * Also when exiting PSR, HW will retrain the link anyways fixing
4591 * any link status error.
4593 if (intel_psr_enabled(intel_dp
))
4596 if (!intel_dp_get_link_status(intel_dp
, link_status
))
4600 * Validate the cached values of intel_dp->link_rate and
4601 * intel_dp->lane_count before attempting to retrain.
4603 if (!intel_dp_link_params_valid(intel_dp
, intel_dp
->link_rate
,
4604 intel_dp
->lane_count
))
4607 /* Retrain if Channel EQ or CR not ok */
4608 return !drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
);
4611 int intel_dp_retrain_link(struct intel_encoder
*encoder
,
4612 struct drm_modeset_acquire_ctx
*ctx
)
4614 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4615 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
4616 struct intel_connector
*connector
= intel_dp
->attached_connector
;
4617 struct drm_connector_state
*conn_state
;
4618 struct intel_crtc_state
*crtc_state
;
4619 struct intel_crtc
*crtc
;
4622 /* FIXME handle the MST connectors as well */
4624 if (!connector
|| connector
->base
.status
!= connector_status_connected
)
4627 ret
= drm_modeset_lock(&dev_priv
->drm
.mode_config
.connection_mutex
,
4632 conn_state
= connector
->base
.state
;
4634 crtc
= to_intel_crtc(conn_state
->crtc
);
4638 ret
= drm_modeset_lock(&crtc
->base
.mutex
, ctx
);
4642 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
4644 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state
));
4646 if (!crtc_state
->base
.active
)
4649 if (conn_state
->commit
&&
4650 !try_wait_for_completion(&conn_state
->commit
->hw_done
))
4653 if (!intel_dp_needs_link_retrain(intel_dp
))
4656 /* Suppress underruns caused by re-training */
4657 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4658 if (crtc_state
->has_pch_encoder
)
4659 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4660 intel_crtc_pch_transcoder(crtc
), false);
4662 intel_dp_start_link_train(intel_dp
);
4663 intel_dp_stop_link_train(intel_dp
);
4665 /* Keep underrun reporting disabled until things are stable */
4666 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4668 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4669 if (crtc_state
->has_pch_encoder
)
4670 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4671 intel_crtc_pch_transcoder(crtc
), true);
4677 * If display is now connected check links status,
4678 * there has been known issues of link loss triggering
4681 * Some sinks (eg. ASUS PB287Q) seem to perform some
4682 * weird HPD ping pong during modesets. So we can apparently
4683 * end up with HPD going low during a modeset, and then
4684 * going back up soon after. And once that happens we must
4685 * retrain the link to get a picture. That's in case no
4686 * userspace component reacted to intermittent HPD dip.
4688 static bool intel_dp_hotplug(struct intel_encoder
*encoder
,
4689 struct intel_connector
*connector
)
4691 struct drm_modeset_acquire_ctx ctx
;
4695 changed
= intel_encoder_hotplug(encoder
, connector
);
4697 drm_modeset_acquire_init(&ctx
, 0);
4700 ret
= intel_dp_retrain_link(encoder
, &ctx
);
4702 if (ret
== -EDEADLK
) {
4703 drm_modeset_backoff(&ctx
);
4710 drm_modeset_drop_locks(&ctx
);
4711 drm_modeset_acquire_fini(&ctx
);
4712 WARN(ret
, "Acquiring modeset locks failed with %i\n", ret
);
4717 static void intel_dp_check_service_irq(struct intel_dp
*intel_dp
)
4721 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
4724 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4725 DP_DEVICE_SERVICE_IRQ_VECTOR
, &val
) != 1 || !val
)
4728 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
, val
);
4730 if (val
& DP_AUTOMATED_TEST_REQUEST
)
4731 intel_dp_handle_test_request(intel_dp
);
4733 if (val
& DP_CP_IRQ
)
4734 intel_hdcp_check_link(intel_dp
->attached_connector
);
4736 if (val
& DP_SINK_SPECIFIC_IRQ
)
4737 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4741 * According to DP spec
4744 * 2. Configure link according to Receiver Capabilities
4745 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4746 * 4. Check link status on receipt of hot-plug interrupt
4748 * intel_dp_short_pulse - handles short pulse interrupts
4749 * when full detection is not required.
4750 * Returns %true if short pulse is handled and full detection
4751 * is NOT required and %false otherwise.
4754 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4756 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
4757 u8 old_sink_count
= intel_dp
->sink_count
;
4761 * Clearing compliance test variables to allow capturing
4762 * of values for next automated test request.
4764 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4767 * Now read the DPCD to see if it's actually running
4768 * If the current value of sink count doesn't match with
4769 * the value that was stored earlier or dpcd read failed
4770 * we need to do full detection
4772 ret
= intel_dp_get_dpcd(intel_dp
);
4774 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4775 /* No need to proceed if we are going to do full detect */
4779 intel_dp_check_service_irq(intel_dp
);
4781 /* Handle CEC interrupts, if any */
4782 drm_dp_cec_irq(&intel_dp
->aux
);
4784 /* defer to the hotplug work for link retraining if needed */
4785 if (intel_dp_needs_link_retrain(intel_dp
))
4788 intel_psr_short_pulse(intel_dp
);
4790 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4791 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4792 /* Send a Hotplug Uevent to userspace to start modeset */
4793 drm_kms_helper_hotplug_event(&dev_priv
->drm
);
4799 /* XXX this is probably wrong for multiple downstream ports */
4800 static enum drm_connector_status
4801 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4803 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4804 u8
*dpcd
= intel_dp
->dpcd
;
4808 lspcon_resume(lspcon
);
4810 if (!intel_dp_get_dpcd(intel_dp
))
4811 return connector_status_disconnected
;
4813 if (intel_dp_is_edp(intel_dp
))
4814 return connector_status_connected
;
4816 /* if there's no downstream port, we're done */
4817 if (!drm_dp_is_branch(dpcd
))
4818 return connector_status_connected
;
4820 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4821 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4822 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4824 return intel_dp
->sink_count
?
4825 connector_status_connected
: connector_status_disconnected
;
4828 if (intel_dp_can_mst(intel_dp
))
4829 return connector_status_connected
;
4831 /* If no HPD, poke DDC gently */
4832 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4833 return connector_status_connected
;
4835 /* Well we tried, say unknown for unreliable port types */
4836 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4837 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4838 if (type
== DP_DS_PORT_TYPE_VGA
||
4839 type
== DP_DS_PORT_TYPE_NON_EDID
)
4840 return connector_status_unknown
;
4842 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4843 DP_DWN_STRM_PORT_TYPE_MASK
;
4844 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4845 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4846 return connector_status_unknown
;
4849 /* Anything else is out of spec, warn and ignore */
4850 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4851 return connector_status_disconnected
;
4854 static enum drm_connector_status
4855 edp_detect(struct intel_dp
*intel_dp
)
4857 return connector_status_connected
;
4860 static bool ibx_digital_port_connected(struct intel_encoder
*encoder
)
4862 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4865 switch (encoder
->hpd_pin
) {
4867 bit
= SDE_PORTB_HOTPLUG
;
4870 bit
= SDE_PORTC_HOTPLUG
;
4873 bit
= SDE_PORTD_HOTPLUG
;
4876 MISSING_CASE(encoder
->hpd_pin
);
4880 return I915_READ(SDEISR
) & bit
;
4883 static bool cpt_digital_port_connected(struct intel_encoder
*encoder
)
4885 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4888 switch (encoder
->hpd_pin
) {
4890 bit
= SDE_PORTB_HOTPLUG_CPT
;
4893 bit
= SDE_PORTC_HOTPLUG_CPT
;
4896 bit
= SDE_PORTD_HOTPLUG_CPT
;
4899 MISSING_CASE(encoder
->hpd_pin
);
4903 return I915_READ(SDEISR
) & bit
;
4906 static bool spt_digital_port_connected(struct intel_encoder
*encoder
)
4908 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4911 switch (encoder
->hpd_pin
) {
4913 bit
= SDE_PORTA_HOTPLUG_SPT
;
4916 bit
= SDE_PORTE_HOTPLUG_SPT
;
4919 return cpt_digital_port_connected(encoder
);
4922 return I915_READ(SDEISR
) & bit
;
4925 static bool g4x_digital_port_connected(struct intel_encoder
*encoder
)
4927 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4930 switch (encoder
->hpd_pin
) {
4932 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4935 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4938 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4941 MISSING_CASE(encoder
->hpd_pin
);
4945 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4948 static bool gm45_digital_port_connected(struct intel_encoder
*encoder
)
4950 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4953 switch (encoder
->hpd_pin
) {
4955 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4958 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4961 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4964 MISSING_CASE(encoder
->hpd_pin
);
4968 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4971 static bool ilk_digital_port_connected(struct intel_encoder
*encoder
)
4973 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4975 if (encoder
->hpd_pin
== HPD_PORT_A
)
4976 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4978 return ibx_digital_port_connected(encoder
);
4981 static bool snb_digital_port_connected(struct intel_encoder
*encoder
)
4983 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4985 if (encoder
->hpd_pin
== HPD_PORT_A
)
4986 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4988 return cpt_digital_port_connected(encoder
);
4991 static bool ivb_digital_port_connected(struct intel_encoder
*encoder
)
4993 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4995 if (encoder
->hpd_pin
== HPD_PORT_A
)
4996 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG_IVB
;
4998 return cpt_digital_port_connected(encoder
);
5001 static bool bdw_digital_port_connected(struct intel_encoder
*encoder
)
5003 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5005 if (encoder
->hpd_pin
== HPD_PORT_A
)
5006 return I915_READ(GEN8_DE_PORT_ISR
) & GEN8_PORT_DP_A_HOTPLUG
;
5008 return cpt_digital_port_connected(encoder
);
5011 static bool bxt_digital_port_connected(struct intel_encoder
*encoder
)
5013 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5016 switch (encoder
->hpd_pin
) {
5018 bit
= BXT_DE_PORT_HP_DDIA
;
5021 bit
= BXT_DE_PORT_HP_DDIB
;
5024 bit
= BXT_DE_PORT_HP_DDIC
;
5027 MISSING_CASE(encoder
->hpd_pin
);
5031 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
5034 static bool icl_combo_port_connected(struct drm_i915_private
*dev_priv
,
5035 struct intel_digital_port
*intel_dig_port
)
5037 enum port port
= intel_dig_port
->base
.port
;
5039 return I915_READ(SDEISR
) & SDE_DDI_HOTPLUG_ICP(port
);
5042 static const char *tc_type_name(enum tc_port_type type
)
5044 static const char * const names
[] = {
5045 [TC_PORT_UNKNOWN
] = "unknown",
5046 [TC_PORT_LEGACY
] = "legacy",
5047 [TC_PORT_TYPEC
] = "typec",
5048 [TC_PORT_TBT
] = "tbt",
5051 if (WARN_ON(type
>= ARRAY_SIZE(names
)))
5052 type
= TC_PORT_UNKNOWN
;
5057 static void icl_update_tc_port_type(struct drm_i915_private
*dev_priv
,
5058 struct intel_digital_port
*intel_dig_port
,
5059 bool is_legacy
, bool is_typec
, bool is_tbt
)
5061 enum port port
= intel_dig_port
->base
.port
;
5062 enum tc_port_type old_type
= intel_dig_port
->tc_type
;
5064 WARN_ON(is_legacy
+ is_typec
+ is_tbt
!= 1);
5067 intel_dig_port
->tc_type
= TC_PORT_LEGACY
;
5069 intel_dig_port
->tc_type
= TC_PORT_TYPEC
;
5071 intel_dig_port
->tc_type
= TC_PORT_TBT
;
5075 /* Types are not supposed to be changed at runtime. */
5076 WARN_ON(old_type
!= TC_PORT_UNKNOWN
&&
5077 old_type
!= intel_dig_port
->tc_type
);
5079 if (old_type
!= intel_dig_port
->tc_type
)
5080 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port
),
5081 tc_type_name(intel_dig_port
->tc_type
));
5085 * This function implements the first part of the Connect Flow described by our
5086 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5087 * lanes, EDID, etc) is done as needed in the typical places.
5089 * Unlike the other ports, type-C ports are not available to use as soon as we
5090 * get a hotplug. The type-C PHYs can be shared between multiple controllers:
5091 * display, USB, etc. As a result, handshaking through FIA is required around
5092 * connect and disconnect to cleanly transfer ownership with the controller and
5093 * set the type-C power state.
5095 * We could opt to only do the connect flow when we actually try to use the AUX
5096 * channels or do a modeset, then immediately run the disconnect flow after
5097 * usage, but there are some implications on this for a dynamic environment:
5098 * things may go away or change behind our backs. So for now our driver is
5099 * always trying to acquire ownership of the controller as soon as it gets an
5100 * interrupt (or polls state and sees a port is connected) and only gives it
5101 * back when it sees a disconnect. Implementation of a more fine-grained model
5102 * will require a lot of coordination with user space and thorough testing for
5103 * the extra possible cases.
5105 static bool icl_tc_phy_connect(struct drm_i915_private
*dev_priv
,
5106 struct intel_digital_port
*dig_port
)
5108 enum tc_port tc_port
= intel_port_to_tc(dev_priv
, dig_port
->base
.port
);
5111 if (dig_port
->tc_type
!= TC_PORT_LEGACY
&&
5112 dig_port
->tc_type
!= TC_PORT_TYPEC
)
5115 val
= I915_READ(PORT_TX_DFLEXDPPMS
);
5116 if (!(val
& DP_PHY_MODE_STATUS_COMPLETED(tc_port
))) {
5117 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port
);
5118 WARN_ON(dig_port
->tc_legacy_port
);
5123 * This function may be called many times in a row without an HPD event
5124 * in between, so try to avoid the write when we can.
5126 val
= I915_READ(PORT_TX_DFLEXDPCSSS
);
5127 if (!(val
& DP_PHY_MODE_STATUS_NOT_SAFE(tc_port
))) {
5128 val
|= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port
);
5129 I915_WRITE(PORT_TX_DFLEXDPCSSS
, val
);
5133 * Now we have to re-check the live state, in case the port recently
5134 * became disconnected. Not necessary for legacy mode.
5136 if (dig_port
->tc_type
== TC_PORT_TYPEC
&&
5137 !(I915_READ(PORT_TX_DFLEXDPSP
) & TC_LIVE_STATE_TC(tc_port
))) {
5138 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port
);
5139 icl_tc_phy_disconnect(dev_priv
, dig_port
);
5147 * See the comment at the connect function. This implements the Disconnect
5150 void icl_tc_phy_disconnect(struct drm_i915_private
*dev_priv
,
5151 struct intel_digital_port
*dig_port
)
5153 enum tc_port tc_port
= intel_port_to_tc(dev_priv
, dig_port
->base
.port
);
5155 if (dig_port
->tc_type
== TC_PORT_UNKNOWN
)
5159 * TBT disconnection flow is read the live status, what was done in
5162 if (dig_port
->tc_type
== TC_PORT_TYPEC
||
5163 dig_port
->tc_type
== TC_PORT_LEGACY
) {
5166 val
= I915_READ(PORT_TX_DFLEXDPCSSS
);
5167 val
&= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port
);
5168 I915_WRITE(PORT_TX_DFLEXDPCSSS
, val
);
5171 DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
5172 port_name(dig_port
->base
.port
),
5173 tc_type_name(dig_port
->tc_type
));
5175 dig_port
->tc_type
= TC_PORT_UNKNOWN
;
5179 * The type-C ports are different because even when they are connected, they may
5180 * not be available/usable by the graphics driver: see the comment on
5181 * icl_tc_phy_connect(). So in our driver instead of adding the additional
5182 * concept of "usable" and make everything check for "connected and usable" we
5183 * define a port as "connected" when it is not only connected, but also when it
5184 * is usable by the rest of the driver. That maintains the old assumption that
5185 * connected ports are usable, and avoids exposing to the users objects they
5188 static bool icl_tc_port_connected(struct drm_i915_private
*dev_priv
,
5189 struct intel_digital_port
*intel_dig_port
)
5191 enum port port
= intel_dig_port
->base
.port
;
5192 enum tc_port tc_port
= intel_port_to_tc(dev_priv
, port
);
5193 bool is_legacy
, is_typec
, is_tbt
;
5197 * WARN if we got a legacy port HPD, but VBT didn't mark the port as
5198 * legacy. Treat the port as legacy from now on.
5200 if (WARN_ON(!intel_dig_port
->tc_legacy_port
&&
5201 I915_READ(SDEISR
) & SDE_TC_HOTPLUG_ICP(tc_port
)))
5202 intel_dig_port
->tc_legacy_port
= true;
5203 is_legacy
= intel_dig_port
->tc_legacy_port
;
5206 * The spec says we shouldn't be using the ISR bits for detecting
5207 * between TC and TBT. We should use DFLEXDPSP.
5209 dpsp
= I915_READ(PORT_TX_DFLEXDPSP
);
5210 is_typec
= dpsp
& TC_LIVE_STATE_TC(tc_port
);
5211 is_tbt
= dpsp
& TC_LIVE_STATE_TBT(tc_port
);
5213 if (!is_legacy
&& !is_typec
&& !is_tbt
) {
5214 icl_tc_phy_disconnect(dev_priv
, intel_dig_port
);
5219 icl_update_tc_port_type(dev_priv
, intel_dig_port
, is_legacy
, is_typec
,
5222 if (!icl_tc_phy_connect(dev_priv
, intel_dig_port
))
5228 static bool icl_digital_port_connected(struct intel_encoder
*encoder
)
5230 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5231 struct intel_digital_port
*dig_port
= enc_to_dig_port(&encoder
->base
);
5233 if (intel_port_is_combophy(dev_priv
, encoder
->port
))
5234 return icl_combo_port_connected(dev_priv
, dig_port
);
5235 else if (intel_port_is_tc(dev_priv
, encoder
->port
))
5236 return icl_tc_port_connected(dev_priv
, dig_port
);
5238 MISSING_CASE(encoder
->hpd_pin
);
5244 * intel_digital_port_connected - is the specified port connected?
5245 * @encoder: intel_encoder
5247 * In cases where there's a connector physically connected but it can't be used
5248 * by our hardware we also return false, since the rest of the driver should
5249 * pretty much treat the port as disconnected. This is relevant for type-C
5250 * (starting on ICL) where there's ownership involved.
5252 * Return %true if port is connected, %false otherwise.
5254 bool intel_digital_port_connected(struct intel_encoder
*encoder
)
5256 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5258 if (HAS_GMCH(dev_priv
)) {
5259 if (IS_GM45(dev_priv
))
5260 return gm45_digital_port_connected(encoder
);
5262 return g4x_digital_port_connected(encoder
);
5265 if (INTEL_GEN(dev_priv
) >= 11)
5266 return icl_digital_port_connected(encoder
);
5267 else if (IS_GEN(dev_priv
, 10) || IS_GEN9_BC(dev_priv
))
5268 return spt_digital_port_connected(encoder
);
5269 else if (IS_GEN9_LP(dev_priv
))
5270 return bxt_digital_port_connected(encoder
);
5271 else if (IS_GEN(dev_priv
, 8))
5272 return bdw_digital_port_connected(encoder
);
5273 else if (IS_GEN(dev_priv
, 7))
5274 return ivb_digital_port_connected(encoder
);
5275 else if (IS_GEN(dev_priv
, 6))
5276 return snb_digital_port_connected(encoder
);
5277 else if (IS_GEN(dev_priv
, 5))
5278 return ilk_digital_port_connected(encoder
);
5280 MISSING_CASE(INTEL_GEN(dev_priv
));
5284 static struct edid
*
5285 intel_dp_get_edid(struct intel_dp
*intel_dp
)
5287 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
5289 /* use cached edid if we have one */
5290 if (intel_connector
->edid
) {
5292 if (IS_ERR(intel_connector
->edid
))
5295 return drm_edid_duplicate(intel_connector
->edid
);
5297 return drm_get_edid(&intel_connector
->base
,
5298 &intel_dp
->aux
.ddc
);
5302 intel_dp_set_edid(struct intel_dp
*intel_dp
)
5304 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
5307 intel_dp_unset_edid(intel_dp
);
5308 edid
= intel_dp_get_edid(intel_dp
);
5309 intel_connector
->detect_edid
= edid
;
5311 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
5312 drm_dp_cec_set_edid(&intel_dp
->aux
, edid
);
5316 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
5318 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
5320 drm_dp_cec_unset_edid(&intel_dp
->aux
);
5321 kfree(intel_connector
->detect_edid
);
5322 intel_connector
->detect_edid
= NULL
;
5324 intel_dp
->has_audio
= false;
5328 intel_dp_detect(struct drm_connector
*connector
,
5329 struct drm_modeset_acquire_ctx
*ctx
,
5332 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5333 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5334 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5335 struct intel_encoder
*encoder
= &dig_port
->base
;
5336 enum drm_connector_status status
;
5337 enum intel_display_power_domain aux_domain
=
5338 intel_aux_power_domain(dig_port
);
5339 intel_wakeref_t wakeref
;
5341 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5342 connector
->base
.id
, connector
->name
);
5343 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
5345 wakeref
= intel_display_power_get(dev_priv
, aux_domain
);
5347 /* Can't disconnect eDP */
5348 if (intel_dp_is_edp(intel_dp
))
5349 status
= edp_detect(intel_dp
);
5350 else if (intel_digital_port_connected(encoder
))
5351 status
= intel_dp_detect_dpcd(intel_dp
);
5353 status
= connector_status_disconnected
;
5355 if (status
== connector_status_disconnected
) {
5356 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
5357 memset(intel_dp
->dsc_dpcd
, 0, sizeof(intel_dp
->dsc_dpcd
));
5359 if (intel_dp
->is_mst
) {
5360 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5362 intel_dp
->mst_mgr
.mst_state
);
5363 intel_dp
->is_mst
= false;
5364 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5371 if (intel_dp
->reset_link_params
) {
5372 /* Initial max link lane count */
5373 intel_dp
->max_link_lane_count
= intel_dp_max_common_lane_count(intel_dp
);
5375 /* Initial max link rate */
5376 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
5378 intel_dp
->reset_link_params
= false;
5381 intel_dp_print_rates(intel_dp
);
5383 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5384 if (INTEL_GEN(dev_priv
) >= 11)
5385 intel_dp_get_dsc_sink_cap(intel_dp
);
5387 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
5388 drm_dp_is_branch(intel_dp
->dpcd
));
5390 intel_dp_configure_mst(intel_dp
);
5392 if (intel_dp
->is_mst
) {
5394 * If we are in MST mode then this connector
5395 * won't appear connected or have anything
5398 status
= connector_status_disconnected
;
5403 * Some external monitors do not signal loss of link synchronization
5404 * with an IRQ_HPD, so force a link status check.
5406 if (!intel_dp_is_edp(intel_dp
)) {
5409 ret
= intel_dp_retrain_link(encoder
, ctx
);
5411 intel_display_power_put(dev_priv
, aux_domain
, wakeref
);
5417 * Clearing NACK and defer counts to get their exact values
5418 * while reading EDID which are required by Compliance tests
5419 * 4.2.2.4 and 4.2.2.5
5421 intel_dp
->aux
.i2c_nack_count
= 0;
5422 intel_dp
->aux
.i2c_defer_count
= 0;
5424 intel_dp_set_edid(intel_dp
);
5425 if (intel_dp_is_edp(intel_dp
) ||
5426 to_intel_connector(connector
)->detect_edid
)
5427 status
= connector_status_connected
;
5429 intel_dp_check_service_irq(intel_dp
);
5432 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
5433 intel_dp_unset_edid(intel_dp
);
5435 intel_display_power_put(dev_priv
, aux_domain
, wakeref
);
5440 intel_dp_force(struct drm_connector
*connector
)
5442 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5443 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5444 struct intel_encoder
*intel_encoder
= &dig_port
->base
;
5445 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
5446 enum intel_display_power_domain aux_domain
=
5447 intel_aux_power_domain(dig_port
);
5448 intel_wakeref_t wakeref
;
5450 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5451 connector
->base
.id
, connector
->name
);
5452 intel_dp_unset_edid(intel_dp
);
5454 if (connector
->status
!= connector_status_connected
)
5457 wakeref
= intel_display_power_get(dev_priv
, aux_domain
);
5459 intel_dp_set_edid(intel_dp
);
5461 intel_display_power_put(dev_priv
, aux_domain
, wakeref
);
5464 static int intel_dp_get_modes(struct drm_connector
*connector
)
5466 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5469 edid
= intel_connector
->detect_edid
;
5471 int ret
= intel_connector_update_modes(connector
, edid
);
5476 /* if eDP has no EDID, fall back to fixed mode */
5477 if (intel_dp_is_edp(intel_attached_dp(connector
)) &&
5478 intel_connector
->panel
.fixed_mode
) {
5479 struct drm_display_mode
*mode
;
5481 mode
= drm_mode_duplicate(connector
->dev
,
5482 intel_connector
->panel
.fixed_mode
);
5484 drm_mode_probed_add(connector
, mode
);
5493 intel_dp_connector_register(struct drm_connector
*connector
)
5495 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5496 struct drm_device
*dev
= connector
->dev
;
5499 ret
= intel_connector_register(connector
);
5503 i915_debugfs_connector_add(connector
);
5505 DRM_DEBUG_KMS("registering %s bus for %s\n",
5506 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
5508 intel_dp
->aux
.dev
= connector
->kdev
;
5509 ret
= drm_dp_aux_register(&intel_dp
->aux
);
5511 drm_dp_cec_register_connector(&intel_dp
->aux
,
5512 connector
->name
, dev
->dev
);
5517 intel_dp_connector_unregister(struct drm_connector
*connector
)
5519 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5521 drm_dp_cec_unregister_connector(&intel_dp
->aux
);
5522 drm_dp_aux_unregister(&intel_dp
->aux
);
5523 intel_connector_unregister(connector
);
5526 void intel_dp_encoder_flush_work(struct drm_encoder
*encoder
)
5528 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
5529 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5531 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5532 if (intel_dp_is_edp(intel_dp
)) {
5533 intel_wakeref_t wakeref
;
5535 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5537 * vdd might still be enabled do to the delayed vdd off.
5538 * Make sure vdd is actually turned off here.
5540 with_pps_lock(intel_dp
, wakeref
)
5541 edp_panel_vdd_off_sync(intel_dp
);
5543 if (intel_dp
->edp_notifier
.notifier_call
) {
5544 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
5545 intel_dp
->edp_notifier
.notifier_call
= NULL
;
5549 intel_dp_aux_fini(intel_dp
);
5552 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
5554 intel_dp_encoder_flush_work(encoder
);
5556 drm_encoder_cleanup(encoder
);
5557 kfree(enc_to_dig_port(encoder
));
5560 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
5562 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5563 intel_wakeref_t wakeref
;
5565 if (!intel_dp_is_edp(intel_dp
))
5569 * vdd might still be enabled do to the delayed vdd off.
5570 * Make sure vdd is actually turned off here.
5572 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5573 with_pps_lock(intel_dp
, wakeref
)
5574 edp_panel_vdd_off_sync(intel_dp
);
5578 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port
*intel_dig_port
,
5581 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_dig_port
->base
.base
);
5582 static const struct drm_dp_aux_msg msg
= {
5583 .request
= DP_AUX_NATIVE_WRITE
,
5584 .address
= DP_AUX_HDCP_AKSV
,
5585 .size
= DRM_HDCP_KSV_LEN
,
5587 u8 txbuf
[HEADER_SIZE
+ DRM_HDCP_KSV_LEN
] = {}, rxbuf
[2], reply
= 0;
5591 /* Output An first, that's easy */
5592 dpcd_ret
= drm_dp_dpcd_write(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_AN
,
5593 an
, DRM_HDCP_AN_LEN
);
5594 if (dpcd_ret
!= DRM_HDCP_AN_LEN
) {
5595 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5597 return dpcd_ret
>= 0 ? -EIO
: dpcd_ret
;
5601 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5602 * order to get it on the wire, we need to create the AUX header as if
5603 * we were writing the data, and then tickle the hardware to output the
5604 * data once the header is sent out.
5606 intel_dp_aux_header(txbuf
, &msg
);
5608 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, HEADER_SIZE
+ msg
.size
,
5609 rxbuf
, sizeof(rxbuf
),
5610 DP_AUX_CH_CTL_AUX_AKSV_SELECT
);
5612 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret
);
5614 } else if (ret
== 0) {
5615 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5619 reply
= (rxbuf
[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK
;
5620 if (reply
!= DP_AUX_NATIVE_REPLY_ACK
) {
5621 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5628 static int intel_dp_hdcp_read_bksv(struct intel_digital_port
*intel_dig_port
,
5632 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BKSV
, bksv
,
5634 if (ret
!= DRM_HDCP_KSV_LEN
) {
5635 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret
);
5636 return ret
>= 0 ? -EIO
: ret
;
5641 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port
*intel_dig_port
,
5646 * For some reason the HDMI and DP HDCP specs call this register
5647 * definition by different names. In the HDMI spec, it's called BSTATUS,
5648 * but in DP it's called BINFO.
5650 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BINFO
,
5651 bstatus
, DRM_HDCP_BSTATUS_LEN
);
5652 if (ret
!= DRM_HDCP_BSTATUS_LEN
) {
5653 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5654 return ret
>= 0 ? -EIO
: ret
;
5660 int intel_dp_hdcp_read_bcaps(struct intel_digital_port
*intel_dig_port
,
5665 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BCAPS
,
5668 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret
);
5669 return ret
>= 0 ? -EIO
: ret
;
5676 int intel_dp_hdcp_repeater_present(struct intel_digital_port
*intel_dig_port
,
5677 bool *repeater_present
)
5682 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5686 *repeater_present
= bcaps
& DP_BCAPS_REPEATER_PRESENT
;
5691 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port
*intel_dig_port
,
5695 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_RI_PRIME
,
5696 ri_prime
, DRM_HDCP_RI_LEN
);
5697 if (ret
!= DRM_HDCP_RI_LEN
) {
5698 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret
);
5699 return ret
>= 0 ? -EIO
: ret
;
5705 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port
*intel_dig_port
,
5710 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5713 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5714 return ret
>= 0 ? -EIO
: ret
;
5716 *ksv_ready
= bstatus
& DP_BSTATUS_READY
;
5721 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port
*intel_dig_port
,
5722 int num_downstream
, u8
*ksv_fifo
)
5727 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5728 for (i
= 0; i
< num_downstream
; i
+= 3) {
5729 size_t len
= min(num_downstream
- i
, 3) * DRM_HDCP_KSV_LEN
;
5730 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5731 DP_AUX_HDCP_KSV_FIFO
,
5732 ksv_fifo
+ i
* DRM_HDCP_KSV_LEN
,
5735 DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5737 return ret
>= 0 ? -EIO
: ret
;
5744 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port
*intel_dig_port
,
5749 if (i
>= DRM_HDCP_V_PRIME_NUM_PARTS
)
5752 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5753 DP_AUX_HDCP_V_PRIME(i
), part
,
5754 DRM_HDCP_V_PRIME_PART_LEN
);
5755 if (ret
!= DRM_HDCP_V_PRIME_PART_LEN
) {
5756 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i
, ret
);
5757 return ret
>= 0 ? -EIO
: ret
;
5763 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port
*intel_dig_port
,
5766 /* Not used for single stream DisplayPort setups */
5771 bool intel_dp_hdcp_check_link(struct intel_digital_port
*intel_dig_port
)
5776 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5779 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5783 return !(bstatus
& (DP_BSTATUS_LINK_FAILURE
| DP_BSTATUS_REAUTH_REQ
));
5787 int intel_dp_hdcp_capable(struct intel_digital_port
*intel_dig_port
,
5793 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5797 *hdcp_capable
= bcaps
& DP_BCAPS_HDCP_CAPABLE
;
5801 static const struct intel_hdcp_shim intel_dp_hdcp_shim
= {
5802 .write_an_aksv
= intel_dp_hdcp_write_an_aksv
,
5803 .read_bksv
= intel_dp_hdcp_read_bksv
,
5804 .read_bstatus
= intel_dp_hdcp_read_bstatus
,
5805 .repeater_present
= intel_dp_hdcp_repeater_present
,
5806 .read_ri_prime
= intel_dp_hdcp_read_ri_prime
,
5807 .read_ksv_ready
= intel_dp_hdcp_read_ksv_ready
,
5808 .read_ksv_fifo
= intel_dp_hdcp_read_ksv_fifo
,
5809 .read_v_prime_part
= intel_dp_hdcp_read_v_prime_part
,
5810 .toggle_signalling
= intel_dp_hdcp_toggle_signalling
,
5811 .check_link
= intel_dp_hdcp_check_link
,
5812 .hdcp_capable
= intel_dp_hdcp_capable
,
5815 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
5817 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
5818 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5820 lockdep_assert_held(&dev_priv
->pps_mutex
);
5822 if (!edp_have_panel_vdd(intel_dp
))
5826 * The VDD bit needs a power domain reference, so if the bit is
5827 * already enabled when we boot or resume, grab this reference and
5828 * schedule a vdd off, so we don't hold on to the reference
5831 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5832 intel_display_power_get(dev_priv
, intel_aux_power_domain(dig_port
));
5834 edp_panel_vdd_schedule_off(intel_dp
);
5837 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
5839 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
5840 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
5843 if (intel_dp_port_enabled(dev_priv
, intel_dp
->output_reg
,
5844 encoder
->port
, &pipe
))
5847 return INVALID_PIPE
;
5850 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
5852 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
5853 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
5854 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
5855 intel_wakeref_t wakeref
;
5857 if (!HAS_DDI(dev_priv
))
5858 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5861 lspcon_resume(lspcon
);
5863 intel_dp
->reset_link_params
= true;
5865 with_pps_lock(intel_dp
, wakeref
) {
5866 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5867 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
5869 if (intel_dp_is_edp(intel_dp
)) {
5871 * Reinit the power sequencer, in case BIOS did
5872 * something nasty with it.
5874 intel_dp_pps_init(intel_dp
);
5875 intel_edp_panel_vdd_sanitize(intel_dp
);
5880 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
5881 .force
= intel_dp_force
,
5882 .fill_modes
= drm_helper_probe_single_connector_modes
,
5883 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
5884 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
5885 .late_register
= intel_dp_connector_register
,
5886 .early_unregister
= intel_dp_connector_unregister
,
5887 .destroy
= intel_connector_destroy
,
5888 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
5889 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
5892 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
5893 .detect_ctx
= intel_dp_detect
,
5894 .get_modes
= intel_dp_get_modes
,
5895 .mode_valid
= intel_dp_mode_valid
,
5896 .atomic_check
= intel_digital_connector_atomic_check
,
5899 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
5900 .reset
= intel_dp_encoder_reset
,
5901 .destroy
= intel_dp_encoder_destroy
,
5905 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
5907 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5908 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
5909 enum irqreturn ret
= IRQ_NONE
;
5910 intel_wakeref_t wakeref
;
5912 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5914 * vdd off can generate a long pulse on eDP which
5915 * would require vdd on to handle it, and thus we
5916 * would end up in an endless cycle of
5917 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5919 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5920 port_name(intel_dig_port
->base
.port
));
5924 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5925 port_name(intel_dig_port
->base
.port
),
5926 long_hpd
? "long" : "short");
5929 intel_dp
->reset_link_params
= true;
5933 wakeref
= intel_display_power_get(dev_priv
,
5934 intel_aux_power_domain(intel_dig_port
));
5936 if (intel_dp
->is_mst
) {
5937 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
5939 * If we were in MST mode, and device is not
5940 * there, get out of MST mode
5942 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5943 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5944 intel_dp
->is_mst
= false;
5945 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5951 if (!intel_dp
->is_mst
) {
5954 handled
= intel_dp_short_pulse(intel_dp
);
5963 intel_display_power_put(dev_priv
,
5964 intel_aux_power_domain(intel_dig_port
),
5970 /* check the VBT to see whether the eDP is on another port */
5971 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
)
5974 * eDP not supported on g4x. so bail out early just
5975 * for a bit extra safety in case the VBT is bonkers.
5977 if (INTEL_GEN(dev_priv
) < 5)
5980 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
5983 return intel_bios_is_port_edp(dev_priv
, port
);
5987 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5989 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5990 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
5992 if (!IS_G4X(dev_priv
) && port
!= PORT_A
)
5993 intel_attach_force_audio_property(connector
);
5995 intel_attach_broadcast_rgb_property(connector
);
5996 if (HAS_GMCH(dev_priv
))
5997 drm_connector_attach_max_bpc_property(connector
, 6, 10);
5998 else if (INTEL_GEN(dev_priv
) >= 5)
5999 drm_connector_attach_max_bpc_property(connector
, 6, 12);
6001 if (intel_dp_is_edp(intel_dp
)) {
6002 u32 allowed_scalers
;
6004 allowed_scalers
= BIT(DRM_MODE_SCALE_ASPECT
) | BIT(DRM_MODE_SCALE_FULLSCREEN
);
6005 if (!HAS_GMCH(dev_priv
))
6006 allowed_scalers
|= BIT(DRM_MODE_SCALE_CENTER
);
6008 drm_connector_attach_scaling_mode_property(connector
, allowed_scalers
);
6010 connector
->state
->scaling_mode
= DRM_MODE_SCALE_ASPECT
;
6015 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
6017 intel_dp
->panel_power_off_time
= ktime_get_boottime();
6018 intel_dp
->last_power_on
= jiffies
;
6019 intel_dp
->last_backlight_off
= jiffies
;
6023 intel_pps_readout_hw_state(struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
6025 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6026 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
6027 struct pps_registers regs
;
6029 intel_pps_get_registers(intel_dp
, ®s
);
6031 /* Workaround: Need to write PP_CONTROL with the unlock key as
6032 * the very first thing. */
6033 pp_ctl
= ironlake_get_pp_control(intel_dp
);
6035 pp_on
= I915_READ(regs
.pp_on
);
6036 pp_off
= I915_READ(regs
.pp_off
);
6037 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
6038 !HAS_PCH_ICP(dev_priv
)) {
6039 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
6040 pp_div
= I915_READ(regs
.pp_div
);
6043 /* Pull timing values out of registers */
6044 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
6045 PANEL_POWER_UP_DELAY_SHIFT
;
6047 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
6048 PANEL_LIGHT_ON_DELAY_SHIFT
;
6050 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
6051 PANEL_LIGHT_OFF_DELAY_SHIFT
;
6053 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
6054 PANEL_POWER_DOWN_DELAY_SHIFT
;
6056 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
6057 HAS_PCH_ICP(dev_priv
)) {
6058 seq
->t11_t12
= ((pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
6059 BXT_POWER_CYCLE_DELAY_SHIFT
) * 1000;
6061 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
6062 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
6067 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
6069 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6071 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
6075 intel_pps_verify_state(struct intel_dp
*intel_dp
)
6077 struct edp_power_seq hw
;
6078 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
6080 intel_pps_readout_hw_state(intel_dp
, &hw
);
6082 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
6083 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
6084 DRM_ERROR("PPS state mismatch\n");
6085 intel_pps_dump_state("sw", sw
);
6086 intel_pps_dump_state("hw", &hw
);
6091 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
6093 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6094 struct edp_power_seq cur
, vbt
, spec
,
6095 *final
= &intel_dp
->pps_delays
;
6097 lockdep_assert_held(&dev_priv
->pps_mutex
);
6099 /* already initialized? */
6100 if (final
->t11_t12
!= 0)
6103 intel_pps_readout_hw_state(intel_dp
, &cur
);
6105 intel_pps_dump_state("cur", &cur
);
6107 vbt
= dev_priv
->vbt
.edp
.pps
;
6108 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6109 * of 500ms appears to be too short. Ocassionally the panel
6110 * just fails to power back on. Increasing the delay to 800ms
6111 * seems sufficient to avoid this problem.
6113 if (dev_priv
->quirks
& QUIRK_INCREASE_T12_DELAY
) {
6114 vbt
.t11_t12
= max_t(u16
, vbt
.t11_t12
, 1300 * 10);
6115 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6118 /* T11_T12 delay is special and actually in units of 100ms, but zero
6119 * based in the hw (so we need to add 100 ms). But the sw vbt
6120 * table multiplies it with 1000 to make it in units of 100usec,
6122 vbt
.t11_t12
+= 100 * 10;
6124 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6125 * our hw here, which are all in 100usec. */
6126 spec
.t1_t3
= 210 * 10;
6127 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
6128 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
6129 spec
.t10
= 500 * 10;
6130 /* This one is special and actually in units of 100ms, but zero
6131 * based in the hw (so we need to add 100 ms). But the sw vbt
6132 * table multiplies it with 1000 to make it in units of 100usec,
6134 spec
.t11_t12
= (510 + 100) * 10;
6136 intel_pps_dump_state("vbt", &vbt
);
6138 /* Use the max of the register settings and vbt. If both are
6139 * unset, fall back to the spec limits. */
6140 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
6142 max(cur.field, vbt.field))
6143 assign_final(t1_t3
);
6147 assign_final(t11_t12
);
6150 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
6151 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
6152 intel_dp
->backlight_on_delay
= get_delay(t8
);
6153 intel_dp
->backlight_off_delay
= get_delay(t9
);
6154 intel_dp
->panel_power_down_delay
= get_delay(t10
);
6155 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
6158 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6159 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
6160 intel_dp
->panel_power_cycle_delay
);
6162 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6163 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
6166 * We override the HW backlight delays to 1 because we do manual waits
6167 * on them. For T8, even BSpec recommends doing it. For T9, if we
6168 * don't do this, we'll end up waiting for the backlight off delay
6169 * twice: once when we do the manual sleep, and once when we disable
6170 * the panel and wait for the PP_STATUS bit to become zero.
6176 * HW has only a 100msec granularity for t11_t12 so round it up
6179 final
->t11_t12
= roundup(final
->t11_t12
, 100 * 10);
6183 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
6184 bool force_disable_vdd
)
6186 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6187 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
6188 int div
= dev_priv
->rawclk_freq
/ 1000;
6189 struct pps_registers regs
;
6190 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
6191 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
6193 lockdep_assert_held(&dev_priv
->pps_mutex
);
6195 intel_pps_get_registers(intel_dp
, ®s
);
6198 * On some VLV machines the BIOS can leave the VDD
6199 * enabled even on power sequencers which aren't
6200 * hooked up to any port. This would mess up the
6201 * power domain tracking the first time we pick
6202 * one of these power sequencers for use since
6203 * edp_panel_vdd_on() would notice that the VDD was
6204 * already on and therefore wouldn't grab the power
6205 * domain reference. Disable VDD first to avoid this.
6206 * This also avoids spuriously turning the VDD on as
6207 * soon as the new power sequencer gets initialized.
6209 if (force_disable_vdd
) {
6210 u32 pp
= ironlake_get_pp_control(intel_dp
);
6212 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
6214 if (pp
& EDP_FORCE_VDD
)
6215 DRM_DEBUG_KMS("VDD already on, disabling first\n");
6217 pp
&= ~EDP_FORCE_VDD
;
6219 I915_WRITE(regs
.pp_ctrl
, pp
);
6222 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
6223 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
6224 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
6225 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
6226 /* Compute the divisor for the pp clock, simply match the Bspec
6228 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
6229 HAS_PCH_ICP(dev_priv
)) {
6230 pp_div
= I915_READ(regs
.pp_ctrl
);
6231 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
6232 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
6233 << BXT_POWER_CYCLE_DELAY_SHIFT
);
6235 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
6236 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
6237 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
6240 /* Haswell doesn't have any port selection bits for the panel
6241 * power sequencer any more. */
6242 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6243 port_sel
= PANEL_PORT_SELECT_VLV(port
);
6244 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
6247 port_sel
= PANEL_PORT_SELECT_DPA
;
6250 port_sel
= PANEL_PORT_SELECT_DPC
;
6253 port_sel
= PANEL_PORT_SELECT_DPD
;
6263 I915_WRITE(regs
.pp_on
, pp_on
);
6264 I915_WRITE(regs
.pp_off
, pp_off
);
6265 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
6266 HAS_PCH_ICP(dev_priv
))
6267 I915_WRITE(regs
.pp_ctrl
, pp_div
);
6269 I915_WRITE(regs
.pp_div
, pp_div
);
6271 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6272 I915_READ(regs
.pp_on
),
6273 I915_READ(regs
.pp_off
),
6274 (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
6275 HAS_PCH_ICP(dev_priv
)) ?
6276 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
6277 I915_READ(regs
.pp_div
));
6280 static void intel_dp_pps_init(struct intel_dp
*intel_dp
)
6282 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6284 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6285 vlv_initial_power_sequencer_setup(intel_dp
);
6287 intel_dp_init_panel_power_sequencer(intel_dp
);
6288 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
6293 * intel_dp_set_drrs_state - program registers for RR switch to take effect
6294 * @dev_priv: i915 device
6295 * @crtc_state: a pointer to the active intel_crtc_state
6296 * @refresh_rate: RR to be programmed
6298 * This function gets called when refresh rate (RR) has to be changed from
6299 * one frequency to another. Switches can be between high and low RR
6300 * supported by the panel or to any other RR based on media playback (in
6301 * this case, RR value needs to be passed from user space).
6303 * The caller of this function needs to take a lock on dev_priv->drrs.
6305 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
6306 const struct intel_crtc_state
*crtc_state
,
6309 struct intel_encoder
*encoder
;
6310 struct intel_digital_port
*dig_port
= NULL
;
6311 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
6312 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6313 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
6315 if (refresh_rate
<= 0) {
6316 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6320 if (intel_dp
== NULL
) {
6321 DRM_DEBUG_KMS("DRRS not supported.\n");
6325 dig_port
= dp_to_dig_port(intel_dp
);
6326 encoder
= &dig_port
->base
;
6329 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6333 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
6334 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6338 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
6340 index
= DRRS_LOW_RR
;
6342 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
6344 "DRRS requested for previously set RR...ignoring\n");
6348 if (!crtc_state
->base
.active
) {
6349 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6353 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
6356 intel_dp_set_m_n(crtc_state
, M1_N1
);
6359 intel_dp_set_m_n(crtc_state
, M2_N2
);
6363 DRM_ERROR("Unsupported refreshrate type\n");
6365 } else if (INTEL_GEN(dev_priv
) > 6) {
6366 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
6369 val
= I915_READ(reg
);
6370 if (index
> DRRS_HIGH_RR
) {
6371 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6372 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
6374 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
6376 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6377 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
6379 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
6381 I915_WRITE(reg
, val
);
6384 dev_priv
->drrs
.refresh_rate_type
= index
;
6386 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
6390 * intel_edp_drrs_enable - init drrs struct if supported
6391 * @intel_dp: DP struct
6392 * @crtc_state: A pointer to the active crtc state.
6394 * Initializes frontbuffer_bits and drrs.dp
6396 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
6397 const struct intel_crtc_state
*crtc_state
)
6399 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6401 if (!crtc_state
->has_drrs
) {
6402 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6406 if (dev_priv
->psr
.enabled
) {
6407 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6411 mutex_lock(&dev_priv
->drrs
.mutex
);
6412 if (dev_priv
->drrs
.dp
) {
6413 DRM_DEBUG_KMS("DRRS already enabled\n");
6417 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
6419 dev_priv
->drrs
.dp
= intel_dp
;
6422 mutex_unlock(&dev_priv
->drrs
.mutex
);
6426 * intel_edp_drrs_disable - Disable DRRS
6427 * @intel_dp: DP struct
6428 * @old_crtc_state: Pointer to old crtc_state.
6431 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
6432 const struct intel_crtc_state
*old_crtc_state
)
6434 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6436 if (!old_crtc_state
->has_drrs
)
6439 mutex_lock(&dev_priv
->drrs
.mutex
);
6440 if (!dev_priv
->drrs
.dp
) {
6441 mutex_unlock(&dev_priv
->drrs
.mutex
);
6445 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6446 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
6447 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6449 dev_priv
->drrs
.dp
= NULL
;
6450 mutex_unlock(&dev_priv
->drrs
.mutex
);
6452 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
6455 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
6457 struct drm_i915_private
*dev_priv
=
6458 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
6459 struct intel_dp
*intel_dp
;
6461 mutex_lock(&dev_priv
->drrs
.mutex
);
6463 intel_dp
= dev_priv
->drrs
.dp
;
6469 * The delayed work can race with an invalidate hence we need to
6473 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
6476 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
6477 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
6479 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6480 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
6484 mutex_unlock(&dev_priv
->drrs
.mutex
);
6488 * intel_edp_drrs_invalidate - Disable Idleness DRRS
6489 * @dev_priv: i915 device
6490 * @frontbuffer_bits: frontbuffer plane tracking bits
6492 * This function gets called everytime rendering on the given planes start.
6493 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6495 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6497 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
6498 unsigned int frontbuffer_bits
)
6500 struct drm_crtc
*crtc
;
6503 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
6506 cancel_delayed_work(&dev_priv
->drrs
.work
);
6508 mutex_lock(&dev_priv
->drrs
.mutex
);
6509 if (!dev_priv
->drrs
.dp
) {
6510 mutex_unlock(&dev_priv
->drrs
.mutex
);
6514 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
6515 pipe
= to_intel_crtc(crtc
)->pipe
;
6517 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
6518 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
6520 /* invalidate means busy screen hence upclock */
6521 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6522 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6523 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6525 mutex_unlock(&dev_priv
->drrs
.mutex
);
6529 * intel_edp_drrs_flush - Restart Idleness DRRS
6530 * @dev_priv: i915 device
6531 * @frontbuffer_bits: frontbuffer plane tracking bits
6533 * This function gets called every time rendering on the given planes has
6534 * completed or flip on a crtc is completed. So DRRS should be upclocked
6535 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6536 * if no other planes are dirty.
6538 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6540 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
6541 unsigned int frontbuffer_bits
)
6543 struct drm_crtc
*crtc
;
6546 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
6549 cancel_delayed_work(&dev_priv
->drrs
.work
);
6551 mutex_lock(&dev_priv
->drrs
.mutex
);
6552 if (!dev_priv
->drrs
.dp
) {
6553 mutex_unlock(&dev_priv
->drrs
.mutex
);
6557 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
6558 pipe
= to_intel_crtc(crtc
)->pipe
;
6560 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
6561 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
6563 /* flush means busy screen hence upclock */
6564 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6565 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6566 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6569 * flush also means no more activity hence schedule downclock, if all
6570 * other fbs are quiescent too
6572 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
6573 schedule_delayed_work(&dev_priv
->drrs
.work
,
6574 msecs_to_jiffies(1000));
6575 mutex_unlock(&dev_priv
->drrs
.mutex
);
6579 * DOC: Display Refresh Rate Switching (DRRS)
6581 * Display Refresh Rate Switching (DRRS) is a power conservation feature
6582 * which enables swtching between low and high refresh rates,
6583 * dynamically, based on the usage scenario. This feature is applicable
6584 * for internal panels.
6586 * Indication that the panel supports DRRS is given by the panel EDID, which
6587 * would list multiple refresh rates for one resolution.
6589 * DRRS is of 2 types - static and seamless.
6590 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6591 * (may appear as a blink on screen) and is used in dock-undock scenario.
6592 * Seamless DRRS involves changing RR without any visual effect to the user
6593 * and can be used during normal system usage. This is done by programming
6594 * certain registers.
6596 * Support for static/seamless DRRS may be indicated in the VBT based on
6597 * inputs from the panel spec.
6599 * DRRS saves power by switching to low RR based on usage scenarios.
6601 * The implementation is based on frontbuffer tracking implementation. When
6602 * there is a disturbance on the screen triggered by user activity or a periodic
6603 * system activity, DRRS is disabled (RR is changed to high RR). When there is
6604 * no movement on screen, after a timeout of 1 second, a switch to low RR is
6607 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6608 * and intel_edp_drrs_flush() are called.
6610 * DRRS can be further extended to support other internal panels and also
6611 * the scenario of video playback wherein RR is set based on the rate
6612 * requested by userspace.
6616 * intel_dp_drrs_init - Init basic DRRS work and mutex.
6617 * @connector: eDP connector
6618 * @fixed_mode: preferred mode of panel
6620 * This function is called only once at driver load to initialize basic
6624 * Downclock mode if panel supports it, else return NULL.
6625 * DRRS support is determined by the presence of downclock mode (apart
6626 * from VBT setting).
6628 static struct drm_display_mode
*
6629 intel_dp_drrs_init(struct intel_connector
*connector
,
6630 struct drm_display_mode
*fixed_mode
)
6632 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
6633 struct drm_display_mode
*downclock_mode
= NULL
;
6635 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
6636 mutex_init(&dev_priv
->drrs
.mutex
);
6638 if (INTEL_GEN(dev_priv
) <= 6) {
6639 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6643 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
6644 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6648 downclock_mode
= intel_find_panel_downclock(dev_priv
, fixed_mode
,
6651 if (!downclock_mode
) {
6652 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6656 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
6658 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
6659 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6660 return downclock_mode
;
6663 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
6664 struct intel_connector
*intel_connector
)
6666 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6667 struct drm_device
*dev
= &dev_priv
->drm
;
6668 struct drm_connector
*connector
= &intel_connector
->base
;
6669 struct drm_display_mode
*fixed_mode
= NULL
;
6670 struct drm_display_mode
*downclock_mode
= NULL
;
6672 struct drm_display_mode
*scan
;
6673 enum pipe pipe
= INVALID_PIPE
;
6674 intel_wakeref_t wakeref
;
6677 if (!intel_dp_is_edp(intel_dp
))
6680 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
, edp_panel_vdd_work
);
6683 * On IBX/CPT we may get here with LVDS already registered. Since the
6684 * driver uses the only internal power sequencer available for both
6685 * eDP and LVDS bail out early in this case to prevent interfering
6686 * with an already powered-on LVDS power sequencer.
6688 if (intel_get_lvds_encoder(&dev_priv
->drm
)) {
6689 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
6690 DRM_INFO("LVDS was detected, not registering eDP\n");
6695 with_pps_lock(intel_dp
, wakeref
) {
6696 intel_dp_init_panel_power_timestamps(intel_dp
);
6697 intel_dp_pps_init(intel_dp
);
6698 intel_edp_panel_vdd_sanitize(intel_dp
);
6701 /* Cache DPCD and EDID for edp. */
6702 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
6705 /* if this fails, presume the device is a ghost */
6706 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6710 mutex_lock(&dev
->mode_config
.mutex
);
6711 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
6713 if (drm_add_edid_modes(connector
, edid
)) {
6714 drm_connector_update_edid_property(connector
,
6718 edid
= ERR_PTR(-EINVAL
);
6721 edid
= ERR_PTR(-ENOENT
);
6723 intel_connector
->edid
= edid
;
6725 /* prefer fixed mode from EDID if available */
6726 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
6727 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
6728 fixed_mode
= drm_mode_duplicate(dev
, scan
);
6729 downclock_mode
= intel_dp_drrs_init(
6730 intel_connector
, fixed_mode
);
6735 /* fallback to VBT if available for eDP */
6736 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
6737 fixed_mode
= drm_mode_duplicate(dev
,
6738 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
6740 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
6741 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
6742 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
6745 mutex_unlock(&dev
->mode_config
.mutex
);
6747 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6748 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
6749 register_reboot_notifier(&intel_dp
->edp_notifier
);
6752 * Figure out the current pipe for the initial backlight setup.
6753 * If the current pipe isn't valid, try the PPS pipe, and if that
6754 * fails just assume pipe A.
6756 pipe
= vlv_active_pipe(intel_dp
);
6758 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
6759 pipe
= intel_dp
->pps_pipe
;
6761 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
6764 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6768 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
6769 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
6770 intel_panel_setup_backlight(connector
, pipe
);
6773 drm_connector_init_panel_orientation_property(
6774 connector
, fixed_mode
->hdisplay
, fixed_mode
->vdisplay
);
6779 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
6781 * vdd might still be enabled do to the delayed vdd off.
6782 * Make sure vdd is actually turned off here.
6784 with_pps_lock(intel_dp
, wakeref
)
6785 edp_panel_vdd_off_sync(intel_dp
);
6790 static void intel_dp_modeset_retry_work_fn(struct work_struct
*work
)
6792 struct intel_connector
*intel_connector
;
6793 struct drm_connector
*connector
;
6795 intel_connector
= container_of(work
, typeof(*intel_connector
),
6796 modeset_retry_work
);
6797 connector
= &intel_connector
->base
;
6798 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector
->base
.id
,
6801 /* Grab the locks before changing connector property*/
6802 mutex_lock(&connector
->dev
->mode_config
.mutex
);
6803 /* Set connector link status to BAD and send a Uevent to notify
6804 * userspace to do a modeset.
6806 drm_connector_set_link_status_property(connector
,
6807 DRM_MODE_LINK_STATUS_BAD
);
6808 mutex_unlock(&connector
->dev
->mode_config
.mutex
);
6809 /* Send Hotplug uevent so userspace can reprobe */
6810 drm_kms_helper_hotplug_event(connector
->dev
);
6814 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
6815 struct intel_connector
*intel_connector
)
6817 struct drm_connector
*connector
= &intel_connector
->base
;
6818 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
6819 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
6820 struct drm_device
*dev
= intel_encoder
->base
.dev
;
6821 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6822 enum port port
= intel_encoder
->port
;
6825 /* Initialize the work for modeset in case of link train failure */
6826 INIT_WORK(&intel_connector
->modeset_retry_work
,
6827 intel_dp_modeset_retry_work_fn
);
6829 if (WARN(intel_dig_port
->max_lanes
< 1,
6830 "Not enough lanes (%d) for DP on port %c\n",
6831 intel_dig_port
->max_lanes
, port_name(port
)))
6834 intel_dp_set_source_rates(intel_dp
);
6836 intel_dp
->reset_link_params
= true;
6837 intel_dp
->pps_pipe
= INVALID_PIPE
;
6838 intel_dp
->active_pipe
= INVALID_PIPE
;
6840 /* intel_dp vfuncs */
6841 if (HAS_DDI(dev_priv
))
6842 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
6844 /* Preserve the current hw state. */
6845 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
6846 intel_dp
->attached_connector
= intel_connector
;
6848 if (intel_dp_is_port_edp(dev_priv
, port
))
6849 type
= DRM_MODE_CONNECTOR_eDP
;
6851 type
= DRM_MODE_CONNECTOR_DisplayPort
;
6853 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6854 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
6857 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6858 * for DP the encoder type can be set by the caller to
6859 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6861 if (type
== DRM_MODE_CONNECTOR_eDP
)
6862 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
6864 /* eDP only on port B and/or C on vlv/chv */
6865 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
6866 intel_dp_is_edp(intel_dp
) &&
6867 port
!= PORT_B
&& port
!= PORT_C
))
6870 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6871 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
6874 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
6875 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
6877 if (!HAS_GMCH(dev_priv
))
6878 connector
->interlace_allowed
= true;
6879 connector
->doublescan_allowed
= 0;
6881 intel_encoder
->hpd_pin
= intel_hpd_pin_default(dev_priv
, port
);
6883 intel_dp_aux_init(intel_dp
);
6885 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
6887 if (HAS_DDI(dev_priv
))
6888 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
6890 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
6892 /* init MST on ports that can support it */
6893 if (HAS_DP_MST(dev_priv
) && !intel_dp_is_edp(intel_dp
) &&
6894 (port
== PORT_B
|| port
== PORT_C
||
6895 port
== PORT_D
|| port
== PORT_F
))
6896 intel_dp_mst_encoder_init(intel_dig_port
,
6897 intel_connector
->base
.base
.id
);
6899 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
6900 intel_dp_aux_fini(intel_dp
);
6901 intel_dp_mst_encoder_cleanup(intel_dig_port
);
6905 intel_dp_add_properties(intel_dp
, connector
);
6907 if (is_hdcp_supported(dev_priv
, port
) && !intel_dp_is_edp(intel_dp
)) {
6908 int ret
= intel_hdcp_init(intel_connector
, &intel_dp_hdcp_shim
);
6910 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6913 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6914 * 0xd. Failure to do so will result in spurious interrupts being
6915 * generated on the port when a cable is not attached.
6917 if (IS_G45(dev_priv
)) {
6918 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
6919 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
6925 drm_connector_cleanup(connector
);
6930 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
6931 i915_reg_t output_reg
,
6934 struct intel_digital_port
*intel_dig_port
;
6935 struct intel_encoder
*intel_encoder
;
6936 struct drm_encoder
*encoder
;
6937 struct intel_connector
*intel_connector
;
6939 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
6940 if (!intel_dig_port
)
6943 intel_connector
= intel_connector_alloc();
6944 if (!intel_connector
)
6945 goto err_connector_alloc
;
6947 intel_encoder
= &intel_dig_port
->base
;
6948 encoder
= &intel_encoder
->base
;
6950 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
6951 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
6952 "DP %c", port_name(port
)))
6953 goto err_encoder_init
;
6955 intel_encoder
->hotplug
= intel_dp_hotplug
;
6956 intel_encoder
->compute_config
= intel_dp_compute_config
;
6957 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6958 intel_encoder
->get_config
= intel_dp_get_config
;
6959 intel_encoder
->update_pipe
= intel_panel_update_backlight
;
6960 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6961 if (IS_CHERRYVIEW(dev_priv
)) {
6962 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6963 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6964 intel_encoder
->enable
= vlv_enable_dp
;
6965 intel_encoder
->disable
= vlv_disable_dp
;
6966 intel_encoder
->post_disable
= chv_post_disable_dp
;
6967 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6968 } else if (IS_VALLEYVIEW(dev_priv
)) {
6969 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6970 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6971 intel_encoder
->enable
= vlv_enable_dp
;
6972 intel_encoder
->disable
= vlv_disable_dp
;
6973 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6975 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6976 intel_encoder
->enable
= g4x_enable_dp
;
6977 intel_encoder
->disable
= g4x_disable_dp
;
6978 intel_encoder
->post_disable
= g4x_post_disable_dp
;
6981 intel_dig_port
->dp
.output_reg
= output_reg
;
6982 intel_dig_port
->max_lanes
= 4;
6984 intel_encoder
->type
= INTEL_OUTPUT_DP
;
6985 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
6986 if (IS_CHERRYVIEW(dev_priv
)) {
6988 intel_encoder
->crtc_mask
= 1 << 2;
6990 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6992 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6994 intel_encoder
->cloneable
= 0;
6995 intel_encoder
->port
= port
;
6997 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
7000 intel_infoframe_init(intel_dig_port
);
7002 intel_dig_port
->aux_ch
= intel_bios_port_aux_ch(dev_priv
, port
);
7003 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
7004 goto err_init_connector
;
7009 drm_encoder_cleanup(encoder
);
7011 kfree(intel_connector
);
7012 err_connector_alloc
:
7013 kfree(intel_dig_port
);
7017 void intel_dp_mst_suspend(struct drm_i915_private
*dev_priv
)
7019 struct intel_encoder
*encoder
;
7021 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
7022 struct intel_dp
*intel_dp
;
7024 if (encoder
->type
!= INTEL_OUTPUT_DDI
)
7027 intel_dp
= enc_to_intel_dp(&encoder
->base
);
7029 if (!intel_dp
->can_mst
)
7032 if (intel_dp
->is_mst
)
7033 drm_dp_mst_topology_mgr_suspend(&intel_dp
->mst_mgr
);
7037 void intel_dp_mst_resume(struct drm_i915_private
*dev_priv
)
7039 struct intel_encoder
*encoder
;
7041 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
7042 struct intel_dp
*intel_dp
;
7045 if (encoder
->type
!= INTEL_OUTPUT_DDI
)
7048 intel_dp
= enc_to_intel_dp(&encoder
->base
);
7050 if (!intel_dp
->can_mst
)
7053 ret
= drm_dp_mst_topology_mgr_resume(&intel_dp
->mst_mgr
);
7055 intel_dp
->is_mst
= false;
7056 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,