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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[thirdparty/kernel/stable.git] / drivers / gpu / drm / i915 / intel_dsi_vbt.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24 *
25 */
26
27 #include <drm/drm_crtc.h>
28 #include <drm/drm_edid.h>
29 #include <drm/i915_drm.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/mfd/intel_soc_pmic.h>
32 #include <linux/slab.h>
33 #include <video/mipi_display.h>
34 #include <asm/intel-mid.h>
35 #include <asm/unaligned.h>
36 #include "i915_drv.h"
37 #include "intel_drv.h"
38 #include "intel_dsi.h"
39
40 #define MIPI_TRANSFER_MODE_SHIFT 0
41 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
42 #define MIPI_PORT_SHIFT 3
43
44 #define PREPARE_CNT_MAX 0x3F
45 #define EXIT_ZERO_CNT_MAX 0x3F
46 #define CLK_ZERO_CNT_MAX 0xFF
47 #define TRAIL_CNT_MAX 0x1F
48
49 #define NS_KHZ_RATIO 1000000
50
51 /* base offsets for gpio pads */
52 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
53 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
54 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
55 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
56 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
57 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
58 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
59 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
60 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
61 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
62 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
63 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
64
65 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
66 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
67
68 struct gpio_map {
69 u16 base_offset;
70 bool init;
71 };
72
73 static struct gpio_map vlv_gpio_table[] = {
74 { VLV_GPIO_NC_0_HV_DDI0_HPD },
75 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
76 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
77 { VLV_GPIO_NC_3_PANEL0_VDDEN },
78 { VLV_GPIO_NC_4_PANEL0_BKLTEN },
79 { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
80 { VLV_GPIO_NC_6_HV_DDI1_HPD },
81 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
82 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
83 { VLV_GPIO_NC_9_PANEL1_VDDEN },
84 { VLV_GPIO_NC_10_PANEL1_BKLTEN },
85 { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
86 };
87
88 #define CHV_GPIO_IDX_START_N 0
89 #define CHV_GPIO_IDX_START_E 73
90 #define CHV_GPIO_IDX_START_SW 100
91 #define CHV_GPIO_IDX_START_SE 198
92
93 #define CHV_VBT_MAX_PINS_PER_FMLY 15
94
95 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
96 #define CHV_GPIO_GPIOEN (1 << 15)
97 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
98 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
99 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
100 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
101 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
102
103 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
104 #define CHV_GPIO_CFGLOCK (1 << 31)
105
106 /* ICL DSI Display GPIO Pins */
107 #define ICL_GPIO_DDSP_HPD_A 0
108 #define ICL_GPIO_L_VDDEN_1 1
109 #define ICL_GPIO_L_BKLTEN_1 2
110 #define ICL_GPIO_DDPA_CTRLCLK_1 3
111 #define ICL_GPIO_DDPA_CTRLDATA_1 4
112 #define ICL_GPIO_DDSP_HPD_B 5
113 #define ICL_GPIO_L_VDDEN_2 6
114 #define ICL_GPIO_L_BKLTEN_2 7
115 #define ICL_GPIO_DDPA_CTRLCLK_2 8
116 #define ICL_GPIO_DDPA_CTRLDATA_2 9
117
118 static inline enum port intel_dsi_seq_port_to_port(u8 port)
119 {
120 return port ? PORT_C : PORT_A;
121 }
122
123 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
124 const u8 *data)
125 {
126 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
127 struct mipi_dsi_device *dsi_device;
128 u8 type, flags, seq_port;
129 u16 len;
130 enum port port;
131
132 DRM_DEBUG_KMS("\n");
133
134 flags = *data++;
135 type = *data++;
136
137 len = *((u16 *) data);
138 data += 2;
139
140 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
141
142 /* For DSI single link on Port A & C, the seq_port value which is
143 * parsed from Sequence Block#53 of VBT has been set to 0
144 * Now, read/write of packets for the DSI single link on Port A and
145 * Port C will based on the DVO port from VBT block 2.
146 */
147 if (intel_dsi->ports == (1 << PORT_C))
148 port = PORT_C;
149 else
150 port = intel_dsi_seq_port_to_port(seq_port);
151
152 dsi_device = intel_dsi->dsi_hosts[port]->device;
153 if (!dsi_device) {
154 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
155 goto out;
156 }
157
158 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
159 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
160 else
161 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
162
163 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
164
165 switch (type) {
166 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
167 mipi_dsi_generic_write(dsi_device, NULL, 0);
168 break;
169 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
170 mipi_dsi_generic_write(dsi_device, data, 1);
171 break;
172 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
173 mipi_dsi_generic_write(dsi_device, data, 2);
174 break;
175 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
176 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
177 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
178 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
179 break;
180 case MIPI_DSI_GENERIC_LONG_WRITE:
181 mipi_dsi_generic_write(dsi_device, data, len);
182 break;
183 case MIPI_DSI_DCS_SHORT_WRITE:
184 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
185 break;
186 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
187 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
188 break;
189 case MIPI_DSI_DCS_READ:
190 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
191 break;
192 case MIPI_DSI_DCS_LONG_WRITE:
193 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
194 break;
195 }
196
197 if (INTEL_GEN(dev_priv) < 11)
198 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
199
200 out:
201 data += len;
202
203 return data;
204 }
205
206 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
207 {
208 u32 delay = *((const u32 *) data);
209
210 DRM_DEBUG_KMS("\n");
211
212 usleep_range(delay, delay + 10);
213 data += 4;
214
215 return data;
216 }
217
218 static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
219 u8 gpio_source, u8 gpio_index, bool value)
220 {
221 struct gpio_map *map;
222 u16 pconf0, padval;
223 u32 tmp;
224 u8 port;
225
226 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
227 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
228 return;
229 }
230
231 map = &vlv_gpio_table[gpio_index];
232
233 if (dev_priv->vbt.dsi.seq_version >= 3) {
234 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
235 port = IOSF_PORT_GPIO_NC;
236 } else {
237 if (gpio_source == 0) {
238 port = IOSF_PORT_GPIO_NC;
239 } else if (gpio_source == 1) {
240 DRM_DEBUG_KMS("SC gpio not supported\n");
241 return;
242 } else {
243 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
244 return;
245 }
246 }
247
248 pconf0 = VLV_GPIO_PCONF0(map->base_offset);
249 padval = VLV_GPIO_PAD_VAL(map->base_offset);
250
251 mutex_lock(&dev_priv->sb_lock);
252 if (!map->init) {
253 /* FIXME: remove constant below */
254 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
255 map->init = true;
256 }
257
258 tmp = 0x4 | value;
259 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
260 mutex_unlock(&dev_priv->sb_lock);
261 }
262
263 static void chv_exec_gpio(struct drm_i915_private *dev_priv,
264 u8 gpio_source, u8 gpio_index, bool value)
265 {
266 u16 cfg0, cfg1;
267 u16 family_num;
268 u8 port;
269
270 if (dev_priv->vbt.dsi.seq_version >= 3) {
271 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
272 /* XXX: it's unclear whether 255->57 is part of SE. */
273 gpio_index -= CHV_GPIO_IDX_START_SE;
274 port = CHV_IOSF_PORT_GPIO_SE;
275 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
276 gpio_index -= CHV_GPIO_IDX_START_SW;
277 port = CHV_IOSF_PORT_GPIO_SW;
278 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
279 gpio_index -= CHV_GPIO_IDX_START_E;
280 port = CHV_IOSF_PORT_GPIO_E;
281 } else {
282 port = CHV_IOSF_PORT_GPIO_N;
283 }
284 } else {
285 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
286 if (gpio_source != 0) {
287 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
288 return;
289 }
290
291 if (gpio_index >= CHV_GPIO_IDX_START_E) {
292 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
293 gpio_index);
294 return;
295 }
296
297 port = CHV_IOSF_PORT_GPIO_N;
298 }
299
300 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
301 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
302
303 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
304 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
305
306 mutex_lock(&dev_priv->sb_lock);
307 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
308 vlv_iosf_sb_write(dev_priv, port, cfg0,
309 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
310 CHV_GPIO_GPIOTXSTATE(value));
311 mutex_unlock(&dev_priv->sb_lock);
312 }
313
314 static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
315 u8 gpio_source, u8 gpio_index, bool value)
316 {
317 /* XXX: this table is a quick ugly hack. */
318 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
319 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
320
321 if (!gpio_desc) {
322 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
323 NULL, gpio_index,
324 value ? GPIOD_OUT_LOW :
325 GPIOD_OUT_HIGH);
326
327 if (IS_ERR_OR_NULL(gpio_desc)) {
328 DRM_ERROR("GPIO index %u request failed (%ld)\n",
329 gpio_index, PTR_ERR(gpio_desc));
330 return;
331 }
332
333 bxt_gpio_table[gpio_index] = gpio_desc;
334 }
335
336 gpiod_set_value(gpio_desc, value);
337 }
338
339 static void icl_exec_gpio(struct drm_i915_private *dev_priv,
340 u8 gpio_source, u8 gpio_index, bool value)
341 {
342 DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
343 }
344
345 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
346 {
347 struct drm_device *dev = intel_dsi->base.base.dev;
348 struct drm_i915_private *dev_priv = to_i915(dev);
349 u8 gpio_source, gpio_index = 0, gpio_number;
350 bool value;
351
352 DRM_DEBUG_KMS("\n");
353
354 if (dev_priv->vbt.dsi.seq_version >= 3)
355 gpio_index = *data++;
356
357 gpio_number = *data++;
358
359 /* gpio source in sequence v2 only */
360 if (dev_priv->vbt.dsi.seq_version == 2)
361 gpio_source = (*data >> 1) & 3;
362 else
363 gpio_source = 0;
364
365 /* pull up/down */
366 value = *data++ & 1;
367
368 if (INTEL_GEN(dev_priv) >= 11)
369 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
370 else if (IS_VALLEYVIEW(dev_priv))
371 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
372 else if (IS_CHERRYVIEW(dev_priv))
373 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
374 else
375 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
376
377 return data;
378 }
379
380 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
381 {
382 DRM_DEBUG_KMS("Skipping I2C element execution\n");
383
384 return data + *(data + 6) + 7;
385 }
386
387 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
388 {
389 DRM_DEBUG_KMS("Skipping SPI element execution\n");
390
391 return data + *(data + 5) + 6;
392 }
393
394 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
395 {
396 #ifdef CONFIG_PMIC_OPREGION
397 u32 value, mask, reg_address;
398 u16 i2c_address;
399 int ret;
400
401 /* byte 0 aka PMIC Flag is reserved */
402 i2c_address = get_unaligned_le16(data + 1);
403 reg_address = get_unaligned_le32(data + 3);
404 value = get_unaligned_le32(data + 7);
405 mask = get_unaligned_le32(data + 11);
406
407 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
408 reg_address,
409 value, mask);
410 if (ret)
411 DRM_ERROR("%s failed, error: %d\n", __func__, ret);
412 #else
413 DRM_ERROR("Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
414 #endif
415
416 return data + 15;
417 }
418
419 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
420 const u8 *data);
421 static const fn_mipi_elem_exec exec_elem[] = {
422 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
423 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
424 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
425 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
426 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
427 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
428 };
429
430 /*
431 * MIPI Sequence from VBT #53 parsing logic
432 * We have already separated each seqence during bios parsing
433 * Following is generic execution function for any sequence
434 */
435
436 static const char * const seq_name[] = {
437 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
438 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
439 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
440 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
441 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
442 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
443 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
444 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
445 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
446 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
447 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
448 };
449
450 static const char *sequence_name(enum mipi_seq seq_id)
451 {
452 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
453 return seq_name[seq_id];
454 else
455 return "(unknown)";
456 }
457
458 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
459 enum mipi_seq seq_id)
460 {
461 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
462 const u8 *data;
463 fn_mipi_elem_exec mipi_elem_exec;
464
465 if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
466 return;
467
468 data = dev_priv->vbt.dsi.sequence[seq_id];
469 if (!data)
470 return;
471
472 WARN_ON(*data != seq_id);
473
474 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
475 seq_id, sequence_name(seq_id));
476
477 /* Skip Sequence Byte. */
478 data++;
479
480 /* Skip Size of Sequence. */
481 if (dev_priv->vbt.dsi.seq_version >= 3)
482 data += 4;
483
484 while (1) {
485 u8 operation_byte = *data++;
486 u8 operation_size = 0;
487
488 if (operation_byte == MIPI_SEQ_ELEM_END)
489 break;
490
491 if (operation_byte < ARRAY_SIZE(exec_elem))
492 mipi_elem_exec = exec_elem[operation_byte];
493 else
494 mipi_elem_exec = NULL;
495
496 /* Size of Operation. */
497 if (dev_priv->vbt.dsi.seq_version >= 3)
498 operation_size = *data++;
499
500 if (mipi_elem_exec) {
501 const u8 *next = data + operation_size;
502
503 data = mipi_elem_exec(intel_dsi, data);
504
505 /* Consistency check if we have size. */
506 if (operation_size && data != next) {
507 DRM_ERROR("Inconsistent operation size\n");
508 return;
509 }
510 } else if (operation_size) {
511 /* We have size, skip. */
512 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
513 operation_byte);
514 data += operation_size;
515 } else {
516 /* No size, can't skip without parsing. */
517 DRM_ERROR("Unsupported MIPI operation byte %u\n",
518 operation_byte);
519 return;
520 }
521 }
522 }
523
524 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
525 {
526 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
527
528 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
529 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
530 return;
531
532 msleep(msec);
533 }
534
535 #define ICL_PREPARE_CNT_MAX 0x7
536 #define ICL_CLK_ZERO_CNT_MAX 0xf
537 #define ICL_TRAIL_CNT_MAX 0x7
538 #define ICL_TCLK_PRE_CNT_MAX 0x3
539 #define ICL_TCLK_POST_CNT_MAX 0x7
540 #define ICL_HS_ZERO_CNT_MAX 0xf
541 #define ICL_EXIT_ZERO_CNT_MAX 0x7
542
543 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
544 {
545 struct drm_device *dev = intel_dsi->base.base.dev;
546 struct drm_i915_private *dev_priv = to_i915(dev);
547 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
548 u32 tlpx_ns;
549 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
550 u32 ths_prepare_ns, tclk_trail_ns;
551 u32 hs_zero_cnt;
552 u32 tclk_pre_cnt, tclk_post_cnt;
553
554 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
555
556 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
557 ths_prepare_ns = max(mipi_config->ths_prepare,
558 mipi_config->tclk_prepare);
559
560 /*
561 * prepare cnt in escape clocks
562 * this field represents a hexadecimal value with a precision
563 * of 1.2 – i.e. the most significant bit is the integer
564 * and the least significant 2 bits are fraction bits.
565 * so, the field can represent a range of 0.25 to 1.75
566 */
567 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
568 if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
569 DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
570 prepare_cnt = ICL_PREPARE_CNT_MAX;
571 }
572
573 /* clk zero count in escape clocks */
574 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
575 ths_prepare_ns, tlpx_ns);
576 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
577 DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
578 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
579 }
580
581 /* trail cnt in escape clocks*/
582 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
583 if (trail_cnt > ICL_TRAIL_CNT_MAX) {
584 DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
585 trail_cnt = ICL_TRAIL_CNT_MAX;
586 }
587
588 /* tclk pre count in escape clocks */
589 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
590 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
591 DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
592 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
593 }
594
595 /* tclk post count in escape clocks */
596 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
597 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
598 DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
599 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
600 }
601
602 /* hs zero cnt in escape clocks */
603 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
604 ths_prepare_ns, tlpx_ns);
605 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
606 DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
607 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
608 }
609
610 /* hs exit zero cnt in escape clocks */
611 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
612 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
613 DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
614 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
615 }
616
617 /* clock lane dphy timings */
618 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
619 CLK_PREPARE(prepare_cnt) |
620 CLK_ZERO_OVERRIDE |
621 CLK_ZERO(clk_zero_cnt) |
622 CLK_PRE_OVERRIDE |
623 CLK_PRE(tclk_pre_cnt) |
624 CLK_POST_OVERRIDE |
625 CLK_POST(tclk_post_cnt) |
626 CLK_TRAIL_OVERRIDE |
627 CLK_TRAIL(trail_cnt));
628
629 /* data lanes dphy timings */
630 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
631 HS_PREPARE(prepare_cnt) |
632 HS_ZERO_OVERRIDE |
633 HS_ZERO(hs_zero_cnt) |
634 HS_TRAIL_OVERRIDE |
635 HS_TRAIL(trail_cnt) |
636 HS_EXIT_OVERRIDE |
637 HS_EXIT(exit_zero_cnt));
638 }
639
640 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
641 {
642 struct drm_device *dev = intel_dsi->base.base.dev;
643 struct drm_i915_private *dev_priv = to_i915(dev);
644 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
645 u32 tlpx_ns, extra_byte_count, tlpx_ui;
646 u32 ui_num, ui_den;
647 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
648 u32 ths_prepare_ns, tclk_trail_ns;
649 u32 tclk_prepare_clkzero, ths_prepare_hszero;
650 u32 lp_to_hs_switch, hs_to_lp_switch;
651 u32 mul;
652
653 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
654
655 switch (intel_dsi->lane_count) {
656 case 1:
657 case 2:
658 extra_byte_count = 2;
659 break;
660 case 3:
661 extra_byte_count = 4;
662 break;
663 case 4:
664 default:
665 extra_byte_count = 3;
666 break;
667 }
668
669 /* in Kbps */
670 ui_num = NS_KHZ_RATIO;
671 ui_den = intel_dsi_bitrate(intel_dsi);
672
673 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
674 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
675
676 /*
677 * B060
678 * LP byte clock = TLPX/ (8UI)
679 */
680 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
681
682 /* DDR clock period = 2 * UI
683 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
684 * UI(nsec) = 10^6 / bitrate
685 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
686 * DDR clock count = ns_value / DDR clock period
687 *
688 * For GEMINILAKE dphy_param_reg will be programmed in terms of
689 * HS byte clock count for other platform in HS ddr clock count
690 */
691 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
692 ths_prepare_ns = max(mipi_config->ths_prepare,
693 mipi_config->tclk_prepare);
694
695 /* prepare count */
696 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
697
698 if (prepare_cnt > PREPARE_CNT_MAX) {
699 DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
700 prepare_cnt = PREPARE_CNT_MAX;
701 }
702
703 /* exit zero count */
704 exit_zero_cnt = DIV_ROUND_UP(
705 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
706 ui_num * mul
707 );
708
709 /*
710 * Exit zero is unified val ths_zero and ths_exit
711 * minimum value for ths_exit = 110ns
712 * min (exit_zero_cnt * 2) = 110/UI
713 * exit_zero_cnt = 55/UI
714 */
715 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
716 exit_zero_cnt += 1;
717
718 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
719 DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
720 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
721 }
722
723 /* clk zero count */
724 clk_zero_cnt = DIV_ROUND_UP(
725 (tclk_prepare_clkzero - ths_prepare_ns)
726 * ui_den, ui_num * mul);
727
728 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
729 DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
730 clk_zero_cnt = CLK_ZERO_CNT_MAX;
731 }
732
733 /* trail count */
734 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
735 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
736
737 if (trail_cnt > TRAIL_CNT_MAX) {
738 DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
739 trail_cnt = TRAIL_CNT_MAX;
740 }
741
742 /* B080 */
743 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
744 clk_zero_cnt << 8 | prepare_cnt;
745
746 /*
747 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
748 * mul + 10UI + Extra Byte Count
749 *
750 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
751 * Extra Byte Count is calculated according to number of lanes.
752 * High Low Switch Count is the Max of LP to HS and
753 * HS to LP switch count
754 *
755 */
756 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
757
758 /* B044 */
759 /* FIXME:
760 * The comment above does not match with the code */
761 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
762 exit_zero_cnt * mul + 10, 8);
763
764 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
765
766 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
767 intel_dsi->hs_to_lp_count += extra_byte_count;
768
769 /* B088 */
770 /* LP -> HS for clock lanes
771 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
772 * extra byte count
773 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
774 * 2(in UI) + extra byte count
775 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
776 * 8 + extra byte count
777 */
778 intel_dsi->clk_lp_to_hs_count =
779 DIV_ROUND_UP(
780 4 * tlpx_ui + prepare_cnt * 2 +
781 clk_zero_cnt * 2,
782 8);
783
784 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
785
786 /* HS->LP for Clock Lanes
787 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
788 * Extra byte count
789 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
790 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
791 * Extra byte count
792 */
793 intel_dsi->clk_hs_to_lp_count =
794 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
795 8);
796 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
797 }
798
799 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
800 {
801 struct drm_device *dev = intel_dsi->base.base.dev;
802 struct drm_i915_private *dev_priv = to_i915(dev);
803 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
804 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
805 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
806 u16 burst_mode_ratio;
807 enum port port;
808
809 DRM_DEBUG_KMS("\n");
810
811 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
812 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
813 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
814 intel_dsi->pixel_format =
815 pixel_format_from_register_bits(
816 mipi_config->videomode_color_format << 7);
817
818 intel_dsi->dual_link = mipi_config->dual_link;
819 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
820 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
821 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
822 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
823 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
824 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
825 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
826 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
827 intel_dsi->init_count = mipi_config->master_init_timer;
828 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
829 intel_dsi->video_frmt_cfg_bits =
830 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
831 intel_dsi->bgr_enabled = mipi_config->rgb_flip;
832
833 /* Starting point, adjusted depending on dual link and burst mode */
834 intel_dsi->pclk = mode->clock;
835
836 /* In dual link mode each port needs half of pixel clock */
837 if (intel_dsi->dual_link) {
838 intel_dsi->pclk /= 2;
839
840 /* we can enable pixel_overlap if needed by panel. In this
841 * case we need to increase the pixelclock for extra pixels
842 */
843 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
844 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
845 }
846 }
847
848 /* Burst Mode Ratio
849 * Target ddr frequency from VBT / non burst ddr freq
850 * multiply by 100 to preserve remainder
851 */
852 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
853 if (mipi_config->target_burst_mode_freq) {
854 u32 bitrate = intel_dsi_bitrate(intel_dsi);
855
856 if (mipi_config->target_burst_mode_freq < bitrate) {
857 DRM_ERROR("Burst mode freq is less than computed\n");
858 return false;
859 }
860
861 burst_mode_ratio = DIV_ROUND_UP(
862 mipi_config->target_burst_mode_freq * 100,
863 bitrate);
864
865 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
866 } else {
867 DRM_ERROR("Burst mode target is not set\n");
868 return false;
869 }
870 } else
871 burst_mode_ratio = 100;
872
873 intel_dsi->burst_mode_ratio = burst_mode_ratio;
874
875 if (INTEL_GEN(dev_priv) >= 11)
876 icl_dphy_param_init(intel_dsi);
877 else
878 vlv_dphy_param_init(intel_dsi);
879
880 DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
881 DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
882 DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count);
883 DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
884 DRM_DEBUG_KMS("Video mode format %s\n",
885 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
886 "non-burst with sync pulse" :
887 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
888 "non-burst with sync events" :
889 intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
890 "burst" : "<unknown>");
891 DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
892 DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val);
893 DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
894 DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop));
895 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
896 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
897 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
898 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
899 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
900 else
901 DRM_DEBUG_KMS("Dual link: NONE\n");
902 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
903 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
904 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
905 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
906 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
907 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
908 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
909 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
910 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
911 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
912 DRM_DEBUG_KMS("BTA %s\n",
913 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
914
915 /* delays in VBT are in unit of 100us, so need to convert
916 * here in ms
917 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
918 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
919 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
920 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
921 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
922 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
923
924 /* a regular driver would get the device in probe */
925 for_each_dsi_port(port, intel_dsi->ports) {
926 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
927 }
928
929 return true;
930 }
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