drivers/iommu/amd_iommu_types.h

   1 /*
   2  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <jroedel@suse.de>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
  21 #define _ASM_X86_AMD_IOMMU_TYPES_H
  22
  23 #include <linux/types.h>
  24 #include <linux/mutex.h>
  25 #include <linux/msi.h>
  26 #include <linux/list.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/pci.h>
  29 #include <linux/irqreturn.h>
  30
  31 /*
  32  * Maximum number of IOMMUs supported
  33  */
  34 #define MAX_IOMMUS      32
  35
  36 /*
  37  * some size calculation constants
  38  */
  39 #define DEV_TABLE_ENTRY_SIZE            32
  40 #define ALIAS_TABLE_ENTRY_SIZE          2
  41 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
  42
  43 /* Capability offsets used by the driver */
  44 #define MMIO_CAP_HDR_OFFSET     0x00
  45 #define MMIO_RANGE_OFFSET       0x0c
  46 #define MMIO_MISC_OFFSET        0x10
  47
  48 /* Masks, shifts and macros to parse the device range capability */
  49 #define MMIO_RANGE_LD_MASK      0xff000000
  50 #define MMIO_RANGE_FD_MASK      0x00ff0000
  51 #define MMIO_RANGE_BUS_MASK     0x0000ff00
  52 #define MMIO_RANGE_LD_SHIFT     24
  53 #define MMIO_RANGE_FD_SHIFT     16
  54 #define MMIO_RANGE_BUS_SHIFT    8
  55 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
  56 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
  57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
  58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
  59
  60 /* Flag masks for the AMD IOMMU exclusion range */
  61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
  62 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
  63
  64 /* Used offsets into the MMIO space */
  65 #define MMIO_DEV_TABLE_OFFSET   0x0000
  66 #define MMIO_CMD_BUF_OFFSET     0x0008
  67 #define MMIO_EVT_BUF_OFFSET     0x0010
  68 #define MMIO_CONTROL_OFFSET     0x0018
  69 #define MMIO_EXCL_BASE_OFFSET   0x0020
  70 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
  71 #define MMIO_EXT_FEATURES       0x0030
  72 #define MMIO_PPR_LOG_OFFSET     0x0038
  73 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0
  74 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
  75 #define MMIO_CMD_HEAD_OFFSET    0x2000
  76 #define MMIO_CMD_TAIL_OFFSET    0x2008
  77 #define MMIO_EVT_HEAD_OFFSET    0x2010
  78 #define MMIO_EVT_TAIL_OFFSET    0x2018
  79 #define MMIO_STATUS_OFFSET      0x2020
  80 #define MMIO_PPR_HEAD_OFFSET    0x2030
  81 #define MMIO_PPR_TAIL_OFFSET    0x2038
  82 #define MMIO_GA_HEAD_OFFSET     0x2040
  83 #define MMIO_GA_TAIL_OFFSET     0x2048
  84 #define MMIO_CNTR_CONF_OFFSET   0x4000
  85 #define MMIO_CNTR_REG_OFFSET    0x40000
  86 #define MMIO_REG_END_OFFSET     0x80000
  87
  88
  89
  90 /* Extended Feature Bits */
  91 #define FEATURE_PREFETCH        (1ULL<<0)
  92 #define FEATURE_PPR             (1ULL<<1)
  93 #define FEATURE_X2APIC          (1ULL<<2)
  94 #define FEATURE_NX              (1ULL<<3)
  95 #define FEATURE_GT              (1ULL<<4)
  96 #define FEATURE_IA              (1ULL<<6)
  97 #define FEATURE_GA              (1ULL<<7)
  98 #define FEATURE_HE              (1ULL<<8)
  99 #define FEATURE_PC              (1ULL<<9)
 100 #define FEATURE_GAM_VAPIC       (1ULL<<21)
 101 #define FEATURE_EPHSUP          (1ULL<<50)
 102
 103 #define FEATURE_PASID_SHIFT     32
 104 #define FEATURE_PASID_MASK      (0x1fULL << FEATURE_PASID_SHIFT)
 105
 106 #define FEATURE_GLXVAL_SHIFT    14
 107 #define FEATURE_GLXVAL_MASK     (0x03ULL << FEATURE_GLXVAL_SHIFT)
 108
 109 /* Note:
 110  * The current driver only support 16-bit PASID.
 111  * Currently, hardware only implement upto 16-bit PASID
 112  * even though the spec says it could have upto 20 bits.
 113  */
 114 #define PASID_MASK              0x0000ffff
 115
 116 /* MMIO status bits */
 117 #define MMIO_STATUS_EVT_INT_MASK        (1 << 1)
 118 #define MMIO_STATUS_COM_WAIT_INT_MASK   (1 << 2)
 119 #define MMIO_STATUS_PPR_INT_MASK        (1 << 6)
 120 #define MMIO_STATUS_GALOG_RUN_MASK      (1 << 8)
 121 #define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
 122 #define MMIO_STATUS_GALOG_INT_MASK      (1 << 10)
 123
 124 /* event logging constants */
 125 #define EVENT_ENTRY_SIZE        0x10
 126 #define EVENT_TYPE_SHIFT        28
 127 #define EVENT_TYPE_MASK         0xf
 128 #define EVENT_TYPE_ILL_DEV      0x1
 129 #define EVENT_TYPE_IO_FAULT     0x2
 130 #define EVENT_TYPE_DEV_TAB_ERR  0x3
 131 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
 132 #define EVENT_TYPE_ILL_CMD      0x5
 133 #define EVENT_TYPE_CMD_HARD_ERR 0x6
 134 #define EVENT_TYPE_IOTLB_INV_TO 0x7
 135 #define EVENT_TYPE_INV_DEV_REQ  0x8
 136 #define EVENT_TYPE_INV_PPR_REQ  0x9
 137 #define EVENT_DEVID_MASK        0xffff
 138 #define EVENT_DEVID_SHIFT       0
 139 #define EVENT_DOMID_MASK        0xffff
 140 #define EVENT_DOMID_SHIFT       0
 141 #define EVENT_FLAGS_MASK        0xfff
 142 #define EVENT_FLAGS_SHIFT       0x10
 143
 144 /* feature control bits */
 145 #define CONTROL_IOMMU_EN        0x00ULL
 146 #define CONTROL_HT_TUN_EN       0x01ULL
 147 #define CONTROL_EVT_LOG_EN      0x02ULL
 148 #define CONTROL_EVT_INT_EN      0x03ULL
 149 #define CONTROL_COMWAIT_EN      0x04ULL
 150 #define CONTROL_INV_TIMEOUT     0x05ULL
 151 #define CONTROL_PASSPW_EN       0x08ULL
 152 #define CONTROL_RESPASSPW_EN    0x09ULL
 153 #define CONTROL_COHERENT_EN     0x0aULL
 154 #define CONTROL_ISOC_EN         0x0bULL
 155 #define CONTROL_CMDBUF_EN       0x0cULL
 156 #define CONTROL_PPFLOG_EN       0x0dULL
 157 #define CONTROL_PPFINT_EN       0x0eULL
 158 #define CONTROL_PPR_EN          0x0fULL
 159 #define CONTROL_GT_EN           0x10ULL
 160 #define CONTROL_GA_EN           0x11ULL
 161 #define CONTROL_GAM_EN          0x19ULL
 162 #define CONTROL_GALOG_EN        0x1CULL
 163 #define CONTROL_GAINT_EN        0x1DULL
 164 #define CONTROL_XT_EN           0x32ULL
 165
 166 #define CTRL_INV_TO_MASK        (7 << CONTROL_INV_TIMEOUT)
 167 #define CTRL_INV_TO_NONE        0
 168 #define CTRL_INV_TO_1MS         1
 169 #define CTRL_INV_TO_10MS        2
 170 #define CTRL_INV_TO_100MS       3
 171 #define CTRL_INV_TO_1S          4
 172 #define CTRL_INV_TO_10S         5
 173 #define CTRL_INV_TO_100S        6
 174
 175 /* command specific defines */
 176 #define CMD_COMPL_WAIT          0x01
 177 #define CMD_INV_DEV_ENTRY       0x02
 178 #define CMD_INV_IOMMU_PAGES     0x03
 179 #define CMD_INV_IOTLB_PAGES     0x04
 180 #define CMD_INV_IRT             0x05
 181 #define CMD_COMPLETE_PPR        0x07
 182 #define CMD_INV_ALL             0x08
 183
 184 #define CMD_COMPL_WAIT_STORE_MASK       0x01
 185 #define CMD_COMPL_WAIT_INT_MASK         0x02
 186 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 187 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 188 #define CMD_INV_IOMMU_PAGES_GN_MASK     0x04
 189
 190 #define PPR_STATUS_MASK                 0xf
 191 #define PPR_STATUS_SHIFT                12
 192
 193 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
 194
 195 /* macros and definitions for device table entries */
 196 #define DEV_ENTRY_VALID         0x00
 197 #define DEV_ENTRY_TRANSLATION   0x01
 198 #define DEV_ENTRY_PPR           0x34
 199 #define DEV_ENTRY_IR            0x3d
 200 #define DEV_ENTRY_IW            0x3e
 201 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
 202 #define DEV_ENTRY_EX            0x67
 203 #define DEV_ENTRY_SYSMGT1       0x68
 204 #define DEV_ENTRY_SYSMGT2       0x69
 205 #define DEV_ENTRY_IRQ_TBL_EN    0x80
 206 #define DEV_ENTRY_INIT_PASS     0xb8
 207 #define DEV_ENTRY_EINT_PASS     0xb9
 208 #define DEV_ENTRY_NMI_PASS      0xba
 209 #define DEV_ENTRY_LINT0_PASS    0xbe
 210 #define DEV_ENTRY_LINT1_PASS    0xbf
 211 #define DEV_ENTRY_MODE_MASK     0x07
 212 #define DEV_ENTRY_MODE_SHIFT    0x09
 213
 214 #define MAX_DEV_TABLE_ENTRIES   0xffff
 215
 216 /* constants to configure the command buffer */
 217 #define CMD_BUFFER_SIZE    8192
 218 #define CMD_BUFFER_UNINITIALIZED 1
 219 #define CMD_BUFFER_ENTRIES 512
 220 #define MMIO_CMD_SIZE_SHIFT 56
 221 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 222
 223 /* constants for event buffer handling */
 224 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 225 #define EVT_LEN_MASK            (0x9ULL << 56)
 226
 227 /* Constants for PPR Log handling */
 228 #define PPR_LOG_ENTRIES         512
 229 #define PPR_LOG_SIZE_SHIFT      56
 230 #define PPR_LOG_SIZE_512        (0x9ULL << PPR_LOG_SIZE_SHIFT)
 231 #define PPR_ENTRY_SIZE          16
 232 #define PPR_LOG_SIZE            (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
 233
 234 #define PPR_REQ_TYPE(x)         (((x) >> 60) & 0xfULL)
 235 #define PPR_FLAGS(x)            (((x) >> 48) & 0xfffULL)
 236 #define PPR_DEVID(x)            ((x) & 0xffffULL)
 237 #define PPR_TAG(x)              (((x) >> 32) & 0x3ffULL)
 238 #define PPR_PASID1(x)           (((x) >> 16) & 0xffffULL)
 239 #define PPR_PASID2(x)           (((x) >> 42) & 0xfULL)
 240 #define PPR_PASID(x)            ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
 241
 242 #define PPR_REQ_FAULT           0x01
 243
 244 /* Constants for GA Log handling */
 245 #define GA_LOG_ENTRIES          512
 246 #define GA_LOG_SIZE_SHIFT       56
 247 #define GA_LOG_SIZE_512         (0x8ULL << GA_LOG_SIZE_SHIFT)
 248 #define GA_ENTRY_SIZE           8
 249 #define GA_LOG_SIZE             (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
 250
 251 #define GA_TAG(x)               (u32)(x & 0xffffffffULL)
 252 #define GA_DEVID(x)             (u16)(((x) >> 32) & 0xffffULL)
 253 #define GA_REQ_TYPE(x)          (((x) >> 60) & 0xfULL)
 254
 255 #define GA_GUEST_NR             0x1
 256
 257 /* Bit value definition for dte irq remapping fields*/
 258 #define DTE_IRQ_PHYS_ADDR_MASK  (((1ULL << 45)-1) << 6)
 259 #define DTE_IRQ_REMAP_INTCTL_MASK       (0x3ULL << 60)
 260 #define DTE_IRQ_TABLE_LEN_MASK  (0xfULL << 1)
 261 #define DTE_IRQ_REMAP_INTCTL    (2ULL << 60)
 262 #define DTE_IRQ_TABLE_LEN       (8ULL << 1)
 263 #define DTE_IRQ_REMAP_ENABLE    1ULL
 264
 265 #define PAGE_MODE_NONE    0x00
 266 #define PAGE_MODE_1_LEVEL 0x01
 267 #define PAGE_MODE_2_LEVEL 0x02
 268 #define PAGE_MODE_3_LEVEL 0x03
 269 #define PAGE_MODE_4_LEVEL 0x04
 270 #define PAGE_MODE_5_LEVEL 0x05
 271 #define PAGE_MODE_6_LEVEL 0x06
 272 #define PAGE_MODE_7_LEVEL 0x07
 273
 274 #define PM_LEVEL_SHIFT(x)       (12 + ((x) * 9))
 275 #define PM_LEVEL_SIZE(x)        (((x) < 6) ? \
 276                                   ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
 277                                    (0xffffffffffffffffULL))
 278 #define PM_LEVEL_INDEX(x, a)    (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
 279 #define PM_LEVEL_ENC(x)         (((x) << 9) & 0xe00ULL)
 280 #define PM_LEVEL_PDE(x, a)      ((a) | PM_LEVEL_ENC((x)) | \
 281                                  IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW)
 282 #define PM_PTE_LEVEL(pte)       (((pte) >> 9) & 0x7ULL)
 283
 284 #define PM_MAP_4k               0
 285 #define PM_ADDR_MASK            0x000ffffffffff000ULL
 286 #define PM_MAP_MASK(lvl)        (PM_ADDR_MASK & \
 287                                 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
 288 #define PM_ALIGNED(lvl, addr)   ((PM_MAP_MASK(lvl) & (addr)) == (addr))
 289
 290 /*
 291  * Returns the page table level to use for a given page size
 292  * Pagesize is expected to be a power-of-two
 293  */
 294 #define PAGE_SIZE_LEVEL(pagesize) \
 295                 ((__ffs(pagesize) - 12) / 9)
 296 /*
 297  * Returns the number of ptes to use for a given page size
 298  * Pagesize is expected to be a power-of-two
 299  */
 300 #define PAGE_SIZE_PTE_COUNT(pagesize) \
 301                 (1ULL << ((__ffs(pagesize) - 12) % 9))
 302
 303 /*
 304  * Aligns a given io-virtual address to a given page size
 305  * Pagesize is expected to be a power-of-two
 306  */
 307 #define PAGE_SIZE_ALIGN(address, pagesize) \
 308                 ((address) & ~((pagesize) - 1))
 309 /*
 310  * Creates an IOMMU PTE for an address and a given pagesize
 311  * The PTE has no permission bits set
 312  * Pagesize is expected to be a power-of-two larger than 4096
 313  */
 314 #define PAGE_SIZE_PTE(address, pagesize)                \
 315                 (((address) | ((pagesize) - 1)) &       \
 316                  (~(pagesize >> 1)) & PM_ADDR_MASK)
 317
 318 /*
 319  * Takes a PTE value with mode=0x07 and returns the page size it maps
 320  */
 321 #define PTE_PAGE_SIZE(pte) \
 322         (1ULL << (1 + ffz(((pte) | 0xfffULL))))
 323
 324 /*
 325  * Takes a page-table level and returns the default page-size for this level
 326  */
 327 #define PTE_LEVEL_PAGE_SIZE(level)                      \
 328         (1ULL << (12 + (9 * (level))))
 329
 330 /*
 331  * Bit value definition for I/O PTE fields
 332  */
 333 #define IOMMU_PTE_PR (1ULL << 0)
 334 #define IOMMU_PTE_U  (1ULL << 59)
 335 #define IOMMU_PTE_FC (1ULL << 60)
 336 #define IOMMU_PTE_IR (1ULL << 61)
 337 #define IOMMU_PTE_IW (1ULL << 62)
 338
 339 /*
 340  * Bit value definition for DTE fields
 341  */
 342 #define DTE_FLAG_V  (1ULL << 0)
 343 #define DTE_FLAG_TV (1ULL << 1)
 344 #define DTE_FLAG_IR (1ULL << 61)
 345 #define DTE_FLAG_IW (1ULL << 62)
 346
 347 #define DTE_FLAG_IOTLB  (1ULL << 32)
 348 #define DTE_FLAG_GV     (1ULL << 55)
 349 #define DTE_FLAG_MASK   (0x3ffULL << 32)
 350 #define DTE_GLX_SHIFT   (56)
 351 #define DTE_GLX_MASK    (3)
 352 #define DEV_DOMID_MASK  0xffffULL
 353
 354 #define DTE_GCR3_VAL_A(x)       (((x) >> 12) & 0x00007ULL)
 355 #define DTE_GCR3_VAL_B(x)       (((x) >> 15) & 0x0ffffULL)
 356 #define DTE_GCR3_VAL_C(x)       (((x) >> 31) & 0xfffffULL)
 357
 358 #define DTE_GCR3_INDEX_A        0
 359 #define DTE_GCR3_INDEX_B        1
 360 #define DTE_GCR3_INDEX_C        1
 361
 362 #define DTE_GCR3_SHIFT_A        58
 363 #define DTE_GCR3_SHIFT_B        16
 364 #define DTE_GCR3_SHIFT_C        43
 365
 366 #define GCR3_VALID              0x01ULL
 367
 368 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 369 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR)
 370 #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK))
 371 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
 372
 373 #define IOMMU_PROT_MASK 0x03
 374 #define IOMMU_PROT_IR 0x01
 375 #define IOMMU_PROT_IW 0x02
 376
 377 /* IOMMU capabilities */
 378 #define IOMMU_CAP_IOTLB   24
 379 #define IOMMU_CAP_NPCACHE 26
 380 #define IOMMU_CAP_EFR     27
 381
 382 /* IOMMU Feature Reporting Field (for IVHD type 10h */
 383 #define IOMMU_FEAT_XTSUP_SHIFT  0
 384 #define IOMMU_FEAT_GASUP_SHIFT  6
 385
 386 /* IOMMU Extended Feature Register (EFR) */
 387 #define IOMMU_EFR_XTSUP_SHIFT   2
 388 #define IOMMU_EFR_GASUP_SHIFT   7
 389
 390 #define MAX_DOMAIN_ID 65536
 391
 392 /* Protection domain flags */
 393 #define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
 394 #define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
 395                                               domain for an IOMMU */
 396 #define PD_PASSTHROUGH_MASK     (1UL << 2) /* domain has no page
 397                                               translation */
 398 #define PD_IOMMUV2_MASK         (1UL << 3) /* domain has gcr3 table */
 399
 400 extern bool amd_iommu_dump;
 401 #define DUMP_printk(format, arg...)                                     \
 402         do {                                                            \
 403                 if (amd_iommu_dump)                                             \
 404                         printk(KERN_INFO "AMD-Vi: " format, ## arg);    \
 405         } while(0);
 406
 407 /* global flag if IOMMUs cache non-present entries */
 408 extern bool amd_iommu_np_cache;
 409 /* Only true if all IOMMUs support device IOTLBs */
 410 extern bool amd_iommu_iotlb_sup;
 411
 412 #define MAX_IRQS_PER_TABLE      256
 413 #define IRQ_TABLE_ALIGNMENT     128
 414
 415 struct irq_remap_table {
 416         raw_spinlock_t lock;
 417         unsigned min_index;
 418         u32 *table;
 419 };
 420
 421 extern struct irq_remap_table **irq_lookup_table;
 422
 423 /* Interrupt remapping feature used? */
 424 extern bool amd_iommu_irq_remap;
 425
 426 /* kmem_cache to get tables with 128 byte alignement */
 427 extern struct kmem_cache *amd_iommu_irq_cache;
 428
 429 /*
 430  * Make iterating over all IOMMUs easier
 431  */
 432 #define for_each_iommu(iommu) \
 433         list_for_each_entry((iommu), &amd_iommu_list, list)
 434 #define for_each_iommu_safe(iommu, next) \
 435         list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
 436
 437 #define APERTURE_RANGE_SHIFT    27      /* 128 MB */
 438 #define APERTURE_RANGE_SIZE     (1ULL << APERTURE_RANGE_SHIFT)
 439 #define APERTURE_RANGE_PAGES    (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
 440 #define APERTURE_MAX_RANGES     32      /* allows 4GB of DMA address space */
 441 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
 442 #define APERTURE_PAGE_INDEX(a)  (((a) >> 21) & 0x3fULL)
 443
 444 /*
 445  * This struct is used to pass information about
 446  * incoming PPR faults around.
 447  */
 448 struct amd_iommu_fault {
 449         u64 address;    /* IO virtual address of the fault*/
 450         u32 pasid;      /* Address space identifier */
 451         u16 device_id;  /* Originating PCI device id */
 452         u16 tag;        /* PPR tag */
 453         u16 flags;      /* Fault flags */
 454
 455 };
 456
 457
 458 struct iommu_domain;
 459 struct irq_domain;
 460 struct amd_irte_ops;
 461
 462 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED      (1 << 0)
 463
 464 /*
 465  * This structure contains generic data for  IOMMU protection domains
 466  * independent of their use.
 467  */
 468 struct protection_domain {
 469         struct list_head list;  /* for list of all protection domains */
 470         struct list_head dev_list; /* List of all devices in this domain */
 471         struct iommu_domain domain; /* generic domain handle used by
 472                                        iommu core code */
 473         spinlock_t lock;        /* mostly used to lock the page table*/
 474         struct mutex api_lock;  /* protect page tables in the iommu-api path */
 475         u16 id;                 /* the domain id written to the device table */
 476         int mode;               /* paging mode (0-6 levels) */
 477         u64 *pt_root;           /* page table root pointer */
 478         int glx;                /* Number of levels for GCR3 table */
 479         u64 *gcr3_tbl;          /* Guest CR3 table */
 480         unsigned long flags;    /* flags to find out type of domain */
 481         bool updated;           /* complete domain flush required */
 482         unsigned dev_cnt;       /* devices assigned to this domain */
 483         unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
 484 };
 485
 486 /*
 487  * Structure where we save information about one hardware AMD IOMMU in the
 488  * system.
 489  */
 490 struct amd_iommu {
 491         struct list_head list;
 492
 493         /* Index within the IOMMU array */
 494         int index;
 495
 496         /* locks the accesses to the hardware */
 497         raw_spinlock_t lock;
 498
 499         /* Pointer to PCI device of this IOMMU */
 500         struct pci_dev *dev;
 501
 502         /* Cache pdev to root device for resume quirks */
 503         struct pci_dev *root_pdev;
 504
 505         /* physical address of MMIO space */
 506         u64 mmio_phys;
 507
 508         /* physical end address of MMIO space */
 509         u64 mmio_phys_end;
 510
 511         /* virtual address of MMIO space */
 512         u8 __iomem *mmio_base;
 513
 514         /* capabilities of that IOMMU read from ACPI */
 515         u32 cap;
 516
 517         /* flags read from acpi table */
 518         u8 acpi_flags;
 519
 520         /* Extended features */
 521         u64 features;
 522
 523         /* IOMMUv2 */
 524         bool is_iommu_v2;
 525
 526         /* PCI device id of the IOMMU device */
 527         u16 devid;
 528
 529         /*
 530          * Capability pointer. There could be more than one IOMMU per PCI
 531          * device function if there are more than one AMD IOMMU capability
 532          * pointers.
 533          */
 534         u16 cap_ptr;
 535
 536         /* pci domain of this IOMMU */
 537         u16 pci_seg;
 538
 539         /* start of exclusion range of that IOMMU */
 540         u64 exclusion_start;
 541         /* length of exclusion range of that IOMMU */
 542         u64 exclusion_length;
 543
 544         /* command buffer virtual address */
 545         u8 *cmd_buf;
 546         u32 cmd_buf_head;
 547         u32 cmd_buf_tail;
 548
 549         /* event buffer virtual address */
 550         u8 *evt_buf;
 551
 552         /* Base of the PPR log, if present */
 553         u8 *ppr_log;
 554
 555         /* Base of the GA log, if present */
 556         u8 *ga_log;
 557
 558         /* Tail of the GA log, if present */
 559         u8 *ga_log_tail;
 560
 561         /* true if interrupts for this IOMMU are already enabled */
 562         bool int_enabled;
 563
 564         /* if one, we need to send a completion wait command */
 565         bool need_sync;
 566
 567         /* Handle for IOMMU core code */
 568         struct iommu_device iommu;
 569
 570         /*
 571          * We can't rely on the BIOS to restore all values on reinit, so we
 572          * need to stash them
 573          */
 574
 575         /* The iommu BAR */
 576         u32 stored_addr_lo;
 577         u32 stored_addr_hi;
 578
 579         /*
 580          * Each iommu has 6 l1s, each of which is documented as having 0x12
 581          * registers
 582          */
 583         u32 stored_l1[6][0x12];
 584
 585         /* The l2 indirect registers */
 586         u32 stored_l2[0x83];
 587
 588         /* The maximum PC banks and counters/bank (PCSup=1) */
 589         u8 max_banks;
 590         u8 max_counters;
 591 #ifdef CONFIG_IRQ_REMAP
 592         struct irq_domain *ir_domain;
 593         struct irq_domain *msi_domain;
 594
 595         struct amd_irte_ops *irte_ops;
 596 #endif
 597
 598         u32 flags;
 599         volatile u64 __aligned(8) cmd_sem;
 600
 601 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
 602         /* DebugFS Info */
 603         struct dentry *debugfs;
 604 #endif
 605 };
 606
 607 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
 608 {
 609         struct iommu_device *iommu = dev_to_iommu_device(dev);
 610
 611         return container_of(iommu, struct amd_iommu, iommu);
 612 }
 613
 614 #define ACPIHID_UID_LEN 256
 615 #define ACPIHID_HID_LEN 9
 616
 617 struct acpihid_map_entry {
 618         struct list_head list;
 619         u8 uid[ACPIHID_UID_LEN];
 620         u8 hid[ACPIHID_HID_LEN];
 621         u16 devid;
 622         u16 root_devid;
 623         bool cmd_line;
 624         struct iommu_group *group;
 625 };
 626
 627 struct devid_map {
 628         struct list_head list;
 629         u8 id;
 630         u16 devid;
 631         bool cmd_line;
 632 };
 633
 634 /*
 635  * This struct contains device specific data for the IOMMU
 636  */
 637 struct iommu_dev_data {
 638         struct list_head list;            /* For domain->dev_list */
 639         struct llist_node dev_data_list;  /* For global dev_data_list */
 640         struct protection_domain *domain; /* Domain the device is bound to */
 641         u16 devid;                        /* PCI Device ID */
 642         u16 alias;                        /* Alias Device ID */
 643         bool iommu_v2;                    /* Device can make use of IOMMUv2 */
 644         bool passthrough;                 /* Device is identity mapped */
 645         struct {
 646                 bool enabled;
 647                 int qdep;
 648         } ats;                            /* ATS state */
 649         bool pri_tlp;                     /* PASID TLB required for
 650                                              PPR completions */
 651         u32 errata;                       /* Bitmap for errata to apply */
 652         bool use_vapic;                   /* Enable device to use vapic mode */
 653         bool defer_attach;
 654
 655         struct ratelimit_state rs;        /* Ratelimit IOPF messages */
 656 };
 657
 658 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
 659 extern struct list_head ioapic_map;
 660 extern struct list_head hpet_map;
 661 extern struct list_head acpihid_map;
 662
 663 /*
 664  * List with all IOMMUs in the system. This list is not locked because it is
 665  * only written and read at driver initialization or suspend time
 666  */
 667 extern struct list_head amd_iommu_list;
 668
 669 /*
 670  * Array with pointers to each IOMMU struct
 671  * The indices are referenced in the protection domains
 672  */
 673 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
 674
 675 /*
 676  * Declarations for the global list of all protection domains
 677  */
 678 extern spinlock_t amd_iommu_pd_lock;
 679 extern struct list_head amd_iommu_pd_list;
 680
 681 /*
 682  * Structure defining one entry in the device table
 683  */
 684 struct dev_table_entry {
 685         u64 data[4];
 686 };
 687
 688 /*
 689  * One entry for unity mappings parsed out of the ACPI table.
 690  */
 691 struct unity_map_entry {
 692         struct list_head list;
 693
 694         /* starting device id this entry is used for (including) */
 695         u16 devid_start;
 696         /* end device id this entry is used for (including) */
 697         u16 devid_end;
 698
 699         /* start address to unity map (including) */
 700         u64 address_start;
 701         /* end address to unity map (including) */
 702         u64 address_end;
 703
 704         /* required protection */
 705         int prot;
 706 };
 707
 708 /*
 709  * List of all unity mappings. It is not locked because as runtime it is only
 710  * read. It is created at ACPI table parsing time.
 711  */
 712 extern struct list_head amd_iommu_unity_map;
 713
 714 /*
 715  * Data structures for device handling
 716  */
 717
 718 /*
 719  * Device table used by hardware. Read and write accesses by software are
 720  * locked with the amd_iommu_pd_table lock.
 721  */
 722 extern struct dev_table_entry *amd_iommu_dev_table;
 723
 724 /*
 725  * Alias table to find requestor ids to device ids. Not locked because only
 726  * read on runtime.
 727  */
 728 extern u16 *amd_iommu_alias_table;
 729
 730 /*
 731  * Reverse lookup table to find the IOMMU which translates a specific device.
 732  */
 733 extern struct amd_iommu **amd_iommu_rlookup_table;
 734
 735 /* size of the dma_ops aperture as power of 2 */
 736 extern unsigned amd_iommu_aperture_order;
 737
 738 /* largest PCI device id we expect translation requests for */
 739 extern u16 amd_iommu_last_bdf;
 740
 741 /* allocation bitmap for domain ids */
 742 extern unsigned long *amd_iommu_pd_alloc_bitmap;
 743
 744 /*
 745  * If true, the addresses will be flushed on unmap time, not when
 746  * they are reused
 747  */
 748 extern bool amd_iommu_unmap_flush;
 749
 750 /* Smallest max PASID supported by any IOMMU in the system */
 751 extern u32 amd_iommu_max_pasid;
 752
 753 extern bool amd_iommu_v2_present;
 754
 755 extern bool amd_iommu_force_isolation;
 756
 757 /* Max levels of glxval supported */
 758 extern int amd_iommu_max_glx_val;
 759
 760 /*
 761  * This function flushes all internal caches of
 762  * the IOMMU used by this driver.
 763  */
 764 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
 765
 766 static inline int get_ioapic_devid(int id)
 767 {
 768         struct devid_map *entry;
 769
 770         list_for_each_entry(entry, &ioapic_map, list) {
 771                 if (entry->id == id)
 772                         return entry->devid;
 773         }
 774
 775         return -EINVAL;
 776 }
 777
 778 static inline int get_hpet_devid(int id)
 779 {
 780         struct devid_map *entry;
 781
 782         list_for_each_entry(entry, &hpet_map, list) {
 783                 if (entry->id == id)
 784                         return entry->devid;
 785         }
 786
 787         return -EINVAL;
 788 }
 789
 790 enum amd_iommu_intr_mode_type {
 791         AMD_IOMMU_GUEST_IR_LEGACY,
 792
 793         /* This mode is not visible to users. It is used when
 794          * we cannot fully enable vAPIC and fallback to only support
 795          * legacy interrupt remapping via 128-bit IRTE.
 796          */
 797         AMD_IOMMU_GUEST_IR_LEGACY_GA,
 798         AMD_IOMMU_GUEST_IR_VAPIC,
 799 };
 800
 801 #define AMD_IOMMU_GUEST_IR_GA(x)        (x == AMD_IOMMU_GUEST_IR_VAPIC || \
 802                                          x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
 803
 804 #define AMD_IOMMU_GUEST_IR_VAPIC(x)     (x == AMD_IOMMU_GUEST_IR_VAPIC)
 805
 806 union irte {
 807         u32 val;
 808         struct {
 809                 u32 valid       : 1,
 810                     no_fault    : 1,
 811                     int_type    : 3,
 812                     rq_eoi      : 1,
 813                     dm          : 1,
 814                     rsvd_1      : 1,
 815                     destination : 8,
 816                     vector      : 8,
 817                     rsvd_2      : 8;
 818         } fields;
 819 };
 820
 821 #define APICID_TO_IRTE_DEST_LO(x)    (x & 0xffffff)
 822 #define APICID_TO_IRTE_DEST_HI(x)    ((x >> 24) & 0xff)
 823
 824 union irte_ga_lo {
 825         u64 val;
 826
 827         /* For int remapping */
 828         struct {
 829                 u64 valid       : 1,
 830                     no_fault    : 1,
 831                     /* ------ */
 832                     int_type    : 3,
 833                     rq_eoi      : 1,
 834                     dm          : 1,
 835                     /* ------ */
 836                     guest_mode  : 1,
 837                     destination : 24,
 838                     ga_tag      : 32;
 839         } fields_remap;
 840
 841         /* For guest vAPIC */
 842         struct {
 843                 u64 valid       : 1,
 844                     no_fault    : 1,
 845                     /* ------ */
 846                     ga_log_intr : 1,
 847                     rsvd1       : 3,
 848                     is_run      : 1,
 849                     /* ------ */
 850                     guest_mode  : 1,
 851                     destination : 24,
 852                     ga_tag      : 32;
 853         } fields_vapic;
 854 };
 855
 856 union irte_ga_hi {
 857         u64 val;
 858         struct {
 859                 u64 vector      : 8,
 860                     rsvd_1      : 4,
 861                     ga_root_ptr : 40,
 862                     rsvd_2      : 4,
 863                     destination : 8;
 864         } fields;
 865 };
 866
 867 struct irte_ga {
 868         union irte_ga_lo lo;
 869         union irte_ga_hi hi;
 870 };
 871
 872 struct irq_2_irte {
 873         u16 devid; /* Device ID for IRTE table */
 874         u16 index; /* Index into IRTE table*/
 875 };
 876
 877 struct amd_ir_data {
 878         u32 cached_ga_tag;
 879         struct irq_2_irte irq_2_irte;
 880         struct msi_msg msi_entry;
 881         void *entry;    /* Pointer to union irte or struct irte_ga */
 882         void *ref;      /* Pointer to the actual irte */
 883 };
 884
 885 struct amd_irte_ops {
 886         void (*prepare)(void *, u32, u32, u8, u32, int);
 887         void (*activate)(void *, u16, u16);
 888         void (*deactivate)(void *, u16, u16);
 889         void (*set_affinity)(void *, u16, u16, u8, u32);
 890         void *(*get)(struct irq_remap_table *, int);
 891         void (*set_allocated)(struct irq_remap_table *, int);
 892         bool (*is_allocated)(struct irq_remap_table *, int);
 893         void (*clear_allocated)(struct irq_remap_table *, int);
 894 };
 895
 896 #ifdef CONFIG_IRQ_REMAP
 897 extern struct amd_irte_ops irte_32_ops;
 898 extern struct amd_irte_ops irte_128_ops;
 899 #endif
 900
 901 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */