1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Jerome Brunet <jbrunet@baylibre.com>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/module.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/irqchip.h>
17 #include <linux/of_address.h>
20 #define MAX_INPUT_MUX 256
22 #define REG_EDGE_POL 0x00
23 #define REG_PIN_03_SEL 0x04
24 #define REG_PIN_47_SEL 0x08
25 #define REG_FILTER_SEL 0x0c
27 #define REG_EDGE_POL_MASK(x) (BIT(x) | BIT(16 + (x)))
28 #define REG_EDGE_POL_EDGE(x) BIT(x)
29 #define REG_EDGE_POL_LOW(x) BIT(16 + (x))
30 #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
31 #define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
33 struct meson_gpio_irq_params
{
34 unsigned int nr_hwirq
;
37 static const struct meson_gpio_irq_params meson8_params
= {
41 static const struct meson_gpio_irq_params meson8b_params
= {
45 static const struct meson_gpio_irq_params gxbb_params
= {
49 static const struct meson_gpio_irq_params gxl_params
= {
53 static const struct meson_gpio_irq_params axg_params
= {
57 static const struct of_device_id meson_irq_gpio_matches
[] = {
58 { .compatible
= "amlogic,meson8-gpio-intc", .data
= &meson8_params
},
59 { .compatible
= "amlogic,meson8b-gpio-intc", .data
= &meson8b_params
},
60 { .compatible
= "amlogic,meson-gxbb-gpio-intc", .data
= &gxbb_params
},
61 { .compatible
= "amlogic,meson-gxl-gpio-intc", .data
= &gxl_params
},
62 { .compatible
= "amlogic,meson-axg-gpio-intc", .data
= &axg_params
},
66 struct meson_gpio_irq_controller
{
67 unsigned int nr_hwirq
;
69 u32 channel_irqs
[NUM_CHANNEL
];
70 DECLARE_BITMAP(channel_map
, NUM_CHANNEL
);
74 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller
*ctl
,
75 unsigned int reg
, u32 mask
, u32 val
)
79 tmp
= readl_relaxed(ctl
->base
+ reg
);
82 writel_relaxed(tmp
, ctl
->base
+ reg
);
85 static unsigned int meson_gpio_irq_channel_to_reg(unsigned int channel
)
87 return (channel
< 4) ? REG_PIN_03_SEL
: REG_PIN_47_SEL
;
91 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller
*ctl
,
95 unsigned int reg
, idx
;
97 spin_lock(&ctl
->lock
);
99 /* Find a free channel */
100 idx
= find_first_zero_bit(ctl
->channel_map
, NUM_CHANNEL
);
101 if (idx
>= NUM_CHANNEL
) {
102 spin_unlock(&ctl
->lock
);
103 pr_err("No channel available\n");
107 /* Mark the channel as used */
108 set_bit(idx
, ctl
->channel_map
);
111 * Setup the mux of the channel to route the signal of the pad
112 * to the appropriate input of the GIC
114 reg
= meson_gpio_irq_channel_to_reg(idx
);
115 meson_gpio_irq_update_bits(ctl
, reg
,
116 0xff << REG_PIN_SEL_SHIFT(idx
),
117 hwirq
<< REG_PIN_SEL_SHIFT(idx
));
120 * Get the hwirq number assigned to this channel through
121 * a pointer the channel_irq table. The added benifit of this
122 * method is that we can also retrieve the channel index with
123 * it, using the table base.
125 *channel_hwirq
= &(ctl
->channel_irqs
[idx
]);
127 spin_unlock(&ctl
->lock
);
129 pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
130 hwirq
, idx
, **channel_hwirq
);
136 meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller
*ctl
,
139 return channel_hwirq
- ctl
->channel_irqs
;
143 meson_gpio_irq_release_channel(struct meson_gpio_irq_controller
*ctl
,
148 idx
= meson_gpio_irq_get_channel_idx(ctl
, channel_hwirq
);
149 clear_bit(idx
, ctl
->channel_map
);
152 static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller
*ctl
,
159 idx
= meson_gpio_irq_get_channel_idx(ctl
, channel_hwirq
);
162 * The controller has a filter block to operate in either LEVEL or
163 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
164 * EDGE_FALLING support (which the GIC does not support), the filter
165 * block is also able to invert the input signal it gets before
166 * providing it to the GIC.
168 type
&= IRQ_TYPE_SENSE_MASK
;
170 if (type
== IRQ_TYPE_EDGE_BOTH
)
173 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
174 val
|= REG_EDGE_POL_EDGE(idx
);
176 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_EDGE_FALLING
))
177 val
|= REG_EDGE_POL_LOW(idx
);
179 spin_lock(&ctl
->lock
);
181 meson_gpio_irq_update_bits(ctl
, REG_EDGE_POL
,
182 REG_EDGE_POL_MASK(idx
), val
);
184 spin_unlock(&ctl
->lock
);
189 static unsigned int meson_gpio_irq_type_output(unsigned int type
)
191 unsigned int sense
= type
& IRQ_TYPE_SENSE_MASK
;
193 type
&= ~IRQ_TYPE_SENSE_MASK
;
196 * The polarity of the signal provided to the GIC should always
199 if (sense
& (IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
))
200 type
|= IRQ_TYPE_LEVEL_HIGH
;
201 else if (sense
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
202 type
|= IRQ_TYPE_EDGE_RISING
;
207 static int meson_gpio_irq_set_type(struct irq_data
*data
, unsigned int type
)
209 struct meson_gpio_irq_controller
*ctl
= data
->domain
->host_data
;
210 u32
*channel_hwirq
= irq_data_get_irq_chip_data(data
);
213 ret
= meson_gpio_irq_type_setup(ctl
, type
, channel_hwirq
);
217 return irq_chip_set_type_parent(data
,
218 meson_gpio_irq_type_output(type
));
221 static struct irq_chip meson_gpio_irq_chip
= {
222 .name
= "meson-gpio-irqchip",
223 .irq_mask
= irq_chip_mask_parent
,
224 .irq_unmask
= irq_chip_unmask_parent
,
225 .irq_eoi
= irq_chip_eoi_parent
,
226 .irq_set_type
= meson_gpio_irq_set_type
,
227 .irq_retrigger
= irq_chip_retrigger_hierarchy
,
229 .irq_set_affinity
= irq_chip_set_affinity_parent
,
231 .flags
= IRQCHIP_SET_TYPE_MASKED
,
234 static int meson_gpio_irq_domain_translate(struct irq_domain
*domain
,
235 struct irq_fwspec
*fwspec
,
236 unsigned long *hwirq
,
239 if (is_of_node(fwspec
->fwnode
) && fwspec
->param_count
== 2) {
240 *hwirq
= fwspec
->param
[0];
241 *type
= fwspec
->param
[1];
248 static int meson_gpio_irq_allocate_gic_irq(struct irq_domain
*domain
,
253 struct irq_fwspec fwspec
;
255 fwspec
.fwnode
= domain
->parent
->fwnode
;
256 fwspec
.param_count
= 3;
257 fwspec
.param
[0] = 0; /* SPI */
258 fwspec
.param
[1] = hwirq
;
259 fwspec
.param
[2] = meson_gpio_irq_type_output(type
);
261 return irq_domain_alloc_irqs_parent(domain
, virq
, 1, &fwspec
);
264 static int meson_gpio_irq_domain_alloc(struct irq_domain
*domain
,
266 unsigned int nr_irqs
,
269 struct irq_fwspec
*fwspec
= data
;
270 struct meson_gpio_irq_controller
*ctl
= domain
->host_data
;
276 if (WARN_ON(nr_irqs
!= 1))
279 ret
= meson_gpio_irq_domain_translate(domain
, fwspec
, &hwirq
, &type
);
283 ret
= meson_gpio_irq_request_channel(ctl
, hwirq
, &channel_hwirq
);
287 ret
= meson_gpio_irq_allocate_gic_irq(domain
, virq
,
288 *channel_hwirq
, type
);
290 pr_err("failed to allocate gic irq %u\n", *channel_hwirq
);
291 meson_gpio_irq_release_channel(ctl
, channel_hwirq
);
295 irq_domain_set_hwirq_and_chip(domain
, virq
, hwirq
,
296 &meson_gpio_irq_chip
, channel_hwirq
);
301 static void meson_gpio_irq_domain_free(struct irq_domain
*domain
,
303 unsigned int nr_irqs
)
305 struct meson_gpio_irq_controller
*ctl
= domain
->host_data
;
306 struct irq_data
*irq_data
;
309 if (WARN_ON(nr_irqs
!= 1))
312 irq_domain_free_irqs_parent(domain
, virq
, 1);
314 irq_data
= irq_domain_get_irq_data(domain
, virq
);
315 channel_hwirq
= irq_data_get_irq_chip_data(irq_data
);
317 meson_gpio_irq_release_channel(ctl
, channel_hwirq
);
320 static const struct irq_domain_ops meson_gpio_irq_domain_ops
= {
321 .alloc
= meson_gpio_irq_domain_alloc
,
322 .free
= meson_gpio_irq_domain_free
,
323 .translate
= meson_gpio_irq_domain_translate
,
326 static int __init
meson_gpio_irq_parse_dt(struct device_node
*node
,
327 struct meson_gpio_irq_controller
*ctl
)
329 const struct of_device_id
*match
;
330 const struct meson_gpio_irq_params
*params
;
333 match
= of_match_node(meson_irq_gpio_matches
, node
);
337 params
= match
->data
;
338 ctl
->nr_hwirq
= params
->nr_hwirq
;
340 ret
= of_property_read_variable_u32_array(node
,
341 "amlogic,channel-interrupts",
346 pr_err("can't get %d channel interrupts\n", NUM_CHANNEL
);
353 static int __init
meson_gpio_irq_of_init(struct device_node
*node
,
354 struct device_node
*parent
)
356 struct irq_domain
*domain
, *parent_domain
;
357 struct meson_gpio_irq_controller
*ctl
;
361 pr_err("missing parent interrupt node\n");
365 parent_domain
= irq_find_host(parent
);
366 if (!parent_domain
) {
367 pr_err("unable to obtain parent domain\n");
371 ctl
= kzalloc(sizeof(*ctl
), GFP_KERNEL
);
375 spin_lock_init(&ctl
->lock
);
377 ctl
->base
= of_iomap(node
, 0);
383 ret
= meson_gpio_irq_parse_dt(node
, ctl
);
385 goto free_channel_irqs
;
387 domain
= irq_domain_create_hierarchy(parent_domain
, 0, ctl
->nr_hwirq
,
388 of_node_to_fwnode(node
),
389 &meson_gpio_irq_domain_ops
,
392 pr_err("failed to add domain\n");
394 goto free_channel_irqs
;
397 pr_info("%d to %d gpio interrupt mux initialized\n",
398 ctl
->nr_hwirq
, NUM_CHANNEL
);
410 IRQCHIP_DECLARE(meson_gpio_intc
, "amlogic,meson-gpio-intc",
411 meson_gpio_irq_of_init
);