1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * ngene.h: nGene PCIe bridge driver
5 * Copyright (C) 2005-2007 Micronas
11 #include <linux/types.h>
12 #include <linux/sched.h>
13 #include <linux/interrupt.h>
14 #include <linux/i2c.h>
16 #include <linux/scatterlist.h>
18 #include <linux/dvb/frontend.h>
20 #include <media/dmxdev.h>
21 #include <media/dvbdev.h>
22 #include <media/dvb_demux.h>
23 #include <media/dvb_ca_en50221.h>
24 #include <media/dvb_frontend.h>
25 #include <media/dvb_ringbuffer.h>
26 #include <media/dvb_net.h>
29 #define DEVICE_NAME "ngene"
31 #define NGENE_VID 0x18c3
32 #define NGENE_PID 0x0720
35 #define VIDEO_CAP_AVC 128
36 #define VIDEO_CAP_H264 128
37 #define VIDEO_CAP_VC1 256
38 #define VIDEO_CAP_WMV9 256
39 #define VIDEO_CAP_MPEG4 512
42 #define DEMOD_TYPE_STV090X 0
43 #define DEMOD_TYPE_DRXK 1
44 #define DEMOD_TYPE_STV0367 2
46 #define DEMOD_TYPE_XO2 32
47 #define DEMOD_TYPE_STV0910 (DEMOD_TYPE_XO2 + 0)
48 #define DEMOD_TYPE_SONY_CT2 (DEMOD_TYPE_XO2 + 1)
49 #define DEMOD_TYPE_SONY_ISDBT (DEMOD_TYPE_XO2 + 2)
50 #define DEMOD_TYPE_SONY_C2T2 (DEMOD_TYPE_XO2 + 3)
51 #define DEMOD_TYPE_ST_ATSC (DEMOD_TYPE_XO2 + 4)
52 #define DEMOD_TYPE_SONY_C2T2I (DEMOD_TYPE_XO2 + 5)
54 #define NGENE_XO2_TYPE_NONE 0
55 #define NGENE_XO2_TYPE_DUOFLEX 1
56 #define NGENE_XO2_TYPE_CI 2
59 STREAM_VIDEOIN1
= 0, /* ITU656 or TS Input */
61 STREAM_AUDIOIN1
, /* I2S or SPI Input */
68 SMODE_AUDIO_SPDIF
= 0x20,
70 SMODE_TRANSPORT_STREAM
= 0x08,
71 SMODE_AUDIO_CAPTURE
= 0x04,
72 SMODE_VBI_CAPTURE
= 0x02,
73 SMODE_VIDEO_CAPTURE
= 0x01
76 enum STREAM_FLAG_BITS
{
77 SFLAG_CHROMA_FORMAT_2COMP
= 0x01, /* Chroma Format : 2's complement */
78 SFLAG_CHROMA_FORMAT_OFFSET
= 0x00, /* Chroma Format : Binary offset */
79 SFLAG_ORDER_LUMA_CHROMA
= 0x02, /* Byte order: Y,Cb,Y,Cr */
80 SFLAG_ORDER_CHROMA_LUMA
= 0x00, /* Byte order: Cb,Y,Cr,Y */
81 SFLAG_COLORBAR
= 0x04, /* Select colorbar */
84 #define PROGRAM_ROM 0x0000
85 #define PROGRAM_SRAM 0x1000
86 #define PERIPHERALS0 0x8000
87 #define PERIPHERALS1 0x9000
88 #define SHARED_BUFFER 0xC000
90 #define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
91 #define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
92 #define NGENE_COMMAND (SHARED_BUFFER+0x0200)
93 #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
94 #define NGENE_STATUS (SHARED_BUFFER+0x0208)
95 #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
96 #define NGENE_EVENT (SHARED_BUFFER+0x0210)
97 #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
98 #define VARIABLES (SHARED_BUFFER+0x0210)
100 #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
101 #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
102 #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
104 #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
105 #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
106 #define EEPROM_AREA (SHARED_BUFFER+0x0A00)
108 #define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
109 #define SG_VBI_1 (SHARED_BUFFER+0x0B00)
110 #define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
111 #define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
112 #define SG_VBI_2 (SHARED_BUFFER+0x0C80)
113 #define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
114 #define SG_V_OUT (SHARED_BUFFER+0x0D80)
115 #define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
117 #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
118 #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
119 #define DATA_A_OUT (SHARED_BUFFER+0x0F80)
120 #define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
121 #define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
122 #define DATA_V_OUT (SHARED_BUFFER+0x3000)
124 #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
126 #define TIMESTAMPS 0xA000
127 #define SCRATCHPAD 0xA080
128 #define FORCE_INT 0xA088
129 #define FORCE_NMI 0xA090
130 #define INT_STATUS 0xA0A0
132 #define DEV_VER 0x9004
134 #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
142 } __attribute__ ((__packed__
));
144 struct SHARED_MEMORY
{
157 u8 pad1
[0xc260 - 0xc218];
164 u8 pad2
[0xd000 - 0xc268];
166 } __attribute__ ((__packed__
));
168 struct BUFFER_STREAM_RESULTS
{
169 u32 Clock
; /* Stream time in 100ns units */
170 u16 RemainingLines
; /* Remaining lines in this field.
171 0 for complete field */
172 u8 FieldCount
; /* Video field number */
173 u8 Flags
; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
175 u16 BlockCount
; /* Audio block count (unused) */
178 } __attribute__ ((__packed__
));
180 struct HW_SCATTER_GATHER_ELEMENT
{
184 } __attribute__ ((__packed__
));
186 struct BUFFER_HEADER
{
188 struct BUFFER_STREAM_RESULTS SR
;
190 u32 Number_of_entries_1
;
192 u64 Address_of_first_entry_1
;
194 u32 Number_of_entries_2
;
196 u64 Address_of_first_entry_2
;
197 } __attribute__ ((__packed__
));
199 struct EVENT_BUFFER
{
206 } __attribute__ ((__packed__
));
208 /* Firmware commands. */
212 CMD_FWLOAD_PREPARE
= 0x01,
213 CMD_FWLOAD_FINISH
= 0x02,
215 CMD_I2C_WRITE
= 0x04,
217 CMD_I2C_WRITE_NOSTOP
= 0x05,
218 CMD_I2C_CONTINUE_WRITE
= 0x06,
219 CMD_I2C_CONTINUE_WRITE_NOSTOP
= 0x07,
221 CMD_DEBUG_OUTPUT
= 0x09,
224 CMD_CONFIGURE_BUFFER
= 0x11,
225 CMD_CONFIGURE_FREE_BUFFER
= 0x12,
228 CMD_SPI_WRITE
= 0x14,
231 CMD_MEM_WRITE
= 0x21,
233 CMD_SFR_WRITE
= 0x23,
234 CMD_IRAM_READ
= 0x24,
235 CMD_IRAM_WRITE
= 0x25,
236 CMD_SET_GPIO_PIN
= 0x26,
237 CMD_SET_GPIO_INT
= 0x27,
238 CMD_CONFIGURE_UART
= 0x28,
239 CMD_WRITE_UART
= 0x29,
251 } __attribute__ ((__packed__
));
253 struct FW_I2C_WRITE
{
254 struct FW_HEADER hdr
;
257 } __attribute__ ((__packed__
));
259 struct FW_I2C_CONTINUE_WRITE
{
260 struct FW_HEADER hdr
;
262 } __attribute__ ((__packed__
));
265 struct FW_HEADER hdr
;
267 u8 Data
[252]; /* followed by two bytes of read data count */
268 } __attribute__ ((__packed__
));
270 struct FW_SPI_WRITE
{
271 struct FW_HEADER hdr
;
274 } __attribute__ ((__packed__
));
277 struct FW_HEADER hdr
;
279 u8 Data
[252]; /* followed by two bytes of read data count */
280 } __attribute__ ((__packed__
));
282 struct FW_FWLOAD_PREPARE
{
283 struct FW_HEADER hdr
;
284 } __attribute__ ((__packed__
));
286 struct FW_FWLOAD_FINISH
{
287 struct FW_HEADER hdr
;
288 u16 Address
; /* address of final block */
290 } __attribute__ ((__packed__
));
293 * Meaning of FW_STREAM_CONTROL::Mode bits:
294 * Bit 7: Loopback PEXin to PEXout using TVOut channel
296 * Bit 5: Audio select; 0=I2S, 1=SPDIF
298 * Bit 3: Enable transport stream
299 * Bit 2: Enable audio capture
300 * Bit 1: Enable ITU-Video VBI capture
301 * Bit 0: Enable ITU-Video capture
303 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
304 * Bit 7: continuous capture
305 * Bit 6: capture one field
306 * Bit 5: capture one frame
308 * Bit 3: starting field; 0=odd, 1=even
309 * Bit 2: sample size; 0=8-bit, 1=10-bit
310 * Bit 1: data format; 0=UYVY, 1=YUY2
311 * Bit 0: resets buffer pointers
315 SMODE_LOOPBACK
= 0x80,
317 _SMODE_AUDIO_SPDIF
= 0x20,
318 _SMODE_AVSYNC
= 0x10,
319 _SMODE_TRANSPORT_STREAM
= 0x08,
320 _SMODE_AUDIO_CAPTURE
= 0x04,
321 _SMODE_VBI_CAPTURE
= 0x02,
322 _SMODE_VIDEO_CAPTURE
= 0x01
326 /* Meaning of FW_STREAM_CONTROL::Stream bits:
327 * Bit 3: Audio sample count: 0 = relative, 1 = absolute
328 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
329 * Bits 1-0: stream select, UVI1, UVI2, TVOUT
332 struct FW_STREAM_CONTROL
{
333 struct FW_HEADER hdr
;
334 u8 Stream
; /* Stream number (UVI1, UVI2, TVOUT) */
335 u8 Control
; /* Value written to UVI1_CTL */
336 u8 Mode
; /* Controls clock source */
337 u8 SetupDataLen
; /* Length of setup data, MSB=1 write
339 u16 CaptureBlockCount
; /* Blocks (a 256 Bytes) to capture per buffer
341 u64 Buffer_Address
; /* Address of first buffer header */
342 u16 BytesPerVideoLine
;
343 u16 MaxLinesPerField
;
344 u16 MinLinesPerField
;
347 u16 MaxVBILinesPerField
;
348 u16 MinVBILinesPerField
;
349 u16 SetupDataAddr
; /* ngene relative address of setup data */
350 u8 SetupData
[32]; /* setup data */
351 } __attribute__((__packed__
));
353 #define AUDIO_BLOCK_SIZE 256
354 #define TS_BLOCK_SIZE 256
357 struct FW_HEADER hdr
;
359 } __attribute__ ((__packed__
));
361 struct FW_MEM_WRITE
{
362 struct FW_HEADER hdr
;
365 } __attribute__ ((__packed__
));
367 struct FW_SFR_IRAM_READ
{
368 struct FW_HEADER hdr
;
370 } __attribute__ ((__packed__
));
372 struct FW_SFR_IRAM_WRITE
{
373 struct FW_HEADER hdr
;
376 } __attribute__ ((__packed__
));
378 struct FW_SET_GPIO_PIN
{
379 struct FW_HEADER hdr
;
381 } __attribute__ ((__packed__
));
383 struct FW_SET_GPIO_INT
{
384 struct FW_HEADER hdr
;
386 } __attribute__ ((__packed__
));
388 struct FW_SET_DEBUGMODE
{
389 struct FW_HEADER hdr
;
391 } __attribute__ ((__packed__
));
393 struct FW_CONFIGURE_BUFFERS
{
394 struct FW_HEADER hdr
;
396 } __attribute__ ((__packed__
));
398 enum _BUFFER_CONFIGS
{
399 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
400 BUFFER_CONFIG_4422
= 0,
401 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
402 BUFFER_CONFIG_3333
= 1,
403 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
404 BUFFER_CONFIG_8022
= 2,
405 BUFFER_CONFIG_FW17
= 255, /* Use new FW 17 command */
408 struct FW_CONFIGURE_FREE_BUFFERS
{
409 struct FW_HEADER hdr
;
411 u8 UVI1_BufferLength
;
412 u8 UVI2_BufferLength
;
414 u8 AUD1_BufferLength
;
415 u8 AUD2_BufferLength
;
418 } __attribute__ ((__packed__
));
420 struct FW_CONFIGURE_UART
{
421 struct FW_HEADER hdr
;
423 } __attribute__ ((__packed__
));
426 _UART_BAUDRATE_19200
= 0,
427 _UART_BAUDRATE_9600
= 1,
428 _UART_BAUDRATE_4800
= 2,
429 _UART_BAUDRATE_2400
= 3,
430 _UART_RX_ENABLE
= 0x40,
431 _UART_TX_ENABLE
= 0x80,
434 struct FW_WRITE_UART
{
435 struct FW_HEADER hdr
;
437 } __attribute__ ((__packed__
));
440 struct ngene_command
{
446 struct FW_HEADER hdr
;
447 struct FW_I2C_WRITE I2CWrite
;
448 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite
;
449 struct FW_I2C_READ I2CRead
;
450 struct FW_STREAM_CONTROL StreamControl
;
451 struct FW_FWLOAD_PREPARE FWLoadPrepare
;
452 struct FW_FWLOAD_FINISH FWLoadFinish
;
453 struct FW_MEM_READ MemoryRead
;
454 struct FW_MEM_WRITE MemoryWrite
;
455 struct FW_SFR_IRAM_READ SfrIramRead
;
456 struct FW_SFR_IRAM_WRITE SfrIramWrite
;
457 struct FW_SPI_WRITE SPIWrite
;
458 struct FW_SPI_READ SPIRead
;
459 struct FW_SET_GPIO_PIN SetGpioPin
;
460 struct FW_SET_GPIO_INT SetGpioInt
;
461 struct FW_SET_DEBUGMODE SetDebugMode
;
462 struct FW_CONFIGURE_BUFFERS ConfigureBuffers
;
463 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers
;
464 struct FW_CONFIGURE_UART ConfigureUart
;
465 struct FW_WRITE_UART WriteUart
;
467 } __attribute__ ((__packed__
));
469 #define NGENE_INTERFACE_VERSION 0x103
470 #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
471 #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
472 #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
473 #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
474 #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
475 Max: (1920x1080i60) */
477 #define OVERFLOW_BUFFER_SIZE (8192)
479 #define RING_SIZE_VIDEO 4
480 #define RING_SIZE_AUDIO 8
481 #define RING_SIZE_TS 8
483 #define NUM_SCATTER_GATHER_ENTRIES 8
485 #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
486 RING_SIZE_VIDEO * 2) + \
487 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
488 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
489 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
490 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
491 (RING_SIZE_TS * PAGE_SIZE * 4) + \
492 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
494 #define EVENT_QUEUE_SIZE 16
496 /* Gathers the current state of a single channel. */
498 struct SBufferHeader
{
499 struct BUFFER_HEADER ngeneBuffer
; /* Physical descriptor */
500 struct SBufferHeader
*Next
;
502 struct HW_SCATTER_GATHER_ELEMENT
*scList1
;
504 struct HW_SCATTER_GATHER_ELEMENT
*scList2
;
507 /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
508 #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
524 struct SRingBufferDescriptor
{
525 struct SBufferHeader
*Head
; /* Points to first buffer in ring buffer
527 u64 PAHead
; /* Physical address of first buffer */
528 u32 MemSize
; /* Memory size of allocated ring buffers
529 (needed for freeing) */
530 u32 NumBuffers
; /* Number of buffers in the ring */
531 u32 Buffer1Length
; /* Allocated length of Buffer 1 */
532 u32 Buffer2Length
; /* Allocated length of Buffer 2 */
533 void *SCListMem
; /* Memory to hold scatter gather lists for this
535 u64 PASCListMem
; /* Physical address .. */
536 u32 SCListMemSize
; /* Size of this memory */
539 enum STREAMMODEFLAGS
{
540 StreamMode_NONE
= 0, /* Stream not used */
541 StreamMode_ANALOG
= 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
542 StreamMode_TSIN
= 2, /* Transport stream input (all) */
543 StreamMode_HDTV
= 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
545 StreamMode_TSOUT
= 8, /* Transport stream output (only stream 3) */
549 enum BufferExchangeFlags
{
550 BEF_EVEN_FIELD
= 0x00000001,
551 BEF_CONTINUATION
= 0x00000002,
552 BEF_MORE_DATA
= 0x00000004,
553 BEF_OVERFLOW
= 0x00000008,
554 DF_SWAP32
= 0x00010000,
557 typedef void *(IBufferExchange
)(void *, void *, u32
, u32
, u32
);
559 struct MICI_STREAMINFO
{
560 IBufferExchange
*pExchange
;
561 IBufferExchange
*pExchangeVBI
; /* Secondary (VBI, ancillary) */
567 u16 nBytesPerLineVideo
;
569 u16 nBytesPerLineVBI
;
570 u32 CaptureLength
; /* Used for audio and transport stream */
573 /****************************************************************************/
574 /* STRUCTS ******************************************************************/
575 /****************************************************************************/
577 /* sound hardware definition */
578 #define MIXER_ADDR_TVTUNER 0
579 #define MIXER_ADDR_LAST 0
581 struct ngene_channel
;
583 /*struct sound chip*/
586 struct ngene_channel
*chan
;
587 struct snd_card
*card
;
589 struct snd_pcm_substream
*substream
;
593 spinlock_t mixer_lock
;
595 int mixer_volume
[MIXER_ADDR_LAST
+ 1][2];
596 int capture_source
[MIXER_ADDR_LAST
+ 1][2];
599 struct ngene_channel
{
600 struct device device
;
601 struct i2c_adapter i2c_adapter
;
602 struct i2c_client
*i2c_client
[1];
612 int (*gate_ctrl
)(struct dvb_frontend
*, int);
614 struct dvb_frontend
*fe
;
615 struct dvb_frontend
*fe2
;
616 struct dmxdev dmxdev
;
617 struct dvb_demux demux
;
618 struct dvb_net dvbnet
;
619 struct dmx_frontend hw_frontend
;
620 struct dmx_frontend mem_frontend
;
622 struct video_device
*v4l_dev
;
623 struct dvb_device
*ci_dev
;
624 struct tasklet_struct demux_tasklet
;
626 struct SBufferHeader
*nextBuffer
;
628 enum HWSTATE HWState
;
632 IBufferExchange
*pBufferExchange
;
633 IBufferExchange
*pBufferExchange2
;
635 spinlock_t state_lock
;
639 u16 nBytesPerVBILine
;
643 struct SRingBufferDescriptor RingBuffer
;
644 struct SRingBufferDescriptor TSRingBuffer
;
645 struct SRingBufferDescriptor TSIdleBuffer
;
652 int (*set_tone
)(struct dvb_frontend
*, enum fe_sec_tone_mode
);
655 /* stuff from analog driver */
658 struct mychip
*mychip
;
659 struct snd_card
*soundcard
;
664 int soundbuffisallocated
;
671 struct ngene_tvnorm
*tvnorms
;
683 struct device device
;
684 struct i2c_adapter i2c_adapter
;
687 struct dvb_ca_en50221
*en
;
692 typedef void (rx_cb_t
)(struct ngene
*, u32
, u8
);
693 typedef void (tx_cb_t
)(struct ngene
*, u32
);
697 struct pci_dev
*pci_dev
;
698 unsigned char __iomem
*iomem
;
700 /*struct i2c_adapter i2c_adapter;*/
703 u32 fw_interface_version
;
706 bool cmd_timeout_workaround
;
710 void *OverflowBuffer
;
711 dma_addr_t PAOverflowBuffer
;
712 void *FWInterfaceBuffer
;
713 dma_addr_t PAFWInterfaceBuffer
;
717 struct EVENT_BUFFER EventQueue
[EVENT_QUEUE_SIZE
];
718 int EventQueueOverflowCount
;
719 int EventQueueOverflowFlag
;
720 struct tasklet_struct event_tasklet
;
721 struct EVENT_BUFFER
*EventBuffer
;
722 int EventQueueWriteIndex
;
723 int EventQueueReadIndex
;
725 wait_queue_head_t cmd_wq
;
727 struct mutex cmd_mutex
;
728 struct mutex stream_mutex
;
729 struct semaphore pll_mutex
;
730 struct mutex i2c_switch_mutex
;
731 int i2c_current_channel
;
735 struct dvb_adapter adapter
[MAX_STREAM
];
736 struct dvb_adapter
*first_adapter
; /* "one_adapter" modprobe opt */
737 struct ngene_channel channel
[MAX_STREAM
];
739 struct ngene_info
*card_info
;
741 tx_cb_t
*TxEventNotify
;
742 rx_cb_t
*RxEventNotify
;
744 wait_queue_head_t tx_wq
;
745 wait_queue_head_t rx_wq
;
746 #define UART_RBUF_LEN 4096
747 u8 uart_rbuf
[UART_RBUF_LEN
];
748 int uart_rp
, uart_wp
;
750 #define TS_FILLER 0x6f
753 #define TSOUT_BUF_SIZE (512*188*8)
754 struct dvb_ringbuffer tsout_rbuf
;
757 #define TSIN_BUF_SIZE (512*188*8)
758 struct dvb_ringbuffer tsin_rbuf
;
761 #define AIN_BUF_SIZE (128*1024)
762 struct dvb_ringbuffer ain_rbuf
;
766 #define VIN_BUF_SIZE (4*1920*1080)
767 struct dvb_ringbuffer vin_rbuf
;
769 unsigned long exp_val
;
778 #define NGENE_TERRATEC 1
779 #define NGENE_SIDEWINDER 2
780 #define NGENE_RACER 3
781 #define NGENE_VIPER 4
782 #define NGENE_PYTHON 5
783 #define NGENE_VBOX_V1 6
784 #define NGENE_VBOX_V2 7
790 int io_type
[MAX_STREAM
];
791 #define NGENE_IO_NONE 0
792 #define NGENE_IO_TV 1
793 #define NGENE_IO_HDTV 2
794 #define NGENE_IO_TSIN 4
795 #define NGENE_IO_TSOUT 8
796 #define NGENE_IO_AIN 16
799 void *tuner_config
[4];
801 int (*demod_attach
[4])(struct ngene_channel
*);
802 int (*tuner_attach
[4])(struct ngene_channel
*);
813 int (*gate_ctrl
)(struct dvb_frontend
*, int);
814 int (*switch_ctrl
)(struct ngene_channel
*, int, int);
818 /* Provided by ngene-core.c */
819 int ngene_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
);
820 void ngene_remove(struct pci_dev
*pdev
);
821 void ngene_shutdown(struct pci_dev
*pdev
);
822 int ngene_command(struct ngene
*dev
, struct ngene_command
*com
);
823 int ngene_command_gpio_set(struct ngene
*dev
, u8 select
, u8 level
);
824 void set_transfer(struct ngene_channel
*chan
, int state
);
825 void FillTSBuffer(void *Buffer
, int Length
, u32 Flags
);
827 /* Provided by ngene-cards.c */
828 int ngene_port_has_cxd2099(struct i2c_adapter
*i2c
, u8
*type
);
830 /* Provided by ngene-i2c.c */
831 int ngene_i2c_init(struct ngene
*dev
, int dev_nr
);
833 /* Provided by ngene-dvb.c */
834 extern struct dvb_device ngene_dvbdev_ci
;
835 void *tsout_exchange(void *priv
, void *buf
, u32 len
, u32 clock
, u32 flags
);
836 void *tsin_exchange(void *priv
, void *buf
, u32 len
, u32 clock
, u32 flags
);
837 int ngene_start_feed(struct dvb_demux_feed
*dvbdmxfeed
);
838 int ngene_stop_feed(struct dvb_demux_feed
*dvbdmxfeed
);
839 int my_dvb_dmx_ts_card_init(struct dvb_demux
*dvbdemux
, char *id
,
840 int (*start_feed
)(struct dvb_demux_feed
*),
841 int (*stop_feed
)(struct dvb_demux_feed
*),
843 int my_dvb_dmxdev_ts_card_init(struct dmxdev
*dmxdev
,
844 struct dvb_demux
*dvbdemux
,
845 struct dmx_frontend
*hw_frontend
,
846 struct dmx_frontend
*mem_frontend
,
847 struct dvb_adapter
*dvb_adapter
);