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Merge tag 'clang-format-for-linus-v5.1-rc5' of git://github.com/ojeda/linux
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/crc32.h>
22 #include <linux/in.h>
23 #include <linux/io.h>
24 #include <linux/ip.h>
25 #include <linux/tcp.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/firmware.h>
30 #include <linux/prefetch.h>
31 #include <linux/pci-aspm.h>
32 #include <linux/ipv6.h>
33 #include <net/ip6_checksum.h>
34
35 #define MODULENAME "r8169"
36
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
52 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
56
57 #define R8169_MSG_DEFAULT \
58 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
59
60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
62 static const int multicast_filter_limit = 32;
63
64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
66
67 #define R8169_REGS_SIZE 256
68 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
69 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
70 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
73
74 /* write/read MMIO register */
75 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
76 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
77 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
78 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
79 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
80 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
81
82 enum mac_version {
83 RTL_GIGA_MAC_VER_01 = 0,
84 RTL_GIGA_MAC_VER_02,
85 RTL_GIGA_MAC_VER_03,
86 RTL_GIGA_MAC_VER_04,
87 RTL_GIGA_MAC_VER_05,
88 RTL_GIGA_MAC_VER_06,
89 RTL_GIGA_MAC_VER_07,
90 RTL_GIGA_MAC_VER_08,
91 RTL_GIGA_MAC_VER_09,
92 RTL_GIGA_MAC_VER_10,
93 RTL_GIGA_MAC_VER_11,
94 RTL_GIGA_MAC_VER_12,
95 RTL_GIGA_MAC_VER_13,
96 RTL_GIGA_MAC_VER_14,
97 RTL_GIGA_MAC_VER_15,
98 RTL_GIGA_MAC_VER_16,
99 RTL_GIGA_MAC_VER_17,
100 RTL_GIGA_MAC_VER_18,
101 RTL_GIGA_MAC_VER_19,
102 RTL_GIGA_MAC_VER_20,
103 RTL_GIGA_MAC_VER_21,
104 RTL_GIGA_MAC_VER_22,
105 RTL_GIGA_MAC_VER_23,
106 RTL_GIGA_MAC_VER_24,
107 RTL_GIGA_MAC_VER_25,
108 RTL_GIGA_MAC_VER_26,
109 RTL_GIGA_MAC_VER_27,
110 RTL_GIGA_MAC_VER_28,
111 RTL_GIGA_MAC_VER_29,
112 RTL_GIGA_MAC_VER_30,
113 RTL_GIGA_MAC_VER_31,
114 RTL_GIGA_MAC_VER_32,
115 RTL_GIGA_MAC_VER_33,
116 RTL_GIGA_MAC_VER_34,
117 RTL_GIGA_MAC_VER_35,
118 RTL_GIGA_MAC_VER_36,
119 RTL_GIGA_MAC_VER_37,
120 RTL_GIGA_MAC_VER_38,
121 RTL_GIGA_MAC_VER_39,
122 RTL_GIGA_MAC_VER_40,
123 RTL_GIGA_MAC_VER_41,
124 RTL_GIGA_MAC_VER_42,
125 RTL_GIGA_MAC_VER_43,
126 RTL_GIGA_MAC_VER_44,
127 RTL_GIGA_MAC_VER_45,
128 RTL_GIGA_MAC_VER_46,
129 RTL_GIGA_MAC_VER_47,
130 RTL_GIGA_MAC_VER_48,
131 RTL_GIGA_MAC_VER_49,
132 RTL_GIGA_MAC_VER_50,
133 RTL_GIGA_MAC_VER_51,
134 RTL_GIGA_MAC_NONE = 0xff,
135 };
136
137 #define JUMBO_1K ETH_DATA_LEN
138 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
139 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
140 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
141 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
142
143 static const struct {
144 const char *name;
145 const char *fw_name;
146 } rtl_chip_infos[] = {
147 /* PCI devices. */
148 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
149 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
150 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
151 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
152 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
153 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
154 /* PCI-E devices. */
155 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
156 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
157 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
158 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
159 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
160 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
161 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
162 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
163 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
164 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
165 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
166 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
167 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
168 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
169 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
170 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
172 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
173 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
174 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
175 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
176 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
177 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
178 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
179 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
180 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
181 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
182 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
183 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
184 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
185 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
186 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
187 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
188 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
189 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
190 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
191 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
192 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
193 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
194 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
195 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
196 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
197 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
198 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
199 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
200 };
201
202 enum cfg_version {
203 RTL_CFG_0 = 0x00,
204 RTL_CFG_1,
205 RTL_CFG_2
206 };
207
208 static const struct pci_device_id rtl8169_pci_tbl[] = {
209 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
210 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
211 { PCI_VDEVICE(REALTEK, 0x8129), RTL_CFG_0 },
212 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_2 },
213 { PCI_VDEVICE(REALTEK, 0x8161), RTL_CFG_1 },
214 { PCI_VDEVICE(REALTEK, 0x8167), RTL_CFG_0 },
215 { PCI_VDEVICE(REALTEK, 0x8168), RTL_CFG_1 },
216 { PCI_VDEVICE(NCUBE, 0x8168), RTL_CFG_1 },
217 { PCI_VDEVICE(REALTEK, 0x8169), RTL_CFG_0 },
218 { PCI_VENDOR_ID_DLINK, 0x4300,
219 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
220 { PCI_VDEVICE(DLINK, 0x4300), RTL_CFG_0 },
221 { PCI_VDEVICE(DLINK, 0x4302), RTL_CFG_0 },
222 { PCI_VDEVICE(AT, 0xc107), RTL_CFG_0 },
223 { PCI_VDEVICE(USR, 0x0116), RTL_CFG_0 },
224 { PCI_VENDOR_ID_LINKSYS, 0x1032,
225 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
226 { 0x0001, 0x8168,
227 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
228 {}
229 };
230
231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
232
233 static struct {
234 u32 msg_enable;
235 } debug = { -1 };
236
237 enum rtl_registers {
238 MAC0 = 0, /* Ethernet hardware address. */
239 MAC4 = 4,
240 MAR0 = 8, /* Multicast filter. */
241 CounterAddrLow = 0x10,
242 CounterAddrHigh = 0x14,
243 TxDescStartAddrLow = 0x20,
244 TxDescStartAddrHigh = 0x24,
245 TxHDescStartAddrLow = 0x28,
246 TxHDescStartAddrHigh = 0x2c,
247 FLASH = 0x30,
248 ERSR = 0x36,
249 ChipCmd = 0x37,
250 TxPoll = 0x38,
251 IntrMask = 0x3c,
252 IntrStatus = 0x3e,
253
254 TxConfig = 0x40,
255 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
256 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
257
258 RxConfig = 0x44,
259 #define RX128_INT_EN (1 << 15) /* 8111c and later */
260 #define RX_MULTI_EN (1 << 14) /* 8111c only */
261 #define RXCFG_FIFO_SHIFT 13
262 /* No threshold before first PCI xfer */
263 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
264 #define RX_EARLY_OFF (1 << 11)
265 #define RXCFG_DMA_SHIFT 8
266 /* Unlimited maximum PCI burst. */
267 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
268
269 RxMissed = 0x4c,
270 Cfg9346 = 0x50,
271 Config0 = 0x51,
272 Config1 = 0x52,
273 Config2 = 0x53,
274 #define PME_SIGNAL (1 << 5) /* 8168c and later */
275
276 Config3 = 0x54,
277 Config4 = 0x55,
278 Config5 = 0x56,
279 MultiIntr = 0x5c,
280 PHYAR = 0x60,
281 PHYstatus = 0x6c,
282 RxMaxSize = 0xda,
283 CPlusCmd = 0xe0,
284 IntrMitigate = 0xe2,
285
286 #define RTL_COALESCE_MASK 0x0f
287 #define RTL_COALESCE_SHIFT 4
288 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
289 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
290
291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
294
295 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
296
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
298
299 #define TxPacketMax (8064 >> 7)
300 #define EarlySize 0x27
301
302 FuncEvent = 0xf0,
303 FuncEventMask = 0xf4,
304 FuncPresetState = 0xf8,
305 IBCR0 = 0xf8,
306 IBCR2 = 0xf9,
307 IBIMR0 = 0xfa,
308 IBISR0 = 0xfb,
309 FuncForceEvent = 0xfc,
310 };
311
312 enum rtl8168_8101_registers {
313 CSIDR = 0x64,
314 CSIAR = 0x68,
315 #define CSIAR_FLAG 0x80000000
316 #define CSIAR_WRITE_CMD 0x80000000
317 #define CSIAR_BYTE_ENABLE 0x0000f000
318 #define CSIAR_ADDR_MASK 0x00000fff
319 PMCH = 0x6f,
320 EPHYAR = 0x80,
321 #define EPHYAR_FLAG 0x80000000
322 #define EPHYAR_WRITE_CMD 0x80000000
323 #define EPHYAR_REG_MASK 0x1f
324 #define EPHYAR_REG_SHIFT 16
325 #define EPHYAR_DATA_MASK 0xffff
326 DLLPR = 0xd0,
327 #define PFM_EN (1 << 6)
328 #define TX_10M_PS_EN (1 << 7)
329 DBG_REG = 0xd1,
330 #define FIX_NAK_1 (1 << 4)
331 #define FIX_NAK_2 (1 << 3)
332 TWSI = 0xd2,
333 MCU = 0xd3,
334 #define NOW_IS_OOB (1 << 7)
335 #define TX_EMPTY (1 << 5)
336 #define RX_EMPTY (1 << 4)
337 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
338 #define EN_NDP (1 << 3)
339 #define EN_OOB_RESET (1 << 2)
340 #define LINK_LIST_RDY (1 << 1)
341 EFUSEAR = 0xdc,
342 #define EFUSEAR_FLAG 0x80000000
343 #define EFUSEAR_WRITE_CMD 0x80000000
344 #define EFUSEAR_READ_CMD 0x00000000
345 #define EFUSEAR_REG_MASK 0x03ff
346 #define EFUSEAR_REG_SHIFT 8
347 #define EFUSEAR_DATA_MASK 0xff
348 MISC_1 = 0xf2,
349 #define PFM_D3COLD_EN (1 << 6)
350 };
351
352 enum rtl8168_registers {
353 LED_FREQ = 0x1a,
354 EEE_LED = 0x1b,
355 ERIDR = 0x70,
356 ERIAR = 0x74,
357 #define ERIAR_FLAG 0x80000000
358 #define ERIAR_WRITE_CMD 0x80000000
359 #define ERIAR_READ_CMD 0x00000000
360 #define ERIAR_ADDR_BYTE_ALIGN 4
361 #define ERIAR_TYPE_SHIFT 16
362 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
363 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
364 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
365 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
366 #define ERIAR_MASK_SHIFT 12
367 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
368 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
369 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
370 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
371 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
372 EPHY_RXER_NUM = 0x7c,
373 OCPDR = 0xb0, /* OCP GPHY access */
374 #define OCPDR_WRITE_CMD 0x80000000
375 #define OCPDR_READ_CMD 0x00000000
376 #define OCPDR_REG_MASK 0x7f
377 #define OCPDR_GPHY_REG_SHIFT 16
378 #define OCPDR_DATA_MASK 0xffff
379 OCPAR = 0xb4,
380 #define OCPAR_FLAG 0x80000000
381 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
382 #define OCPAR_GPHY_READ_CMD 0x0000f060
383 GPHY_OCP = 0xb8,
384 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
385 MISC = 0xf0, /* 8168e only. */
386 #define TXPLA_RST (1 << 29)
387 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
388 #define PWM_EN (1 << 22)
389 #define RXDV_GATED_EN (1 << 19)
390 #define EARLY_TALLY_EN (1 << 16)
391 };
392
393 enum rtl_register_content {
394 /* InterruptStatusBits */
395 SYSErr = 0x8000,
396 PCSTimeout = 0x4000,
397 SWInt = 0x0100,
398 TxDescUnavail = 0x0080,
399 RxFIFOOver = 0x0040,
400 LinkChg = 0x0020,
401 RxOverflow = 0x0010,
402 TxErr = 0x0008,
403 TxOK = 0x0004,
404 RxErr = 0x0002,
405 RxOK = 0x0001,
406
407 /* RxStatusDesc */
408 RxBOVF = (1 << 24),
409 RxFOVF = (1 << 23),
410 RxRWT = (1 << 22),
411 RxRES = (1 << 21),
412 RxRUNT = (1 << 20),
413 RxCRC = (1 << 19),
414
415 /* ChipCmdBits */
416 StopReq = 0x80,
417 CmdReset = 0x10,
418 CmdRxEnb = 0x08,
419 CmdTxEnb = 0x04,
420 RxBufEmpty = 0x01,
421
422 /* TXPoll register p.5 */
423 HPQ = 0x80, /* Poll cmd on the high prio queue */
424 NPQ = 0x40, /* Poll cmd on the low prio queue */
425 FSWInt = 0x01, /* Forced software interrupt */
426
427 /* Cfg9346Bits */
428 Cfg9346_Lock = 0x00,
429 Cfg9346_Unlock = 0xc0,
430
431 /* rx_mode_bits */
432 AcceptErr = 0x20,
433 AcceptRunt = 0x10,
434 AcceptBroadcast = 0x08,
435 AcceptMulticast = 0x04,
436 AcceptMyPhys = 0x02,
437 AcceptAllPhys = 0x01,
438 #define RX_CONFIG_ACCEPT_MASK 0x3f
439
440 /* TxConfigBits */
441 TxInterFrameGapShift = 24,
442 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
443
444 /* Config1 register p.24 */
445 LEDS1 = (1 << 7),
446 LEDS0 = (1 << 6),
447 Speed_down = (1 << 4),
448 MEMMAP = (1 << 3),
449 IOMAP = (1 << 2),
450 VPD = (1 << 1),
451 PMEnable = (1 << 0), /* Power Management Enable */
452
453 /* Config2 register p. 25 */
454 ClkReqEn = (1 << 7), /* Clock Request Enable */
455 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
456 PCI_Clock_66MHz = 0x01,
457 PCI_Clock_33MHz = 0x00,
458
459 /* Config3 register p.25 */
460 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
461 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
462 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
463 Rdy_to_L23 = (1 << 1), /* L23 Enable */
464 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
465
466 /* Config4 register */
467 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
468
469 /* Config5 register p.27 */
470 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
471 MWF = (1 << 5), /* Accept Multicast wakeup frame */
472 UWF = (1 << 4), /* Accept Unicast wakeup frame */
473 Spi_en = (1 << 3),
474 LanWake = (1 << 1), /* LanWake enable/disable */
475 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
476 ASPM_en = (1 << 0), /* ASPM enable */
477
478 /* CPlusCmd p.31 */
479 EnableBist = (1 << 15), // 8168 8101
480 Mac_dbgo_oe = (1 << 14), // 8168 8101
481 Normal_mode = (1 << 13), // unused
482 Force_half_dup = (1 << 12), // 8168 8101
483 Force_rxflow_en = (1 << 11), // 8168 8101
484 Force_txflow_en = (1 << 10), // 8168 8101
485 Cxpl_dbg_sel = (1 << 9), // 8168 8101
486 ASF = (1 << 8), // 8168 8101
487 PktCntrDisable = (1 << 7), // 8168 8101
488 Mac_dbgo_sel = 0x001c, // 8168
489 RxVlan = (1 << 6),
490 RxChkSum = (1 << 5),
491 PCIDAC = (1 << 4),
492 PCIMulRW = (1 << 3),
493 #define INTT_MASK GENMASK(1, 0)
494 INTT_0 = 0x0000, // 8168
495 INTT_1 = 0x0001, // 8168
496 INTT_2 = 0x0002, // 8168
497 INTT_3 = 0x0003, // 8168
498
499 /* rtl8169_PHYstatus */
500 TBI_Enable = 0x80,
501 TxFlowCtrl = 0x40,
502 RxFlowCtrl = 0x20,
503 _1000bpsF = 0x10,
504 _100bps = 0x08,
505 _10bps = 0x04,
506 LinkStatus = 0x02,
507 FullDup = 0x01,
508
509 /* _TBICSRBit */
510 TBILinkOK = 0x02000000,
511
512 /* ResetCounterCommand */
513 CounterReset = 0x1,
514
515 /* DumpCounterCommand */
516 CounterDump = 0x8,
517
518 /* magic enable v2 */
519 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
520 };
521
522 enum rtl_desc_bit {
523 /* First doubleword. */
524 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
525 RingEnd = (1 << 30), /* End of descriptor ring */
526 FirstFrag = (1 << 29), /* First segment of a packet */
527 LastFrag = (1 << 28), /* Final segment of a packet */
528 };
529
530 /* Generic case. */
531 enum rtl_tx_desc_bit {
532 /* First doubleword. */
533 TD_LSO = (1 << 27), /* Large Send Offload */
534 #define TD_MSS_MAX 0x07ffu /* MSS value */
535
536 /* Second doubleword. */
537 TxVlanTag = (1 << 17), /* Add VLAN tag */
538 };
539
540 /* 8169, 8168b and 810x except 8102e. */
541 enum rtl_tx_desc_bit_0 {
542 /* First doubleword. */
543 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
544 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
545 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
546 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
547 };
548
549 /* 8102e, 8168c and beyond. */
550 enum rtl_tx_desc_bit_1 {
551 /* First doubleword. */
552 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
553 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
554 #define GTTCPHO_SHIFT 18
555 #define GTTCPHO_MAX 0x7fU
556
557 /* Second doubleword. */
558 #define TCPHO_SHIFT 18
559 #define TCPHO_MAX 0x3ffU
560 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
561 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
562 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
563 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
564 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
565 };
566
567 enum rtl_rx_desc_bit {
568 /* Rx private */
569 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
570 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
571
572 #define RxProtoUDP (PID1)
573 #define RxProtoTCP (PID0)
574 #define RxProtoIP (PID1 | PID0)
575 #define RxProtoMask RxProtoIP
576
577 IPFail = (1 << 16), /* IP checksum failed */
578 UDPFail = (1 << 15), /* UDP/IP checksum failed */
579 TCPFail = (1 << 14), /* TCP/IP checksum failed */
580 RxVlanTag = (1 << 16), /* VLAN tag available */
581 };
582
583 #define RsvdMask 0x3fffc000
584 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
585
586 struct TxDesc {
587 __le32 opts1;
588 __le32 opts2;
589 __le64 addr;
590 };
591
592 struct RxDesc {
593 __le32 opts1;
594 __le32 opts2;
595 __le64 addr;
596 };
597
598 struct ring_info {
599 struct sk_buff *skb;
600 u32 len;
601 };
602
603 struct rtl8169_counters {
604 __le64 tx_packets;
605 __le64 rx_packets;
606 __le64 tx_errors;
607 __le32 rx_errors;
608 __le16 rx_missed;
609 __le16 align_errors;
610 __le32 tx_one_collision;
611 __le32 tx_multi_collision;
612 __le64 rx_unicast;
613 __le64 rx_broadcast;
614 __le32 rx_multicast;
615 __le16 tx_aborted;
616 __le16 tx_underun;
617 };
618
619 struct rtl8169_tc_offsets {
620 bool inited;
621 __le64 tx_errors;
622 __le32 tx_multi_collision;
623 __le16 tx_aborted;
624 };
625
626 enum rtl_flag {
627 RTL_FLAG_TASK_ENABLED = 0,
628 RTL_FLAG_TASK_RESET_PENDING,
629 RTL_FLAG_MAX
630 };
631
632 struct rtl8169_stats {
633 u64 packets;
634 u64 bytes;
635 struct u64_stats_sync syncp;
636 };
637
638 struct rtl8169_private {
639 void __iomem *mmio_addr; /* memory map physical address */
640 struct pci_dev *pci_dev;
641 struct net_device *dev;
642 struct phy_device *phydev;
643 struct napi_struct napi;
644 u32 msg_enable;
645 u16 mac_version;
646 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
647 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
648 u32 dirty_tx;
649 struct rtl8169_stats rx_stats;
650 struct rtl8169_stats tx_stats;
651 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
652 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
653 dma_addr_t TxPhyAddr;
654 dma_addr_t RxPhyAddr;
655 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
656 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
657 u16 cp_cmd;
658
659 u16 irq_mask;
660 const struct rtl_coalesce_info *coalesce_info;
661 struct clk *clk;
662
663 struct mdio_ops {
664 void (*write)(struct rtl8169_private *, int, int);
665 int (*read)(struct rtl8169_private *, int);
666 } mdio_ops;
667
668 struct jumbo_ops {
669 void (*enable)(struct rtl8169_private *);
670 void (*disable)(struct rtl8169_private *);
671 } jumbo_ops;
672
673 void (*hw_start)(struct rtl8169_private *tp);
674 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
675
676 struct {
677 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
678 struct mutex mutex;
679 struct work_struct work;
680 } wk;
681
682 unsigned irq_enabled:1;
683 unsigned supports_gmii:1;
684 dma_addr_t counters_phys_addr;
685 struct rtl8169_counters *counters;
686 struct rtl8169_tc_offsets tc_offset;
687 u32 saved_wolopts;
688
689 const char *fw_name;
690 struct rtl_fw {
691 const struct firmware *fw;
692
693 #define RTL_VER_SIZE 32
694
695 char version[RTL_VER_SIZE];
696
697 struct rtl_fw_phy_action {
698 __le32 *code;
699 size_t size;
700 } phy_action;
701 } *rtl_fw;
702
703 u32 ocp_base;
704 };
705
706 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
707 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
708 module_param_named(debug, debug.msg_enable, int, 0);
709 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
710 MODULE_SOFTDEP("pre: realtek");
711 MODULE_LICENSE("GPL");
712 MODULE_FIRMWARE(FIRMWARE_8168D_1);
713 MODULE_FIRMWARE(FIRMWARE_8168D_2);
714 MODULE_FIRMWARE(FIRMWARE_8168E_1);
715 MODULE_FIRMWARE(FIRMWARE_8168E_2);
716 MODULE_FIRMWARE(FIRMWARE_8168E_3);
717 MODULE_FIRMWARE(FIRMWARE_8105E_1);
718 MODULE_FIRMWARE(FIRMWARE_8168F_1);
719 MODULE_FIRMWARE(FIRMWARE_8168F_2);
720 MODULE_FIRMWARE(FIRMWARE_8402_1);
721 MODULE_FIRMWARE(FIRMWARE_8411_1);
722 MODULE_FIRMWARE(FIRMWARE_8411_2);
723 MODULE_FIRMWARE(FIRMWARE_8106E_1);
724 MODULE_FIRMWARE(FIRMWARE_8106E_2);
725 MODULE_FIRMWARE(FIRMWARE_8168G_2);
726 MODULE_FIRMWARE(FIRMWARE_8168G_3);
727 MODULE_FIRMWARE(FIRMWARE_8168H_1);
728 MODULE_FIRMWARE(FIRMWARE_8168H_2);
729 MODULE_FIRMWARE(FIRMWARE_8107E_1);
730 MODULE_FIRMWARE(FIRMWARE_8107E_2);
731
732 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
733 {
734 return &tp->pci_dev->dev;
735 }
736
737 static void rtl_lock_work(struct rtl8169_private *tp)
738 {
739 mutex_lock(&tp->wk.mutex);
740 }
741
742 static void rtl_unlock_work(struct rtl8169_private *tp)
743 {
744 mutex_unlock(&tp->wk.mutex);
745 }
746
747 static void rtl_lock_config_regs(struct rtl8169_private *tp)
748 {
749 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
750 }
751
752 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
753 {
754 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
755 }
756
757 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
758 {
759 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
760 PCI_EXP_DEVCTL_READRQ, force);
761 }
762
763 struct rtl_cond {
764 bool (*check)(struct rtl8169_private *);
765 const char *msg;
766 };
767
768 static void rtl_udelay(unsigned int d)
769 {
770 udelay(d);
771 }
772
773 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
774 void (*delay)(unsigned int), unsigned int d, int n,
775 bool high)
776 {
777 int i;
778
779 for (i = 0; i < n; i++) {
780 delay(d);
781 if (c->check(tp) == high)
782 return true;
783 }
784 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
785 c->msg, !high, n, d);
786 return false;
787 }
788
789 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
790 const struct rtl_cond *c,
791 unsigned int d, int n)
792 {
793 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
794 }
795
796 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
797 const struct rtl_cond *c,
798 unsigned int d, int n)
799 {
800 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
801 }
802
803 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
804 const struct rtl_cond *c,
805 unsigned int d, int n)
806 {
807 return rtl_loop_wait(tp, c, msleep, d, n, true);
808 }
809
810 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
811 const struct rtl_cond *c,
812 unsigned int d, int n)
813 {
814 return rtl_loop_wait(tp, c, msleep, d, n, false);
815 }
816
817 #define DECLARE_RTL_COND(name) \
818 static bool name ## _check(struct rtl8169_private *); \
819 \
820 static const struct rtl_cond name = { \
821 .check = name ## _check, \
822 .msg = #name \
823 }; \
824 \
825 static bool name ## _check(struct rtl8169_private *tp)
826
827 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
828 {
829 if (reg & 0xffff0001) {
830 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
831 return true;
832 }
833 return false;
834 }
835
836 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
837 {
838 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
839 }
840
841 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
842 {
843 if (rtl_ocp_reg_failure(tp, reg))
844 return;
845
846 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
847
848 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
849 }
850
851 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
852 {
853 if (rtl_ocp_reg_failure(tp, reg))
854 return 0;
855
856 RTL_W32(tp, GPHY_OCP, reg << 15);
857
858 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
859 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
860 }
861
862 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
863 {
864 if (rtl_ocp_reg_failure(tp, reg))
865 return;
866
867 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
868 }
869
870 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
871 {
872 if (rtl_ocp_reg_failure(tp, reg))
873 return 0;
874
875 RTL_W32(tp, OCPDR, reg << 15);
876
877 return RTL_R32(tp, OCPDR);
878 }
879
880 #define OCP_STD_PHY_BASE 0xa400
881
882 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
883 {
884 if (reg == 0x1f) {
885 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
886 return;
887 }
888
889 if (tp->ocp_base != OCP_STD_PHY_BASE)
890 reg -= 0x10;
891
892 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
893 }
894
895 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
896 {
897 if (tp->ocp_base != OCP_STD_PHY_BASE)
898 reg -= 0x10;
899
900 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
901 }
902
903 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
904 {
905 if (reg == 0x1f) {
906 tp->ocp_base = value << 4;
907 return;
908 }
909
910 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
911 }
912
913 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
914 {
915 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
916 }
917
918 DECLARE_RTL_COND(rtl_phyar_cond)
919 {
920 return RTL_R32(tp, PHYAR) & 0x80000000;
921 }
922
923 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
924 {
925 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
926
927 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
928 /*
929 * According to hardware specs a 20us delay is required after write
930 * complete indication, but before sending next command.
931 */
932 udelay(20);
933 }
934
935 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
936 {
937 int value;
938
939 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
940
941 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
942 RTL_R32(tp, PHYAR) & 0xffff : ~0;
943
944 /*
945 * According to hardware specs a 20us delay is required after read
946 * complete indication, but before sending next command.
947 */
948 udelay(20);
949
950 return value;
951 }
952
953 DECLARE_RTL_COND(rtl_ocpar_cond)
954 {
955 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
956 }
957
958 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
959 {
960 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
961 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
962 RTL_W32(tp, EPHY_RXER_NUM, 0);
963
964 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
965 }
966
967 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
968 {
969 r8168dp_1_mdio_access(tp, reg,
970 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
971 }
972
973 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
974 {
975 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
976
977 mdelay(1);
978 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
979 RTL_W32(tp, EPHY_RXER_NUM, 0);
980
981 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
982 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
983 }
984
985 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
986
987 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
988 {
989 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
990 }
991
992 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
993 {
994 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
995 }
996
997 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
998 {
999 r8168dp_2_mdio_start(tp);
1000
1001 r8169_mdio_write(tp, reg, value);
1002
1003 r8168dp_2_mdio_stop(tp);
1004 }
1005
1006 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1007 {
1008 int value;
1009
1010 r8168dp_2_mdio_start(tp);
1011
1012 value = r8169_mdio_read(tp, reg);
1013
1014 r8168dp_2_mdio_stop(tp);
1015
1016 return value;
1017 }
1018
1019 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1020 {
1021 tp->mdio_ops.write(tp, location, val);
1022 }
1023
1024 static int rtl_readphy(struct rtl8169_private *tp, int location)
1025 {
1026 return tp->mdio_ops.read(tp, location);
1027 }
1028
1029 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1030 {
1031 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1032 }
1033
1034 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1035 {
1036 int val;
1037
1038 val = rtl_readphy(tp, reg_addr);
1039 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1040 }
1041
1042 DECLARE_RTL_COND(rtl_ephyar_cond)
1043 {
1044 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1045 }
1046
1047 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1048 {
1049 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1050 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1051
1052 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1053
1054 udelay(10);
1055 }
1056
1057 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1058 {
1059 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1060
1061 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1062 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1063 }
1064
1065 DECLARE_RTL_COND(rtl_eriar_cond)
1066 {
1067 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1068 }
1069
1070 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1071 u32 val, int type)
1072 {
1073 BUG_ON((addr & 3) || (mask == 0));
1074 RTL_W32(tp, ERIDR, val);
1075 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1076
1077 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1078 }
1079
1080 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1081 {
1082 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1083
1084 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1085 RTL_R32(tp, ERIDR) : ~0;
1086 }
1087
1088 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1089 u32 m, int type)
1090 {
1091 u32 val;
1092
1093 val = rtl_eri_read(tp, addr, type);
1094 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1095 }
1096
1097 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1098 {
1099 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1100 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1101 RTL_R32(tp, OCPDR) : ~0;
1102 }
1103
1104 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1105 {
1106 return rtl_eri_read(tp, reg, ERIAR_OOB);
1107 }
1108
1109 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1110 u32 data)
1111 {
1112 RTL_W32(tp, OCPDR, data);
1113 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1114 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1115 }
1116
1117 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1118 u32 data)
1119 {
1120 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1121 data, ERIAR_OOB);
1122 }
1123
1124 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1125 {
1126 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1127
1128 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1129 }
1130
1131 #define OOB_CMD_RESET 0x00
1132 #define OOB_CMD_DRIVER_START 0x05
1133 #define OOB_CMD_DRIVER_STOP 0x06
1134
1135 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1136 {
1137 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1138 }
1139
1140 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1141 {
1142 u16 reg;
1143
1144 reg = rtl8168_get_ocp_reg(tp);
1145
1146 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1147 }
1148
1149 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1150 {
1151 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1152 }
1153
1154 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1155 {
1156 return RTL_R8(tp, IBISR0) & 0x20;
1157 }
1158
1159 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1160 {
1161 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1162 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1163 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1164 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1165 }
1166
1167 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1168 {
1169 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1170 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1171 }
1172
1173 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1174 {
1175 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1176 r8168ep_ocp_write(tp, 0x01, 0x30,
1177 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1178 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1179 }
1180
1181 static void rtl8168_driver_start(struct rtl8169_private *tp)
1182 {
1183 switch (tp->mac_version) {
1184 case RTL_GIGA_MAC_VER_27:
1185 case RTL_GIGA_MAC_VER_28:
1186 case RTL_GIGA_MAC_VER_31:
1187 rtl8168dp_driver_start(tp);
1188 break;
1189 case RTL_GIGA_MAC_VER_49:
1190 case RTL_GIGA_MAC_VER_50:
1191 case RTL_GIGA_MAC_VER_51:
1192 rtl8168ep_driver_start(tp);
1193 break;
1194 default:
1195 BUG();
1196 break;
1197 }
1198 }
1199
1200 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1201 {
1202 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1203 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1204 }
1205
1206 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1207 {
1208 rtl8168ep_stop_cmac(tp);
1209 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1210 r8168ep_ocp_write(tp, 0x01, 0x30,
1211 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1212 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1213 }
1214
1215 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1216 {
1217 switch (tp->mac_version) {
1218 case RTL_GIGA_MAC_VER_27:
1219 case RTL_GIGA_MAC_VER_28:
1220 case RTL_GIGA_MAC_VER_31:
1221 rtl8168dp_driver_stop(tp);
1222 break;
1223 case RTL_GIGA_MAC_VER_49:
1224 case RTL_GIGA_MAC_VER_50:
1225 case RTL_GIGA_MAC_VER_51:
1226 rtl8168ep_driver_stop(tp);
1227 break;
1228 default:
1229 BUG();
1230 break;
1231 }
1232 }
1233
1234 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1235 {
1236 u16 reg = rtl8168_get_ocp_reg(tp);
1237
1238 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1239 }
1240
1241 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1242 {
1243 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1244 }
1245
1246 static bool r8168_check_dash(struct rtl8169_private *tp)
1247 {
1248 switch (tp->mac_version) {
1249 case RTL_GIGA_MAC_VER_27:
1250 case RTL_GIGA_MAC_VER_28:
1251 case RTL_GIGA_MAC_VER_31:
1252 return r8168dp_check_dash(tp);
1253 case RTL_GIGA_MAC_VER_49:
1254 case RTL_GIGA_MAC_VER_50:
1255 case RTL_GIGA_MAC_VER_51:
1256 return r8168ep_check_dash(tp);
1257 default:
1258 return false;
1259 }
1260 }
1261
1262 struct exgmac_reg {
1263 u16 addr;
1264 u16 mask;
1265 u32 val;
1266 };
1267
1268 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1269 const struct exgmac_reg *r, int len)
1270 {
1271 while (len-- > 0) {
1272 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1273 r++;
1274 }
1275 }
1276
1277 DECLARE_RTL_COND(rtl_efusear_cond)
1278 {
1279 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1280 }
1281
1282 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1283 {
1284 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1285
1286 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1287 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1288 }
1289
1290 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1291 {
1292 RTL_W16(tp, IntrStatus, bits);
1293 }
1294
1295 static void rtl_irq_disable(struct rtl8169_private *tp)
1296 {
1297 RTL_W16(tp, IntrMask, 0);
1298 tp->irq_enabled = 0;
1299 }
1300
1301 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1302 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1303 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1304
1305 static void rtl_irq_enable(struct rtl8169_private *tp)
1306 {
1307 tp->irq_enabled = 1;
1308 RTL_W16(tp, IntrMask, tp->irq_mask);
1309 }
1310
1311 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1312 {
1313 rtl_irq_disable(tp);
1314 rtl_ack_events(tp, 0xffff);
1315 /* PCI commit */
1316 RTL_R8(tp, ChipCmd);
1317 }
1318
1319 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1320 {
1321 struct net_device *dev = tp->dev;
1322 struct phy_device *phydev = tp->phydev;
1323
1324 if (!netif_running(dev))
1325 return;
1326
1327 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1328 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1329 if (phydev->speed == SPEED_1000) {
1330 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1331 ERIAR_EXGMAC);
1332 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1333 ERIAR_EXGMAC);
1334 } else if (phydev->speed == SPEED_100) {
1335 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1336 ERIAR_EXGMAC);
1337 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1338 ERIAR_EXGMAC);
1339 } else {
1340 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1341 ERIAR_EXGMAC);
1342 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1343 ERIAR_EXGMAC);
1344 }
1345 /* Reset packet filter */
1346 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1347 ERIAR_EXGMAC);
1348 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1349 ERIAR_EXGMAC);
1350 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1351 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1352 if (phydev->speed == SPEED_1000) {
1353 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1354 ERIAR_EXGMAC);
1355 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1356 ERIAR_EXGMAC);
1357 } else {
1358 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1359 ERIAR_EXGMAC);
1360 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1361 ERIAR_EXGMAC);
1362 }
1363 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1364 if (phydev->speed == SPEED_10) {
1365 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1366 ERIAR_EXGMAC);
1367 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1368 ERIAR_EXGMAC);
1369 } else {
1370 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1371 ERIAR_EXGMAC);
1372 }
1373 }
1374 }
1375
1376 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1377
1378 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1379 {
1380 struct rtl8169_private *tp = netdev_priv(dev);
1381
1382 rtl_lock_work(tp);
1383 wol->supported = WAKE_ANY;
1384 wol->wolopts = tp->saved_wolopts;
1385 rtl_unlock_work(tp);
1386 }
1387
1388 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1389 {
1390 unsigned int i, tmp;
1391 static const struct {
1392 u32 opt;
1393 u16 reg;
1394 u8 mask;
1395 } cfg[] = {
1396 { WAKE_PHY, Config3, LinkUp },
1397 { WAKE_UCAST, Config5, UWF },
1398 { WAKE_BCAST, Config5, BWF },
1399 { WAKE_MCAST, Config5, MWF },
1400 { WAKE_ANY, Config5, LanWake },
1401 { WAKE_MAGIC, Config3, MagicPacket }
1402 };
1403 u8 options;
1404
1405 rtl_unlock_config_regs(tp);
1406
1407 switch (tp->mac_version) {
1408 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1409 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1410 tmp = ARRAY_SIZE(cfg) - 1;
1411 if (wolopts & WAKE_MAGIC)
1412 rtl_w0w1_eri(tp,
1413 0x0dc,
1414 ERIAR_MASK_0100,
1415 MagicPacket_v2,
1416 0x0000,
1417 ERIAR_EXGMAC);
1418 else
1419 rtl_w0w1_eri(tp,
1420 0x0dc,
1421 ERIAR_MASK_0100,
1422 0x0000,
1423 MagicPacket_v2,
1424 ERIAR_EXGMAC);
1425 break;
1426 default:
1427 tmp = ARRAY_SIZE(cfg);
1428 break;
1429 }
1430
1431 for (i = 0; i < tmp; i++) {
1432 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1433 if (wolopts & cfg[i].opt)
1434 options |= cfg[i].mask;
1435 RTL_W8(tp, cfg[i].reg, options);
1436 }
1437
1438 switch (tp->mac_version) {
1439 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1440 options = RTL_R8(tp, Config1) & ~PMEnable;
1441 if (wolopts)
1442 options |= PMEnable;
1443 RTL_W8(tp, Config1, options);
1444 break;
1445 default:
1446 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1447 if (wolopts)
1448 options |= PME_SIGNAL;
1449 RTL_W8(tp, Config2, options);
1450 break;
1451 }
1452
1453 rtl_lock_config_regs(tp);
1454
1455 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1456 }
1457
1458 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1459 {
1460 struct rtl8169_private *tp = netdev_priv(dev);
1461 struct device *d = tp_to_dev(tp);
1462
1463 if (wol->wolopts & ~WAKE_ANY)
1464 return -EINVAL;
1465
1466 pm_runtime_get_noresume(d);
1467
1468 rtl_lock_work(tp);
1469
1470 tp->saved_wolopts = wol->wolopts;
1471
1472 if (pm_runtime_active(d))
1473 __rtl8169_set_wol(tp, tp->saved_wolopts);
1474
1475 rtl_unlock_work(tp);
1476
1477 pm_runtime_put_noidle(d);
1478
1479 return 0;
1480 }
1481
1482 static void rtl8169_get_drvinfo(struct net_device *dev,
1483 struct ethtool_drvinfo *info)
1484 {
1485 struct rtl8169_private *tp = netdev_priv(dev);
1486 struct rtl_fw *rtl_fw = tp->rtl_fw;
1487
1488 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1489 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1490 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1491 if (rtl_fw)
1492 strlcpy(info->fw_version, rtl_fw->version,
1493 sizeof(info->fw_version));
1494 }
1495
1496 static int rtl8169_get_regs_len(struct net_device *dev)
1497 {
1498 return R8169_REGS_SIZE;
1499 }
1500
1501 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1502 netdev_features_t features)
1503 {
1504 struct rtl8169_private *tp = netdev_priv(dev);
1505
1506 if (dev->mtu > TD_MSS_MAX)
1507 features &= ~NETIF_F_ALL_TSO;
1508
1509 if (dev->mtu > JUMBO_1K &&
1510 tp->mac_version > RTL_GIGA_MAC_VER_06)
1511 features &= ~NETIF_F_IP_CSUM;
1512
1513 return features;
1514 }
1515
1516 static int rtl8169_set_features(struct net_device *dev,
1517 netdev_features_t features)
1518 {
1519 struct rtl8169_private *tp = netdev_priv(dev);
1520 u32 rx_config;
1521
1522 rtl_lock_work(tp);
1523
1524 rx_config = RTL_R32(tp, RxConfig);
1525 if (features & NETIF_F_RXALL)
1526 rx_config |= (AcceptErr | AcceptRunt);
1527 else
1528 rx_config &= ~(AcceptErr | AcceptRunt);
1529
1530 RTL_W32(tp, RxConfig, rx_config);
1531
1532 if (features & NETIF_F_RXCSUM)
1533 tp->cp_cmd |= RxChkSum;
1534 else
1535 tp->cp_cmd &= ~RxChkSum;
1536
1537 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1538 tp->cp_cmd |= RxVlan;
1539 else
1540 tp->cp_cmd &= ~RxVlan;
1541
1542 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1543 RTL_R16(tp, CPlusCmd);
1544
1545 rtl_unlock_work(tp);
1546
1547 return 0;
1548 }
1549
1550 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1551 {
1552 return (skb_vlan_tag_present(skb)) ?
1553 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1554 }
1555
1556 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1557 {
1558 u32 opts2 = le32_to_cpu(desc->opts2);
1559
1560 if (opts2 & RxVlanTag)
1561 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1562 }
1563
1564 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1565 void *p)
1566 {
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568 u32 __iomem *data = tp->mmio_addr;
1569 u32 *dw = p;
1570 int i;
1571
1572 rtl_lock_work(tp);
1573 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1574 memcpy_fromio(dw++, data++, 4);
1575 rtl_unlock_work(tp);
1576 }
1577
1578 static u32 rtl8169_get_msglevel(struct net_device *dev)
1579 {
1580 struct rtl8169_private *tp = netdev_priv(dev);
1581
1582 return tp->msg_enable;
1583 }
1584
1585 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1586 {
1587 struct rtl8169_private *tp = netdev_priv(dev);
1588
1589 tp->msg_enable = value;
1590 }
1591
1592 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1593 "tx_packets",
1594 "rx_packets",
1595 "tx_errors",
1596 "rx_errors",
1597 "rx_missed",
1598 "align_errors",
1599 "tx_single_collisions",
1600 "tx_multi_collisions",
1601 "unicast",
1602 "broadcast",
1603 "multicast",
1604 "tx_aborted",
1605 "tx_underrun",
1606 };
1607
1608 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1609 {
1610 switch (sset) {
1611 case ETH_SS_STATS:
1612 return ARRAY_SIZE(rtl8169_gstrings);
1613 default:
1614 return -EOPNOTSUPP;
1615 }
1616 }
1617
1618 DECLARE_RTL_COND(rtl_counters_cond)
1619 {
1620 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1621 }
1622
1623 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1624 {
1625 dma_addr_t paddr = tp->counters_phys_addr;
1626 u32 cmd;
1627
1628 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1629 RTL_R32(tp, CounterAddrHigh);
1630 cmd = (u64)paddr & DMA_BIT_MASK(32);
1631 RTL_W32(tp, CounterAddrLow, cmd);
1632 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1633
1634 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1635 }
1636
1637 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1638 {
1639 /*
1640 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1641 * tally counters.
1642 */
1643 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1644 return true;
1645
1646 return rtl8169_do_counters(tp, CounterReset);
1647 }
1648
1649 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1650 {
1651 u8 val = RTL_R8(tp, ChipCmd);
1652
1653 /*
1654 * Some chips are unable to dump tally counters when the receiver
1655 * is disabled. If 0xff chip may be in a PCI power-save state.
1656 */
1657 if (!(val & CmdRxEnb) || val == 0xff)
1658 return true;
1659
1660 return rtl8169_do_counters(tp, CounterDump);
1661 }
1662
1663 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1664 {
1665 struct rtl8169_counters *counters = tp->counters;
1666 bool ret = false;
1667
1668 /*
1669 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1670 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1671 * reset by a power cycle, while the counter values collected by the
1672 * driver are reset at every driver unload/load cycle.
1673 *
1674 * To make sure the HW values returned by @get_stats64 match the SW
1675 * values, we collect the initial values at first open(*) and use them
1676 * as offsets to normalize the values returned by @get_stats64.
1677 *
1678 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1679 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1680 * set at open time by rtl_hw_start.
1681 */
1682
1683 if (tp->tc_offset.inited)
1684 return true;
1685
1686 /* If both, reset and update fail, propagate to caller. */
1687 if (rtl8169_reset_counters(tp))
1688 ret = true;
1689
1690 if (rtl8169_update_counters(tp))
1691 ret = true;
1692
1693 tp->tc_offset.tx_errors = counters->tx_errors;
1694 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1695 tp->tc_offset.tx_aborted = counters->tx_aborted;
1696 tp->tc_offset.inited = true;
1697
1698 return ret;
1699 }
1700
1701 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1702 struct ethtool_stats *stats, u64 *data)
1703 {
1704 struct rtl8169_private *tp = netdev_priv(dev);
1705 struct device *d = tp_to_dev(tp);
1706 struct rtl8169_counters *counters = tp->counters;
1707
1708 ASSERT_RTNL();
1709
1710 pm_runtime_get_noresume(d);
1711
1712 if (pm_runtime_active(d))
1713 rtl8169_update_counters(tp);
1714
1715 pm_runtime_put_noidle(d);
1716
1717 data[0] = le64_to_cpu(counters->tx_packets);
1718 data[1] = le64_to_cpu(counters->rx_packets);
1719 data[2] = le64_to_cpu(counters->tx_errors);
1720 data[3] = le32_to_cpu(counters->rx_errors);
1721 data[4] = le16_to_cpu(counters->rx_missed);
1722 data[5] = le16_to_cpu(counters->align_errors);
1723 data[6] = le32_to_cpu(counters->tx_one_collision);
1724 data[7] = le32_to_cpu(counters->tx_multi_collision);
1725 data[8] = le64_to_cpu(counters->rx_unicast);
1726 data[9] = le64_to_cpu(counters->rx_broadcast);
1727 data[10] = le32_to_cpu(counters->rx_multicast);
1728 data[11] = le16_to_cpu(counters->tx_aborted);
1729 data[12] = le16_to_cpu(counters->tx_underun);
1730 }
1731
1732 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1733 {
1734 switch(stringset) {
1735 case ETH_SS_STATS:
1736 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1737 break;
1738 }
1739 }
1740
1741 /*
1742 * Interrupt coalescing
1743 *
1744 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1745 * > 8169, 8168 and 810x line of chipsets
1746 *
1747 * 8169, 8168, and 8136(810x) serial chipsets support it.
1748 *
1749 * > 2 - the Tx timer unit at gigabit speed
1750 *
1751 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1752 * (0xe0) bit 1 and bit 0.
1753 *
1754 * For 8169
1755 * bit[1:0] \ speed 1000M 100M 10M
1756 * 0 0 320ns 2.56us 40.96us
1757 * 0 1 2.56us 20.48us 327.7us
1758 * 1 0 5.12us 40.96us 655.4us
1759 * 1 1 10.24us 81.92us 1.31ms
1760 *
1761 * For the other
1762 * bit[1:0] \ speed 1000M 100M 10M
1763 * 0 0 5us 2.56us 40.96us
1764 * 0 1 40us 20.48us 327.7us
1765 * 1 0 80us 40.96us 655.4us
1766 * 1 1 160us 81.92us 1.31ms
1767 */
1768
1769 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1770 struct rtl_coalesce_scale {
1771 /* Rx / Tx */
1772 u32 nsecs[2];
1773 };
1774
1775 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1776 struct rtl_coalesce_info {
1777 u32 speed;
1778 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1779 };
1780
1781 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1782 #define rxtx_x1822(r, t) { \
1783 {{(r), (t)}}, \
1784 {{(r)*8, (t)*8}}, \
1785 {{(r)*8*2, (t)*8*2}}, \
1786 {{(r)*8*2*2, (t)*8*2*2}}, \
1787 }
1788 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1789 /* speed delays: rx00 tx00 */
1790 { SPEED_10, rxtx_x1822(40960, 40960) },
1791 { SPEED_100, rxtx_x1822( 2560, 2560) },
1792 { SPEED_1000, rxtx_x1822( 320, 320) },
1793 { 0 },
1794 };
1795
1796 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1797 /* speed delays: rx00 tx00 */
1798 { SPEED_10, rxtx_x1822(40960, 40960) },
1799 { SPEED_100, rxtx_x1822( 2560, 2560) },
1800 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1801 { 0 },
1802 };
1803 #undef rxtx_x1822
1804
1805 /* get rx/tx scale vector corresponding to current speed */
1806 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1807 {
1808 struct rtl8169_private *tp = netdev_priv(dev);
1809 struct ethtool_link_ksettings ecmd;
1810 const struct rtl_coalesce_info *ci;
1811 int rc;
1812
1813 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1814 if (rc < 0)
1815 return ERR_PTR(rc);
1816
1817 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1818 if (ecmd.base.speed == ci->speed) {
1819 return ci;
1820 }
1821 }
1822
1823 return ERR_PTR(-ELNRNG);
1824 }
1825
1826 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1827 {
1828 struct rtl8169_private *tp = netdev_priv(dev);
1829 const struct rtl_coalesce_info *ci;
1830 const struct rtl_coalesce_scale *scale;
1831 struct {
1832 u32 *max_frames;
1833 u32 *usecs;
1834 } coal_settings [] = {
1835 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1836 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1837 }, *p = coal_settings;
1838 int i;
1839 u16 w;
1840
1841 memset(ec, 0, sizeof(*ec));
1842
1843 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1844 ci = rtl_coalesce_info(dev);
1845 if (IS_ERR(ci))
1846 return PTR_ERR(ci);
1847
1848 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1849
1850 /* read IntrMitigate and adjust according to scale */
1851 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1852 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1853 w >>= RTL_COALESCE_SHIFT;
1854 *p->usecs = w & RTL_COALESCE_MASK;
1855 }
1856
1857 for (i = 0; i < 2; i++) {
1858 p = coal_settings + i;
1859 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1860
1861 /*
1862 * ethtool_coalesce says it is illegal to set both usecs and
1863 * max_frames to 0.
1864 */
1865 if (!*p->usecs && !*p->max_frames)
1866 *p->max_frames = 1;
1867 }
1868
1869 return 0;
1870 }
1871
1872 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1873 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1874 struct net_device *dev, u32 nsec, u16 *cp01)
1875 {
1876 const struct rtl_coalesce_info *ci;
1877 u16 i;
1878
1879 ci = rtl_coalesce_info(dev);
1880 if (IS_ERR(ci))
1881 return ERR_CAST(ci);
1882
1883 for (i = 0; i < 4; i++) {
1884 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1885 ci->scalev[i].nsecs[1]);
1886 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1887 *cp01 = i;
1888 return &ci->scalev[i];
1889 }
1890 }
1891
1892 return ERR_PTR(-EINVAL);
1893 }
1894
1895 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1896 {
1897 struct rtl8169_private *tp = netdev_priv(dev);
1898 const struct rtl_coalesce_scale *scale;
1899 struct {
1900 u32 frames;
1901 u32 usecs;
1902 } coal_settings [] = {
1903 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1904 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1905 }, *p = coal_settings;
1906 u16 w = 0, cp01;
1907 int i;
1908
1909 scale = rtl_coalesce_choose_scale(dev,
1910 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1911 if (IS_ERR(scale))
1912 return PTR_ERR(scale);
1913
1914 for (i = 0; i < 2; i++, p++) {
1915 u32 units;
1916
1917 /*
1918 * accept max_frames=1 we returned in rtl_get_coalesce.
1919 * accept it not only when usecs=0 because of e.g. the following scenario:
1920 *
1921 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1922 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1923 * - then user does `ethtool -C eth0 rx-usecs 100`
1924 *
1925 * since ethtool sends to kernel whole ethtool_coalesce
1926 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1927 * we'll reject it below in `frames % 4 != 0`.
1928 */
1929 if (p->frames == 1) {
1930 p->frames = 0;
1931 }
1932
1933 units = p->usecs * 1000 / scale->nsecs[i];
1934 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1935 return -EINVAL;
1936
1937 w <<= RTL_COALESCE_SHIFT;
1938 w |= units;
1939 w <<= RTL_COALESCE_SHIFT;
1940 w |= p->frames >> 2;
1941 }
1942
1943 rtl_lock_work(tp);
1944
1945 RTL_W16(tp, IntrMitigate, swab16(w));
1946
1947 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1948 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1949 RTL_R16(tp, CPlusCmd);
1950
1951 rtl_unlock_work(tp);
1952
1953 return 0;
1954 }
1955
1956 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1957 {
1958 struct phy_device *phydev = tp->phydev;
1959 int ret;
1960
1961 switch (tp->mac_version) {
1962 case RTL_GIGA_MAC_VER_34:
1963 case RTL_GIGA_MAC_VER_35:
1964 case RTL_GIGA_MAC_VER_36:
1965 case RTL_GIGA_MAC_VER_38:
1966 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1967 break;
1968 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1969 phy_write(phydev, 0x1f, 0x0a5c);
1970 ret = phy_read(phydev, 0x12);
1971 phy_write(phydev, 0x1f, 0x0000);
1972 break;
1973 default:
1974 ret = -EPROTONOSUPPORT;
1975 break;
1976 }
1977
1978 return ret;
1979 }
1980
1981 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1982 {
1983 struct phy_device *phydev = tp->phydev;
1984 int ret;
1985
1986 switch (tp->mac_version) {
1987 case RTL_GIGA_MAC_VER_34:
1988 case RTL_GIGA_MAC_VER_35:
1989 case RTL_GIGA_MAC_VER_36:
1990 case RTL_GIGA_MAC_VER_38:
1991 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1992 break;
1993 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1994 phy_write(phydev, 0x1f, 0x0a5d);
1995 ret = phy_read(phydev, 0x11);
1996 phy_write(phydev, 0x1f, 0x0000);
1997 break;
1998 default:
1999 ret = -EPROTONOSUPPORT;
2000 break;
2001 }
2002
2003 return ret;
2004 }
2005
2006 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2007 {
2008 struct phy_device *phydev = tp->phydev;
2009 int ret;
2010
2011 switch (tp->mac_version) {
2012 case RTL_GIGA_MAC_VER_34:
2013 case RTL_GIGA_MAC_VER_35:
2014 case RTL_GIGA_MAC_VER_36:
2015 case RTL_GIGA_MAC_VER_38:
2016 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2017 break;
2018 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2019 phy_write(phydev, 0x1f, 0x0a5d);
2020 ret = phy_read(phydev, 0x10);
2021 phy_write(phydev, 0x1f, 0x0000);
2022 break;
2023 default:
2024 ret = -EPROTONOSUPPORT;
2025 break;
2026 }
2027
2028 return ret;
2029 }
2030
2031 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2032 {
2033 struct phy_device *phydev = tp->phydev;
2034 int ret = 0;
2035
2036 switch (tp->mac_version) {
2037 case RTL_GIGA_MAC_VER_34:
2038 case RTL_GIGA_MAC_VER_35:
2039 case RTL_GIGA_MAC_VER_36:
2040 case RTL_GIGA_MAC_VER_38:
2041 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2042 break;
2043 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2044 phy_write(phydev, 0x1f, 0x0a5d);
2045 phy_write(phydev, 0x10, val);
2046 phy_write(phydev, 0x1f, 0x0000);
2047 break;
2048 default:
2049 ret = -EPROTONOSUPPORT;
2050 break;
2051 }
2052
2053 return ret;
2054 }
2055
2056 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2057 {
2058 struct rtl8169_private *tp = netdev_priv(dev);
2059 struct device *d = tp_to_dev(tp);
2060 int ret;
2061
2062 pm_runtime_get_noresume(d);
2063
2064 if (!pm_runtime_active(d)) {
2065 ret = -EOPNOTSUPP;
2066 goto out;
2067 }
2068
2069 /* Get Supported EEE */
2070 ret = rtl_get_eee_supp(tp);
2071 if (ret < 0)
2072 goto out;
2073 data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2074
2075 /* Get advertisement EEE */
2076 ret = rtl_get_eee_adv(tp);
2077 if (ret < 0)
2078 goto out;
2079 data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2080 data->eee_enabled = !!data->advertised;
2081
2082 /* Get LP advertisement EEE */
2083 ret = rtl_get_eee_lpadv(tp);
2084 if (ret < 0)
2085 goto out;
2086 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2087 data->eee_active = !!(data->advertised & data->lp_advertised);
2088 out:
2089 pm_runtime_put_noidle(d);
2090 return ret < 0 ? ret : 0;
2091 }
2092
2093 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2094 {
2095 struct rtl8169_private *tp = netdev_priv(dev);
2096 struct device *d = tp_to_dev(tp);
2097 int old_adv, adv = 0, cap, ret;
2098
2099 pm_runtime_get_noresume(d);
2100
2101 if (!dev->phydev || !pm_runtime_active(d)) {
2102 ret = -EOPNOTSUPP;
2103 goto out;
2104 }
2105
2106 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2107 dev->phydev->duplex != DUPLEX_FULL) {
2108 ret = -EPROTONOSUPPORT;
2109 goto out;
2110 }
2111
2112 /* Get Supported EEE */
2113 ret = rtl_get_eee_supp(tp);
2114 if (ret < 0)
2115 goto out;
2116 cap = ret;
2117
2118 ret = rtl_get_eee_adv(tp);
2119 if (ret < 0)
2120 goto out;
2121 old_adv = ret;
2122
2123 if (data->eee_enabled) {
2124 adv = !data->advertised ? cap :
2125 ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2126 /* Mask prohibited EEE modes */
2127 adv &= ~dev->phydev->eee_broken_modes;
2128 }
2129
2130 if (old_adv != adv) {
2131 ret = rtl_set_eee_adv(tp, adv);
2132 if (ret < 0)
2133 goto out;
2134
2135 /* Restart autonegotiation so the new modes get sent to the
2136 * link partner.
2137 */
2138 ret = phy_restart_aneg(dev->phydev);
2139 }
2140
2141 out:
2142 pm_runtime_put_noidle(d);
2143 return ret < 0 ? ret : 0;
2144 }
2145
2146 static const struct ethtool_ops rtl8169_ethtool_ops = {
2147 .get_drvinfo = rtl8169_get_drvinfo,
2148 .get_regs_len = rtl8169_get_regs_len,
2149 .get_link = ethtool_op_get_link,
2150 .get_coalesce = rtl_get_coalesce,
2151 .set_coalesce = rtl_set_coalesce,
2152 .get_msglevel = rtl8169_get_msglevel,
2153 .set_msglevel = rtl8169_set_msglevel,
2154 .get_regs = rtl8169_get_regs,
2155 .get_wol = rtl8169_get_wol,
2156 .set_wol = rtl8169_set_wol,
2157 .get_strings = rtl8169_get_strings,
2158 .get_sset_count = rtl8169_get_sset_count,
2159 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2160 .get_ts_info = ethtool_op_get_ts_info,
2161 .nway_reset = phy_ethtool_nway_reset,
2162 .get_eee = rtl8169_get_eee,
2163 .set_eee = rtl8169_set_eee,
2164 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2165 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2166 };
2167
2168 static void rtl_enable_eee(struct rtl8169_private *tp)
2169 {
2170 int supported = rtl_get_eee_supp(tp);
2171
2172 if (supported > 0)
2173 rtl_set_eee_adv(tp, supported);
2174 }
2175
2176 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2177 {
2178 /*
2179 * The driver currently handles the 8168Bf and the 8168Be identically
2180 * but they can be identified more specifically through the test below
2181 * if needed:
2182 *
2183 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2184 *
2185 * Same thing for the 8101Eb and the 8101Ec:
2186 *
2187 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2188 */
2189 static const struct rtl_mac_info {
2190 u16 mask;
2191 u16 val;
2192 u16 mac_version;
2193 } mac_info[] = {
2194 /* 8168EP family. */
2195 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2196 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2197 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2198
2199 /* 8168H family. */
2200 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2201 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2202
2203 /* 8168G family. */
2204 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2205 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2206 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2207 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2208
2209 /* 8168F family. */
2210 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2211 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2212 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2213
2214 /* 8168E family. */
2215 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2216 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2217 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2218
2219 /* 8168D family. */
2220 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2221 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2222
2223 /* 8168DP family. */
2224 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2225 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2226 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2227
2228 /* 8168C family. */
2229 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2230 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2231 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2232 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2233 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2234 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2235 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2236
2237 /* 8168B family. */
2238 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2239 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2240 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2241
2242 /* 8101 family. */
2243 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2244 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2245 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2246 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2247 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2248 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2249 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2250 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2251 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2252 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2253 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2254 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2255 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2256 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2257 /* FIXME: where did these entries come from ? -- FR */
2258 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2259 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2260
2261 /* 8110 family. */
2262 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2263 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2264 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2265 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2266 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2267 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2268
2269 /* Catch-all */
2270 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2271 };
2272 const struct rtl_mac_info *p = mac_info;
2273 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2274
2275 while ((reg & p->mask) != p->val)
2276 p++;
2277 tp->mac_version = p->mac_version;
2278
2279 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2280 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2281 } else if (!tp->supports_gmii) {
2282 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2283 tp->mac_version = RTL_GIGA_MAC_VER_43;
2284 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2285 tp->mac_version = RTL_GIGA_MAC_VER_47;
2286 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2287 tp->mac_version = RTL_GIGA_MAC_VER_48;
2288 }
2289 }
2290
2291 struct phy_reg {
2292 u16 reg;
2293 u16 val;
2294 };
2295
2296 static void rtl_writephy_batch(struct rtl8169_private *tp,
2297 const struct phy_reg *regs, int len)
2298 {
2299 while (len-- > 0) {
2300 rtl_writephy(tp, regs->reg, regs->val);
2301 regs++;
2302 }
2303 }
2304
2305 #define PHY_READ 0x00000000
2306 #define PHY_DATA_OR 0x10000000
2307 #define PHY_DATA_AND 0x20000000
2308 #define PHY_BJMPN 0x30000000
2309 #define PHY_MDIO_CHG 0x40000000
2310 #define PHY_CLEAR_READCOUNT 0x70000000
2311 #define PHY_WRITE 0x80000000
2312 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2313 #define PHY_COMP_EQ_SKIPN 0xa0000000
2314 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2315 #define PHY_WRITE_PREVIOUS 0xc0000000
2316 #define PHY_SKIPN 0xd0000000
2317 #define PHY_DELAY_MS 0xe0000000
2318
2319 struct fw_info {
2320 u32 magic;
2321 char version[RTL_VER_SIZE];
2322 __le32 fw_start;
2323 __le32 fw_len;
2324 u8 chksum;
2325 } __packed;
2326
2327 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2328
2329 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2330 {
2331 const struct firmware *fw = rtl_fw->fw;
2332 struct fw_info *fw_info = (struct fw_info *)fw->data;
2333 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2334 char *version = rtl_fw->version;
2335 bool rc = false;
2336
2337 if (fw->size < FW_OPCODE_SIZE)
2338 goto out;
2339
2340 if (!fw_info->magic) {
2341 size_t i, size, start;
2342 u8 checksum = 0;
2343
2344 if (fw->size < sizeof(*fw_info))
2345 goto out;
2346
2347 for (i = 0; i < fw->size; i++)
2348 checksum += fw->data[i];
2349 if (checksum != 0)
2350 goto out;
2351
2352 start = le32_to_cpu(fw_info->fw_start);
2353 if (start > fw->size)
2354 goto out;
2355
2356 size = le32_to_cpu(fw_info->fw_len);
2357 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2358 goto out;
2359
2360 memcpy(version, fw_info->version, RTL_VER_SIZE);
2361
2362 pa->code = (__le32 *)(fw->data + start);
2363 pa->size = size;
2364 } else {
2365 if (fw->size % FW_OPCODE_SIZE)
2366 goto out;
2367
2368 strlcpy(version, tp->fw_name, RTL_VER_SIZE);
2369
2370 pa->code = (__le32 *)fw->data;
2371 pa->size = fw->size / FW_OPCODE_SIZE;
2372 }
2373 version[RTL_VER_SIZE - 1] = 0;
2374
2375 rc = true;
2376 out:
2377 return rc;
2378 }
2379
2380 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2381 struct rtl_fw_phy_action *pa)
2382 {
2383 bool rc = false;
2384 size_t index;
2385
2386 for (index = 0; index < pa->size; index++) {
2387 u32 action = le32_to_cpu(pa->code[index]);
2388 u32 regno = (action & 0x0fff0000) >> 16;
2389
2390 switch(action & 0xf0000000) {
2391 case PHY_READ:
2392 case PHY_DATA_OR:
2393 case PHY_DATA_AND:
2394 case PHY_MDIO_CHG:
2395 case PHY_CLEAR_READCOUNT:
2396 case PHY_WRITE:
2397 case PHY_WRITE_PREVIOUS:
2398 case PHY_DELAY_MS:
2399 break;
2400
2401 case PHY_BJMPN:
2402 if (regno > index) {
2403 netif_err(tp, ifup, tp->dev,
2404 "Out of range of firmware\n");
2405 goto out;
2406 }
2407 break;
2408 case PHY_READCOUNT_EQ_SKIP:
2409 if (index + 2 >= pa->size) {
2410 netif_err(tp, ifup, tp->dev,
2411 "Out of range of firmware\n");
2412 goto out;
2413 }
2414 break;
2415 case PHY_COMP_EQ_SKIPN:
2416 case PHY_COMP_NEQ_SKIPN:
2417 case PHY_SKIPN:
2418 if (index + 1 + regno >= pa->size) {
2419 netif_err(tp, ifup, tp->dev,
2420 "Out of range of firmware\n");
2421 goto out;
2422 }
2423 break;
2424
2425 default:
2426 netif_err(tp, ifup, tp->dev,
2427 "Invalid action 0x%08x\n", action);
2428 goto out;
2429 }
2430 }
2431 rc = true;
2432 out:
2433 return rc;
2434 }
2435
2436 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2437 {
2438 struct net_device *dev = tp->dev;
2439 int rc = -EINVAL;
2440
2441 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2442 netif_err(tp, ifup, dev, "invalid firmware\n");
2443 goto out;
2444 }
2445
2446 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2447 rc = 0;
2448 out:
2449 return rc;
2450 }
2451
2452 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2453 {
2454 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2455 struct mdio_ops org, *ops = &tp->mdio_ops;
2456 u32 predata, count;
2457 size_t index;
2458
2459 predata = count = 0;
2460 org.write = ops->write;
2461 org.read = ops->read;
2462
2463 for (index = 0; index < pa->size; ) {
2464 u32 action = le32_to_cpu(pa->code[index]);
2465 u32 data = action & 0x0000ffff;
2466 u32 regno = (action & 0x0fff0000) >> 16;
2467
2468 if (!action)
2469 break;
2470
2471 switch(action & 0xf0000000) {
2472 case PHY_READ:
2473 predata = rtl_readphy(tp, regno);
2474 count++;
2475 index++;
2476 break;
2477 case PHY_DATA_OR:
2478 predata |= data;
2479 index++;
2480 break;
2481 case PHY_DATA_AND:
2482 predata &= data;
2483 index++;
2484 break;
2485 case PHY_BJMPN:
2486 index -= regno;
2487 break;
2488 case PHY_MDIO_CHG:
2489 if (data == 0) {
2490 ops->write = org.write;
2491 ops->read = org.read;
2492 } else if (data == 1) {
2493 ops->write = mac_mcu_write;
2494 ops->read = mac_mcu_read;
2495 }
2496
2497 index++;
2498 break;
2499 case PHY_CLEAR_READCOUNT:
2500 count = 0;
2501 index++;
2502 break;
2503 case PHY_WRITE:
2504 rtl_writephy(tp, regno, data);
2505 index++;
2506 break;
2507 case PHY_READCOUNT_EQ_SKIP:
2508 index += (count == data) ? 2 : 1;
2509 break;
2510 case PHY_COMP_EQ_SKIPN:
2511 if (predata == data)
2512 index += regno;
2513 index++;
2514 break;
2515 case PHY_COMP_NEQ_SKIPN:
2516 if (predata != data)
2517 index += regno;
2518 index++;
2519 break;
2520 case PHY_WRITE_PREVIOUS:
2521 rtl_writephy(tp, regno, predata);
2522 index++;
2523 break;
2524 case PHY_SKIPN:
2525 index += regno + 1;
2526 break;
2527 case PHY_DELAY_MS:
2528 mdelay(data);
2529 index++;
2530 break;
2531
2532 default:
2533 BUG();
2534 }
2535 }
2536
2537 ops->write = org.write;
2538 ops->read = org.read;
2539 }
2540
2541 static void rtl_release_firmware(struct rtl8169_private *tp)
2542 {
2543 if (tp->rtl_fw) {
2544 release_firmware(tp->rtl_fw->fw);
2545 kfree(tp->rtl_fw);
2546 tp->rtl_fw = NULL;
2547 }
2548 }
2549
2550 static void rtl_apply_firmware(struct rtl8169_private *tp)
2551 {
2552 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2553 if (tp->rtl_fw)
2554 rtl_phy_write_fw(tp, tp->rtl_fw);
2555 }
2556
2557 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2558 {
2559 if (rtl_readphy(tp, reg) != val)
2560 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2561 else
2562 rtl_apply_firmware(tp);
2563 }
2564
2565 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2566 {
2567 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
2568 }
2569
2570 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2571 {
2572 struct phy_device *phydev = tp->phydev;
2573
2574 phy_write(phydev, 0x1f, 0x0007);
2575 phy_write(phydev, 0x1e, 0x0020);
2576 phy_set_bits(phydev, 0x15, BIT(8));
2577
2578 phy_write(phydev, 0x1f, 0x0005);
2579 phy_write(phydev, 0x05, 0x8b85);
2580 phy_set_bits(phydev, 0x06, BIT(13));
2581
2582 phy_write(phydev, 0x1f, 0x0000);
2583 }
2584
2585 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2586 {
2587 phy_write(tp->phydev, 0x1f, 0x0a43);
2588 phy_set_bits(tp->phydev, 0x11, BIT(4));
2589 phy_write(tp->phydev, 0x1f, 0x0000);
2590 }
2591
2592 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2593 {
2594 static const struct phy_reg phy_reg_init[] = {
2595 { 0x1f, 0x0001 },
2596 { 0x06, 0x006e },
2597 { 0x08, 0x0708 },
2598 { 0x15, 0x4000 },
2599 { 0x18, 0x65c7 },
2600
2601 { 0x1f, 0x0001 },
2602 { 0x03, 0x00a1 },
2603 { 0x02, 0x0008 },
2604 { 0x01, 0x0120 },
2605 { 0x00, 0x1000 },
2606 { 0x04, 0x0800 },
2607 { 0x04, 0x0000 },
2608
2609 { 0x03, 0xff41 },
2610 { 0x02, 0xdf60 },
2611 { 0x01, 0x0140 },
2612 { 0x00, 0x0077 },
2613 { 0x04, 0x7800 },
2614 { 0x04, 0x7000 },
2615
2616 { 0x03, 0x802f },
2617 { 0x02, 0x4f02 },
2618 { 0x01, 0x0409 },
2619 { 0x00, 0xf0f9 },
2620 { 0x04, 0x9800 },
2621 { 0x04, 0x9000 },
2622
2623 { 0x03, 0xdf01 },
2624 { 0x02, 0xdf20 },
2625 { 0x01, 0xff95 },
2626 { 0x00, 0xba00 },
2627 { 0x04, 0xa800 },
2628 { 0x04, 0xa000 },
2629
2630 { 0x03, 0xff41 },
2631 { 0x02, 0xdf20 },
2632 { 0x01, 0x0140 },
2633 { 0x00, 0x00bb },
2634 { 0x04, 0xb800 },
2635 { 0x04, 0xb000 },
2636
2637 { 0x03, 0xdf41 },
2638 { 0x02, 0xdc60 },
2639 { 0x01, 0x6340 },
2640 { 0x00, 0x007d },
2641 { 0x04, 0xd800 },
2642 { 0x04, 0xd000 },
2643
2644 { 0x03, 0xdf01 },
2645 { 0x02, 0xdf20 },
2646 { 0x01, 0x100a },
2647 { 0x00, 0xa0ff },
2648 { 0x04, 0xf800 },
2649 { 0x04, 0xf000 },
2650
2651 { 0x1f, 0x0000 },
2652 { 0x0b, 0x0000 },
2653 { 0x00, 0x9200 }
2654 };
2655
2656 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2657 }
2658
2659 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2660 {
2661 static const struct phy_reg phy_reg_init[] = {
2662 { 0x1f, 0x0002 },
2663 { 0x01, 0x90d0 },
2664 { 0x1f, 0x0000 }
2665 };
2666
2667 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2668 }
2669
2670 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2671 {
2672 struct pci_dev *pdev = tp->pci_dev;
2673
2674 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2675 (pdev->subsystem_device != 0xe000))
2676 return;
2677
2678 rtl_writephy(tp, 0x1f, 0x0001);
2679 rtl_writephy(tp, 0x10, 0xf01b);
2680 rtl_writephy(tp, 0x1f, 0x0000);
2681 }
2682
2683 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2684 {
2685 static const struct phy_reg phy_reg_init[] = {
2686 { 0x1f, 0x0001 },
2687 { 0x04, 0x0000 },
2688 { 0x03, 0x00a1 },
2689 { 0x02, 0x0008 },
2690 { 0x01, 0x0120 },
2691 { 0x00, 0x1000 },
2692 { 0x04, 0x0800 },
2693 { 0x04, 0x9000 },
2694 { 0x03, 0x802f },
2695 { 0x02, 0x4f02 },
2696 { 0x01, 0x0409 },
2697 { 0x00, 0xf099 },
2698 { 0x04, 0x9800 },
2699 { 0x04, 0xa000 },
2700 { 0x03, 0xdf01 },
2701 { 0x02, 0xdf20 },
2702 { 0x01, 0xff95 },
2703 { 0x00, 0xba00 },
2704 { 0x04, 0xa800 },
2705 { 0x04, 0xf000 },
2706 { 0x03, 0xdf01 },
2707 { 0x02, 0xdf20 },
2708 { 0x01, 0x101a },
2709 { 0x00, 0xa0ff },
2710 { 0x04, 0xf800 },
2711 { 0x04, 0x0000 },
2712 { 0x1f, 0x0000 },
2713
2714 { 0x1f, 0x0001 },
2715 { 0x10, 0xf41b },
2716 { 0x14, 0xfb54 },
2717 { 0x18, 0xf5c7 },
2718 { 0x1f, 0x0000 },
2719
2720 { 0x1f, 0x0001 },
2721 { 0x17, 0x0cc0 },
2722 { 0x1f, 0x0000 }
2723 };
2724
2725 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2726
2727 rtl8169scd_hw_phy_config_quirk(tp);
2728 }
2729
2730 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2731 {
2732 static const struct phy_reg phy_reg_init[] = {
2733 { 0x1f, 0x0001 },
2734 { 0x04, 0x0000 },
2735 { 0x03, 0x00a1 },
2736 { 0x02, 0x0008 },
2737 { 0x01, 0x0120 },
2738 { 0x00, 0x1000 },
2739 { 0x04, 0x0800 },
2740 { 0x04, 0x9000 },
2741 { 0x03, 0x802f },
2742 { 0x02, 0x4f02 },
2743 { 0x01, 0x0409 },
2744 { 0x00, 0xf099 },
2745 { 0x04, 0x9800 },
2746 { 0x04, 0xa000 },
2747 { 0x03, 0xdf01 },
2748 { 0x02, 0xdf20 },
2749 { 0x01, 0xff95 },
2750 { 0x00, 0xba00 },
2751 { 0x04, 0xa800 },
2752 { 0x04, 0xf000 },
2753 { 0x03, 0xdf01 },
2754 { 0x02, 0xdf20 },
2755 { 0x01, 0x101a },
2756 { 0x00, 0xa0ff },
2757 { 0x04, 0xf800 },
2758 { 0x04, 0x0000 },
2759 { 0x1f, 0x0000 },
2760
2761 { 0x1f, 0x0001 },
2762 { 0x0b, 0x8480 },
2763 { 0x1f, 0x0000 },
2764
2765 { 0x1f, 0x0001 },
2766 { 0x18, 0x67c7 },
2767 { 0x04, 0x2000 },
2768 { 0x03, 0x002f },
2769 { 0x02, 0x4360 },
2770 { 0x01, 0x0109 },
2771 { 0x00, 0x3022 },
2772 { 0x04, 0x2800 },
2773 { 0x1f, 0x0000 },
2774
2775 { 0x1f, 0x0001 },
2776 { 0x17, 0x0cc0 },
2777 { 0x1f, 0x0000 }
2778 };
2779
2780 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2781 }
2782
2783 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2784 {
2785 static const struct phy_reg phy_reg_init[] = {
2786 { 0x10, 0xf41b },
2787 { 0x1f, 0x0000 }
2788 };
2789
2790 rtl_writephy(tp, 0x1f, 0x0001);
2791 rtl_patchphy(tp, 0x16, 1 << 0);
2792
2793 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2794 }
2795
2796 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2797 {
2798 static const struct phy_reg phy_reg_init[] = {
2799 { 0x1f, 0x0001 },
2800 { 0x10, 0xf41b },
2801 { 0x1f, 0x0000 }
2802 };
2803
2804 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2805 }
2806
2807 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2808 {
2809 static const struct phy_reg phy_reg_init[] = {
2810 { 0x1f, 0x0000 },
2811 { 0x1d, 0x0f00 },
2812 { 0x1f, 0x0002 },
2813 { 0x0c, 0x1ec8 },
2814 { 0x1f, 0x0000 }
2815 };
2816
2817 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2818 }
2819
2820 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2821 {
2822 static const struct phy_reg phy_reg_init[] = {
2823 { 0x1f, 0x0001 },
2824 { 0x1d, 0x3d98 },
2825 { 0x1f, 0x0000 }
2826 };
2827
2828 rtl_writephy(tp, 0x1f, 0x0000);
2829 rtl_patchphy(tp, 0x14, 1 << 5);
2830 rtl_patchphy(tp, 0x0d, 1 << 5);
2831
2832 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2833 }
2834
2835 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2836 {
2837 static const struct phy_reg phy_reg_init[] = {
2838 { 0x1f, 0x0001 },
2839 { 0x12, 0x2300 },
2840 { 0x1f, 0x0002 },
2841 { 0x00, 0x88d4 },
2842 { 0x01, 0x82b1 },
2843 { 0x03, 0x7002 },
2844 { 0x08, 0x9e30 },
2845 { 0x09, 0x01f0 },
2846 { 0x0a, 0x5500 },
2847 { 0x0c, 0x00c8 },
2848 { 0x1f, 0x0003 },
2849 { 0x12, 0xc096 },
2850 { 0x16, 0x000a },
2851 { 0x1f, 0x0000 },
2852 { 0x1f, 0x0000 },
2853 { 0x09, 0x2000 },
2854 { 0x09, 0x0000 }
2855 };
2856
2857 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2858
2859 rtl_patchphy(tp, 0x14, 1 << 5);
2860 rtl_patchphy(tp, 0x0d, 1 << 5);
2861 rtl_writephy(tp, 0x1f, 0x0000);
2862 }
2863
2864 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2865 {
2866 static const struct phy_reg phy_reg_init[] = {
2867 { 0x1f, 0x0001 },
2868 { 0x12, 0x2300 },
2869 { 0x03, 0x802f },
2870 { 0x02, 0x4f02 },
2871 { 0x01, 0x0409 },
2872 { 0x00, 0xf099 },
2873 { 0x04, 0x9800 },
2874 { 0x04, 0x9000 },
2875 { 0x1d, 0x3d98 },
2876 { 0x1f, 0x0002 },
2877 { 0x0c, 0x7eb8 },
2878 { 0x06, 0x0761 },
2879 { 0x1f, 0x0003 },
2880 { 0x16, 0x0f0a },
2881 { 0x1f, 0x0000 }
2882 };
2883
2884 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2885
2886 rtl_patchphy(tp, 0x16, 1 << 0);
2887 rtl_patchphy(tp, 0x14, 1 << 5);
2888 rtl_patchphy(tp, 0x0d, 1 << 5);
2889 rtl_writephy(tp, 0x1f, 0x0000);
2890 }
2891
2892 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2893 {
2894 static const struct phy_reg phy_reg_init[] = {
2895 { 0x1f, 0x0001 },
2896 { 0x12, 0x2300 },
2897 { 0x1d, 0x3d98 },
2898 { 0x1f, 0x0002 },
2899 { 0x0c, 0x7eb8 },
2900 { 0x06, 0x5461 },
2901 { 0x1f, 0x0003 },
2902 { 0x16, 0x0f0a },
2903 { 0x1f, 0x0000 }
2904 };
2905
2906 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2907
2908 rtl_patchphy(tp, 0x16, 1 << 0);
2909 rtl_patchphy(tp, 0x14, 1 << 5);
2910 rtl_patchphy(tp, 0x0d, 1 << 5);
2911 rtl_writephy(tp, 0x1f, 0x0000);
2912 }
2913
2914 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2915 {
2916 rtl8168c_3_hw_phy_config(tp);
2917 }
2918
2919 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2920 {
2921 static const struct phy_reg phy_reg_init_0[] = {
2922 /* Channel Estimation */
2923 { 0x1f, 0x0001 },
2924 { 0x06, 0x4064 },
2925 { 0x07, 0x2863 },
2926 { 0x08, 0x059c },
2927 { 0x09, 0x26b4 },
2928 { 0x0a, 0x6a19 },
2929 { 0x0b, 0xdcc8 },
2930 { 0x10, 0xf06d },
2931 { 0x14, 0x7f68 },
2932 { 0x18, 0x7fd9 },
2933 { 0x1c, 0xf0ff },
2934 { 0x1d, 0x3d9c },
2935 { 0x1f, 0x0003 },
2936 { 0x12, 0xf49f },
2937 { 0x13, 0x070b },
2938 { 0x1a, 0x05ad },
2939 { 0x14, 0x94c0 },
2940
2941 /*
2942 * Tx Error Issue
2943 * Enhance line driver power
2944 */
2945 { 0x1f, 0x0002 },
2946 { 0x06, 0x5561 },
2947 { 0x1f, 0x0005 },
2948 { 0x05, 0x8332 },
2949 { 0x06, 0x5561 },
2950
2951 /*
2952 * Can not link to 1Gbps with bad cable
2953 * Decrease SNR threshold form 21.07dB to 19.04dB
2954 */
2955 { 0x1f, 0x0001 },
2956 { 0x17, 0x0cc0 },
2957
2958 { 0x1f, 0x0000 },
2959 { 0x0d, 0xf880 }
2960 };
2961
2962 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2963
2964 /*
2965 * Rx Error Issue
2966 * Fine Tune Switching regulator parameter
2967 */
2968 rtl_writephy(tp, 0x1f, 0x0002);
2969 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2970 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2971
2972 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2973 static const struct phy_reg phy_reg_init[] = {
2974 { 0x1f, 0x0002 },
2975 { 0x05, 0x669a },
2976 { 0x1f, 0x0005 },
2977 { 0x05, 0x8330 },
2978 { 0x06, 0x669a },
2979 { 0x1f, 0x0002 }
2980 };
2981 int val;
2982
2983 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2984
2985 val = rtl_readphy(tp, 0x0d);
2986
2987 if ((val & 0x00ff) != 0x006c) {
2988 static const u32 set[] = {
2989 0x0065, 0x0066, 0x0067, 0x0068,
2990 0x0069, 0x006a, 0x006b, 0x006c
2991 };
2992 int i;
2993
2994 rtl_writephy(tp, 0x1f, 0x0002);
2995
2996 val &= 0xff00;
2997 for (i = 0; i < ARRAY_SIZE(set); i++)
2998 rtl_writephy(tp, 0x0d, val | set[i]);
2999 }
3000 } else {
3001 static const struct phy_reg phy_reg_init[] = {
3002 { 0x1f, 0x0002 },
3003 { 0x05, 0x6662 },
3004 { 0x1f, 0x0005 },
3005 { 0x05, 0x8330 },
3006 { 0x06, 0x6662 }
3007 };
3008
3009 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3010 }
3011
3012 /* RSET couple improve */
3013 rtl_writephy(tp, 0x1f, 0x0002);
3014 rtl_patchphy(tp, 0x0d, 0x0300);
3015 rtl_patchphy(tp, 0x0f, 0x0010);
3016
3017 /* Fine tune PLL performance */
3018 rtl_writephy(tp, 0x1f, 0x0002);
3019 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3020 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3021
3022 rtl_writephy(tp, 0x1f, 0x0005);
3023 rtl_writephy(tp, 0x05, 0x001b);
3024
3025 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3026
3027 rtl_writephy(tp, 0x1f, 0x0000);
3028 }
3029
3030 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3031 {
3032 static const struct phy_reg phy_reg_init_0[] = {
3033 /* Channel Estimation */
3034 { 0x1f, 0x0001 },
3035 { 0x06, 0x4064 },
3036 { 0x07, 0x2863 },
3037 { 0x08, 0x059c },
3038 { 0x09, 0x26b4 },
3039 { 0x0a, 0x6a19 },
3040 { 0x0b, 0xdcc8 },
3041 { 0x10, 0xf06d },
3042 { 0x14, 0x7f68 },
3043 { 0x18, 0x7fd9 },
3044 { 0x1c, 0xf0ff },
3045 { 0x1d, 0x3d9c },
3046 { 0x1f, 0x0003 },
3047 { 0x12, 0xf49f },
3048 { 0x13, 0x070b },
3049 { 0x1a, 0x05ad },
3050 { 0x14, 0x94c0 },
3051
3052 /*
3053 * Tx Error Issue
3054 * Enhance line driver power
3055 */
3056 { 0x1f, 0x0002 },
3057 { 0x06, 0x5561 },
3058 { 0x1f, 0x0005 },
3059 { 0x05, 0x8332 },
3060 { 0x06, 0x5561 },
3061
3062 /*
3063 * Can not link to 1Gbps with bad cable
3064 * Decrease SNR threshold form 21.07dB to 19.04dB
3065 */
3066 { 0x1f, 0x0001 },
3067 { 0x17, 0x0cc0 },
3068
3069 { 0x1f, 0x0000 },
3070 { 0x0d, 0xf880 }
3071 };
3072
3073 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3074
3075 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3076 static const struct phy_reg phy_reg_init[] = {
3077 { 0x1f, 0x0002 },
3078 { 0x05, 0x669a },
3079 { 0x1f, 0x0005 },
3080 { 0x05, 0x8330 },
3081 { 0x06, 0x669a },
3082
3083 { 0x1f, 0x0002 }
3084 };
3085 int val;
3086
3087 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3088
3089 val = rtl_readphy(tp, 0x0d);
3090 if ((val & 0x00ff) != 0x006c) {
3091 static const u32 set[] = {
3092 0x0065, 0x0066, 0x0067, 0x0068,
3093 0x0069, 0x006a, 0x006b, 0x006c
3094 };
3095 int i;
3096
3097 rtl_writephy(tp, 0x1f, 0x0002);
3098
3099 val &= 0xff00;
3100 for (i = 0; i < ARRAY_SIZE(set); i++)
3101 rtl_writephy(tp, 0x0d, val | set[i]);
3102 }
3103 } else {
3104 static const struct phy_reg phy_reg_init[] = {
3105 { 0x1f, 0x0002 },
3106 { 0x05, 0x2642 },
3107 { 0x1f, 0x0005 },
3108 { 0x05, 0x8330 },
3109 { 0x06, 0x2642 }
3110 };
3111
3112 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3113 }
3114
3115 /* Fine tune PLL performance */
3116 rtl_writephy(tp, 0x1f, 0x0002);
3117 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3118 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3119
3120 /* Switching regulator Slew rate */
3121 rtl_writephy(tp, 0x1f, 0x0002);
3122 rtl_patchphy(tp, 0x0f, 0x0017);
3123
3124 rtl_writephy(tp, 0x1f, 0x0005);
3125 rtl_writephy(tp, 0x05, 0x001b);
3126
3127 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3128
3129 rtl_writephy(tp, 0x1f, 0x0000);
3130 }
3131
3132 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3133 {
3134 static const struct phy_reg phy_reg_init[] = {
3135 { 0x1f, 0x0002 },
3136 { 0x10, 0x0008 },
3137 { 0x0d, 0x006c },
3138
3139 { 0x1f, 0x0000 },
3140 { 0x0d, 0xf880 },
3141
3142 { 0x1f, 0x0001 },
3143 { 0x17, 0x0cc0 },
3144
3145 { 0x1f, 0x0001 },
3146 { 0x0b, 0xa4d8 },
3147 { 0x09, 0x281c },
3148 { 0x07, 0x2883 },
3149 { 0x0a, 0x6b35 },
3150 { 0x1d, 0x3da4 },
3151 { 0x1c, 0xeffd },
3152 { 0x14, 0x7f52 },
3153 { 0x18, 0x7fc6 },
3154 { 0x08, 0x0601 },
3155 { 0x06, 0x4063 },
3156 { 0x10, 0xf074 },
3157 { 0x1f, 0x0003 },
3158 { 0x13, 0x0789 },
3159 { 0x12, 0xf4bd },
3160 { 0x1a, 0x04fd },
3161 { 0x14, 0x84b0 },
3162 { 0x1f, 0x0000 },
3163 { 0x00, 0x9200 },
3164
3165 { 0x1f, 0x0005 },
3166 { 0x01, 0x0340 },
3167 { 0x1f, 0x0001 },
3168 { 0x04, 0x4000 },
3169 { 0x03, 0x1d21 },
3170 { 0x02, 0x0c32 },
3171 { 0x01, 0x0200 },
3172 { 0x00, 0x5554 },
3173 { 0x04, 0x4800 },
3174 { 0x04, 0x4000 },
3175 { 0x04, 0xf000 },
3176 { 0x03, 0xdf01 },
3177 { 0x02, 0xdf20 },
3178 { 0x01, 0x101a },
3179 { 0x00, 0xa0ff },
3180 { 0x04, 0xf800 },
3181 { 0x04, 0xf000 },
3182 { 0x1f, 0x0000 },
3183
3184 { 0x1f, 0x0007 },
3185 { 0x1e, 0x0023 },
3186 { 0x16, 0x0000 },
3187 { 0x1f, 0x0000 }
3188 };
3189
3190 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3191 }
3192
3193 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3194 {
3195 static const struct phy_reg phy_reg_init[] = {
3196 { 0x1f, 0x0001 },
3197 { 0x17, 0x0cc0 },
3198
3199 { 0x1f, 0x0007 },
3200 { 0x1e, 0x002d },
3201 { 0x18, 0x0040 },
3202 { 0x1f, 0x0000 }
3203 };
3204
3205 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3206 rtl_patchphy(tp, 0x0d, 1 << 5);
3207 }
3208
3209 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3210 {
3211 static const struct phy_reg phy_reg_init[] = {
3212 /* Enable Delay cap */
3213 { 0x1f, 0x0005 },
3214 { 0x05, 0x8b80 },
3215 { 0x06, 0xc896 },
3216 { 0x1f, 0x0000 },
3217
3218 /* Channel estimation fine tune */
3219 { 0x1f, 0x0001 },
3220 { 0x0b, 0x6c20 },
3221 { 0x07, 0x2872 },
3222 { 0x1c, 0xefff },
3223 { 0x1f, 0x0003 },
3224 { 0x14, 0x6420 },
3225 { 0x1f, 0x0000 },
3226
3227 /* Update PFM & 10M TX idle timer */
3228 { 0x1f, 0x0007 },
3229 { 0x1e, 0x002f },
3230 { 0x15, 0x1919 },
3231 { 0x1f, 0x0000 },
3232
3233 { 0x1f, 0x0007 },
3234 { 0x1e, 0x00ac },
3235 { 0x18, 0x0006 },
3236 { 0x1f, 0x0000 }
3237 };
3238
3239 rtl_apply_firmware(tp);
3240
3241 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3242
3243 /* DCO enable for 10M IDLE Power */
3244 rtl_writephy(tp, 0x1f, 0x0007);
3245 rtl_writephy(tp, 0x1e, 0x0023);
3246 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3247 rtl_writephy(tp, 0x1f, 0x0000);
3248
3249 /* For impedance matching */
3250 rtl_writephy(tp, 0x1f, 0x0002);
3251 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3252 rtl_writephy(tp, 0x1f, 0x0000);
3253
3254 /* PHY auto speed down */
3255 rtl_writephy(tp, 0x1f, 0x0007);
3256 rtl_writephy(tp, 0x1e, 0x002d);
3257 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3258 rtl_writephy(tp, 0x1f, 0x0000);
3259 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3260
3261 rtl_writephy(tp, 0x1f, 0x0005);
3262 rtl_writephy(tp, 0x05, 0x8b86);
3263 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3264 rtl_writephy(tp, 0x1f, 0x0000);
3265
3266 rtl_writephy(tp, 0x1f, 0x0005);
3267 rtl_writephy(tp, 0x05, 0x8b85);
3268 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3269 rtl_writephy(tp, 0x1f, 0x0007);
3270 rtl_writephy(tp, 0x1e, 0x0020);
3271 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3272 rtl_writephy(tp, 0x1f, 0x0006);
3273 rtl_writephy(tp, 0x00, 0x5a00);
3274 rtl_writephy(tp, 0x1f, 0x0000);
3275 rtl_writephy(tp, 0x0d, 0x0007);
3276 rtl_writephy(tp, 0x0e, 0x003c);
3277 rtl_writephy(tp, 0x0d, 0x4007);
3278 rtl_writephy(tp, 0x0e, 0x0000);
3279 rtl_writephy(tp, 0x0d, 0x0000);
3280 }
3281
3282 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3283 {
3284 const u16 w[] = {
3285 addr[0] | (addr[1] << 8),
3286 addr[2] | (addr[3] << 8),
3287 addr[4] | (addr[5] << 8)
3288 };
3289 const struct exgmac_reg e[] = {
3290 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3291 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3292 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3293 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3294 };
3295
3296 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3297 }
3298
3299 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3300 {
3301 static const struct phy_reg phy_reg_init[] = {
3302 /* Enable Delay cap */
3303 { 0x1f, 0x0004 },
3304 { 0x1f, 0x0007 },
3305 { 0x1e, 0x00ac },
3306 { 0x18, 0x0006 },
3307 { 0x1f, 0x0002 },
3308 { 0x1f, 0x0000 },
3309 { 0x1f, 0x0000 },
3310
3311 /* Channel estimation fine tune */
3312 { 0x1f, 0x0003 },
3313 { 0x09, 0xa20f },
3314 { 0x1f, 0x0000 },
3315 { 0x1f, 0x0000 },
3316
3317 /* Green Setting */
3318 { 0x1f, 0x0005 },
3319 { 0x05, 0x8b5b },
3320 { 0x06, 0x9222 },
3321 { 0x05, 0x8b6d },
3322 { 0x06, 0x8000 },
3323 { 0x05, 0x8b76 },
3324 { 0x06, 0x8000 },
3325 { 0x1f, 0x0000 }
3326 };
3327
3328 rtl_apply_firmware(tp);
3329
3330 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3331
3332 /* For 4-corner performance improve */
3333 rtl_writephy(tp, 0x1f, 0x0005);
3334 rtl_writephy(tp, 0x05, 0x8b80);
3335 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3336 rtl_writephy(tp, 0x1f, 0x0000);
3337
3338 /* PHY auto speed down */
3339 rtl_writephy(tp, 0x1f, 0x0004);
3340 rtl_writephy(tp, 0x1f, 0x0007);
3341 rtl_writephy(tp, 0x1e, 0x002d);
3342 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3343 rtl_writephy(tp, 0x1f, 0x0002);
3344 rtl_writephy(tp, 0x1f, 0x0000);
3345 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3346
3347 /* improve 10M EEE waveform */
3348 rtl_writephy(tp, 0x1f, 0x0005);
3349 rtl_writephy(tp, 0x05, 0x8b86);
3350 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3351 rtl_writephy(tp, 0x1f, 0x0000);
3352
3353 /* Improve 2-pair detection performance */
3354 rtl_writephy(tp, 0x1f, 0x0005);
3355 rtl_writephy(tp, 0x05, 0x8b85);
3356 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3357 rtl_writephy(tp, 0x1f, 0x0000);
3358
3359 rtl8168f_config_eee_phy(tp);
3360 rtl_enable_eee(tp);
3361
3362 /* Green feature */
3363 rtl_writephy(tp, 0x1f, 0x0003);
3364 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3365 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3366 rtl_writephy(tp, 0x1f, 0x0000);
3367 rtl_writephy(tp, 0x1f, 0x0005);
3368 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3369 rtl_writephy(tp, 0x1f, 0x0000);
3370
3371 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3372 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3373 }
3374
3375 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3376 {
3377 /* For 4-corner performance improve */
3378 rtl_writephy(tp, 0x1f, 0x0005);
3379 rtl_writephy(tp, 0x05, 0x8b80);
3380 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3381 rtl_writephy(tp, 0x1f, 0x0000);
3382
3383 /* PHY auto speed down */
3384 rtl_writephy(tp, 0x1f, 0x0007);
3385 rtl_writephy(tp, 0x1e, 0x002d);
3386 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3387 rtl_writephy(tp, 0x1f, 0x0000);
3388 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3389
3390 /* Improve 10M EEE waveform */
3391 rtl_writephy(tp, 0x1f, 0x0005);
3392 rtl_writephy(tp, 0x05, 0x8b86);
3393 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3394 rtl_writephy(tp, 0x1f, 0x0000);
3395
3396 rtl8168f_config_eee_phy(tp);
3397 rtl_enable_eee(tp);
3398 }
3399
3400 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3401 {
3402 static const struct phy_reg phy_reg_init[] = {
3403 /* Channel estimation fine tune */
3404 { 0x1f, 0x0003 },
3405 { 0x09, 0xa20f },
3406 { 0x1f, 0x0000 },
3407
3408 /* Modify green table for giga & fnet */
3409 { 0x1f, 0x0005 },
3410 { 0x05, 0x8b55 },
3411 { 0x06, 0x0000 },
3412 { 0x05, 0x8b5e },
3413 { 0x06, 0x0000 },
3414 { 0x05, 0x8b67 },
3415 { 0x06, 0x0000 },
3416 { 0x05, 0x8b70 },
3417 { 0x06, 0x0000 },
3418 { 0x1f, 0x0000 },
3419 { 0x1f, 0x0007 },
3420 { 0x1e, 0x0078 },
3421 { 0x17, 0x0000 },
3422 { 0x19, 0x00fb },
3423 { 0x1f, 0x0000 },
3424
3425 /* Modify green table for 10M */
3426 { 0x1f, 0x0005 },
3427 { 0x05, 0x8b79 },
3428 { 0x06, 0xaa00 },
3429 { 0x1f, 0x0000 },
3430
3431 /* Disable hiimpedance detection (RTCT) */
3432 { 0x1f, 0x0003 },
3433 { 0x01, 0x328a },
3434 { 0x1f, 0x0000 }
3435 };
3436
3437 rtl_apply_firmware(tp);
3438
3439 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3440
3441 rtl8168f_hw_phy_config(tp);
3442
3443 /* Improve 2-pair detection performance */
3444 rtl_writephy(tp, 0x1f, 0x0005);
3445 rtl_writephy(tp, 0x05, 0x8b85);
3446 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3447 rtl_writephy(tp, 0x1f, 0x0000);
3448 }
3449
3450 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3451 {
3452 rtl_apply_firmware(tp);
3453
3454 rtl8168f_hw_phy_config(tp);
3455 }
3456
3457 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3458 {
3459 static const struct phy_reg phy_reg_init[] = {
3460 /* Channel estimation fine tune */
3461 { 0x1f, 0x0003 },
3462 { 0x09, 0xa20f },
3463 { 0x1f, 0x0000 },
3464
3465 /* Modify green table for giga & fnet */
3466 { 0x1f, 0x0005 },
3467 { 0x05, 0x8b55 },
3468 { 0x06, 0x0000 },
3469 { 0x05, 0x8b5e },
3470 { 0x06, 0x0000 },
3471 { 0x05, 0x8b67 },
3472 { 0x06, 0x0000 },
3473 { 0x05, 0x8b70 },
3474 { 0x06, 0x0000 },
3475 { 0x1f, 0x0000 },
3476 { 0x1f, 0x0007 },
3477 { 0x1e, 0x0078 },
3478 { 0x17, 0x0000 },
3479 { 0x19, 0x00aa },
3480 { 0x1f, 0x0000 },
3481
3482 /* Modify green table for 10M */
3483 { 0x1f, 0x0005 },
3484 { 0x05, 0x8b79 },
3485 { 0x06, 0xaa00 },
3486 { 0x1f, 0x0000 },
3487
3488 /* Disable hiimpedance detection (RTCT) */
3489 { 0x1f, 0x0003 },
3490 { 0x01, 0x328a },
3491 { 0x1f, 0x0000 }
3492 };
3493
3494
3495 rtl_apply_firmware(tp);
3496
3497 rtl8168f_hw_phy_config(tp);
3498
3499 /* Improve 2-pair detection performance */
3500 rtl_writephy(tp, 0x1f, 0x0005);
3501 rtl_writephy(tp, 0x05, 0x8b85);
3502 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3503 rtl_writephy(tp, 0x1f, 0x0000);
3504
3505 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3506
3507 /* Modify green table for giga */
3508 rtl_writephy(tp, 0x1f, 0x0005);
3509 rtl_writephy(tp, 0x05, 0x8b54);
3510 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3511 rtl_writephy(tp, 0x05, 0x8b5d);
3512 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3513 rtl_writephy(tp, 0x05, 0x8a7c);
3514 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3515 rtl_writephy(tp, 0x05, 0x8a7f);
3516 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3517 rtl_writephy(tp, 0x05, 0x8a82);
3518 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3519 rtl_writephy(tp, 0x05, 0x8a85);
3520 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3521 rtl_writephy(tp, 0x05, 0x8a88);
3522 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3523 rtl_writephy(tp, 0x1f, 0x0000);
3524
3525 /* uc same-seed solution */
3526 rtl_writephy(tp, 0x1f, 0x0005);
3527 rtl_writephy(tp, 0x05, 0x8b85);
3528 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3529 rtl_writephy(tp, 0x1f, 0x0000);
3530
3531 /* Green feature */
3532 rtl_writephy(tp, 0x1f, 0x0003);
3533 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3534 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3535 rtl_writephy(tp, 0x1f, 0x0000);
3536 }
3537
3538 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3539 {
3540 phy_write(tp->phydev, 0x1f, 0x0a43);
3541 phy_clear_bits(tp->phydev, 0x10, BIT(2));
3542 }
3543
3544 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3545 {
3546 struct phy_device *phydev = tp->phydev;
3547
3548 phy_write(phydev, 0x1f, 0x0bcc);
3549 phy_clear_bits(phydev, 0x14, BIT(8));
3550
3551 phy_write(phydev, 0x1f, 0x0a44);
3552 phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3553
3554 phy_write(phydev, 0x1f, 0x0a43);
3555 phy_write(phydev, 0x13, 0x8084);
3556 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3557 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3558
3559 phy_write(phydev, 0x1f, 0x0000);
3560 }
3561
3562 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3563 {
3564 rtl_apply_firmware(tp);
3565
3566 rtl_writephy(tp, 0x1f, 0x0a46);
3567 if (rtl_readphy(tp, 0x10) & 0x0100) {
3568 rtl_writephy(tp, 0x1f, 0x0bcc);
3569 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3570 } else {
3571 rtl_writephy(tp, 0x1f, 0x0bcc);
3572 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3573 }
3574
3575 rtl_writephy(tp, 0x1f, 0x0a46);
3576 if (rtl_readphy(tp, 0x13) & 0x0100) {
3577 rtl_writephy(tp, 0x1f, 0x0c41);
3578 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3579 } else {
3580 rtl_writephy(tp, 0x1f, 0x0c41);
3581 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3582 }
3583
3584 /* Enable PHY auto speed down */
3585 rtl_writephy(tp, 0x1f, 0x0a44);
3586 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3587
3588 rtl8168g_phy_adjust_10m_aldps(tp);
3589
3590 /* EEE auto-fallback function */
3591 rtl_writephy(tp, 0x1f, 0x0a4b);
3592 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3593
3594 /* Enable UC LPF tune function */
3595 rtl_writephy(tp, 0x1f, 0x0a43);
3596 rtl_writephy(tp, 0x13, 0x8012);
3597 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3598
3599 rtl_writephy(tp, 0x1f, 0x0c42);
3600 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3601
3602 /* Improve SWR Efficiency */
3603 rtl_writephy(tp, 0x1f, 0x0bcd);
3604 rtl_writephy(tp, 0x14, 0x5065);
3605 rtl_writephy(tp, 0x14, 0xd065);
3606 rtl_writephy(tp, 0x1f, 0x0bc8);
3607 rtl_writephy(tp, 0x11, 0x5655);
3608 rtl_writephy(tp, 0x1f, 0x0bcd);
3609 rtl_writephy(tp, 0x14, 0x1065);
3610 rtl_writephy(tp, 0x14, 0x9065);
3611 rtl_writephy(tp, 0x14, 0x1065);
3612
3613 rtl8168g_disable_aldps(tp);
3614 rtl8168g_config_eee_phy(tp);
3615 rtl_enable_eee(tp);
3616 }
3617
3618 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3619 {
3620 rtl_apply_firmware(tp);
3621 rtl8168g_config_eee_phy(tp);
3622 rtl_enable_eee(tp);
3623 }
3624
3625 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3626 {
3627 u16 dout_tapbin;
3628 u32 data;
3629
3630 rtl_apply_firmware(tp);
3631
3632 /* CHN EST parameters adjust - giga master */
3633 rtl_writephy(tp, 0x1f, 0x0a43);
3634 rtl_writephy(tp, 0x13, 0x809b);
3635 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3636 rtl_writephy(tp, 0x13, 0x80a2);
3637 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3638 rtl_writephy(tp, 0x13, 0x80a4);
3639 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3640 rtl_writephy(tp, 0x13, 0x809c);
3641 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3642 rtl_writephy(tp, 0x1f, 0x0000);
3643
3644 /* CHN EST parameters adjust - giga slave */
3645 rtl_writephy(tp, 0x1f, 0x0a43);
3646 rtl_writephy(tp, 0x13, 0x80ad);
3647 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3648 rtl_writephy(tp, 0x13, 0x80b4);
3649 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3650 rtl_writephy(tp, 0x13, 0x80ac);
3651 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3652 rtl_writephy(tp, 0x1f, 0x0000);
3653
3654 /* CHN EST parameters adjust - fnet */
3655 rtl_writephy(tp, 0x1f, 0x0a43);
3656 rtl_writephy(tp, 0x13, 0x808e);
3657 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3658 rtl_writephy(tp, 0x13, 0x8090);
3659 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3660 rtl_writephy(tp, 0x13, 0x8092);
3661 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3662 rtl_writephy(tp, 0x1f, 0x0000);
3663
3664 /* enable R-tune & PGA-retune function */
3665 dout_tapbin = 0;
3666 rtl_writephy(tp, 0x1f, 0x0a46);
3667 data = rtl_readphy(tp, 0x13);
3668 data &= 3;
3669 data <<= 2;
3670 dout_tapbin |= data;
3671 data = rtl_readphy(tp, 0x12);
3672 data &= 0xc000;
3673 data >>= 14;
3674 dout_tapbin |= data;
3675 dout_tapbin = ~(dout_tapbin^0x08);
3676 dout_tapbin <<= 12;
3677 dout_tapbin &= 0xf000;
3678 rtl_writephy(tp, 0x1f, 0x0a43);
3679 rtl_writephy(tp, 0x13, 0x827a);
3680 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3681 rtl_writephy(tp, 0x13, 0x827b);
3682 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3683 rtl_writephy(tp, 0x13, 0x827c);
3684 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3685 rtl_writephy(tp, 0x13, 0x827d);
3686 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3687
3688 rtl_writephy(tp, 0x1f, 0x0a43);
3689 rtl_writephy(tp, 0x13, 0x0811);
3690 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3691 rtl_writephy(tp, 0x1f, 0x0a42);
3692 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3693 rtl_writephy(tp, 0x1f, 0x0000);
3694
3695 /* enable GPHY 10M */
3696 rtl_writephy(tp, 0x1f, 0x0a44);
3697 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3698 rtl_writephy(tp, 0x1f, 0x0000);
3699
3700 /* SAR ADC performance */
3701 rtl_writephy(tp, 0x1f, 0x0bca);
3702 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3703 rtl_writephy(tp, 0x1f, 0x0000);
3704
3705 rtl_writephy(tp, 0x1f, 0x0a43);
3706 rtl_writephy(tp, 0x13, 0x803f);
3707 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3708 rtl_writephy(tp, 0x13, 0x8047);
3709 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3710 rtl_writephy(tp, 0x13, 0x804f);
3711 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3712 rtl_writephy(tp, 0x13, 0x8057);
3713 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3714 rtl_writephy(tp, 0x13, 0x805f);
3715 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3716 rtl_writephy(tp, 0x13, 0x8067);
3717 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3718 rtl_writephy(tp, 0x13, 0x806f);
3719 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3720 rtl_writephy(tp, 0x1f, 0x0000);
3721
3722 /* disable phy pfm mode */
3723 rtl_writephy(tp, 0x1f, 0x0a44);
3724 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3725 rtl_writephy(tp, 0x1f, 0x0000);
3726
3727 rtl8168g_disable_aldps(tp);
3728 rtl8168g_config_eee_phy(tp);
3729 rtl_enable_eee(tp);
3730 }
3731
3732 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3733 {
3734 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3735 u16 rlen;
3736 u32 data;
3737
3738 rtl_apply_firmware(tp);
3739
3740 /* CHIN EST parameter update */
3741 rtl_writephy(tp, 0x1f, 0x0a43);
3742 rtl_writephy(tp, 0x13, 0x808a);
3743 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3744 rtl_writephy(tp, 0x1f, 0x0000);
3745
3746 /* enable R-tune & PGA-retune function */
3747 rtl_writephy(tp, 0x1f, 0x0a43);
3748 rtl_writephy(tp, 0x13, 0x0811);
3749 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3750 rtl_writephy(tp, 0x1f, 0x0a42);
3751 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3752 rtl_writephy(tp, 0x1f, 0x0000);
3753
3754 /* enable GPHY 10M */
3755 rtl_writephy(tp, 0x1f, 0x0a44);
3756 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3757 rtl_writephy(tp, 0x1f, 0x0000);
3758
3759 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3760 data = r8168_mac_ocp_read(tp, 0xdd02);
3761 ioffset_p3 = ((data & 0x80)>>7);
3762 ioffset_p3 <<= 3;
3763
3764 data = r8168_mac_ocp_read(tp, 0xdd00);
3765 ioffset_p3 |= ((data & (0xe000))>>13);
3766 ioffset_p2 = ((data & (0x1e00))>>9);
3767 ioffset_p1 = ((data & (0x01e0))>>5);
3768 ioffset_p0 = ((data & 0x0010)>>4);
3769 ioffset_p0 <<= 3;
3770 ioffset_p0 |= (data & (0x07));
3771 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3772
3773 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3774 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3775 rtl_writephy(tp, 0x1f, 0x0bcf);
3776 rtl_writephy(tp, 0x16, data);
3777 rtl_writephy(tp, 0x1f, 0x0000);
3778 }
3779
3780 /* Modify rlen (TX LPF corner frequency) level */
3781 rtl_writephy(tp, 0x1f, 0x0bcd);
3782 data = rtl_readphy(tp, 0x16);
3783 data &= 0x000f;
3784 rlen = 0;
3785 if (data > 3)
3786 rlen = data - 3;
3787 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3788 rtl_writephy(tp, 0x17, data);
3789 rtl_writephy(tp, 0x1f, 0x0bcd);
3790 rtl_writephy(tp, 0x1f, 0x0000);
3791
3792 /* disable phy pfm mode */
3793 rtl_writephy(tp, 0x1f, 0x0a44);
3794 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3795 rtl_writephy(tp, 0x1f, 0x0000);
3796
3797 rtl8168g_disable_aldps(tp);
3798 rtl8168g_config_eee_phy(tp);
3799 rtl_enable_eee(tp);
3800 }
3801
3802 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3803 {
3804 /* Enable PHY auto speed down */
3805 rtl_writephy(tp, 0x1f, 0x0a44);
3806 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3807 rtl_writephy(tp, 0x1f, 0x0000);
3808
3809 rtl8168g_phy_adjust_10m_aldps(tp);
3810
3811 /* Enable EEE auto-fallback function */
3812 rtl_writephy(tp, 0x1f, 0x0a4b);
3813 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3814 rtl_writephy(tp, 0x1f, 0x0000);
3815
3816 /* Enable UC LPF tune function */
3817 rtl_writephy(tp, 0x1f, 0x0a43);
3818 rtl_writephy(tp, 0x13, 0x8012);
3819 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3820 rtl_writephy(tp, 0x1f, 0x0000);
3821
3822 /* set rg_sel_sdm_rate */
3823 rtl_writephy(tp, 0x1f, 0x0c42);
3824 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3825 rtl_writephy(tp, 0x1f, 0x0000);
3826
3827 rtl8168g_disable_aldps(tp);
3828 rtl8168g_config_eee_phy(tp);
3829 rtl_enable_eee(tp);
3830 }
3831
3832 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3833 {
3834 rtl8168g_phy_adjust_10m_aldps(tp);
3835
3836 /* Enable UC LPF tune function */
3837 rtl_writephy(tp, 0x1f, 0x0a43);
3838 rtl_writephy(tp, 0x13, 0x8012);
3839 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3840 rtl_writephy(tp, 0x1f, 0x0000);
3841
3842 /* Set rg_sel_sdm_rate */
3843 rtl_writephy(tp, 0x1f, 0x0c42);
3844 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3845 rtl_writephy(tp, 0x1f, 0x0000);
3846
3847 /* Channel estimation parameters */
3848 rtl_writephy(tp, 0x1f, 0x0a43);
3849 rtl_writephy(tp, 0x13, 0x80f3);
3850 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3851 rtl_writephy(tp, 0x13, 0x80f0);
3852 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3853 rtl_writephy(tp, 0x13, 0x80ef);
3854 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3855 rtl_writephy(tp, 0x13, 0x80f6);
3856 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3857 rtl_writephy(tp, 0x13, 0x80ec);
3858 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3859 rtl_writephy(tp, 0x13, 0x80ed);
3860 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3861 rtl_writephy(tp, 0x13, 0x80f2);
3862 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3863 rtl_writephy(tp, 0x13, 0x80f4);
3864 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3865 rtl_writephy(tp, 0x1f, 0x0a43);
3866 rtl_writephy(tp, 0x13, 0x8110);
3867 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3868 rtl_writephy(tp, 0x13, 0x810f);
3869 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3870 rtl_writephy(tp, 0x13, 0x8111);
3871 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3872 rtl_writephy(tp, 0x13, 0x8113);
3873 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3874 rtl_writephy(tp, 0x13, 0x8115);
3875 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3876 rtl_writephy(tp, 0x13, 0x810e);
3877 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3878 rtl_writephy(tp, 0x13, 0x810c);
3879 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3880 rtl_writephy(tp, 0x13, 0x810b);
3881 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3882 rtl_writephy(tp, 0x1f, 0x0a43);
3883 rtl_writephy(tp, 0x13, 0x80d1);
3884 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3885 rtl_writephy(tp, 0x13, 0x80cd);
3886 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3887 rtl_writephy(tp, 0x13, 0x80d3);
3888 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3889 rtl_writephy(tp, 0x13, 0x80d5);
3890 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3891 rtl_writephy(tp, 0x13, 0x80d7);
3892 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3893
3894 /* Force PWM-mode */
3895 rtl_writephy(tp, 0x1f, 0x0bcd);
3896 rtl_writephy(tp, 0x14, 0x5065);
3897 rtl_writephy(tp, 0x14, 0xd065);
3898 rtl_writephy(tp, 0x1f, 0x0bc8);
3899 rtl_writephy(tp, 0x12, 0x00ed);
3900 rtl_writephy(tp, 0x1f, 0x0bcd);
3901 rtl_writephy(tp, 0x14, 0x1065);
3902 rtl_writephy(tp, 0x14, 0x9065);
3903 rtl_writephy(tp, 0x14, 0x1065);
3904 rtl_writephy(tp, 0x1f, 0x0000);
3905
3906 rtl8168g_disable_aldps(tp);
3907 rtl8168g_config_eee_phy(tp);
3908 rtl_enable_eee(tp);
3909 }
3910
3911 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3912 {
3913 static const struct phy_reg phy_reg_init[] = {
3914 { 0x1f, 0x0003 },
3915 { 0x08, 0x441d },
3916 { 0x01, 0x9100 },
3917 { 0x1f, 0x0000 }
3918 };
3919
3920 rtl_writephy(tp, 0x1f, 0x0000);
3921 rtl_patchphy(tp, 0x11, 1 << 12);
3922 rtl_patchphy(tp, 0x19, 1 << 13);
3923 rtl_patchphy(tp, 0x10, 1 << 15);
3924
3925 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3926 }
3927
3928 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3929 {
3930 static const struct phy_reg phy_reg_init[] = {
3931 { 0x1f, 0x0005 },
3932 { 0x1a, 0x0000 },
3933 { 0x1f, 0x0000 },
3934
3935 { 0x1f, 0x0004 },
3936 { 0x1c, 0x0000 },
3937 { 0x1f, 0x0000 },
3938
3939 { 0x1f, 0x0001 },
3940 { 0x15, 0x7701 },
3941 { 0x1f, 0x0000 }
3942 };
3943
3944 /* Disable ALDPS before ram code */
3945 rtl_writephy(tp, 0x1f, 0x0000);
3946 rtl_writephy(tp, 0x18, 0x0310);
3947 msleep(100);
3948
3949 rtl_apply_firmware(tp);
3950
3951 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3952 }
3953
3954 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3955 {
3956 /* Disable ALDPS before setting firmware */
3957 rtl_writephy(tp, 0x1f, 0x0000);
3958 rtl_writephy(tp, 0x18, 0x0310);
3959 msleep(20);
3960
3961 rtl_apply_firmware(tp);
3962
3963 /* EEE setting */
3964 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3965 rtl_writephy(tp, 0x1f, 0x0004);
3966 rtl_writephy(tp, 0x10, 0x401f);
3967 rtl_writephy(tp, 0x19, 0x7030);
3968 rtl_writephy(tp, 0x1f, 0x0000);
3969 }
3970
3971 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3972 {
3973 static const struct phy_reg phy_reg_init[] = {
3974 { 0x1f, 0x0004 },
3975 { 0x10, 0xc07f },
3976 { 0x19, 0x7030 },
3977 { 0x1f, 0x0000 }
3978 };
3979
3980 /* Disable ALDPS before ram code */
3981 rtl_writephy(tp, 0x1f, 0x0000);
3982 rtl_writephy(tp, 0x18, 0x0310);
3983 msleep(100);
3984
3985 rtl_apply_firmware(tp);
3986
3987 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3988 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3989
3990 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3991 }
3992
3993 static void rtl_hw_phy_config(struct net_device *dev)
3994 {
3995 struct rtl8169_private *tp = netdev_priv(dev);
3996
3997 switch (tp->mac_version) {
3998 case RTL_GIGA_MAC_VER_01:
3999 break;
4000 case RTL_GIGA_MAC_VER_02:
4001 case RTL_GIGA_MAC_VER_03:
4002 rtl8169s_hw_phy_config(tp);
4003 break;
4004 case RTL_GIGA_MAC_VER_04:
4005 rtl8169sb_hw_phy_config(tp);
4006 break;
4007 case RTL_GIGA_MAC_VER_05:
4008 rtl8169scd_hw_phy_config(tp);
4009 break;
4010 case RTL_GIGA_MAC_VER_06:
4011 rtl8169sce_hw_phy_config(tp);
4012 break;
4013 case RTL_GIGA_MAC_VER_07:
4014 case RTL_GIGA_MAC_VER_08:
4015 case RTL_GIGA_MAC_VER_09:
4016 rtl8102e_hw_phy_config(tp);
4017 break;
4018 case RTL_GIGA_MAC_VER_11:
4019 rtl8168bb_hw_phy_config(tp);
4020 break;
4021 case RTL_GIGA_MAC_VER_12:
4022 rtl8168bef_hw_phy_config(tp);
4023 break;
4024 case RTL_GIGA_MAC_VER_17:
4025 rtl8168bef_hw_phy_config(tp);
4026 break;
4027 case RTL_GIGA_MAC_VER_18:
4028 rtl8168cp_1_hw_phy_config(tp);
4029 break;
4030 case RTL_GIGA_MAC_VER_19:
4031 rtl8168c_1_hw_phy_config(tp);
4032 break;
4033 case RTL_GIGA_MAC_VER_20:
4034 rtl8168c_2_hw_phy_config(tp);
4035 break;
4036 case RTL_GIGA_MAC_VER_21:
4037 rtl8168c_3_hw_phy_config(tp);
4038 break;
4039 case RTL_GIGA_MAC_VER_22:
4040 rtl8168c_4_hw_phy_config(tp);
4041 break;
4042 case RTL_GIGA_MAC_VER_23:
4043 case RTL_GIGA_MAC_VER_24:
4044 rtl8168cp_2_hw_phy_config(tp);
4045 break;
4046 case RTL_GIGA_MAC_VER_25:
4047 rtl8168d_1_hw_phy_config(tp);
4048 break;
4049 case RTL_GIGA_MAC_VER_26:
4050 rtl8168d_2_hw_phy_config(tp);
4051 break;
4052 case RTL_GIGA_MAC_VER_27:
4053 rtl8168d_3_hw_phy_config(tp);
4054 break;
4055 case RTL_GIGA_MAC_VER_28:
4056 rtl8168d_4_hw_phy_config(tp);
4057 break;
4058 case RTL_GIGA_MAC_VER_29:
4059 case RTL_GIGA_MAC_VER_30:
4060 rtl8105e_hw_phy_config(tp);
4061 break;
4062 case RTL_GIGA_MAC_VER_31:
4063 /* None. */
4064 break;
4065 case RTL_GIGA_MAC_VER_32:
4066 case RTL_GIGA_MAC_VER_33:
4067 rtl8168e_1_hw_phy_config(tp);
4068 break;
4069 case RTL_GIGA_MAC_VER_34:
4070 rtl8168e_2_hw_phy_config(tp);
4071 break;
4072 case RTL_GIGA_MAC_VER_35:
4073 rtl8168f_1_hw_phy_config(tp);
4074 break;
4075 case RTL_GIGA_MAC_VER_36:
4076 rtl8168f_2_hw_phy_config(tp);
4077 break;
4078
4079 case RTL_GIGA_MAC_VER_37:
4080 rtl8402_hw_phy_config(tp);
4081 break;
4082
4083 case RTL_GIGA_MAC_VER_38:
4084 rtl8411_hw_phy_config(tp);
4085 break;
4086
4087 case RTL_GIGA_MAC_VER_39:
4088 rtl8106e_hw_phy_config(tp);
4089 break;
4090
4091 case RTL_GIGA_MAC_VER_40:
4092 rtl8168g_1_hw_phy_config(tp);
4093 break;
4094 case RTL_GIGA_MAC_VER_42:
4095 case RTL_GIGA_MAC_VER_43:
4096 case RTL_GIGA_MAC_VER_44:
4097 rtl8168g_2_hw_phy_config(tp);
4098 break;
4099 case RTL_GIGA_MAC_VER_45:
4100 case RTL_GIGA_MAC_VER_47:
4101 rtl8168h_1_hw_phy_config(tp);
4102 break;
4103 case RTL_GIGA_MAC_VER_46:
4104 case RTL_GIGA_MAC_VER_48:
4105 rtl8168h_2_hw_phy_config(tp);
4106 break;
4107
4108 case RTL_GIGA_MAC_VER_49:
4109 rtl8168ep_1_hw_phy_config(tp);
4110 break;
4111 case RTL_GIGA_MAC_VER_50:
4112 case RTL_GIGA_MAC_VER_51:
4113 rtl8168ep_2_hw_phy_config(tp);
4114 break;
4115
4116 case RTL_GIGA_MAC_VER_41:
4117 default:
4118 break;
4119 }
4120 }
4121
4122 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4123 {
4124 if (!test_and_set_bit(flag, tp->wk.flags))
4125 schedule_work(&tp->wk.work);
4126 }
4127
4128 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4129 {
4130 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4131 (RTL_R8(tp, PHYstatus) & TBI_Enable);
4132 }
4133
4134 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4135 {
4136 rtl_hw_phy_config(dev);
4137
4138 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4139 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4140 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4141 netif_dbg(tp, drv, dev,
4142 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4143 RTL_W8(tp, 0x82, 0x01);
4144 }
4145
4146 /* We may have called phy_speed_down before */
4147 phy_speed_up(tp->phydev);
4148
4149 genphy_soft_reset(tp->phydev);
4150
4151 /* It was reported that several chips end up with 10MBit/Half on a
4152 * 1GBit link after resuming from S3. For whatever reason the PHY on
4153 * these chips doesn't properly start a renegotiation when soft-reset.
4154 * Explicitly requesting a renegotiation fixes this.
4155 */
4156 if (tp->phydev->autoneg == AUTONEG_ENABLE)
4157 phy_restart_aneg(tp->phydev);
4158 }
4159
4160 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4161 {
4162 rtl_lock_work(tp);
4163
4164 rtl_unlock_config_regs(tp);
4165
4166 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4167 RTL_R32(tp, MAC4);
4168
4169 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4170 RTL_R32(tp, MAC0);
4171
4172 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4173 rtl_rar_exgmac_set(tp, addr);
4174
4175 rtl_lock_config_regs(tp);
4176
4177 rtl_unlock_work(tp);
4178 }
4179
4180 static int rtl_set_mac_address(struct net_device *dev, void *p)
4181 {
4182 struct rtl8169_private *tp = netdev_priv(dev);
4183 struct device *d = tp_to_dev(tp);
4184 int ret;
4185
4186 ret = eth_mac_addr(dev, p);
4187 if (ret)
4188 return ret;
4189
4190 pm_runtime_get_noresume(d);
4191
4192 if (pm_runtime_active(d))
4193 rtl_rar_set(tp, dev->dev_addr);
4194
4195 pm_runtime_put_noidle(d);
4196
4197 return 0;
4198 }
4199
4200 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4201 {
4202 struct rtl8169_private *tp = netdev_priv(dev);
4203
4204 if (!netif_running(dev))
4205 return -ENODEV;
4206
4207 return phy_mii_ioctl(tp->phydev, ifr, cmd);
4208 }
4209
4210 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4211 {
4212 struct mdio_ops *ops = &tp->mdio_ops;
4213
4214 switch (tp->mac_version) {
4215 case RTL_GIGA_MAC_VER_27:
4216 ops->write = r8168dp_1_mdio_write;
4217 ops->read = r8168dp_1_mdio_read;
4218 break;
4219 case RTL_GIGA_MAC_VER_28:
4220 case RTL_GIGA_MAC_VER_31:
4221 ops->write = r8168dp_2_mdio_write;
4222 ops->read = r8168dp_2_mdio_read;
4223 break;
4224 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4225 ops->write = r8168g_mdio_write;
4226 ops->read = r8168g_mdio_read;
4227 break;
4228 default:
4229 ops->write = r8169_mdio_write;
4230 ops->read = r8169_mdio_read;
4231 break;
4232 }
4233 }
4234
4235 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4236 {
4237 switch (tp->mac_version) {
4238 case RTL_GIGA_MAC_VER_25:
4239 case RTL_GIGA_MAC_VER_26:
4240 case RTL_GIGA_MAC_VER_29:
4241 case RTL_GIGA_MAC_VER_30:
4242 case RTL_GIGA_MAC_VER_32:
4243 case RTL_GIGA_MAC_VER_33:
4244 case RTL_GIGA_MAC_VER_34:
4245 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4246 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4247 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4248 break;
4249 default:
4250 break;
4251 }
4252 }
4253
4254 static void r8168_pll_power_down(struct rtl8169_private *tp)
4255 {
4256 if (r8168_check_dash(tp))
4257 return;
4258
4259 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4260 tp->mac_version == RTL_GIGA_MAC_VER_33)
4261 rtl_ephy_write(tp, 0x19, 0xff64);
4262
4263 if (device_may_wakeup(tp_to_dev(tp))) {
4264 phy_speed_down(tp->phydev, false);
4265 rtl_wol_suspend_quirk(tp);
4266 return;
4267 }
4268
4269 switch (tp->mac_version) {
4270 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4271 case RTL_GIGA_MAC_VER_37:
4272 case RTL_GIGA_MAC_VER_39:
4273 case RTL_GIGA_MAC_VER_43:
4274 case RTL_GIGA_MAC_VER_44:
4275 case RTL_GIGA_MAC_VER_45:
4276 case RTL_GIGA_MAC_VER_46:
4277 case RTL_GIGA_MAC_VER_47:
4278 case RTL_GIGA_MAC_VER_48:
4279 case RTL_GIGA_MAC_VER_50:
4280 case RTL_GIGA_MAC_VER_51:
4281 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4282 break;
4283 case RTL_GIGA_MAC_VER_40:
4284 case RTL_GIGA_MAC_VER_41:
4285 case RTL_GIGA_MAC_VER_49:
4286 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4287 0xfc000000, ERIAR_EXGMAC);
4288 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4289 break;
4290 }
4291 }
4292
4293 static void r8168_pll_power_up(struct rtl8169_private *tp)
4294 {
4295 switch (tp->mac_version) {
4296 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4297 case RTL_GIGA_MAC_VER_37:
4298 case RTL_GIGA_MAC_VER_39:
4299 case RTL_GIGA_MAC_VER_43:
4300 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4301 break;
4302 case RTL_GIGA_MAC_VER_44:
4303 case RTL_GIGA_MAC_VER_45:
4304 case RTL_GIGA_MAC_VER_46:
4305 case RTL_GIGA_MAC_VER_47:
4306 case RTL_GIGA_MAC_VER_48:
4307 case RTL_GIGA_MAC_VER_50:
4308 case RTL_GIGA_MAC_VER_51:
4309 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4310 break;
4311 case RTL_GIGA_MAC_VER_40:
4312 case RTL_GIGA_MAC_VER_41:
4313 case RTL_GIGA_MAC_VER_49:
4314 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4315 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4316 0x00000000, ERIAR_EXGMAC);
4317 break;
4318 }
4319
4320 phy_resume(tp->phydev);
4321 /* give MAC/PHY some time to resume */
4322 msleep(20);
4323 }
4324
4325 static void rtl_pll_power_down(struct rtl8169_private *tp)
4326 {
4327 switch (tp->mac_version) {
4328 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4329 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4330 break;
4331 default:
4332 r8168_pll_power_down(tp);
4333 }
4334 }
4335
4336 static void rtl_pll_power_up(struct rtl8169_private *tp)
4337 {
4338 switch (tp->mac_version) {
4339 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4340 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4341 break;
4342 default:
4343 r8168_pll_power_up(tp);
4344 }
4345 }
4346
4347 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4348 {
4349 switch (tp->mac_version) {
4350 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4351 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4352 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4353 break;
4354 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4355 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4356 case RTL_GIGA_MAC_VER_38:
4357 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4358 break;
4359 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4360 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4361 break;
4362 default:
4363 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4364 break;
4365 }
4366 }
4367
4368 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4369 {
4370 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4371 }
4372
4373 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4374 {
4375 if (tp->jumbo_ops.enable) {
4376 rtl_unlock_config_regs(tp);
4377 tp->jumbo_ops.enable(tp);
4378 rtl_lock_config_regs(tp);
4379 }
4380 }
4381
4382 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4383 {
4384 if (tp->jumbo_ops.disable) {
4385 rtl_unlock_config_regs(tp);
4386 tp->jumbo_ops.disable(tp);
4387 rtl_lock_config_regs(tp);
4388 }
4389 }
4390
4391 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4392 {
4393 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4394 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4395 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4396 }
4397
4398 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4399 {
4400 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4401 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4402 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4403 }
4404
4405 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4406 {
4407 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4408 }
4409
4410 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4411 {
4412 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4413 }
4414
4415 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4416 {
4417 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4418 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4419 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4420 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4421 }
4422
4423 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4424 {
4425 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4426 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4427 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4428 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4429 }
4430
4431 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4432 {
4433 rtl_tx_performance_tweak(tp,
4434 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4435 }
4436
4437 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4438 {
4439 rtl_tx_performance_tweak(tp,
4440 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4441 }
4442
4443 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4444 {
4445 r8168b_0_hw_jumbo_enable(tp);
4446
4447 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4448 }
4449
4450 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4451 {
4452 r8168b_0_hw_jumbo_disable(tp);
4453
4454 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4455 }
4456
4457 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4458 {
4459 struct jumbo_ops *ops = &tp->jumbo_ops;
4460
4461 switch (tp->mac_version) {
4462 case RTL_GIGA_MAC_VER_11:
4463 ops->disable = r8168b_0_hw_jumbo_disable;
4464 ops->enable = r8168b_0_hw_jumbo_enable;
4465 break;
4466 case RTL_GIGA_MAC_VER_12:
4467 case RTL_GIGA_MAC_VER_17:
4468 ops->disable = r8168b_1_hw_jumbo_disable;
4469 ops->enable = r8168b_1_hw_jumbo_enable;
4470 break;
4471 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4472 case RTL_GIGA_MAC_VER_19:
4473 case RTL_GIGA_MAC_VER_20:
4474 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4475 case RTL_GIGA_MAC_VER_22:
4476 case RTL_GIGA_MAC_VER_23:
4477 case RTL_GIGA_MAC_VER_24:
4478 case RTL_GIGA_MAC_VER_25:
4479 case RTL_GIGA_MAC_VER_26:
4480 ops->disable = r8168c_hw_jumbo_disable;
4481 ops->enable = r8168c_hw_jumbo_enable;
4482 break;
4483 case RTL_GIGA_MAC_VER_27:
4484 case RTL_GIGA_MAC_VER_28:
4485 ops->disable = r8168dp_hw_jumbo_disable;
4486 ops->enable = r8168dp_hw_jumbo_enable;
4487 break;
4488 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4489 case RTL_GIGA_MAC_VER_32:
4490 case RTL_GIGA_MAC_VER_33:
4491 case RTL_GIGA_MAC_VER_34:
4492 ops->disable = r8168e_hw_jumbo_disable;
4493 ops->enable = r8168e_hw_jumbo_enable;
4494 break;
4495
4496 /*
4497 * No action needed for jumbo frames with 8169.
4498 * No jumbo for 810x at all.
4499 */
4500 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4501 default:
4502 ops->disable = NULL;
4503 ops->enable = NULL;
4504 break;
4505 }
4506 }
4507
4508 DECLARE_RTL_COND(rtl_chipcmd_cond)
4509 {
4510 return RTL_R8(tp, ChipCmd) & CmdReset;
4511 }
4512
4513 static void rtl_hw_reset(struct rtl8169_private *tp)
4514 {
4515 RTL_W8(tp, ChipCmd, CmdReset);
4516
4517 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4518 }
4519
4520 static void rtl_request_firmware(struct rtl8169_private *tp)
4521 {
4522 struct rtl_fw *rtl_fw;
4523 int rc = -ENOMEM;
4524
4525 /* firmware loaded already or no firmware available */
4526 if (tp->rtl_fw || !tp->fw_name)
4527 return;
4528
4529 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4530 if (!rtl_fw)
4531 goto err_warn;
4532
4533 rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4534 if (rc < 0)
4535 goto err_free;
4536
4537 rc = rtl_check_firmware(tp, rtl_fw);
4538 if (rc < 0)
4539 goto err_release_firmware;
4540
4541 tp->rtl_fw = rtl_fw;
4542
4543 return;
4544
4545 err_release_firmware:
4546 release_firmware(rtl_fw->fw);
4547 err_free:
4548 kfree(rtl_fw);
4549 err_warn:
4550 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4551 tp->fw_name, rc);
4552 }
4553
4554 static void rtl_rx_close(struct rtl8169_private *tp)
4555 {
4556 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4557 }
4558
4559 DECLARE_RTL_COND(rtl_npq_cond)
4560 {
4561 return RTL_R8(tp, TxPoll) & NPQ;
4562 }
4563
4564 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4565 {
4566 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4567 }
4568
4569 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4570 {
4571 /* Disable interrupts */
4572 rtl8169_irq_mask_and_ack(tp);
4573
4574 rtl_rx_close(tp);
4575
4576 switch (tp->mac_version) {
4577 case RTL_GIGA_MAC_VER_27:
4578 case RTL_GIGA_MAC_VER_28:
4579 case RTL_GIGA_MAC_VER_31:
4580 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4581 break;
4582 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4583 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4584 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4585 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4586 break;
4587 default:
4588 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4589 udelay(100);
4590 break;
4591 }
4592
4593 rtl_hw_reset(tp);
4594 }
4595
4596 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4597 {
4598 u32 val = TX_DMA_BURST << TxDMAShift |
4599 InterFrameGap << TxInterFrameGapShift;
4600
4601 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4602 tp->mac_version != RTL_GIGA_MAC_VER_39)
4603 val |= TXCFG_AUTO_FIFO;
4604
4605 RTL_W32(tp, TxConfig, val);
4606 }
4607
4608 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4609 {
4610 /* Low hurts. Let's disable the filtering. */
4611 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4612 }
4613
4614 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4615 {
4616 /*
4617 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4618 * register to be written before TxDescAddrLow to work.
4619 * Switching from MMIO to I/O access fixes the issue as well.
4620 */
4621 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4622 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4623 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4624 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4625 }
4626
4627 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4628 {
4629 u32 val;
4630
4631 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4632 val = 0x000fff00;
4633 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4634 val = 0x00ffff00;
4635 else
4636 return;
4637
4638 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4639 val |= 0xff;
4640
4641 RTL_W32(tp, 0x7c, val);
4642 }
4643
4644 static void rtl_set_rx_mode(struct net_device *dev)
4645 {
4646 struct rtl8169_private *tp = netdev_priv(dev);
4647 u32 mc_filter[2]; /* Multicast hash filter */
4648 int rx_mode;
4649 u32 tmp = 0;
4650
4651 if (dev->flags & IFF_PROMISC) {
4652 /* Unconditionally log net taps. */
4653 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4654 rx_mode =
4655 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4656 AcceptAllPhys;
4657 mc_filter[1] = mc_filter[0] = 0xffffffff;
4658 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4659 (dev->flags & IFF_ALLMULTI)) {
4660 /* Too many to filter perfectly -- accept all multicasts. */
4661 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4662 mc_filter[1] = mc_filter[0] = 0xffffffff;
4663 } else {
4664 struct netdev_hw_addr *ha;
4665
4666 rx_mode = AcceptBroadcast | AcceptMyPhys;
4667 mc_filter[1] = mc_filter[0] = 0;
4668 netdev_for_each_mc_addr(ha, dev) {
4669 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4670 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4671 rx_mode |= AcceptMulticast;
4672 }
4673 }
4674
4675 if (dev->features & NETIF_F_RXALL)
4676 rx_mode |= (AcceptErr | AcceptRunt);
4677
4678 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4679
4680 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4681 u32 data = mc_filter[0];
4682
4683 mc_filter[0] = swab32(mc_filter[1]);
4684 mc_filter[1] = swab32(data);
4685 }
4686
4687 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4688 mc_filter[1] = mc_filter[0] = 0xffffffff;
4689
4690 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4691 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4692
4693 RTL_W32(tp, RxConfig, tmp);
4694 }
4695
4696 static void rtl_hw_start(struct rtl8169_private *tp)
4697 {
4698 rtl_unlock_config_regs(tp);
4699
4700 tp->hw_start(tp);
4701
4702 rtl_set_rx_max_size(tp);
4703 rtl_set_rx_tx_desc_registers(tp);
4704 rtl_lock_config_regs(tp);
4705
4706 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4707 RTL_R8(tp, IntrMask);
4708 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4709 rtl_init_rxcfg(tp);
4710 rtl_set_tx_config_registers(tp);
4711
4712 rtl_set_rx_mode(tp->dev);
4713 /* no early-rx interrupts */
4714 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4715 rtl_irq_enable(tp);
4716 }
4717
4718 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4719 {
4720 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4721 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4722
4723 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4724
4725 tp->cp_cmd |= PCIMulRW;
4726
4727 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4728 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4729 netif_dbg(tp, drv, tp->dev,
4730 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4731 tp->cp_cmd |= (1 << 14);
4732 }
4733
4734 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4735
4736 rtl8169_set_magic_reg(tp, tp->mac_version);
4737
4738 /*
4739 * Undocumented corner. Supposedly:
4740 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4741 */
4742 RTL_W16(tp, IntrMitigate, 0x0000);
4743
4744 RTL_W32(tp, RxMissed, 0);
4745 }
4746
4747 DECLARE_RTL_COND(rtl_csiar_cond)
4748 {
4749 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4750 }
4751
4752 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4753 {
4754 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4755
4756 RTL_W32(tp, CSIDR, value);
4757 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4758 CSIAR_BYTE_ENABLE | func << 16);
4759
4760 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4761 }
4762
4763 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4764 {
4765 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4766
4767 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4768 CSIAR_BYTE_ENABLE);
4769
4770 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4771 RTL_R32(tp, CSIDR) : ~0;
4772 }
4773
4774 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4775 {
4776 struct pci_dev *pdev = tp->pci_dev;
4777 u32 csi;
4778
4779 /* According to Realtek the value at config space address 0x070f
4780 * controls the L0s/L1 entrance latency. We try standard ECAM access
4781 * first and if it fails fall back to CSI.
4782 */
4783 if (pdev->cfg_size > 0x070f &&
4784 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4785 return;
4786
4787 netdev_notice_once(tp->dev,
4788 "No native access to PCI extended config space, falling back to CSI\n");
4789 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4790 rtl_csi_write(tp, 0x070c, csi | val << 24);
4791 }
4792
4793 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4794 {
4795 rtl_csi_access_enable(tp, 0x27);
4796 }
4797
4798 struct ephy_info {
4799 unsigned int offset;
4800 u16 mask;
4801 u16 bits;
4802 };
4803
4804 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4805 int len)
4806 {
4807 u16 w;
4808
4809 while (len-- > 0) {
4810 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4811 rtl_ephy_write(tp, e->offset, w);
4812 e++;
4813 }
4814 }
4815
4816 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4817 {
4818 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4819 PCI_EXP_LNKCTL_CLKREQ_EN);
4820 }
4821
4822 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4823 {
4824 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4825 PCI_EXP_LNKCTL_CLKREQ_EN);
4826 }
4827
4828 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4829 {
4830 /* work around an issue when PCI reset occurs during L2/L3 state */
4831 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4832 }
4833
4834 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4835 {
4836 if (enable) {
4837 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4838 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4839 } else {
4840 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4841 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4842 }
4843
4844 udelay(10);
4845 }
4846
4847 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4848 {
4849 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4850
4851 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4852 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4853
4854 if (tp->dev->mtu <= ETH_DATA_LEN) {
4855 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4856 PCI_EXP_DEVCTL_NOSNOOP_EN);
4857 }
4858 }
4859
4860 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4861 {
4862 rtl_hw_start_8168bb(tp);
4863
4864 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4865
4866 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4867 }
4868
4869 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4870 {
4871 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4872
4873 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4874
4875 if (tp->dev->mtu <= ETH_DATA_LEN)
4876 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4877
4878 rtl_disable_clock_request(tp);
4879
4880 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4881 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4882 }
4883
4884 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4885 {
4886 static const struct ephy_info e_info_8168cp[] = {
4887 { 0x01, 0, 0x0001 },
4888 { 0x02, 0x0800, 0x1000 },
4889 { 0x03, 0, 0x0042 },
4890 { 0x06, 0x0080, 0x0000 },
4891 { 0x07, 0, 0x2000 }
4892 };
4893
4894 rtl_set_def_aspm_entry_latency(tp);
4895
4896 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4897
4898 __rtl_hw_start_8168cp(tp);
4899 }
4900
4901 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4902 {
4903 rtl_set_def_aspm_entry_latency(tp);
4904
4905 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4906
4907 if (tp->dev->mtu <= ETH_DATA_LEN)
4908 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4909
4910 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4911 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4912 }
4913
4914 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4915 {
4916 rtl_set_def_aspm_entry_latency(tp);
4917
4918 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4919
4920 /* Magic. */
4921 RTL_W8(tp, DBG_REG, 0x20);
4922
4923 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4924
4925 if (tp->dev->mtu <= ETH_DATA_LEN)
4926 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4927
4928 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4929 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4930 }
4931
4932 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4933 {
4934 static const struct ephy_info e_info_8168c_1[] = {
4935 { 0x02, 0x0800, 0x1000 },
4936 { 0x03, 0, 0x0002 },
4937 { 0x06, 0x0080, 0x0000 }
4938 };
4939
4940 rtl_set_def_aspm_entry_latency(tp);
4941
4942 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4943
4944 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4945
4946 __rtl_hw_start_8168cp(tp);
4947 }
4948
4949 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4950 {
4951 static const struct ephy_info e_info_8168c_2[] = {
4952 { 0x01, 0, 0x0001 },
4953 { 0x03, 0x0400, 0x0220 }
4954 };
4955
4956 rtl_set_def_aspm_entry_latency(tp);
4957
4958 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4959
4960 __rtl_hw_start_8168cp(tp);
4961 }
4962
4963 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4964 {
4965 rtl_hw_start_8168c_2(tp);
4966 }
4967
4968 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4969 {
4970 rtl_set_def_aspm_entry_latency(tp);
4971
4972 __rtl_hw_start_8168cp(tp);
4973 }
4974
4975 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4976 {
4977 rtl_set_def_aspm_entry_latency(tp);
4978
4979 rtl_disable_clock_request(tp);
4980
4981 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4982
4983 if (tp->dev->mtu <= ETH_DATA_LEN)
4984 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4985
4986 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4987 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4988 }
4989
4990 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4991 {
4992 rtl_set_def_aspm_entry_latency(tp);
4993
4994 if (tp->dev->mtu <= ETH_DATA_LEN)
4995 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4996
4997 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4998
4999 rtl_disable_clock_request(tp);
5000 }
5001
5002 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5003 {
5004 static const struct ephy_info e_info_8168d_4[] = {
5005 { 0x0b, 0x0000, 0x0048 },
5006 { 0x19, 0x0020, 0x0050 },
5007 { 0x0c, 0x0100, 0x0020 }
5008 };
5009
5010 rtl_set_def_aspm_entry_latency(tp);
5011
5012 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5013
5014 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5015
5016 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5017
5018 rtl_enable_clock_request(tp);
5019 }
5020
5021 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5022 {
5023 static const struct ephy_info e_info_8168e_1[] = {
5024 { 0x00, 0x0200, 0x0100 },
5025 { 0x00, 0x0000, 0x0004 },
5026 { 0x06, 0x0002, 0x0001 },
5027 { 0x06, 0x0000, 0x0030 },
5028 { 0x07, 0x0000, 0x2000 },
5029 { 0x00, 0x0000, 0x0020 },
5030 { 0x03, 0x5800, 0x2000 },
5031 { 0x03, 0x0000, 0x0001 },
5032 { 0x01, 0x0800, 0x1000 },
5033 { 0x07, 0x0000, 0x4000 },
5034 { 0x1e, 0x0000, 0x2000 },
5035 { 0x19, 0xffff, 0xfe6c },
5036 { 0x0a, 0x0000, 0x0040 }
5037 };
5038
5039 rtl_set_def_aspm_entry_latency(tp);
5040
5041 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5042
5043 if (tp->dev->mtu <= ETH_DATA_LEN)
5044 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5045
5046 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5047
5048 rtl_disable_clock_request(tp);
5049
5050 /* Reset tx FIFO pointer */
5051 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5052 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5053
5054 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5055 }
5056
5057 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5058 {
5059 static const struct ephy_info e_info_8168e_2[] = {
5060 { 0x09, 0x0000, 0x0080 },
5061 { 0x19, 0x0000, 0x0224 }
5062 };
5063
5064 rtl_set_def_aspm_entry_latency(tp);
5065
5066 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5067
5068 if (tp->dev->mtu <= ETH_DATA_LEN)
5069 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5070
5071 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5072 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5073 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5074 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5075 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5076 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5077 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5078 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5079
5080 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5081
5082 rtl_disable_clock_request(tp);
5083
5084 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5085
5086 /* Adjust EEE LED frequency */
5087 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5088
5089 rtl8168_config_eee_mac(tp);
5090
5091 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5092 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5093 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5094
5095 rtl_hw_aspm_clkreq_enable(tp, true);
5096 }
5097
5098 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5099 {
5100 rtl_set_def_aspm_entry_latency(tp);
5101
5102 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5103
5104 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5105 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5106 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5107 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5108 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5109 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5110 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5111 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5112 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5113 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5114
5115 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5116
5117 rtl_disable_clock_request(tp);
5118
5119 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5120 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5121 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5122 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5123
5124 rtl8168_config_eee_mac(tp);
5125 }
5126
5127 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5128 {
5129 static const struct ephy_info e_info_8168f_1[] = {
5130 { 0x06, 0x00c0, 0x0020 },
5131 { 0x08, 0x0001, 0x0002 },
5132 { 0x09, 0x0000, 0x0080 },
5133 { 0x19, 0x0000, 0x0224 }
5134 };
5135
5136 rtl_hw_start_8168f(tp);
5137
5138 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5139
5140 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5141
5142 /* Adjust EEE LED frequency */
5143 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5144 }
5145
5146 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5147 {
5148 static const struct ephy_info e_info_8168f_1[] = {
5149 { 0x06, 0x00c0, 0x0020 },
5150 { 0x0f, 0xffff, 0x5200 },
5151 { 0x1e, 0x0000, 0x4000 },
5152 { 0x19, 0x0000, 0x0224 }
5153 };
5154
5155 rtl_hw_start_8168f(tp);
5156 rtl_pcie_state_l2l3_disable(tp);
5157
5158 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5159
5160 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5161 }
5162
5163 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5164 {
5165 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5166 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5167 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5168 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5169
5170 rtl_set_def_aspm_entry_latency(tp);
5171
5172 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5173
5174 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5175 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5176 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5177
5178 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5179 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5180
5181 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5182 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5183
5184 /* Adjust EEE LED frequency */
5185 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5186
5187 rtl8168_config_eee_mac(tp);
5188
5189 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5190 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5191
5192 rtl_pcie_state_l2l3_disable(tp);
5193 }
5194
5195 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5196 {
5197 static const struct ephy_info e_info_8168g_1[] = {
5198 { 0x00, 0x0000, 0x0008 },
5199 { 0x0c, 0x37d0, 0x0820 },
5200 { 0x1e, 0x0000, 0x0001 },
5201 { 0x19, 0x8000, 0x0000 }
5202 };
5203
5204 rtl_hw_start_8168g(tp);
5205
5206 /* disable aspm and clock request before access ephy */
5207 rtl_hw_aspm_clkreq_enable(tp, false);
5208 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5209 rtl_hw_aspm_clkreq_enable(tp, true);
5210 }
5211
5212 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5213 {
5214 static const struct ephy_info e_info_8168g_2[] = {
5215 { 0x00, 0x0000, 0x0008 },
5216 { 0x0c, 0x3df0, 0x0200 },
5217 { 0x19, 0xffff, 0xfc00 },
5218 { 0x1e, 0xffff, 0x20eb }
5219 };
5220
5221 rtl_hw_start_8168g(tp);
5222
5223 /* disable aspm and clock request before access ephy */
5224 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5225 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5226 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5227 }
5228
5229 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5230 {
5231 static const struct ephy_info e_info_8411_2[] = {
5232 { 0x00, 0x0000, 0x0008 },
5233 { 0x0c, 0x3df0, 0x0200 },
5234 { 0x0f, 0xffff, 0x5200 },
5235 { 0x19, 0x0020, 0x0000 },
5236 { 0x1e, 0x0000, 0x2000 }
5237 };
5238
5239 rtl_hw_start_8168g(tp);
5240
5241 /* disable aspm and clock request before access ephy */
5242 rtl_hw_aspm_clkreq_enable(tp, false);
5243 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5244 rtl_hw_aspm_clkreq_enable(tp, true);
5245 }
5246
5247 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5248 {
5249 int rg_saw_cnt;
5250 u32 data;
5251 static const struct ephy_info e_info_8168h_1[] = {
5252 { 0x1e, 0x0800, 0x0001 },
5253 { 0x1d, 0x0000, 0x0800 },
5254 { 0x05, 0xffff, 0x2089 },
5255 { 0x06, 0xffff, 0x5881 },
5256 { 0x04, 0xffff, 0x154a },
5257 { 0x01, 0xffff, 0x068b }
5258 };
5259
5260 /* disable aspm and clock request before access ephy */
5261 rtl_hw_aspm_clkreq_enable(tp, false);
5262 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5263
5264 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5265 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5266 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5267 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5268
5269 rtl_set_def_aspm_entry_latency(tp);
5270
5271 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5272
5273 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5274 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5275
5276 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5277
5278 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5279
5280 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5281
5282 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5283 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5284
5285 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5286 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5287
5288 /* Adjust EEE LED frequency */
5289 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5290
5291 rtl8168_config_eee_mac(tp);
5292
5293 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5294 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5295
5296 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5297
5298 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5299
5300 rtl_pcie_state_l2l3_disable(tp);
5301
5302 rtl_writephy(tp, 0x1f, 0x0c42);
5303 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5304 rtl_writephy(tp, 0x1f, 0x0000);
5305 if (rg_saw_cnt > 0) {
5306 u16 sw_cnt_1ms_ini;
5307
5308 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5309 sw_cnt_1ms_ini &= 0x0fff;
5310 data = r8168_mac_ocp_read(tp, 0xd412);
5311 data &= ~0x0fff;
5312 data |= sw_cnt_1ms_ini;
5313 r8168_mac_ocp_write(tp, 0xd412, data);
5314 }
5315
5316 data = r8168_mac_ocp_read(tp, 0xe056);
5317 data &= ~0xf0;
5318 data |= 0x70;
5319 r8168_mac_ocp_write(tp, 0xe056, data);
5320
5321 data = r8168_mac_ocp_read(tp, 0xe052);
5322 data &= ~0x6000;
5323 data |= 0x8008;
5324 r8168_mac_ocp_write(tp, 0xe052, data);
5325
5326 data = r8168_mac_ocp_read(tp, 0xe0d6);
5327 data &= ~0x01ff;
5328 data |= 0x017f;
5329 r8168_mac_ocp_write(tp, 0xe0d6, data);
5330
5331 data = r8168_mac_ocp_read(tp, 0xd420);
5332 data &= ~0x0fff;
5333 data |= 0x047f;
5334 r8168_mac_ocp_write(tp, 0xd420, data);
5335
5336 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5337 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5338 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5339 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5340
5341 rtl_hw_aspm_clkreq_enable(tp, true);
5342 }
5343
5344 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5345 {
5346 rtl8168ep_stop_cmac(tp);
5347
5348 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5349 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5350 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5351 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5352
5353 rtl_set_def_aspm_entry_latency(tp);
5354
5355 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5356
5357 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5358 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5359
5360 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5361
5362 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5363
5364 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5365 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5366
5367 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5368 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5369
5370 /* Adjust EEE LED frequency */
5371 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5372
5373 rtl8168_config_eee_mac(tp);
5374
5375 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5376
5377 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5378
5379 rtl_pcie_state_l2l3_disable(tp);
5380 }
5381
5382 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5383 {
5384 static const struct ephy_info e_info_8168ep_1[] = {
5385 { 0x00, 0xffff, 0x10ab },
5386 { 0x06, 0xffff, 0xf030 },
5387 { 0x08, 0xffff, 0x2006 },
5388 { 0x0d, 0xffff, 0x1666 },
5389 { 0x0c, 0x3ff0, 0x0000 }
5390 };
5391
5392 /* disable aspm and clock request before access ephy */
5393 rtl_hw_aspm_clkreq_enable(tp, false);
5394 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5395
5396 rtl_hw_start_8168ep(tp);
5397
5398 rtl_hw_aspm_clkreq_enable(tp, true);
5399 }
5400
5401 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5402 {
5403 static const struct ephy_info e_info_8168ep_2[] = {
5404 { 0x00, 0xffff, 0x10a3 },
5405 { 0x19, 0xffff, 0xfc00 },
5406 { 0x1e, 0xffff, 0x20ea }
5407 };
5408
5409 /* disable aspm and clock request before access ephy */
5410 rtl_hw_aspm_clkreq_enable(tp, false);
5411 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5412
5413 rtl_hw_start_8168ep(tp);
5414
5415 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5416 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5417
5418 rtl_hw_aspm_clkreq_enable(tp, true);
5419 }
5420
5421 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5422 {
5423 u32 data;
5424 static const struct ephy_info e_info_8168ep_3[] = {
5425 { 0x00, 0xffff, 0x10a3 },
5426 { 0x19, 0xffff, 0x7c00 },
5427 { 0x1e, 0xffff, 0x20eb },
5428 { 0x0d, 0xffff, 0x1666 }
5429 };
5430
5431 /* disable aspm and clock request before access ephy */
5432 rtl_hw_aspm_clkreq_enable(tp, false);
5433 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5434
5435 rtl_hw_start_8168ep(tp);
5436
5437 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5438 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5439
5440 data = r8168_mac_ocp_read(tp, 0xd3e2);
5441 data &= 0xf000;
5442 data |= 0x0271;
5443 r8168_mac_ocp_write(tp, 0xd3e2, data);
5444
5445 data = r8168_mac_ocp_read(tp, 0xd3e4);
5446 data &= 0xff00;
5447 r8168_mac_ocp_write(tp, 0xd3e4, data);
5448
5449 data = r8168_mac_ocp_read(tp, 0xe860);
5450 data |= 0x0080;
5451 r8168_mac_ocp_write(tp, 0xe860, data);
5452
5453 rtl_hw_aspm_clkreq_enable(tp, true);
5454 }
5455
5456 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5457 {
5458 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5459
5460 tp->cp_cmd &= ~INTT_MASK;
5461 tp->cp_cmd |= PktCntrDisable | INTT_1;
5462 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5463
5464 RTL_W16(tp, IntrMitigate, 0x5100);
5465
5466 /* Work around for RxFIFO overflow. */
5467 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5468 tp->irq_mask |= RxFIFOOver;
5469 tp->irq_mask &= ~RxOverflow;
5470 }
5471
5472 switch (tp->mac_version) {
5473 case RTL_GIGA_MAC_VER_11:
5474 rtl_hw_start_8168bb(tp);
5475 break;
5476
5477 case RTL_GIGA_MAC_VER_12:
5478 case RTL_GIGA_MAC_VER_17:
5479 rtl_hw_start_8168bef(tp);
5480 break;
5481
5482 case RTL_GIGA_MAC_VER_18:
5483 rtl_hw_start_8168cp_1(tp);
5484 break;
5485
5486 case RTL_GIGA_MAC_VER_19:
5487 rtl_hw_start_8168c_1(tp);
5488 break;
5489
5490 case RTL_GIGA_MAC_VER_20:
5491 rtl_hw_start_8168c_2(tp);
5492 break;
5493
5494 case RTL_GIGA_MAC_VER_21:
5495 rtl_hw_start_8168c_3(tp);
5496 break;
5497
5498 case RTL_GIGA_MAC_VER_22:
5499 rtl_hw_start_8168c_4(tp);
5500 break;
5501
5502 case RTL_GIGA_MAC_VER_23:
5503 rtl_hw_start_8168cp_2(tp);
5504 break;
5505
5506 case RTL_GIGA_MAC_VER_24:
5507 rtl_hw_start_8168cp_3(tp);
5508 break;
5509
5510 case RTL_GIGA_MAC_VER_25:
5511 case RTL_GIGA_MAC_VER_26:
5512 case RTL_GIGA_MAC_VER_27:
5513 rtl_hw_start_8168d(tp);
5514 break;
5515
5516 case RTL_GIGA_MAC_VER_28:
5517 rtl_hw_start_8168d_4(tp);
5518 break;
5519
5520 case RTL_GIGA_MAC_VER_31:
5521 rtl_hw_start_8168dp(tp);
5522 break;
5523
5524 case RTL_GIGA_MAC_VER_32:
5525 case RTL_GIGA_MAC_VER_33:
5526 rtl_hw_start_8168e_1(tp);
5527 break;
5528 case RTL_GIGA_MAC_VER_34:
5529 rtl_hw_start_8168e_2(tp);
5530 break;
5531
5532 case RTL_GIGA_MAC_VER_35:
5533 case RTL_GIGA_MAC_VER_36:
5534 rtl_hw_start_8168f_1(tp);
5535 break;
5536
5537 case RTL_GIGA_MAC_VER_38:
5538 rtl_hw_start_8411(tp);
5539 break;
5540
5541 case RTL_GIGA_MAC_VER_40:
5542 case RTL_GIGA_MAC_VER_41:
5543 rtl_hw_start_8168g_1(tp);
5544 break;
5545 case RTL_GIGA_MAC_VER_42:
5546 rtl_hw_start_8168g_2(tp);
5547 break;
5548
5549 case RTL_GIGA_MAC_VER_44:
5550 rtl_hw_start_8411_2(tp);
5551 break;
5552
5553 case RTL_GIGA_MAC_VER_45:
5554 case RTL_GIGA_MAC_VER_46:
5555 rtl_hw_start_8168h_1(tp);
5556 break;
5557
5558 case RTL_GIGA_MAC_VER_49:
5559 rtl_hw_start_8168ep_1(tp);
5560 break;
5561
5562 case RTL_GIGA_MAC_VER_50:
5563 rtl_hw_start_8168ep_2(tp);
5564 break;
5565
5566 case RTL_GIGA_MAC_VER_51:
5567 rtl_hw_start_8168ep_3(tp);
5568 break;
5569
5570 default:
5571 netif_err(tp, drv, tp->dev,
5572 "unknown chipset (mac_version = %d)\n",
5573 tp->mac_version);
5574 break;
5575 }
5576 }
5577
5578 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5579 {
5580 static const struct ephy_info e_info_8102e_1[] = {
5581 { 0x01, 0, 0x6e65 },
5582 { 0x02, 0, 0x091f },
5583 { 0x03, 0, 0xc2f9 },
5584 { 0x06, 0, 0xafb5 },
5585 { 0x07, 0, 0x0e00 },
5586 { 0x19, 0, 0xec80 },
5587 { 0x01, 0, 0x2e65 },
5588 { 0x01, 0, 0x6e65 }
5589 };
5590 u8 cfg1;
5591
5592 rtl_set_def_aspm_entry_latency(tp);
5593
5594 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5595
5596 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5597
5598 RTL_W8(tp, Config1,
5599 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5600 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5601
5602 cfg1 = RTL_R8(tp, Config1);
5603 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5604 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5605
5606 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5607 }
5608
5609 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5610 {
5611 rtl_set_def_aspm_entry_latency(tp);
5612
5613 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5614
5615 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5616 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5617 }
5618
5619 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5620 {
5621 rtl_hw_start_8102e_2(tp);
5622
5623 rtl_ephy_write(tp, 0x03, 0xc2f9);
5624 }
5625
5626 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5627 {
5628 static const struct ephy_info e_info_8105e_1[] = {
5629 { 0x07, 0, 0x4000 },
5630 { 0x19, 0, 0x0200 },
5631 { 0x19, 0, 0x0020 },
5632 { 0x1e, 0, 0x2000 },
5633 { 0x03, 0, 0x0001 },
5634 { 0x19, 0, 0x0100 },
5635 { 0x19, 0, 0x0004 },
5636 { 0x0a, 0, 0x0020 }
5637 };
5638
5639 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5640 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5641
5642 /* Disable Early Tally Counter */
5643 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5644
5645 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5646 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5647
5648 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5649
5650 rtl_pcie_state_l2l3_disable(tp);
5651 }
5652
5653 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5654 {
5655 rtl_hw_start_8105e_1(tp);
5656 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5657 }
5658
5659 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5660 {
5661 static const struct ephy_info e_info_8402[] = {
5662 { 0x19, 0xffff, 0xff64 },
5663 { 0x1e, 0, 0x4000 }
5664 };
5665
5666 rtl_set_def_aspm_entry_latency(tp);
5667
5668 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5669 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5670
5671 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5672
5673 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5674
5675 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5676
5677 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5678 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5679 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5680 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5681 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5682 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5683 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5684
5685 rtl_pcie_state_l2l3_disable(tp);
5686 }
5687
5688 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5689 {
5690 rtl_hw_aspm_clkreq_enable(tp, false);
5691
5692 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5693 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5694
5695 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5696 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5697 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5698
5699 rtl_pcie_state_l2l3_disable(tp);
5700 rtl_hw_aspm_clkreq_enable(tp, true);
5701 }
5702
5703 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5704 {
5705 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5706 tp->irq_mask &= ~RxFIFOOver;
5707
5708 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5709 tp->mac_version == RTL_GIGA_MAC_VER_16)
5710 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5711 PCI_EXP_DEVCTL_NOSNOOP_EN);
5712
5713 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5714
5715 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5716 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5717
5718 switch (tp->mac_version) {
5719 case RTL_GIGA_MAC_VER_07:
5720 rtl_hw_start_8102e_1(tp);
5721 break;
5722
5723 case RTL_GIGA_MAC_VER_08:
5724 rtl_hw_start_8102e_3(tp);
5725 break;
5726
5727 case RTL_GIGA_MAC_VER_09:
5728 rtl_hw_start_8102e_2(tp);
5729 break;
5730
5731 case RTL_GIGA_MAC_VER_29:
5732 rtl_hw_start_8105e_1(tp);
5733 break;
5734 case RTL_GIGA_MAC_VER_30:
5735 rtl_hw_start_8105e_2(tp);
5736 break;
5737
5738 case RTL_GIGA_MAC_VER_37:
5739 rtl_hw_start_8402(tp);
5740 break;
5741
5742 case RTL_GIGA_MAC_VER_39:
5743 rtl_hw_start_8106(tp);
5744 break;
5745 case RTL_GIGA_MAC_VER_43:
5746 rtl_hw_start_8168g_2(tp);
5747 break;
5748 case RTL_GIGA_MAC_VER_47:
5749 case RTL_GIGA_MAC_VER_48:
5750 rtl_hw_start_8168h_1(tp);
5751 break;
5752 }
5753
5754 RTL_W16(tp, IntrMitigate, 0x0000);
5755 }
5756
5757 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5758 {
5759 struct rtl8169_private *tp = netdev_priv(dev);
5760
5761 if (new_mtu > ETH_DATA_LEN)
5762 rtl_hw_jumbo_enable(tp);
5763 else
5764 rtl_hw_jumbo_disable(tp);
5765
5766 dev->mtu = new_mtu;
5767 netdev_update_features(dev);
5768
5769 return 0;
5770 }
5771
5772 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5773 {
5774 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5775 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5776 }
5777
5778 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5779 void **data_buff, struct RxDesc *desc)
5780 {
5781 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5782 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5783
5784 kfree(*data_buff);
5785 *data_buff = NULL;
5786 rtl8169_make_unusable_by_asic(desc);
5787 }
5788
5789 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5790 {
5791 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5792
5793 /* Force memory writes to complete before releasing descriptor */
5794 dma_wmb();
5795
5796 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5797 }
5798
5799 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5800 struct RxDesc *desc)
5801 {
5802 void *data;
5803 dma_addr_t mapping;
5804 struct device *d = tp_to_dev(tp);
5805 int node = dev_to_node(d);
5806
5807 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5808 if (!data)
5809 return NULL;
5810
5811 /* Memory should be properly aligned, but better check. */
5812 if (!IS_ALIGNED((unsigned long)data, 8)) {
5813 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5814 goto err_out;
5815 }
5816
5817 mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5818 if (unlikely(dma_mapping_error(d, mapping))) {
5819 if (net_ratelimit())
5820 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5821 goto err_out;
5822 }
5823
5824 desc->addr = cpu_to_le64(mapping);
5825 rtl8169_mark_to_asic(desc);
5826 return data;
5827
5828 err_out:
5829 kfree(data);
5830 return NULL;
5831 }
5832
5833 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5834 {
5835 unsigned int i;
5836
5837 for (i = 0; i < NUM_RX_DESC; i++) {
5838 if (tp->Rx_databuff[i]) {
5839 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5840 tp->RxDescArray + i);
5841 }
5842 }
5843 }
5844
5845 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5846 {
5847 desc->opts1 |= cpu_to_le32(RingEnd);
5848 }
5849
5850 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5851 {
5852 unsigned int i;
5853
5854 for (i = 0; i < NUM_RX_DESC; i++) {
5855 void *data;
5856
5857 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5858 if (!data) {
5859 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5860 goto err_out;
5861 }
5862 tp->Rx_databuff[i] = data;
5863 }
5864
5865 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5866 return 0;
5867
5868 err_out:
5869 rtl8169_rx_clear(tp);
5870 return -ENOMEM;
5871 }
5872
5873 static int rtl8169_init_ring(struct rtl8169_private *tp)
5874 {
5875 rtl8169_init_ring_indexes(tp);
5876
5877 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5878 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5879
5880 return rtl8169_rx_fill(tp);
5881 }
5882
5883 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5884 struct TxDesc *desc)
5885 {
5886 unsigned int len = tx_skb->len;
5887
5888 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5889
5890 desc->opts1 = 0x00;
5891 desc->opts2 = 0x00;
5892 desc->addr = 0x00;
5893 tx_skb->len = 0;
5894 }
5895
5896 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5897 unsigned int n)
5898 {
5899 unsigned int i;
5900
5901 for (i = 0; i < n; i++) {
5902 unsigned int entry = (start + i) % NUM_TX_DESC;
5903 struct ring_info *tx_skb = tp->tx_skb + entry;
5904 unsigned int len = tx_skb->len;
5905
5906 if (len) {
5907 struct sk_buff *skb = tx_skb->skb;
5908
5909 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5910 tp->TxDescArray + entry);
5911 if (skb) {
5912 dev_consume_skb_any(skb);
5913 tx_skb->skb = NULL;
5914 }
5915 }
5916 }
5917 }
5918
5919 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5920 {
5921 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5922 tp->cur_tx = tp->dirty_tx = 0;
5923 netdev_reset_queue(tp->dev);
5924 }
5925
5926 static void rtl_reset_work(struct rtl8169_private *tp)
5927 {
5928 struct net_device *dev = tp->dev;
5929 int i;
5930
5931 napi_disable(&tp->napi);
5932 netif_stop_queue(dev);
5933 synchronize_rcu();
5934
5935 rtl8169_hw_reset(tp);
5936
5937 for (i = 0; i < NUM_RX_DESC; i++)
5938 rtl8169_mark_to_asic(tp->RxDescArray + i);
5939
5940 rtl8169_tx_clear(tp);
5941 rtl8169_init_ring_indexes(tp);
5942
5943 napi_enable(&tp->napi);
5944 rtl_hw_start(tp);
5945 netif_wake_queue(dev);
5946 }
5947
5948 static void rtl8169_tx_timeout(struct net_device *dev)
5949 {
5950 struct rtl8169_private *tp = netdev_priv(dev);
5951
5952 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5953 }
5954
5955 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5956 {
5957 u32 status = opts0 | len;
5958
5959 if (entry == NUM_TX_DESC - 1)
5960 status |= RingEnd;
5961
5962 return cpu_to_le32(status);
5963 }
5964
5965 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5966 u32 *opts)
5967 {
5968 struct skb_shared_info *info = skb_shinfo(skb);
5969 unsigned int cur_frag, entry;
5970 struct TxDesc *uninitialized_var(txd);
5971 struct device *d = tp_to_dev(tp);
5972
5973 entry = tp->cur_tx;
5974 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5975 const skb_frag_t *frag = info->frags + cur_frag;
5976 dma_addr_t mapping;
5977 u32 len;
5978 void *addr;
5979
5980 entry = (entry + 1) % NUM_TX_DESC;
5981
5982 txd = tp->TxDescArray + entry;
5983 len = skb_frag_size(frag);
5984 addr = skb_frag_address(frag);
5985 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5986 if (unlikely(dma_mapping_error(d, mapping))) {
5987 if (net_ratelimit())
5988 netif_err(tp, drv, tp->dev,
5989 "Failed to map TX fragments DMA!\n");
5990 goto err_out;
5991 }
5992
5993 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5994 txd->opts2 = cpu_to_le32(opts[1]);
5995 txd->addr = cpu_to_le64(mapping);
5996
5997 tp->tx_skb[entry].len = len;
5998 }
5999
6000 if (cur_frag) {
6001 tp->tx_skb[entry].skb = skb;
6002 txd->opts1 |= cpu_to_le32(LastFrag);
6003 }
6004
6005 return cur_frag;
6006
6007 err_out:
6008 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6009 return -EIO;
6010 }
6011
6012 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6013 {
6014 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6015 }
6016
6017 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6018 struct net_device *dev);
6019 /* r8169_csum_workaround()
6020 * The hw limites the value the transport offset. When the offset is out of the
6021 * range, calculate the checksum by sw.
6022 */
6023 static void r8169_csum_workaround(struct rtl8169_private *tp,
6024 struct sk_buff *skb)
6025 {
6026 if (skb_shinfo(skb)->gso_size) {
6027 netdev_features_t features = tp->dev->features;
6028 struct sk_buff *segs, *nskb;
6029
6030 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6031 segs = skb_gso_segment(skb, features);
6032 if (IS_ERR(segs) || !segs)
6033 goto drop;
6034
6035 do {
6036 nskb = segs;
6037 segs = segs->next;
6038 nskb->next = NULL;
6039 rtl8169_start_xmit(nskb, tp->dev);
6040 } while (segs);
6041
6042 dev_consume_skb_any(skb);
6043 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6044 if (skb_checksum_help(skb) < 0)
6045 goto drop;
6046
6047 rtl8169_start_xmit(skb, tp->dev);
6048 } else {
6049 struct net_device_stats *stats;
6050
6051 drop:
6052 stats = &tp->dev->stats;
6053 stats->tx_dropped++;
6054 dev_kfree_skb_any(skb);
6055 }
6056 }
6057
6058 /* msdn_giant_send_check()
6059 * According to the document of microsoft, the TCP Pseudo Header excludes the
6060 * packet length for IPv6 TCP large packets.
6061 */
6062 static int msdn_giant_send_check(struct sk_buff *skb)
6063 {
6064 const struct ipv6hdr *ipv6h;
6065 struct tcphdr *th;
6066 int ret;
6067
6068 ret = skb_cow_head(skb, 0);
6069 if (ret)
6070 return ret;
6071
6072 ipv6h = ipv6_hdr(skb);
6073 th = tcp_hdr(skb);
6074
6075 th->check = 0;
6076 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6077
6078 return ret;
6079 }
6080
6081 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6082 struct sk_buff *skb, u32 *opts)
6083 {
6084 u32 mss = skb_shinfo(skb)->gso_size;
6085
6086 if (mss) {
6087 opts[0] |= TD_LSO;
6088 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6089 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6090 const struct iphdr *ip = ip_hdr(skb);
6091
6092 if (ip->protocol == IPPROTO_TCP)
6093 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6094 else if (ip->protocol == IPPROTO_UDP)
6095 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6096 else
6097 WARN_ON_ONCE(1);
6098 }
6099
6100 return true;
6101 }
6102
6103 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6104 struct sk_buff *skb, u32 *opts)
6105 {
6106 u32 transport_offset = (u32)skb_transport_offset(skb);
6107 u32 mss = skb_shinfo(skb)->gso_size;
6108
6109 if (mss) {
6110 if (transport_offset > GTTCPHO_MAX) {
6111 netif_warn(tp, tx_err, tp->dev,
6112 "Invalid transport offset 0x%x for TSO\n",
6113 transport_offset);
6114 return false;
6115 }
6116
6117 switch (vlan_get_protocol(skb)) {
6118 case htons(ETH_P_IP):
6119 opts[0] |= TD1_GTSENV4;
6120 break;
6121
6122 case htons(ETH_P_IPV6):
6123 if (msdn_giant_send_check(skb))
6124 return false;
6125
6126 opts[0] |= TD1_GTSENV6;
6127 break;
6128
6129 default:
6130 WARN_ON_ONCE(1);
6131 break;
6132 }
6133
6134 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6135 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6136 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6137 u8 ip_protocol;
6138
6139 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6140 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6141
6142 if (transport_offset > TCPHO_MAX) {
6143 netif_warn(tp, tx_err, tp->dev,
6144 "Invalid transport offset 0x%x\n",
6145 transport_offset);
6146 return false;
6147 }
6148
6149 switch (vlan_get_protocol(skb)) {
6150 case htons(ETH_P_IP):
6151 opts[1] |= TD1_IPv4_CS;
6152 ip_protocol = ip_hdr(skb)->protocol;
6153 break;
6154
6155 case htons(ETH_P_IPV6):
6156 opts[1] |= TD1_IPv6_CS;
6157 ip_protocol = ipv6_hdr(skb)->nexthdr;
6158 break;
6159
6160 default:
6161 ip_protocol = IPPROTO_RAW;
6162 break;
6163 }
6164
6165 if (ip_protocol == IPPROTO_TCP)
6166 opts[1] |= TD1_TCP_CS;
6167 else if (ip_protocol == IPPROTO_UDP)
6168 opts[1] |= TD1_UDP_CS;
6169 else
6170 WARN_ON_ONCE(1);
6171
6172 opts[1] |= transport_offset << TCPHO_SHIFT;
6173 } else {
6174 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6175 return !eth_skb_pad(skb);
6176 }
6177
6178 return true;
6179 }
6180
6181 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
6182 unsigned int nr_frags)
6183 {
6184 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
6185
6186 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
6187 return slots_avail > nr_frags;
6188 }
6189
6190 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6191 struct net_device *dev)
6192 {
6193 struct rtl8169_private *tp = netdev_priv(dev);
6194 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6195 struct TxDesc *txd = tp->TxDescArray + entry;
6196 struct device *d = tp_to_dev(tp);
6197 dma_addr_t mapping;
6198 u32 opts[2], len;
6199 int frags;
6200
6201 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
6202 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6203 goto err_stop_0;
6204 }
6205
6206 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6207 goto err_stop_0;
6208
6209 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6210 opts[0] = DescOwn;
6211
6212 if (!tp->tso_csum(tp, skb, opts)) {
6213 r8169_csum_workaround(tp, skb);
6214 return NETDEV_TX_OK;
6215 }
6216
6217 len = skb_headlen(skb);
6218 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6219 if (unlikely(dma_mapping_error(d, mapping))) {
6220 if (net_ratelimit())
6221 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6222 goto err_dma_0;
6223 }
6224
6225 tp->tx_skb[entry].len = len;
6226 txd->addr = cpu_to_le64(mapping);
6227
6228 frags = rtl8169_xmit_frags(tp, skb, opts);
6229 if (frags < 0)
6230 goto err_dma_1;
6231 else if (frags)
6232 opts[0] |= FirstFrag;
6233 else {
6234 opts[0] |= FirstFrag | LastFrag;
6235 tp->tx_skb[entry].skb = skb;
6236 }
6237
6238 txd->opts2 = cpu_to_le32(opts[1]);
6239
6240 netdev_sent_queue(dev, skb->len);
6241
6242 skb_tx_timestamp(skb);
6243
6244 /* Force memory writes to complete before releasing descriptor */
6245 dma_wmb();
6246
6247 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6248
6249 /* Force all memory writes to complete before notifying device */
6250 wmb();
6251
6252 tp->cur_tx += frags + 1;
6253
6254 RTL_W8(tp, TxPoll, NPQ);
6255
6256 if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6257 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6258 * not miss a ring update when it notices a stopped queue.
6259 */
6260 smp_wmb();
6261 netif_stop_queue(dev);
6262 /* Sync with rtl_tx:
6263 * - publish queue status and cur_tx ring index (write barrier)
6264 * - refresh dirty_tx ring index (read barrier).
6265 * May the current thread have a pessimistic view of the ring
6266 * status and forget to wake up queue, a racing rtl_tx thread
6267 * can't.
6268 */
6269 smp_mb();
6270 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6271 netif_wake_queue(dev);
6272 }
6273
6274 return NETDEV_TX_OK;
6275
6276 err_dma_1:
6277 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6278 err_dma_0:
6279 dev_kfree_skb_any(skb);
6280 dev->stats.tx_dropped++;
6281 return NETDEV_TX_OK;
6282
6283 err_stop_0:
6284 netif_stop_queue(dev);
6285 dev->stats.tx_dropped++;
6286 return NETDEV_TX_BUSY;
6287 }
6288
6289 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6290 {
6291 struct rtl8169_private *tp = netdev_priv(dev);
6292 struct pci_dev *pdev = tp->pci_dev;
6293 u16 pci_status, pci_cmd;
6294
6295 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6296 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6297
6298 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6299 pci_cmd, pci_status);
6300
6301 /*
6302 * The recovery sequence below admits a very elaborated explanation:
6303 * - it seems to work;
6304 * - I did not see what else could be done;
6305 * - it makes iop3xx happy.
6306 *
6307 * Feel free to adjust to your needs.
6308 */
6309 if (pdev->broken_parity_status)
6310 pci_cmd &= ~PCI_COMMAND_PARITY;
6311 else
6312 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6313
6314 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6315
6316 pci_write_config_word(pdev, PCI_STATUS,
6317 pci_status & (PCI_STATUS_DETECTED_PARITY |
6318 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6319 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6320
6321 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6322 }
6323
6324 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6325 int budget)
6326 {
6327 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6328
6329 dirty_tx = tp->dirty_tx;
6330 smp_rmb();
6331 tx_left = tp->cur_tx - dirty_tx;
6332
6333 while (tx_left > 0) {
6334 unsigned int entry = dirty_tx % NUM_TX_DESC;
6335 struct ring_info *tx_skb = tp->tx_skb + entry;
6336 u32 status;
6337
6338 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6339 if (status & DescOwn)
6340 break;
6341
6342 /* This barrier is needed to keep us from reading
6343 * any other fields out of the Tx descriptor until
6344 * we know the status of DescOwn
6345 */
6346 dma_rmb();
6347
6348 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6349 tp->TxDescArray + entry);
6350 if (status & LastFrag) {
6351 pkts_compl++;
6352 bytes_compl += tx_skb->skb->len;
6353 napi_consume_skb(tx_skb->skb, budget);
6354 tx_skb->skb = NULL;
6355 }
6356 dirty_tx++;
6357 tx_left--;
6358 }
6359
6360 if (tp->dirty_tx != dirty_tx) {
6361 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6362
6363 u64_stats_update_begin(&tp->tx_stats.syncp);
6364 tp->tx_stats.packets += pkts_compl;
6365 tp->tx_stats.bytes += bytes_compl;
6366 u64_stats_update_end(&tp->tx_stats.syncp);
6367
6368 tp->dirty_tx = dirty_tx;
6369 /* Sync with rtl8169_start_xmit:
6370 * - publish dirty_tx ring index (write barrier)
6371 * - refresh cur_tx ring index and queue status (read barrier)
6372 * May the current thread miss the stopped queue condition,
6373 * a racing xmit thread can only have a right view of the
6374 * ring status.
6375 */
6376 smp_mb();
6377 if (netif_queue_stopped(dev) &&
6378 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6379 netif_wake_queue(dev);
6380 }
6381 /*
6382 * 8168 hack: TxPoll requests are lost when the Tx packets are
6383 * too close. Let's kick an extra TxPoll request when a burst
6384 * of start_xmit activity is detected (if it is not detected,
6385 * it is slow enough). -- FR
6386 */
6387 if (tp->cur_tx != dirty_tx)
6388 RTL_W8(tp, TxPoll, NPQ);
6389 }
6390 }
6391
6392 static inline int rtl8169_fragmented_frame(u32 status)
6393 {
6394 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6395 }
6396
6397 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6398 {
6399 u32 status = opts1 & RxProtoMask;
6400
6401 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6402 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6403 skb->ip_summed = CHECKSUM_UNNECESSARY;
6404 else
6405 skb_checksum_none_assert(skb);
6406 }
6407
6408 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6409 struct rtl8169_private *tp,
6410 int pkt_size,
6411 dma_addr_t addr)
6412 {
6413 struct sk_buff *skb;
6414 struct device *d = tp_to_dev(tp);
6415
6416 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6417 prefetch(data);
6418 skb = napi_alloc_skb(&tp->napi, pkt_size);
6419 if (skb)
6420 skb_copy_to_linear_data(skb, data, pkt_size);
6421 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6422
6423 return skb;
6424 }
6425
6426 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6427 {
6428 unsigned int cur_rx, rx_left;
6429 unsigned int count;
6430
6431 cur_rx = tp->cur_rx;
6432
6433 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6434 unsigned int entry = cur_rx % NUM_RX_DESC;
6435 struct RxDesc *desc = tp->RxDescArray + entry;
6436 u32 status;
6437
6438 status = le32_to_cpu(desc->opts1);
6439 if (status & DescOwn)
6440 break;
6441
6442 /* This barrier is needed to keep us from reading
6443 * any other fields out of the Rx descriptor until
6444 * we know the status of DescOwn
6445 */
6446 dma_rmb();
6447
6448 if (unlikely(status & RxRES)) {
6449 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6450 status);
6451 dev->stats.rx_errors++;
6452 if (status & (RxRWT | RxRUNT))
6453 dev->stats.rx_length_errors++;
6454 if (status & RxCRC)
6455 dev->stats.rx_crc_errors++;
6456 /* RxFOVF is a reserved bit on later chip versions */
6457 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6458 status & RxFOVF) {
6459 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6460 dev->stats.rx_fifo_errors++;
6461 } else if (status & (RxRUNT | RxCRC) &&
6462 !(status & RxRWT) &&
6463 dev->features & NETIF_F_RXALL) {
6464 goto process_pkt;
6465 }
6466 } else {
6467 struct sk_buff *skb;
6468 dma_addr_t addr;
6469 int pkt_size;
6470
6471 process_pkt:
6472 addr = le64_to_cpu(desc->addr);
6473 if (likely(!(dev->features & NETIF_F_RXFCS)))
6474 pkt_size = (status & 0x00003fff) - 4;
6475 else
6476 pkt_size = status & 0x00003fff;
6477
6478 /*
6479 * The driver does not support incoming fragmented
6480 * frames. They are seen as a symptom of over-mtu
6481 * sized frames.
6482 */
6483 if (unlikely(rtl8169_fragmented_frame(status))) {
6484 dev->stats.rx_dropped++;
6485 dev->stats.rx_length_errors++;
6486 goto release_descriptor;
6487 }
6488
6489 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6490 tp, pkt_size, addr);
6491 if (!skb) {
6492 dev->stats.rx_dropped++;
6493 goto release_descriptor;
6494 }
6495
6496 rtl8169_rx_csum(skb, status);
6497 skb_put(skb, pkt_size);
6498 skb->protocol = eth_type_trans(skb, dev);
6499
6500 rtl8169_rx_vlan_tag(desc, skb);
6501
6502 if (skb->pkt_type == PACKET_MULTICAST)
6503 dev->stats.multicast++;
6504
6505 napi_gro_receive(&tp->napi, skb);
6506
6507 u64_stats_update_begin(&tp->rx_stats.syncp);
6508 tp->rx_stats.packets++;
6509 tp->rx_stats.bytes += pkt_size;
6510 u64_stats_update_end(&tp->rx_stats.syncp);
6511 }
6512 release_descriptor:
6513 desc->opts2 = 0;
6514 rtl8169_mark_to_asic(desc);
6515 }
6516
6517 count = cur_rx - tp->cur_rx;
6518 tp->cur_rx = cur_rx;
6519
6520 return count;
6521 }
6522
6523 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6524 {
6525 struct rtl8169_private *tp = dev_instance;
6526 u16 status = RTL_R16(tp, IntrStatus);
6527
6528 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6529 return IRQ_NONE;
6530
6531 if (unlikely(status & SYSErr)) {
6532 rtl8169_pcierr_interrupt(tp->dev);
6533 goto out;
6534 }
6535
6536 if (status & LinkChg)
6537 phy_mac_interrupt(tp->phydev);
6538
6539 if (unlikely(status & RxFIFOOver &&
6540 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6541 netif_stop_queue(tp->dev);
6542 /* XXX - Hack alert. See rtl_task(). */
6543 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6544 }
6545
6546 if (status & (RTL_EVENT_NAPI | LinkChg)) {
6547 rtl_irq_disable(tp);
6548 napi_schedule_irqoff(&tp->napi);
6549 }
6550 out:
6551 rtl_ack_events(tp, status);
6552
6553 return IRQ_HANDLED;
6554 }
6555
6556 static void rtl_task(struct work_struct *work)
6557 {
6558 static const struct {
6559 int bitnr;
6560 void (*action)(struct rtl8169_private *);
6561 } rtl_work[] = {
6562 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6563 };
6564 struct rtl8169_private *tp =
6565 container_of(work, struct rtl8169_private, wk.work);
6566 struct net_device *dev = tp->dev;
6567 int i;
6568
6569 rtl_lock_work(tp);
6570
6571 if (!netif_running(dev) ||
6572 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6573 goto out_unlock;
6574
6575 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6576 bool pending;
6577
6578 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6579 if (pending)
6580 rtl_work[i].action(tp);
6581 }
6582
6583 out_unlock:
6584 rtl_unlock_work(tp);
6585 }
6586
6587 static int rtl8169_poll(struct napi_struct *napi, int budget)
6588 {
6589 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6590 struct net_device *dev = tp->dev;
6591 int work_done;
6592
6593 work_done = rtl_rx(dev, tp, (u32) budget);
6594
6595 rtl_tx(dev, tp, budget);
6596
6597 if (work_done < budget) {
6598 napi_complete_done(napi, work_done);
6599 rtl_irq_enable(tp);
6600 }
6601
6602 return work_done;
6603 }
6604
6605 static void rtl8169_rx_missed(struct net_device *dev)
6606 {
6607 struct rtl8169_private *tp = netdev_priv(dev);
6608
6609 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6610 return;
6611
6612 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6613 RTL_W32(tp, RxMissed, 0);
6614 }
6615
6616 static void r8169_phylink_handler(struct net_device *ndev)
6617 {
6618 struct rtl8169_private *tp = netdev_priv(ndev);
6619
6620 if (netif_carrier_ok(ndev)) {
6621 rtl_link_chg_patch(tp);
6622 pm_request_resume(&tp->pci_dev->dev);
6623 } else {
6624 pm_runtime_idle(&tp->pci_dev->dev);
6625 }
6626
6627 if (net_ratelimit())
6628 phy_print_status(tp->phydev);
6629 }
6630
6631 static int r8169_phy_connect(struct rtl8169_private *tp)
6632 {
6633 struct phy_device *phydev = tp->phydev;
6634 phy_interface_t phy_mode;
6635 int ret;
6636
6637 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6638 PHY_INTERFACE_MODE_MII;
6639
6640 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6641 phy_mode);
6642 if (ret)
6643 return ret;
6644
6645 if (!tp->supports_gmii)
6646 phy_set_max_speed(phydev, SPEED_100);
6647
6648 /* Ensure to advertise everything, incl. pause */
6649 linkmode_copy(phydev->advertising, phydev->supported);
6650
6651 phy_attached_info(phydev);
6652
6653 return 0;
6654 }
6655
6656 static void rtl8169_down(struct net_device *dev)
6657 {
6658 struct rtl8169_private *tp = netdev_priv(dev);
6659
6660 phy_stop(tp->phydev);
6661
6662 napi_disable(&tp->napi);
6663 netif_stop_queue(dev);
6664
6665 rtl8169_hw_reset(tp);
6666 /*
6667 * At this point device interrupts can not be enabled in any function,
6668 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6669 * and napi is disabled (rtl8169_poll).
6670 */
6671 rtl8169_rx_missed(dev);
6672
6673 /* Give a racing hard_start_xmit a few cycles to complete. */
6674 synchronize_rcu();
6675
6676 rtl8169_tx_clear(tp);
6677
6678 rtl8169_rx_clear(tp);
6679
6680 rtl_pll_power_down(tp);
6681 }
6682
6683 static int rtl8169_close(struct net_device *dev)
6684 {
6685 struct rtl8169_private *tp = netdev_priv(dev);
6686 struct pci_dev *pdev = tp->pci_dev;
6687
6688 pm_runtime_get_sync(&pdev->dev);
6689
6690 /* Update counters before going down */
6691 rtl8169_update_counters(tp);
6692
6693 rtl_lock_work(tp);
6694 /* Clear all task flags */
6695 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6696
6697 rtl8169_down(dev);
6698 rtl_unlock_work(tp);
6699
6700 cancel_work_sync(&tp->wk.work);
6701
6702 phy_disconnect(tp->phydev);
6703
6704 pci_free_irq(pdev, 0, tp);
6705
6706 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6707 tp->RxPhyAddr);
6708 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6709 tp->TxPhyAddr);
6710 tp->TxDescArray = NULL;
6711 tp->RxDescArray = NULL;
6712
6713 pm_runtime_put_sync(&pdev->dev);
6714
6715 return 0;
6716 }
6717
6718 #ifdef CONFIG_NET_POLL_CONTROLLER
6719 static void rtl8169_netpoll(struct net_device *dev)
6720 {
6721 struct rtl8169_private *tp = netdev_priv(dev);
6722
6723 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6724 }
6725 #endif
6726
6727 static int rtl_open(struct net_device *dev)
6728 {
6729 struct rtl8169_private *tp = netdev_priv(dev);
6730 struct pci_dev *pdev = tp->pci_dev;
6731 int retval = -ENOMEM;
6732
6733 pm_runtime_get_sync(&pdev->dev);
6734
6735 /*
6736 * Rx and Tx descriptors needs 256 bytes alignment.
6737 * dma_alloc_coherent provides more.
6738 */
6739 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6740 &tp->TxPhyAddr, GFP_KERNEL);
6741 if (!tp->TxDescArray)
6742 goto err_pm_runtime_put;
6743
6744 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6745 &tp->RxPhyAddr, GFP_KERNEL);
6746 if (!tp->RxDescArray)
6747 goto err_free_tx_0;
6748
6749 retval = rtl8169_init_ring(tp);
6750 if (retval < 0)
6751 goto err_free_rx_1;
6752
6753 rtl_request_firmware(tp);
6754
6755 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6756 dev->name);
6757 if (retval < 0)
6758 goto err_release_fw_2;
6759
6760 retval = r8169_phy_connect(tp);
6761 if (retval)
6762 goto err_free_irq;
6763
6764 rtl_lock_work(tp);
6765
6766 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6767
6768 napi_enable(&tp->napi);
6769
6770 rtl8169_init_phy(dev, tp);
6771
6772 rtl_pll_power_up(tp);
6773
6774 rtl_hw_start(tp);
6775
6776 if (!rtl8169_init_counter_offsets(tp))
6777 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6778
6779 phy_start(tp->phydev);
6780 netif_start_queue(dev);
6781
6782 rtl_unlock_work(tp);
6783
6784 pm_runtime_put_sync(&pdev->dev);
6785 out:
6786 return retval;
6787
6788 err_free_irq:
6789 pci_free_irq(pdev, 0, tp);
6790 err_release_fw_2:
6791 rtl_release_firmware(tp);
6792 rtl8169_rx_clear(tp);
6793 err_free_rx_1:
6794 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6795 tp->RxPhyAddr);
6796 tp->RxDescArray = NULL;
6797 err_free_tx_0:
6798 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6799 tp->TxPhyAddr);
6800 tp->TxDescArray = NULL;
6801 err_pm_runtime_put:
6802 pm_runtime_put_noidle(&pdev->dev);
6803 goto out;
6804 }
6805
6806 static void
6807 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6808 {
6809 struct rtl8169_private *tp = netdev_priv(dev);
6810 struct pci_dev *pdev = tp->pci_dev;
6811 struct rtl8169_counters *counters = tp->counters;
6812 unsigned int start;
6813
6814 pm_runtime_get_noresume(&pdev->dev);
6815
6816 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6817 rtl8169_rx_missed(dev);
6818
6819 do {
6820 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6821 stats->rx_packets = tp->rx_stats.packets;
6822 stats->rx_bytes = tp->rx_stats.bytes;
6823 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6824
6825 do {
6826 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6827 stats->tx_packets = tp->tx_stats.packets;
6828 stats->tx_bytes = tp->tx_stats.bytes;
6829 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6830
6831 stats->rx_dropped = dev->stats.rx_dropped;
6832 stats->tx_dropped = dev->stats.tx_dropped;
6833 stats->rx_length_errors = dev->stats.rx_length_errors;
6834 stats->rx_errors = dev->stats.rx_errors;
6835 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6836 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6837 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6838 stats->multicast = dev->stats.multicast;
6839
6840 /*
6841 * Fetch additonal counter values missing in stats collected by driver
6842 * from tally counters.
6843 */
6844 if (pm_runtime_active(&pdev->dev))
6845 rtl8169_update_counters(tp);
6846
6847 /*
6848 * Subtract values fetched during initalization.
6849 * See rtl8169_init_counter_offsets for a description why we do that.
6850 */
6851 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6852 le64_to_cpu(tp->tc_offset.tx_errors);
6853 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6854 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6855 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6856 le16_to_cpu(tp->tc_offset.tx_aborted);
6857
6858 pm_runtime_put_noidle(&pdev->dev);
6859 }
6860
6861 static void rtl8169_net_suspend(struct net_device *dev)
6862 {
6863 struct rtl8169_private *tp = netdev_priv(dev);
6864
6865 if (!netif_running(dev))
6866 return;
6867
6868 phy_stop(tp->phydev);
6869 netif_device_detach(dev);
6870
6871 rtl_lock_work(tp);
6872 napi_disable(&tp->napi);
6873 /* Clear all task flags */
6874 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6875
6876 rtl_unlock_work(tp);
6877
6878 rtl_pll_power_down(tp);
6879 }
6880
6881 #ifdef CONFIG_PM
6882
6883 static int rtl8169_suspend(struct device *device)
6884 {
6885 struct net_device *dev = dev_get_drvdata(device);
6886 struct rtl8169_private *tp = netdev_priv(dev);
6887
6888 rtl8169_net_suspend(dev);
6889 clk_disable_unprepare(tp->clk);
6890
6891 return 0;
6892 }
6893
6894 static void __rtl8169_resume(struct net_device *dev)
6895 {
6896 struct rtl8169_private *tp = netdev_priv(dev);
6897
6898 netif_device_attach(dev);
6899
6900 rtl_pll_power_up(tp);
6901 rtl8169_init_phy(dev, tp);
6902
6903 phy_start(tp->phydev);
6904
6905 rtl_lock_work(tp);
6906 napi_enable(&tp->napi);
6907 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6908 rtl_reset_work(tp);
6909 rtl_unlock_work(tp);
6910 }
6911
6912 static int rtl8169_resume(struct device *device)
6913 {
6914 struct net_device *dev = dev_get_drvdata(device);
6915 struct rtl8169_private *tp = netdev_priv(dev);
6916
6917 clk_prepare_enable(tp->clk);
6918
6919 if (netif_running(dev))
6920 __rtl8169_resume(dev);
6921
6922 return 0;
6923 }
6924
6925 static int rtl8169_runtime_suspend(struct device *device)
6926 {
6927 struct net_device *dev = dev_get_drvdata(device);
6928 struct rtl8169_private *tp = netdev_priv(dev);
6929
6930 if (!tp->TxDescArray)
6931 return 0;
6932
6933 rtl_lock_work(tp);
6934 __rtl8169_set_wol(tp, WAKE_ANY);
6935 rtl_unlock_work(tp);
6936
6937 rtl8169_net_suspend(dev);
6938
6939 /* Update counters before going runtime suspend */
6940 rtl8169_rx_missed(dev);
6941 rtl8169_update_counters(tp);
6942
6943 return 0;
6944 }
6945
6946 static int rtl8169_runtime_resume(struct device *device)
6947 {
6948 struct net_device *dev = dev_get_drvdata(device);
6949 struct rtl8169_private *tp = netdev_priv(dev);
6950 rtl_rar_set(tp, dev->dev_addr);
6951
6952 if (!tp->TxDescArray)
6953 return 0;
6954
6955 rtl_lock_work(tp);
6956 __rtl8169_set_wol(tp, tp->saved_wolopts);
6957 rtl_unlock_work(tp);
6958
6959 __rtl8169_resume(dev);
6960
6961 return 0;
6962 }
6963
6964 static int rtl8169_runtime_idle(struct device *device)
6965 {
6966 struct net_device *dev = dev_get_drvdata(device);
6967
6968 if (!netif_running(dev) || !netif_carrier_ok(dev))
6969 pm_schedule_suspend(device, 10000);
6970
6971 return -EBUSY;
6972 }
6973
6974 static const struct dev_pm_ops rtl8169_pm_ops = {
6975 .suspend = rtl8169_suspend,
6976 .resume = rtl8169_resume,
6977 .freeze = rtl8169_suspend,
6978 .thaw = rtl8169_resume,
6979 .poweroff = rtl8169_suspend,
6980 .restore = rtl8169_resume,
6981 .runtime_suspend = rtl8169_runtime_suspend,
6982 .runtime_resume = rtl8169_runtime_resume,
6983 .runtime_idle = rtl8169_runtime_idle,
6984 };
6985
6986 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6987
6988 #else /* !CONFIG_PM */
6989
6990 #define RTL8169_PM_OPS NULL
6991
6992 #endif /* !CONFIG_PM */
6993
6994 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6995 {
6996 /* WoL fails with 8168b when the receiver is disabled. */
6997 switch (tp->mac_version) {
6998 case RTL_GIGA_MAC_VER_11:
6999 case RTL_GIGA_MAC_VER_12:
7000 case RTL_GIGA_MAC_VER_17:
7001 pci_clear_master(tp->pci_dev);
7002
7003 RTL_W8(tp, ChipCmd, CmdRxEnb);
7004 /* PCI commit */
7005 RTL_R8(tp, ChipCmd);
7006 break;
7007 default:
7008 break;
7009 }
7010 }
7011
7012 static void rtl_shutdown(struct pci_dev *pdev)
7013 {
7014 struct net_device *dev = pci_get_drvdata(pdev);
7015 struct rtl8169_private *tp = netdev_priv(dev);
7016
7017 rtl8169_net_suspend(dev);
7018
7019 /* Restore original MAC address */
7020 rtl_rar_set(tp, dev->perm_addr);
7021
7022 rtl8169_hw_reset(tp);
7023
7024 if (system_state == SYSTEM_POWER_OFF) {
7025 if (tp->saved_wolopts) {
7026 rtl_wol_suspend_quirk(tp);
7027 rtl_wol_shutdown_quirk(tp);
7028 }
7029
7030 pci_wake_from_d3(pdev, true);
7031 pci_set_power_state(pdev, PCI_D3hot);
7032 }
7033 }
7034
7035 static void rtl_remove_one(struct pci_dev *pdev)
7036 {
7037 struct net_device *dev = pci_get_drvdata(pdev);
7038 struct rtl8169_private *tp = netdev_priv(dev);
7039
7040 if (r8168_check_dash(tp))
7041 rtl8168_driver_stop(tp);
7042
7043 netif_napi_del(&tp->napi);
7044
7045 unregister_netdev(dev);
7046 mdiobus_unregister(tp->phydev->mdio.bus);
7047
7048 rtl_release_firmware(tp);
7049
7050 if (pci_dev_run_wake(pdev))
7051 pm_runtime_get_noresume(&pdev->dev);
7052
7053 /* restore original MAC address */
7054 rtl_rar_set(tp, dev->perm_addr);
7055 }
7056
7057 static const struct net_device_ops rtl_netdev_ops = {
7058 .ndo_open = rtl_open,
7059 .ndo_stop = rtl8169_close,
7060 .ndo_get_stats64 = rtl8169_get_stats64,
7061 .ndo_start_xmit = rtl8169_start_xmit,
7062 .ndo_tx_timeout = rtl8169_tx_timeout,
7063 .ndo_validate_addr = eth_validate_addr,
7064 .ndo_change_mtu = rtl8169_change_mtu,
7065 .ndo_fix_features = rtl8169_fix_features,
7066 .ndo_set_features = rtl8169_set_features,
7067 .ndo_set_mac_address = rtl_set_mac_address,
7068 .ndo_do_ioctl = rtl8169_ioctl,
7069 .ndo_set_rx_mode = rtl_set_rx_mode,
7070 #ifdef CONFIG_NET_POLL_CONTROLLER
7071 .ndo_poll_controller = rtl8169_netpoll,
7072 #endif
7073
7074 };
7075
7076 static const struct rtl_cfg_info {
7077 void (*hw_start)(struct rtl8169_private *tp);
7078 u16 irq_mask;
7079 unsigned int has_gmii:1;
7080 const struct rtl_coalesce_info *coalesce_info;
7081 } rtl_cfg_infos [] = {
7082 [RTL_CFG_0] = {
7083 .hw_start = rtl_hw_start_8169,
7084 .irq_mask = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7085 .has_gmii = 1,
7086 .coalesce_info = rtl_coalesce_info_8169,
7087 },
7088 [RTL_CFG_1] = {
7089 .hw_start = rtl_hw_start_8168,
7090 .irq_mask = LinkChg | RxOverflow,
7091 .has_gmii = 1,
7092 .coalesce_info = rtl_coalesce_info_8168_8136,
7093 },
7094 [RTL_CFG_2] = {
7095 .hw_start = rtl_hw_start_8101,
7096 .irq_mask = LinkChg | RxOverflow | RxFIFOOver,
7097 .coalesce_info = rtl_coalesce_info_8168_8136,
7098 }
7099 };
7100
7101 static int rtl_alloc_irq(struct rtl8169_private *tp)
7102 {
7103 unsigned int flags;
7104
7105 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7106 rtl_unlock_config_regs(tp);
7107 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7108 rtl_lock_config_regs(tp);
7109 flags = PCI_IRQ_LEGACY;
7110 } else {
7111 flags = PCI_IRQ_ALL_TYPES;
7112 }
7113
7114 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7115 }
7116
7117 static void rtl_read_mac_address(struct rtl8169_private *tp,
7118 u8 mac_addr[ETH_ALEN])
7119 {
7120 u32 value;
7121
7122 /* Get MAC address */
7123 switch (tp->mac_version) {
7124 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7125 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7126 value = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7127 mac_addr[0] = (value >> 0) & 0xff;
7128 mac_addr[1] = (value >> 8) & 0xff;
7129 mac_addr[2] = (value >> 16) & 0xff;
7130 mac_addr[3] = (value >> 24) & 0xff;
7131
7132 value = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7133 mac_addr[4] = (value >> 0) & 0xff;
7134 mac_addr[5] = (value >> 8) & 0xff;
7135 break;
7136 default:
7137 break;
7138 }
7139 }
7140
7141 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7142 {
7143 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7144 }
7145
7146 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7147 {
7148 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7149 }
7150
7151 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7152 {
7153 struct rtl8169_private *tp = mii_bus->priv;
7154
7155 if (phyaddr > 0)
7156 return -ENODEV;
7157
7158 return rtl_readphy(tp, phyreg);
7159 }
7160
7161 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7162 int phyreg, u16 val)
7163 {
7164 struct rtl8169_private *tp = mii_bus->priv;
7165
7166 if (phyaddr > 0)
7167 return -ENODEV;
7168
7169 rtl_writephy(tp, phyreg, val);
7170
7171 return 0;
7172 }
7173
7174 static int r8169_mdio_register(struct rtl8169_private *tp)
7175 {
7176 struct pci_dev *pdev = tp->pci_dev;
7177 struct mii_bus *new_bus;
7178 int ret;
7179
7180 new_bus = devm_mdiobus_alloc(&pdev->dev);
7181 if (!new_bus)
7182 return -ENOMEM;
7183
7184 new_bus->name = "r8169";
7185 new_bus->priv = tp;
7186 new_bus->parent = &pdev->dev;
7187 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7188 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7189 PCI_DEVID(pdev->bus->number, pdev->devfn));
7190
7191 new_bus->read = r8169_mdio_read_reg;
7192 new_bus->write = r8169_mdio_write_reg;
7193
7194 ret = mdiobus_register(new_bus);
7195 if (ret)
7196 return ret;
7197
7198 tp->phydev = mdiobus_get_phy(new_bus, 0);
7199 if (!tp->phydev) {
7200 mdiobus_unregister(new_bus);
7201 return -ENODEV;
7202 }
7203
7204 /* PHY will be woken up in rtl_open() */
7205 phy_suspend(tp->phydev);
7206
7207 return 0;
7208 }
7209
7210 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7211 {
7212 u32 data;
7213
7214 tp->ocp_base = OCP_STD_PHY_BASE;
7215
7216 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7217
7218 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7219 return;
7220
7221 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7222 return;
7223
7224 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7225 msleep(1);
7226 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7227
7228 data = r8168_mac_ocp_read(tp, 0xe8de);
7229 data &= ~(1 << 14);
7230 r8168_mac_ocp_write(tp, 0xe8de, data);
7231
7232 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7233 return;
7234
7235 data = r8168_mac_ocp_read(tp, 0xe8de);
7236 data |= (1 << 15);
7237 r8168_mac_ocp_write(tp, 0xe8de, data);
7238
7239 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7240 return;
7241 }
7242
7243 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7244 {
7245 rtl8168ep_stop_cmac(tp);
7246 rtl_hw_init_8168g(tp);
7247 }
7248
7249 static void rtl_hw_initialize(struct rtl8169_private *tp)
7250 {
7251 switch (tp->mac_version) {
7252 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7253 rtl_hw_init_8168g(tp);
7254 break;
7255 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7256 rtl_hw_init_8168ep(tp);
7257 break;
7258 default:
7259 break;
7260 }
7261 }
7262
7263 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7264 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7265 {
7266 switch (tp->mac_version) {
7267 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7268 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7269 return false;
7270 default:
7271 return true;
7272 }
7273 }
7274
7275 static int rtl_jumbo_max(struct rtl8169_private *tp)
7276 {
7277 /* Non-GBit versions don't support jumbo frames */
7278 if (!tp->supports_gmii)
7279 return JUMBO_1K;
7280
7281 switch (tp->mac_version) {
7282 /* RTL8169 */
7283 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7284 return JUMBO_7K;
7285 /* RTL8168b */
7286 case RTL_GIGA_MAC_VER_11:
7287 case RTL_GIGA_MAC_VER_12:
7288 case RTL_GIGA_MAC_VER_17:
7289 return JUMBO_4K;
7290 /* RTL8168c */
7291 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7292 return JUMBO_6K;
7293 default:
7294 return JUMBO_9K;
7295 }
7296 }
7297
7298 static void rtl_disable_clk(void *data)
7299 {
7300 clk_disable_unprepare(data);
7301 }
7302
7303 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7304 {
7305 struct device *d = tp_to_dev(tp);
7306 struct clk *clk;
7307 int rc;
7308
7309 clk = devm_clk_get(d, "ether_clk");
7310 if (IS_ERR(clk)) {
7311 rc = PTR_ERR(clk);
7312 if (rc == -ENOENT)
7313 /* clk-core allows NULL (for suspend / resume) */
7314 rc = 0;
7315 else if (rc != -EPROBE_DEFER)
7316 dev_err(d, "failed to get clk: %d\n", rc);
7317 } else {
7318 tp->clk = clk;
7319 rc = clk_prepare_enable(clk);
7320 if (rc)
7321 dev_err(d, "failed to enable clk: %d\n", rc);
7322 else
7323 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7324 }
7325
7326 return rc;
7327 }
7328
7329 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7330 {
7331 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7332 /* align to u16 for is_valid_ether_addr() */
7333 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7334 struct rtl8169_private *tp;
7335 struct net_device *dev;
7336 int chipset, region, i;
7337 int jumbo_max, rc;
7338
7339 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7340 if (!dev)
7341 return -ENOMEM;
7342
7343 SET_NETDEV_DEV(dev, &pdev->dev);
7344 dev->netdev_ops = &rtl_netdev_ops;
7345 tp = netdev_priv(dev);
7346 tp->dev = dev;
7347 tp->pci_dev = pdev;
7348 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7349 tp->supports_gmii = cfg->has_gmii;
7350
7351 /* Get the *optional* external "ether_clk" used on some boards */
7352 rc = rtl_get_ether_clk(tp);
7353 if (rc)
7354 return rc;
7355
7356 /* Disable ASPM completely as that cause random device stop working
7357 * problems as well as full system hangs for some PCIe devices users.
7358 */
7359 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7360
7361 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7362 rc = pcim_enable_device(pdev);
7363 if (rc < 0) {
7364 dev_err(&pdev->dev, "enable failure\n");
7365 return rc;
7366 }
7367
7368 if (pcim_set_mwi(pdev) < 0)
7369 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7370
7371 /* use first MMIO region */
7372 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7373 if (region < 0) {
7374 dev_err(&pdev->dev, "no MMIO resource found\n");
7375 return -ENODEV;
7376 }
7377
7378 /* check for weird/broken PCI region reporting */
7379 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7380 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7381 return -ENODEV;
7382 }
7383
7384 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7385 if (rc < 0) {
7386 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7387 return rc;
7388 }
7389
7390 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7391
7392 /* Identify chip attached to board */
7393 rtl8169_get_mac_version(tp);
7394 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7395 return -ENODEV;
7396
7397 if (rtl_tbi_enabled(tp)) {
7398 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7399 return -ENODEV;
7400 }
7401
7402 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7403
7404 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7405 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7406 dev->features |= NETIF_F_HIGHDMA;
7407 } else {
7408 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7409 if (rc < 0) {
7410 dev_err(&pdev->dev, "DMA configuration failed\n");
7411 return rc;
7412 }
7413 }
7414
7415 rtl_init_rxcfg(tp);
7416
7417 rtl8169_irq_mask_and_ack(tp);
7418
7419 rtl_hw_initialize(tp);
7420
7421 rtl_hw_reset(tp);
7422
7423 pci_set_master(pdev);
7424
7425 rtl_init_mdio_ops(tp);
7426 rtl_init_jumbo_ops(tp);
7427
7428 chipset = tp->mac_version;
7429
7430 rc = rtl_alloc_irq(tp);
7431 if (rc < 0) {
7432 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7433 return rc;
7434 }
7435
7436 mutex_init(&tp->wk.mutex);
7437 INIT_WORK(&tp->wk.work, rtl_task);
7438 u64_stats_init(&tp->rx_stats.syncp);
7439 u64_stats_init(&tp->tx_stats.syncp);
7440
7441 /* get MAC address */
7442 rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7443 if (rc)
7444 rtl_read_mac_address(tp, mac_addr);
7445
7446 if (is_valid_ether_addr(mac_addr))
7447 rtl_rar_set(tp, mac_addr);
7448
7449 for (i = 0; i < ETH_ALEN; i++)
7450 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7451
7452 dev->ethtool_ops = &rtl8169_ethtool_ops;
7453
7454 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7455
7456 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7457 * properly for all devices */
7458 dev->features |= NETIF_F_RXCSUM |
7459 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7460
7461 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7462 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7463 NETIF_F_HW_VLAN_CTAG_RX;
7464 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7465 NETIF_F_HIGHDMA;
7466 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7467
7468 tp->cp_cmd |= RxChkSum | RxVlan;
7469
7470 /*
7471 * Pretend we are using VLANs; This bypasses a nasty bug where
7472 * Interrupts stop flowing on high load on 8110SCd controllers.
7473 */
7474 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7475 /* Disallow toggling */
7476 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7477
7478 if (rtl_chip_supports_csum_v2(tp)) {
7479 tp->tso_csum = rtl8169_tso_csum_v2;
7480 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7481 } else {
7482 tp->tso_csum = rtl8169_tso_csum_v1;
7483 }
7484
7485 dev->hw_features |= NETIF_F_RXALL;
7486 dev->hw_features |= NETIF_F_RXFCS;
7487
7488 /* MTU range: 60 - hw-specific max */
7489 dev->min_mtu = ETH_ZLEN;
7490 jumbo_max = rtl_jumbo_max(tp);
7491 dev->max_mtu = jumbo_max;
7492
7493 tp->hw_start = cfg->hw_start;
7494 tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7495 tp->coalesce_info = cfg->coalesce_info;
7496
7497 tp->fw_name = rtl_chip_infos[chipset].fw_name;
7498
7499 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7500 &tp->counters_phys_addr,
7501 GFP_KERNEL);
7502 if (!tp->counters)
7503 return -ENOMEM;
7504
7505 pci_set_drvdata(pdev, dev);
7506
7507 rc = r8169_mdio_register(tp);
7508 if (rc)
7509 return rc;
7510
7511 /* chip gets powered up in rtl_open() */
7512 rtl_pll_power_down(tp);
7513
7514 rc = register_netdev(dev);
7515 if (rc)
7516 goto err_mdio_unregister;
7517
7518 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7519 rtl_chip_infos[chipset].name, dev->dev_addr,
7520 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7521 pci_irq_vector(pdev, 0));
7522
7523 if (jumbo_max > JUMBO_1K)
7524 netif_info(tp, probe, dev,
7525 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7526 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7527 "ok" : "ko");
7528
7529 if (r8168_check_dash(tp))
7530 rtl8168_driver_start(tp);
7531
7532 if (pci_dev_run_wake(pdev))
7533 pm_runtime_put_sync(&pdev->dev);
7534
7535 return 0;
7536
7537 err_mdio_unregister:
7538 mdiobus_unregister(tp->phydev->mdio.bus);
7539 return rc;
7540 }
7541
7542 static struct pci_driver rtl8169_pci_driver = {
7543 .name = MODULENAME,
7544 .id_table = rtl8169_pci_tbl,
7545 .probe = rtl_init_one,
7546 .remove = rtl_remove_one,
7547 .shutdown = rtl_shutdown,
7548 .driver.pm = RTL8169_PM_OPS,
7549 };
7550
7551 module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git