2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/async.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
33 #include <linux/pci-p2pdma.h>
37 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
38 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
40 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
43 * These can be higher, but we need to ensure that any command doesn't
44 * require an sg allocation that needs more than a page of data.
46 #define NVME_MAX_KB_SZ 4096
47 #define NVME_MAX_SEGS 127
49 static int use_threaded_interrupts
;
50 module_param(use_threaded_interrupts
, int, 0);
52 static bool use_cmb_sqes
= true;
53 module_param(use_cmb_sqes
, bool, 0444);
54 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
56 static unsigned int max_host_mem_size_mb
= 128;
57 module_param(max_host_mem_size_mb
, uint
, 0444);
58 MODULE_PARM_DESC(max_host_mem_size_mb
,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
61 static unsigned int sgl_threshold
= SZ_32K
;
62 module_param(sgl_threshold
, uint
, 0644);
63 MODULE_PARM_DESC(sgl_threshold
,
64 "Use SGLs when average request segment size is larger or equal to "
65 "this size. Use 0 to disable SGLs.");
67 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
);
68 static const struct kernel_param_ops io_queue_depth_ops
= {
69 .set
= io_queue_depth_set
,
73 static int io_queue_depth
= 1024;
74 module_param_cb(io_queue_depth
, &io_queue_depth_ops
, &io_queue_depth
, 0644);
75 MODULE_PARM_DESC(io_queue_depth
, "set io queue depth, should >= 2");
80 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
83 * Represents an NVM Express device. Each nvme_dev is a PCI function.
86 struct nvme_queue
*queues
;
87 struct blk_mq_tag_set tagset
;
88 struct blk_mq_tag_set admin_tagset
;
91 struct dma_pool
*prp_page_pool
;
92 struct dma_pool
*prp_small_pool
;
93 unsigned online_queues
;
95 unsigned int num_vecs
;
99 unsigned long bar_mapped_size
;
100 struct work_struct remove_work
;
101 struct mutex shutdown_lock
;
107 struct nvme_ctrl ctrl
;
108 struct completion ioq_wait
;
110 mempool_t
*iod_mempool
;
112 /* shadow doorbell buffer support: */
114 dma_addr_t dbbuf_dbs_dma_addr
;
116 dma_addr_t dbbuf_eis_dma_addr
;
118 /* host memory buffer support: */
120 u32 nr_host_mem_descs
;
121 dma_addr_t host_mem_descs_dma
;
122 struct nvme_host_mem_buf_desc
*host_mem_descs
;
123 void **host_mem_desc_bufs
;
126 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
)
130 ret
= kstrtoint(val
, 10, &n
);
131 if (ret
!= 0 || n
< 2)
134 return param_set_int(val
, kp
);
137 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
139 return qid
* 2 * stride
;
142 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
144 return (qid
* 2 + 1) * stride
;
147 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
149 return container_of(ctrl
, struct nvme_dev
, ctrl
);
153 * An NVM Express queue. Each device has at least two (one for admin
154 * commands and one for I/O commands).
157 struct device
*q_dmadev
;
158 struct nvme_dev
*dev
;
160 struct nvme_command
*sq_cmds
;
162 spinlock_t cq_lock ____cacheline_aligned_in_smp
;
163 volatile struct nvme_completion
*cqes
;
164 struct blk_mq_tags
**tags
;
165 dma_addr_t sq_dma_addr
;
166 dma_addr_t cq_dma_addr
;
182 * The nvme_iod describes the data in an I/O, including the list of PRP
183 * entries. You can't see it in this data structure because C doesn't let
184 * me express that. Use nvme_init_iod to ensure there's enough space
185 * allocated to store the PRP list.
188 struct nvme_request req
;
189 struct nvme_queue
*nvmeq
;
192 int npages
; /* In the PRP list. 0 means small pool in use */
193 int nents
; /* Used in scatterlist */
194 int length
; /* Of data, in bytes */
195 dma_addr_t first_dma
;
196 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
197 struct scatterlist
*sg
;
198 struct scatterlist inline_sg
[0];
202 * Check we didin't inadvertently grow the command struct
204 static inline void _nvme_check_size(void)
206 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
207 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
208 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
209 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
210 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
211 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
212 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
213 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
214 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != NVME_IDENTIFY_DATA_SIZE
);
215 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != NVME_IDENTIFY_DATA_SIZE
);
216 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
217 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
218 BUILD_BUG_ON(sizeof(struct nvme_dbbuf
) != 64);
221 static inline unsigned int nvme_dbbuf_size(u32 stride
)
223 return ((num_possible_cpus() + 1) * 8 * stride
);
226 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
228 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
233 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
234 &dev
->dbbuf_dbs_dma_addr
,
238 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
239 &dev
->dbbuf_eis_dma_addr
,
241 if (!dev
->dbbuf_eis
) {
242 dma_free_coherent(dev
->dev
, mem_size
,
243 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
244 dev
->dbbuf_dbs
= NULL
;
251 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
253 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
255 if (dev
->dbbuf_dbs
) {
256 dma_free_coherent(dev
->dev
, mem_size
,
257 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
258 dev
->dbbuf_dbs
= NULL
;
260 if (dev
->dbbuf_eis
) {
261 dma_free_coherent(dev
->dev
, mem_size
,
262 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
263 dev
->dbbuf_eis
= NULL
;
267 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
268 struct nvme_queue
*nvmeq
, int qid
)
270 if (!dev
->dbbuf_dbs
|| !qid
)
273 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
274 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
275 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
276 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
279 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
281 struct nvme_command c
;
286 memset(&c
, 0, sizeof(c
));
287 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
288 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
289 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
291 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
292 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
293 /* Free memory and continue on */
294 nvme_dbbuf_dma_free(dev
);
298 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
300 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
303 /* Update dbbuf and return true if an MMIO is required */
304 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
305 volatile u32
*dbbuf_ei
)
311 * Ensure that the queue is written before updating
312 * the doorbell in memory
316 old_value
= *dbbuf_db
;
320 * Ensure that the doorbell is updated before reading the event
321 * index from memory. The controller needs to provide similar
322 * ordering to ensure the envent index is updated before reading
327 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
335 * Max size of iod being embedded in the request payload
337 #define NVME_INT_PAGES 2
338 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
341 * Will slightly overestimate the number of pages needed. This is OK
342 * as it only leads to a small amount of wasted memory for the lifetime of
345 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
347 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
348 dev
->ctrl
.page_size
);
349 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
353 * Calculates the number of pages needed for the SGL segments. For example a 4k
354 * page can accommodate 256 SGL descriptors.
356 static int nvme_pci_npages_sgl(unsigned int num_seg
)
358 return DIV_ROUND_UP(num_seg
* sizeof(struct nvme_sgl_desc
), PAGE_SIZE
);
361 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev
*dev
,
362 unsigned int size
, unsigned int nseg
, bool use_sgl
)
367 alloc_size
= sizeof(__le64
*) * nvme_pci_npages_sgl(nseg
);
369 alloc_size
= sizeof(__le64
*) * nvme_npages(size
, dev
);
371 return alloc_size
+ sizeof(struct scatterlist
) * nseg
;
374 static unsigned int nvme_pci_cmd_size(struct nvme_dev
*dev
, bool use_sgl
)
376 unsigned int alloc_size
= nvme_pci_iod_alloc_size(dev
,
377 NVME_INT_BYTES(dev
), NVME_INT_PAGES
,
380 return sizeof(struct nvme_iod
) + alloc_size
;
383 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
384 unsigned int hctx_idx
)
386 struct nvme_dev
*dev
= data
;
387 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
389 WARN_ON(hctx_idx
!= 0);
390 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
391 WARN_ON(nvmeq
->tags
);
393 hctx
->driver_data
= nvmeq
;
394 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
398 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
400 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
405 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
406 unsigned int hctx_idx
)
408 struct nvme_dev
*dev
= data
;
409 struct nvme_queue
*nvmeq
= &dev
->queues
[hctx_idx
+ 1];
412 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
414 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
415 hctx
->driver_data
= nvmeq
;
419 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
420 unsigned int hctx_idx
, unsigned int numa_node
)
422 struct nvme_dev
*dev
= set
->driver_data
;
423 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
424 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
425 struct nvme_queue
*nvmeq
= &dev
->queues
[queue_idx
];
430 nvme_req(req
)->ctrl
= &dev
->ctrl
;
434 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
436 struct nvme_dev
*dev
= set
->driver_data
;
438 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
),
439 dev
->num_vecs
> 1 ? 1 /* admin queue */ : 0);
443 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
444 * @nvmeq: The queue to use
445 * @cmd: The command to send
447 static void nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
449 spin_lock(&nvmeq
->sq_lock
);
451 memcpy(&nvmeq
->sq_cmds
[nvmeq
->sq_tail
], cmd
, sizeof(*cmd
));
453 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
455 if (nvme_dbbuf_update_and_check_event(nvmeq
->sq_tail
,
456 nvmeq
->dbbuf_sq_db
, nvmeq
->dbbuf_sq_ei
))
457 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
458 spin_unlock(&nvmeq
->sq_lock
);
461 static void **nvme_pci_iod_list(struct request
*req
)
463 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
464 return (void **)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
467 static inline bool nvme_pci_use_sgls(struct nvme_dev
*dev
, struct request
*req
)
469 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
470 int nseg
= blk_rq_nr_phys_segments(req
);
471 unsigned int avg_seg_size
;
476 avg_seg_size
= DIV_ROUND_UP(blk_rq_payload_bytes(req
), nseg
);
478 if (!(dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))))
480 if (!iod
->nvmeq
->qid
)
482 if (!sgl_threshold
|| avg_seg_size
< sgl_threshold
)
487 static blk_status_t
nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
489 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
490 int nseg
= blk_rq_nr_phys_segments(rq
);
491 unsigned int size
= blk_rq_payload_bytes(rq
);
493 iod
->use_sgl
= nvme_pci_use_sgls(dev
, rq
);
495 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
496 iod
->sg
= mempool_alloc(dev
->iod_mempool
, GFP_ATOMIC
);
498 return BLK_STS_RESOURCE
;
500 iod
->sg
= iod
->inline_sg
;
511 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
513 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
514 const int last_prp
= dev
->ctrl
.page_size
/ sizeof(__le64
) - 1;
515 dma_addr_t dma_addr
= iod
->first_dma
, next_dma_addr
;
519 if (iod
->npages
== 0)
520 dma_pool_free(dev
->prp_small_pool
, nvme_pci_iod_list(req
)[0],
523 for (i
= 0; i
< iod
->npages
; i
++) {
524 void *addr
= nvme_pci_iod_list(req
)[i
];
527 struct nvme_sgl_desc
*sg_list
= addr
;
530 le64_to_cpu((sg_list
[SGES_PER_PAGE
- 1]).addr
);
532 __le64
*prp_list
= addr
;
534 next_dma_addr
= le64_to_cpu(prp_list
[last_prp
]);
537 dma_pool_free(dev
->prp_page_pool
, addr
, dma_addr
);
538 dma_addr
= next_dma_addr
;
541 if (iod
->sg
!= iod
->inline_sg
)
542 mempool_free(iod
->sg
, dev
->iod_mempool
);
545 static void nvme_print_sgl(struct scatterlist
*sgl
, int nents
)
548 struct scatterlist
*sg
;
550 for_each_sg(sgl
, sg
, nents
, i
) {
551 dma_addr_t phys
= sg_phys(sg
);
552 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
553 "dma_address:%pad dma_length:%d\n",
554 i
, &phys
, sg
->offset
, sg
->length
, &sg_dma_address(sg
),
559 static blk_status_t
nvme_pci_setup_prps(struct nvme_dev
*dev
,
560 struct request
*req
, struct nvme_rw_command
*cmnd
)
562 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
563 struct dma_pool
*pool
;
564 int length
= blk_rq_payload_bytes(req
);
565 struct scatterlist
*sg
= iod
->sg
;
566 int dma_len
= sg_dma_len(sg
);
567 u64 dma_addr
= sg_dma_address(sg
);
568 u32 page_size
= dev
->ctrl
.page_size
;
569 int offset
= dma_addr
& (page_size
- 1);
571 void **list
= nvme_pci_iod_list(req
);
575 length
-= (page_size
- offset
);
581 dma_len
-= (page_size
- offset
);
583 dma_addr
+= (page_size
- offset
);
586 dma_addr
= sg_dma_address(sg
);
587 dma_len
= sg_dma_len(sg
);
590 if (length
<= page_size
) {
591 iod
->first_dma
= dma_addr
;
595 nprps
= DIV_ROUND_UP(length
, page_size
);
596 if (nprps
<= (256 / 8)) {
597 pool
= dev
->prp_small_pool
;
600 pool
= dev
->prp_page_pool
;
604 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
606 iod
->first_dma
= dma_addr
;
608 return BLK_STS_RESOURCE
;
611 iod
->first_dma
= prp_dma
;
614 if (i
== page_size
>> 3) {
615 __le64
*old_prp_list
= prp_list
;
616 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
618 return BLK_STS_RESOURCE
;
619 list
[iod
->npages
++] = prp_list
;
620 prp_list
[0] = old_prp_list
[i
- 1];
621 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
624 prp_list
[i
++] = cpu_to_le64(dma_addr
);
625 dma_len
-= page_size
;
626 dma_addr
+= page_size
;
632 if (unlikely(dma_len
< 0))
635 dma_addr
= sg_dma_address(sg
);
636 dma_len
= sg_dma_len(sg
);
640 cmnd
->dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
641 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
646 WARN(DO_ONCE(nvme_print_sgl
, iod
->sg
, iod
->nents
),
647 "Invalid SGL for payload:%d nents:%d\n",
648 blk_rq_payload_bytes(req
), iod
->nents
);
649 return BLK_STS_IOERR
;
652 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc
*sge
,
653 struct scatterlist
*sg
)
655 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
656 sge
->length
= cpu_to_le32(sg_dma_len(sg
));
657 sge
->type
= NVME_SGL_FMT_DATA_DESC
<< 4;
660 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc
*sge
,
661 dma_addr_t dma_addr
, int entries
)
663 sge
->addr
= cpu_to_le64(dma_addr
);
664 if (entries
< SGES_PER_PAGE
) {
665 sge
->length
= cpu_to_le32(entries
* sizeof(*sge
));
666 sge
->type
= NVME_SGL_FMT_LAST_SEG_DESC
<< 4;
668 sge
->length
= cpu_to_le32(PAGE_SIZE
);
669 sge
->type
= NVME_SGL_FMT_SEG_DESC
<< 4;
673 static blk_status_t
nvme_pci_setup_sgls(struct nvme_dev
*dev
,
674 struct request
*req
, struct nvme_rw_command
*cmd
, int entries
)
676 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
677 struct dma_pool
*pool
;
678 struct nvme_sgl_desc
*sg_list
;
679 struct scatterlist
*sg
= iod
->sg
;
683 /* setting the transfer type as SGL */
684 cmd
->flags
= NVME_CMD_SGL_METABUF
;
687 nvme_pci_sgl_set_data(&cmd
->dptr
.sgl
, sg
);
691 if (entries
<= (256 / sizeof(struct nvme_sgl_desc
))) {
692 pool
= dev
->prp_small_pool
;
695 pool
= dev
->prp_page_pool
;
699 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
702 return BLK_STS_RESOURCE
;
705 nvme_pci_iod_list(req
)[0] = sg_list
;
706 iod
->first_dma
= sgl_dma
;
708 nvme_pci_sgl_set_seg(&cmd
->dptr
.sgl
, sgl_dma
, entries
);
711 if (i
== SGES_PER_PAGE
) {
712 struct nvme_sgl_desc
*old_sg_desc
= sg_list
;
713 struct nvme_sgl_desc
*link
= &old_sg_desc
[i
- 1];
715 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
717 return BLK_STS_RESOURCE
;
720 nvme_pci_iod_list(req
)[iod
->npages
++] = sg_list
;
721 sg_list
[i
++] = *link
;
722 nvme_pci_sgl_set_seg(link
, sgl_dma
, entries
);
725 nvme_pci_sgl_set_data(&sg_list
[i
++], sg
);
727 } while (--entries
> 0);
732 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
733 struct nvme_command
*cmnd
)
735 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
736 struct request_queue
*q
= req
->q
;
737 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
738 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
739 blk_status_t ret
= BLK_STS_IOERR
;
742 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
743 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
747 ret
= BLK_STS_RESOURCE
;
749 if (is_pci_p2pdma_page(sg_page(iod
->sg
)))
750 nr_mapped
= pci_p2pdma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
,
753 nr_mapped
= dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
,
754 dma_dir
, DMA_ATTR_NO_WARN
);
759 ret
= nvme_pci_setup_sgls(dev
, req
, &cmnd
->rw
, nr_mapped
);
761 ret
= nvme_pci_setup_prps(dev
, req
, &cmnd
->rw
);
763 if (ret
!= BLK_STS_OK
)
767 if (blk_integrity_rq(req
)) {
768 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
771 sg_init_table(&iod
->meta_sg
, 1);
772 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
775 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
778 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
784 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
789 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
791 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
792 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
793 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
796 /* P2PDMA requests do not need to be unmapped */
797 if (!is_pci_p2pdma_page(sg_page(iod
->sg
)))
798 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
800 if (blk_integrity_rq(req
))
801 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
804 nvme_cleanup_cmd(req
);
805 nvme_free_iod(dev
, req
);
809 * NOTE: ns is NULL when called on the admin queue.
811 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
812 const struct blk_mq_queue_data
*bd
)
814 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
815 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
816 struct nvme_dev
*dev
= nvmeq
->dev
;
817 struct request
*req
= bd
->rq
;
818 struct nvme_command cmnd
;
822 * We should not need to do this, but we're still using this to
823 * ensure we can drain requests on a dying queue.
825 if (unlikely(nvmeq
->cq_vector
< 0))
826 return BLK_STS_IOERR
;
828 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
832 ret
= nvme_init_iod(req
, dev
);
836 if (blk_rq_nr_phys_segments(req
)) {
837 ret
= nvme_map_data(dev
, req
, &cmnd
);
839 goto out_cleanup_iod
;
842 blk_mq_start_request(req
);
843 nvme_submit_cmd(nvmeq
, &cmnd
);
846 nvme_free_iod(dev
, req
);
848 nvme_cleanup_cmd(req
);
852 static void nvme_pci_complete_rq(struct request
*req
)
854 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
856 nvme_unmap_data(iod
->nvmeq
->dev
, req
);
857 nvme_complete_rq(req
);
860 /* We read the CQE phase first to check if the rest of the entry is valid */
861 static inline bool nvme_cqe_pending(struct nvme_queue
*nvmeq
)
863 return (le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
867 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
869 u16 head
= nvmeq
->cq_head
;
871 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
873 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
876 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
, u16 idx
)
878 volatile struct nvme_completion
*cqe
= &nvmeq
->cqes
[idx
];
881 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
882 dev_warn(nvmeq
->dev
->ctrl
.device
,
883 "invalid id %d completed on queue %d\n",
884 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
889 * AEN requests are special as they don't time out and can
890 * survive any kind of queue freeze and often don't respond to
891 * aborts. We don't even bother to allocate a struct request
892 * for them but rather special case them here.
894 if (unlikely(nvmeq
->qid
== 0 &&
895 cqe
->command_id
>= NVME_AQ_BLK_MQ_DEPTH
)) {
896 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
897 cqe
->status
, &cqe
->result
);
901 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
->command_id
);
902 nvme_end_request(req
, cqe
->status
, cqe
->result
);
905 static void nvme_complete_cqes(struct nvme_queue
*nvmeq
, u16 start
, u16 end
)
907 while (start
!= end
) {
908 nvme_handle_cqe(nvmeq
, start
);
909 if (++start
== nvmeq
->q_depth
)
914 static inline void nvme_update_cq_head(struct nvme_queue
*nvmeq
)
916 if (nvmeq
->cq_head
== nvmeq
->q_depth
- 1) {
918 nvmeq
->cq_phase
= !nvmeq
->cq_phase
;
924 static inline bool nvme_process_cq(struct nvme_queue
*nvmeq
, u16
*start
,
929 *start
= nvmeq
->cq_head
;
930 while (!found
&& nvme_cqe_pending(nvmeq
)) {
931 if (nvmeq
->cqes
[nvmeq
->cq_head
].command_id
== tag
)
933 nvme_update_cq_head(nvmeq
);
935 *end
= nvmeq
->cq_head
;
938 nvme_ring_cq_doorbell(nvmeq
);
942 static irqreturn_t
nvme_irq(int irq
, void *data
)
944 struct nvme_queue
*nvmeq
= data
;
945 irqreturn_t ret
= IRQ_NONE
;
948 spin_lock(&nvmeq
->cq_lock
);
949 if (nvmeq
->cq_head
!= nvmeq
->last_cq_head
)
951 nvme_process_cq(nvmeq
, &start
, &end
, -1);
952 nvmeq
->last_cq_head
= nvmeq
->cq_head
;
953 spin_unlock(&nvmeq
->cq_lock
);
956 nvme_complete_cqes(nvmeq
, start
, end
);
963 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
965 struct nvme_queue
*nvmeq
= data
;
966 if (nvme_cqe_pending(nvmeq
))
967 return IRQ_WAKE_THREAD
;
971 static int __nvme_poll(struct nvme_queue
*nvmeq
, unsigned int tag
)
976 if (!nvme_cqe_pending(nvmeq
))
979 spin_lock_irq(&nvmeq
->cq_lock
);
980 found
= nvme_process_cq(nvmeq
, &start
, &end
, tag
);
981 spin_unlock_irq(&nvmeq
->cq_lock
);
983 nvme_complete_cqes(nvmeq
, start
, end
);
987 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
989 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
991 return __nvme_poll(nvmeq
, tag
);
994 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
)
996 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
997 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
998 struct nvme_command c
;
1000 memset(&c
, 0, sizeof(c
));
1001 c
.common
.opcode
= nvme_admin_async_event
;
1002 c
.common
.command_id
= NVME_AQ_BLK_MQ_DEPTH
;
1003 nvme_submit_cmd(nvmeq
, &c
);
1006 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
1008 struct nvme_command c
;
1010 memset(&c
, 0, sizeof(c
));
1011 c
.delete_queue
.opcode
= opcode
;
1012 c
.delete_queue
.qid
= cpu_to_le16(id
);
1014 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1017 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
1018 struct nvme_queue
*nvmeq
, s16 vector
)
1020 struct nvme_command c
;
1021 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
1024 * Note: we (ab)use the fact that the prp fields survive if no data
1025 * is attached to the request.
1027 memset(&c
, 0, sizeof(c
));
1028 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1029 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1030 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1031 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1032 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1033 c
.create_cq
.irq_vector
= cpu_to_le16(vector
);
1035 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1038 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1039 struct nvme_queue
*nvmeq
)
1041 struct nvme_ctrl
*ctrl
= &dev
->ctrl
;
1042 struct nvme_command c
;
1043 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1046 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1047 * set. Since URGENT priority is zeroes, it makes all queues
1050 if (ctrl
->quirks
& NVME_QUIRK_MEDIUM_PRIO_SQ
)
1051 flags
|= NVME_SQ_PRIO_MEDIUM
;
1054 * Note: we (ab)use the fact that the prp fields survive if no data
1055 * is attached to the request.
1057 memset(&c
, 0, sizeof(c
));
1058 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1059 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1060 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1061 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1062 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1063 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1065 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1068 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1070 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1073 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1075 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1078 static void abort_endio(struct request
*req
, blk_status_t error
)
1080 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1081 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1083 dev_warn(nvmeq
->dev
->ctrl
.device
,
1084 "Abort status: 0x%x", nvme_req(req
)->status
);
1085 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
1086 blk_mq_free_request(req
);
1089 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1092 /* If true, indicates loss of adapter communication, possibly by a
1093 * NVMe Subsystem reset.
1095 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1097 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1098 switch (dev
->ctrl
.state
) {
1099 case NVME_CTRL_RESETTING
:
1100 case NVME_CTRL_CONNECTING
:
1106 /* We shouldn't reset unless the controller is on fatal error state
1107 * _or_ if we lost the communication with it.
1109 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1115 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1117 /* Read a config register to help see what died. */
1121 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1123 if (result
== PCIBIOS_SUCCESSFUL
)
1124 dev_warn(dev
->ctrl
.device
,
1125 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1128 dev_warn(dev
->ctrl
.device
,
1129 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1133 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1135 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1136 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1137 struct nvme_dev
*dev
= nvmeq
->dev
;
1138 struct request
*abort_req
;
1139 struct nvme_command cmd
;
1140 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1142 /* If PCI error recovery process is happening, we cannot reset or
1143 * the recovery mechanism will surely fail.
1146 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1147 return BLK_EH_RESET_TIMER
;
1150 * Reset immediately if the controller is failed
1152 if (nvme_should_reset(dev
, csts
)) {
1153 nvme_warn_reset(dev
, csts
);
1154 nvme_dev_disable(dev
, false);
1155 nvme_reset_ctrl(&dev
->ctrl
);
1160 * Did we miss an interrupt?
1162 if (__nvme_poll(nvmeq
, req
->tag
)) {
1163 dev_warn(dev
->ctrl
.device
,
1164 "I/O %d QID %d timeout, completion polled\n",
1165 req
->tag
, nvmeq
->qid
);
1170 * Shutdown immediately if controller times out while starting. The
1171 * reset work will see the pci device disabled when it gets the forced
1172 * cancellation error. All outstanding requests are completed on
1173 * shutdown, so we return BLK_EH_DONE.
1175 switch (dev
->ctrl
.state
) {
1176 case NVME_CTRL_CONNECTING
:
1177 case NVME_CTRL_RESETTING
:
1178 dev_warn_ratelimited(dev
->ctrl
.device
,
1179 "I/O %d QID %d timeout, disable controller\n",
1180 req
->tag
, nvmeq
->qid
);
1181 nvme_dev_disable(dev
, false);
1182 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1189 * Shutdown the controller immediately and schedule a reset if the
1190 * command was already aborted once before and still hasn't been
1191 * returned to the driver, or if this is the admin queue.
1193 if (!nvmeq
->qid
|| iod
->aborted
) {
1194 dev_warn(dev
->ctrl
.device
,
1195 "I/O %d QID %d timeout, reset controller\n",
1196 req
->tag
, nvmeq
->qid
);
1197 nvme_dev_disable(dev
, false);
1198 nvme_reset_ctrl(&dev
->ctrl
);
1200 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1204 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1205 atomic_inc(&dev
->ctrl
.abort_limit
);
1206 return BLK_EH_RESET_TIMER
;
1210 memset(&cmd
, 0, sizeof(cmd
));
1211 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1212 cmd
.abort
.cid
= req
->tag
;
1213 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1215 dev_warn(nvmeq
->dev
->ctrl
.device
,
1216 "I/O %d QID %d timeout, aborting\n",
1217 req
->tag
, nvmeq
->qid
);
1219 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1220 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1221 if (IS_ERR(abort_req
)) {
1222 atomic_inc(&dev
->ctrl
.abort_limit
);
1223 return BLK_EH_RESET_TIMER
;
1226 abort_req
->timeout
= ADMIN_TIMEOUT
;
1227 abort_req
->end_io_data
= NULL
;
1228 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1231 * The aborted req will be completed on receiving the abort req.
1232 * We enable the timer again. If hit twice, it'll cause a device reset,
1233 * as the device then is in a faulty state.
1235 return BLK_EH_RESET_TIMER
;
1238 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1240 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1241 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1243 if (nvmeq
->sq_cmds
) {
1244 if (nvmeq
->sq_cmds_is_io
)
1245 pci_free_p2pmem(to_pci_dev(nvmeq
->q_dmadev
),
1247 SQ_SIZE(nvmeq
->q_depth
));
1249 dma_free_coherent(nvmeq
->q_dmadev
,
1250 SQ_SIZE(nvmeq
->q_depth
),
1252 nvmeq
->sq_dma_addr
);
1256 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1260 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1261 dev
->ctrl
.queue_count
--;
1262 nvme_free_queue(&dev
->queues
[i
]);
1267 * nvme_suspend_queue - put queue into suspended state
1268 * @nvmeq: queue to suspend
1270 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1274 spin_lock_irq(&nvmeq
->cq_lock
);
1275 if (nvmeq
->cq_vector
== -1) {
1276 spin_unlock_irq(&nvmeq
->cq_lock
);
1279 vector
= nvmeq
->cq_vector
;
1280 nvmeq
->dev
->online_queues
--;
1281 nvmeq
->cq_vector
= -1;
1282 spin_unlock_irq(&nvmeq
->cq_lock
);
1285 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1286 * having to grab the lock.
1290 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1291 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1293 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), vector
, nvmeq
);
1298 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1300 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
1304 nvme_shutdown_ctrl(&dev
->ctrl
);
1306 nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1308 spin_lock_irq(&nvmeq
->cq_lock
);
1309 nvme_process_cq(nvmeq
, &start
, &end
, -1);
1310 spin_unlock_irq(&nvmeq
->cq_lock
);
1312 nvme_complete_cqes(nvmeq
, start
, end
);
1315 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1318 int q_depth
= dev
->q_depth
;
1319 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1320 dev
->ctrl
.page_size
);
1322 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1323 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1324 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1325 q_depth
= div_u64(mem_per_q
, entry_size
);
1328 * Ensure the reduced q_depth is above some threshold where it
1329 * would be better to map queues in system memory with the
1339 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1342 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1344 if (qid
&& dev
->cmb_use_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
)) {
1345 nvmeq
->sq_cmds
= pci_alloc_p2pmem(pdev
, SQ_SIZE(depth
));
1346 nvmeq
->sq_dma_addr
= pci_p2pmem_virt_to_bus(pdev
,
1348 nvmeq
->sq_cmds_is_io
= true;
1351 if (!nvmeq
->sq_cmds
) {
1352 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1353 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1354 nvmeq
->sq_cmds_is_io
= false;
1357 if (!nvmeq
->sq_cmds
)
1362 static int nvme_alloc_queue(struct nvme_dev
*dev
, int qid
, int depth
)
1364 struct nvme_queue
*nvmeq
= &dev
->queues
[qid
];
1366 if (dev
->ctrl
.queue_count
> qid
)
1369 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1370 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1374 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1377 nvmeq
->q_dmadev
= dev
->dev
;
1379 spin_lock_init(&nvmeq
->sq_lock
);
1380 spin_lock_init(&nvmeq
->cq_lock
);
1382 nvmeq
->cq_phase
= 1;
1383 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1384 nvmeq
->q_depth
= depth
;
1386 nvmeq
->cq_vector
= -1;
1387 dev
->ctrl
.queue_count
++;
1392 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1393 nvmeq
->cq_dma_addr
);
1398 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1400 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1401 int nr
= nvmeq
->dev
->ctrl
.instance
;
1403 if (use_threaded_interrupts
) {
1404 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1405 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1407 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1408 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1412 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1414 struct nvme_dev
*dev
= nvmeq
->dev
;
1416 spin_lock_irq(&nvmeq
->cq_lock
);
1419 nvmeq
->cq_phase
= 1;
1420 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1421 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1422 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1423 dev
->online_queues
++;
1424 spin_unlock_irq(&nvmeq
->cq_lock
);
1427 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1429 struct nvme_dev
*dev
= nvmeq
->dev
;
1434 * A queue's vector matches the queue identifier unless the controller
1435 * has only one vector available.
1437 vector
= dev
->num_vecs
== 1 ? 0 : qid
;
1438 result
= adapter_alloc_cq(dev
, qid
, nvmeq
, vector
);
1442 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1449 * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
1450 * invoke free_irq for it and cause a 'Trying to free already-free IRQ
1451 * xxx' warning if the create CQ/SQ command times out.
1453 nvmeq
->cq_vector
= vector
;
1454 nvme_init_queue(nvmeq
, qid
);
1455 result
= queue_request_irq(nvmeq
);
1462 nvmeq
->cq_vector
= -1;
1463 dev
->online_queues
--;
1464 adapter_delete_sq(dev
, qid
);
1466 adapter_delete_cq(dev
, qid
);
1470 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1471 .queue_rq
= nvme_queue_rq
,
1472 .complete
= nvme_pci_complete_rq
,
1473 .init_hctx
= nvme_admin_init_hctx
,
1474 .exit_hctx
= nvme_admin_exit_hctx
,
1475 .init_request
= nvme_init_request
,
1476 .timeout
= nvme_timeout
,
1479 static const struct blk_mq_ops nvme_mq_ops
= {
1480 .queue_rq
= nvme_queue_rq
,
1481 .complete
= nvme_pci_complete_rq
,
1482 .init_hctx
= nvme_init_hctx
,
1483 .init_request
= nvme_init_request
,
1484 .map_queues
= nvme_pci_map_queues
,
1485 .timeout
= nvme_timeout
,
1489 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1491 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1493 * If the controller was reset during removal, it's possible
1494 * user requests may be waiting on a stopped queue. Start the
1495 * queue to flush these to completion.
1497 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1498 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1499 blk_mq_free_tag_set(&dev
->admin_tagset
);
1503 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1505 if (!dev
->ctrl
.admin_q
) {
1506 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1507 dev
->admin_tagset
.nr_hw_queues
= 1;
1509 dev
->admin_tagset
.queue_depth
= NVME_AQ_MQ_TAG_DEPTH
;
1510 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1511 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1512 dev
->admin_tagset
.cmd_size
= nvme_pci_cmd_size(dev
, false);
1513 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1514 dev
->admin_tagset
.driver_data
= dev
;
1516 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1518 dev
->ctrl
.admin_tagset
= &dev
->admin_tagset
;
1520 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1521 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1522 blk_mq_free_tag_set(&dev
->admin_tagset
);
1525 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1526 nvme_dev_remove_admin(dev
);
1527 dev
->ctrl
.admin_q
= NULL
;
1531 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1536 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1538 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1541 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1543 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1545 if (size
<= dev
->bar_mapped_size
)
1547 if (size
> pci_resource_len(pdev
, 0))
1551 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1553 dev
->bar_mapped_size
= 0;
1556 dev
->bar_mapped_size
= size
;
1557 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1562 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1566 struct nvme_queue
*nvmeq
;
1568 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1572 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1573 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1575 if (dev
->subsystem
&&
1576 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1577 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1579 result
= nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1583 result
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1587 nvmeq
= &dev
->queues
[0];
1588 aqa
= nvmeq
->q_depth
- 1;
1591 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1592 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1593 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1595 result
= nvme_enable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1599 nvmeq
->cq_vector
= 0;
1600 nvme_init_queue(nvmeq
, 0);
1601 result
= queue_request_irq(nvmeq
);
1603 nvmeq
->cq_vector
= -1;
1610 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1615 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1616 if (nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1622 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1623 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1624 ret
= nvme_create_queue(&dev
->queues
[i
], i
);
1630 * Ignore failing Create SQ/CQ commands, we can continue with less
1631 * than the desired amount of queues, and even a controller without
1632 * I/O queues can still be used to issue admin commands. This might
1633 * be useful to upgrade a buggy firmware for example.
1635 return ret
>= 0 ? 0 : ret
;
1638 static ssize_t
nvme_cmb_show(struct device
*dev
,
1639 struct device_attribute
*attr
,
1642 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1644 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1645 ndev
->cmbloc
, ndev
->cmbsz
);
1647 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1649 static u64
nvme_cmb_size_unit(struct nvme_dev
*dev
)
1651 u8 szu
= (dev
->cmbsz
>> NVME_CMBSZ_SZU_SHIFT
) & NVME_CMBSZ_SZU_MASK
;
1653 return 1ULL << (12 + 4 * szu
);
1656 static u32
nvme_cmb_size(struct nvme_dev
*dev
)
1658 return (dev
->cmbsz
>> NVME_CMBSZ_SZ_SHIFT
) & NVME_CMBSZ_SZ_MASK
;
1661 static void nvme_map_cmb(struct nvme_dev
*dev
)
1664 resource_size_t bar_size
;
1665 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1671 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1674 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1676 size
= nvme_cmb_size_unit(dev
) * nvme_cmb_size(dev
);
1677 offset
= nvme_cmb_size_unit(dev
) * NVME_CMB_OFST(dev
->cmbloc
);
1678 bar
= NVME_CMB_BIR(dev
->cmbloc
);
1679 bar_size
= pci_resource_len(pdev
, bar
);
1681 if (offset
> bar_size
)
1685 * Controllers may support a CMB size larger than their BAR,
1686 * for example, due to being behind a bridge. Reduce the CMB to
1687 * the reported size of the BAR
1689 if (size
> bar_size
- offset
)
1690 size
= bar_size
- offset
;
1692 if (pci_p2pdma_add_resource(pdev
, bar
, size
, offset
)) {
1693 dev_warn(dev
->ctrl
.device
,
1694 "failed to register the CMB\n");
1698 dev
->cmb_size
= size
;
1699 dev
->cmb_use_sqes
= use_cmb_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
);
1701 if ((dev
->cmbsz
& (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
)) ==
1702 (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
))
1703 pci_p2pmem_publish(pdev
, true);
1705 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1706 &dev_attr_cmb
.attr
, NULL
))
1707 dev_warn(dev
->ctrl
.device
,
1708 "failed to add sysfs attribute for CMB\n");
1711 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1713 if (dev
->cmb_size
) {
1714 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1715 &dev_attr_cmb
.attr
, NULL
);
1720 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1722 u64 dma_addr
= dev
->host_mem_descs_dma
;
1723 struct nvme_command c
;
1726 memset(&c
, 0, sizeof(c
));
1727 c
.features
.opcode
= nvme_admin_set_features
;
1728 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1729 c
.features
.dword11
= cpu_to_le32(bits
);
1730 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1731 ilog2(dev
->ctrl
.page_size
));
1732 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1733 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1734 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1736 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1738 dev_warn(dev
->ctrl
.device
,
1739 "failed to set host mem (err %d, flags %#x).\n",
1745 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1749 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1750 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1751 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1753 dma_free_attrs(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1754 le64_to_cpu(desc
->addr
),
1755 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1758 kfree(dev
->host_mem_desc_bufs
);
1759 dev
->host_mem_desc_bufs
= NULL
;
1760 dma_free_coherent(dev
->dev
,
1761 dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
),
1762 dev
->host_mem_descs
, dev
->host_mem_descs_dma
);
1763 dev
->host_mem_descs
= NULL
;
1764 dev
->nr_host_mem_descs
= 0;
1767 static int __nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 preferred
,
1770 struct nvme_host_mem_buf_desc
*descs
;
1771 u32 max_entries
, len
;
1772 dma_addr_t descs_dma
;
1777 tmp
= (preferred
+ chunk_size
- 1);
1778 do_div(tmp
, chunk_size
);
1781 if (dev
->ctrl
.hmmaxd
&& dev
->ctrl
.hmmaxd
< max_entries
)
1782 max_entries
= dev
->ctrl
.hmmaxd
;
1784 descs
= dma_zalloc_coherent(dev
->dev
, max_entries
* sizeof(*descs
),
1785 &descs_dma
, GFP_KERNEL
);
1789 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1791 goto out_free_descs
;
1793 for (size
= 0; size
< preferred
&& i
< max_entries
; size
+= len
) {
1794 dma_addr_t dma_addr
;
1796 len
= min_t(u64
, chunk_size
, preferred
- size
);
1797 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1798 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1802 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1803 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1810 dev
->nr_host_mem_descs
= i
;
1811 dev
->host_mem_size
= size
;
1812 dev
->host_mem_descs
= descs
;
1813 dev
->host_mem_descs_dma
= descs_dma
;
1814 dev
->host_mem_desc_bufs
= bufs
;
1819 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1821 dma_free_attrs(dev
->dev
, size
, bufs
[i
],
1822 le64_to_cpu(descs
[i
].addr
),
1823 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1828 dma_free_coherent(dev
->dev
, max_entries
* sizeof(*descs
), descs
,
1831 dev
->host_mem_descs
= NULL
;
1835 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1839 /* start big and work our way down */
1840 for (chunk_size
= min_t(u64
, preferred
, PAGE_SIZE
* MAX_ORDER_NR_PAGES
);
1841 chunk_size
>= max_t(u32
, dev
->ctrl
.hmminds
* 4096, PAGE_SIZE
* 2);
1843 if (!__nvme_alloc_host_mem(dev
, preferred
, chunk_size
)) {
1844 if (!min
|| dev
->host_mem_size
>= min
)
1846 nvme_free_host_mem(dev
);
1853 static int nvme_setup_host_mem(struct nvme_dev
*dev
)
1855 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1856 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1857 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1858 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1861 preferred
= min(preferred
, max
);
1863 dev_warn(dev
->ctrl
.device
,
1864 "min host memory (%lld MiB) above limit (%d MiB).\n",
1865 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1866 nvme_free_host_mem(dev
);
1871 * If we already have a buffer allocated check if we can reuse it.
1873 if (dev
->host_mem_descs
) {
1874 if (dev
->host_mem_size
>= min
)
1875 enable_bits
|= NVME_HOST_MEM_RETURN
;
1877 nvme_free_host_mem(dev
);
1880 if (!dev
->host_mem_descs
) {
1881 if (nvme_alloc_host_mem(dev
, min
, preferred
)) {
1882 dev_warn(dev
->ctrl
.device
,
1883 "failed to allocate host memory buffer.\n");
1884 return 0; /* controller must work without HMB */
1887 dev_info(dev
->ctrl
.device
,
1888 "allocated %lld MiB host memory buffer.\n",
1889 dev
->host_mem_size
>> ilog2(SZ_1M
));
1892 ret
= nvme_set_host_mem(dev
, enable_bits
);
1894 nvme_free_host_mem(dev
);
1898 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1900 struct nvme_queue
*adminq
= &dev
->queues
[0];
1901 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1902 int result
, nr_io_queues
;
1905 struct irq_affinity affd
= {
1909 nr_io_queues
= num_possible_cpus();
1910 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1914 if (nr_io_queues
== 0)
1917 if (dev
->cmb_use_sqes
) {
1918 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1919 sizeof(struct nvme_command
));
1921 dev
->q_depth
= result
;
1923 dev
->cmb_use_sqes
= false;
1927 size
= db_bar_size(dev
, nr_io_queues
);
1928 result
= nvme_remap_bar(dev
, size
);
1931 if (!--nr_io_queues
)
1934 adminq
->q_db
= dev
->dbs
;
1936 /* Deregister the admin queue's interrupt */
1937 pci_free_irq(pdev
, 0, adminq
);
1940 * If we enable msix early due to not intx, disable it again before
1941 * setting up the full range we need.
1943 pci_free_irq_vectors(pdev
);
1944 result
= pci_alloc_irq_vectors_affinity(pdev
, 1, nr_io_queues
+ 1,
1945 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
, &affd
);
1948 dev
->num_vecs
= result
;
1949 dev
->max_qid
= max(result
- 1, 1);
1952 * Should investigate if there's a performance win from allocating
1953 * more queues than interrupt vectors; it might allow the submission
1954 * path to scale better, even if the receive path is limited by the
1955 * number of interrupts.
1958 result
= queue_request_irq(adminq
);
1960 adminq
->cq_vector
= -1;
1963 return nvme_create_io_queues(dev
);
1966 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
1968 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1970 blk_mq_free_request(req
);
1971 complete(&nvmeq
->dev
->ioq_wait
);
1974 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
1976 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1980 unsigned long flags
;
1982 spin_lock_irqsave(&nvmeq
->cq_lock
, flags
);
1983 nvme_process_cq(nvmeq
, &start
, &end
, -1);
1984 spin_unlock_irqrestore(&nvmeq
->cq_lock
, flags
);
1986 nvme_complete_cqes(nvmeq
, start
, end
);
1989 nvme_del_queue_end(req
, error
);
1992 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1994 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1995 struct request
*req
;
1996 struct nvme_command cmd
;
1998 memset(&cmd
, 0, sizeof(cmd
));
1999 cmd
.delete_queue
.opcode
= opcode
;
2000 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
2002 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
2004 return PTR_ERR(req
);
2006 req
->timeout
= ADMIN_TIMEOUT
;
2007 req
->end_io_data
= nvmeq
;
2009 blk_execute_rq_nowait(q
, NULL
, req
, false,
2010 opcode
== nvme_admin_delete_cq
?
2011 nvme_del_cq_end
: nvme_del_queue_end
);
2015 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
2017 int pass
, queues
= dev
->online_queues
- 1;
2018 unsigned long timeout
;
2019 u8 opcode
= nvme_admin_delete_sq
;
2021 for (pass
= 0; pass
< 2; pass
++) {
2022 int sent
= 0, i
= queues
;
2024 reinit_completion(&dev
->ioq_wait
);
2026 timeout
= ADMIN_TIMEOUT
;
2027 for (; i
> 0; i
--, sent
++)
2028 if (nvme_delete_queue(&dev
->queues
[i
], opcode
))
2032 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
2038 opcode
= nvme_admin_delete_cq
;
2043 * return error value only when tagset allocation failed
2045 static int nvme_dev_add(struct nvme_dev
*dev
)
2049 if (!dev
->ctrl
.tagset
) {
2050 dev
->tagset
.ops
= &nvme_mq_ops
;
2051 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
2052 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
2053 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
2054 dev
->tagset
.queue_depth
=
2055 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
2056 dev
->tagset
.cmd_size
= nvme_pci_cmd_size(dev
, false);
2057 if ((dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))) && sgl_threshold
) {
2058 dev
->tagset
.cmd_size
= max(dev
->tagset
.cmd_size
,
2059 nvme_pci_cmd_size(dev
, true));
2061 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
2062 dev
->tagset
.driver_data
= dev
;
2064 ret
= blk_mq_alloc_tag_set(&dev
->tagset
);
2066 dev_warn(dev
->ctrl
.device
,
2067 "IO queues tagset allocation failed %d\n", ret
);
2070 dev
->ctrl
.tagset
= &dev
->tagset
;
2072 nvme_dbbuf_set(dev
);
2074 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
2076 /* Free previously allocated queues that are no longer usable */
2077 nvme_free_queues(dev
, dev
->online_queues
);
2083 static int nvme_pci_enable(struct nvme_dev
*dev
)
2085 int result
= -ENOMEM
;
2086 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2088 if (pci_enable_device_mem(pdev
))
2091 pci_set_master(pdev
);
2093 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
2094 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
2097 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
2103 * Some devices and/or platforms don't advertise or work with INTx
2104 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2105 * adjust this later.
2107 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
2111 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
2113 dev
->q_depth
= min_t(int, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
2115 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
2116 dev
->dbs
= dev
->bar
+ 4096;
2119 * Temporary fix for the Apple controller found in the MacBook8,1 and
2120 * some MacBook7,1 to avoid controller resets and data loss.
2122 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
2124 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
2125 "set queue depth=%u to work around controller resets\n",
2127 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
2128 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
2129 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
2131 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
2132 "set queue depth=%u\n", dev
->q_depth
);
2137 pci_enable_pcie_error_reporting(pdev
);
2138 pci_save_state(pdev
);
2142 pci_disable_device(pdev
);
2146 static void nvme_dev_unmap(struct nvme_dev
*dev
)
2150 pci_release_mem_regions(to_pci_dev(dev
->dev
));
2153 static void nvme_pci_disable(struct nvme_dev
*dev
)
2155 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2157 pci_free_irq_vectors(pdev
);
2159 if (pci_is_enabled(pdev
)) {
2160 pci_disable_pcie_error_reporting(pdev
);
2161 pci_disable_device(pdev
);
2165 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
2169 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2171 mutex_lock(&dev
->shutdown_lock
);
2172 if (pci_is_enabled(pdev
)) {
2173 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2175 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
2176 dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
2177 nvme_start_freeze(&dev
->ctrl
);
2178 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
2179 pdev
->error_state
!= pci_channel_io_normal
);
2183 * Give the controller a chance to complete all entered requests if
2184 * doing a safe shutdown.
2188 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
2191 nvme_stop_queues(&dev
->ctrl
);
2193 if (!dead
&& dev
->ctrl
.queue_count
> 0) {
2194 nvme_disable_io_queues(dev
);
2195 nvme_disable_admin_queue(dev
, shutdown
);
2197 for (i
= dev
->ctrl
.queue_count
- 1; i
>= 0; i
--)
2198 nvme_suspend_queue(&dev
->queues
[i
]);
2200 nvme_pci_disable(dev
);
2202 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2203 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2206 * The driver will not be starting up queues again if shutting down so
2207 * must flush all entered requests to their failed completion to avoid
2208 * deadlocking blk-mq hot-cpu notifier.
2211 nvme_start_queues(&dev
->ctrl
);
2212 mutex_unlock(&dev
->shutdown_lock
);
2215 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2217 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2218 PAGE_SIZE
, PAGE_SIZE
, 0);
2219 if (!dev
->prp_page_pool
)
2222 /* Optimisation for I/Os between 4k and 128k */
2223 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2225 if (!dev
->prp_small_pool
) {
2226 dma_pool_destroy(dev
->prp_page_pool
);
2232 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2234 dma_pool_destroy(dev
->prp_page_pool
);
2235 dma_pool_destroy(dev
->prp_small_pool
);
2238 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2240 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2242 nvme_dbbuf_dma_free(dev
);
2243 put_device(dev
->dev
);
2244 if (dev
->tagset
.tags
)
2245 blk_mq_free_tag_set(&dev
->tagset
);
2246 if (dev
->ctrl
.admin_q
)
2247 blk_put_queue(dev
->ctrl
.admin_q
);
2249 free_opal_dev(dev
->ctrl
.opal_dev
);
2250 mempool_destroy(dev
->iod_mempool
);
2254 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
2256 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
2258 nvme_get_ctrl(&dev
->ctrl
);
2259 nvme_dev_disable(dev
, false);
2260 nvme_kill_queues(&dev
->ctrl
);
2261 if (!queue_work(nvme_wq
, &dev
->remove_work
))
2262 nvme_put_ctrl(&dev
->ctrl
);
2265 static void nvme_reset_work(struct work_struct
*work
)
2267 struct nvme_dev
*dev
=
2268 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2269 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2270 int result
= -ENODEV
;
2271 enum nvme_ctrl_state new_state
= NVME_CTRL_LIVE
;
2273 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
))
2277 * If we're called to reset a live controller first shut it down before
2280 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2281 nvme_dev_disable(dev
, false);
2283 mutex_lock(&dev
->shutdown_lock
);
2284 result
= nvme_pci_enable(dev
);
2288 result
= nvme_pci_configure_admin_queue(dev
);
2292 result
= nvme_alloc_admin_tags(dev
);
2297 * Limit the max command size to prevent iod->sg allocations going
2298 * over a single page.
2300 dev
->ctrl
.max_hw_sectors
= NVME_MAX_KB_SZ
<< 1;
2301 dev
->ctrl
.max_segments
= NVME_MAX_SEGS
;
2302 mutex_unlock(&dev
->shutdown_lock
);
2305 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2306 * initializing procedure here.
2308 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_CONNECTING
)) {
2309 dev_warn(dev
->ctrl
.device
,
2310 "failed to mark controller CONNECTING\n");
2314 result
= nvme_init_identify(&dev
->ctrl
);
2318 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2319 if (!dev
->ctrl
.opal_dev
)
2320 dev
->ctrl
.opal_dev
=
2321 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2322 else if (was_suspend
)
2323 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2325 free_opal_dev(dev
->ctrl
.opal_dev
);
2326 dev
->ctrl
.opal_dev
= NULL
;
2329 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2330 result
= nvme_dbbuf_dma_alloc(dev
);
2333 "unable to allocate dma for dbbuf\n");
2336 if (dev
->ctrl
.hmpre
) {
2337 result
= nvme_setup_host_mem(dev
);
2342 result
= nvme_setup_io_queues(dev
);
2347 * Keep the controller around but remove all namespaces if we don't have
2348 * any working I/O queue.
2350 if (dev
->online_queues
< 2) {
2351 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2352 nvme_kill_queues(&dev
->ctrl
);
2353 nvme_remove_namespaces(&dev
->ctrl
);
2354 new_state
= NVME_CTRL_ADMIN_ONLY
;
2356 nvme_start_queues(&dev
->ctrl
);
2357 nvme_wait_freeze(&dev
->ctrl
);
2358 /* hit this only when allocate tagset fails */
2359 if (nvme_dev_add(dev
))
2360 new_state
= NVME_CTRL_ADMIN_ONLY
;
2361 nvme_unfreeze(&dev
->ctrl
);
2365 * If only admin queue live, keep it to do further investigation or
2368 if (!nvme_change_ctrl_state(&dev
->ctrl
, new_state
)) {
2369 dev_warn(dev
->ctrl
.device
,
2370 "failed to mark controller state %d\n", new_state
);
2374 nvme_start_ctrl(&dev
->ctrl
);
2378 nvme_remove_dead_ctrl(dev
, result
);
2381 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2383 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2384 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2386 if (pci_get_drvdata(pdev
))
2387 device_release_driver(&pdev
->dev
);
2388 nvme_put_ctrl(&dev
->ctrl
);
2391 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2393 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2397 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2399 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2403 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2405 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2409 static int nvme_pci_get_address(struct nvme_ctrl
*ctrl
, char *buf
, int size
)
2411 struct pci_dev
*pdev
= to_pci_dev(to_nvme_dev(ctrl
)->dev
);
2413 return snprintf(buf
, size
, "%s", dev_name(&pdev
->dev
));
2416 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2418 .module
= THIS_MODULE
,
2419 .flags
= NVME_F_METADATA_SUPPORTED
|
2421 .reg_read32
= nvme_pci_reg_read32
,
2422 .reg_write32
= nvme_pci_reg_write32
,
2423 .reg_read64
= nvme_pci_reg_read64
,
2424 .free_ctrl
= nvme_pci_free_ctrl
,
2425 .submit_async_event
= nvme_pci_submit_async_event
,
2426 .get_address
= nvme_pci_get_address
,
2429 static int nvme_dev_map(struct nvme_dev
*dev
)
2431 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2433 if (pci_request_mem_regions(pdev
, "nvme"))
2436 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2441 pci_release_mem_regions(pdev
);
2445 static unsigned long check_vendor_combination_bug(struct pci_dev
*pdev
)
2447 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2449 * Several Samsung devices seem to drop off the PCIe bus
2450 * randomly when APST is on and uses the deepest sleep state.
2451 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2452 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2453 * 950 PRO 256GB", but it seems to be restricted to two Dell
2456 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2457 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2458 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2459 return NVME_QUIRK_NO_DEEPEST_PS
;
2460 } else if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa804) {
2462 * Samsung SSD 960 EVO drops off the PCIe bus after system
2463 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2464 * within few minutes after bootup on a Coffee Lake board -
2467 if (dmi_match(DMI_BOARD_VENDOR
, "ASUSTeK COMPUTER INC.") &&
2468 (dmi_match(DMI_BOARD_NAME
, "PRIME B350M-A") ||
2469 dmi_match(DMI_BOARD_NAME
, "PRIME Z370-A")))
2470 return NVME_QUIRK_NO_APST
;
2476 static void nvme_async_probe(void *data
, async_cookie_t cookie
)
2478 struct nvme_dev
*dev
= data
;
2480 nvme_reset_ctrl_sync(&dev
->ctrl
);
2481 flush_work(&dev
->ctrl
.scan_work
);
2482 nvme_put_ctrl(&dev
->ctrl
);
2485 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2487 int node
, result
= -ENOMEM
;
2488 struct nvme_dev
*dev
;
2489 unsigned long quirks
= id
->driver_data
;
2492 node
= dev_to_node(&pdev
->dev
);
2493 if (node
== NUMA_NO_NODE
)
2494 set_dev_node(&pdev
->dev
, first_memory_node
);
2496 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2500 dev
->queues
= kcalloc_node(num_possible_cpus() + 1,
2501 sizeof(struct nvme_queue
), GFP_KERNEL
, node
);
2505 dev
->dev
= get_device(&pdev
->dev
);
2506 pci_set_drvdata(pdev
, dev
);
2508 result
= nvme_dev_map(dev
);
2512 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2513 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2514 mutex_init(&dev
->shutdown_lock
);
2515 init_completion(&dev
->ioq_wait
);
2517 result
= nvme_setup_prp_pools(dev
);
2521 quirks
|= check_vendor_combination_bug(pdev
);
2524 * Double check that our mempool alloc size will cover the biggest
2525 * command we support.
2527 alloc_size
= nvme_pci_iod_alloc_size(dev
, NVME_MAX_KB_SZ
,
2528 NVME_MAX_SEGS
, true);
2529 WARN_ON_ONCE(alloc_size
> PAGE_SIZE
);
2531 dev
->iod_mempool
= mempool_create_node(1, mempool_kmalloc
,
2533 (void *) alloc_size
,
2535 if (!dev
->iod_mempool
) {
2540 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2543 goto release_mempool
;
2545 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2547 nvme_get_ctrl(&dev
->ctrl
);
2548 async_schedule(nvme_async_probe
, dev
);
2553 mempool_destroy(dev
->iod_mempool
);
2555 nvme_release_prp_pools(dev
);
2557 nvme_dev_unmap(dev
);
2559 put_device(dev
->dev
);
2566 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2568 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2569 nvme_dev_disable(dev
, false);
2572 static void nvme_reset_done(struct pci_dev
*pdev
)
2574 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2575 nvme_reset_ctrl_sync(&dev
->ctrl
);
2578 static void nvme_shutdown(struct pci_dev
*pdev
)
2580 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2581 nvme_dev_disable(dev
, true);
2585 * The driver's remove may be called on a device in a partially initialized
2586 * state. This function must not have any dependencies on the device state in
2589 static void nvme_remove(struct pci_dev
*pdev
)
2591 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2593 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2594 pci_set_drvdata(pdev
, NULL
);
2596 if (!pci_device_is_present(pdev
)) {
2597 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2598 nvme_dev_disable(dev
, true);
2599 nvme_dev_remove_admin(dev
);
2602 flush_work(&dev
->ctrl
.reset_work
);
2603 nvme_stop_ctrl(&dev
->ctrl
);
2604 nvme_remove_namespaces(&dev
->ctrl
);
2605 nvme_dev_disable(dev
, true);
2606 nvme_release_cmb(dev
);
2607 nvme_free_host_mem(dev
);
2608 nvme_dev_remove_admin(dev
);
2609 nvme_free_queues(dev
, 0);
2610 nvme_uninit_ctrl(&dev
->ctrl
);
2611 nvme_release_prp_pools(dev
);
2612 nvme_dev_unmap(dev
);
2613 nvme_put_ctrl(&dev
->ctrl
);
2616 #ifdef CONFIG_PM_SLEEP
2617 static int nvme_suspend(struct device
*dev
)
2619 struct pci_dev
*pdev
= to_pci_dev(dev
);
2620 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2622 nvme_dev_disable(ndev
, true);
2626 static int nvme_resume(struct device
*dev
)
2628 struct pci_dev
*pdev
= to_pci_dev(dev
);
2629 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2631 nvme_reset_ctrl(&ndev
->ctrl
);
2636 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2638 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2639 pci_channel_state_t state
)
2641 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2644 * A frozen channel requires a reset. When detected, this method will
2645 * shutdown the controller to quiesce. The controller will be restarted
2646 * after the slot reset through driver's slot_reset callback.
2649 case pci_channel_io_normal
:
2650 return PCI_ERS_RESULT_CAN_RECOVER
;
2651 case pci_channel_io_frozen
:
2652 dev_warn(dev
->ctrl
.device
,
2653 "frozen state error detected, reset controller\n");
2654 nvme_dev_disable(dev
, false);
2655 return PCI_ERS_RESULT_NEED_RESET
;
2656 case pci_channel_io_perm_failure
:
2657 dev_warn(dev
->ctrl
.device
,
2658 "failure state error detected, request disconnect\n");
2659 return PCI_ERS_RESULT_DISCONNECT
;
2661 return PCI_ERS_RESULT_NEED_RESET
;
2664 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2666 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2668 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2669 pci_restore_state(pdev
);
2670 nvme_reset_ctrl(&dev
->ctrl
);
2671 return PCI_ERS_RESULT_RECOVERED
;
2674 static void nvme_error_resume(struct pci_dev
*pdev
)
2676 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2678 flush_work(&dev
->ctrl
.reset_work
);
2681 static const struct pci_error_handlers nvme_err_handler
= {
2682 .error_detected
= nvme_error_detected
,
2683 .slot_reset
= nvme_slot_reset
,
2684 .resume
= nvme_error_resume
,
2685 .reset_prepare
= nvme_reset_prepare
,
2686 .reset_done
= nvme_reset_done
,
2689 static const struct pci_device_id nvme_id_table
[] = {
2690 { PCI_VDEVICE(INTEL
, 0x0953),
2691 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2692 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2693 { PCI_VDEVICE(INTEL
, 0x0a53),
2694 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2695 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2696 { PCI_VDEVICE(INTEL
, 0x0a54),
2697 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2698 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2699 { PCI_VDEVICE(INTEL
, 0x0a55),
2700 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2701 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2702 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2703 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
2704 NVME_QUIRK_MEDIUM_PRIO_SQ
},
2705 { PCI_VDEVICE(INTEL
, 0xf1a6), /* Intel 760p/Pro 7600p */
2706 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
2707 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2708 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2709 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2710 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2711 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2712 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2713 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2714 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2715 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2716 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2717 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2718 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2719 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2720 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2721 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2722 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2723 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2724 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2725 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2726 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2727 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2728 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2729 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2732 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2734 static struct pci_driver nvme_driver
= {
2736 .id_table
= nvme_id_table
,
2737 .probe
= nvme_probe
,
2738 .remove
= nvme_remove
,
2739 .shutdown
= nvme_shutdown
,
2741 .pm
= &nvme_dev_pm_ops
,
2743 .sriov_configure
= pci_sriov_configure_simple
,
2744 .err_handler
= &nvme_err_handler
,
2747 static int __init
nvme_init(void)
2749 return pci_register_driver(&nvme_driver
);
2752 static void __exit
nvme_exit(void)
2754 pci_unregister_driver(&nvme_driver
);
2755 flush_workqueue(nvme_wq
);
2759 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2760 MODULE_LICENSE("GPL");
2761 MODULE_VERSION("1.0");
2762 module_init(nvme_init
);
2763 module_exit(nvme_exit
);