Following additions from ver1.20
1. Fixed GT interrupts issue when DC6 is enabled
2. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.20
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
File: i915/skl_dmc_ver1_18.bin
File: i915/skl_dmc_ver1_19.bin
File: i915/skl_dmc_ver1_20.bin
+File: i915/skl_dmc_ver1_21.bin
File: i915/skl_dmc_ver1.bin
-Version: DMC API/ABI ver 1 - release 20 for Skylake
+Version: DMC API/ABI ver 1 - release 21 for Skylake
File: i915/bxt_dmc_ver1_04.bin
File: i915/bxt_dmc_ver1_05.bin
-skl_dmc_ver1_20.bin
\ No newline at end of file
+skl_dmc_ver1_21.bin
\ No newline at end of file