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x86/mm/64: implement arch_sync_kernel_mappings()
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457c8996 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4
LT
2/*
3 * linux/arch/x86_64/mm/init.c
4 *
5 * Copyright (C) 1995 Linus Torvalds
a2531293 6 * Copyright (C) 2000 Pavel Machek <pavel@ucw.cz>
1da177e4
LT
7 * Copyright (C) 2002,2003 Andi Kleen <ak@suse.de>
8 */
9
1da177e4
LT
10#include <linux/signal.h>
11#include <linux/sched.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15#include <linux/types.h>
16#include <linux/ptrace.h>
17#include <linux/mman.h>
18#include <linux/mm.h>
19#include <linux/swap.h>
20#include <linux/smp.h>
21#include <linux/init.h>
11034d55 22#include <linux/initrd.h>
1da177e4 23#include <linux/pagemap.h>
a9ce6bc1 24#include <linux/memblock.h>
1da177e4 25#include <linux/proc_fs.h>
59170891 26#include <linux/pci.h>
6fb14755 27#include <linux/pfn.h>
c9cf5528 28#include <linux/poison.h>
17a941d8 29#include <linux/dma-mapping.h>
a63fdc51 30#include <linux/memory.h>
44df75e6 31#include <linux/memory_hotplug.h>
4b94ffdc 32#include <linux/memremap.h>
ae32b129 33#include <linux/nmi.h>
5a0e3ad6 34#include <linux/gfp.h>
2f96b8c1 35#include <linux/kcore.h>
1da177e4
LT
36
37#include <asm/processor.h>
46eaa670 38#include <asm/bios_ebda.h>
7c0f6ba6 39#include <linux/uaccess.h>
1da177e4
LT
40#include <asm/pgtable.h>
41#include <asm/pgalloc.h>
42#include <asm/dma.h>
43#include <asm/fixmap.h>
66441bd3 44#include <asm/e820/api.h>
1da177e4
LT
45#include <asm/apic.h>
46#include <asm/tlb.h>
47#include <asm/mmu_context.h>
48#include <asm/proto.h>
49#include <asm/smp.h>
2bc0414e 50#include <asm/sections.h>
718fc13b 51#include <asm/kdebug.h>
aaa64e04 52#include <asm/numa.h>
d1163651 53#include <asm/set_memory.h>
4fcb2083 54#include <asm/init.h>
43c75f93 55#include <asm/uv/uv.h>
e5f15b45 56#include <asm/setup.h>
59566b0b 57#include <asm/ftrace.h>
1da177e4 58
5c51bdbe
YL
59#include "mm_internal.h"
60
cf4fb15b 61#include "ident_map.c"
aece2785 62
eccd9064
BS
63#define DEFINE_POPULATE(fname, type1, type2, init) \
64static inline void fname##_init(struct mm_struct *mm, \
65 type1##_t *arg1, type2##_t *arg2, bool init) \
66{ \
67 if (init) \
68 fname##_safe(mm, arg1, arg2); \
69 else \
70 fname(mm, arg1, arg2); \
71}
72
73DEFINE_POPULATE(p4d_populate, p4d, pud, init)
74DEFINE_POPULATE(pgd_populate, pgd, p4d, init)
75DEFINE_POPULATE(pud_populate, pud, pmd, init)
76DEFINE_POPULATE(pmd_populate_kernel, pmd, pte, init)
77
78#define DEFINE_ENTRY(type1, type2, init) \
79static inline void set_##type1##_init(type1##_t *arg1, \
80 type2##_t arg2, bool init) \
81{ \
82 if (init) \
83 set_##type1##_safe(arg1, arg2); \
84 else \
85 set_##type1(arg1, arg2); \
86}
87
88DEFINE_ENTRY(p4d, p4d, init)
89DEFINE_ENTRY(pud, pud, init)
90DEFINE_ENTRY(pmd, pmd, init)
91DEFINE_ENTRY(pte, pte, init)
92
93
1da177e4
LT
94/*
95 * NOTE: pagetable_init alloc all the fixmap pagetables contiguous on the
96 * physical space so we can cache the place of the first one and move
97 * around without checking the pgd every time.
98 */
99
8a57f484 100/* Bits supported by the hardware: */
f955371c 101pteval_t __supported_pte_mask __read_mostly = ~0;
8a57f484
DH
102/* Bits allowed in normal kernel mappings: */
103pteval_t __default_kernel_pte_mask __read_mostly = ~0;
bd220a24 104EXPORT_SYMBOL_GPL(__supported_pte_mask);
8a57f484
DH
105/* Used in PAGE_KERNEL_* macros which are reasonably used out-of-tree: */
106EXPORT_SYMBOL(__default_kernel_pte_mask);
bd220a24 107
bd220a24
YL
108int force_personality32;
109
deed05b7
IM
110/*
111 * noexec32=on|off
112 * Control non executable heap for 32bit processes.
113 * To control the stack too use noexec=off
114 *
115 * on PROT_READ does not imply PROT_EXEC for 32-bit processes (default)
116 * off PROT_READ implies PROT_EXEC
117 */
bd220a24
YL
118static int __init nonx32_setup(char *str)
119{
120 if (!strcmp(str, "on"))
121 force_personality32 &= ~READ_IMPLIES_EXEC;
122 else if (!strcmp(str, "off"))
123 force_personality32 |= READ_IMPLIES_EXEC;
124 return 1;
125}
126__setup("noexec32=", nonx32_setup);
127
91f606a8 128static void sync_global_pgds_l5(unsigned long start, unsigned long end)
141efad7
KS
129{
130 unsigned long addr;
131
132 for (addr = start; addr <= end; addr = ALIGN(addr + 1, PGDIR_SIZE)) {
133 const pgd_t *pgd_ref = pgd_offset_k(addr);
134 struct page *page;
135
136 /* Check for overflow */
137 if (addr < start)
138 break;
139
140 if (pgd_none(*pgd_ref))
141 continue;
142
143 spin_lock(&pgd_lock);
144 list_for_each_entry(page, &pgd_list, lru) {
145 pgd_t *pgd;
146 spinlock_t *pgt_lock;
147
148 pgd = (pgd_t *)page_address(page) + pgd_index(addr);
149 /* the pgt_lock only for Xen */
150 pgt_lock = &pgd_page_get_mm(page)->page_table_lock;
151 spin_lock(pgt_lock);
152
153 if (!pgd_none(*pgd_ref) && !pgd_none(*pgd))
154 BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_ref));
155
156 if (pgd_none(*pgd))
157 set_pgd(pgd, *pgd_ref);
158
159 spin_unlock(pgt_lock);
160 }
161 spin_unlock(&pgd_lock);
162 }
163}
91f606a8
KS
164
165static void sync_global_pgds_l4(unsigned long start, unsigned long end)
6afb5157 166{
fc5f9d5f 167 unsigned long addr;
44235dcd 168
fc5f9d5f
BH
169 for (addr = start; addr <= end; addr = ALIGN(addr + 1, PGDIR_SIZE)) {
170 pgd_t *pgd_ref = pgd_offset_k(addr);
f2a6a705 171 const p4d_t *p4d_ref;
44235dcd
JF
172 struct page *page;
173
f2a6a705
KS
174 /*
175 * With folded p4d, pgd_none() is always false, we need to
176 * handle synchonization on p4d level.
177 */
c65e774f 178 MAYBE_BUILD_BUG_ON(pgd_none(*pgd_ref));
fc5f9d5f 179 p4d_ref = p4d_offset(pgd_ref, addr);
f2a6a705
KS
180
181 if (p4d_none(*p4d_ref))
44235dcd
JF
182 continue;
183
a79e53d8 184 spin_lock(&pgd_lock);
44235dcd 185 list_for_each_entry(page, &pgd_list, lru) {
be354f40 186 pgd_t *pgd;
f2a6a705 187 p4d_t *p4d;
617d34d9
JF
188 spinlock_t *pgt_lock;
189
fc5f9d5f
BH
190 pgd = (pgd_t *)page_address(page) + pgd_index(addr);
191 p4d = p4d_offset(pgd, addr);
a79e53d8 192 /* the pgt_lock only for Xen */
617d34d9
JF
193 pgt_lock = &pgd_page_get_mm(page)->page_table_lock;
194 spin_lock(pgt_lock);
195
f2a6a705
KS
196 if (!p4d_none(*p4d_ref) && !p4d_none(*p4d))
197 BUG_ON(p4d_page_vaddr(*p4d)
198 != p4d_page_vaddr(*p4d_ref));
617d34d9 199
f2a6a705
KS
200 if (p4d_none(*p4d))
201 set_p4d(p4d, *p4d_ref);
9661d5bc 202
617d34d9 203 spin_unlock(pgt_lock);
44235dcd 204 }
a79e53d8 205 spin_unlock(&pgd_lock);
44235dcd 206 }
6afb5157 207}
91f606a8
KS
208
209/*
210 * When memory was added make sure all the processes MM have
211 * suitable PGD entries in the local PGD level page.
212 */
213void sync_global_pgds(unsigned long start, unsigned long end)
214{
ed7588d5 215 if (pgtable_l5_enabled())
91f606a8
KS
216 sync_global_pgds_l5(start, end);
217 else
218 sync_global_pgds_l4(start, end);
219}
6afb5157 220
8e19843c
JR
221void arch_sync_kernel_mappings(unsigned long start, unsigned long end)
222{
223 sync_global_pgds(start, end);
224}
225
8d6ea967
MS
226/*
227 * NOTE: This function is marked __ref because it calls __init function
228 * (alloc_bootmem_pages). It's safe to do it ONLY when after_bootmem == 0.
229 */
230static __ref void *spp_getpage(void)
14a62c34 231{
1da177e4 232 void *ptr;
14a62c34 233
1da177e4 234 if (after_bootmem)
75f296d9 235 ptr = (void *) get_zeroed_page(GFP_ATOMIC);
1da177e4 236 else
15c3c114 237 ptr = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
14a62c34
TG
238
239 if (!ptr || ((unsigned long)ptr & ~PAGE_MASK)) {
240 panic("set_pte_phys: cannot allocate page data %s\n",
241 after_bootmem ? "after bootmem" : "");
242 }
1da177e4 243
10f22dde 244 pr_debug("spp_getpage %p\n", ptr);
14a62c34 245
1da177e4 246 return ptr;
14a62c34 247}
1da177e4 248
f2a6a705 249static p4d_t *fill_p4d(pgd_t *pgd, unsigned long vaddr)
1da177e4 250{
458a3e64 251 if (pgd_none(*pgd)) {
f2a6a705
KS
252 p4d_t *p4d = (p4d_t *)spp_getpage();
253 pgd_populate(&init_mm, pgd, p4d);
254 if (p4d != p4d_offset(pgd, 0))
458a3e64 255 printk(KERN_ERR "PAGETABLE BUG #00! %p <-> %p\n",
f2a6a705
KS
256 p4d, p4d_offset(pgd, 0));
257 }
258 return p4d_offset(pgd, vaddr);
259}
260
261static pud_t *fill_pud(p4d_t *p4d, unsigned long vaddr)
262{
263 if (p4d_none(*p4d)) {
264 pud_t *pud = (pud_t *)spp_getpage();
265 p4d_populate(&init_mm, p4d, pud);
266 if (pud != pud_offset(p4d, 0))
267 printk(KERN_ERR "PAGETABLE BUG #01! %p <-> %p\n",
268 pud, pud_offset(p4d, 0));
458a3e64 269 }
f2a6a705 270 return pud_offset(p4d, vaddr);
458a3e64 271}
1da177e4 272
f254f390 273static pmd_t *fill_pmd(pud_t *pud, unsigned long vaddr)
458a3e64 274{
1da177e4 275 if (pud_none(*pud)) {
458a3e64 276 pmd_t *pmd = (pmd_t *) spp_getpage();
bb23e403 277 pud_populate(&init_mm, pud, pmd);
458a3e64 278 if (pmd != pmd_offset(pud, 0))
f2a6a705 279 printk(KERN_ERR "PAGETABLE BUG #02! %p <-> %p\n",
458a3e64 280 pmd, pmd_offset(pud, 0));
1da177e4 281 }
458a3e64
TH
282 return pmd_offset(pud, vaddr);
283}
284
f254f390 285static pte_t *fill_pte(pmd_t *pmd, unsigned long vaddr)
458a3e64 286{
1da177e4 287 if (pmd_none(*pmd)) {
458a3e64 288 pte_t *pte = (pte_t *) spp_getpage();
bb23e403 289 pmd_populate_kernel(&init_mm, pmd, pte);
458a3e64 290 if (pte != pte_offset_kernel(pmd, 0))
f2a6a705 291 printk(KERN_ERR "PAGETABLE BUG #03!\n");
1da177e4 292 }
458a3e64
TH
293 return pte_offset_kernel(pmd, vaddr);
294}
295
f2a6a705 296static void __set_pte_vaddr(pud_t *pud, unsigned long vaddr, pte_t new_pte)
458a3e64 297{
f2a6a705
KS
298 pmd_t *pmd = fill_pmd(pud, vaddr);
299 pte_t *pte = fill_pte(pmd, vaddr);
1da177e4 300
1da177e4
LT
301 set_pte(pte, new_pte);
302
303 /*
304 * It's enough to flush this one mapping.
305 * (PGE mappings get flushed as well)
306 */
1299ef1d 307 __flush_tlb_one_kernel(vaddr);
1da177e4
LT
308}
309
f2a6a705
KS
310void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte)
311{
312 p4d_t *p4d = p4d_page + p4d_index(vaddr);
313 pud_t *pud = fill_pud(p4d, vaddr);
314
315 __set_pte_vaddr(pud, vaddr, new_pte);
316}
317
318void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte)
319{
320 pud_t *pud = pud_page + pud_index(vaddr);
321
322 __set_pte_vaddr(pud, vaddr, new_pte);
323}
324
458a3e64 325void set_pte_vaddr(unsigned long vaddr, pte_t pteval)
0814e0ba
EH
326{
327 pgd_t *pgd;
f2a6a705 328 p4d_t *p4d_page;
0814e0ba
EH
329
330 pr_debug("set_pte_vaddr %lx to %lx\n", vaddr, native_pte_val(pteval));
331
332 pgd = pgd_offset_k(vaddr);
333 if (pgd_none(*pgd)) {
334 printk(KERN_ERR
335 "PGD FIXMAP MISSING, it should be setup in head.S!\n");
336 return;
337 }
f2a6a705
KS
338
339 p4d_page = p4d_offset(pgd, 0);
340 set_pte_vaddr_p4d(p4d_page, vaddr, pteval);
0814e0ba
EH
341}
342
458a3e64 343pmd_t * __init populate_extra_pmd(unsigned long vaddr)
11124411
TH
344{
345 pgd_t *pgd;
f2a6a705 346 p4d_t *p4d;
11124411
TH
347 pud_t *pud;
348
349 pgd = pgd_offset_k(vaddr);
f2a6a705
KS
350 p4d = fill_p4d(pgd, vaddr);
351 pud = fill_pud(p4d, vaddr);
458a3e64
TH
352 return fill_pmd(pud, vaddr);
353}
354
355pte_t * __init populate_extra_pte(unsigned long vaddr)
356{
357 pmd_t *pmd;
11124411 358
458a3e64
TH
359 pmd = populate_extra_pmd(vaddr);
360 return fill_pte(pmd, vaddr);
11124411
TH
361}
362
3a9e189d
JS
363/*
364 * Create large page table mappings for a range of physical addresses.
365 */
366static void __init __init_extra_mapping(unsigned long phys, unsigned long size,
2df58b6d 367 enum page_cache_mode cache)
3a9e189d
JS
368{
369 pgd_t *pgd;
f2a6a705 370 p4d_t *p4d;
3a9e189d
JS
371 pud_t *pud;
372 pmd_t *pmd;
2df58b6d 373 pgprot_t prot;
3a9e189d 374
2df58b6d
JG
375 pgprot_val(prot) = pgprot_val(PAGE_KERNEL_LARGE) |
376 pgprot_val(pgprot_4k_2_large(cachemode2pgprot(cache)));
3a9e189d
JS
377 BUG_ON((phys & ~PMD_MASK) || (size & ~PMD_MASK));
378 for (; size; phys += PMD_SIZE, size -= PMD_SIZE) {
379 pgd = pgd_offset_k((unsigned long)__va(phys));
380 if (pgd_none(*pgd)) {
f2a6a705
KS
381 p4d = (p4d_t *) spp_getpage();
382 set_pgd(pgd, __pgd(__pa(p4d) | _KERNPG_TABLE |
383 _PAGE_USER));
384 }
385 p4d = p4d_offset(pgd, (unsigned long)__va(phys));
386 if (p4d_none(*p4d)) {
3a9e189d 387 pud = (pud_t *) spp_getpage();
f2a6a705 388 set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE |
3a9e189d
JS
389 _PAGE_USER));
390 }
f2a6a705 391 pud = pud_offset(p4d, (unsigned long)__va(phys));
3a9e189d
JS
392 if (pud_none(*pud)) {
393 pmd = (pmd_t *) spp_getpage();
394 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE |
395 _PAGE_USER));
396 }
397 pmd = pmd_offset(pud, phys);
398 BUG_ON(!pmd_none(*pmd));
399 set_pmd(pmd, __pmd(phys | pgprot_val(prot)));
400 }
401}
402
403void __init init_extra_mapping_wb(unsigned long phys, unsigned long size)
404{
2df58b6d 405 __init_extra_mapping(phys, size, _PAGE_CACHE_MODE_WB);
3a9e189d
JS
406}
407
408void __init init_extra_mapping_uc(unsigned long phys, unsigned long size)
409{
2df58b6d 410 __init_extra_mapping(phys, size, _PAGE_CACHE_MODE_UC);
3a9e189d
JS
411}
412
31eedd82 413/*
88f3aec7
IM
414 * The head.S code sets up the kernel high mapping:
415 *
416 * from __START_KERNEL_map to __START_KERNEL_map + size (== _end-_text)
31eedd82 417 *
1e3b3081 418 * phys_base holds the negative offset to the kernel, which is added
31eedd82
TG
419 * to the compile time generated pmds. This results in invalid pmds up
420 * to the point where we hit the physaddr 0 mapping.
421 *
e5f15b45
YL
422 * We limit the mappings to the region from _text to _brk_end. _brk_end
423 * is rounded up to the 2MB boundary. This catches the invalid pmds as
31eedd82
TG
424 * well, as they are located before _text:
425 */
426void __init cleanup_highmap(void)
427{
428 unsigned long vaddr = __START_KERNEL_map;
10054230 429 unsigned long vaddr_end = __START_KERNEL_map + KERNEL_IMAGE_SIZE;
e5f15b45 430 unsigned long end = roundup((unsigned long)_brk_end, PMD_SIZE) - 1;
31eedd82 431 pmd_t *pmd = level2_kernel_pgt;
31eedd82 432
10054230
YL
433 /*
434 * Native path, max_pfn_mapped is not set yet.
435 * Xen has valid max_pfn_mapped set in
436 * arch/x86/xen/mmu.c:xen_setup_kernel_pagetable().
437 */
438 if (max_pfn_mapped)
439 vaddr_end = __START_KERNEL_map + (max_pfn_mapped << PAGE_SHIFT);
440
e5f15b45 441 for (; vaddr + PMD_SIZE - 1 < vaddr_end; pmd++, vaddr += PMD_SIZE) {
2884f110 442 if (pmd_none(*pmd))
31eedd82
TG
443 continue;
444 if (vaddr < (unsigned long) _text || vaddr > end)
445 set_pmd(pmd, __pmd(0));
446 }
447}
448
59b3d020
TG
449/*
450 * Create PTE level page table mapping for physical addresses.
451 * It returns the last physical address mapped.
452 */
7b16eb89 453static unsigned long __meminit
59b3d020 454phys_pte_init(pte_t *pte_page, unsigned long paddr, unsigned long paddr_end,
eccd9064 455 pgprot_t prot, bool init)
4f9c11dd 456{
59b3d020
TG
457 unsigned long pages = 0, paddr_next;
458 unsigned long paddr_last = paddr_end;
459 pte_t *pte;
4f9c11dd 460 int i;
7b16eb89 461
59b3d020
TG
462 pte = pte_page + pte_index(paddr);
463 i = pte_index(paddr);
4f9c11dd 464
59b3d020
TG
465 for (; i < PTRS_PER_PTE; i++, paddr = paddr_next, pte++) {
466 paddr_next = (paddr & PAGE_MASK) + PAGE_SIZE;
467 if (paddr >= paddr_end) {
eceb3632 468 if (!after_bootmem &&
3bce64f0 469 !e820__mapped_any(paddr & PAGE_MASK, paddr_next,
09821ff1 470 E820_TYPE_RAM) &&
3bce64f0 471 !e820__mapped_any(paddr & PAGE_MASK, paddr_next,
09821ff1 472 E820_TYPE_RESERVED_KERN))
eccd9064 473 set_pte_init(pte, __pte(0), init);
eceb3632 474 continue;
4f9c11dd
JF
475 }
476
b27a43c1
SS
477 /*
478 * We will re-use the existing mapping.
479 * Xen for example has some special requirements, like mapping
480 * pagetable pages as RO. So assume someone who pre-setup
481 * these mappings are more intelligent.
482 */
dcb32d99 483 if (!pte_none(*pte)) {
876ee61a
JB
484 if (!after_bootmem)
485 pages++;
4f9c11dd 486 continue;
3afa3949 487 }
4f9c11dd
JF
488
489 if (0)
59b3d020
TG
490 pr_info(" pte=%p addr=%lx pte=%016lx\n", pte, paddr,
491 pfn_pte(paddr >> PAGE_SHIFT, PAGE_KERNEL).pte);
4f9c11dd 492 pages++;
eccd9064 493 set_pte_init(pte, pfn_pte(paddr >> PAGE_SHIFT, prot), init);
59b3d020 494 paddr_last = (paddr & PAGE_MASK) + PAGE_SIZE;
4f9c11dd 495 }
a2699e47 496
4f9c11dd 497 update_page_count(PG_LEVEL_4K, pages);
7b16eb89 498
59b3d020 499 return paddr_last;
4f9c11dd
JF
500}
501
59b3d020
TG
502/*
503 * Create PMD level page table mapping for physical addresses. The virtual
504 * and physical address have to be aligned at this level.
505 * It returns the last physical address mapped.
506 */
cc615032 507static unsigned long __meminit
59b3d020 508phys_pmd_init(pmd_t *pmd_page, unsigned long paddr, unsigned long paddr_end,
eccd9064 509 unsigned long page_size_mask, pgprot_t prot, bool init)
44df75e6 510{
59b3d020
TG
511 unsigned long pages = 0, paddr_next;
512 unsigned long paddr_last = paddr_end;
ce0c0e50 513
59b3d020 514 int i = pmd_index(paddr);
44df75e6 515
59b3d020
TG
516 for (; i < PTRS_PER_PMD; i++, paddr = paddr_next) {
517 pmd_t *pmd = pmd_page + pmd_index(paddr);
4f9c11dd 518 pte_t *pte;
b27a43c1 519 pgprot_t new_prot = prot;
44df75e6 520
59b3d020
TG
521 paddr_next = (paddr & PMD_MASK) + PMD_SIZE;
522 if (paddr >= paddr_end) {
eceb3632 523 if (!after_bootmem &&
3bce64f0 524 !e820__mapped_any(paddr & PMD_MASK, paddr_next,
09821ff1 525 E820_TYPE_RAM) &&
3bce64f0 526 !e820__mapped_any(paddr & PMD_MASK, paddr_next,
09821ff1 527 E820_TYPE_RESERVED_KERN))
eccd9064 528 set_pmd_init(pmd, __pmd(0), init);
eceb3632 529 continue;
44df75e6 530 }
6ad91658 531
dcb32d99 532 if (!pmd_none(*pmd)) {
8ae3a5a8
JB
533 if (!pmd_large(*pmd)) {
534 spin_lock(&init_mm.page_table_lock);
973dc4f3 535 pte = (pte_t *)pmd_page_vaddr(*pmd);
59b3d020 536 paddr_last = phys_pte_init(pte, paddr,
eccd9064
BS
537 paddr_end, prot,
538 init);
8ae3a5a8 539 spin_unlock(&init_mm.page_table_lock);
a2699e47 540 continue;
8ae3a5a8 541 }
b27a43c1
SS
542 /*
543 * If we are ok with PG_LEVEL_2M mapping, then we will
544 * use the existing mapping,
545 *
546 * Otherwise, we will split the large page mapping but
547 * use the same existing protection bits except for
548 * large page, so that we don't violate Intel's TLB
549 * Application note (317080) which says, while changing
550 * the page sizes, new and old translations should
551 * not differ with respect to page frame and
552 * attributes.
553 */
3afa3949 554 if (page_size_mask & (1 << PG_LEVEL_2M)) {
876ee61a
JB
555 if (!after_bootmem)
556 pages++;
59b3d020 557 paddr_last = paddr_next;
b27a43c1 558 continue;
3afa3949 559 }
b27a43c1 560 new_prot = pte_pgprot(pte_clrhuge(*(pte_t *)pmd));
4f9c11dd
JF
561 }
562
b50efd2a 563 if (page_size_mask & (1<<PG_LEVEL_2M)) {
4f9c11dd 564 pages++;
8ae3a5a8 565 spin_lock(&init_mm.page_table_lock);
eccd9064
BS
566 set_pte_init((pte_t *)pmd,
567 pfn_pte((paddr & PMD_MASK) >> PAGE_SHIFT,
568 __pgprot(pgprot_val(prot) | _PAGE_PSE)),
569 init);
8ae3a5a8 570 spin_unlock(&init_mm.page_table_lock);
59b3d020 571 paddr_last = paddr_next;
6ad91658 572 continue;
4f9c11dd 573 }
6ad91658 574
868bf4d6 575 pte = alloc_low_page();
eccd9064 576 paddr_last = phys_pte_init(pte, paddr, paddr_end, new_prot, init);
4f9c11dd 577
8ae3a5a8 578 spin_lock(&init_mm.page_table_lock);
eccd9064 579 pmd_populate_kernel_init(&init_mm, pmd, pte, init);
8ae3a5a8 580 spin_unlock(&init_mm.page_table_lock);
44df75e6 581 }
ce0c0e50 582 update_page_count(PG_LEVEL_2M, pages);
59b3d020 583 return paddr_last;
44df75e6
MT
584}
585
59b3d020
TG
586/*
587 * Create PUD level page table mapping for physical addresses. The virtual
faa37933
TG
588 * and physical address do not have to be aligned at this level. KASLR can
589 * randomize virtual addresses up to this level.
59b3d020
TG
590 * It returns the last physical address mapped.
591 */
cc615032 592static unsigned long __meminit
59b3d020 593phys_pud_init(pud_t *pud_page, unsigned long paddr, unsigned long paddr_end,
c164fbb4 594 unsigned long page_size_mask, pgprot_t _prot, bool init)
14a62c34 595{
59b3d020
TG
596 unsigned long pages = 0, paddr_next;
597 unsigned long paddr_last = paddr_end;
faa37933
TG
598 unsigned long vaddr = (unsigned long)__va(paddr);
599 int i = pud_index(vaddr);
44df75e6 600
59b3d020 601 for (; i < PTRS_PER_PUD; i++, paddr = paddr_next) {
faa37933 602 pud_t *pud;
1da177e4 603 pmd_t *pmd;
c164fbb4 604 pgprot_t prot = _prot;
1da177e4 605
faa37933
TG
606 vaddr = (unsigned long)__va(paddr);
607 pud = pud_page + pud_index(vaddr);
59b3d020 608 paddr_next = (paddr & PUD_MASK) + PUD_SIZE;
faa37933 609
59b3d020 610 if (paddr >= paddr_end) {
eceb3632 611 if (!after_bootmem &&
3bce64f0 612 !e820__mapped_any(paddr & PUD_MASK, paddr_next,
09821ff1 613 E820_TYPE_RAM) &&
3bce64f0 614 !e820__mapped_any(paddr & PUD_MASK, paddr_next,
09821ff1 615 E820_TYPE_RESERVED_KERN))
eccd9064 616 set_pud_init(pud, __pud(0), init);
1da177e4 617 continue;
14a62c34 618 }
1da177e4 619
dcb32d99 620 if (!pud_none(*pud)) {
a2699e47 621 if (!pud_large(*pud)) {
973dc4f3 622 pmd = pmd_offset(pud, 0);
59b3d020
TG
623 paddr_last = phys_pmd_init(pmd, paddr,
624 paddr_end,
625 page_size_mask,
eccd9064 626 prot, init);
a2699e47
SS
627 continue;
628 }
b27a43c1
SS
629 /*
630 * If we are ok with PG_LEVEL_1G mapping, then we will
631 * use the existing mapping.
632 *
633 * Otherwise, we will split the gbpage mapping but use
634 * the same existing protection bits except for large
635 * page, so that we don't violate Intel's TLB
636 * Application note (317080) which says, while changing
637 * the page sizes, new and old translations should
638 * not differ with respect to page frame and
639 * attributes.
640 */
3afa3949 641 if (page_size_mask & (1 << PG_LEVEL_1G)) {
876ee61a
JB
642 if (!after_bootmem)
643 pages++;
59b3d020 644 paddr_last = paddr_next;
b27a43c1 645 continue;
3afa3949 646 }
b27a43c1 647 prot = pte_pgprot(pte_clrhuge(*(pte_t *)pud));
ef925766
AK
648 }
649
b50efd2a 650 if (page_size_mask & (1<<PG_LEVEL_1G)) {
ce0c0e50 651 pages++;
8ae3a5a8 652 spin_lock(&init_mm.page_table_lock);
c164fbb4
LG
653
654 prot = __pgprot(pgprot_val(prot) | __PAGE_KERNEL_LARGE);
655
eccd9064
BS
656 set_pte_init((pte_t *)pud,
657 pfn_pte((paddr & PUD_MASK) >> PAGE_SHIFT,
c164fbb4 658 prot),
eccd9064 659 init);
8ae3a5a8 660 spin_unlock(&init_mm.page_table_lock);
59b3d020 661 paddr_last = paddr_next;
6ad91658
KM
662 continue;
663 }
664
868bf4d6 665 pmd = alloc_low_page();
59b3d020 666 paddr_last = phys_pmd_init(pmd, paddr, paddr_end,
eccd9064 667 page_size_mask, prot, init);
8ae3a5a8
JB
668
669 spin_lock(&init_mm.page_table_lock);
eccd9064 670 pud_populate_init(&init_mm, pud, pmd, init);
44df75e6 671 spin_unlock(&init_mm.page_table_lock);
1da177e4 672 }
a2699e47 673
ce0c0e50 674 update_page_count(PG_LEVEL_1G, pages);
cc615032 675
59b3d020 676 return paddr_last;
14a62c34 677}
1da177e4 678
7e82ea94
KS
679static unsigned long __meminit
680phys_p4d_init(p4d_t *p4d_page, unsigned long paddr, unsigned long paddr_end,
c164fbb4 681 unsigned long page_size_mask, pgprot_t prot, bool init)
7e82ea94 682{
432c8332
KS
683 unsigned long vaddr, vaddr_end, vaddr_next, paddr_next, paddr_last;
684
685 paddr_last = paddr_end;
686 vaddr = (unsigned long)__va(paddr);
687 vaddr_end = (unsigned long)__va(paddr_end);
7e82ea94 688
ed7588d5 689 if (!pgtable_l5_enabled())
eccd9064 690 return phys_pud_init((pud_t *) p4d_page, paddr, paddr_end,
c164fbb4 691 page_size_mask, prot, init);
7e82ea94 692
432c8332
KS
693 for (; vaddr < vaddr_end; vaddr = vaddr_next) {
694 p4d_t *p4d = p4d_page + p4d_index(vaddr);
7e82ea94
KS
695 pud_t *pud;
696
432c8332
KS
697 vaddr_next = (vaddr & P4D_MASK) + P4D_SIZE;
698 paddr = __pa(vaddr);
7e82ea94
KS
699
700 if (paddr >= paddr_end) {
432c8332 701 paddr_next = __pa(vaddr_next);
7e82ea94
KS
702 if (!after_bootmem &&
703 !e820__mapped_any(paddr & P4D_MASK, paddr_next,
704 E820_TYPE_RAM) &&
705 !e820__mapped_any(paddr & P4D_MASK, paddr_next,
706 E820_TYPE_RESERVED_KERN))
eccd9064 707 set_p4d_init(p4d, __p4d(0), init);
7e82ea94
KS
708 continue;
709 }
710
711 if (!p4d_none(*p4d)) {
712 pud = pud_offset(p4d, 0);
432c8332 713 paddr_last = phys_pud_init(pud, paddr, __pa(vaddr_end),
c164fbb4 714 page_size_mask, prot, init);
7e82ea94
KS
715 continue;
716 }
717
718 pud = alloc_low_page();
432c8332 719 paddr_last = phys_pud_init(pud, paddr, __pa(vaddr_end),
c164fbb4 720 page_size_mask, prot, init);
7e82ea94
KS
721
722 spin_lock(&init_mm.page_table_lock);
eccd9064 723 p4d_populate_init(&init_mm, p4d, pud, init);
7e82ea94
KS
724 spin_unlock(&init_mm.page_table_lock);
725 }
7e82ea94
KS
726
727 return paddr_last;
728}
729
eccd9064
BS
730static unsigned long __meminit
731__kernel_physical_mapping_init(unsigned long paddr_start,
732 unsigned long paddr_end,
733 unsigned long page_size_mask,
c164fbb4 734 pgprot_t prot, bool init)
14a62c34 735{
9b861528 736 bool pgd_changed = false;
59b3d020 737 unsigned long vaddr, vaddr_start, vaddr_end, vaddr_next, paddr_last;
1da177e4 738
59b3d020
TG
739 paddr_last = paddr_end;
740 vaddr = (unsigned long)__va(paddr_start);
741 vaddr_end = (unsigned long)__va(paddr_end);
742 vaddr_start = vaddr;
1da177e4 743
59b3d020
TG
744 for (; vaddr < vaddr_end; vaddr = vaddr_next) {
745 pgd_t *pgd = pgd_offset_k(vaddr);
f2a6a705 746 p4d_t *p4d;
44df75e6 747
59b3d020 748 vaddr_next = (vaddr & PGDIR_MASK) + PGDIR_SIZE;
4f9c11dd 749
7e82ea94
KS
750 if (pgd_val(*pgd)) {
751 p4d = (p4d_t *)pgd_page_vaddr(*pgd);
752 paddr_last = phys_p4d_init(p4d, __pa(vaddr),
59b3d020 753 __pa(vaddr_end),
eccd9064 754 page_size_mask,
c164fbb4 755 prot, init);
4f9c11dd
JF
756 continue;
757 }
758
7e82ea94
KS
759 p4d = alloc_low_page();
760 paddr_last = phys_p4d_init(p4d, __pa(vaddr), __pa(vaddr_end),
c164fbb4 761 page_size_mask, prot, init);
8ae3a5a8
JB
762
763 spin_lock(&init_mm.page_table_lock);
ed7588d5 764 if (pgtable_l5_enabled())
eccd9064 765 pgd_populate_init(&init_mm, pgd, p4d, init);
7e82ea94 766 else
eccd9064
BS
767 p4d_populate_init(&init_mm, p4d_offset(pgd, vaddr),
768 (pud_t *) p4d, init);
769
8ae3a5a8 770 spin_unlock(&init_mm.page_table_lock);
9b861528 771 pgd_changed = true;
14a62c34 772 }
9b861528
HL
773
774 if (pgd_changed)
5372e155 775 sync_global_pgds(vaddr_start, vaddr_end - 1);
9b861528 776
59b3d020 777 return paddr_last;
b50efd2a 778}
7b16eb89 779
eccd9064
BS
780
781/*
782 * Create page table mapping for the physical memory for specific physical
783 * addresses. Note that it can only be used to populate non-present entries.
784 * The virtual and physical addresses have to be aligned on PMD level
785 * down. It returns the last physical address mapped.
786 */
787unsigned long __meminit
788kernel_physical_mapping_init(unsigned long paddr_start,
789 unsigned long paddr_end,
c164fbb4 790 unsigned long page_size_mask, pgprot_t prot)
eccd9064
BS
791{
792 return __kernel_physical_mapping_init(paddr_start, paddr_end,
c164fbb4 793 page_size_mask, prot, true);
eccd9064
BS
794}
795
796/*
797 * This function is similar to kernel_physical_mapping_init() above with the
798 * exception that it uses set_{pud,pmd}() instead of the set_{pud,pte}_safe()
799 * when updating the mapping. The caller is responsible to flush the TLBs after
800 * the function returns.
801 */
802unsigned long __meminit
803kernel_physical_mapping_change(unsigned long paddr_start,
804 unsigned long paddr_end,
805 unsigned long page_size_mask)
806{
807 return __kernel_physical_mapping_init(paddr_start, paddr_end,
c164fbb4
LG
808 page_size_mask, PAGE_KERNEL,
809 false);
eccd9064
BS
810}
811
2b97690f 812#ifndef CONFIG_NUMA
d8fc3afc 813void __init initmem_init(void)
1f75d7e3 814{
d7dc899a 815 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1f75d7e3 816}
3551f88f 817#endif
1f75d7e3 818
1da177e4
LT
819void __init paging_init(void)
820{
3551f88f 821 sparse_memory_present_with_active_regions(MAX_NUMNODES);
44df75e6 822 sparse_init();
44b57280
YL
823
824 /*
825 * clear the default setting with node 0
826 * note: don't use nodes_clear here, that is really clearing when
827 * numa support is not compiled in, and later node_set_state
828 * will not set it back.
829 */
4b0ef1fe 830 node_clear_state(0, N_MEMORY);
aa61ee7b 831 node_clear_state(0, N_NORMAL_MEMORY);
44b57280 832
4c0b2e5f 833 zone_sizes_init();
1da177e4 834}
1da177e4 835
44df75e6
MT
836/*
837 * Memory hotplug specific functions
44df75e6 838 */
bc02af93 839#ifdef CONFIG_MEMORY_HOTPLUG
ea085417
SZ
840/*
841 * After memory hotplug the variables max_pfn, max_low_pfn and high_memory need
842 * updating.
843 */
3072e413 844static void update_end_of_memory_vars(u64 start, u64 size)
ea085417
SZ
845{
846 unsigned long end_pfn = PFN_UP(start + size);
847
848 if (end_pfn > max_pfn) {
849 max_pfn = end_pfn;
850 max_low_pfn = end_pfn;
851 high_memory = (void *)__va(max_pfn * PAGE_SIZE - 1) + 1;
852 }
853}
854
24e6d5a5 855int add_pages(int nid, unsigned long start_pfn, unsigned long nr_pages,
f5637d3b 856 struct mhp_params *params)
44df75e6 857{
44df75e6
MT
858 int ret;
859
f5637d3b 860 ret = __add_pages(nid, start_pfn, nr_pages, params);
fe8b868e 861 WARN_ON_ONCE(ret);
44df75e6 862
ea085417 863 /* update max_pfn, max_low_pfn and high_memory */
3072e413
MH
864 update_end_of_memory_vars(start_pfn << PAGE_SHIFT,
865 nr_pages << PAGE_SHIFT);
ea085417 866
44df75e6 867 return ret;
44df75e6 868}
3072e413 869
940519f0 870int arch_add_memory(int nid, u64 start, u64 size,
f5637d3b 871 struct mhp_params *params)
3072e413
MH
872{
873 unsigned long start_pfn = start >> PAGE_SHIFT;
874 unsigned long nr_pages = size >> PAGE_SHIFT;
875
bfeb022f 876 init_memory_mapping(start, start + size, params->pgprot);
3072e413 877
f5637d3b 878 return add_pages(nid, start_pfn, nr_pages, params);
3072e413 879}
44df75e6 880
ae9aae9e
WC
881#define PAGE_INUSE 0xFD
882
a7e6c701 883static void __meminit free_pagetable(struct page *page, int order)
ae9aae9e 884{
ae9aae9e
WC
885 unsigned long magic;
886 unsigned int nr_pages = 1 << order;
4b94ffdc 887
ae9aae9e
WC
888 /* bootmem page has reserved flag */
889 if (PageReserved(page)) {
890 __ClearPageReserved(page);
ae9aae9e 891
ddffe98d 892 magic = (unsigned long)page->freelist;
ae9aae9e
WC
893 if (magic == SECTION_INFO || magic == MIX_SECTION_INFO) {
894 while (nr_pages--)
895 put_page_bootmem(page++);
896 } else
170a5a7e
JL
897 while (nr_pages--)
898 free_reserved_page(page++);
ae9aae9e
WC
899 } else
900 free_pages((unsigned long)page_address(page), order);
ae9aae9e
WC
901}
902
a7e6c701 903static void __meminit free_hugepage_table(struct page *page,
24b6d416 904 struct vmem_altmap *altmap)
a7e6c701
DW
905{
906 if (altmap)
907 vmem_altmap_free(altmap, PMD_SIZE / PAGE_SIZE);
908 else
909 free_pagetable(page, get_order(PMD_SIZE));
910}
911
912static void __meminit free_pte_table(pte_t *pte_start, pmd_t *pmd)
ae9aae9e
WC
913{
914 pte_t *pte;
915 int i;
916
917 for (i = 0; i < PTRS_PER_PTE; i++) {
918 pte = pte_start + i;
dcb32d99 919 if (!pte_none(*pte))
ae9aae9e
WC
920 return;
921 }
922
923 /* free a pte talbe */
a7e6c701 924 free_pagetable(pmd_page(*pmd), 0);
ae9aae9e
WC
925 spin_lock(&init_mm.page_table_lock);
926 pmd_clear(pmd);
927 spin_unlock(&init_mm.page_table_lock);
928}
929
a7e6c701 930static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud)
ae9aae9e
WC
931{
932 pmd_t *pmd;
933 int i;
934
935 for (i = 0; i < PTRS_PER_PMD; i++) {
936 pmd = pmd_start + i;
dcb32d99 937 if (!pmd_none(*pmd))
ae9aae9e
WC
938 return;
939 }
940
941 /* free a pmd talbe */
a7e6c701 942 free_pagetable(pud_page(*pud), 0);
ae9aae9e
WC
943 spin_lock(&init_mm.page_table_lock);
944 pud_clear(pud);
945 spin_unlock(&init_mm.page_table_lock);
946}
947
a7e6c701 948static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d)
f2a6a705
KS
949{
950 pud_t *pud;
951 int i;
952
953 for (i = 0; i < PTRS_PER_PUD; i++) {
954 pud = pud_start + i;
955 if (!pud_none(*pud))
956 return;
957 }
958
959 /* free a pud talbe */
a7e6c701 960 free_pagetable(p4d_page(*p4d), 0);
f2a6a705
KS
961 spin_lock(&init_mm.page_table_lock);
962 p4d_clear(p4d);
963 spin_unlock(&init_mm.page_table_lock);
964}
965
ae9aae9e
WC
966static void __meminit
967remove_pte_table(pte_t *pte_start, unsigned long addr, unsigned long end,
a7e6c701 968 bool direct)
ae9aae9e
WC
969{
970 unsigned long next, pages = 0;
971 pte_t *pte;
972 void *page_addr;
973 phys_addr_t phys_addr;
974
975 pte = pte_start + pte_index(addr);
976 for (; addr < end; addr = next, pte++) {
977 next = (addr + PAGE_SIZE) & PAGE_MASK;
978 if (next > end)
979 next = end;
980
981 if (!pte_present(*pte))
982 continue;
983
984 /*
985 * We mapped [0,1G) memory as identity mapping when
986 * initializing, in arch/x86/kernel/head_64.S. These
987 * pagetables cannot be removed.
988 */
989 phys_addr = pte_val(*pte) + (addr & PAGE_MASK);
990 if (phys_addr < (phys_addr_t)0x40000000)
991 return;
992
b500f77b 993 if (PAGE_ALIGNED(addr) && PAGE_ALIGNED(next)) {
ae9aae9e
WC
994 /*
995 * Do not free direct mapping pages since they were
996 * freed when offlining, or simplely not in use.
997 */
998 if (!direct)
a7e6c701 999 free_pagetable(pte_page(*pte), 0);
ae9aae9e
WC
1000
1001 spin_lock(&init_mm.page_table_lock);
1002 pte_clear(&init_mm, addr, pte);
1003 spin_unlock(&init_mm.page_table_lock);
1004
1005 /* For non-direct mapping, pages means nothing. */
1006 pages++;
1007 } else {
1008 /*
1009 * If we are here, we are freeing vmemmap pages since
1010 * direct mapped memory ranges to be freed are aligned.
1011 *
1012 * If we are not removing the whole page, it means
1013 * other page structs in this page are being used and
1014 * we canot remove them. So fill the unused page_structs
1015 * with 0xFD, and remove the page when it is wholly
1016 * filled with 0xFD.
1017 */
1018 memset((void *)addr, PAGE_INUSE, next - addr);
1019
1020 page_addr = page_address(pte_page(*pte));
1021 if (!memchr_inv(page_addr, PAGE_INUSE, PAGE_SIZE)) {
a7e6c701 1022 free_pagetable(pte_page(*pte), 0);
ae9aae9e
WC
1023
1024 spin_lock(&init_mm.page_table_lock);
1025 pte_clear(&init_mm, addr, pte);
1026 spin_unlock(&init_mm.page_table_lock);
1027 }
1028 }
1029 }
1030
1031 /* Call free_pte_table() in remove_pmd_table(). */
1032 flush_tlb_all();
1033 if (direct)
1034 update_page_count(PG_LEVEL_4K, -pages);
1035}
1036
1037static void __meminit
1038remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
24b6d416 1039 bool direct, struct vmem_altmap *altmap)
ae9aae9e
WC
1040{
1041 unsigned long next, pages = 0;
1042 pte_t *pte_base;
1043 pmd_t *pmd;
1044 void *page_addr;
1045
1046 pmd = pmd_start + pmd_index(addr);
1047 for (; addr < end; addr = next, pmd++) {
1048 next = pmd_addr_end(addr, end);
1049
1050 if (!pmd_present(*pmd))
1051 continue;
1052
1053 if (pmd_large(*pmd)) {
1054 if (IS_ALIGNED(addr, PMD_SIZE) &&
1055 IS_ALIGNED(next, PMD_SIZE)) {
1056 if (!direct)
a7e6c701
DW
1057 free_hugepage_table(pmd_page(*pmd),
1058 altmap);
ae9aae9e
WC
1059
1060 spin_lock(&init_mm.page_table_lock);
1061 pmd_clear(pmd);
1062 spin_unlock(&init_mm.page_table_lock);
1063 pages++;
1064 } else {
1065 /* If here, we are freeing vmemmap pages. */
1066 memset((void *)addr, PAGE_INUSE, next - addr);
1067
1068 page_addr = page_address(pmd_page(*pmd));
1069 if (!memchr_inv(page_addr, PAGE_INUSE,
1070 PMD_SIZE)) {
a7e6c701
DW
1071 free_hugepage_table(pmd_page(*pmd),
1072 altmap);
ae9aae9e
WC
1073
1074 spin_lock(&init_mm.page_table_lock);
1075 pmd_clear(pmd);
1076 spin_unlock(&init_mm.page_table_lock);
1077 }
1078 }
1079
1080 continue;
1081 }
1082
1083 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
a7e6c701
DW
1084 remove_pte_table(pte_base, addr, next, direct);
1085 free_pte_table(pte_base, pmd);
ae9aae9e
WC
1086 }
1087
1088 /* Call free_pmd_table() in remove_pud_table(). */
1089 if (direct)
1090 update_page_count(PG_LEVEL_2M, -pages);
1091}
1092
1093static void __meminit
1094remove_pud_table(pud_t *pud_start, unsigned long addr, unsigned long end,
24b6d416 1095 struct vmem_altmap *altmap, bool direct)
ae9aae9e
WC
1096{
1097 unsigned long next, pages = 0;
1098 pmd_t *pmd_base;
1099 pud_t *pud;
1100 void *page_addr;
1101
1102 pud = pud_start + pud_index(addr);
1103 for (; addr < end; addr = next, pud++) {
1104 next = pud_addr_end(addr, end);
1105
1106 if (!pud_present(*pud))
1107 continue;
1108
1109 if (pud_large(*pud)) {
1110 if (IS_ALIGNED(addr, PUD_SIZE) &&
1111 IS_ALIGNED(next, PUD_SIZE)) {
1112 if (!direct)
1113 free_pagetable(pud_page(*pud),
a7e6c701 1114 get_order(PUD_SIZE));
ae9aae9e
WC
1115
1116 spin_lock(&init_mm.page_table_lock);
1117 pud_clear(pud);
1118 spin_unlock(&init_mm.page_table_lock);
1119 pages++;
1120 } else {
1121 /* If here, we are freeing vmemmap pages. */
1122 memset((void *)addr, PAGE_INUSE, next - addr);
1123
1124 page_addr = page_address(pud_page(*pud));
1125 if (!memchr_inv(page_addr, PAGE_INUSE,
1126 PUD_SIZE)) {
1127 free_pagetable(pud_page(*pud),
a7e6c701 1128 get_order(PUD_SIZE));
ae9aae9e
WC
1129
1130 spin_lock(&init_mm.page_table_lock);
1131 pud_clear(pud);
1132 spin_unlock(&init_mm.page_table_lock);
1133 }
1134 }
1135
1136 continue;
1137 }
1138
e6ab9c4d 1139 pmd_base = pmd_offset(pud, 0);
24b6d416 1140 remove_pmd_table(pmd_base, addr, next, direct, altmap);
a7e6c701 1141 free_pmd_table(pmd_base, pud);
ae9aae9e
WC
1142 }
1143
1144 if (direct)
1145 update_page_count(PG_LEVEL_1G, -pages);
1146}
1147
f2a6a705
KS
1148static void __meminit
1149remove_p4d_table(p4d_t *p4d_start, unsigned long addr, unsigned long end,
24b6d416 1150 struct vmem_altmap *altmap, bool direct)
f2a6a705
KS
1151{
1152 unsigned long next, pages = 0;
1153 pud_t *pud_base;
1154 p4d_t *p4d;
1155
1156 p4d = p4d_start + p4d_index(addr);
1157 for (; addr < end; addr = next, p4d++) {
1158 next = p4d_addr_end(addr, end);
1159
1160 if (!p4d_present(*p4d))
1161 continue;
1162
1163 BUILD_BUG_ON(p4d_large(*p4d));
1164
e6ab9c4d 1165 pud_base = pud_offset(p4d, 0);
24b6d416 1166 remove_pud_table(pud_base, addr, next, altmap, direct);
98fe3633
JG
1167 /*
1168 * For 4-level page tables we do not want to free PUDs, but in the
1169 * 5-level case we should free them. This code will have to change
1170 * to adapt for boot-time switching between 4 and 5 level page tables.
1171 */
ed7588d5 1172 if (pgtable_l5_enabled())
a7e6c701 1173 free_pud_table(pud_base, p4d);
f2a6a705
KS
1174 }
1175
1176 if (direct)
1177 update_page_count(PG_LEVEL_512G, -pages);
1178}
1179
ae9aae9e
WC
1180/* start and end are both virtual address. */
1181static void __meminit
24b6d416
CH
1182remove_pagetable(unsigned long start, unsigned long end, bool direct,
1183 struct vmem_altmap *altmap)
ae9aae9e
WC
1184{
1185 unsigned long next;
5255e0a7 1186 unsigned long addr;
ae9aae9e 1187 pgd_t *pgd;
f2a6a705 1188 p4d_t *p4d;
ae9aae9e 1189
5255e0a7
YI
1190 for (addr = start; addr < end; addr = next) {
1191 next = pgd_addr_end(addr, end);
ae9aae9e 1192
5255e0a7 1193 pgd = pgd_offset_k(addr);
ae9aae9e
WC
1194 if (!pgd_present(*pgd))
1195 continue;
1196
e6ab9c4d 1197 p4d = p4d_offset(pgd, 0);
24b6d416 1198 remove_p4d_table(p4d, addr, next, altmap, direct);
ae9aae9e
WC
1199 }
1200
ae9aae9e
WC
1201 flush_tlb_all();
1202}
1203
24b6d416
CH
1204void __ref vmemmap_free(unsigned long start, unsigned long end,
1205 struct vmem_altmap *altmap)
0197518c 1206{
24b6d416 1207 remove_pagetable(start, end, false, altmap);
0197518c
TC
1208}
1209
bbcab878
TC
1210static void __meminit
1211kernel_physical_mapping_remove(unsigned long start, unsigned long end)
1212{
1213 start = (unsigned long)__va(start);
1214 end = (unsigned long)__va(end);
1215
24b6d416 1216 remove_pagetable(start, end, true, NULL);
bbcab878
TC
1217}
1218
ac5c9426
DH
1219void __ref arch_remove_memory(int nid, u64 start, u64 size,
1220 struct vmem_altmap *altmap)
24d335ca
WC
1221{
1222 unsigned long start_pfn = start >> PAGE_SHIFT;
1223 unsigned long nr_pages = size >> PAGE_SHIFT;
24d335ca 1224
feee6b29 1225 __remove_pages(start_pfn, nr_pages, altmap);
4b94ffdc 1226 kernel_physical_mapping_remove(start, start + size);
24d335ca 1227}
45e0b78b
KM
1228#endif /* CONFIG_MEMORY_HOTPLUG */
1229
81ac3ad9 1230static struct kcore_list kcore_vsyscall;
1da177e4 1231
94b43c3d
YL
1232static void __init register_page_bootmem_info(void)
1233{
1234#ifdef CONFIG_NUMA
1235 int i;
1236
1237 for_each_online_node(i)
1238 register_page_bootmem_info_node(NODE_DATA(i));
1239#endif
1240}
1241
1da177e4
LT
1242void __init mem_init(void)
1243{
0dc243ae 1244 pci_iommu_alloc();
1da177e4 1245
48ddb154 1246 /* clear_bss() already clear the empty_zero_page */
1da177e4 1247
bced0e32 1248 /* this will put all memory onto the freelists */
c6ffc5ca 1249 memblock_free_all();
1da177e4 1250 after_bootmem = 1;
6f84f8d1 1251 x86_init.hyper.init_after_bootmem();
1da177e4 1252
353b1e7b
PT
1253 /*
1254 * Must be done after boot memory is put on freelist, because here we
1255 * might set fields in deferred struct pages that have not yet been
c6ffc5ca 1256 * initialized, and memblock_free_all() initializes all the reserved
353b1e7b
PT
1257 * deferred pages for us.
1258 */
1259 register_page_bootmem_info();
1260
1da177e4 1261 /* Register memory areas for /proc/kcore */
cd026ca2
JZ
1262 if (get_gate_vma(&init_mm))
1263 kclist_add(&kcore_vsyscall, (void *)VSYSCALL_ADDR, PAGE_SIZE, KCORE_USER);
1da177e4 1264
46a84132 1265 mem_init_print_info(NULL);
1da177e4
LT
1266}
1267
502f6604 1268int kernel_set_to_readonly;
16239630 1269
67df197b
AV
1270void mark_rodata_ro(void)
1271{
74e08179 1272 unsigned long start = PFN_ALIGN(_text);
fc8d7826 1273 unsigned long rodata_start = PFN_ALIGN(__start_rodata);
2d0004d1
KC
1274 unsigned long end = (unsigned long)__end_rodata_hpage_align;
1275 unsigned long text_end = PFN_ALIGN(_etext);
1276 unsigned long rodata_end = PFN_ALIGN(__end_rodata);
45e2a9d4 1277 unsigned long all_end;
8f0f996e 1278
6fb14755 1279 printk(KERN_INFO "Write protecting the kernel read-only data: %luk\n",
e3ebadd9 1280 (end - start) >> 10);
984bb80d
AV
1281 set_memory_ro(start, (end - start) >> PAGE_SHIFT);
1282
16239630
SR
1283 kernel_set_to_readonly = 1;
1284
984bb80d 1285 /*
72212675
YL
1286 * The rodata/data/bss/brk section (but not the kernel text!)
1287 * should also be not-executable.
45e2a9d4
KC
1288 *
1289 * We align all_end to PMD_SIZE because the existing mapping
1290 * is a full PMD. If we would align _brk_end to PAGE_SIZE we
1291 * split the PMD and the reminder between _brk_end and the end
1292 * of the PMD will remain mapped executable.
1293 *
1294 * Any PMD which was setup after the one which covers _brk_end
1295 * has been zapped already via cleanup_highmem().
984bb80d 1296 */
45e2a9d4 1297 all_end = roundup((unsigned long)_brk_end, PMD_SIZE);
ab76f7b4 1298 set_memory_nx(text_end, (all_end - text_end) >> PAGE_SHIFT);
67df197b 1299
59566b0b
SRV
1300 set_ftrace_ops_ro();
1301
0c42f392 1302#ifdef CONFIG_CPA_DEBUG
10f22dde 1303 printk(KERN_INFO "Testing CPA: undo %lx-%lx\n", start, end);
6d238cc4 1304 set_memory_rw(start, (end-start) >> PAGE_SHIFT);
0c42f392 1305
10f22dde 1306 printk(KERN_INFO "Testing CPA: again\n");
6d238cc4 1307 set_memory_ro(start, (end-start) >> PAGE_SHIFT);
0c42f392 1308#endif
74e08179 1309
5494c3a6
KC
1310 free_kernel_image_pages("unused kernel image (text/rodata gap)",
1311 (void *)text_end, (void *)rodata_start);
1312 free_kernel_image_pages("unused kernel image (rodata/data gap)",
1313 (void *)rodata_end, (void *)_sdata);
e1a58320
SS
1314
1315 debug_checkwx();
67df197b 1316}
4e4eee0e 1317
14a62c34
TG
1318int kern_addr_valid(unsigned long addr)
1319{
1da177e4 1320 unsigned long above = ((long)addr) >> __VIRTUAL_MASK_SHIFT;
14a62c34 1321 pgd_t *pgd;
f2a6a705 1322 p4d_t *p4d;
14a62c34
TG
1323 pud_t *pud;
1324 pmd_t *pmd;
1325 pte_t *pte;
1da177e4
LT
1326
1327 if (above != 0 && above != -1UL)
14a62c34
TG
1328 return 0;
1329
1da177e4
LT
1330 pgd = pgd_offset_k(addr);
1331 if (pgd_none(*pgd))
1332 return 0;
1333
f2a6a705
KS
1334 p4d = p4d_offset(pgd, addr);
1335 if (p4d_none(*p4d))
1336 return 0;
1337
1338 pud = pud_offset(p4d, addr);
1da177e4 1339 if (pud_none(*pud))
14a62c34 1340 return 0;
1da177e4 1341
0ee364eb
MG
1342 if (pud_large(*pud))
1343 return pfn_valid(pud_pfn(*pud));
1344
1da177e4
LT
1345 pmd = pmd_offset(pud, addr);
1346 if (pmd_none(*pmd))
1347 return 0;
14a62c34 1348
1da177e4
LT
1349 if (pmd_large(*pmd))
1350 return pfn_valid(pmd_pfn(*pmd));
1351
1352 pte = pte_offset_kernel(pmd, addr);
1353 if (pte_none(*pte))
1354 return 0;
14a62c34 1355
1da177e4
LT
1356 return pfn_valid(pte_pfn(*pte));
1357}
1358
078eb6aa
PT
1359/*
1360 * Block size is the minimum amount of memory which can be hotplugged or
1361 * hotremoved. It must be power of two and must be equal or larger than
1362 * MIN_MEMORY_BLOCK_SIZE.
1363 */
1364#define MAX_BLOCK_SIZE (2UL << 30)
1365
1366/* Amount of ram needed to start using large blocks */
1367#define MEM_SIZE_FOR_LARGE_BLOCK (64UL << 30)
1368
f642fb58 1369/* Adjustable memory block size */
1370static unsigned long set_memory_block_size;
1371int __init set_memory_block_size_order(unsigned int order)
1372{
1373 unsigned long size = 1UL << order;
1374
1375 if (size > MEM_SIZE_FOR_LARGE_BLOCK || size < MIN_MEMORY_BLOCK_SIZE)
1376 return -EINVAL;
1377
1378 set_memory_block_size = size;
1379 return 0;
1380}
1381
982792c7 1382static unsigned long probe_memory_block_size(void)
1dc41aa6 1383{
078eb6aa
PT
1384 unsigned long boot_mem_end = max_pfn << PAGE_SHIFT;
1385 unsigned long bz;
982792c7 1386
f642fb58 1387 /* If memory block size has been set, then use it */
1388 bz = set_memory_block_size;
1389 if (bz)
078eb6aa 1390 goto done;
982792c7 1391
078eb6aa
PT
1392 /* Use regular block if RAM is smaller than MEM_SIZE_FOR_LARGE_BLOCK */
1393 if (boot_mem_end < MEM_SIZE_FOR_LARGE_BLOCK) {
1394 bz = MIN_MEMORY_BLOCK_SIZE;
1395 goto done;
1396 }
1397
1398 /* Find the largest allowed block size that aligns to memory end */
1399 for (bz = MAX_BLOCK_SIZE; bz > MIN_MEMORY_BLOCK_SIZE; bz >>= 1) {
1400 if (IS_ALIGNED(boot_mem_end, bz))
1401 break;
1402 }
1403done:
43c75f93 1404 pr_info("x86/mm: Memory block size: %ldMB\n", bz >> 20);
982792c7
YL
1405
1406 return bz;
1407}
1408
1409static unsigned long memory_block_size_probed;
1410unsigned long memory_block_size_bytes(void)
1411{
1412 if (!memory_block_size_probed)
1413 memory_block_size_probed = probe_memory_block_size();
1414
1415 return memory_block_size_probed;
1416}
1417
0889eba5
CL
1418#ifdef CONFIG_SPARSEMEM_VMEMMAP
1419/*
1420 * Initialise the sparsemem vmemmap using huge-pages at the PMD level.
1421 */
c2b91e2e
YL
1422static long __meminitdata addr_start, addr_end;
1423static void __meminitdata *p_start, *p_end;
1424static int __meminitdata node_start;
1425
e8216da5 1426static int __meminit vmemmap_populate_hugepages(unsigned long start,
4b94ffdc 1427 unsigned long end, int node, struct vmem_altmap *altmap)
0889eba5 1428{
0aad818b 1429 unsigned long addr;
0889eba5
CL
1430 unsigned long next;
1431 pgd_t *pgd;
f2a6a705 1432 p4d_t *p4d;
0889eba5
CL
1433 pud_t *pud;
1434 pmd_t *pmd;
1435
0aad818b 1436 for (addr = start; addr < end; addr = next) {
e8216da5 1437 next = pmd_addr_end(addr, end);
0889eba5
CL
1438
1439 pgd = vmemmap_pgd_populate(addr, node);
1440 if (!pgd)
1441 return -ENOMEM;
14a62c34 1442
f2a6a705
KS
1443 p4d = vmemmap_p4d_populate(pgd, addr, node);
1444 if (!p4d)
1445 return -ENOMEM;
1446
1447 pud = vmemmap_pud_populate(p4d, addr, node);
0889eba5
CL
1448 if (!pud)
1449 return -ENOMEM;
1450
e8216da5
JW
1451 pmd = pmd_offset(pud, addr);
1452 if (pmd_none(*pmd)) {
e8216da5 1453 void *p;
14a62c34 1454
a8fc357b
CH
1455 if (altmap)
1456 p = altmap_alloc_block_buf(PMD_SIZE, altmap);
1457 else
1458 p = vmemmap_alloc_block_buf(PMD_SIZE, node);
8e2cdbcb
JW
1459 if (p) {
1460 pte_t entry;
1461
1462 entry = pfn_pte(__pa(p) >> PAGE_SHIFT,
1463 PAGE_KERNEL_LARGE);
1464 set_pmd(pmd, __pmd(pte_val(entry)));
1465
1466 /* check to see if we have contiguous blocks */
1467 if (p_end != p || node_start != node) {
1468 if (p_start)
c9cdaeb2 1469 pr_debug(" [%lx-%lx] PMD -> [%p-%p] on node %d\n",
8e2cdbcb
JW
1470 addr_start, addr_end-1, p_start, p_end-1, node_start);
1471 addr_start = addr;
1472 node_start = node;
1473 p_start = p;
1474 }
7c934d39 1475
8e2cdbcb
JW
1476 addr_end = addr + PMD_SIZE;
1477 p_end = p + PMD_SIZE;
1478 continue;
4b94ffdc
DW
1479 } else if (altmap)
1480 return -ENOMEM; /* no fallback */
8e2cdbcb 1481 } else if (pmd_large(*pmd)) {
e8216da5 1482 vmemmap_verify((pte_t *)pmd, node, addr, next);
8e2cdbcb
JW
1483 continue;
1484 }
8e2cdbcb
JW
1485 if (vmemmap_populate_basepages(addr, next, node))
1486 return -ENOMEM;
0889eba5 1487 }
0889eba5
CL
1488 return 0;
1489}
c2b91e2e 1490
7b73d978
CH
1491int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node,
1492 struct vmem_altmap *altmap)
e8216da5
JW
1493{
1494 int err;
1495
e9c0a3f0
DW
1496 if (end - start < PAGES_PER_SECTION * sizeof(struct page))
1497 err = vmemmap_populate_basepages(start, end, node);
1498 else if (boot_cpu_has(X86_FEATURE_PSE))
4b94ffdc
DW
1499 err = vmemmap_populate_hugepages(start, end, node, altmap);
1500 else if (altmap) {
1501 pr_err_once("%s: no cpu support for altmap allocations\n",
1502 __func__);
1503 err = -ENOMEM;
1504 } else
e8216da5
JW
1505 err = vmemmap_populate_basepages(start, end, node);
1506 if (!err)
5372e155 1507 sync_global_pgds(start, end - 1);
e8216da5
JW
1508 return err;
1509}
1510
46723bfa
YI
1511#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE) && defined(CONFIG_HAVE_BOOTMEM_INFO_NODE)
1512void register_page_bootmem_memmap(unsigned long section_nr,
15670bfe 1513 struct page *start_page, unsigned long nr_pages)
46723bfa
YI
1514{
1515 unsigned long addr = (unsigned long)start_page;
15670bfe 1516 unsigned long end = (unsigned long)(start_page + nr_pages);
46723bfa
YI
1517 unsigned long next;
1518 pgd_t *pgd;
f2a6a705 1519 p4d_t *p4d;
46723bfa
YI
1520 pud_t *pud;
1521 pmd_t *pmd;
15670bfe 1522 unsigned int nr_pmd_pages;
46723bfa
YI
1523 struct page *page;
1524
1525 for (; addr < end; addr = next) {
1526 pte_t *pte = NULL;
1527
1528 pgd = pgd_offset_k(addr);
1529 if (pgd_none(*pgd)) {
1530 next = (addr + PAGE_SIZE) & PAGE_MASK;
1531 continue;
1532 }
1533 get_page_bootmem(section_nr, pgd_page(*pgd), MIX_SECTION_INFO);
1534
f2a6a705
KS
1535 p4d = p4d_offset(pgd, addr);
1536 if (p4d_none(*p4d)) {
1537 next = (addr + PAGE_SIZE) & PAGE_MASK;
1538 continue;
1539 }
1540 get_page_bootmem(section_nr, p4d_page(*p4d), MIX_SECTION_INFO);
1541
1542 pud = pud_offset(p4d, addr);
46723bfa
YI
1543 if (pud_none(*pud)) {
1544 next = (addr + PAGE_SIZE) & PAGE_MASK;
1545 continue;
1546 }
1547 get_page_bootmem(section_nr, pud_page(*pud), MIX_SECTION_INFO);
1548
16bf9226 1549 if (!boot_cpu_has(X86_FEATURE_PSE)) {
46723bfa
YI
1550 next = (addr + PAGE_SIZE) & PAGE_MASK;
1551 pmd = pmd_offset(pud, addr);
1552 if (pmd_none(*pmd))
1553 continue;
1554 get_page_bootmem(section_nr, pmd_page(*pmd),
1555 MIX_SECTION_INFO);
1556
1557 pte = pte_offset_kernel(pmd, addr);
1558 if (pte_none(*pte))
1559 continue;
1560 get_page_bootmem(section_nr, pte_page(*pte),
1561 SECTION_INFO);
1562 } else {
1563 next = pmd_addr_end(addr, end);
1564
1565 pmd = pmd_offset(pud, addr);
1566 if (pmd_none(*pmd))
1567 continue;
1568
15670bfe 1569 nr_pmd_pages = 1 << get_order(PMD_SIZE);
46723bfa 1570 page = pmd_page(*pmd);
15670bfe 1571 while (nr_pmd_pages--)
46723bfa
YI
1572 get_page_bootmem(section_nr, page++,
1573 SECTION_INFO);
1574 }
1575 }
1576}
1577#endif
1578
c2b91e2e
YL
1579void __meminit vmemmap_populate_print_last(void)
1580{
1581 if (p_start) {
c9cdaeb2 1582 pr_debug(" [%lx-%lx] PMD -> [%p-%p] on node %d\n",
c2b91e2e
YL
1583 addr_start, addr_end-1, p_start, p_end-1, node_start);
1584 p_start = NULL;
1585 p_end = NULL;
1586 node_start = 0;
1587 }
1588}
0889eba5 1589#endif