1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/mem_encrypt.h>
22 #include <linux/smp.h>
23 #include <linux/cpu.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/pgtable.h>
27 #include <linux/stackprotector.h>
28 #include <linux/utsname.h>
30 #include <asm/alternative.h>
31 #include <asm/cmdline.h>
32 #include <asm/perf_event.h>
33 #include <asm/mmu_context.h>
34 #include <asm/doublefault.h>
35 #include <asm/archrandom.h>
36 #include <asm/hypervisor.h>
37 #include <asm/processor.h>
38 #include <asm/tlbflush.h>
39 #include <asm/debugreg.h>
40 #include <asm/sections.h>
41 #include <asm/vsyscall.h>
42 #include <linux/topology.h>
43 #include <linux/cpumask.h>
44 #include <linux/atomic.h>
45 #include <asm/proto.h>
46 #include <asm/setup.h>
49 #include <asm/fpu/api.h>
51 #include <asm/hwcap2.h>
52 #include <linux/numa.h>
59 #include <asm/cacheinfo.h>
60 #include <asm/memtype.h>
61 #include <asm/microcode.h>
62 #include <asm/microcode_intel.h>
63 #include <asm/intel-family.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/uv/uv.h>
66 #include <asm/set_memory.h>
67 #include <asm/traps.h>
72 u32 elf_hwcap2 __read_mostly
;
74 /* Number of siblings per CPU package */
75 int smp_num_siblings
= 1;
76 EXPORT_SYMBOL(smp_num_siblings
);
78 /* Last level cache ID of each logical CPU */
79 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
81 u16
get_llc_id(unsigned int cpu
)
83 return per_cpu(cpu_llc_id
, cpu
);
85 EXPORT_SYMBOL_GPL(get_llc_id
);
87 /* L2 cache ID of each logical CPU */
88 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_l2c_id
) = BAD_APICID
;
90 static struct ppin_info
{
95 [X86_VENDOR_INTEL
] = {
96 .feature
= X86_FEATURE_INTEL_PPIN
,
97 .msr_ppin_ctl
= MSR_PPIN_CTL
,
101 .feature
= X86_FEATURE_AMD_PPIN
,
102 .msr_ppin_ctl
= MSR_AMD_PPIN_CTL
,
103 .msr_ppin
= MSR_AMD_PPIN
107 static const struct x86_cpu_id ppin_cpuids
[] = {
108 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN
, &ppin_info
[X86_VENDOR_AMD
]),
109 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN
, &ppin_info
[X86_VENDOR_INTEL
]),
111 /* Legacy models without CPUID enumeration */
112 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X
, &ppin_info
[X86_VENDOR_INTEL
]),
113 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X
, &ppin_info
[X86_VENDOR_INTEL
]),
114 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D
, &ppin_info
[X86_VENDOR_INTEL
]),
115 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X
, &ppin_info
[X86_VENDOR_INTEL
]),
116 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X
, &ppin_info
[X86_VENDOR_INTEL
]),
117 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X
, &ppin_info
[X86_VENDOR_INTEL
]),
118 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D
, &ppin_info
[X86_VENDOR_INTEL
]),
119 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X
, &ppin_info
[X86_VENDOR_INTEL
]),
120 X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X
, &ppin_info
[X86_VENDOR_INTEL
]),
121 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL
, &ppin_info
[X86_VENDOR_INTEL
]),
122 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM
, &ppin_info
[X86_VENDOR_INTEL
]),
127 static void ppin_init(struct cpuinfo_x86
*c
)
129 const struct x86_cpu_id
*id
;
130 unsigned long long val
;
131 struct ppin_info
*info
;
133 id
= x86_match_cpu(ppin_cpuids
);
138 * Testing the presence of the MSR is not enough. Need to check
139 * that the PPIN_CTL allows reading of the PPIN.
141 info
= (struct ppin_info
*)id
->driver_data
;
143 if (rdmsrl_safe(info
->msr_ppin_ctl
, &val
))
146 if ((val
& 3UL) == 1UL) {
147 /* PPIN locked in disabled mode */
151 /* If PPIN is disabled, try to enable */
153 wrmsrl_safe(info
->msr_ppin_ctl
, val
| 2UL);
154 rdmsrl_safe(info
->msr_ppin_ctl
, &val
);
157 /* Is the enable bit set? */
159 c
->ppin
= __rdmsr(info
->msr_ppin
);
160 set_cpu_cap(c
, info
->feature
);
165 clear_cpu_cap(c
, info
->feature
);
168 static void default_init(struct cpuinfo_x86
*c
)
171 cpu_detect_cache_sizes(c
);
173 /* Not much we can do here... */
174 /* Check if at least it has cpuid */
175 if (c
->cpuid_level
== -1) {
176 /* No cpuid. It must be an ancient CPU */
178 strcpy(c
->x86_model_id
, "486");
179 else if (c
->x86
== 3)
180 strcpy(c
->x86_model_id
, "386");
185 static const struct cpu_dev default_cpu
= {
186 .c_init
= default_init
,
187 .c_vendor
= "Unknown",
188 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
191 static const struct cpu_dev
*this_cpu
= &default_cpu
;
193 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
196 * We need valid kernel segments for data and code in long mode too
197 * IRET will check the segment types kkeil 2000/10/28
198 * Also sysret mandates a special GDT layout
200 * TLS descriptors are currently at a different place compared to i386.
201 * Hopefully nobody expects them at a fixed place (Wine?)
203 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
204 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
205 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
206 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
207 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
208 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
210 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
211 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
212 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
213 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
215 * Segments used for calling PnP BIOS have byte granularity.
216 * They code segments and data segments have fixed 64k limits,
217 * the transfer segment sizes are set at run time.
220 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
222 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
224 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
226 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
228 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
230 * The APM segments have byte granularity and their bases
231 * are set at run time. All have 64k limits.
234 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
236 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
238 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
240 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
241 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
244 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
247 static int __init
x86_nopcid_setup(char *s
)
249 /* nopcid doesn't accept parameters */
253 /* do not emit a message if the feature is not present */
254 if (!boot_cpu_has(X86_FEATURE_PCID
))
257 setup_clear_cpu_cap(X86_FEATURE_PCID
);
258 pr_info("nopcid: PCID feature disabled\n");
261 early_param("nopcid", x86_nopcid_setup
);
264 static int __init
x86_noinvpcid_setup(char *s
)
266 /* noinvpcid doesn't accept parameters */
270 /* do not emit a message if the feature is not present */
271 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
274 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
275 pr_info("noinvpcid: INVPCID feature disabled\n");
278 early_param("noinvpcid", x86_noinvpcid_setup
);
281 static int cachesize_override
= -1;
282 static int disable_x86_serial_nr
= 1;
284 static int __init
cachesize_setup(char *str
)
286 get_option(&str
, &cachesize_override
);
289 __setup("cachesize=", cachesize_setup
);
291 /* Standard macro to see if a specific flag is changeable */
292 static inline int flag_is_changeable_p(u32 flag
)
297 * Cyrix and IDT cpus allow disabling of CPUID
298 * so the code below may return different results
299 * when it is executed before and after enabling
300 * the CPUID. Add "volatile" to not allow gcc to
301 * optimize the subsequent calls to this function.
303 asm volatile ("pushfl \n\t"
314 : "=&r" (f1
), "=&r" (f2
)
317 return ((f1
^f2
) & flag
) != 0;
320 /* Probe for the CPUID instruction */
321 int have_cpuid_p(void)
323 return flag_is_changeable_p(X86_EFLAGS_ID
);
326 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
328 unsigned long lo
, hi
;
330 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
333 /* Disable processor serial number: */
335 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
337 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
339 pr_notice("CPU serial number disabled.\n");
340 clear_cpu_cap(c
, X86_FEATURE_PN
);
342 /* Disabling the serial number may affect the cpuid level */
343 c
->cpuid_level
= cpuid_eax(0);
346 static int __init
x86_serial_nr_setup(char *s
)
348 disable_x86_serial_nr
= 0;
351 __setup("serialnumber", x86_serial_nr_setup
);
353 static inline int flag_is_changeable_p(u32 flag
)
357 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
362 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
364 if (cpu_has(c
, X86_FEATURE_SMEP
))
365 cr4_set_bits(X86_CR4_SMEP
);
368 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
370 unsigned long eflags
= native_save_fl();
372 /* This should have been cleared long ago */
373 BUG_ON(eflags
& X86_EFLAGS_AC
);
375 if (cpu_has(c
, X86_FEATURE_SMAP
))
376 cr4_set_bits(X86_CR4_SMAP
);
379 static __always_inline
void setup_umip(struct cpuinfo_x86
*c
)
381 /* Check the boot processor, plus build option for UMIP. */
382 if (!cpu_feature_enabled(X86_FEATURE_UMIP
))
385 /* Check the current processor's cpuid bits. */
386 if (!cpu_has(c
, X86_FEATURE_UMIP
))
389 cr4_set_bits(X86_CR4_UMIP
);
391 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
397 * Make sure UMIP is disabled in case it was enabled in a
398 * previous boot (e.g., via kexec).
400 cr4_clear_bits(X86_CR4_UMIP
);
403 /* These bits should not change their value after CPU init is finished. */
404 static const unsigned long cr4_pinned_mask
=
405 X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_UMIP
|
406 X86_CR4_FSGSBASE
| X86_CR4_CET
;
407 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning
);
408 static unsigned long cr4_pinned_bits __ro_after_init
;
410 void native_write_cr0(unsigned long val
)
412 unsigned long bits_missing
= 0;
415 asm volatile("mov %0,%%cr0": "+r" (val
) : : "memory");
417 if (static_branch_likely(&cr_pinning
)) {
418 if (unlikely((val
& X86_CR0_WP
) != X86_CR0_WP
)) {
419 bits_missing
= X86_CR0_WP
;
423 /* Warn after we've set the missing bits. */
424 WARN_ONCE(bits_missing
, "CR0 WP bit went missing!?\n");
427 EXPORT_SYMBOL(native_write_cr0
);
429 void __no_profile
native_write_cr4(unsigned long val
)
431 unsigned long bits_changed
= 0;
434 asm volatile("mov %0,%%cr4": "+r" (val
) : : "memory");
436 if (static_branch_likely(&cr_pinning
)) {
437 if (unlikely((val
& cr4_pinned_mask
) != cr4_pinned_bits
)) {
438 bits_changed
= (val
& cr4_pinned_mask
) ^ cr4_pinned_bits
;
439 val
= (val
& ~cr4_pinned_mask
) | cr4_pinned_bits
;
442 /* Warn after we've corrected the changed bits. */
443 WARN_ONCE(bits_changed
, "pinned CR4 bits changed: 0x%lx!?\n",
447 #if IS_MODULE(CONFIG_LKDTM)
448 EXPORT_SYMBOL_GPL(native_write_cr4
);
451 void cr4_update_irqsoff(unsigned long set
, unsigned long clear
)
453 unsigned long newval
, cr4
= this_cpu_read(cpu_tlbstate
.cr4
);
455 lockdep_assert_irqs_disabled();
457 newval
= (cr4
& ~clear
) | set
;
459 this_cpu_write(cpu_tlbstate
.cr4
, newval
);
463 EXPORT_SYMBOL(cr4_update_irqsoff
);
465 /* Read the CR4 shadow. */
466 unsigned long cr4_read_shadow(void)
468 return this_cpu_read(cpu_tlbstate
.cr4
);
470 EXPORT_SYMBOL_GPL(cr4_read_shadow
);
474 unsigned long cr4
= __read_cr4();
476 if (boot_cpu_has(X86_FEATURE_PCID
))
477 cr4
|= X86_CR4_PCIDE
;
478 if (static_branch_likely(&cr_pinning
))
479 cr4
= (cr4
& ~cr4_pinned_mask
) | cr4_pinned_bits
;
483 /* Initialize cr4 shadow for this CPU. */
484 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
488 * Once CPU feature detection is finished (and boot params have been
489 * parsed), record any of the sensitive CR bits that are set, and
492 static void __init
setup_cr_pinning(void)
494 cr4_pinned_bits
= this_cpu_read(cpu_tlbstate
.cr4
) & cr4_pinned_mask
;
495 static_key_enable(&cr_pinning
.key
);
498 static __init
int x86_nofsgsbase_setup(char *arg
)
500 /* Require an exact match without trailing characters. */
504 /* Do not emit a message if the feature is not present. */
505 if (!boot_cpu_has(X86_FEATURE_FSGSBASE
))
508 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE
);
509 pr_info("FSGSBASE disabled via kernel command line\n");
512 __setup("nofsgsbase", x86_nofsgsbase_setup
);
515 * Protection Keys are not available in 32-bit mode.
517 static bool pku_disabled
;
519 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
521 if (c
== &boot_cpu_data
) {
522 if (pku_disabled
|| !cpu_feature_enabled(X86_FEATURE_PKU
))
525 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
526 * bit to be set. Enforce it.
528 setup_force_cpu_cap(X86_FEATURE_OSPKE
);
530 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE
)) {
534 cr4_set_bits(X86_CR4_PKE
);
535 /* Load the default PKRU value */
536 pkru_write_default();
539 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
540 static __init
int setup_disable_pku(char *arg
)
543 * Do not clear the X86_FEATURE_PKU bit. All of the
544 * runtime checks are against OSPKE so clearing the
547 * This way, we will see "pku" in cpuinfo, but not
548 * "ospke", which is exactly what we want. It shows
549 * that the CPU has PKU, but the OS has not enabled it.
550 * This happens to be exactly how a system would look
551 * if we disabled the config option.
553 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
557 __setup("nopku", setup_disable_pku
);
560 #ifdef CONFIG_X86_KERNEL_IBT
562 __noendbr u64
ibt_save(bool disable
)
566 if (cpu_feature_enabled(X86_FEATURE_IBT
)) {
567 rdmsrl(MSR_IA32_S_CET
, msr
);
569 wrmsrl(MSR_IA32_S_CET
, msr
& ~CET_ENDBR_EN
);
575 __noendbr
void ibt_restore(u64 save
)
579 if (cpu_feature_enabled(X86_FEATURE_IBT
)) {
580 rdmsrl(MSR_IA32_S_CET
, msr
);
581 msr
&= ~CET_ENDBR_EN
;
582 msr
|= (save
& CET_ENDBR_EN
);
583 wrmsrl(MSR_IA32_S_CET
, msr
);
589 static __always_inline
void setup_cet(struct cpuinfo_x86
*c
)
591 bool user_shstk
, kernel_ibt
;
593 if (!IS_ENABLED(CONFIG_X86_CET
))
596 kernel_ibt
= HAS_KERNEL_IBT
&& cpu_feature_enabled(X86_FEATURE_IBT
);
597 user_shstk
= cpu_feature_enabled(X86_FEATURE_SHSTK
) &&
598 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK
);
600 if (!kernel_ibt
&& !user_shstk
)
604 set_cpu_cap(c
, X86_FEATURE_USER_SHSTK
);
607 wrmsrl(MSR_IA32_S_CET
, CET_ENDBR_EN
);
609 wrmsrl(MSR_IA32_S_CET
, 0);
611 cr4_set_bits(X86_CR4_CET
);
613 if (kernel_ibt
&& ibt_selftest()) {
614 pr_err("IBT selftest: Failed!\n");
615 wrmsrl(MSR_IA32_S_CET
, 0);
616 setup_clear_cpu_cap(X86_FEATURE_IBT
);
620 __noendbr
void cet_disable(void)
622 if (!(cpu_feature_enabled(X86_FEATURE_IBT
) ||
623 cpu_feature_enabled(X86_FEATURE_SHSTK
)))
626 wrmsrl(MSR_IA32_S_CET
, 0);
627 wrmsrl(MSR_IA32_U_CET
, 0);
631 * Some CPU features depend on higher CPUID levels, which may not always
632 * be available due to CPUID level capping or broken virtualization
633 * software. Add those features to this table to auto-disable them.
635 struct cpuid_dependent_feature
{
640 static const struct cpuid_dependent_feature
641 cpuid_dependent_features
[] = {
642 { X86_FEATURE_MWAIT
, 0x00000005 },
643 { X86_FEATURE_DCA
, 0x00000009 },
644 { X86_FEATURE_XSAVE
, 0x0000000d },
648 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
650 const struct cpuid_dependent_feature
*df
;
652 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
654 if (!cpu_has(c
, df
->feature
))
657 * Note: cpuid_level is set to -1 if unavailable, but
658 * extended_extended_level is set to 0 if unavailable
659 * and the legitimate extended levels are all negative
660 * when signed; hence the weird messing around with
663 if (!((s32
)df
->level
< 0 ?
664 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
665 (s32
)df
->level
> (s32
)c
->cpuid_level
))
668 clear_cpu_cap(c
, df
->feature
);
672 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
673 x86_cap_flag(df
->feature
), df
->level
);
678 * Naming convention should be: <Name> [(<Codename>)]
679 * This table only is used unless init_<vendor>() below doesn't set it;
680 * in particular, if CPUID levels 0x80000002..4 are supported, this
684 /* Look up CPU names by table lookup. */
685 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
688 const struct legacy_cpu_model_info
*info
;
690 if (c
->x86_model
>= 16)
691 return NULL
; /* Range check */
696 info
= this_cpu
->legacy_models
;
698 while (info
->family
) {
699 if (info
->family
== c
->x86
)
700 return info
->model_names
[c
->x86_model
];
704 return NULL
; /* Not found */
707 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
708 __u32 cpu_caps_cleared
[NCAPINTS
+ NBUGINTS
] __aligned(sizeof(unsigned long));
709 __u32 cpu_caps_set
[NCAPINTS
+ NBUGINTS
] __aligned(sizeof(unsigned long));
712 /* The 32-bit entry code needs to find cpu_entry_area. */
713 DEFINE_PER_CPU(struct cpu_entry_area
*, cpu_entry_area
);
716 /* Load the original GDT from the per-cpu structure */
717 void load_direct_gdt(int cpu
)
719 struct desc_ptr gdt_descr
;
721 gdt_descr
.address
= (long)get_cpu_gdt_rw(cpu
);
722 gdt_descr
.size
= GDT_SIZE
- 1;
723 load_gdt(&gdt_descr
);
725 EXPORT_SYMBOL_GPL(load_direct_gdt
);
727 /* Load a fixmap remapping of the per-cpu GDT */
728 void load_fixmap_gdt(int cpu
)
730 struct desc_ptr gdt_descr
;
732 gdt_descr
.address
= (long)get_cpu_gdt_ro(cpu
);
733 gdt_descr
.size
= GDT_SIZE
- 1;
734 load_gdt(&gdt_descr
);
736 EXPORT_SYMBOL_GPL(load_fixmap_gdt
);
739 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
740 * @cpu: The CPU number for which this is invoked
742 * Invoked during early boot to switch from early GDT and early per CPU to
743 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
744 * switch is implicit by loading the direct GDT. On 64bit this requires
747 void __init
switch_gdt_and_percpu_base(int cpu
)
749 load_direct_gdt(cpu
);
753 * No need to load %gs. It is already correct.
755 * Writing %gs on 64bit would zero GSBASE which would make any per
756 * CPU operation up to the point of the wrmsrl() fault.
758 * Set GSBASE to the new offset. Until the wrmsrl() happens the
759 * early mapping is still valid. That means the GSBASE update will
760 * lose any prior per CPU data which was not copied over in
761 * setup_per_cpu_areas().
763 * This works even with stackprotector enabled because the
764 * per CPU stack canary is 0 in both per CPU areas.
766 wrmsrl(MSR_GS_BASE
, cpu_kernelmode_gs_base(cpu
));
769 * %fs is already set to __KERNEL_PERCPU, but after switching GDT
770 * it is required to load FS again so that the 'hidden' part is
771 * updated from the new GDT. Up to this point the early per CPU
772 * translation is active. Any content of the early per CPU data
773 * which was not copied over in setup_per_cpu_areas() is lost.
775 loadsegment(fs
, __KERNEL_PERCPU
);
779 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
781 static void get_model_name(struct cpuinfo_x86
*c
)
786 if (c
->extended_cpuid_level
< 0x80000004)
789 v
= (unsigned int *)c
->x86_model_id
;
790 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
791 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
792 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
793 c
->x86_model_id
[48] = 0;
795 /* Trim whitespace */
796 p
= q
= s
= &c
->x86_model_id
[0];
802 /* Note the last non-whitespace index */
812 void detect_num_cpu_cores(struct cpuinfo_x86
*c
)
814 unsigned int eax
, ebx
, ecx
, edx
;
816 c
->x86_max_cores
= 1;
817 if (!IS_ENABLED(CONFIG_SMP
) || c
->cpuid_level
< 4)
820 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
822 c
->x86_max_cores
= (eax
>> 26) + 1;
825 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
827 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
829 n
= c
->extended_cpuid_level
;
831 if (n
>= 0x80000005) {
832 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
833 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
835 /* On K8 L1 TLB is inclusive, so don't count it */
840 if (n
< 0x80000006) /* Some chips just has a large L1. */
843 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
847 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
849 /* do processor-specific cache resizing */
850 if (this_cpu
->legacy_cache_size
)
851 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
853 /* Allow user to override all this if necessary. */
854 if (cachesize_override
!= -1)
855 l2size
= cachesize_override
;
858 return; /* Again, no L2 cache is possible */
861 c
->x86_cache_size
= l2size
;
864 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
865 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
866 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
867 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
868 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
869 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
870 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
872 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
874 if (this_cpu
->c_detect_tlb
)
875 this_cpu
->c_detect_tlb(c
);
877 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
878 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
879 tlb_lli_4m
[ENTRIES
]);
881 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
882 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
883 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
886 int detect_ht_early(struct cpuinfo_x86
*c
)
889 u32 eax
, ebx
, ecx
, edx
;
891 if (!cpu_has(c
, X86_FEATURE_HT
))
894 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
897 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
900 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
902 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
903 if (smp_num_siblings
== 1)
904 pr_info_once("CPU0: Hyper-Threading is disabled\n");
909 void detect_ht(struct cpuinfo_x86
*c
)
912 int index_msb
, core_bits
;
914 if (detect_ht_early(c
) < 0)
917 index_msb
= get_count_order(smp_num_siblings
);
918 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
920 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
922 index_msb
= get_count_order(smp_num_siblings
);
924 core_bits
= get_count_order(c
->x86_max_cores
);
926 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
927 ((1 << core_bits
) - 1);
931 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
933 char *v
= c
->x86_vendor_id
;
936 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
940 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
941 (cpu_devs
[i
]->c_ident
[1] &&
942 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
944 this_cpu
= cpu_devs
[i
];
945 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
950 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
951 "CPU: Your system may be unstable.\n", v
);
953 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
954 this_cpu
= &default_cpu
;
957 void cpu_detect(struct cpuinfo_x86
*c
)
959 /* Get vendor name */
960 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
961 (unsigned int *)&c
->x86_vendor_id
[0],
962 (unsigned int *)&c
->x86_vendor_id
[8],
963 (unsigned int *)&c
->x86_vendor_id
[4]);
966 /* Intel-defined flags: level 0x00000001 */
967 if (c
->cpuid_level
>= 0x00000001) {
968 u32 junk
, tfms
, cap0
, misc
;
970 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
971 c
->x86
= x86_family(tfms
);
972 c
->x86_model
= x86_model(tfms
);
973 c
->x86_stepping
= x86_stepping(tfms
);
975 if (cap0
& (1<<19)) {
976 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
977 c
->x86_cache_alignment
= c
->x86_clflush_size
;
982 static void apply_forced_caps(struct cpuinfo_x86
*c
)
986 for (i
= 0; i
< NCAPINTS
+ NBUGINTS
; i
++) {
987 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
988 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
992 static void init_speculation_control(struct cpuinfo_x86
*c
)
995 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
996 * and they also have a different bit for STIBP support. Also,
997 * a hypervisor might have set the individual AMD bits even on
998 * Intel CPUs, for finer-grained selection of what's available.
1000 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL
)) {
1001 set_cpu_cap(c
, X86_FEATURE_IBRS
);
1002 set_cpu_cap(c
, X86_FEATURE_IBPB
);
1003 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
1006 if (cpu_has(c
, X86_FEATURE_INTEL_STIBP
))
1007 set_cpu_cap(c
, X86_FEATURE_STIBP
);
1009 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL_SSBD
) ||
1010 cpu_has(c
, X86_FEATURE_VIRT_SSBD
))
1011 set_cpu_cap(c
, X86_FEATURE_SSBD
);
1013 if (cpu_has(c
, X86_FEATURE_AMD_IBRS
)) {
1014 set_cpu_cap(c
, X86_FEATURE_IBRS
);
1015 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
1018 if (cpu_has(c
, X86_FEATURE_AMD_IBPB
))
1019 set_cpu_cap(c
, X86_FEATURE_IBPB
);
1021 if (cpu_has(c
, X86_FEATURE_AMD_STIBP
)) {
1022 set_cpu_cap(c
, X86_FEATURE_STIBP
);
1023 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
1026 if (cpu_has(c
, X86_FEATURE_AMD_SSBD
)) {
1027 set_cpu_cap(c
, X86_FEATURE_SSBD
);
1028 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
1029 clear_cpu_cap(c
, X86_FEATURE_VIRT_SSBD
);
1033 void get_cpu_cap(struct cpuinfo_x86
*c
)
1035 u32 eax
, ebx
, ecx
, edx
;
1037 /* Intel-defined flags: level 0x00000001 */
1038 if (c
->cpuid_level
>= 0x00000001) {
1039 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
1041 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
1042 c
->x86_capability
[CPUID_1_EDX
] = edx
;
1045 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
1046 if (c
->cpuid_level
>= 0x00000006)
1047 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
1049 /* Additional Intel-defined flags: level 0x00000007 */
1050 if (c
->cpuid_level
>= 0x00000007) {
1051 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
1052 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
1053 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
1054 c
->x86_capability
[CPUID_7_EDX
] = edx
;
1056 /* Check valid sub-leaf index before accessing it */
1058 cpuid_count(0x00000007, 1, &eax
, &ebx
, &ecx
, &edx
);
1059 c
->x86_capability
[CPUID_7_1_EAX
] = eax
;
1063 /* Extended state features: level 0x0000000d */
1064 if (c
->cpuid_level
>= 0x0000000d) {
1065 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
1067 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
1070 /* AMD-defined flags: level 0x80000001 */
1071 eax
= cpuid_eax(0x80000000);
1072 c
->extended_cpuid_level
= eax
;
1074 if ((eax
& 0xffff0000) == 0x80000000) {
1075 if (eax
>= 0x80000001) {
1076 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
1078 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
1079 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
1083 if (c
->extended_cpuid_level
>= 0x80000007) {
1084 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
1086 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
1090 if (c
->extended_cpuid_level
>= 0x80000008) {
1091 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
1092 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
1095 if (c
->extended_cpuid_level
>= 0x8000000a)
1096 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
1098 if (c
->extended_cpuid_level
>= 0x8000001f)
1099 c
->x86_capability
[CPUID_8000_001F_EAX
] = cpuid_eax(0x8000001f);
1101 if (c
->extended_cpuid_level
>= 0x80000021)
1102 c
->x86_capability
[CPUID_8000_0021_EAX
] = cpuid_eax(0x80000021);
1104 init_scattered_cpuid_features(c
);
1105 init_speculation_control(c
);
1108 * Clear/Set all flags overridden by options, after probe.
1109 * This needs to happen each time we re-probe, which may happen
1110 * several times during CPU initialization.
1112 apply_forced_caps(c
);
1115 void get_cpu_address_sizes(struct cpuinfo_x86
*c
)
1117 u32 eax
, ebx
, ecx
, edx
;
1119 if (c
->extended_cpuid_level
>= 0x80000008) {
1120 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
1122 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
1123 c
->x86_phys_bits
= eax
& 0xff;
1125 #ifdef CONFIG_X86_32
1126 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
1127 c
->x86_phys_bits
= 36;
1129 c
->x86_cache_bits
= c
->x86_phys_bits
;
1132 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
1134 #ifdef CONFIG_X86_32
1138 * First of all, decide if this is a 486 or higher
1139 * It's a 486 if we can modify the AC flag
1141 if (flag_is_changeable_p(X86_EFLAGS_AC
))
1146 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
1147 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
1148 c
->x86_vendor_id
[0] = 0;
1149 cpu_devs
[i
]->c_identify(c
);
1150 if (c
->x86_vendor_id
[0]) {
1158 #define NO_SPECULATION BIT(0)
1159 #define NO_MELTDOWN BIT(1)
1160 #define NO_SSB BIT(2)
1161 #define NO_L1TF BIT(3)
1162 #define NO_MDS BIT(4)
1163 #define MSBDS_ONLY BIT(5)
1164 #define NO_SWAPGS BIT(6)
1165 #define NO_ITLB_MULTIHIT BIT(7)
1166 #define NO_SPECTRE_V2 BIT(8)
1167 #define NO_MMIO BIT(9)
1168 #define NO_EIBRS_PBRSB BIT(10)
1170 #define VULNWL(vendor, family, model, whitelist) \
1171 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1173 #define VULNWL_INTEL(model, whitelist) \
1174 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1176 #define VULNWL_AMD(family, whitelist) \
1177 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1179 #define VULNWL_HYGON(family, whitelist) \
1180 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1182 static const __initconst
struct x86_cpu_id cpu_vuln_whitelist
[] = {
1183 VULNWL(ANY
, 4, X86_MODEL_ANY
, NO_SPECULATION
),
1184 VULNWL(CENTAUR
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1185 VULNWL(INTEL
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1186 VULNWL(NSC
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1187 VULNWL(VORTEX
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1188 VULNWL(VORTEX
, 6, X86_MODEL_ANY
, NO_SPECULATION
),
1190 /* Intel Family 6 */
1191 VULNWL_INTEL(TIGERLAKE
, NO_MMIO
),
1192 VULNWL_INTEL(TIGERLAKE_L
, NO_MMIO
),
1193 VULNWL_INTEL(ALDERLAKE
, NO_MMIO
),
1194 VULNWL_INTEL(ALDERLAKE_L
, NO_MMIO
),
1196 VULNWL_INTEL(ATOM_SALTWELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1197 VULNWL_INTEL(ATOM_SALTWELL_TABLET
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1198 VULNWL_INTEL(ATOM_SALTWELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1199 VULNWL_INTEL(ATOM_BONNELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1200 VULNWL_INTEL(ATOM_BONNELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
1202 VULNWL_INTEL(ATOM_SILVERMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1203 VULNWL_INTEL(ATOM_SILVERMONT_D
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1204 VULNWL_INTEL(ATOM_SILVERMONT_MID
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1205 VULNWL_INTEL(ATOM_AIRMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1206 VULNWL_INTEL(XEON_PHI_KNL
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1207 VULNWL_INTEL(XEON_PHI_KNM
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1209 VULNWL_INTEL(CORE_YONAH
, NO_SSB
),
1211 VULNWL_INTEL(ATOM_AIRMONT_MID
, NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1212 VULNWL_INTEL(ATOM_AIRMONT_NP
, NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
1214 VULNWL_INTEL(ATOM_GOLDMONT
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
| NO_MMIO
),
1215 VULNWL_INTEL(ATOM_GOLDMONT_D
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
| NO_MMIO
),
1216 VULNWL_INTEL(ATOM_GOLDMONT_PLUS
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
| NO_MMIO
| NO_EIBRS_PBRSB
),
1219 * Technically, swapgs isn't serializing on AMD (despite it previously
1220 * being documented as such in the APM). But according to AMD, %gs is
1221 * updated non-speculatively, and the issuing of %gs-relative memory
1222 * operands will be blocked until the %gs update completes, which is
1223 * good enough for our purposes.
1226 VULNWL_INTEL(ATOM_TREMONT
, NO_EIBRS_PBRSB
),
1227 VULNWL_INTEL(ATOM_TREMONT_L
, NO_EIBRS_PBRSB
),
1228 VULNWL_INTEL(ATOM_TREMONT_D
, NO_ITLB_MULTIHIT
| NO_EIBRS_PBRSB
),
1230 /* AMD Family 0xf - 0x12 */
1231 VULNWL_AMD(0x0f, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
| NO_MMIO
),
1232 VULNWL_AMD(0x10, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
| NO_MMIO
),
1233 VULNWL_AMD(0x11, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
| NO_MMIO
),
1234 VULNWL_AMD(0x12, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
| NO_MMIO
),
1236 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1237 VULNWL_AMD(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
| NO_MMIO
| NO_EIBRS_PBRSB
),
1238 VULNWL_HYGON(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
| NO_MMIO
| NO_EIBRS_PBRSB
),
1240 /* Zhaoxin Family 7 */
1241 VULNWL(CENTAUR
, 7, X86_MODEL_ANY
, NO_SPECTRE_V2
| NO_SWAPGS
| NO_MMIO
),
1242 VULNWL(ZHAOXIN
, 7, X86_MODEL_ANY
, NO_SPECTRE_V2
| NO_SWAPGS
| NO_MMIO
),
1246 #define VULNBL(vendor, family, model, blacklist) \
1247 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1249 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1250 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1251 INTEL_FAM6_##model, steppings, \
1252 X86_FEATURE_ANY, issues)
1254 #define VULNBL_AMD(family, blacklist) \
1255 VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1257 #define VULNBL_HYGON(family, blacklist) \
1258 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1260 #define SRBDS BIT(0)
1261 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1263 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1264 #define MMIO_SBDS BIT(2)
1265 /* CPU is affected by RETbleed, speculating where you would not expect it */
1266 #define RETBLEED BIT(3)
1267 /* CPU is affected by SMT (cross-thread) return predictions */
1268 #define SMT_RSB BIT(4)
1270 static const struct x86_cpu_id cpu_vuln_blacklist
[] __initconst
= {
1271 VULNBL_INTEL_STEPPINGS(IVYBRIDGE
, X86_STEPPING_ANY
, SRBDS
),
1272 VULNBL_INTEL_STEPPINGS(HASWELL
, X86_STEPPING_ANY
, SRBDS
),
1273 VULNBL_INTEL_STEPPINGS(HASWELL_L
, X86_STEPPING_ANY
, SRBDS
),
1274 VULNBL_INTEL_STEPPINGS(HASWELL_G
, X86_STEPPING_ANY
, SRBDS
),
1275 VULNBL_INTEL_STEPPINGS(HASWELL_X
, X86_STEPPING_ANY
, MMIO
),
1276 VULNBL_INTEL_STEPPINGS(BROADWELL_D
, X86_STEPPING_ANY
, MMIO
),
1277 VULNBL_INTEL_STEPPINGS(BROADWELL_G
, X86_STEPPING_ANY
, SRBDS
),
1278 VULNBL_INTEL_STEPPINGS(BROADWELL_X
, X86_STEPPING_ANY
, MMIO
),
1279 VULNBL_INTEL_STEPPINGS(BROADWELL
, X86_STEPPING_ANY
, SRBDS
),
1280 VULNBL_INTEL_STEPPINGS(SKYLAKE_L
, X86_STEPPING_ANY
, SRBDS
| MMIO
| RETBLEED
),
1281 VULNBL_INTEL_STEPPINGS(SKYLAKE_X
, X86_STEPPING_ANY
, MMIO
| RETBLEED
),
1282 VULNBL_INTEL_STEPPINGS(SKYLAKE
, X86_STEPPING_ANY
, SRBDS
| MMIO
| RETBLEED
),
1283 VULNBL_INTEL_STEPPINGS(KABYLAKE_L
, X86_STEPPING_ANY
, SRBDS
| MMIO
| RETBLEED
),
1284 VULNBL_INTEL_STEPPINGS(KABYLAKE
, X86_STEPPING_ANY
, SRBDS
| MMIO
| RETBLEED
),
1285 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L
, X86_STEPPING_ANY
, RETBLEED
),
1286 VULNBL_INTEL_STEPPINGS(ICELAKE_L
, X86_STEPPING_ANY
, MMIO
| MMIO_SBDS
| RETBLEED
),
1287 VULNBL_INTEL_STEPPINGS(ICELAKE_D
, X86_STEPPING_ANY
, MMIO
),
1288 VULNBL_INTEL_STEPPINGS(ICELAKE_X
, X86_STEPPING_ANY
, MMIO
),
1289 VULNBL_INTEL_STEPPINGS(COMETLAKE
, X86_STEPPING_ANY
, MMIO
| MMIO_SBDS
| RETBLEED
),
1290 VULNBL_INTEL_STEPPINGS(COMETLAKE_L
, X86_STEPPINGS(0x0, 0x0), MMIO
| RETBLEED
),
1291 VULNBL_INTEL_STEPPINGS(COMETLAKE_L
, X86_STEPPING_ANY
, MMIO
| MMIO_SBDS
| RETBLEED
),
1292 VULNBL_INTEL_STEPPINGS(LAKEFIELD
, X86_STEPPING_ANY
, MMIO
| MMIO_SBDS
| RETBLEED
),
1293 VULNBL_INTEL_STEPPINGS(ROCKETLAKE
, X86_STEPPING_ANY
, MMIO
| RETBLEED
),
1294 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT
, X86_STEPPING_ANY
, MMIO
| MMIO_SBDS
),
1295 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D
, X86_STEPPING_ANY
, MMIO
),
1296 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L
, X86_STEPPING_ANY
, MMIO
| MMIO_SBDS
),
1298 VULNBL_AMD(0x15, RETBLEED
),
1299 VULNBL_AMD(0x16, RETBLEED
),
1300 VULNBL_AMD(0x17, RETBLEED
| SMT_RSB
),
1301 VULNBL_HYGON(0x18, RETBLEED
| SMT_RSB
),
1305 static bool __init
cpu_matches(const struct x86_cpu_id
*table
, unsigned long which
)
1307 const struct x86_cpu_id
*m
= x86_match_cpu(table
);
1309 return m
&& !!(m
->driver_data
& which
);
1312 u64
x86_read_arch_cap_msr(void)
1316 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
))
1317 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, ia32_cap
);
1322 static bool arch_cap_mmio_immune(u64 ia32_cap
)
1324 return (ia32_cap
& ARCH_CAP_FBSDP_NO
&&
1325 ia32_cap
& ARCH_CAP_PSDP_NO
&&
1326 ia32_cap
& ARCH_CAP_SBDR_SSDP_NO
);
1329 static void __init
cpu_set_bug_bits(struct cpuinfo_x86
*c
)
1331 u64 ia32_cap
= x86_read_arch_cap_msr();
1333 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1334 if (!cpu_matches(cpu_vuln_whitelist
, NO_ITLB_MULTIHIT
) &&
1335 !(ia32_cap
& ARCH_CAP_PSCHANGE_MC_NO
))
1336 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT
);
1338 if (cpu_matches(cpu_vuln_whitelist
, NO_SPECULATION
))
1341 setup_force_cpu_bug(X86_BUG_SPECTRE_V1
);
1343 if (!cpu_matches(cpu_vuln_whitelist
, NO_SPECTRE_V2
))
1344 setup_force_cpu_bug(X86_BUG_SPECTRE_V2
);
1346 if (!cpu_matches(cpu_vuln_whitelist
, NO_SSB
) &&
1347 !(ia32_cap
& ARCH_CAP_SSB_NO
) &&
1348 !cpu_has(c
, X86_FEATURE_AMD_SSB_NO
))
1349 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS
);
1352 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
1353 * flag and protect from vendor-specific bugs via the whitelist.
1355 if ((ia32_cap
& ARCH_CAP_IBRS_ALL
) || cpu_has(c
, X86_FEATURE_AUTOIBRS
)) {
1356 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED
);
1357 if (!cpu_matches(cpu_vuln_whitelist
, NO_EIBRS_PBRSB
) &&
1358 !(ia32_cap
& ARCH_CAP_PBRSB_NO
))
1359 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB
);
1362 if (!cpu_matches(cpu_vuln_whitelist
, NO_MDS
) &&
1363 !(ia32_cap
& ARCH_CAP_MDS_NO
)) {
1364 setup_force_cpu_bug(X86_BUG_MDS
);
1365 if (cpu_matches(cpu_vuln_whitelist
, MSBDS_ONLY
))
1366 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY
);
1369 if (!cpu_matches(cpu_vuln_whitelist
, NO_SWAPGS
))
1370 setup_force_cpu_bug(X86_BUG_SWAPGS
);
1373 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1374 * - TSX is supported or
1375 * - TSX_CTRL is present
1377 * TSX_CTRL check is needed for cases when TSX could be disabled before
1378 * the kernel boot e.g. kexec.
1379 * TSX_CTRL check alone is not sufficient for cases when the microcode
1380 * update is not present or running as guest that don't get TSX_CTRL.
1382 if (!(ia32_cap
& ARCH_CAP_TAA_NO
) &&
1383 (cpu_has(c
, X86_FEATURE_RTM
) ||
1384 (ia32_cap
& ARCH_CAP_TSX_CTRL_MSR
)))
1385 setup_force_cpu_bug(X86_BUG_TAA
);
1388 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1389 * in the vulnerability blacklist.
1391 * Some of the implications and mitigation of Shared Buffers Data
1392 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1395 if ((cpu_has(c
, X86_FEATURE_RDRAND
) ||
1396 cpu_has(c
, X86_FEATURE_RDSEED
)) &&
1397 cpu_matches(cpu_vuln_blacklist
, SRBDS
| MMIO_SBDS
))
1398 setup_force_cpu_bug(X86_BUG_SRBDS
);
1401 * Processor MMIO Stale Data bug enumeration
1403 * Affected CPU list is generally enough to enumerate the vulnerability,
1404 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1405 * not want the guest to enumerate the bug.
1407 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1408 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1410 if (!arch_cap_mmio_immune(ia32_cap
)) {
1411 if (cpu_matches(cpu_vuln_blacklist
, MMIO
))
1412 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA
);
1413 else if (!cpu_matches(cpu_vuln_whitelist
, NO_MMIO
))
1414 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN
);
1417 if (!cpu_has(c
, X86_FEATURE_BTC_NO
)) {
1418 if (cpu_matches(cpu_vuln_blacklist
, RETBLEED
) || (ia32_cap
& ARCH_CAP_RSBA
))
1419 setup_force_cpu_bug(X86_BUG_RETBLEED
);
1422 if (cpu_matches(cpu_vuln_blacklist
, SMT_RSB
))
1423 setup_force_cpu_bug(X86_BUG_SMT_RSB
);
1425 if (cpu_matches(cpu_vuln_whitelist
, NO_MELTDOWN
))
1428 /* Rogue Data Cache Load? No! */
1429 if (ia32_cap
& ARCH_CAP_RDCL_NO
)
1432 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN
);
1434 if (cpu_matches(cpu_vuln_whitelist
, NO_L1TF
))
1437 setup_force_cpu_bug(X86_BUG_L1TF
);
1441 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1442 * unfortunately, that's not true in practice because of early VIA
1443 * chips and (more importantly) broken virtualizers that are not easy
1444 * to detect. In the latter case it doesn't even *fail* reliably, so
1445 * probing for it doesn't even work. Disable it completely on 32-bit
1446 * unless we can find a reliable way to detect all the broken cases.
1447 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1449 static void detect_nopl(void)
1451 #ifdef CONFIG_X86_32
1452 setup_clear_cpu_cap(X86_FEATURE_NOPL
);
1454 setup_force_cpu_cap(X86_FEATURE_NOPL
);
1459 * We parse cpu parameters early because fpu__init_system() is executed
1460 * before parse_early_param().
1462 static void __init
cpu_parse_early_param(void)
1465 char *argptr
= arg
, *opt
;
1466 int arglen
, taint
= 0;
1468 #ifdef CONFIG_X86_32
1469 if (cmdline_find_option_bool(boot_command_line
, "no387"))
1470 #ifdef CONFIG_MATH_EMULATION
1471 setup_clear_cpu_cap(X86_FEATURE_FPU
);
1473 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1476 if (cmdline_find_option_bool(boot_command_line
, "nofxsr"))
1477 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
1480 if (cmdline_find_option_bool(boot_command_line
, "noxsave"))
1481 setup_clear_cpu_cap(X86_FEATURE_XSAVE
);
1483 if (cmdline_find_option_bool(boot_command_line
, "noxsaveopt"))
1484 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT
);
1486 if (cmdline_find_option_bool(boot_command_line
, "noxsaves"))
1487 setup_clear_cpu_cap(X86_FEATURE_XSAVES
);
1489 if (cmdline_find_option_bool(boot_command_line
, "nousershstk"))
1490 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK
);
1492 arglen
= cmdline_find_option(boot_command_line
, "clearcpuid", arg
, sizeof(arg
));
1496 pr_info("Clearing CPUID bits:");
1499 bool found __maybe_unused
= false;
1502 opt
= strsep(&argptr
, ",");
1505 * Handle naked numbers first for feature flags which don't
1508 if (!kstrtouint(opt
, 10, &bit
)) {
1509 if (bit
< NCAPINTS
* 32) {
1511 /* empty-string, i.e., ""-defined feature flags */
1512 if (!x86_cap_flags
[bit
])
1513 pr_cont(" " X86_CAP_FMT_NUM
, x86_cap_flag_num(bit
));
1515 pr_cont(" " X86_CAP_FMT
, x86_cap_flag(bit
));
1517 setup_clear_cpu_cap(bit
);
1521 * The assumption is that there are no feature names with only
1522 * numbers in the name thus go to the next argument.
1527 for (bit
= 0; bit
< 32 * NCAPINTS
; bit
++) {
1528 if (!x86_cap_flag(bit
))
1531 if (strcmp(x86_cap_flag(bit
), opt
))
1534 pr_cont(" %s", opt
);
1535 setup_clear_cpu_cap(bit
);
1542 pr_cont(" (unknown: %s)", opt
);
1547 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_STILL_OK
);
1551 * Do minimum CPU detection early.
1552 * Fields really needed: vendor, cpuid_level, family, model, mask,
1554 * The others are not touched to avoid unwanted side effects.
1556 * WARNING: this function is only called on the boot CPU. Don't add code
1557 * here that is supposed to run on all CPUs.
1559 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
1561 #ifdef CONFIG_X86_64
1562 c
->x86_clflush_size
= 64;
1563 c
->x86_phys_bits
= 36;
1564 c
->x86_virt_bits
= 48;
1566 c
->x86_clflush_size
= 32;
1567 c
->x86_phys_bits
= 32;
1568 c
->x86_virt_bits
= 32;
1570 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1572 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1573 c
->extended_cpuid_level
= 0;
1575 if (!have_cpuid_p())
1576 identify_cpu_without_cpuid(c
);
1578 /* cyrix could have cpuid enabled via c_identify()*/
1579 if (have_cpuid_p()) {
1583 get_cpu_address_sizes(c
);
1584 setup_force_cpu_cap(X86_FEATURE_CPUID
);
1585 cpu_parse_early_param();
1587 if (this_cpu
->c_early_init
)
1588 this_cpu
->c_early_init(c
);
1591 filter_cpuid_features(c
, false);
1593 if (this_cpu
->c_bsp_init
)
1594 this_cpu
->c_bsp_init(c
);
1596 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
1599 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
1601 cpu_set_bug_bits(c
);
1605 #ifdef CONFIG_X86_32
1607 * Regardless of whether PCID is enumerated, the SDM says
1608 * that it can't be enabled in 32-bit mode.
1610 setup_clear_cpu_cap(X86_FEATURE_PCID
);
1614 * Later in the boot process pgtable_l5_enabled() relies on
1615 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1616 * enabled by this point we need to clear the feature bit to avoid
1617 * false-positives at the later stage.
1619 * pgtable_l5_enabled() can be false here for several reasons:
1620 * - 5-level paging is disabled compile-time;
1621 * - it's 32-bit kernel;
1622 * - machine doesn't support 5-level paging;
1623 * - user specified 'no5lvl' in kernel command line.
1625 if (!pgtable_l5_enabled())
1626 setup_clear_cpu_cap(X86_FEATURE_LA57
);
1631 void __init
early_cpu_init(void)
1633 const struct cpu_dev
*const *cdev
;
1636 #ifdef CONFIG_PROCESSOR_SELECT
1637 pr_info("KERNEL supported cpus:\n");
1640 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
1641 const struct cpu_dev
*cpudev
= *cdev
;
1643 if (count
>= X86_VENDOR_NUM
)
1645 cpu_devs
[count
] = cpudev
;
1648 #ifdef CONFIG_PROCESSOR_SELECT
1652 for (j
= 0; j
< 2; j
++) {
1653 if (!cpudev
->c_ident
[j
])
1655 pr_info(" %s %s\n", cpudev
->c_vendor
,
1656 cpudev
->c_ident
[j
]);
1661 early_identify_cpu(&boot_cpu_data
);
1664 static bool detect_null_seg_behavior(void)
1667 * Empirically, writing zero to a segment selector on AMD does
1668 * not clear the base, whereas writing zero to a segment
1669 * selector on Intel does clear the base. Intel's behavior
1670 * allows slightly faster context switches in the common case
1671 * where GS is unused by the prev and next threads.
1673 * Since neither vendor documents this anywhere that I can see,
1674 * detect it directly instead of hard-coding the choice by
1677 * I've designated AMD's behavior as the "bug" because it's
1678 * counterintuitive and less friendly.
1681 unsigned long old_base
, tmp
;
1682 rdmsrl(MSR_FS_BASE
, old_base
);
1683 wrmsrl(MSR_FS_BASE
, 1);
1685 rdmsrl(MSR_FS_BASE
, tmp
);
1686 wrmsrl(MSR_FS_BASE
, old_base
);
1690 void check_null_seg_clears_base(struct cpuinfo_x86
*c
)
1692 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1693 if (!IS_ENABLED(CONFIG_X86_64
))
1696 if (cpu_has(c
, X86_FEATURE_NULL_SEL_CLR_BASE
))
1700 * CPUID bit above wasn't set. If this kernel is still running
1701 * as a HV guest, then the HV has decided not to advertize
1702 * that CPUID bit for whatever reason. For example, one
1703 * member of the migration pool might be vulnerable. Which
1704 * means, the bug is present: set the BUG flag and return.
1706 if (cpu_has(c
, X86_FEATURE_HYPERVISOR
)) {
1707 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
1712 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1713 * 0x18 is the respective family for Hygon.
1715 if ((c
->x86
== 0x17 || c
->x86
== 0x18) &&
1716 detect_null_seg_behavior())
1719 /* All the remaining ones are affected */
1720 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
1723 static void generic_identify(struct cpuinfo_x86
*c
)
1725 c
->extended_cpuid_level
= 0;
1727 if (!have_cpuid_p())
1728 identify_cpu_without_cpuid(c
);
1730 /* cyrix could have cpuid enabled via c_identify()*/
1731 if (!have_cpuid_p())
1740 get_cpu_address_sizes(c
);
1742 if (c
->cpuid_level
>= 0x00000001) {
1743 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
1744 #ifdef CONFIG_X86_32
1746 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1748 c
->apicid
= c
->initial_apicid
;
1751 c
->phys_proc_id
= c
->initial_apicid
;
1754 get_model_name(c
); /* Default name */
1757 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1758 * systems that run Linux at CPL > 0 may or may not have the
1759 * issue, but, even if they have the issue, there's absolutely
1760 * nothing we can do about it because we can't use the real IRET
1763 * NB: For the time being, only 32-bit kernels support
1764 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1765 * whether to apply espfix using paravirt hooks. If any
1766 * non-paravirt system ever shows up that does *not* have the
1767 * ESPFIX issue, we can change this.
1769 #ifdef CONFIG_X86_32
1770 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1775 * Validate that ACPI/mptables have the same information about the
1776 * effective APIC id and update the package map.
1778 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1781 unsigned int apicid
, cpu
= smp_processor_id();
1783 apicid
= apic
->cpu_present_to_apicid(cpu
);
1785 if (apicid
!= c
->apicid
) {
1786 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1787 cpu
, apicid
, c
->initial_apicid
);
1789 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1790 BUG_ON(topology_update_die_map(c
->cpu_die_id
, cpu
));
1792 c
->logical_proc_id
= 0;
1797 * This does the hard work of actually picking apart the CPU stuff...
1799 static void identify_cpu(struct cpuinfo_x86
*c
)
1803 c
->loops_per_jiffy
= loops_per_jiffy
;
1804 c
->x86_cache_size
= 0;
1805 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1806 c
->x86_model
= c
->x86_stepping
= 0; /* So far unknown... */
1807 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1808 c
->x86_model_id
[0] = '\0'; /* Unset */
1809 c
->x86_max_cores
= 1;
1810 c
->x86_coreid_bits
= 0;
1812 #ifdef CONFIG_X86_64
1813 c
->x86_clflush_size
= 64;
1814 c
->x86_phys_bits
= 36;
1815 c
->x86_virt_bits
= 48;
1817 c
->cpuid_level
= -1; /* CPUID not detected */
1818 c
->x86_clflush_size
= 32;
1819 c
->x86_phys_bits
= 32;
1820 c
->x86_virt_bits
= 32;
1822 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1823 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1824 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1825 memset(&c
->vmx_capability
, 0, sizeof(c
->vmx_capability
));
1828 generic_identify(c
);
1830 if (this_cpu
->c_identify
)
1831 this_cpu
->c_identify(c
);
1833 /* Clear/Set all flags overridden by options, after probe */
1834 apply_forced_caps(c
);
1836 #ifdef CONFIG_X86_64
1837 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1841 * Vendor-specific initialization. In this section we
1842 * canonicalize the feature flags, meaning if there are
1843 * features a certain CPU supports which CPUID doesn't
1844 * tell us, CPUID claiming incorrect flags, or other bugs,
1845 * we handle them here.
1847 * At the end of this section, c->x86_capability better
1848 * indicate the features this CPU genuinely supports!
1850 if (this_cpu
->c_init
)
1851 this_cpu
->c_init(c
);
1853 /* Disable the PN if appropriate */
1854 squash_the_stupid_serial_number(c
);
1856 /* Set up SMEP/SMAP/UMIP */
1861 /* Enable FSGSBASE instructions if available. */
1862 if (cpu_has(c
, X86_FEATURE_FSGSBASE
)) {
1863 cr4_set_bits(X86_CR4_FSGSBASE
);
1864 elf_hwcap2
|= HWCAP2_FSGSBASE
;
1868 * The vendor-specific functions might have changed features.
1869 * Now we do "generic changes."
1872 /* Filter out anything that depends on CPUID levels we don't have */
1873 filter_cpuid_features(c
, true);
1875 /* If the model name is still unset, do table lookup. */
1876 if (!c
->x86_model_id
[0]) {
1878 p
= table_lookup_model(c
);
1880 strcpy(c
->x86_model_id
, p
);
1882 /* Last resort... */
1883 sprintf(c
->x86_model_id
, "%02x/%02x",
1884 c
->x86
, c
->x86_model
);
1887 #ifdef CONFIG_X86_64
1896 * Clear/Set all flags overridden by options, need do it
1897 * before following smp all cpus cap AND.
1899 apply_forced_caps(c
);
1902 * On SMP, boot_cpu_data holds the common feature set between
1903 * all CPUs; so make sure that we indicate which features are
1904 * common between the CPUs. The first time this routine gets
1905 * executed, c == &boot_cpu_data.
1907 if (c
!= &boot_cpu_data
) {
1908 /* AND the already accumulated flags with these */
1909 for (i
= 0; i
< NCAPINTS
; i
++)
1910 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1912 /* OR, i.e. replicate the bug flags */
1913 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1914 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1919 /* Init Machine Check Exception if available. */
1922 select_idle_routine(c
);
1925 numa_add_cpu(smp_processor_id());
1930 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1931 * on 32-bit kernels:
1933 #ifdef CONFIG_X86_32
1934 void enable_sep_cpu(void)
1936 struct tss_struct
*tss
;
1939 if (!boot_cpu_has(X86_FEATURE_SEP
))
1943 tss
= &per_cpu(cpu_tss_rw
, cpu
);
1946 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1947 * see the big comment in struct x86_hw_tss's definition.
1950 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1951 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1952 wrmsr(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1), 0);
1953 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1959 void __init
identify_boot_cpu(void)
1961 identify_cpu(&boot_cpu_data
);
1962 if (HAS_KERNEL_IBT
&& cpu_feature_enabled(X86_FEATURE_IBT
))
1963 pr_info("CET detected: Indirect Branch Tracking enabled\n");
1964 #ifdef CONFIG_X86_32
1967 cpu_detect_tlb(&boot_cpu_data
);
1974 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1976 BUG_ON(c
== &boot_cpu_data
);
1978 #ifdef CONFIG_X86_32
1981 validate_apic_and_package_id(c
);
1982 x86_spec_ctrl_setup_ap();
1988 void print_cpu_info(struct cpuinfo_x86
*c
)
1990 const char *vendor
= NULL
;
1992 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1993 vendor
= this_cpu
->c_vendor
;
1995 if (c
->cpuid_level
>= 0)
1996 vendor
= c
->x86_vendor_id
;
1999 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
2000 pr_cont("%s ", vendor
);
2002 if (c
->x86_model_id
[0])
2003 pr_cont("%s", c
->x86_model_id
);
2005 pr_cont("%d86", c
->x86
);
2007 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
2009 if (c
->x86_stepping
|| c
->cpuid_level
>= 0)
2010 pr_cont(", stepping: 0x%x)\n", c
->x86_stepping
);
2016 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
2017 * function prevents it from becoming an environment variable for init.
2019 static __init
int setup_clearcpuid(char *arg
)
2023 __setup("clearcpuid=", setup_clearcpuid
);
2025 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot
, pcpu_hot
) = {
2026 .current_task
= &init_task
,
2027 .preempt_count
= INIT_PREEMPT_COUNT
,
2028 .top_of_stack
= TOP_OF_INIT_STACK
,
2030 EXPORT_PER_CPU_SYMBOL(pcpu_hot
);
2032 #ifdef CONFIG_X86_64
2033 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data
,
2034 fixed_percpu_data
) __aligned(PAGE_SIZE
) __visible
;
2035 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data
);
2037 static void wrmsrl_cstar(unsigned long val
)
2040 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
2041 * is so far ignored by the CPU, but raises a #VE trap in a TDX
2042 * guest. Avoid the pointless write on all Intel CPUs.
2044 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
2045 wrmsrl(MSR_CSTAR
, val
);
2048 /* May not be marked __init: used by software suspend */
2049 void syscall_init(void)
2051 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
2052 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
2054 #ifdef CONFIG_IA32_EMULATION
2055 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat
);
2057 * This only works on Intel CPUs.
2058 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
2059 * This does not cause SYSENTER to jump to the wrong location, because
2060 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
2062 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
2063 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
,
2064 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
2065 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
2067 wrmsrl_cstar((unsigned long)ignore_sysret
);
2068 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
2069 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
2070 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
2074 * Flags to clear on syscall; clear as much as possible
2075 * to minimize user space-kernel interference.
2077 wrmsrl(MSR_SYSCALL_MASK
,
2078 X86_EFLAGS_CF
|X86_EFLAGS_PF
|X86_EFLAGS_AF
|
2079 X86_EFLAGS_ZF
|X86_EFLAGS_SF
|X86_EFLAGS_TF
|
2080 X86_EFLAGS_IF
|X86_EFLAGS_DF
|X86_EFLAGS_OF
|
2081 X86_EFLAGS_IOPL
|X86_EFLAGS_NT
|X86_EFLAGS_RF
|
2082 X86_EFLAGS_AC
|X86_EFLAGS_ID
);
2085 #else /* CONFIG_X86_64 */
2087 #ifdef CONFIG_STACKPROTECTOR
2088 DEFINE_PER_CPU(unsigned long, __stack_chk_guard
);
2089 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard
);
2092 #endif /* CONFIG_X86_64 */
2095 * Clear all 6 debug registers:
2097 static void clear_all_debug_regs(void)
2101 for (i
= 0; i
< 8; i
++) {
2102 /* Ignore db4, db5 */
2103 if ((i
== 4) || (i
== 5))
2112 * Restore debug regs if using kgdbwait and you have a kernel debugger
2113 * connection established.
2115 static void dbg_restore_debug_regs(void)
2117 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
2118 arch_kgdb_ops
.correct_hw_break();
2120 #else /* ! CONFIG_KGDB */
2121 #define dbg_restore_debug_regs()
2122 #endif /* ! CONFIG_KGDB */
2124 static inline void setup_getcpu(int cpu
)
2126 unsigned long cpudata
= vdso_encode_cpunode(cpu
, early_cpu_to_node(cpu
));
2127 struct desc_struct d
= { };
2129 if (boot_cpu_has(X86_FEATURE_RDTSCP
) || boot_cpu_has(X86_FEATURE_RDPID
))
2130 wrmsr(MSR_TSC_AUX
, cpudata
, 0);
2132 /* Store CPU and node number in limit. */
2134 d
.limit1
= cpudata
>> 16;
2136 d
.type
= 5; /* RO data, expand down, accessed */
2137 d
.dpl
= 3; /* Visible to user code */
2138 d
.s
= 1; /* Not a system segment */
2139 d
.p
= 1; /* Present */
2140 d
.d
= 1; /* 32-bit */
2142 write_gdt_entry(get_cpu_gdt_rw(cpu
), GDT_ENTRY_CPUNODE
, &d
, DESCTYPE_S
);
2145 #ifdef CONFIG_X86_64
2146 static inline void ucode_cpu_init(int cpu
) { }
2148 static inline void tss_setup_ist(struct tss_struct
*tss
)
2150 /* Set up the per-CPU TSS IST stacks */
2151 tss
->x86_tss
.ist
[IST_INDEX_DF
] = __this_cpu_ist_top_va(DF
);
2152 tss
->x86_tss
.ist
[IST_INDEX_NMI
] = __this_cpu_ist_top_va(NMI
);
2153 tss
->x86_tss
.ist
[IST_INDEX_DB
] = __this_cpu_ist_top_va(DB
);
2154 tss
->x86_tss
.ist
[IST_INDEX_MCE
] = __this_cpu_ist_top_va(MCE
);
2155 /* Only mapped when SEV-ES is active */
2156 tss
->x86_tss
.ist
[IST_INDEX_VC
] = __this_cpu_ist_top_va(VC
);
2159 #else /* CONFIG_X86_64 */
2161 static inline void ucode_cpu_init(int cpu
)
2163 show_ucode_info_early();
2166 static inline void tss_setup_ist(struct tss_struct
*tss
) { }
2168 #endif /* !CONFIG_X86_64 */
2170 static inline void tss_setup_io_bitmap(struct tss_struct
*tss
)
2172 tss
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET_INVALID
;
2174 #ifdef CONFIG_X86_IOPL_IOPERM
2175 tss
->io_bitmap
.prev_max
= 0;
2176 tss
->io_bitmap
.prev_sequence
= 0;
2177 memset(tss
->io_bitmap
.bitmap
, 0xff, sizeof(tss
->io_bitmap
.bitmap
));
2179 * Invalidate the extra array entry past the end of the all
2180 * permission bitmap as required by the hardware.
2182 tss
->io_bitmap
.mapall
[IO_BITMAP_LONGS
] = ~0UL;
2187 * Setup everything needed to handle exceptions from the IDT, including the IST
2188 * exceptions which use paranoid_entry().
2190 void cpu_init_exception_handling(void)
2192 struct tss_struct
*tss
= this_cpu_ptr(&cpu_tss_rw
);
2193 int cpu
= raw_smp_processor_id();
2195 /* paranoid_entry() gets the CPU number from the GDT */
2198 /* IST vectors need TSS to be set up. */
2200 tss_setup_io_bitmap(tss
);
2201 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
2205 /* GHCB needs to be setup to handle #VC. */
2208 /* Finally load the IDT */
2213 * cpu_init() initializes state that is per-CPU. Some data is already
2214 * initialized (naturally) in the bootstrap process, such as the GDT. We
2215 * reload it nevertheless, this function acts as a 'CPU state barrier',
2216 * nothing should get across.
2220 struct task_struct
*cur
= current
;
2221 int cpu
= raw_smp_processor_id();
2223 ucode_cpu_init(cpu
);
2226 if (this_cpu_read(numa_node
) == 0 &&
2227 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
2228 set_numa_node(early_cpu_to_node(cpu
));
2230 pr_debug("Initializing CPU#%d\n", cpu
);
2232 if (IS_ENABLED(CONFIG_X86_64
) || cpu_feature_enabled(X86_FEATURE_VME
) ||
2233 boot_cpu_has(X86_FEATURE_TSC
) || boot_cpu_has(X86_FEATURE_DE
))
2234 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
2236 if (IS_ENABLED(CONFIG_X86_64
)) {
2238 memset(cur
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
2241 wrmsrl(MSR_FS_BASE
, 0);
2242 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
2249 cur
->active_mm
= &init_mm
;
2251 initialize_tlbstate_and_flush();
2252 enter_lazy_tlb(&init_mm
, cur
);
2255 * sp0 points to the entry trampoline stack regardless of what task
2258 load_sp0((unsigned long)(cpu_entry_stack(cpu
) + 1));
2260 load_mm_ldt(&init_mm
);
2262 clear_all_debug_regs();
2263 dbg_restore_debug_regs();
2265 doublefault_init_cpu_tss();
2270 load_fixmap_gdt(cpu
);
2273 #ifdef CONFIG_MICROCODE_LATE_LOADING
2275 * store_cpu_caps() - Store a snapshot of CPU capabilities
2276 * @curr_info: Pointer where to store it
2280 void store_cpu_caps(struct cpuinfo_x86
*curr_info
)
2282 /* Reload CPUID max function as it might've changed. */
2283 curr_info
->cpuid_level
= cpuid_eax(0);
2285 /* Copy all capability leafs and pick up the synthetic ones. */
2286 memcpy(&curr_info
->x86_capability
, &boot_cpu_data
.x86_capability
,
2287 sizeof(curr_info
->x86_capability
));
2289 /* Get the hardware CPUID leafs */
2290 get_cpu_cap(curr_info
);
2294 * microcode_check() - Check if any CPU capabilities changed after an update.
2295 * @prev_info: CPU capabilities stored before an update.
2297 * The microcode loader calls this upon late microcode load to recheck features,
2298 * only when microcode has been updated. Caller holds microcode_mutex and CPU
2303 void microcode_check(struct cpuinfo_x86
*prev_info
)
2305 struct cpuinfo_x86 curr_info
;
2307 perf_check_microcode();
2309 store_cpu_caps(&curr_info
);
2311 if (!memcmp(&prev_info
->x86_capability
, &curr_info
.x86_capability
,
2312 sizeof(prev_info
->x86_capability
)))
2315 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2316 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2321 * Invoked from core CPU hotplug code after hotplug operations
2323 void arch_smt_update(void)
2325 /* Handle the speculative execution misfeatures */
2326 cpu_bugs_smt_update();
2327 /* Check whether IPI broadcasting can be enabled */
2331 void __init
arch_cpu_finalize_init(void)
2333 identify_boot_cpu();
2336 * identify_boot_cpu() initialized SMT support information, let the
2339 cpu_smt_check_topology();
2341 if (!IS_ENABLED(CONFIG_SMP
)) {
2343 print_cpu_info(&boot_cpu_data
);
2346 cpu_select_mitigations();
2350 if (IS_ENABLED(CONFIG_X86_32
)) {
2352 * Check whether this is a real i386 which is not longer
2353 * supported and fixup the utsname.
2355 if (boot_cpu_data
.x86
< 4)
2356 panic("Kernel requires i486+ for 'invlpg' and other features");
2358 init_utsname()->machine
[1] =
2359 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
2363 * Must be before alternatives because it might set or clear
2369 alternative_instructions();
2371 if (IS_ENABLED(CONFIG_X86_64
)) {
2373 * Make sure the first 2MB area is not mapped by huge pages
2374 * There are typically fixed size MTRRs in there and overlapping
2375 * MTRRs into large pages causes slow downs.
2377 * Right now we don't do that with gbpages because there seems
2378 * very little benefit for that case.
2380 if (!direct_gbpages
)
2381 set_memory_4k((unsigned long)__va(0), 1);
2383 fpu__init_check_bugs();
2387 * This needs to be called before any devices perform DMA
2388 * operations that might use the SWIOTLB bounce buffers. It will
2389 * mark the bounce buffers as decrypted so that their usage will
2390 * not cause "plain-text" data to be decrypted when accessed. It
2391 * must be called after late_time_init() so that Hyper-V x86/x64
2392 * hypercalls work when the SWIOTLB bounce buffers are decrypted.