2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "dc/inc/core_types.h"
32 #include "dal_asic_id.h"
33 #include "dmub/dmub_srv.h"
34 #include "dc/inc/hw/dmcu.h"
35 #include "dc/inc/hw/abm.h"
36 #include "dc/dc_dmub_srv.h"
40 #include "amdgpu_display.h"
41 #include "amdgpu_ucode.h"
43 #include "amdgpu_dm.h"
44 #ifdef CONFIG_DRM_AMD_DC_HDCP
45 #include "amdgpu_dm_hdcp.h"
46 #include <drm/drm_hdcp.h>
48 #include "amdgpu_pm.h"
50 #include "amd_shared.h"
51 #include "amdgpu_dm_irq.h"
52 #include "dm_helpers.h"
53 #include "amdgpu_dm_mst_types.h"
54 #if defined(CONFIG_DEBUG_FS)
55 #include "amdgpu_dm_debugfs.h"
58 #include "ivsrcid/ivsrcid_vislands30.h"
60 #include <linux/module.h>
61 #include <linux/moduleparam.h>
62 #include <linux/version.h>
63 #include <linux/types.h>
64 #include <linux/pm_runtime.h>
65 #include <linux/pci.h>
66 #include <linux/firmware.h>
67 #include <linux/component.h>
69 #include <drm/drm_atomic.h>
70 #include <drm/drm_atomic_uapi.h>
71 #include <drm/drm_atomic_helper.h>
72 #include <drm/drm_dp_mst_helper.h>
73 #include <drm/drm_fb_helper.h>
74 #include <drm/drm_fourcc.h>
75 #include <drm/drm_edid.h>
76 #include <drm/drm_vblank.h>
77 #include <drm/drm_audio_component.h>
78 #include <drm/drm_hdcp.h>
80 #if defined(CONFIG_DRM_AMD_DC_DCN)
81 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
83 #include "dcn/dcn_1_0_offset.h"
84 #include "dcn/dcn_1_0_sh_mask.h"
85 #include "soc15_hw_ip.h"
86 #include "vega10_ip_offset.h"
88 #include "soc15_common.h"
91 #include "modules/inc/mod_freesync.h"
92 #include "modules/power/power_helpers.h"
93 #include "modules/inc/mod_info_packet.h"
95 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
96 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB
);
98 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
99 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU
);
101 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
102 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU
);
104 /* Number of bytes in PSP header for firmware. */
105 #define PSP_HEADER_BYTES 0x100
107 /* Number of bytes in PSP footer for firmware. */
108 #define PSP_FOOTER_BYTES 0x100
113 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
114 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
115 * requests into DC requests, and DC responses into DRM responses.
117 * The root control structure is &struct amdgpu_display_manager.
120 /* basic init/fini API */
121 static int amdgpu_dm_init(struct amdgpu_device
*adev
);
122 static void amdgpu_dm_fini(struct amdgpu_device
*adev
);
125 * initializes drm_device display related structures, based on the information
126 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
127 * drm_encoder, drm_mode_config
129 * Returns 0 on success
131 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device
*adev
);
132 /* removes and deallocates the drm structures, created by the above function */
133 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager
*dm
);
135 static int amdgpu_dm_plane_init(struct amdgpu_display_manager
*dm
,
136 struct drm_plane
*plane
,
137 unsigned long possible_crtcs
,
138 const struct dc_plane_cap
*plane_cap
);
139 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager
*dm
,
140 struct drm_plane
*plane
,
141 uint32_t link_index
);
142 static int amdgpu_dm_connector_init(struct amdgpu_display_manager
*dm
,
143 struct amdgpu_dm_connector
*amdgpu_dm_connector
,
145 struct amdgpu_encoder
*amdgpu_encoder
);
146 static int amdgpu_dm_encoder_init(struct drm_device
*dev
,
147 struct amdgpu_encoder
*aencoder
,
148 uint32_t link_index
);
150 static int amdgpu_dm_connector_get_modes(struct drm_connector
*connector
);
152 static int amdgpu_dm_atomic_commit(struct drm_device
*dev
,
153 struct drm_atomic_state
*state
,
156 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state
*state
);
158 static int amdgpu_dm_atomic_check(struct drm_device
*dev
,
159 struct drm_atomic_state
*state
);
161 static void handle_cursor_update(struct drm_plane
*plane
,
162 struct drm_plane_state
*old_plane_state
);
164 static void amdgpu_dm_set_psr_caps(struct dc_link
*link
);
165 static bool amdgpu_dm_psr_enable(struct dc_stream_state
*stream
);
166 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state
*stream
);
167 static bool amdgpu_dm_psr_disable(struct dc_stream_state
*stream
);
171 * dm_vblank_get_counter
174 * Get counter for number of vertical blanks
177 * struct amdgpu_device *adev - [in] desired amdgpu device
178 * int disp_idx - [in] which CRTC to get the counter from
181 * Counter for vertical blanks
183 static u32
dm_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
185 if (crtc
>= adev
->mode_info
.num_crtc
)
188 struct amdgpu_crtc
*acrtc
= adev
->mode_info
.crtcs
[crtc
];
189 struct dm_crtc_state
*acrtc_state
= to_dm_crtc_state(
193 if (acrtc_state
->stream
== NULL
) {
194 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
199 return dc_stream_get_vblank_counter(acrtc_state
->stream
);
203 static int dm_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
204 u32
*vbl
, u32
*position
)
206 uint32_t v_blank_start
, v_blank_end
, h_position
, v_position
;
208 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
211 struct amdgpu_crtc
*acrtc
= adev
->mode_info
.crtcs
[crtc
];
212 struct dm_crtc_state
*acrtc_state
= to_dm_crtc_state(
215 if (acrtc_state
->stream
== NULL
) {
216 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
222 * TODO rework base driver to use values directly.
223 * for now parse it back into reg-format
225 dc_stream_get_scanoutpos(acrtc_state
->stream
,
231 *position
= v_position
| (h_position
<< 16);
232 *vbl
= v_blank_start
| (v_blank_end
<< 16);
238 static bool dm_is_idle(void *handle
)
244 static int dm_wait_for_idle(void *handle
)
250 static bool dm_check_soft_reset(void *handle
)
255 static int dm_soft_reset(void *handle
)
261 static struct amdgpu_crtc
*
262 get_crtc_by_otg_inst(struct amdgpu_device
*adev
,
265 struct drm_device
*dev
= adev
->ddev
;
266 struct drm_crtc
*crtc
;
267 struct amdgpu_crtc
*amdgpu_crtc
;
269 if (otg_inst
== -1) {
271 return adev
->mode_info
.crtcs
[0];
274 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
275 amdgpu_crtc
= to_amdgpu_crtc(crtc
);
277 if (amdgpu_crtc
->otg_inst
== otg_inst
)
284 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state
*dm_state
)
286 return dm_state
->freesync_config
.state
== VRR_STATE_ACTIVE_VARIABLE
||
287 dm_state
->freesync_config
.state
== VRR_STATE_ACTIVE_FIXED
;
291 * dm_pflip_high_irq() - Handle pageflip interrupt
292 * @interrupt_params: ignored
294 * Handles the pageflip interrupt by notifying all interested parties
295 * that the pageflip has been completed.
297 static void dm_pflip_high_irq(void *interrupt_params
)
299 struct amdgpu_crtc
*amdgpu_crtc
;
300 struct common_irq_params
*irq_params
= interrupt_params
;
301 struct amdgpu_device
*adev
= irq_params
->adev
;
303 struct drm_pending_vblank_event
*e
;
304 struct dm_crtc_state
*acrtc_state
;
305 uint32_t vpos
, hpos
, v_blank_start
, v_blank_end
;
308 amdgpu_crtc
= get_crtc_by_otg_inst(adev
, irq_params
->irq_src
- IRQ_TYPE_PFLIP
);
310 /* IRQ could occur when in initial stage */
311 /* TODO work and BO cleanup */
312 if (amdgpu_crtc
== NULL
) {
313 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
317 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
319 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
){
320 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
321 amdgpu_crtc
->pflip_status
,
322 AMDGPU_FLIP_SUBMITTED
,
323 amdgpu_crtc
->crtc_id
,
325 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
329 /* page flip completed. */
330 e
= amdgpu_crtc
->event
;
331 amdgpu_crtc
->event
= NULL
;
336 acrtc_state
= to_dm_crtc_state(amdgpu_crtc
->base
.state
);
337 vrr_active
= amdgpu_dm_vrr_active(acrtc_state
);
339 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
341 !dc_stream_get_scanoutpos(acrtc_state
->stream
, &v_blank_start
,
342 &v_blank_end
, &hpos
, &vpos
) ||
343 (vpos
< v_blank_start
)) {
344 /* Update to correct count and vblank timestamp if racing with
345 * vblank irq. This also updates to the correct vblank timestamp
346 * even in VRR mode, as scanout is past the front-porch atm.
348 drm_crtc_accurate_vblank_count(&amdgpu_crtc
->base
);
350 /* Wake up userspace by sending the pageflip event with proper
351 * count and timestamp of vblank of flip completion.
354 drm_crtc_send_vblank_event(&amdgpu_crtc
->base
, e
);
356 /* Event sent, so done with vblank for this flip */
357 drm_crtc_vblank_put(&amdgpu_crtc
->base
);
360 /* VRR active and inside front-porch: vblank count and
361 * timestamp for pageflip event will only be up to date after
362 * drm_crtc_handle_vblank() has been executed from late vblank
363 * irq handler after start of back-porch (vline 0). We queue the
364 * pageflip event for send-out by drm_crtc_handle_vblank() with
365 * updated timestamp and count, once it runs after us.
367 * We need to open-code this instead of using the helper
368 * drm_crtc_arm_vblank_event(), as that helper would
369 * call drm_crtc_accurate_vblank_count(), which we must
370 * not call in VRR mode while we are in front-porch!
373 /* sequence will be replaced by real count during send-out. */
374 e
->sequence
= drm_crtc_vblank_count(&amdgpu_crtc
->base
);
375 e
->pipe
= amdgpu_crtc
->crtc_id
;
377 list_add_tail(&e
->base
.link
, &adev
->ddev
->vblank_event_list
);
381 /* Keep track of vblank of this flip for flip throttling. We use the
382 * cooked hw counter, as that one incremented at start of this vblank
383 * of pageflip completion, so last_flip_vblank is the forbidden count
384 * for queueing new pageflips if vsync + VRR is enabled.
386 amdgpu_crtc
->last_flip_vblank
=
387 amdgpu_get_vblank_counter_kms(&amdgpu_crtc
->base
);
389 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
390 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
392 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
393 amdgpu_crtc
->crtc_id
, amdgpu_crtc
,
394 vrr_active
, (int) !e
);
397 static void dm_vupdate_high_irq(void *interrupt_params
)
399 struct common_irq_params
*irq_params
= interrupt_params
;
400 struct amdgpu_device
*adev
= irq_params
->adev
;
401 struct amdgpu_crtc
*acrtc
;
402 struct dm_crtc_state
*acrtc_state
;
405 acrtc
= get_crtc_by_otg_inst(adev
, irq_params
->irq_src
- IRQ_TYPE_VUPDATE
);
408 acrtc_state
= to_dm_crtc_state(acrtc
->base
.state
);
410 DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d\n",
412 amdgpu_dm_vrr_active(acrtc_state
));
414 /* Core vblank handling is done here after end of front-porch in
415 * vrr mode, as vblank timestamping will give valid results
416 * while now done after front-porch. This will also deliver
417 * page-flip completion events that have been queued to us
418 * if a pageflip happened inside front-porch.
420 if (amdgpu_dm_vrr_active(acrtc_state
)) {
421 drm_crtc_handle_vblank(&acrtc
->base
);
423 /* BTR processing for pre-DCE12 ASICs */
424 if (acrtc_state
->stream
&&
425 adev
->family
< AMDGPU_FAMILY_AI
) {
426 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
427 mod_freesync_handle_v_update(
428 adev
->dm
.freesync_module
,
430 &acrtc_state
->vrr_params
);
432 dc_stream_adjust_vmin_vmax(
435 &acrtc_state
->vrr_params
.adjust
);
436 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
443 * dm_crtc_high_irq() - Handles CRTC interrupt
444 * @interrupt_params: used for determining the CRTC instance
446 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
449 static void dm_crtc_high_irq(void *interrupt_params
)
451 struct common_irq_params
*irq_params
= interrupt_params
;
452 struct amdgpu_device
*adev
= irq_params
->adev
;
453 struct amdgpu_crtc
*acrtc
;
454 struct dm_crtc_state
*acrtc_state
;
457 acrtc
= get_crtc_by_otg_inst(adev
, irq_params
->irq_src
- IRQ_TYPE_VBLANK
);
461 acrtc_state
= to_dm_crtc_state(acrtc
->base
.state
);
463 DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc
->crtc_id
,
464 amdgpu_dm_vrr_active(acrtc_state
),
465 acrtc_state
->active_planes
);
468 * Core vblank handling at start of front-porch is only possible
469 * in non-vrr mode, as only there vblank timestamping will give
470 * valid results while done in front-porch. Otherwise defer it
471 * to dm_vupdate_high_irq after end of front-porch.
473 if (!amdgpu_dm_vrr_active(acrtc_state
))
474 drm_crtc_handle_vblank(&acrtc
->base
);
477 * Following stuff must happen at start of vblank, for crc
478 * computation and below-the-range btr support in vrr mode.
480 amdgpu_dm_crtc_handle_crc_irq(&acrtc
->base
);
482 /* BTR updates need to happen before VUPDATE on Vega and above. */
483 if (adev
->family
< AMDGPU_FAMILY_AI
)
486 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
488 if (acrtc_state
->stream
&& acrtc_state
->vrr_params
.supported
&&
489 acrtc_state
->freesync_config
.state
== VRR_STATE_ACTIVE_VARIABLE
) {
490 mod_freesync_handle_v_update(adev
->dm
.freesync_module
,
492 &acrtc_state
->vrr_params
);
494 dc_stream_adjust_vmin_vmax(adev
->dm
.dc
, acrtc_state
->stream
,
495 &acrtc_state
->vrr_params
.adjust
);
499 * If there aren't any active_planes then DCH HUBP may be clock-gated.
500 * In that case, pageflip completion interrupts won't fire and pageflip
501 * completion events won't get delivered. Prevent this by sending
502 * pending pageflip events from here if a flip is still pending.
504 * If any planes are enabled, use dm_pflip_high_irq() instead, to
505 * avoid race conditions between flip programming and completion,
506 * which could cause too early flip completion events.
508 if (adev
->family
>= AMDGPU_FAMILY_RV
&&
509 acrtc
->pflip_status
== AMDGPU_FLIP_SUBMITTED
&&
510 acrtc_state
->active_planes
== 0) {
512 drm_crtc_send_vblank_event(&acrtc
->base
, acrtc
->event
);
514 drm_crtc_vblank_put(&acrtc
->base
);
516 acrtc
->pflip_status
= AMDGPU_FLIP_NONE
;
519 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
522 static int dm_set_clockgating_state(void *handle
,
523 enum amd_clockgating_state state
)
528 static int dm_set_powergating_state(void *handle
,
529 enum amd_powergating_state state
)
534 /* Prototypes of private functions */
535 static int dm_early_init(void* handle
);
537 /* Allocate memory for FBC compressed data */
538 static void amdgpu_dm_fbc_init(struct drm_connector
*connector
)
540 struct drm_device
*dev
= connector
->dev
;
541 struct amdgpu_device
*adev
= dev
->dev_private
;
542 struct dm_comressor_info
*compressor
= &adev
->dm
.compressor
;
543 struct amdgpu_dm_connector
*aconn
= to_amdgpu_dm_connector(connector
);
544 struct drm_display_mode
*mode
;
545 unsigned long max_size
= 0;
547 if (adev
->dm
.dc
->fbc_compressor
== NULL
)
550 if (aconn
->dc_link
->connector_signal
!= SIGNAL_TYPE_EDP
)
553 if (compressor
->bo_ptr
)
557 list_for_each_entry(mode
, &connector
->modes
, head
) {
558 if (max_size
< mode
->htotal
* mode
->vtotal
)
559 max_size
= mode
->htotal
* mode
->vtotal
;
563 int r
= amdgpu_bo_create_kernel(adev
, max_size
* 4, PAGE_SIZE
,
564 AMDGPU_GEM_DOMAIN_GTT
, &compressor
->bo_ptr
,
565 &compressor
->gpu_addr
, &compressor
->cpu_addr
);
568 DRM_ERROR("DM: Failed to initialize FBC\n");
570 adev
->dm
.dc
->ctx
->fbc_gpu_addr
= compressor
->gpu_addr
;
571 DRM_INFO("DM: FBC alloc %lu\n", max_size
*4);
578 static int amdgpu_dm_audio_component_get_eld(struct device
*kdev
, int port
,
579 int pipe
, bool *enabled
,
580 unsigned char *buf
, int max_bytes
)
582 struct drm_device
*dev
= dev_get_drvdata(kdev
);
583 struct amdgpu_device
*adev
= dev
->dev_private
;
584 struct drm_connector
*connector
;
585 struct drm_connector_list_iter conn_iter
;
586 struct amdgpu_dm_connector
*aconnector
;
591 mutex_lock(&adev
->dm
.audio_lock
);
593 drm_connector_list_iter_begin(dev
, &conn_iter
);
594 drm_for_each_connector_iter(connector
, &conn_iter
) {
595 aconnector
= to_amdgpu_dm_connector(connector
);
596 if (aconnector
->audio_inst
!= port
)
600 ret
= drm_eld_size(connector
->eld
);
601 memcpy(buf
, connector
->eld
, min(max_bytes
, ret
));
605 drm_connector_list_iter_end(&conn_iter
);
607 mutex_unlock(&adev
->dm
.audio_lock
);
609 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port
, ret
, *enabled
);
614 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops
= {
615 .get_eld
= amdgpu_dm_audio_component_get_eld
,
618 static int amdgpu_dm_audio_component_bind(struct device
*kdev
,
619 struct device
*hda_kdev
, void *data
)
621 struct drm_device
*dev
= dev_get_drvdata(kdev
);
622 struct amdgpu_device
*adev
= dev
->dev_private
;
623 struct drm_audio_component
*acomp
= data
;
625 acomp
->ops
= &amdgpu_dm_audio_component_ops
;
627 adev
->dm
.audio_component
= acomp
;
632 static void amdgpu_dm_audio_component_unbind(struct device
*kdev
,
633 struct device
*hda_kdev
, void *data
)
635 struct drm_device
*dev
= dev_get_drvdata(kdev
);
636 struct amdgpu_device
*adev
= dev
->dev_private
;
637 struct drm_audio_component
*acomp
= data
;
641 adev
->dm
.audio_component
= NULL
;
644 static const struct component_ops amdgpu_dm_audio_component_bind_ops
= {
645 .bind
= amdgpu_dm_audio_component_bind
,
646 .unbind
= amdgpu_dm_audio_component_unbind
,
649 static int amdgpu_dm_audio_init(struct amdgpu_device
*adev
)
656 adev
->mode_info
.audio
.enabled
= true;
658 adev
->mode_info
.audio
.num_pins
= adev
->dm
.dc
->res_pool
->audio_count
;
660 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
661 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
662 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
663 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
664 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
665 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
666 adev
->mode_info
.audio
.pin
[i
].connected
= false;
667 adev
->mode_info
.audio
.pin
[i
].id
=
668 adev
->dm
.dc
->res_pool
->audios
[i
]->inst
;
669 adev
->mode_info
.audio
.pin
[i
].offset
= 0;
672 ret
= component_add(adev
->dev
, &amdgpu_dm_audio_component_bind_ops
);
676 adev
->dm
.audio_registered
= true;
681 static void amdgpu_dm_audio_fini(struct amdgpu_device
*adev
)
686 if (!adev
->mode_info
.audio
.enabled
)
689 if (adev
->dm
.audio_registered
) {
690 component_del(adev
->dev
, &amdgpu_dm_audio_component_bind_ops
);
691 adev
->dm
.audio_registered
= false;
694 /* TODO: Disable audio? */
696 adev
->mode_info
.audio
.enabled
= false;
699 void amdgpu_dm_audio_eld_notify(struct amdgpu_device
*adev
, int pin
)
701 struct drm_audio_component
*acomp
= adev
->dm
.audio_component
;
703 if (acomp
&& acomp
->audio_ops
&& acomp
->audio_ops
->pin_eld_notify
) {
704 DRM_DEBUG_KMS("Notify ELD: %d\n", pin
);
706 acomp
->audio_ops
->pin_eld_notify(acomp
->audio_ops
->audio_ptr
,
711 static int dm_dmub_hw_init(struct amdgpu_device
*adev
)
713 const struct dmcub_firmware_header_v1_0
*hdr
;
714 struct dmub_srv
*dmub_srv
= adev
->dm
.dmub_srv
;
715 struct dmub_srv_fb_info
*fb_info
= adev
->dm
.dmub_fb_info
;
716 const struct firmware
*dmub_fw
= adev
->dm
.dmub_fw
;
717 struct dmcu
*dmcu
= adev
->dm
.dc
->res_pool
->dmcu
;
718 struct abm
*abm
= adev
->dm
.dc
->res_pool
->abm
;
719 struct dmub_srv_hw_params hw_params
;
720 enum dmub_status status
;
721 const unsigned char *fw_inst_const
, *fw_bss_data
;
722 uint32_t i
, fw_inst_const_size
, fw_bss_data_size
;
726 /* DMUB isn't supported on the ASIC. */
730 DRM_ERROR("No framebuffer info for DMUB service.\n");
735 /* Firmware required for DMUB support. */
736 DRM_ERROR("No firmware provided for DMUB.\n");
740 status
= dmub_srv_has_hw_support(dmub_srv
, &has_hw_support
);
741 if (status
!= DMUB_STATUS_OK
) {
742 DRM_ERROR("Error checking HW support for DMUB: %d\n", status
);
746 if (!has_hw_support
) {
747 DRM_INFO("DMUB unsupported on ASIC\n");
751 hdr
= (const struct dmcub_firmware_header_v1_0
*)dmub_fw
->data
;
753 fw_inst_const
= dmub_fw
->data
+
754 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
) +
757 fw_bss_data
= dmub_fw
->data
+
758 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
) +
759 le32_to_cpu(hdr
->inst_const_bytes
);
761 /* Copy firmware and bios info into FB memory. */
762 fw_inst_const_size
= le32_to_cpu(hdr
->inst_const_bytes
) -
763 PSP_HEADER_BYTES
- PSP_FOOTER_BYTES
;
765 fw_bss_data_size
= le32_to_cpu(hdr
->bss_data_bytes
);
767 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
768 * amdgpu_ucode_init_single_fw will load dmub firmware
769 * fw_inst_const part to cw0; otherwise, the firmware back door load
770 * will be done by dm_dmub_hw_init
772 if (adev
->firmware
.load_type
!= AMDGPU_FW_LOAD_PSP
) {
773 memcpy(fb_info
->fb
[DMUB_WINDOW_0_INST_CONST
].cpu_addr
, fw_inst_const
,
777 if (fw_bss_data_size
)
778 memcpy(fb_info
->fb
[DMUB_WINDOW_2_BSS_DATA
].cpu_addr
,
779 fw_bss_data
, fw_bss_data_size
);
781 /* Copy firmware bios info into FB memory. */
782 memcpy(fb_info
->fb
[DMUB_WINDOW_3_VBIOS
].cpu_addr
, adev
->bios
,
785 /* Reset regions that need to be reset. */
786 memset(fb_info
->fb
[DMUB_WINDOW_4_MAILBOX
].cpu_addr
, 0,
787 fb_info
->fb
[DMUB_WINDOW_4_MAILBOX
].size
);
789 memset(fb_info
->fb
[DMUB_WINDOW_5_TRACEBUFF
].cpu_addr
, 0,
790 fb_info
->fb
[DMUB_WINDOW_5_TRACEBUFF
].size
);
792 memset(fb_info
->fb
[DMUB_WINDOW_6_FW_STATE
].cpu_addr
, 0,
793 fb_info
->fb
[DMUB_WINDOW_6_FW_STATE
].size
);
795 /* Initialize hardware. */
796 memset(&hw_params
, 0, sizeof(hw_params
));
797 hw_params
.fb_base
= adev
->gmc
.fb_start
;
798 hw_params
.fb_offset
= adev
->gmc
.aper_base
;
800 /* backdoor load firmware and trigger dmub running */
801 if (adev
->firmware
.load_type
!= AMDGPU_FW_LOAD_PSP
)
802 hw_params
.load_inst_const
= true;
805 hw_params
.psp_version
= dmcu
->psp_version
;
807 for (i
= 0; i
< fb_info
->num_fb
; ++i
)
808 hw_params
.fb
[i
] = &fb_info
->fb
[i
];
810 status
= dmub_srv_hw_init(dmub_srv
, &hw_params
);
811 if (status
!= DMUB_STATUS_OK
) {
812 DRM_ERROR("Error initializing DMUB HW: %d\n", status
);
816 /* Wait for firmware load to finish. */
817 status
= dmub_srv_wait_for_auto_load(dmub_srv
, 100000);
818 if (status
!= DMUB_STATUS_OK
)
819 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status
);
821 /* Init DMCU and ABM if available. */
823 dmcu
->funcs
->dmcu_init(dmcu
);
824 abm
->dmcu_is_running
= dmcu
->funcs
->is_dmcu_initialized(dmcu
);
827 adev
->dm
.dc
->ctx
->dmub_srv
= dc_dmub_srv_create(adev
->dm
.dc
, dmub_srv
);
828 if (!adev
->dm
.dc
->ctx
->dmub_srv
) {
829 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
833 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
834 adev
->dm
.dmcub_fw_version
);
839 static int amdgpu_dm_init(struct amdgpu_device
*adev
)
841 struct dc_init_data init_data
;
842 #ifdef CONFIG_DRM_AMD_DC_HDCP
843 struct dc_callback_init init_params
;
847 adev
->dm
.ddev
= adev
->ddev
;
848 adev
->dm
.adev
= adev
;
850 /* Zero all the fields */
851 memset(&init_data
, 0, sizeof(init_data
));
852 #ifdef CONFIG_DRM_AMD_DC_HDCP
853 memset(&init_params
, 0, sizeof(init_params
));
856 mutex_init(&adev
->dm
.dc_lock
);
857 mutex_init(&adev
->dm
.audio_lock
);
859 if(amdgpu_dm_irq_init(adev
)) {
860 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
864 init_data
.asic_id
.chip_family
= adev
->family
;
866 init_data
.asic_id
.pci_revision_id
= adev
->pdev
->revision
;
867 init_data
.asic_id
.hw_internal_rev
= adev
->external_rev_id
;
869 init_data
.asic_id
.vram_width
= adev
->gmc
.vram_width
;
870 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
871 init_data
.asic_id
.atombios_base_address
=
872 adev
->mode_info
.atom_context
->bios
;
874 init_data
.driver
= adev
;
876 adev
->dm
.cgs_device
= amdgpu_cgs_create_device(adev
);
878 if (!adev
->dm
.cgs_device
) {
879 DRM_ERROR("amdgpu: failed to create cgs device.\n");
883 init_data
.cgs_device
= adev
->dm
.cgs_device
;
885 init_data
.dce_environment
= DCE_ENV_PRODUCTION_DRV
;
887 switch (adev
->asic_type
) {
892 init_data
.flags
.gpu_vm_support
= true;
898 if (amdgpu_dc_feature_mask
& DC_FBC_MASK
)
899 init_data
.flags
.fbc_support
= true;
901 if (amdgpu_dc_feature_mask
& DC_MULTI_MON_PP_MCLK_SWITCH_MASK
)
902 init_data
.flags
.multi_mon_pp_mclk_switch
= true;
904 if (amdgpu_dc_feature_mask
& DC_DISABLE_FRACTIONAL_PWM_MASK
)
905 init_data
.flags
.disable_fractional_pwm
= true;
907 init_data
.flags
.power_down_display_on_boot
= true;
909 init_data
.soc_bounding_box
= adev
->dm
.soc_bounding_box
;
911 /* Display Core create. */
912 adev
->dm
.dc
= dc_create(&init_data
);
915 DRM_INFO("Display Core initialized with v%s!\n", DC_VER
);
917 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER
);
921 if (amdgpu_dc_debug_mask
& DC_DISABLE_PIPE_SPLIT
) {
922 adev
->dm
.dc
->debug
.force_single_disp_pipe_split
= false;
923 adev
->dm
.dc
->debug
.pipe_split_policy
= MPC_SPLIT_AVOID
;
926 if (adev
->asic_type
!= CHIP_CARRIZO
&& adev
->asic_type
!= CHIP_STONEY
)
927 adev
->dm
.dc
->debug
.disable_stutter
= amdgpu_pp_feature_mask
& PP_STUTTER_MODE
? false : true;
929 if (amdgpu_dc_debug_mask
& DC_DISABLE_STUTTER
)
930 adev
->dm
.dc
->debug
.disable_stutter
= true;
932 if (amdgpu_dc_debug_mask
& DC_DISABLE_DSC
)
933 adev
->dm
.dc
->debug
.disable_dsc
= true;
935 if (amdgpu_dc_debug_mask
& DC_DISABLE_CLOCK_GATING
)
936 adev
->dm
.dc
->debug
.disable_clock_gate
= true;
938 r
= dm_dmub_hw_init(adev
);
940 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r
);
944 dc_hardware_init(adev
->dm
.dc
);
946 adev
->dm
.freesync_module
= mod_freesync_create(adev
->dm
.dc
);
947 if (!adev
->dm
.freesync_module
) {
949 "amdgpu: failed to initialize freesync_module.\n");
951 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
952 adev
->dm
.freesync_module
);
954 amdgpu_dm_init_color_mod();
956 #ifdef CONFIG_DRM_AMD_DC_HDCP
957 if (adev
->asic_type
>= CHIP_RAVEN
) {
958 adev
->dm
.hdcp_workqueue
= hdcp_create_workqueue(adev
, &init_params
.cp_psp
, adev
->dm
.dc
);
960 if (!adev
->dm
.hdcp_workqueue
)
961 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
963 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev
->dm
.hdcp_workqueue
);
965 dc_init_callbacks(adev
->dm
.dc
, &init_params
);
968 if (amdgpu_dm_initialize_drm_device(adev
)) {
970 "amdgpu: failed to initialize sw for display support.\n");
974 /* Update the actual used number of crtc */
975 adev
->mode_info
.num_crtc
= adev
->dm
.display_indexes_num
;
977 /* TODO: Add_display_info? */
979 /* TODO use dynamic cursor width */
980 adev
->ddev
->mode_config
.cursor_width
= adev
->dm
.dc
->caps
.max_cursor_size
;
981 adev
->ddev
->mode_config
.cursor_height
= adev
->dm
.dc
->caps
.max_cursor_size
;
983 if (drm_vblank_init(adev
->ddev
, adev
->dm
.display_indexes_num
)) {
985 "amdgpu: failed to initialize sw for display support.\n");
989 DRM_DEBUG_DRIVER("KMS initialized.\n");
993 amdgpu_dm_fini(adev
);
998 static void amdgpu_dm_fini(struct amdgpu_device
*adev
)
1000 amdgpu_dm_audio_fini(adev
);
1002 amdgpu_dm_destroy_drm_device(&adev
->dm
);
1004 #ifdef CONFIG_DRM_AMD_DC_HDCP
1005 if (adev
->dm
.hdcp_workqueue
) {
1006 hdcp_destroy(adev
->dm
.hdcp_workqueue
);
1007 adev
->dm
.hdcp_workqueue
= NULL
;
1011 dc_deinit_callbacks(adev
->dm
.dc
);
1013 if (adev
->dm
.dc
->ctx
->dmub_srv
) {
1014 dc_dmub_srv_destroy(&adev
->dm
.dc
->ctx
->dmub_srv
);
1015 adev
->dm
.dc
->ctx
->dmub_srv
= NULL
;
1018 if (adev
->dm
.dmub_bo
)
1019 amdgpu_bo_free_kernel(&adev
->dm
.dmub_bo
,
1020 &adev
->dm
.dmub_bo_gpu_addr
,
1021 &adev
->dm
.dmub_bo_cpu_addr
);
1023 /* DC Destroy TODO: Replace destroy DAL */
1025 dc_destroy(&adev
->dm
.dc
);
1027 * TODO: pageflip, vlank interrupt
1029 * amdgpu_dm_irq_fini(adev);
1032 if (adev
->dm
.cgs_device
) {
1033 amdgpu_cgs_destroy_device(adev
->dm
.cgs_device
);
1034 adev
->dm
.cgs_device
= NULL
;
1036 if (adev
->dm
.freesync_module
) {
1037 mod_freesync_destroy(adev
->dm
.freesync_module
);
1038 adev
->dm
.freesync_module
= NULL
;
1041 mutex_destroy(&adev
->dm
.audio_lock
);
1042 mutex_destroy(&adev
->dm
.dc_lock
);
1047 static int load_dmcu_fw(struct amdgpu_device
*adev
)
1049 const char *fw_name_dmcu
= NULL
;
1051 const struct dmcu_firmware_header_v1_0
*hdr
;
1053 switch(adev
->asic_type
) {
1063 case CHIP_POLARIS11
:
1064 case CHIP_POLARIS10
:
1065 case CHIP_POLARIS12
:
1075 fw_name_dmcu
= FIRMWARE_NAVI12_DMCU
;
1078 if (ASICREV_IS_PICASSO(adev
->external_rev_id
))
1079 fw_name_dmcu
= FIRMWARE_RAVEN_DMCU
;
1080 else if (ASICREV_IS_RAVEN2(adev
->external_rev_id
))
1081 fw_name_dmcu
= FIRMWARE_RAVEN_DMCU
;
1086 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev
->asic_type
);
1090 if (adev
->firmware
.load_type
!= AMDGPU_FW_LOAD_PSP
) {
1091 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1095 r
= request_firmware_direct(&adev
->dm
.fw_dmcu
, fw_name_dmcu
, adev
->dev
);
1097 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1098 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1099 adev
->dm
.fw_dmcu
= NULL
;
1103 dev_err(adev
->dev
, "amdgpu_dm: Can't load firmware \"%s\"\n",
1108 r
= amdgpu_ucode_validate(adev
->dm
.fw_dmcu
);
1110 dev_err(adev
->dev
, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1112 release_firmware(adev
->dm
.fw_dmcu
);
1113 adev
->dm
.fw_dmcu
= NULL
;
1117 hdr
= (const struct dmcu_firmware_header_v1_0
*)adev
->dm
.fw_dmcu
->data
;
1118 adev
->firmware
.ucode
[AMDGPU_UCODE_ID_DMCU_ERAM
].ucode_id
= AMDGPU_UCODE_ID_DMCU_ERAM
;
1119 adev
->firmware
.ucode
[AMDGPU_UCODE_ID_DMCU_ERAM
].fw
= adev
->dm
.fw_dmcu
;
1120 adev
->firmware
.fw_size
+=
1121 ALIGN(le32_to_cpu(hdr
->header
.ucode_size_bytes
) - le32_to_cpu(hdr
->intv_size_bytes
), PAGE_SIZE
);
1123 adev
->firmware
.ucode
[AMDGPU_UCODE_ID_DMCU_INTV
].ucode_id
= AMDGPU_UCODE_ID_DMCU_INTV
;
1124 adev
->firmware
.ucode
[AMDGPU_UCODE_ID_DMCU_INTV
].fw
= adev
->dm
.fw_dmcu
;
1125 adev
->firmware
.fw_size
+=
1126 ALIGN(le32_to_cpu(hdr
->intv_size_bytes
), PAGE_SIZE
);
1128 adev
->dm
.dmcu_fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
1130 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1135 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx
, uint32_t address
)
1137 struct amdgpu_device
*adev
= ctx
;
1139 return dm_read_reg(adev
->dm
.dc
->ctx
, address
);
1142 static void amdgpu_dm_dmub_reg_write(void *ctx
, uint32_t address
,
1145 struct amdgpu_device
*adev
= ctx
;
1147 return dm_write_reg(adev
->dm
.dc
->ctx
, address
, value
);
1150 static int dm_dmub_sw_init(struct amdgpu_device
*adev
)
1152 struct dmub_srv_create_params create_params
;
1153 struct dmub_srv_region_params region_params
;
1154 struct dmub_srv_region_info region_info
;
1155 struct dmub_srv_fb_params fb_params
;
1156 struct dmub_srv_fb_info
*fb_info
;
1157 struct dmub_srv
*dmub_srv
;
1158 const struct dmcub_firmware_header_v1_0
*hdr
;
1159 const char *fw_name_dmub
;
1160 enum dmub_asic dmub_asic
;
1161 enum dmub_status status
;
1164 switch (adev
->asic_type
) {
1166 dmub_asic
= DMUB_ASIC_DCN21
;
1167 fw_name_dmub
= FIRMWARE_RENOIR_DMUB
;
1171 /* ASIC doesn't support DMUB. */
1175 r
= request_firmware_direct(&adev
->dm
.dmub_fw
, fw_name_dmub
, adev
->dev
);
1177 DRM_ERROR("DMUB firmware loading failed: %d\n", r
);
1181 r
= amdgpu_ucode_validate(adev
->dm
.dmub_fw
);
1183 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r
);
1187 hdr
= (const struct dmcub_firmware_header_v1_0
*)adev
->dm
.dmub_fw
->data
;
1189 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
) {
1190 adev
->firmware
.ucode
[AMDGPU_UCODE_ID_DMCUB
].ucode_id
=
1191 AMDGPU_UCODE_ID_DMCUB
;
1192 adev
->firmware
.ucode
[AMDGPU_UCODE_ID_DMCUB
].fw
=
1194 adev
->firmware
.fw_size
+=
1195 ALIGN(le32_to_cpu(hdr
->inst_const_bytes
), PAGE_SIZE
);
1197 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1198 adev
->dm
.dmcub_fw_version
);
1201 adev
->dm
.dmcub_fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
1203 adev
->dm
.dmub_srv
= kzalloc(sizeof(*adev
->dm
.dmub_srv
), GFP_KERNEL
);
1204 dmub_srv
= adev
->dm
.dmub_srv
;
1207 DRM_ERROR("Failed to allocate DMUB service!\n");
1211 memset(&create_params
, 0, sizeof(create_params
));
1212 create_params
.user_ctx
= adev
;
1213 create_params
.funcs
.reg_read
= amdgpu_dm_dmub_reg_read
;
1214 create_params
.funcs
.reg_write
= amdgpu_dm_dmub_reg_write
;
1215 create_params
.asic
= dmub_asic
;
1217 /* Create the DMUB service. */
1218 status
= dmub_srv_create(dmub_srv
, &create_params
);
1219 if (status
!= DMUB_STATUS_OK
) {
1220 DRM_ERROR("Error creating DMUB service: %d\n", status
);
1224 /* Calculate the size of all the regions for the DMUB service. */
1225 memset(®ion_params
, 0, sizeof(region_params
));
1227 region_params
.inst_const_size
= le32_to_cpu(hdr
->inst_const_bytes
) -
1228 PSP_HEADER_BYTES
- PSP_FOOTER_BYTES
;
1229 region_params
.bss_data_size
= le32_to_cpu(hdr
->bss_data_bytes
);
1230 region_params
.vbios_size
= adev
->bios_size
;
1231 region_params
.fw_bss_data
=
1232 adev
->dm
.dmub_fw
->data
+
1233 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
) +
1234 le32_to_cpu(hdr
->inst_const_bytes
);
1235 region_params
.fw_inst_const
=
1236 adev
->dm
.dmub_fw
->data
+
1237 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
) +
1240 status
= dmub_srv_calc_region_info(dmub_srv
, ®ion_params
,
1243 if (status
!= DMUB_STATUS_OK
) {
1244 DRM_ERROR("Error calculating DMUB region info: %d\n", status
);
1249 * Allocate a framebuffer based on the total size of all the regions.
1250 * TODO: Move this into GART.
1252 r
= amdgpu_bo_create_kernel(adev
, region_info
.fb_size
, PAGE_SIZE
,
1253 AMDGPU_GEM_DOMAIN_VRAM
, &adev
->dm
.dmub_bo
,
1254 &adev
->dm
.dmub_bo_gpu_addr
,
1255 &adev
->dm
.dmub_bo_cpu_addr
);
1259 /* Rebase the regions on the framebuffer address. */
1260 memset(&fb_params
, 0, sizeof(fb_params
));
1261 fb_params
.cpu_addr
= adev
->dm
.dmub_bo_cpu_addr
;
1262 fb_params
.gpu_addr
= adev
->dm
.dmub_bo_gpu_addr
;
1263 fb_params
.region_info
= ®ion_info
;
1265 adev
->dm
.dmub_fb_info
=
1266 kzalloc(sizeof(*adev
->dm
.dmub_fb_info
), GFP_KERNEL
);
1267 fb_info
= adev
->dm
.dmub_fb_info
;
1271 "Failed to allocate framebuffer info for DMUB service!\n");
1275 status
= dmub_srv_calc_fb_info(dmub_srv
, &fb_params
, fb_info
);
1276 if (status
!= DMUB_STATUS_OK
) {
1277 DRM_ERROR("Error calculating DMUB FB info: %d\n", status
);
1284 static int dm_sw_init(void *handle
)
1286 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1289 r
= dm_dmub_sw_init(adev
);
1293 return load_dmcu_fw(adev
);
1296 static int dm_sw_fini(void *handle
)
1298 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1300 kfree(adev
->dm
.dmub_fb_info
);
1301 adev
->dm
.dmub_fb_info
= NULL
;
1303 if (adev
->dm
.dmub_srv
) {
1304 dmub_srv_destroy(adev
->dm
.dmub_srv
);
1305 adev
->dm
.dmub_srv
= NULL
;
1308 if (adev
->dm
.dmub_fw
) {
1309 release_firmware(adev
->dm
.dmub_fw
);
1310 adev
->dm
.dmub_fw
= NULL
;
1313 if(adev
->dm
.fw_dmcu
) {
1314 release_firmware(adev
->dm
.fw_dmcu
);
1315 adev
->dm
.fw_dmcu
= NULL
;
1321 static int detect_mst_link_for_all_connectors(struct drm_device
*dev
)
1323 struct amdgpu_dm_connector
*aconnector
;
1324 struct drm_connector
*connector
;
1325 struct drm_connector_list_iter iter
;
1328 drm_connector_list_iter_begin(dev
, &iter
);
1329 drm_for_each_connector_iter(connector
, &iter
) {
1330 aconnector
= to_amdgpu_dm_connector(connector
);
1331 if (aconnector
->dc_link
->type
== dc_connection_mst_branch
&&
1332 aconnector
->mst_mgr
.aux
) {
1333 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
1335 aconnector
->base
.base
.id
);
1337 ret
= drm_dp_mst_topology_mgr_set_mst(&aconnector
->mst_mgr
, true);
1339 DRM_ERROR("DM_MST: Failed to start MST\n");
1340 aconnector
->dc_link
->type
=
1341 dc_connection_single
;
1346 drm_connector_list_iter_end(&iter
);
1351 static int dm_late_init(void *handle
)
1353 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1355 struct dmcu_iram_parameters params
;
1356 unsigned int linear_lut
[16];
1358 struct dmcu
*dmcu
= NULL
;
1361 if (!adev
->dm
.fw_dmcu
)
1362 return detect_mst_link_for_all_connectors(adev
->ddev
);
1364 dmcu
= adev
->dm
.dc
->res_pool
->dmcu
;
1366 for (i
= 0; i
< 16; i
++)
1367 linear_lut
[i
] = 0xFFFF * i
/ 15;
1370 params
.backlight_ramping_start
= 0xCCCC;
1371 params
.backlight_ramping_reduction
= 0xCCCCCCCC;
1372 params
.backlight_lut_array_size
= 16;
1373 params
.backlight_lut_array
= linear_lut
;
1375 /* Min backlight level after ABM reduction, Don't allow below 1%
1376 * 0xFFFF x 0.01 = 0x28F
1378 params
.min_abm_backlight
= 0x28F;
1380 /* todo will enable for navi10 */
1381 if (adev
->asic_type
<= CHIP_RAVEN
) {
1382 ret
= dmcu_load_iram(dmcu
, params
);
1388 return detect_mst_link_for_all_connectors(adev
->ddev
);
1391 static void s3_handle_mst(struct drm_device
*dev
, bool suspend
)
1393 struct amdgpu_dm_connector
*aconnector
;
1394 struct drm_connector
*connector
;
1395 struct drm_connector_list_iter iter
;
1396 struct drm_dp_mst_topology_mgr
*mgr
;
1398 bool need_hotplug
= false;
1400 drm_connector_list_iter_begin(dev
, &iter
);
1401 drm_for_each_connector_iter(connector
, &iter
) {
1402 aconnector
= to_amdgpu_dm_connector(connector
);
1403 if (aconnector
->dc_link
->type
!= dc_connection_mst_branch
||
1404 aconnector
->mst_port
)
1407 mgr
= &aconnector
->mst_mgr
;
1410 drm_dp_mst_topology_mgr_suspend(mgr
);
1412 ret
= drm_dp_mst_topology_mgr_resume(mgr
, true);
1414 drm_dp_mst_topology_mgr_set_mst(mgr
, false);
1415 need_hotplug
= true;
1419 drm_connector_list_iter_end(&iter
);
1422 drm_kms_helper_hotplug_event(dev
);
1425 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device
*adev
)
1427 struct smu_context
*smu
= &adev
->smu
;
1430 if (!is_support_sw_smu(adev
))
1433 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
1434 * on window driver dc implementation.
1435 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
1436 * should be passed to smu during boot up and resume from s3.
1437 * boot up: dc calculate dcn watermark clock settings within dc_create,
1438 * dcn20_resource_construct
1439 * then call pplib functions below to pass the settings to smu:
1440 * smu_set_watermarks_for_clock_ranges
1441 * smu_set_watermarks_table
1442 * navi10_set_watermarks_table
1443 * smu_write_watermarks_table
1445 * For Renoir, clock settings of dcn watermark are also fixed values.
1446 * dc has implemented different flow for window driver:
1447 * dc_hardware_init / dc_set_power_state
1452 * smu_set_watermarks_for_clock_ranges
1453 * renoir_set_watermarks_table
1454 * smu_write_watermarks_table
1457 * dc_hardware_init -> amdgpu_dm_init
1458 * dc_set_power_state --> dm_resume
1460 * therefore, this function apply to navi10/12/14 but not Renoir
1463 switch(adev
->asic_type
) {
1472 mutex_lock(&smu
->mutex
);
1474 /* pass data to smu controller */
1475 if ((smu
->watermarks_bitmap
& WATERMARKS_EXIST
) &&
1476 !(smu
->watermarks_bitmap
& WATERMARKS_LOADED
)) {
1477 ret
= smu_write_watermarks_table(smu
);
1480 mutex_unlock(&smu
->mutex
);
1481 DRM_ERROR("Failed to update WMTABLE!\n");
1484 smu
->watermarks_bitmap
|= WATERMARKS_LOADED
;
1487 mutex_unlock(&smu
->mutex
);
1493 * dm_hw_init() - Initialize DC device
1494 * @handle: The base driver device containing the amdgpu_dm device.
1496 * Initialize the &struct amdgpu_display_manager device. This involves calling
1497 * the initializers of each DM component, then populating the struct with them.
1499 * Although the function implies hardware initialization, both hardware and
1500 * software are initialized here. Splitting them out to their relevant init
1501 * hooks is a future TODO item.
1503 * Some notable things that are initialized here:
1505 * - Display Core, both software and hardware
1506 * - DC modules that we need (freesync and color management)
1507 * - DRM software states
1508 * - Interrupt sources and handlers
1510 * - Debug FS entries, if enabled
1512 static int dm_hw_init(void *handle
)
1514 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1515 /* Create DAL display manager */
1516 amdgpu_dm_init(adev
);
1517 amdgpu_dm_hpd_init(adev
);
1523 * dm_hw_fini() - Teardown DC device
1524 * @handle: The base driver device containing the amdgpu_dm device.
1526 * Teardown components within &struct amdgpu_display_manager that require
1527 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1528 * were loaded. Also flush IRQ workqueues and disable them.
1530 static int dm_hw_fini(void *handle
)
1532 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1534 amdgpu_dm_hpd_fini(adev
);
1536 amdgpu_dm_irq_fini(adev
);
1537 amdgpu_dm_fini(adev
);
1542 static int dm_enable_vblank(struct drm_crtc
*crtc
);
1543 static void dm_disable_vblank(struct drm_crtc
*crtc
);
1545 static void dm_gpureset_toggle_interrupts(struct amdgpu_device
*adev
,
1546 struct dc_state
*state
, bool enable
)
1548 enum dc_irq_source irq_source
;
1549 struct amdgpu_crtc
*acrtc
;
1553 for (i
= 0; i
< state
->stream_count
; i
++) {
1554 acrtc
= get_crtc_by_otg_inst(
1555 adev
, state
->stream_status
[i
].primary_otg_inst
);
1557 if (acrtc
&& state
->stream_status
[i
].plane_count
!= 0) {
1558 irq_source
= IRQ_TYPE_PFLIP
+ acrtc
->otg_inst
;
1559 rc
= dc_interrupt_set(adev
->dm
.dc
, irq_source
, enable
) ? 0 : -EBUSY
;
1560 DRM_DEBUG("crtc %d - vupdate irq %sabling: r=%d\n",
1561 acrtc
->crtc_id
, enable
? "en" : "dis", rc
);
1563 DRM_WARN("Failed to %s pflip interrupts\n",
1564 enable
? "enable" : "disable");
1567 rc
= dm_enable_vblank(&acrtc
->base
);
1569 DRM_WARN("Failed to enable vblank interrupts\n");
1571 dm_disable_vblank(&acrtc
->base
);
1579 enum dc_status
amdgpu_dm_commit_zero_streams(struct dc
*dc
)
1581 struct dc_state
*context
= NULL
;
1582 enum dc_status res
= DC_ERROR_UNEXPECTED
;
1584 struct dc_stream_state
*del_streams
[MAX_PIPES
];
1585 int del_streams_count
= 0;
1587 memset(del_streams
, 0, sizeof(del_streams
));
1589 context
= dc_create_state(dc
);
1590 if (context
== NULL
)
1591 goto context_alloc_fail
;
1593 dc_resource_state_copy_construct_current(dc
, context
);
1595 /* First remove from context all streams */
1596 for (i
= 0; i
< context
->stream_count
; i
++) {
1597 struct dc_stream_state
*stream
= context
->streams
[i
];
1599 del_streams
[del_streams_count
++] = stream
;
1602 /* Remove all planes for removed streams and then remove the streams */
1603 for (i
= 0; i
< del_streams_count
; i
++) {
1604 if (!dc_rem_all_planes_for_stream(dc
, del_streams
[i
], context
)) {
1605 res
= DC_FAIL_DETACH_SURFACES
;
1609 res
= dc_remove_stream_from_ctx(dc
, context
, del_streams
[i
]);
1615 res
= dc_validate_global_state(dc
, context
, false);
1618 DRM_ERROR("%s:resource validation failed, dc_status:%d\n", __func__
, res
);
1622 res
= dc_commit_state(dc
, context
);
1625 dc_release_state(context
);
1631 static int dm_suspend(void *handle
)
1633 struct amdgpu_device
*adev
= handle
;
1634 struct amdgpu_display_manager
*dm
= &adev
->dm
;
1637 if (adev
->in_gpu_reset
) {
1638 mutex_lock(&dm
->dc_lock
);
1639 dm
->cached_dc_state
= dc_copy_state(dm
->dc
->current_state
);
1641 dm_gpureset_toggle_interrupts(adev
, dm
->cached_dc_state
, false);
1643 amdgpu_dm_commit_zero_streams(dm
->dc
);
1645 amdgpu_dm_irq_suspend(adev
);
1650 WARN_ON(adev
->dm
.cached_state
);
1651 adev
->dm
.cached_state
= drm_atomic_helper_suspend(adev
->ddev
);
1653 s3_handle_mst(adev
->ddev
, true);
1655 amdgpu_dm_irq_suspend(adev
);
1658 dc_set_power_state(dm
->dc
, DC_ACPI_CM_POWER_STATE_D3
);
1663 static struct amdgpu_dm_connector
*
1664 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state
*state
,
1665 struct drm_crtc
*crtc
)
1668 struct drm_connector_state
*new_con_state
;
1669 struct drm_connector
*connector
;
1670 struct drm_crtc
*crtc_from_state
;
1672 for_each_new_connector_in_state(state
, connector
, new_con_state
, i
) {
1673 crtc_from_state
= new_con_state
->crtc
;
1675 if (crtc_from_state
== crtc
)
1676 return to_amdgpu_dm_connector(connector
);
1682 static void emulated_link_detect(struct dc_link
*link
)
1684 struct dc_sink_init_data sink_init_data
= { 0 };
1685 struct display_sink_capability sink_caps
= { 0 };
1686 enum dc_edid_status edid_status
;
1687 struct dc_context
*dc_ctx
= link
->ctx
;
1688 struct dc_sink
*sink
= NULL
;
1689 struct dc_sink
*prev_sink
= NULL
;
1691 link
->type
= dc_connection_none
;
1692 prev_sink
= link
->local_sink
;
1694 if (prev_sink
!= NULL
)
1695 dc_sink_retain(prev_sink
);
1697 switch (link
->connector_signal
) {
1698 case SIGNAL_TYPE_HDMI_TYPE_A
: {
1699 sink_caps
.transaction_type
= DDC_TRANSACTION_TYPE_I2C
;
1700 sink_caps
.signal
= SIGNAL_TYPE_HDMI_TYPE_A
;
1704 case SIGNAL_TYPE_DVI_SINGLE_LINK
: {
1705 sink_caps
.transaction_type
= DDC_TRANSACTION_TYPE_I2C
;
1706 sink_caps
.signal
= SIGNAL_TYPE_DVI_SINGLE_LINK
;
1710 case SIGNAL_TYPE_DVI_DUAL_LINK
: {
1711 sink_caps
.transaction_type
= DDC_TRANSACTION_TYPE_I2C
;
1712 sink_caps
.signal
= SIGNAL_TYPE_DVI_DUAL_LINK
;
1716 case SIGNAL_TYPE_LVDS
: {
1717 sink_caps
.transaction_type
= DDC_TRANSACTION_TYPE_I2C
;
1718 sink_caps
.signal
= SIGNAL_TYPE_LVDS
;
1722 case SIGNAL_TYPE_EDP
: {
1723 sink_caps
.transaction_type
=
1724 DDC_TRANSACTION_TYPE_I2C_OVER_AUX
;
1725 sink_caps
.signal
= SIGNAL_TYPE_EDP
;
1729 case SIGNAL_TYPE_DISPLAY_PORT
: {
1730 sink_caps
.transaction_type
=
1731 DDC_TRANSACTION_TYPE_I2C_OVER_AUX
;
1732 sink_caps
.signal
= SIGNAL_TYPE_VIRTUAL
;
1737 DC_ERROR("Invalid connector type! signal:%d\n",
1738 link
->connector_signal
);
1742 sink_init_data
.link
= link
;
1743 sink_init_data
.sink_signal
= sink_caps
.signal
;
1745 sink
= dc_sink_create(&sink_init_data
);
1747 DC_ERROR("Failed to create sink!\n");
1751 /* dc_sink_create returns a new reference */
1752 link
->local_sink
= sink
;
1754 edid_status
= dm_helpers_read_local_edid(
1759 if (edid_status
!= EDID_OK
)
1760 DC_ERROR("Failed to read EDID");
1764 static void dm_gpureset_commit_state(struct dc_state
*dc_state
,
1765 struct amdgpu_display_manager
*dm
)
1768 struct dc_surface_update surface_updates
[MAX_SURFACES
];
1769 struct dc_plane_info plane_infos
[MAX_SURFACES
];
1770 struct dc_scaling_info scaling_infos
[MAX_SURFACES
];
1771 struct dc_flip_addrs flip_addrs
[MAX_SURFACES
];
1772 struct dc_stream_update stream_update
;
1776 bundle
= kzalloc(sizeof(*bundle
), GFP_KERNEL
);
1779 dm_error("Failed to allocate update bundle\n");
1783 for (k
= 0; k
< dc_state
->stream_count
; k
++) {
1784 bundle
->stream_update
.stream
= dc_state
->streams
[k
];
1786 for (m
= 0; m
< dc_state
->stream_status
->plane_count
; m
++) {
1787 bundle
->surface_updates
[m
].surface
=
1788 dc_state
->stream_status
->plane_states
[m
];
1789 bundle
->surface_updates
[m
].surface
->force_full_update
=
1792 dc_commit_updates_for_stream(
1793 dm
->dc
, bundle
->surface_updates
,
1794 dc_state
->stream_status
->plane_count
,
1795 dc_state
->streams
[k
], &bundle
->stream_update
, dc_state
);
1804 static int dm_resume(void *handle
)
1806 struct amdgpu_device
*adev
= handle
;
1807 struct drm_device
*ddev
= adev
->ddev
;
1808 struct amdgpu_display_manager
*dm
= &adev
->dm
;
1809 struct amdgpu_dm_connector
*aconnector
;
1810 struct drm_connector
*connector
;
1811 struct drm_connector_list_iter iter
;
1812 struct drm_crtc
*crtc
;
1813 struct drm_crtc_state
*new_crtc_state
;
1814 struct dm_crtc_state
*dm_new_crtc_state
;
1815 struct drm_plane
*plane
;
1816 struct drm_plane_state
*new_plane_state
;
1817 struct dm_plane_state
*dm_new_plane_state
;
1818 struct dm_atomic_state
*dm_state
= to_dm_atomic_state(dm
->atomic_obj
.state
);
1819 enum dc_connection_type new_connection_type
= dc_connection_none
;
1820 struct dc_state
*dc_state
;
1823 if (adev
->in_gpu_reset
) {
1824 dc_state
= dm
->cached_dc_state
;
1826 r
= dm_dmub_hw_init(adev
);
1828 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r
);
1830 dc_set_power_state(dm
->dc
, DC_ACPI_CM_POWER_STATE_D0
);
1833 amdgpu_dm_irq_resume_early(adev
);
1835 for (i
= 0; i
< dc_state
->stream_count
; i
++) {
1836 dc_state
->streams
[i
]->mode_changed
= true;
1837 for (j
= 0; j
< dc_state
->stream_status
->plane_count
; j
++) {
1838 dc_state
->stream_status
->plane_states
[j
]->update_flags
.raw
1843 WARN_ON(!dc_commit_state(dm
->dc
, dc_state
));
1845 dm_gpureset_commit_state(dm
->cached_dc_state
, dm
);
1847 dm_gpureset_toggle_interrupts(adev
, dm
->cached_dc_state
, true);
1849 dc_release_state(dm
->cached_dc_state
);
1850 dm
->cached_dc_state
= NULL
;
1852 amdgpu_dm_irq_resume_late(adev
);
1854 mutex_unlock(&dm
->dc_lock
);
1858 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1859 dc_release_state(dm_state
->context
);
1860 dm_state
->context
= dc_create_state(dm
->dc
);
1861 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1862 dc_resource_state_construct(dm
->dc
, dm_state
->context
);
1864 /* Before powering on DC we need to re-initialize DMUB. */
1865 r
= dm_dmub_hw_init(adev
);
1867 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r
);
1869 /* power on hardware */
1870 dc_set_power_state(dm
->dc
, DC_ACPI_CM_POWER_STATE_D0
);
1872 /* program HPD filter */
1876 * early enable HPD Rx IRQ, should be done before set mode as short
1877 * pulse interrupts are used for MST
1879 amdgpu_dm_irq_resume_early(adev
);
1881 /* On resume we need to rewrite the MSTM control bits to enable MST*/
1882 s3_handle_mst(ddev
, false);
1885 drm_connector_list_iter_begin(ddev
, &iter
);
1886 drm_for_each_connector_iter(connector
, &iter
) {
1887 aconnector
= to_amdgpu_dm_connector(connector
);
1890 * this is the case when traversing through already created
1891 * MST connectors, should be skipped
1893 if (aconnector
->mst_port
)
1896 mutex_lock(&aconnector
->hpd_lock
);
1897 if (!dc_link_detect_sink(aconnector
->dc_link
, &new_connection_type
))
1898 DRM_ERROR("KMS: Failed to detect connector\n");
1900 if (aconnector
->base
.force
&& new_connection_type
== dc_connection_none
)
1901 emulated_link_detect(aconnector
->dc_link
);
1903 dc_link_detect(aconnector
->dc_link
, DETECT_REASON_HPD
);
1905 if (aconnector
->fake_enable
&& aconnector
->dc_link
->local_sink
)
1906 aconnector
->fake_enable
= false;
1908 if (aconnector
->dc_sink
)
1909 dc_sink_release(aconnector
->dc_sink
);
1910 aconnector
->dc_sink
= NULL
;
1911 amdgpu_dm_update_connector_after_detect(aconnector
);
1912 mutex_unlock(&aconnector
->hpd_lock
);
1914 drm_connector_list_iter_end(&iter
);
1916 /* Force mode set in atomic commit */
1917 for_each_new_crtc_in_state(dm
->cached_state
, crtc
, new_crtc_state
, i
)
1918 new_crtc_state
->active_changed
= true;
1921 * atomic_check is expected to create the dc states. We need to release
1922 * them here, since they were duplicated as part of the suspend
1925 for_each_new_crtc_in_state(dm
->cached_state
, crtc
, new_crtc_state
, i
) {
1926 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
1927 if (dm_new_crtc_state
->stream
) {
1928 WARN_ON(kref_read(&dm_new_crtc_state
->stream
->refcount
) > 1);
1929 dc_stream_release(dm_new_crtc_state
->stream
);
1930 dm_new_crtc_state
->stream
= NULL
;
1934 for_each_new_plane_in_state(dm
->cached_state
, plane
, new_plane_state
, i
) {
1935 dm_new_plane_state
= to_dm_plane_state(new_plane_state
);
1936 if (dm_new_plane_state
->dc_state
) {
1937 WARN_ON(kref_read(&dm_new_plane_state
->dc_state
->refcount
) > 1);
1938 dc_plane_state_release(dm_new_plane_state
->dc_state
);
1939 dm_new_plane_state
->dc_state
= NULL
;
1943 drm_atomic_helper_resume(ddev
, dm
->cached_state
);
1945 dm
->cached_state
= NULL
;
1947 amdgpu_dm_irq_resume_late(adev
);
1949 amdgpu_dm_smu_write_watermarks_table(adev
);
1957 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1958 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1959 * the base driver's device list to be initialized and torn down accordingly.
1961 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1964 static const struct amd_ip_funcs amdgpu_dm_funcs
= {
1966 .early_init
= dm_early_init
,
1967 .late_init
= dm_late_init
,
1968 .sw_init
= dm_sw_init
,
1969 .sw_fini
= dm_sw_fini
,
1970 .hw_init
= dm_hw_init
,
1971 .hw_fini
= dm_hw_fini
,
1972 .suspend
= dm_suspend
,
1973 .resume
= dm_resume
,
1974 .is_idle
= dm_is_idle
,
1975 .wait_for_idle
= dm_wait_for_idle
,
1976 .check_soft_reset
= dm_check_soft_reset
,
1977 .soft_reset
= dm_soft_reset
,
1978 .set_clockgating_state
= dm_set_clockgating_state
,
1979 .set_powergating_state
= dm_set_powergating_state
,
1982 const struct amdgpu_ip_block_version dm_ip_block
=
1984 .type
= AMD_IP_BLOCK_TYPE_DCE
,
1988 .funcs
= &amdgpu_dm_funcs
,
1998 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs
= {
1999 .fb_create
= amdgpu_display_user_framebuffer_create
,
2000 .output_poll_changed
= drm_fb_helper_output_poll_changed
,
2001 .atomic_check
= amdgpu_dm_atomic_check
,
2002 .atomic_commit
= amdgpu_dm_atomic_commit
,
2005 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs
= {
2006 .atomic_commit_tail
= amdgpu_dm_atomic_commit_tail
2009 static void update_connector_ext_caps(struct amdgpu_dm_connector
*aconnector
)
2011 u32 max_cll
, min_cll
, max
, min
, q
, r
;
2012 struct amdgpu_dm_backlight_caps
*caps
;
2013 struct amdgpu_display_manager
*dm
;
2014 struct drm_connector
*conn_base
;
2015 struct amdgpu_device
*adev
;
2016 static const u8 pre_computed_values
[] = {
2017 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
2018 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};
2020 if (!aconnector
|| !aconnector
->dc_link
)
2023 conn_base
= &aconnector
->base
;
2024 adev
= conn_base
->dev
->dev_private
;
2026 caps
= &dm
->backlight_caps
;
2027 caps
->ext_caps
= &aconnector
->dc_link
->dpcd_sink_ext_caps
;
2028 caps
->aux_support
= false;
2029 max_cll
= conn_base
->hdr_sink_metadata
.hdmi_type1
.max_cll
;
2030 min_cll
= conn_base
->hdr_sink_metadata
.hdmi_type1
.min_cll
;
2032 if (caps
->ext_caps
->bits
.oled
== 1 ||
2033 caps
->ext_caps
->bits
.sdr_aux_backlight_control
== 1 ||
2034 caps
->ext_caps
->bits
.hdr_aux_backlight_control
== 1)
2035 caps
->aux_support
= true;
2037 /* From the specification (CTA-861-G), for calculating the maximum
2038 * luminance we need to use:
2039 * Luminance = 50*2**(CV/32)
2040 * Where CV is a one-byte value.
2041 * For calculating this expression we may need float point precision;
2042 * to avoid this complexity level, we take advantage that CV is divided
2043 * by a constant. From the Euclids division algorithm, we know that CV
2044 * can be written as: CV = 32*q + r. Next, we replace CV in the
2045 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
2046 * need to pre-compute the value of r/32. For pre-computing the values
2047 * We just used the following Ruby line:
2048 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
2049 * The results of the above expressions can be verified at
2050 * pre_computed_values.
2054 max
= (1 << q
) * pre_computed_values
[r
];
2056 // min luminance: maxLum * (CV/255)^2 / 100
2057 q
= DIV_ROUND_CLOSEST(min_cll
, 255);
2058 min
= max
* DIV_ROUND_CLOSEST((q
* q
), 100);
2060 caps
->aux_max_input_signal
= max
;
2061 caps
->aux_min_input_signal
= min
;
2064 void amdgpu_dm_update_connector_after_detect(
2065 struct amdgpu_dm_connector
*aconnector
)
2067 struct drm_connector
*connector
= &aconnector
->base
;
2068 struct drm_device
*dev
= connector
->dev
;
2069 struct dc_sink
*sink
;
2071 /* MST handled by drm_mst framework */
2072 if (aconnector
->mst_mgr
.mst_state
== true)
2076 sink
= aconnector
->dc_link
->local_sink
;
2078 dc_sink_retain(sink
);
2081 * Edid mgmt connector gets first update only in mode_valid hook and then
2082 * the connector sink is set to either fake or physical sink depends on link status.
2083 * Skip if already done during boot.
2085 if (aconnector
->base
.force
!= DRM_FORCE_UNSPECIFIED
2086 && aconnector
->dc_em_sink
) {
2089 * For S3 resume with headless use eml_sink to fake stream
2090 * because on resume connector->sink is set to NULL
2092 mutex_lock(&dev
->mode_config
.mutex
);
2095 if (aconnector
->dc_sink
) {
2096 amdgpu_dm_update_freesync_caps(connector
, NULL
);
2098 * retain and release below are used to
2099 * bump up refcount for sink because the link doesn't point
2100 * to it anymore after disconnect, so on next crtc to connector
2101 * reshuffle by UMD we will get into unwanted dc_sink release
2103 dc_sink_release(aconnector
->dc_sink
);
2105 aconnector
->dc_sink
= sink
;
2106 dc_sink_retain(aconnector
->dc_sink
);
2107 amdgpu_dm_update_freesync_caps(connector
,
2110 amdgpu_dm_update_freesync_caps(connector
, NULL
);
2111 if (!aconnector
->dc_sink
) {
2112 aconnector
->dc_sink
= aconnector
->dc_em_sink
;
2113 dc_sink_retain(aconnector
->dc_sink
);
2117 mutex_unlock(&dev
->mode_config
.mutex
);
2120 dc_sink_release(sink
);
2125 * TODO: temporary guard to look for proper fix
2126 * if this sink is MST sink, we should not do anything
2128 if (sink
&& sink
->sink_signal
== SIGNAL_TYPE_DISPLAY_PORT_MST
) {
2129 dc_sink_release(sink
);
2133 if (aconnector
->dc_sink
== sink
) {
2135 * We got a DP short pulse (Link Loss, DP CTS, etc...).
2138 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2139 aconnector
->connector_id
);
2141 dc_sink_release(sink
);
2145 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2146 aconnector
->connector_id
, aconnector
->dc_sink
, sink
);
2148 mutex_lock(&dev
->mode_config
.mutex
);
2151 * 1. Update status of the drm connector
2152 * 2. Send an event and let userspace tell us what to do
2156 * TODO: check if we still need the S3 mode update workaround.
2157 * If yes, put it here.
2159 if (aconnector
->dc_sink
)
2160 amdgpu_dm_update_freesync_caps(connector
, NULL
);
2162 aconnector
->dc_sink
= sink
;
2163 dc_sink_retain(aconnector
->dc_sink
);
2164 if (sink
->dc_edid
.length
== 0) {
2165 aconnector
->edid
= NULL
;
2166 if (aconnector
->dc_link
->aux_mode
) {
2167 drm_dp_cec_unset_edid(
2168 &aconnector
->dm_dp_aux
.aux
);
2172 (struct edid
*)sink
->dc_edid
.raw_edid
;
2174 drm_connector_update_edid_property(connector
,
2177 if (aconnector
->dc_link
->aux_mode
)
2178 drm_dp_cec_set_edid(&aconnector
->dm_dp_aux
.aux
,
2182 amdgpu_dm_update_freesync_caps(connector
, aconnector
->edid
);
2183 update_connector_ext_caps(aconnector
);
2185 drm_dp_cec_unset_edid(&aconnector
->dm_dp_aux
.aux
);
2186 amdgpu_dm_update_freesync_caps(connector
, NULL
);
2187 drm_connector_update_edid_property(connector
, NULL
);
2188 aconnector
->num_modes
= 0;
2189 dc_sink_release(aconnector
->dc_sink
);
2190 aconnector
->dc_sink
= NULL
;
2191 aconnector
->edid
= NULL
;
2192 #ifdef CONFIG_DRM_AMD_DC_HDCP
2193 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
2194 if (connector
->state
->content_protection
== DRM_MODE_CONTENT_PROTECTION_ENABLED
)
2195 connector
->state
->content_protection
= DRM_MODE_CONTENT_PROTECTION_DESIRED
;
2199 mutex_unlock(&dev
->mode_config
.mutex
);
2202 dc_sink_release(sink
);
2205 static void handle_hpd_irq(void *param
)
2207 struct amdgpu_dm_connector
*aconnector
= (struct amdgpu_dm_connector
*)param
;
2208 struct drm_connector
*connector
= &aconnector
->base
;
2209 struct drm_device
*dev
= connector
->dev
;
2210 enum dc_connection_type new_connection_type
= dc_connection_none
;
2211 #ifdef CONFIG_DRM_AMD_DC_HDCP
2212 struct amdgpu_device
*adev
= dev
->dev_private
;
2216 * In case of failure or MST no need to update connector status or notify the OS
2217 * since (for MST case) MST does this in its own context.
2219 mutex_lock(&aconnector
->hpd_lock
);
2221 #ifdef CONFIG_DRM_AMD_DC_HDCP
2222 if (adev
->dm
.hdcp_workqueue
)
2223 hdcp_reset_display(adev
->dm
.hdcp_workqueue
, aconnector
->dc_link
->link_index
);
2225 if (aconnector
->fake_enable
)
2226 aconnector
->fake_enable
= false;
2228 if (!dc_link_detect_sink(aconnector
->dc_link
, &new_connection_type
))
2229 DRM_ERROR("KMS: Failed to detect connector\n");
2231 if (aconnector
->base
.force
&& new_connection_type
== dc_connection_none
) {
2232 emulated_link_detect(aconnector
->dc_link
);
2235 drm_modeset_lock_all(dev
);
2236 dm_restore_drm_connector_state(dev
, connector
);
2237 drm_modeset_unlock_all(dev
);
2239 if (aconnector
->base
.force
== DRM_FORCE_UNSPECIFIED
)
2240 drm_kms_helper_hotplug_event(dev
);
2242 } else if (dc_link_detect(aconnector
->dc_link
, DETECT_REASON_HPD
)) {
2243 amdgpu_dm_update_connector_after_detect(aconnector
);
2246 drm_modeset_lock_all(dev
);
2247 dm_restore_drm_connector_state(dev
, connector
);
2248 drm_modeset_unlock_all(dev
);
2250 if (aconnector
->base
.force
== DRM_FORCE_UNSPECIFIED
)
2251 drm_kms_helper_hotplug_event(dev
);
2253 mutex_unlock(&aconnector
->hpd_lock
);
2257 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector
*aconnector
)
2259 uint8_t esi
[DP_PSR_ERROR_STATUS
- DP_SINK_COUNT_ESI
] = { 0 };
2261 bool new_irq_handled
= false;
2263 int dpcd_bytes_to_read
;
2265 const int max_process_count
= 30;
2266 int process_count
= 0;
2268 const struct dc_link_status
*link_status
= dc_link_get_status(aconnector
->dc_link
);
2270 if (link_status
->dpcd_caps
->dpcd_rev
.raw
< 0x12) {
2271 dpcd_bytes_to_read
= DP_LANE0_1_STATUS
- DP_SINK_COUNT
;
2272 /* DPCD 0x200 - 0x201 for downstream IRQ */
2273 dpcd_addr
= DP_SINK_COUNT
;
2275 dpcd_bytes_to_read
= DP_PSR_ERROR_STATUS
- DP_SINK_COUNT_ESI
;
2276 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
2277 dpcd_addr
= DP_SINK_COUNT_ESI
;
2280 dret
= drm_dp_dpcd_read(
2281 &aconnector
->dm_dp_aux
.aux
,
2284 dpcd_bytes_to_read
);
2286 while (dret
== dpcd_bytes_to_read
&&
2287 process_count
< max_process_count
) {
2293 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
2294 /* handle HPD short pulse irq */
2295 if (aconnector
->mst_mgr
.mst_state
)
2297 &aconnector
->mst_mgr
,
2301 if (new_irq_handled
) {
2302 /* ACK at DPCD to notify down stream */
2303 const int ack_dpcd_bytes_to_write
=
2304 dpcd_bytes_to_read
- 1;
2306 for (retry
= 0; retry
< 3; retry
++) {
2309 wret
= drm_dp_dpcd_write(
2310 &aconnector
->dm_dp_aux
.aux
,
2313 ack_dpcd_bytes_to_write
);
2314 if (wret
== ack_dpcd_bytes_to_write
)
2318 /* check if there is new irq to be handled */
2319 dret
= drm_dp_dpcd_read(
2320 &aconnector
->dm_dp_aux
.aux
,
2323 dpcd_bytes_to_read
);
2325 new_irq_handled
= false;
2331 if (process_count
== max_process_count
)
2332 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
2335 static void handle_hpd_rx_irq(void *param
)
2337 struct amdgpu_dm_connector
*aconnector
= (struct amdgpu_dm_connector
*)param
;
2338 struct drm_connector
*connector
= &aconnector
->base
;
2339 struct drm_device
*dev
= connector
->dev
;
2340 struct dc_link
*dc_link
= aconnector
->dc_link
;
2341 bool is_mst_root_connector
= aconnector
->mst_mgr
.mst_state
;
2342 enum dc_connection_type new_connection_type
= dc_connection_none
;
2343 #ifdef CONFIG_DRM_AMD_DC_HDCP
2344 union hpd_irq_data hpd_irq_data
;
2345 struct amdgpu_device
*adev
= dev
->dev_private
;
2347 memset(&hpd_irq_data
, 0, sizeof(hpd_irq_data
));
2351 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
2352 * conflict, after implement i2c helper, this mutex should be
2355 if (dc_link
->type
!= dc_connection_mst_branch
)
2356 mutex_lock(&aconnector
->hpd_lock
);
2359 #ifdef CONFIG_DRM_AMD_DC_HDCP
2360 if (dc_link_handle_hpd_rx_irq(dc_link
, &hpd_irq_data
, NULL
) &&
2362 if (dc_link_handle_hpd_rx_irq(dc_link
, NULL
, NULL
) &&
2364 !is_mst_root_connector
) {
2365 /* Downstream Port status changed. */
2366 if (!dc_link_detect_sink(dc_link
, &new_connection_type
))
2367 DRM_ERROR("KMS: Failed to detect connector\n");
2369 if (aconnector
->base
.force
&& new_connection_type
== dc_connection_none
) {
2370 emulated_link_detect(dc_link
);
2372 if (aconnector
->fake_enable
)
2373 aconnector
->fake_enable
= false;
2375 amdgpu_dm_update_connector_after_detect(aconnector
);
2378 drm_modeset_lock_all(dev
);
2379 dm_restore_drm_connector_state(dev
, connector
);
2380 drm_modeset_unlock_all(dev
);
2382 drm_kms_helper_hotplug_event(dev
);
2383 } else if (dc_link_detect(dc_link
, DETECT_REASON_HPDRX
)) {
2385 if (aconnector
->fake_enable
)
2386 aconnector
->fake_enable
= false;
2388 amdgpu_dm_update_connector_after_detect(aconnector
);
2391 drm_modeset_lock_all(dev
);
2392 dm_restore_drm_connector_state(dev
, connector
);
2393 drm_modeset_unlock_all(dev
);
2395 drm_kms_helper_hotplug_event(dev
);
2398 #ifdef CONFIG_DRM_AMD_DC_HDCP
2399 if (hpd_irq_data
.bytes
.device_service_irq
.bits
.CP_IRQ
) {
2400 if (adev
->dm
.hdcp_workqueue
)
2401 hdcp_handle_cpirq(adev
->dm
.hdcp_workqueue
, aconnector
->base
.index
);
2404 if ((dc_link
->cur_link_settings
.lane_count
!= LANE_COUNT_UNKNOWN
) ||
2405 (dc_link
->type
== dc_connection_mst_branch
))
2406 dm_handle_hpd_rx_irq(aconnector
);
2408 if (dc_link
->type
!= dc_connection_mst_branch
) {
2409 drm_dp_cec_irq(&aconnector
->dm_dp_aux
.aux
);
2410 mutex_unlock(&aconnector
->hpd_lock
);
2414 static void register_hpd_handlers(struct amdgpu_device
*adev
)
2416 struct drm_device
*dev
= adev
->ddev
;
2417 struct drm_connector
*connector
;
2418 struct amdgpu_dm_connector
*aconnector
;
2419 const struct dc_link
*dc_link
;
2420 struct dc_interrupt_params int_params
= {0};
2422 int_params
.requested_polarity
= INTERRUPT_POLARITY_DEFAULT
;
2423 int_params
.current_polarity
= INTERRUPT_POLARITY_DEFAULT
;
2425 list_for_each_entry(connector
,
2426 &dev
->mode_config
.connector_list
, head
) {
2428 aconnector
= to_amdgpu_dm_connector(connector
);
2429 dc_link
= aconnector
->dc_link
;
2431 if (DC_IRQ_SOURCE_INVALID
!= dc_link
->irq_source_hpd
) {
2432 int_params
.int_context
= INTERRUPT_LOW_IRQ_CONTEXT
;
2433 int_params
.irq_source
= dc_link
->irq_source_hpd
;
2435 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
2437 (void *) aconnector
);
2440 if (DC_IRQ_SOURCE_INVALID
!= dc_link
->irq_source_hpd_rx
) {
2442 /* Also register for DP short pulse (hpd_rx). */
2443 int_params
.int_context
= INTERRUPT_LOW_IRQ_CONTEXT
;
2444 int_params
.irq_source
= dc_link
->irq_source_hpd_rx
;
2446 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
2448 (void *) aconnector
);
2453 /* Register IRQ sources and initialize IRQ callbacks */
2454 static int dce110_register_irq_handlers(struct amdgpu_device
*adev
)
2456 struct dc
*dc
= adev
->dm
.dc
;
2457 struct common_irq_params
*c_irq_params
;
2458 struct dc_interrupt_params int_params
= {0};
2461 unsigned client_id
= AMDGPU_IRQ_CLIENTID_LEGACY
;
2463 if (adev
->asic_type
>= CHIP_VEGA10
)
2464 client_id
= SOC15_IH_CLIENTID_DCE
;
2466 int_params
.requested_polarity
= INTERRUPT_POLARITY_DEFAULT
;
2467 int_params
.current_polarity
= INTERRUPT_POLARITY_DEFAULT
;
2470 * Actions of amdgpu_irq_add_id():
2471 * 1. Register a set() function with base driver.
2472 * Base driver will call set() function to enable/disable an
2473 * interrupt in DC hardware.
2474 * 2. Register amdgpu_dm_irq_handler().
2475 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2476 * coming from DC hardware.
2477 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2478 * for acknowledging and handling. */
2480 /* Use VBLANK interrupt */
2481 for (i
= VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0
; i
<= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0
; i
++) {
2482 r
= amdgpu_irq_add_id(adev
, client_id
, i
, &adev
->crtc_irq
);
2484 DRM_ERROR("Failed to add crtc irq id!\n");
2488 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
2489 int_params
.irq_source
=
2490 dc_interrupt_to_irq_source(dc
, i
, 0);
2492 c_irq_params
= &adev
->dm
.vblank_params
[int_params
.irq_source
- DC_IRQ_SOURCE_VBLANK1
];
2494 c_irq_params
->adev
= adev
;
2495 c_irq_params
->irq_src
= int_params
.irq_source
;
2497 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
2498 dm_crtc_high_irq
, c_irq_params
);
2501 /* Use VUPDATE interrupt */
2502 for (i
= VISLANDS30_IV_SRCID_D1_V_UPDATE_INT
; i
<= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT
; i
+= 2) {
2503 r
= amdgpu_irq_add_id(adev
, client_id
, i
, &adev
->vupdate_irq
);
2505 DRM_ERROR("Failed to add vupdate irq id!\n");
2509 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
2510 int_params
.irq_source
=
2511 dc_interrupt_to_irq_source(dc
, i
, 0);
2513 c_irq_params
= &adev
->dm
.vupdate_params
[int_params
.irq_source
- DC_IRQ_SOURCE_VUPDATE1
];
2515 c_irq_params
->adev
= adev
;
2516 c_irq_params
->irq_src
= int_params
.irq_source
;
2518 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
2519 dm_vupdate_high_irq
, c_irq_params
);
2522 /* Use GRPH_PFLIP interrupt */
2523 for (i
= VISLANDS30_IV_SRCID_D1_GRPH_PFLIP
;
2524 i
<= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP
; i
+= 2) {
2525 r
= amdgpu_irq_add_id(adev
, client_id
, i
, &adev
->pageflip_irq
);
2527 DRM_ERROR("Failed to add page flip irq id!\n");
2531 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
2532 int_params
.irq_source
=
2533 dc_interrupt_to_irq_source(dc
, i
, 0);
2535 c_irq_params
= &adev
->dm
.pflip_params
[int_params
.irq_source
- DC_IRQ_SOURCE_PFLIP_FIRST
];
2537 c_irq_params
->adev
= adev
;
2538 c_irq_params
->irq_src
= int_params
.irq_source
;
2540 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
2541 dm_pflip_high_irq
, c_irq_params
);
2546 r
= amdgpu_irq_add_id(adev
, client_id
,
2547 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
, &adev
->hpd_irq
);
2549 DRM_ERROR("Failed to add hpd irq id!\n");
2553 register_hpd_handlers(adev
);
2558 #if defined(CONFIG_DRM_AMD_DC_DCN)
2559 /* Register IRQ sources and initialize IRQ callbacks */
2560 static int dcn10_register_irq_handlers(struct amdgpu_device
*adev
)
2562 struct dc
*dc
= adev
->dm
.dc
;
2563 struct common_irq_params
*c_irq_params
;
2564 struct dc_interrupt_params int_params
= {0};
2568 int_params
.requested_polarity
= INTERRUPT_POLARITY_DEFAULT
;
2569 int_params
.current_polarity
= INTERRUPT_POLARITY_DEFAULT
;
2572 * Actions of amdgpu_irq_add_id():
2573 * 1. Register a set() function with base driver.
2574 * Base driver will call set() function to enable/disable an
2575 * interrupt in DC hardware.
2576 * 2. Register amdgpu_dm_irq_handler().
2577 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2578 * coming from DC hardware.
2579 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2580 * for acknowledging and handling.
2583 /* Use VSTARTUP interrupt */
2584 for (i
= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP
;
2585 i
<= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP
+ adev
->mode_info
.num_crtc
- 1;
2587 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_DCE
, i
, &adev
->crtc_irq
);
2590 DRM_ERROR("Failed to add crtc irq id!\n");
2594 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
2595 int_params
.irq_source
=
2596 dc_interrupt_to_irq_source(dc
, i
, 0);
2598 c_irq_params
= &adev
->dm
.vblank_params
[int_params
.irq_source
- DC_IRQ_SOURCE_VBLANK1
];
2600 c_irq_params
->adev
= adev
;
2601 c_irq_params
->irq_src
= int_params
.irq_source
;
2603 amdgpu_dm_irq_register_interrupt(
2604 adev
, &int_params
, dm_crtc_high_irq
, c_irq_params
);
2607 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
2608 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
2609 * to trigger at end of each vblank, regardless of state of the lock,
2610 * matching DCE behaviour.
2612 for (i
= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT
;
2613 i
<= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT
+ adev
->mode_info
.num_crtc
- 1;
2615 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_DCE
, i
, &adev
->vupdate_irq
);
2618 DRM_ERROR("Failed to add vupdate irq id!\n");
2622 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
2623 int_params
.irq_source
=
2624 dc_interrupt_to_irq_source(dc
, i
, 0);
2626 c_irq_params
= &adev
->dm
.vupdate_params
[int_params
.irq_source
- DC_IRQ_SOURCE_VUPDATE1
];
2628 c_irq_params
->adev
= adev
;
2629 c_irq_params
->irq_src
= int_params
.irq_source
;
2631 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
2632 dm_vupdate_high_irq
, c_irq_params
);
2635 /* Use GRPH_PFLIP interrupt */
2636 for (i
= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT
;
2637 i
<= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT
+ adev
->mode_info
.num_crtc
- 1;
2639 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_DCE
, i
, &adev
->pageflip_irq
);
2641 DRM_ERROR("Failed to add page flip irq id!\n");
2645 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
2646 int_params
.irq_source
=
2647 dc_interrupt_to_irq_source(dc
, i
, 0);
2649 c_irq_params
= &adev
->dm
.pflip_params
[int_params
.irq_source
- DC_IRQ_SOURCE_PFLIP_FIRST
];
2651 c_irq_params
->adev
= adev
;
2652 c_irq_params
->irq_src
= int_params
.irq_source
;
2654 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
2655 dm_pflip_high_irq
, c_irq_params
);
2660 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_DCE
, DCN_1_0__SRCID__DC_HPD1_INT
,
2663 DRM_ERROR("Failed to add hpd irq id!\n");
2667 register_hpd_handlers(adev
);
2674 * Acquires the lock for the atomic state object and returns
2675 * the new atomic state.
2677 * This should only be called during atomic check.
2679 static int dm_atomic_get_state(struct drm_atomic_state
*state
,
2680 struct dm_atomic_state
**dm_state
)
2682 struct drm_device
*dev
= state
->dev
;
2683 struct amdgpu_device
*adev
= dev
->dev_private
;
2684 struct amdgpu_display_manager
*dm
= &adev
->dm
;
2685 struct drm_private_state
*priv_state
;
2690 priv_state
= drm_atomic_get_private_obj_state(state
, &dm
->atomic_obj
);
2691 if (IS_ERR(priv_state
))
2692 return PTR_ERR(priv_state
);
2694 *dm_state
= to_dm_atomic_state(priv_state
);
2699 struct dm_atomic_state
*
2700 dm_atomic_get_new_state(struct drm_atomic_state
*state
)
2702 struct drm_device
*dev
= state
->dev
;
2703 struct amdgpu_device
*adev
= dev
->dev_private
;
2704 struct amdgpu_display_manager
*dm
= &adev
->dm
;
2705 struct drm_private_obj
*obj
;
2706 struct drm_private_state
*new_obj_state
;
2709 for_each_new_private_obj_in_state(state
, obj
, new_obj_state
, i
) {
2710 if (obj
->funcs
== dm
->atomic_obj
.funcs
)
2711 return to_dm_atomic_state(new_obj_state
);
2717 struct dm_atomic_state
*
2718 dm_atomic_get_old_state(struct drm_atomic_state
*state
)
2720 struct drm_device
*dev
= state
->dev
;
2721 struct amdgpu_device
*adev
= dev
->dev_private
;
2722 struct amdgpu_display_manager
*dm
= &adev
->dm
;
2723 struct drm_private_obj
*obj
;
2724 struct drm_private_state
*old_obj_state
;
2727 for_each_old_private_obj_in_state(state
, obj
, old_obj_state
, i
) {
2728 if (obj
->funcs
== dm
->atomic_obj
.funcs
)
2729 return to_dm_atomic_state(old_obj_state
);
2735 static struct drm_private_state
*
2736 dm_atomic_duplicate_state(struct drm_private_obj
*obj
)
2738 struct dm_atomic_state
*old_state
, *new_state
;
2740 new_state
= kzalloc(sizeof(*new_state
), GFP_KERNEL
);
2744 __drm_atomic_helper_private_obj_duplicate_state(obj
, &new_state
->base
);
2746 old_state
= to_dm_atomic_state(obj
->state
);
2748 if (old_state
&& old_state
->context
)
2749 new_state
->context
= dc_copy_state(old_state
->context
);
2751 if (!new_state
->context
) {
2756 return &new_state
->base
;
2759 static void dm_atomic_destroy_state(struct drm_private_obj
*obj
,
2760 struct drm_private_state
*state
)
2762 struct dm_atomic_state
*dm_state
= to_dm_atomic_state(state
);
2764 if (dm_state
&& dm_state
->context
)
2765 dc_release_state(dm_state
->context
);
2770 static struct drm_private_state_funcs dm_atomic_state_funcs
= {
2771 .atomic_duplicate_state
= dm_atomic_duplicate_state
,
2772 .atomic_destroy_state
= dm_atomic_destroy_state
,
2775 static int amdgpu_dm_mode_config_init(struct amdgpu_device
*adev
)
2777 struct dm_atomic_state
*state
;
2780 adev
->mode_info
.mode_config_initialized
= true;
2782 adev
->ddev
->mode_config
.funcs
= (void *)&amdgpu_dm_mode_funcs
;
2783 adev
->ddev
->mode_config
.helper_private
= &amdgpu_dm_mode_config_helperfuncs
;
2785 adev
->ddev
->mode_config
.max_width
= 16384;
2786 adev
->ddev
->mode_config
.max_height
= 16384;
2788 adev
->ddev
->mode_config
.preferred_depth
= 24;
2789 adev
->ddev
->mode_config
.prefer_shadow
= 1;
2790 /* indicates support for immediate flip */
2791 adev
->ddev
->mode_config
.async_page_flip
= true;
2793 adev
->ddev
->mode_config
.fb_base
= adev
->gmc
.aper_base
;
2795 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
2799 state
->context
= dc_create_state(adev
->dm
.dc
);
2800 if (!state
->context
) {
2805 dc_resource_state_copy_construct_current(adev
->dm
.dc
, state
->context
);
2807 drm_atomic_private_obj_init(adev
->ddev
,
2808 &adev
->dm
.atomic_obj
,
2810 &dm_atomic_state_funcs
);
2812 r
= amdgpu_display_modeset_create_props(adev
);
2816 r
= amdgpu_dm_audio_init(adev
);
2823 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2824 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2825 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
2827 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2828 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2830 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager
*dm
)
2832 #if defined(CONFIG_ACPI)
2833 struct amdgpu_dm_backlight_caps caps
;
2835 if (dm
->backlight_caps
.caps_valid
)
2838 amdgpu_acpi_get_backlight_caps(dm
->adev
, &caps
);
2839 if (caps
.caps_valid
) {
2840 dm
->backlight_caps
.caps_valid
= true;
2841 if (caps
.aux_support
)
2843 dm
->backlight_caps
.min_input_signal
= caps
.min_input_signal
;
2844 dm
->backlight_caps
.max_input_signal
= caps
.max_input_signal
;
2846 dm
->backlight_caps
.min_input_signal
=
2847 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT
;
2848 dm
->backlight_caps
.max_input_signal
=
2849 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT
;
2852 if (dm
->backlight_caps
.aux_support
)
2855 dm
->backlight_caps
.min_input_signal
= AMDGPU_DM_DEFAULT_MIN_BACKLIGHT
;
2856 dm
->backlight_caps
.max_input_signal
= AMDGPU_DM_DEFAULT_MAX_BACKLIGHT
;
2860 static int set_backlight_via_aux(struct dc_link
*link
, uint32_t brightness
)
2867 rc
= dc_link_set_backlight_level_nits(link
, true, brightness
,
2868 AUX_BL_DEFAULT_TRANSITION_TIME_MS
);
2873 static u32
convert_brightness(const struct amdgpu_dm_backlight_caps
*caps
,
2874 const uint32_t user_brightness
)
2876 u32 min
, max
, conversion_pace
;
2877 u32 brightness
= user_brightness
;
2882 if (!caps
->aux_support
) {
2883 max
= caps
->max_input_signal
;
2884 min
= caps
->min_input_signal
;
2886 * The brightness input is in the range 0-255
2887 * It needs to be rescaled to be between the
2888 * requested min and max input signal
2889 * It also needs to be scaled up by 0x101 to
2890 * match the DC interface which has a range of
2893 conversion_pace
= 0x101;
2898 / AMDGPU_MAX_BL_LEVEL
2899 + min
* conversion_pace
;
2902 * We are doing a linear interpolation here, which is OK but
2903 * does not provide the optimal result. We probably want
2904 * something close to the Perceptual Quantizer (PQ) curve.
2906 max
= caps
->aux_max_input_signal
;
2907 min
= caps
->aux_min_input_signal
;
2909 brightness
= (AMDGPU_MAX_BL_LEVEL
- user_brightness
) * min
2910 + user_brightness
* max
;
2911 // Multiple the value by 1000 since we use millinits
2913 brightness
= DIV_ROUND_CLOSEST(brightness
, AMDGPU_MAX_BL_LEVEL
);
2920 static int amdgpu_dm_backlight_update_status(struct backlight_device
*bd
)
2922 struct amdgpu_display_manager
*dm
= bl_get_data(bd
);
2923 struct amdgpu_dm_backlight_caps caps
;
2924 struct dc_link
*link
= NULL
;
2928 amdgpu_dm_update_backlight_caps(dm
);
2929 caps
= dm
->backlight_caps
;
2931 link
= (struct dc_link
*)dm
->backlight_link
;
2933 brightness
= convert_brightness(&caps
, bd
->props
.brightness
);
2934 // Change brightness based on AUX property
2935 if (caps
.aux_support
)
2936 return set_backlight_via_aux(link
, brightness
);
2938 rc
= dc_link_set_backlight_level(dm
->backlight_link
, brightness
, 0);
2943 static int amdgpu_dm_backlight_get_brightness(struct backlight_device
*bd
)
2945 struct amdgpu_display_manager
*dm
= bl_get_data(bd
);
2946 int ret
= dc_link_get_backlight_level(dm
->backlight_link
);
2948 if (ret
== DC_ERROR_UNEXPECTED
)
2949 return bd
->props
.brightness
;
2953 static const struct backlight_ops amdgpu_dm_backlight_ops
= {
2954 .options
= BL_CORE_SUSPENDRESUME
,
2955 .get_brightness
= amdgpu_dm_backlight_get_brightness
,
2956 .update_status
= amdgpu_dm_backlight_update_status
,
2960 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager
*dm
)
2963 struct backlight_properties props
= { 0 };
2965 amdgpu_dm_update_backlight_caps(dm
);
2967 props
.max_brightness
= AMDGPU_MAX_BL_LEVEL
;
2968 props
.brightness
= AMDGPU_MAX_BL_LEVEL
;
2969 props
.type
= BACKLIGHT_RAW
;
2971 snprintf(bl_name
, sizeof(bl_name
), "amdgpu_bl%d",
2972 dm
->adev
->ddev
->primary
->index
);
2974 dm
->backlight_dev
= backlight_device_register(bl_name
,
2975 dm
->adev
->ddev
->dev
,
2977 &amdgpu_dm_backlight_ops
,
2980 if (IS_ERR(dm
->backlight_dev
))
2981 DRM_ERROR("DM: Backlight registration failed!\n");
2983 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name
);
2988 static int initialize_plane(struct amdgpu_display_manager
*dm
,
2989 struct amdgpu_mode_info
*mode_info
, int plane_id
,
2990 enum drm_plane_type plane_type
,
2991 const struct dc_plane_cap
*plane_cap
)
2993 struct drm_plane
*plane
;
2994 unsigned long possible_crtcs
;
2997 plane
= kzalloc(sizeof(struct drm_plane
), GFP_KERNEL
);
2999 DRM_ERROR("KMS: Failed to allocate plane\n");
3002 plane
->type
= plane_type
;
3005 * HACK: IGT tests expect that the primary plane for a CRTC
3006 * can only have one possible CRTC. Only expose support for
3007 * any CRTC if they're not going to be used as a primary plane
3008 * for a CRTC - like overlay or underlay planes.
3010 possible_crtcs
= 1 << plane_id
;
3011 if (plane_id
>= dm
->dc
->caps
.max_streams
)
3012 possible_crtcs
= 0xff;
3014 ret
= amdgpu_dm_plane_init(dm
, plane
, possible_crtcs
, plane_cap
);
3017 DRM_ERROR("KMS: Failed to initialize plane\n");
3023 mode_info
->planes
[plane_id
] = plane
;
3029 static void register_backlight_device(struct amdgpu_display_manager
*dm
,
3030 struct dc_link
*link
)
3032 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3033 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3035 if ((link
->connector_signal
& (SIGNAL_TYPE_EDP
| SIGNAL_TYPE_LVDS
)) &&
3036 link
->type
!= dc_connection_none
) {
3038 * Event if registration failed, we should continue with
3039 * DM initialization because not having a backlight control
3040 * is better then a black screen.
3042 amdgpu_dm_register_backlight_device(dm
);
3044 if (dm
->backlight_dev
)
3045 dm
->backlight_link
= link
;
3052 * In this architecture, the association
3053 * connector -> encoder -> crtc
3054 * id not really requried. The crtc and connector will hold the
3055 * display_index as an abstraction to use with DAL component
3057 * Returns 0 on success
3059 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device
*adev
)
3061 struct amdgpu_display_manager
*dm
= &adev
->dm
;
3063 struct amdgpu_dm_connector
*aconnector
= NULL
;
3064 struct amdgpu_encoder
*aencoder
= NULL
;
3065 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
3067 int32_t primary_planes
;
3068 enum dc_connection_type new_connection_type
= dc_connection_none
;
3069 const struct dc_plane_cap
*plane
;
3071 link_cnt
= dm
->dc
->caps
.max_links
;
3072 if (amdgpu_dm_mode_config_init(dm
->adev
)) {
3073 DRM_ERROR("DM: Failed to initialize mode config\n");
3077 /* There is one primary plane per CRTC */
3078 primary_planes
= dm
->dc
->caps
.max_streams
;
3079 ASSERT(primary_planes
<= AMDGPU_MAX_PLANES
);
3082 * Initialize primary planes, implicit planes for legacy IOCTLS.
3083 * Order is reversed to match iteration order in atomic check.
3085 for (i
= (primary_planes
- 1); i
>= 0; i
--) {
3086 plane
= &dm
->dc
->caps
.planes
[i
];
3088 if (initialize_plane(dm
, mode_info
, i
,
3089 DRM_PLANE_TYPE_PRIMARY
, plane
)) {
3090 DRM_ERROR("KMS: Failed to initialize primary plane\n");
3096 * Initialize overlay planes, index starting after primary planes.
3097 * These planes have a higher DRM index than the primary planes since
3098 * they should be considered as having a higher z-order.
3099 * Order is reversed to match iteration order in atomic check.
3101 * Only support DCN for now, and only expose one so we don't encourage
3102 * userspace to use up all the pipes.
3104 for (i
= 0; i
< dm
->dc
->caps
.max_planes
; ++i
) {
3105 struct dc_plane_cap
*plane
= &dm
->dc
->caps
.planes
[i
];
3107 if (plane
->type
!= DC_PLANE_TYPE_DCN_UNIVERSAL
)
3110 if (!plane
->blends_with_above
|| !plane
->blends_with_below
)
3113 if (!plane
->pixel_format_support
.argb8888
)
3116 if (initialize_plane(dm
, NULL
, primary_planes
+ i
,
3117 DRM_PLANE_TYPE_OVERLAY
, plane
)) {
3118 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
3122 /* Only create one overlay plane. */
3126 for (i
= 0; i
< dm
->dc
->caps
.max_streams
; i
++)
3127 if (amdgpu_dm_crtc_init(dm
, mode_info
->planes
[i
], i
)) {
3128 DRM_ERROR("KMS: Failed to initialize crtc\n");
3132 dm
->display_indexes_num
= dm
->dc
->caps
.max_streams
;
3134 /* loops over all connectors on the board */
3135 for (i
= 0; i
< link_cnt
; i
++) {
3136 struct dc_link
*link
= NULL
;
3138 if (i
> AMDGPU_DM_MAX_DISPLAY_INDEX
) {
3140 "KMS: Cannot support more than %d display indexes\n",
3141 AMDGPU_DM_MAX_DISPLAY_INDEX
);
3145 aconnector
= kzalloc(sizeof(*aconnector
), GFP_KERNEL
);
3149 aencoder
= kzalloc(sizeof(*aencoder
), GFP_KERNEL
);
3153 if (amdgpu_dm_encoder_init(dm
->ddev
, aencoder
, i
)) {
3154 DRM_ERROR("KMS: Failed to initialize encoder\n");
3158 if (amdgpu_dm_connector_init(dm
, aconnector
, i
, aencoder
)) {
3159 DRM_ERROR("KMS: Failed to initialize connector\n");
3163 link
= dc_get_link_at_index(dm
->dc
, i
);
3165 if (!dc_link_detect_sink(link
, &new_connection_type
))
3166 DRM_ERROR("KMS: Failed to detect connector\n");
3168 if (aconnector
->base
.force
&& new_connection_type
== dc_connection_none
) {
3169 emulated_link_detect(link
);
3170 amdgpu_dm_update_connector_after_detect(aconnector
);
3172 } else if (dc_link_detect(link
, DETECT_REASON_BOOT
)) {
3173 amdgpu_dm_update_connector_after_detect(aconnector
);
3174 register_backlight_device(dm
, link
);
3175 if (amdgpu_dc_feature_mask
& DC_PSR_MASK
)
3176 amdgpu_dm_set_psr_caps(link
);
3182 /* Software is initialized. Now we can register interrupt handlers. */
3183 switch (adev
->asic_type
) {
3193 case CHIP_POLARIS11
:
3194 case CHIP_POLARIS10
:
3195 case CHIP_POLARIS12
:
3200 if (dce110_register_irq_handlers(dm
->adev
)) {
3201 DRM_ERROR("DM: Failed to initialize IRQ\n");
3205 #if defined(CONFIG_DRM_AMD_DC_DCN)
3211 if (dcn10_register_irq_handlers(dm
->adev
)) {
3212 DRM_ERROR("DM: Failed to initialize IRQ\n");
3218 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev
->asic_type
);
3222 /* No userspace support. */
3223 dm
->dc
->debug
.disable_tri_buf
= true;
3233 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager
*dm
)
3235 drm_mode_config_cleanup(dm
->ddev
);
3236 drm_atomic_private_obj_fini(&dm
->atomic_obj
);
3240 /******************************************************************************
3241 * amdgpu_display_funcs functions
3242 *****************************************************************************/
3245 * dm_bandwidth_update - program display watermarks
3247 * @adev: amdgpu_device pointer
3249 * Calculate and program the display watermarks and line buffer allocation.
3251 static void dm_bandwidth_update(struct amdgpu_device
*adev
)
3253 /* TODO: implement later */
3256 static const struct amdgpu_display_funcs dm_display_funcs
= {
3257 .bandwidth_update
= dm_bandwidth_update
, /* called unconditionally */
3258 .vblank_get_counter
= dm_vblank_get_counter
,/* called unconditionally */
3259 .backlight_set_level
= NULL
, /* never called for DC */
3260 .backlight_get_level
= NULL
, /* never called for DC */
3261 .hpd_sense
= NULL
,/* called unconditionally */
3262 .hpd_set_polarity
= NULL
, /* called unconditionally */
3263 .hpd_get_gpio_reg
= NULL
, /* VBIOS parsing. DAL does it. */
3264 .page_flip_get_scanoutpos
=
3265 dm_crtc_get_scanoutpos
,/* called unconditionally */
3266 .add_encoder
= NULL
, /* VBIOS parsing. DAL does it. */
3267 .add_connector
= NULL
, /* VBIOS parsing. DAL does it. */
3270 #if defined(CONFIG_DEBUG_KERNEL_DC)
3272 static ssize_t
s3_debug_store(struct device
*device
,
3273 struct device_attribute
*attr
,
3279 struct drm_device
*drm_dev
= dev_get_drvdata(device
);
3280 struct amdgpu_device
*adev
= drm_dev
->dev_private
;
3282 ret
= kstrtoint(buf
, 0, &s3_state
);
3287 drm_kms_helper_hotplug_event(adev
->ddev
);
3292 return ret
== 0 ? count
: 0;
3295 DEVICE_ATTR_WO(s3_debug
);
3299 static int dm_early_init(void *handle
)
3301 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3303 switch (adev
->asic_type
) {
3306 adev
->mode_info
.num_crtc
= 6;
3307 adev
->mode_info
.num_hpd
= 6;
3308 adev
->mode_info
.num_dig
= 6;
3311 adev
->mode_info
.num_crtc
= 4;
3312 adev
->mode_info
.num_hpd
= 6;
3313 adev
->mode_info
.num_dig
= 7;
3317 adev
->mode_info
.num_crtc
= 2;
3318 adev
->mode_info
.num_hpd
= 6;
3319 adev
->mode_info
.num_dig
= 6;
3323 adev
->mode_info
.num_crtc
= 6;
3324 adev
->mode_info
.num_hpd
= 6;
3325 adev
->mode_info
.num_dig
= 7;
3328 adev
->mode_info
.num_crtc
= 3;
3329 adev
->mode_info
.num_hpd
= 6;
3330 adev
->mode_info
.num_dig
= 9;
3333 adev
->mode_info
.num_crtc
= 2;
3334 adev
->mode_info
.num_hpd
= 6;
3335 adev
->mode_info
.num_dig
= 9;
3337 case CHIP_POLARIS11
:
3338 case CHIP_POLARIS12
:
3339 adev
->mode_info
.num_crtc
= 5;
3340 adev
->mode_info
.num_hpd
= 5;
3341 adev
->mode_info
.num_dig
= 5;
3343 case CHIP_POLARIS10
:
3345 adev
->mode_info
.num_crtc
= 6;
3346 adev
->mode_info
.num_hpd
= 6;
3347 adev
->mode_info
.num_dig
= 6;
3352 adev
->mode_info
.num_crtc
= 6;
3353 adev
->mode_info
.num_hpd
= 6;
3354 adev
->mode_info
.num_dig
= 6;
3356 #if defined(CONFIG_DRM_AMD_DC_DCN)
3358 adev
->mode_info
.num_crtc
= 4;
3359 adev
->mode_info
.num_hpd
= 4;
3360 adev
->mode_info
.num_dig
= 4;
3365 adev
->mode_info
.num_crtc
= 6;
3366 adev
->mode_info
.num_hpd
= 6;
3367 adev
->mode_info
.num_dig
= 6;
3370 adev
->mode_info
.num_crtc
= 5;
3371 adev
->mode_info
.num_hpd
= 5;
3372 adev
->mode_info
.num_dig
= 5;
3375 adev
->mode_info
.num_crtc
= 4;
3376 adev
->mode_info
.num_hpd
= 4;
3377 adev
->mode_info
.num_dig
= 4;
3380 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev
->asic_type
);
3384 amdgpu_dm_set_irq_funcs(adev
);
3386 if (adev
->mode_info
.funcs
== NULL
)
3387 adev
->mode_info
.funcs
= &dm_display_funcs
;
3390 * Note: Do NOT change adev->audio_endpt_rreg and
3391 * adev->audio_endpt_wreg because they are initialised in
3392 * amdgpu_device_init()
3394 #if defined(CONFIG_DEBUG_KERNEL_DC)
3397 &dev_attr_s3_debug
);
3403 static bool modeset_required(struct drm_crtc_state
*crtc_state
,
3404 struct dc_stream_state
*new_stream
,
3405 struct dc_stream_state
*old_stream
)
3407 if (!drm_atomic_crtc_needs_modeset(crtc_state
))
3410 if (!crtc_state
->enable
)
3413 return crtc_state
->active
;
3416 static bool modereset_required(struct drm_crtc_state
*crtc_state
)
3418 if (!drm_atomic_crtc_needs_modeset(crtc_state
))
3421 return !crtc_state
->enable
|| !crtc_state
->active
;
3424 static void amdgpu_dm_encoder_destroy(struct drm_encoder
*encoder
)
3426 drm_encoder_cleanup(encoder
);
3430 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs
= {
3431 .destroy
= amdgpu_dm_encoder_destroy
,
3435 static int fill_dc_scaling_info(const struct drm_plane_state
*state
,
3436 struct dc_scaling_info
*scaling_info
)
3438 int scale_w
, scale_h
;
3440 memset(scaling_info
, 0, sizeof(*scaling_info
));
3442 /* Source is fixed 16.16 but we ignore mantissa for now... */
3443 scaling_info
->src_rect
.x
= state
->src_x
>> 16;
3444 scaling_info
->src_rect
.y
= state
->src_y
>> 16;
3446 scaling_info
->src_rect
.width
= state
->src_w
>> 16;
3447 if (scaling_info
->src_rect
.width
== 0)
3450 scaling_info
->src_rect
.height
= state
->src_h
>> 16;
3451 if (scaling_info
->src_rect
.height
== 0)
3454 scaling_info
->dst_rect
.x
= state
->crtc_x
;
3455 scaling_info
->dst_rect
.y
= state
->crtc_y
;
3457 if (state
->crtc_w
== 0)
3460 scaling_info
->dst_rect
.width
= state
->crtc_w
;
3462 if (state
->crtc_h
== 0)
3465 scaling_info
->dst_rect
.height
= state
->crtc_h
;
3467 /* DRM doesn't specify clipping on destination output. */
3468 scaling_info
->clip_rect
= scaling_info
->dst_rect
;
3470 /* TODO: Validate scaling per-format with DC plane caps */
3471 scale_w
= scaling_info
->dst_rect
.width
* 1000 /
3472 scaling_info
->src_rect
.width
;
3474 if (scale_w
< 250 || scale_w
> 16000)
3477 scale_h
= scaling_info
->dst_rect
.height
* 1000 /
3478 scaling_info
->src_rect
.height
;
3480 if (scale_h
< 250 || scale_h
> 16000)
3484 * The "scaling_quality" can be ignored for now, quality = 0 has DC
3485 * assume reasonable defaults based on the format.
3491 static int get_fb_info(const struct amdgpu_framebuffer
*amdgpu_fb
,
3492 uint64_t *tiling_flags
, bool *tmz_surface
)
3494 struct amdgpu_bo
*rbo
= gem_to_amdgpu_bo(amdgpu_fb
->base
.obj
[0]);
3495 int r
= amdgpu_bo_reserve(rbo
, false);
3498 /* Don't show error message when returning -ERESTARTSYS */
3499 if (r
!= -ERESTARTSYS
)
3500 DRM_ERROR("Unable to reserve buffer: %d\n", r
);
3505 amdgpu_bo_get_tiling_flags(rbo
, tiling_flags
);
3508 *tmz_surface
= amdgpu_bo_encrypted(rbo
);
3510 amdgpu_bo_unreserve(rbo
);
3515 static inline uint64_t get_dcc_address(uint64_t address
, uint64_t tiling_flags
)
3517 uint32_t offset
= AMDGPU_TILING_GET(tiling_flags
, DCC_OFFSET_256B
);
3519 return offset
? (address
+ offset
* 256) : 0;
3523 fill_plane_dcc_attributes(struct amdgpu_device
*adev
,
3524 const struct amdgpu_framebuffer
*afb
,
3525 const enum surface_pixel_format format
,
3526 const enum dc_rotation_angle rotation
,
3527 const struct plane_size
*plane_size
,
3528 const union dc_tiling_info
*tiling_info
,
3529 const uint64_t info
,
3530 struct dc_plane_dcc_param
*dcc
,
3531 struct dc_plane_address
*address
,
3532 bool force_disable_dcc
)
3534 struct dc
*dc
= adev
->dm
.dc
;
3535 struct dc_dcc_surface_param input
;
3536 struct dc_surface_dcc_cap output
;
3537 uint32_t offset
= AMDGPU_TILING_GET(info
, DCC_OFFSET_256B
);
3538 uint32_t i64b
= AMDGPU_TILING_GET(info
, DCC_INDEPENDENT_64B
) != 0;
3539 uint64_t dcc_address
;
3541 memset(&input
, 0, sizeof(input
));
3542 memset(&output
, 0, sizeof(output
));
3544 if (force_disable_dcc
)
3550 if (format
>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
3553 if (!dc
->cap_funcs
.get_dcc_compression_cap
)
3556 input
.format
= format
;
3557 input
.surface_size
.width
= plane_size
->surface_size
.width
;
3558 input
.surface_size
.height
= plane_size
->surface_size
.height
;
3559 input
.swizzle_mode
= tiling_info
->gfx9
.swizzle
;
3561 if (rotation
== ROTATION_ANGLE_0
|| rotation
== ROTATION_ANGLE_180
)
3562 input
.scan
= SCAN_DIRECTION_HORIZONTAL
;
3563 else if (rotation
== ROTATION_ANGLE_90
|| rotation
== ROTATION_ANGLE_270
)
3564 input
.scan
= SCAN_DIRECTION_VERTICAL
;
3566 if (!dc
->cap_funcs
.get_dcc_compression_cap(dc
, &input
, &output
))
3569 if (!output
.capable
)
3572 if (i64b
== 0 && output
.grph
.rgb
.independent_64b_blks
!= 0)
3577 AMDGPU_TILING_GET(info
, DCC_PITCH_MAX
) + 1;
3578 dcc
->independent_64b_blks
= i64b
;
3580 dcc_address
= get_dcc_address(afb
->address
, info
);
3581 address
->grph
.meta_addr
.low_part
= lower_32_bits(dcc_address
);
3582 address
->grph
.meta_addr
.high_part
= upper_32_bits(dcc_address
);
3588 fill_plane_buffer_attributes(struct amdgpu_device
*adev
,
3589 const struct amdgpu_framebuffer
*afb
,
3590 const enum surface_pixel_format format
,
3591 const enum dc_rotation_angle rotation
,
3592 const uint64_t tiling_flags
,
3593 union dc_tiling_info
*tiling_info
,
3594 struct plane_size
*plane_size
,
3595 struct dc_plane_dcc_param
*dcc
,
3596 struct dc_plane_address
*address
,
3598 bool force_disable_dcc
)
3600 const struct drm_framebuffer
*fb
= &afb
->base
;
3603 memset(tiling_info
, 0, sizeof(*tiling_info
));
3604 memset(plane_size
, 0, sizeof(*plane_size
));
3605 memset(dcc
, 0, sizeof(*dcc
));
3606 memset(address
, 0, sizeof(*address
));
3608 address
->tmz_surface
= tmz_surface
;
3610 if (format
< SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
) {
3611 plane_size
->surface_size
.x
= 0;
3612 plane_size
->surface_size
.y
= 0;
3613 plane_size
->surface_size
.width
= fb
->width
;
3614 plane_size
->surface_size
.height
= fb
->height
;
3615 plane_size
->surface_pitch
=
3616 fb
->pitches
[0] / fb
->format
->cpp
[0];
3618 address
->type
= PLN_ADDR_TYPE_GRAPHICS
;
3619 address
->grph
.addr
.low_part
= lower_32_bits(afb
->address
);
3620 address
->grph
.addr
.high_part
= upper_32_bits(afb
->address
);
3621 } else if (format
< SURFACE_PIXEL_FORMAT_INVALID
) {
3622 uint64_t chroma_addr
= afb
->address
+ fb
->offsets
[1];
3624 plane_size
->surface_size
.x
= 0;
3625 plane_size
->surface_size
.y
= 0;
3626 plane_size
->surface_size
.width
= fb
->width
;
3627 plane_size
->surface_size
.height
= fb
->height
;
3628 plane_size
->surface_pitch
=
3629 fb
->pitches
[0] / fb
->format
->cpp
[0];
3631 plane_size
->chroma_size
.x
= 0;
3632 plane_size
->chroma_size
.y
= 0;
3633 /* TODO: set these based on surface format */
3634 plane_size
->chroma_size
.width
= fb
->width
/ 2;
3635 plane_size
->chroma_size
.height
= fb
->height
/ 2;
3637 plane_size
->chroma_pitch
=
3638 fb
->pitches
[1] / fb
->format
->cpp
[1];
3640 address
->type
= PLN_ADDR_TYPE_VIDEO_PROGRESSIVE
;
3641 address
->video_progressive
.luma_addr
.low_part
=
3642 lower_32_bits(afb
->address
);
3643 address
->video_progressive
.luma_addr
.high_part
=
3644 upper_32_bits(afb
->address
);
3645 address
->video_progressive
.chroma_addr
.low_part
=
3646 lower_32_bits(chroma_addr
);
3647 address
->video_progressive
.chroma_addr
.high_part
=
3648 upper_32_bits(chroma_addr
);
3651 /* Fill GFX8 params */
3652 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == DC_ARRAY_2D_TILED_THIN1
) {
3653 unsigned int bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
3655 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
3656 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
3657 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
3658 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
3659 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
3661 /* XXX fix me for VI */
3662 tiling_info
->gfx8
.num_banks
= num_banks
;
3663 tiling_info
->gfx8
.array_mode
=
3664 DC_ARRAY_2D_TILED_THIN1
;
3665 tiling_info
->gfx8
.tile_split
= tile_split
;
3666 tiling_info
->gfx8
.bank_width
= bankw
;
3667 tiling_info
->gfx8
.bank_height
= bankh
;
3668 tiling_info
->gfx8
.tile_aspect
= mtaspect
;
3669 tiling_info
->gfx8
.tile_mode
=
3670 DC_ADDR_SURF_MICRO_TILING_DISPLAY
;
3671 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
)
3672 == DC_ARRAY_1D_TILED_THIN1
) {
3673 tiling_info
->gfx8
.array_mode
= DC_ARRAY_1D_TILED_THIN1
;
3676 tiling_info
->gfx8
.pipe_config
=
3677 AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
3679 if (adev
->asic_type
== CHIP_VEGA10
||
3680 adev
->asic_type
== CHIP_VEGA12
||
3681 adev
->asic_type
== CHIP_VEGA20
||
3682 adev
->asic_type
== CHIP_NAVI10
||
3683 adev
->asic_type
== CHIP_NAVI14
||
3684 adev
->asic_type
== CHIP_NAVI12
||
3685 adev
->asic_type
== CHIP_RENOIR
||
3686 adev
->asic_type
== CHIP_RAVEN
) {
3687 /* Fill GFX9 params */
3688 tiling_info
->gfx9
.num_pipes
=
3689 adev
->gfx
.config
.gb_addr_config_fields
.num_pipes
;
3690 tiling_info
->gfx9
.num_banks
=
3691 adev
->gfx
.config
.gb_addr_config_fields
.num_banks
;
3692 tiling_info
->gfx9
.pipe_interleave
=
3693 adev
->gfx
.config
.gb_addr_config_fields
.pipe_interleave_size
;
3694 tiling_info
->gfx9
.num_shader_engines
=
3695 adev
->gfx
.config
.gb_addr_config_fields
.num_se
;
3696 tiling_info
->gfx9
.max_compressed_frags
=
3697 adev
->gfx
.config
.gb_addr_config_fields
.max_compress_frags
;
3698 tiling_info
->gfx9
.num_rb_per_se
=
3699 adev
->gfx
.config
.gb_addr_config_fields
.num_rb_per_se
;
3700 tiling_info
->gfx9
.swizzle
=
3701 AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
3702 tiling_info
->gfx9
.shaderEnable
= 1;
3704 ret
= fill_plane_dcc_attributes(adev
, afb
, format
, rotation
,
3705 plane_size
, tiling_info
,
3706 tiling_flags
, dcc
, address
,
3716 fill_blending_from_plane_state(const struct drm_plane_state
*plane_state
,
3717 bool *per_pixel_alpha
, bool *global_alpha
,
3718 int *global_alpha_value
)
3720 *per_pixel_alpha
= false;
3721 *global_alpha
= false;
3722 *global_alpha_value
= 0xff;
3724 if (plane_state
->plane
->type
!= DRM_PLANE_TYPE_OVERLAY
)
3727 if (plane_state
->pixel_blend_mode
== DRM_MODE_BLEND_PREMULTI
) {
3728 static const uint32_t alpha_formats
[] = {
3729 DRM_FORMAT_ARGB8888
,
3730 DRM_FORMAT_RGBA8888
,
3731 DRM_FORMAT_ABGR8888
,
3733 uint32_t format
= plane_state
->fb
->format
->format
;
3736 for (i
= 0; i
< ARRAY_SIZE(alpha_formats
); ++i
) {
3737 if (format
== alpha_formats
[i
]) {
3738 *per_pixel_alpha
= true;
3744 if (plane_state
->alpha
< 0xffff) {
3745 *global_alpha
= true;
3746 *global_alpha_value
= plane_state
->alpha
>> 8;
3751 fill_plane_color_attributes(const struct drm_plane_state
*plane_state
,
3752 const enum surface_pixel_format format
,
3753 enum dc_color_space
*color_space
)
3757 *color_space
= COLOR_SPACE_SRGB
;
3759 /* DRM color properties only affect non-RGB formats. */
3760 if (format
< SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
3763 full_range
= (plane_state
->color_range
== DRM_COLOR_YCBCR_FULL_RANGE
);
3765 switch (plane_state
->color_encoding
) {
3766 case DRM_COLOR_YCBCR_BT601
:
3768 *color_space
= COLOR_SPACE_YCBCR601
;
3770 *color_space
= COLOR_SPACE_YCBCR601_LIMITED
;
3773 case DRM_COLOR_YCBCR_BT709
:
3775 *color_space
= COLOR_SPACE_YCBCR709
;
3777 *color_space
= COLOR_SPACE_YCBCR709_LIMITED
;
3780 case DRM_COLOR_YCBCR_BT2020
:
3782 *color_space
= COLOR_SPACE_2020_YCBCR
;
3795 fill_dc_plane_info_and_addr(struct amdgpu_device
*adev
,
3796 const struct drm_plane_state
*plane_state
,
3797 const uint64_t tiling_flags
,
3798 struct dc_plane_info
*plane_info
,
3799 struct dc_plane_address
*address
,
3801 bool force_disable_dcc
)
3803 const struct drm_framebuffer
*fb
= plane_state
->fb
;
3804 const struct amdgpu_framebuffer
*afb
=
3805 to_amdgpu_framebuffer(plane_state
->fb
);
3806 struct drm_format_name_buf format_name
;
3809 memset(plane_info
, 0, sizeof(*plane_info
));
3811 switch (fb
->format
->format
) {
3813 plane_info
->format
=
3814 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS
;
3816 case DRM_FORMAT_RGB565
:
3817 plane_info
->format
= SURFACE_PIXEL_FORMAT_GRPH_RGB565
;
3819 case DRM_FORMAT_XRGB8888
:
3820 case DRM_FORMAT_ARGB8888
:
3821 plane_info
->format
= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888
;
3823 case DRM_FORMAT_XRGB2101010
:
3824 case DRM_FORMAT_ARGB2101010
:
3825 plane_info
->format
= SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010
;
3827 case DRM_FORMAT_XBGR2101010
:
3828 case DRM_FORMAT_ABGR2101010
:
3829 plane_info
->format
= SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
;
3831 case DRM_FORMAT_XBGR8888
:
3832 case DRM_FORMAT_ABGR8888
:
3833 plane_info
->format
= SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
;
3835 case DRM_FORMAT_NV21
:
3836 plane_info
->format
= SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr
;
3838 case DRM_FORMAT_NV12
:
3839 plane_info
->format
= SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb
;
3841 case DRM_FORMAT_P010
:
3842 plane_info
->format
= SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb
;
3844 case DRM_FORMAT_XRGB16161616F
:
3845 case DRM_FORMAT_ARGB16161616F
:
3846 plane_info
->format
= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F
;
3848 case DRM_FORMAT_XBGR16161616F
:
3849 case DRM_FORMAT_ABGR16161616F
:
3850 plane_info
->format
= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
;
3854 "Unsupported screen format %s\n",
3855 drm_get_format_name(fb
->format
->format
, &format_name
));
3859 switch (plane_state
->rotation
& DRM_MODE_ROTATE_MASK
) {
3860 case DRM_MODE_ROTATE_0
:
3861 plane_info
->rotation
= ROTATION_ANGLE_0
;
3863 case DRM_MODE_ROTATE_90
:
3864 plane_info
->rotation
= ROTATION_ANGLE_90
;
3866 case DRM_MODE_ROTATE_180
:
3867 plane_info
->rotation
= ROTATION_ANGLE_180
;
3869 case DRM_MODE_ROTATE_270
:
3870 plane_info
->rotation
= ROTATION_ANGLE_270
;
3873 plane_info
->rotation
= ROTATION_ANGLE_0
;
3877 plane_info
->visible
= true;
3878 plane_info
->stereo_format
= PLANE_STEREO_FORMAT_NONE
;
3880 plane_info
->layer_index
= 0;
3882 ret
= fill_plane_color_attributes(plane_state
, plane_info
->format
,
3883 &plane_info
->color_space
);
3887 ret
= fill_plane_buffer_attributes(adev
, afb
, plane_info
->format
,
3888 plane_info
->rotation
, tiling_flags
,
3889 &plane_info
->tiling_info
,
3890 &plane_info
->plane_size
,
3891 &plane_info
->dcc
, address
, tmz_surface
,
3896 fill_blending_from_plane_state(
3897 plane_state
, &plane_info
->per_pixel_alpha
,
3898 &plane_info
->global_alpha
, &plane_info
->global_alpha_value
);
3903 static int fill_dc_plane_attributes(struct amdgpu_device
*adev
,
3904 struct dc_plane_state
*dc_plane_state
,
3905 struct drm_plane_state
*plane_state
,
3906 struct drm_crtc_state
*crtc_state
)
3908 struct dm_crtc_state
*dm_crtc_state
= to_dm_crtc_state(crtc_state
);
3909 const struct amdgpu_framebuffer
*amdgpu_fb
=
3910 to_amdgpu_framebuffer(plane_state
->fb
);
3911 struct dc_scaling_info scaling_info
;
3912 struct dc_plane_info plane_info
;
3913 uint64_t tiling_flags
;
3915 bool tmz_surface
= false;
3916 bool force_disable_dcc
= false;
3918 ret
= fill_dc_scaling_info(plane_state
, &scaling_info
);
3922 dc_plane_state
->src_rect
= scaling_info
.src_rect
;
3923 dc_plane_state
->dst_rect
= scaling_info
.dst_rect
;
3924 dc_plane_state
->clip_rect
= scaling_info
.clip_rect
;
3925 dc_plane_state
->scaling_quality
= scaling_info
.scaling_quality
;
3927 ret
= get_fb_info(amdgpu_fb
, &tiling_flags
, &tmz_surface
);
3931 force_disable_dcc
= adev
->asic_type
== CHIP_RAVEN
&& adev
->in_suspend
;
3932 ret
= fill_dc_plane_info_and_addr(adev
, plane_state
, tiling_flags
,
3934 &dc_plane_state
->address
,
3940 dc_plane_state
->format
= plane_info
.format
;
3941 dc_plane_state
->color_space
= plane_info
.color_space
;
3942 dc_plane_state
->format
= plane_info
.format
;
3943 dc_plane_state
->plane_size
= plane_info
.plane_size
;
3944 dc_plane_state
->rotation
= plane_info
.rotation
;
3945 dc_plane_state
->horizontal_mirror
= plane_info
.horizontal_mirror
;
3946 dc_plane_state
->stereo_format
= plane_info
.stereo_format
;
3947 dc_plane_state
->tiling_info
= plane_info
.tiling_info
;
3948 dc_plane_state
->visible
= plane_info
.visible
;
3949 dc_plane_state
->per_pixel_alpha
= plane_info
.per_pixel_alpha
;
3950 dc_plane_state
->global_alpha
= plane_info
.global_alpha
;
3951 dc_plane_state
->global_alpha_value
= plane_info
.global_alpha_value
;
3952 dc_plane_state
->dcc
= plane_info
.dcc
;
3953 dc_plane_state
->layer_index
= plane_info
.layer_index
; // Always returns 0
3956 * Always set input transfer function, since plane state is refreshed
3959 ret
= amdgpu_dm_update_plane_color_mgmt(dm_crtc_state
, dc_plane_state
);
3966 static void update_stream_scaling_settings(const struct drm_display_mode
*mode
,
3967 const struct dm_connector_state
*dm_state
,
3968 struct dc_stream_state
*stream
)
3970 enum amdgpu_rmx_type rmx_type
;
3972 struct rect src
= { 0 }; /* viewport in composition space*/
3973 struct rect dst
= { 0 }; /* stream addressable area */
3975 /* no mode. nothing to be done */
3979 /* Full screen scaling by default */
3980 src
.width
= mode
->hdisplay
;
3981 src
.height
= mode
->vdisplay
;
3982 dst
.width
= stream
->timing
.h_addressable
;
3983 dst
.height
= stream
->timing
.v_addressable
;
3986 rmx_type
= dm_state
->scaling
;
3987 if (rmx_type
== RMX_ASPECT
|| rmx_type
== RMX_OFF
) {
3988 if (src
.width
* dst
.height
<
3989 src
.height
* dst
.width
) {
3990 /* height needs less upscaling/more downscaling */
3991 dst
.width
= src
.width
*
3992 dst
.height
/ src
.height
;
3994 /* width needs less upscaling/more downscaling */
3995 dst
.height
= src
.height
*
3996 dst
.width
/ src
.width
;
3998 } else if (rmx_type
== RMX_CENTER
) {
4002 dst
.x
= (stream
->timing
.h_addressable
- dst
.width
) / 2;
4003 dst
.y
= (stream
->timing
.v_addressable
- dst
.height
) / 2;
4005 if (dm_state
->underscan_enable
) {
4006 dst
.x
+= dm_state
->underscan_hborder
/ 2;
4007 dst
.y
+= dm_state
->underscan_vborder
/ 2;
4008 dst
.width
-= dm_state
->underscan_hborder
;
4009 dst
.height
-= dm_state
->underscan_vborder
;
4016 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
4017 dst
.x
, dst
.y
, dst
.width
, dst
.height
);
4021 static enum dc_color_depth
4022 convert_color_depth_from_display_info(const struct drm_connector
*connector
,
4023 bool is_y420
, int requested_bpc
)
4030 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
4031 if (connector
->display_info
.hdmi
.y420_dc_modes
& DRM_EDID_YCBCR420_DC_48
)
4033 else if (connector
->display_info
.hdmi
.y420_dc_modes
& DRM_EDID_YCBCR420_DC_36
)
4035 else if (connector
->display_info
.hdmi
.y420_dc_modes
& DRM_EDID_YCBCR420_DC_30
)
4038 bpc
= (uint8_t)connector
->display_info
.bpc
;
4039 /* Assume 8 bpc by default if no bpc is specified. */
4040 bpc
= bpc
? bpc
: 8;
4043 if (requested_bpc
> 0) {
4045 * Cap display bpc based on the user requested value.
4047 * The value for state->max_bpc may not correctly updated
4048 * depending on when the connector gets added to the state
4049 * or if this was called outside of atomic check, so it
4050 * can't be used directly.
4052 bpc
= min_t(u8
, bpc
, requested_bpc
);
4054 /* Round down to the nearest even number. */
4055 bpc
= bpc
- (bpc
& 1);
4061 * Temporary Work around, DRM doesn't parse color depth for
4062 * EDID revision before 1.4
4063 * TODO: Fix edid parsing
4065 return COLOR_DEPTH_888
;
4067 return COLOR_DEPTH_666
;
4069 return COLOR_DEPTH_888
;
4071 return COLOR_DEPTH_101010
;
4073 return COLOR_DEPTH_121212
;
4075 return COLOR_DEPTH_141414
;
4077 return COLOR_DEPTH_161616
;
4079 return COLOR_DEPTH_UNDEFINED
;
4083 static enum dc_aspect_ratio
4084 get_aspect_ratio(const struct drm_display_mode
*mode_in
)
4086 /* 1-1 mapping, since both enums follow the HDMI spec. */
4087 return (enum dc_aspect_ratio
) mode_in
->picture_aspect_ratio
;
4090 static enum dc_color_space
4091 get_output_color_space(const struct dc_crtc_timing
*dc_crtc_timing
)
4093 enum dc_color_space color_space
= COLOR_SPACE_SRGB
;
4095 switch (dc_crtc_timing
->pixel_encoding
) {
4096 case PIXEL_ENCODING_YCBCR422
:
4097 case PIXEL_ENCODING_YCBCR444
:
4098 case PIXEL_ENCODING_YCBCR420
:
4101 * 27030khz is the separation point between HDTV and SDTV
4102 * according to HDMI spec, we use YCbCr709 and YCbCr601
4105 if (dc_crtc_timing
->pix_clk_100hz
> 270300) {
4106 if (dc_crtc_timing
->flags
.Y_ONLY
)
4108 COLOR_SPACE_YCBCR709_LIMITED
;
4110 color_space
= COLOR_SPACE_YCBCR709
;
4112 if (dc_crtc_timing
->flags
.Y_ONLY
)
4114 COLOR_SPACE_YCBCR601_LIMITED
;
4116 color_space
= COLOR_SPACE_YCBCR601
;
4121 case PIXEL_ENCODING_RGB
:
4122 color_space
= COLOR_SPACE_SRGB
;
4133 static bool adjust_colour_depth_from_display_info(
4134 struct dc_crtc_timing
*timing_out
,
4135 const struct drm_display_info
*info
)
4137 enum dc_color_depth depth
= timing_out
->display_color_depth
;
4140 normalized_clk
= timing_out
->pix_clk_100hz
/ 10;
4141 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
4142 if (timing_out
->pixel_encoding
== PIXEL_ENCODING_YCBCR420
)
4143 normalized_clk
/= 2;
4144 /* Adjusting pix clock following on HDMI spec based on colour depth */
4146 case COLOR_DEPTH_888
:
4148 case COLOR_DEPTH_101010
:
4149 normalized_clk
= (normalized_clk
* 30) / 24;
4151 case COLOR_DEPTH_121212
:
4152 normalized_clk
= (normalized_clk
* 36) / 24;
4154 case COLOR_DEPTH_161616
:
4155 normalized_clk
= (normalized_clk
* 48) / 24;
4158 /* The above depths are the only ones valid for HDMI. */
4161 if (normalized_clk
<= info
->max_tmds_clock
) {
4162 timing_out
->display_color_depth
= depth
;
4165 } while (--depth
> COLOR_DEPTH_666
);
4169 static void fill_stream_properties_from_drm_display_mode(
4170 struct dc_stream_state
*stream
,
4171 const struct drm_display_mode
*mode_in
,
4172 const struct drm_connector
*connector
,
4173 const struct drm_connector_state
*connector_state
,
4174 const struct dc_stream_state
*old_stream
,
4177 struct dc_crtc_timing
*timing_out
= &stream
->timing
;
4178 const struct drm_display_info
*info
= &connector
->display_info
;
4179 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
4180 struct hdmi_vendor_infoframe hv_frame
;
4181 struct hdmi_avi_infoframe avi_frame
;
4183 memset(&hv_frame
, 0, sizeof(hv_frame
));
4184 memset(&avi_frame
, 0, sizeof(avi_frame
));
4186 timing_out
->h_border_left
= 0;
4187 timing_out
->h_border_right
= 0;
4188 timing_out
->v_border_top
= 0;
4189 timing_out
->v_border_bottom
= 0;
4190 /* TODO: un-hardcode */
4191 if (drm_mode_is_420_only(info
, mode_in
)
4192 && stream
->signal
== SIGNAL_TYPE_HDMI_TYPE_A
)
4193 timing_out
->pixel_encoding
= PIXEL_ENCODING_YCBCR420
;
4194 else if (drm_mode_is_420_also(info
, mode_in
)
4195 && aconnector
->force_yuv420_output
)
4196 timing_out
->pixel_encoding
= PIXEL_ENCODING_YCBCR420
;
4197 else if ((connector
->display_info
.color_formats
& DRM_COLOR_FORMAT_YCRCB444
)
4198 && stream
->signal
== SIGNAL_TYPE_HDMI_TYPE_A
)
4199 timing_out
->pixel_encoding
= PIXEL_ENCODING_YCBCR444
;
4201 timing_out
->pixel_encoding
= PIXEL_ENCODING_RGB
;
4203 timing_out
->timing_3d_format
= TIMING_3D_FORMAT_NONE
;
4204 timing_out
->display_color_depth
= convert_color_depth_from_display_info(
4206 (timing_out
->pixel_encoding
== PIXEL_ENCODING_YCBCR420
),
4208 timing_out
->scan_type
= SCANNING_TYPE_NODATA
;
4209 timing_out
->hdmi_vic
= 0;
4212 timing_out
->vic
= old_stream
->timing
.vic
;
4213 timing_out
->flags
.HSYNC_POSITIVE_POLARITY
= old_stream
->timing
.flags
.HSYNC_POSITIVE_POLARITY
;
4214 timing_out
->flags
.VSYNC_POSITIVE_POLARITY
= old_stream
->timing
.flags
.VSYNC_POSITIVE_POLARITY
;
4216 timing_out
->vic
= drm_match_cea_mode(mode_in
);
4217 if (mode_in
->flags
& DRM_MODE_FLAG_PHSYNC
)
4218 timing_out
->flags
.HSYNC_POSITIVE_POLARITY
= 1;
4219 if (mode_in
->flags
& DRM_MODE_FLAG_PVSYNC
)
4220 timing_out
->flags
.VSYNC_POSITIVE_POLARITY
= 1;
4223 if (stream
->signal
== SIGNAL_TYPE_HDMI_TYPE_A
) {
4224 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame
, (struct drm_connector
*)connector
, mode_in
);
4225 timing_out
->vic
= avi_frame
.video_code
;
4226 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame
, (struct drm_connector
*)connector
, mode_in
);
4227 timing_out
->hdmi_vic
= hv_frame
.vic
;
4230 timing_out
->h_addressable
= mode_in
->crtc_hdisplay
;
4231 timing_out
->h_total
= mode_in
->crtc_htotal
;
4232 timing_out
->h_sync_width
=
4233 mode_in
->crtc_hsync_end
- mode_in
->crtc_hsync_start
;
4234 timing_out
->h_front_porch
=
4235 mode_in
->crtc_hsync_start
- mode_in
->crtc_hdisplay
;
4236 timing_out
->v_total
= mode_in
->crtc_vtotal
;
4237 timing_out
->v_addressable
= mode_in
->crtc_vdisplay
;
4238 timing_out
->v_front_porch
=
4239 mode_in
->crtc_vsync_start
- mode_in
->crtc_vdisplay
;
4240 timing_out
->v_sync_width
=
4241 mode_in
->crtc_vsync_end
- mode_in
->crtc_vsync_start
;
4242 timing_out
->pix_clk_100hz
= mode_in
->crtc_clock
* 10;
4243 timing_out
->aspect_ratio
= get_aspect_ratio(mode_in
);
4245 stream
->output_color_space
= get_output_color_space(timing_out
);
4247 stream
->out_transfer_func
->type
= TF_TYPE_PREDEFINED
;
4248 stream
->out_transfer_func
->tf
= TRANSFER_FUNCTION_SRGB
;
4249 if (stream
->signal
== SIGNAL_TYPE_HDMI_TYPE_A
) {
4250 if (!adjust_colour_depth_from_display_info(timing_out
, info
) &&
4251 drm_mode_is_420_also(info
, mode_in
) &&
4252 timing_out
->pixel_encoding
!= PIXEL_ENCODING_YCBCR420
) {
4253 timing_out
->pixel_encoding
= PIXEL_ENCODING_YCBCR420
;
4254 adjust_colour_depth_from_display_info(timing_out
, info
);
4259 static void fill_audio_info(struct audio_info
*audio_info
,
4260 const struct drm_connector
*drm_connector
,
4261 const struct dc_sink
*dc_sink
)
4264 int cea_revision
= 0;
4265 const struct dc_edid_caps
*edid_caps
= &dc_sink
->edid_caps
;
4267 audio_info
->manufacture_id
= edid_caps
->manufacturer_id
;
4268 audio_info
->product_id
= edid_caps
->product_id
;
4270 cea_revision
= drm_connector
->display_info
.cea_rev
;
4272 strscpy(audio_info
->display_name
,
4273 edid_caps
->display_name
,
4274 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS
);
4276 if (cea_revision
>= 3) {
4277 audio_info
->mode_count
= edid_caps
->audio_mode_count
;
4279 for (i
= 0; i
< audio_info
->mode_count
; ++i
) {
4280 audio_info
->modes
[i
].format_code
=
4281 (enum audio_format_code
)
4282 (edid_caps
->audio_modes
[i
].format_code
);
4283 audio_info
->modes
[i
].channel_count
=
4284 edid_caps
->audio_modes
[i
].channel_count
;
4285 audio_info
->modes
[i
].sample_rates
.all
=
4286 edid_caps
->audio_modes
[i
].sample_rate
;
4287 audio_info
->modes
[i
].sample_size
=
4288 edid_caps
->audio_modes
[i
].sample_size
;
4292 audio_info
->flags
.all
= edid_caps
->speaker_flags
;
4294 /* TODO: We only check for the progressive mode, check for interlace mode too */
4295 if (drm_connector
->latency_present
[0]) {
4296 audio_info
->video_latency
= drm_connector
->video_latency
[0];
4297 audio_info
->audio_latency
= drm_connector
->audio_latency
[0];
4300 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
4305 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode
*src_mode
,
4306 struct drm_display_mode
*dst_mode
)
4308 dst_mode
->crtc_hdisplay
= src_mode
->crtc_hdisplay
;
4309 dst_mode
->crtc_vdisplay
= src_mode
->crtc_vdisplay
;
4310 dst_mode
->crtc_clock
= src_mode
->crtc_clock
;
4311 dst_mode
->crtc_hblank_start
= src_mode
->crtc_hblank_start
;
4312 dst_mode
->crtc_hblank_end
= src_mode
->crtc_hblank_end
;
4313 dst_mode
->crtc_hsync_start
= src_mode
->crtc_hsync_start
;
4314 dst_mode
->crtc_hsync_end
= src_mode
->crtc_hsync_end
;
4315 dst_mode
->crtc_htotal
= src_mode
->crtc_htotal
;
4316 dst_mode
->crtc_hskew
= src_mode
->crtc_hskew
;
4317 dst_mode
->crtc_vblank_start
= src_mode
->crtc_vblank_start
;
4318 dst_mode
->crtc_vblank_end
= src_mode
->crtc_vblank_end
;
4319 dst_mode
->crtc_vsync_start
= src_mode
->crtc_vsync_start
;
4320 dst_mode
->crtc_vsync_end
= src_mode
->crtc_vsync_end
;
4321 dst_mode
->crtc_vtotal
= src_mode
->crtc_vtotal
;
4325 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode
*drm_mode
,
4326 const struct drm_display_mode
*native_mode
,
4329 if (scale_enabled
) {
4330 copy_crtc_timing_for_drm_display_mode(native_mode
, drm_mode
);
4331 } else if (native_mode
->clock
== drm_mode
->clock
&&
4332 native_mode
->htotal
== drm_mode
->htotal
&&
4333 native_mode
->vtotal
== drm_mode
->vtotal
) {
4334 copy_crtc_timing_for_drm_display_mode(native_mode
, drm_mode
);
4336 /* no scaling nor amdgpu inserted, no need to patch */
4340 static struct dc_sink
*
4341 create_fake_sink(struct amdgpu_dm_connector
*aconnector
)
4343 struct dc_sink_init_data sink_init_data
= { 0 };
4344 struct dc_sink
*sink
= NULL
;
4345 sink_init_data
.link
= aconnector
->dc_link
;
4346 sink_init_data
.sink_signal
= aconnector
->dc_link
->connector_signal
;
4348 sink
= dc_sink_create(&sink_init_data
);
4350 DRM_ERROR("Failed to create sink!\n");
4353 sink
->sink_signal
= SIGNAL_TYPE_VIRTUAL
;
4358 static void set_multisync_trigger_params(
4359 struct dc_stream_state
*stream
)
4361 if (stream
->triggered_crtc_reset
.enabled
) {
4362 stream
->triggered_crtc_reset
.event
= CRTC_EVENT_VSYNC_RISING
;
4363 stream
->triggered_crtc_reset
.delay
= TRIGGER_DELAY_NEXT_LINE
;
4367 static void set_master_stream(struct dc_stream_state
*stream_set
[],
4370 int j
, highest_rfr
= 0, master_stream
= 0;
4372 for (j
= 0; j
< stream_count
; j
++) {
4373 if (stream_set
[j
] && stream_set
[j
]->triggered_crtc_reset
.enabled
) {
4374 int refresh_rate
= 0;
4376 refresh_rate
= (stream_set
[j
]->timing
.pix_clk_100hz
*100)/
4377 (stream_set
[j
]->timing
.h_total
*stream_set
[j
]->timing
.v_total
);
4378 if (refresh_rate
> highest_rfr
) {
4379 highest_rfr
= refresh_rate
;
4384 for (j
= 0; j
< stream_count
; j
++) {
4386 stream_set
[j
]->triggered_crtc_reset
.event_source
= stream_set
[master_stream
];
4390 static void dm_enable_per_frame_crtc_master_sync(struct dc_state
*context
)
4394 if (context
->stream_count
< 2)
4396 for (i
= 0; i
< context
->stream_count
; i
++) {
4397 if (!context
->streams
[i
])
4400 * TODO: add a function to read AMD VSDB bits and set
4401 * crtc_sync_master.multi_sync_enabled flag
4402 * For now it's set to false
4404 set_multisync_trigger_params(context
->streams
[i
]);
4406 set_master_stream(context
->streams
, context
->stream_count
);
4409 static struct dc_stream_state
*
4410 create_stream_for_sink(struct amdgpu_dm_connector
*aconnector
,
4411 const struct drm_display_mode
*drm_mode
,
4412 const struct dm_connector_state
*dm_state
,
4413 const struct dc_stream_state
*old_stream
,
4416 struct drm_display_mode
*preferred_mode
= NULL
;
4417 struct drm_connector
*drm_connector
;
4418 const struct drm_connector_state
*con_state
=
4419 dm_state
? &dm_state
->base
: NULL
;
4420 struct dc_stream_state
*stream
= NULL
;
4421 struct drm_display_mode mode
= *drm_mode
;
4422 bool native_mode_found
= false;
4423 bool scale
= dm_state
? (dm_state
->scaling
!= RMX_OFF
) : false;
4425 int preferred_refresh
= 0;
4426 #if defined(CONFIG_DRM_AMD_DC_DCN)
4427 struct dsc_dec_dpcd_caps dsc_caps
;
4429 uint32_t link_bandwidth_kbps
;
4431 struct dc_sink
*sink
= NULL
;
4432 if (aconnector
== NULL
) {
4433 DRM_ERROR("aconnector is NULL!\n");
4437 drm_connector
= &aconnector
->base
;
4439 if (!aconnector
->dc_sink
) {
4440 sink
= create_fake_sink(aconnector
);
4444 sink
= aconnector
->dc_sink
;
4445 dc_sink_retain(sink
);
4448 stream
= dc_create_stream_for_sink(sink
);
4450 if (stream
== NULL
) {
4451 DRM_ERROR("Failed to create stream for sink!\n");
4455 stream
->dm_stream_context
= aconnector
;
4457 stream
->timing
.flags
.LTE_340MCSC_SCRAMBLE
=
4458 drm_connector
->display_info
.hdmi
.scdc
.scrambling
.low_rates
;
4460 list_for_each_entry(preferred_mode
, &aconnector
->base
.modes
, head
) {
4461 /* Search for preferred mode */
4462 if (preferred_mode
->type
& DRM_MODE_TYPE_PREFERRED
) {
4463 native_mode_found
= true;
4467 if (!native_mode_found
)
4468 preferred_mode
= list_first_entry_or_null(
4469 &aconnector
->base
.modes
,
4470 struct drm_display_mode
,
4473 mode_refresh
= drm_mode_vrefresh(&mode
);
4475 if (preferred_mode
== NULL
) {
4477 * This may not be an error, the use case is when we have no
4478 * usermode calls to reset and set mode upon hotplug. In this
4479 * case, we call set mode ourselves to restore the previous mode
4480 * and the modelist may not be filled in in time.
4482 DRM_DEBUG_DRIVER("No preferred mode found\n");
4484 decide_crtc_timing_for_drm_display_mode(
4485 &mode
, preferred_mode
,
4486 dm_state
? (dm_state
->scaling
!= RMX_OFF
) : false);
4487 preferred_refresh
= drm_mode_vrefresh(preferred_mode
);
4491 drm_mode_set_crtcinfo(&mode
, 0);
4494 * If scaling is enabled and refresh rate didn't change
4495 * we copy the vic and polarities of the old timings
4497 if (!scale
|| mode_refresh
!= preferred_refresh
)
4498 fill_stream_properties_from_drm_display_mode(stream
,
4499 &mode
, &aconnector
->base
, con_state
, NULL
, requested_bpc
);
4501 fill_stream_properties_from_drm_display_mode(stream
,
4502 &mode
, &aconnector
->base
, con_state
, old_stream
, requested_bpc
);
4504 stream
->timing
.flags
.DSC
= 0;
4506 if (aconnector
->dc_link
&& sink
->sink_signal
== SIGNAL_TYPE_DISPLAY_PORT
) {
4507 #if defined(CONFIG_DRM_AMD_DC_DCN)
4508 dc_dsc_parse_dsc_dpcd(aconnector
->dc_link
->ctx
->dc
,
4509 aconnector
->dc_link
->dpcd_caps
.dsc_caps
.dsc_basic_caps
.raw
,
4510 aconnector
->dc_link
->dpcd_caps
.dsc_caps
.dsc_ext_caps
.raw
,
4513 link_bandwidth_kbps
= dc_link_bandwidth_kbps(aconnector
->dc_link
,
4514 dc_link_get_link_cap(aconnector
->dc_link
));
4516 #if defined(CONFIG_DRM_AMD_DC_DCN)
4517 if (dsc_caps
.is_dsc_supported
)
4518 if (dc_dsc_compute_config(aconnector
->dc_link
->ctx
->dc
->res_pool
->dscs
[0],
4520 aconnector
->dc_link
->ctx
->dc
->debug
.dsc_min_slice_height_override
,
4521 link_bandwidth_kbps
,
4523 &stream
->timing
.dsc_cfg
))
4524 stream
->timing
.flags
.DSC
= 1;
4528 update_stream_scaling_settings(&mode
, dm_state
, stream
);
4531 &stream
->audio_info
,
4535 update_stream_signal(stream
, sink
);
4537 if (stream
->signal
== SIGNAL_TYPE_HDMI_TYPE_A
)
4538 mod_build_hf_vsif_infopacket(stream
, &stream
->vsp_infopacket
, false, false);
4539 if (stream
->link
->psr_settings
.psr_feature_enabled
) {
4540 struct dc
*core_dc
= stream
->link
->ctx
->dc
;
4542 if (dc_is_dmcu_initialized(core_dc
)) {
4544 // should decide stream support vsc sdp colorimetry capability
4545 // before building vsc info packet
4547 stream
->use_vsc_sdp_for_colorimetry
= false;
4548 if (aconnector
->dc_sink
->sink_signal
== SIGNAL_TYPE_DISPLAY_PORT_MST
) {
4549 stream
->use_vsc_sdp_for_colorimetry
=
4550 aconnector
->dc_sink
->is_vsc_sdp_colorimetry_supported
;
4552 if (stream
->link
->dpcd_caps
.dpcd_rev
.raw
>= 0x14 &&
4553 stream
->link
->dpcd_caps
.dprx_feature
.bits
.VSC_SDP_COLORIMETRY_SUPPORTED
) {
4554 stream
->use_vsc_sdp_for_colorimetry
= true;
4557 mod_build_vsc_infopacket(stream
, &stream
->vsc_infopacket
);
4561 dc_sink_release(sink
);
4566 static void amdgpu_dm_crtc_destroy(struct drm_crtc
*crtc
)
4568 drm_crtc_cleanup(crtc
);
4572 static void dm_crtc_destroy_state(struct drm_crtc
*crtc
,
4573 struct drm_crtc_state
*state
)
4575 struct dm_crtc_state
*cur
= to_dm_crtc_state(state
);
4577 /* TODO Destroy dc_stream objects are stream object is flattened */
4579 dc_stream_release(cur
->stream
);
4582 __drm_atomic_helper_crtc_destroy_state(state
);
4588 static void dm_crtc_reset_state(struct drm_crtc
*crtc
)
4590 struct dm_crtc_state
*state
;
4593 dm_crtc_destroy_state(crtc
, crtc
->state
);
4595 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
4596 if (WARN_ON(!state
))
4599 crtc
->state
= &state
->base
;
4600 crtc
->state
->crtc
= crtc
;
4604 static struct drm_crtc_state
*
4605 dm_crtc_duplicate_state(struct drm_crtc
*crtc
)
4607 struct dm_crtc_state
*state
, *cur
;
4609 cur
= to_dm_crtc_state(crtc
->state
);
4611 if (WARN_ON(!crtc
->state
))
4614 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
4618 __drm_atomic_helper_crtc_duplicate_state(crtc
, &state
->base
);
4621 state
->stream
= cur
->stream
;
4622 dc_stream_retain(state
->stream
);
4625 state
->active_planes
= cur
->active_planes
;
4626 state
->interrupts_enabled
= cur
->interrupts_enabled
;
4627 state
->vrr_params
= cur
->vrr_params
;
4628 state
->vrr_infopacket
= cur
->vrr_infopacket
;
4629 state
->abm_level
= cur
->abm_level
;
4630 state
->vrr_supported
= cur
->vrr_supported
;
4631 state
->freesync_config
= cur
->freesync_config
;
4632 state
->crc_src
= cur
->crc_src
;
4633 state
->cm_has_degamma
= cur
->cm_has_degamma
;
4634 state
->cm_is_degamma_srgb
= cur
->cm_is_degamma_srgb
;
4636 /* TODO Duplicate dc_stream after objects are stream object is flattened */
4638 return &state
->base
;
4641 static inline int dm_set_vupdate_irq(struct drm_crtc
*crtc
, bool enable
)
4643 enum dc_irq_source irq_source
;
4644 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
4645 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
4648 irq_source
= IRQ_TYPE_VUPDATE
+ acrtc
->otg_inst
;
4650 rc
= dc_interrupt_set(adev
->dm
.dc
, irq_source
, enable
) ? 0 : -EBUSY
;
4652 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
4653 acrtc
->crtc_id
, enable
? "en" : "dis", rc
);
4657 static inline int dm_set_vblank(struct drm_crtc
*crtc
, bool enable
)
4659 enum dc_irq_source irq_source
;
4660 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
4661 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
4662 struct dm_crtc_state
*acrtc_state
= to_dm_crtc_state(crtc
->state
);
4666 /* vblank irq on -> Only need vupdate irq in vrr mode */
4667 if (amdgpu_dm_vrr_active(acrtc_state
))
4668 rc
= dm_set_vupdate_irq(crtc
, true);
4670 /* vblank irq off -> vupdate irq off */
4671 rc
= dm_set_vupdate_irq(crtc
, false);
4677 irq_source
= IRQ_TYPE_VBLANK
+ acrtc
->otg_inst
;
4678 return dc_interrupt_set(adev
->dm
.dc
, irq_source
, enable
) ? 0 : -EBUSY
;
4681 static int dm_enable_vblank(struct drm_crtc
*crtc
)
4683 return dm_set_vblank(crtc
, true);
4686 static void dm_disable_vblank(struct drm_crtc
*crtc
)
4688 dm_set_vblank(crtc
, false);
4691 /* Implemented only the options currently availible for the driver */
4692 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs
= {
4693 .reset
= dm_crtc_reset_state
,
4694 .destroy
= amdgpu_dm_crtc_destroy
,
4695 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
4696 .set_config
= drm_atomic_helper_set_config
,
4697 .page_flip
= drm_atomic_helper_page_flip
,
4698 .atomic_duplicate_state
= dm_crtc_duplicate_state
,
4699 .atomic_destroy_state
= dm_crtc_destroy_state
,
4700 .set_crc_source
= amdgpu_dm_crtc_set_crc_source
,
4701 .verify_crc_source
= amdgpu_dm_crtc_verify_crc_source
,
4702 .get_crc_sources
= amdgpu_dm_crtc_get_crc_sources
,
4703 .get_vblank_counter
= amdgpu_get_vblank_counter_kms
,
4704 .enable_vblank
= dm_enable_vblank
,
4705 .disable_vblank
= dm_disable_vblank
,
4706 .get_vblank_timestamp
= drm_crtc_vblank_helper_get_vblank_timestamp
,
4709 static enum drm_connector_status
4710 amdgpu_dm_connector_detect(struct drm_connector
*connector
, bool force
)
4713 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
4717 * 1. This interface is NOT called in context of HPD irq.
4718 * 2. This interface *is called* in context of user-mode ioctl. Which
4719 * makes it a bad place for *any* MST-related activity.
4722 if (aconnector
->base
.force
== DRM_FORCE_UNSPECIFIED
&&
4723 !aconnector
->fake_enable
)
4724 connected
= (aconnector
->dc_sink
!= NULL
);
4726 connected
= (aconnector
->base
.force
== DRM_FORCE_ON
);
4728 return (connected
? connector_status_connected
:
4729 connector_status_disconnected
);
4732 int amdgpu_dm_connector_atomic_set_property(struct drm_connector
*connector
,
4733 struct drm_connector_state
*connector_state
,
4734 struct drm_property
*property
,
4737 struct drm_device
*dev
= connector
->dev
;
4738 struct amdgpu_device
*adev
= dev
->dev_private
;
4739 struct dm_connector_state
*dm_old_state
=
4740 to_dm_connector_state(connector
->state
);
4741 struct dm_connector_state
*dm_new_state
=
4742 to_dm_connector_state(connector_state
);
4746 if (property
== dev
->mode_config
.scaling_mode_property
) {
4747 enum amdgpu_rmx_type rmx_type
;
4750 case DRM_MODE_SCALE_CENTER
:
4751 rmx_type
= RMX_CENTER
;
4753 case DRM_MODE_SCALE_ASPECT
:
4754 rmx_type
= RMX_ASPECT
;
4756 case DRM_MODE_SCALE_FULLSCREEN
:
4757 rmx_type
= RMX_FULL
;
4759 case DRM_MODE_SCALE_NONE
:
4765 if (dm_old_state
->scaling
== rmx_type
)
4768 dm_new_state
->scaling
= rmx_type
;
4770 } else if (property
== adev
->mode_info
.underscan_hborder_property
) {
4771 dm_new_state
->underscan_hborder
= val
;
4773 } else if (property
== adev
->mode_info
.underscan_vborder_property
) {
4774 dm_new_state
->underscan_vborder
= val
;
4776 } else if (property
== adev
->mode_info
.underscan_property
) {
4777 dm_new_state
->underscan_enable
= val
;
4779 } else if (property
== adev
->mode_info
.abm_level_property
) {
4780 dm_new_state
->abm_level
= val
;
4787 int amdgpu_dm_connector_atomic_get_property(struct drm_connector
*connector
,
4788 const struct drm_connector_state
*state
,
4789 struct drm_property
*property
,
4792 struct drm_device
*dev
= connector
->dev
;
4793 struct amdgpu_device
*adev
= dev
->dev_private
;
4794 struct dm_connector_state
*dm_state
=
4795 to_dm_connector_state(state
);
4798 if (property
== dev
->mode_config
.scaling_mode_property
) {
4799 switch (dm_state
->scaling
) {
4801 *val
= DRM_MODE_SCALE_CENTER
;
4804 *val
= DRM_MODE_SCALE_ASPECT
;
4807 *val
= DRM_MODE_SCALE_FULLSCREEN
;
4811 *val
= DRM_MODE_SCALE_NONE
;
4815 } else if (property
== adev
->mode_info
.underscan_hborder_property
) {
4816 *val
= dm_state
->underscan_hborder
;
4818 } else if (property
== adev
->mode_info
.underscan_vborder_property
) {
4819 *val
= dm_state
->underscan_vborder
;
4821 } else if (property
== adev
->mode_info
.underscan_property
) {
4822 *val
= dm_state
->underscan_enable
;
4824 } else if (property
== adev
->mode_info
.abm_level_property
) {
4825 *val
= dm_state
->abm_level
;
4832 static void amdgpu_dm_connector_unregister(struct drm_connector
*connector
)
4834 struct amdgpu_dm_connector
*amdgpu_dm_connector
= to_amdgpu_dm_connector(connector
);
4836 drm_dp_aux_unregister(&amdgpu_dm_connector
->dm_dp_aux
.aux
);
4839 static void amdgpu_dm_connector_destroy(struct drm_connector
*connector
)
4841 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
4842 const struct dc_link
*link
= aconnector
->dc_link
;
4843 struct amdgpu_device
*adev
= connector
->dev
->dev_private
;
4844 struct amdgpu_display_manager
*dm
= &adev
->dm
;
4846 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
4847 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
4849 if ((link
->connector_signal
& (SIGNAL_TYPE_EDP
| SIGNAL_TYPE_LVDS
)) &&
4850 link
->type
!= dc_connection_none
&&
4851 dm
->backlight_dev
) {
4852 backlight_device_unregister(dm
->backlight_dev
);
4853 dm
->backlight_dev
= NULL
;
4857 if (aconnector
->dc_em_sink
)
4858 dc_sink_release(aconnector
->dc_em_sink
);
4859 aconnector
->dc_em_sink
= NULL
;
4860 if (aconnector
->dc_sink
)
4861 dc_sink_release(aconnector
->dc_sink
);
4862 aconnector
->dc_sink
= NULL
;
4864 drm_dp_cec_unregister_connector(&aconnector
->dm_dp_aux
.aux
);
4865 drm_connector_unregister(connector
);
4866 drm_connector_cleanup(connector
);
4867 if (aconnector
->i2c
) {
4868 i2c_del_adapter(&aconnector
->i2c
->base
);
4869 kfree(aconnector
->i2c
);
4871 kfree(aconnector
->dm_dp_aux
.aux
.name
);
4876 void amdgpu_dm_connector_funcs_reset(struct drm_connector
*connector
)
4878 struct dm_connector_state
*state
=
4879 to_dm_connector_state(connector
->state
);
4881 if (connector
->state
)
4882 __drm_atomic_helper_connector_destroy_state(connector
->state
);
4886 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
4889 state
->scaling
= RMX_OFF
;
4890 state
->underscan_enable
= false;
4891 state
->underscan_hborder
= 0;
4892 state
->underscan_vborder
= 0;
4893 state
->base
.max_requested_bpc
= 8;
4894 state
->vcpi_slots
= 0;
4896 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4897 state
->abm_level
= amdgpu_dm_abm_level
;
4899 __drm_atomic_helper_connector_reset(connector
, &state
->base
);
4903 struct drm_connector_state
*
4904 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector
*connector
)
4906 struct dm_connector_state
*state
=
4907 to_dm_connector_state(connector
->state
);
4909 struct dm_connector_state
*new_state
=
4910 kmemdup(state
, sizeof(*state
), GFP_KERNEL
);
4915 __drm_atomic_helper_connector_duplicate_state(connector
, &new_state
->base
);
4917 new_state
->freesync_capable
= state
->freesync_capable
;
4918 new_state
->abm_level
= state
->abm_level
;
4919 new_state
->scaling
= state
->scaling
;
4920 new_state
->underscan_enable
= state
->underscan_enable
;
4921 new_state
->underscan_hborder
= state
->underscan_hborder
;
4922 new_state
->underscan_vborder
= state
->underscan_vborder
;
4923 new_state
->vcpi_slots
= state
->vcpi_slots
;
4924 new_state
->pbn
= state
->pbn
;
4925 return &new_state
->base
;
4929 amdgpu_dm_connector_late_register(struct drm_connector
*connector
)
4931 struct amdgpu_dm_connector
*amdgpu_dm_connector
=
4932 to_amdgpu_dm_connector(connector
);
4935 if ((connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
) ||
4936 (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)) {
4937 amdgpu_dm_connector
->dm_dp_aux
.aux
.dev
= connector
->kdev
;
4938 r
= drm_dp_aux_register(&amdgpu_dm_connector
->dm_dp_aux
.aux
);
4943 #if defined(CONFIG_DEBUG_FS)
4944 connector_debugfs_init(amdgpu_dm_connector
);
4950 static const struct drm_connector_funcs amdgpu_dm_connector_funcs
= {
4951 .reset
= amdgpu_dm_connector_funcs_reset
,
4952 .detect
= amdgpu_dm_connector_detect
,
4953 .fill_modes
= drm_helper_probe_single_connector_modes
,
4954 .destroy
= amdgpu_dm_connector_destroy
,
4955 .atomic_duplicate_state
= amdgpu_dm_connector_atomic_duplicate_state
,
4956 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4957 .atomic_set_property
= amdgpu_dm_connector_atomic_set_property
,
4958 .atomic_get_property
= amdgpu_dm_connector_atomic_get_property
,
4959 .late_register
= amdgpu_dm_connector_late_register
,
4960 .early_unregister
= amdgpu_dm_connector_unregister
4963 static int get_modes(struct drm_connector
*connector
)
4965 return amdgpu_dm_connector_get_modes(connector
);
4968 static void create_eml_sink(struct amdgpu_dm_connector
*aconnector
)
4970 struct dc_sink_init_data init_params
= {
4971 .link
= aconnector
->dc_link
,
4972 .sink_signal
= SIGNAL_TYPE_VIRTUAL
4976 if (!aconnector
->base
.edid_blob_ptr
) {
4977 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
4978 aconnector
->base
.name
);
4980 aconnector
->base
.force
= DRM_FORCE_OFF
;
4981 aconnector
->base
.override_edid
= false;
4985 edid
= (struct edid
*) aconnector
->base
.edid_blob_ptr
->data
;
4987 aconnector
->edid
= edid
;
4989 aconnector
->dc_em_sink
= dc_link_add_remote_sink(
4990 aconnector
->dc_link
,
4992 (edid
->extensions
+ 1) * EDID_LENGTH
,
4995 if (aconnector
->base
.force
== DRM_FORCE_ON
) {
4996 aconnector
->dc_sink
= aconnector
->dc_link
->local_sink
?
4997 aconnector
->dc_link
->local_sink
:
4998 aconnector
->dc_em_sink
;
4999 dc_sink_retain(aconnector
->dc_sink
);
5003 static void handle_edid_mgmt(struct amdgpu_dm_connector
*aconnector
)
5005 struct dc_link
*link
= (struct dc_link
*)aconnector
->dc_link
;
5008 * In case of headless boot with force on for DP managed connector
5009 * Those settings have to be != 0 to get initial modeset
5011 if (link
->connector_signal
== SIGNAL_TYPE_DISPLAY_PORT
) {
5012 link
->verified_link_cap
.lane_count
= LANE_COUNT_FOUR
;
5013 link
->verified_link_cap
.link_rate
= LINK_RATE_HIGH2
;
5017 aconnector
->base
.override_edid
= true;
5018 create_eml_sink(aconnector
);
5021 static struct dc_stream_state
*
5022 create_validate_stream_for_sink(struct amdgpu_dm_connector
*aconnector
,
5023 const struct drm_display_mode
*drm_mode
,
5024 const struct dm_connector_state
*dm_state
,
5025 const struct dc_stream_state
*old_stream
)
5027 struct drm_connector
*connector
= &aconnector
->base
;
5028 struct amdgpu_device
*adev
= connector
->dev
->dev_private
;
5029 struct dc_stream_state
*stream
;
5030 int requested_bpc
= connector
->state
? connector
->state
->max_requested_bpc
: 8;
5031 enum dc_status dc_result
= DC_OK
;
5034 stream
= create_stream_for_sink(aconnector
, drm_mode
,
5035 dm_state
, old_stream
,
5037 if (stream
== NULL
) {
5038 DRM_ERROR("Failed to create stream for sink!\n");
5042 dc_result
= dc_validate_stream(adev
->dm
.dc
, stream
);
5044 if (dc_result
!= DC_OK
) {
5045 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
5051 dc_stream_release(stream
);
5053 requested_bpc
-= 2; /* lower bpc to retry validation */
5056 } while (stream
== NULL
&& requested_bpc
>= 6);
5061 enum drm_mode_status
amdgpu_dm_connector_mode_valid(struct drm_connector
*connector
,
5062 struct drm_display_mode
*mode
)
5064 int result
= MODE_ERROR
;
5065 struct dc_sink
*dc_sink
;
5066 /* TODO: Unhardcode stream count */
5067 struct dc_stream_state
*stream
;
5068 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
5070 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
5071 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
))
5075 * Only run this the first time mode_valid is called to initilialize
5078 if (aconnector
->base
.force
!= DRM_FORCE_UNSPECIFIED
&&
5079 !aconnector
->dc_em_sink
)
5080 handle_edid_mgmt(aconnector
);
5082 dc_sink
= to_amdgpu_dm_connector(connector
)->dc_sink
;
5084 if (dc_sink
== NULL
) {
5085 DRM_ERROR("dc_sink is NULL!\n");
5089 stream
= create_validate_stream_for_sink(aconnector
, mode
, NULL
, NULL
);
5091 dc_stream_release(stream
);
5096 /* TODO: error handling*/
5100 static int fill_hdr_info_packet(const struct drm_connector_state
*state
,
5101 struct dc_info_packet
*out
)
5103 struct hdmi_drm_infoframe frame
;
5104 unsigned char buf
[30]; /* 26 + 4 */
5108 memset(out
, 0, sizeof(*out
));
5110 if (!state
->hdr_output_metadata
)
5113 ret
= drm_hdmi_infoframe_set_hdr_metadata(&frame
, state
);
5117 len
= hdmi_drm_infoframe_pack_only(&frame
, buf
, sizeof(buf
));
5121 /* Static metadata is a fixed 26 bytes + 4 byte header. */
5125 /* Prepare the infopacket for DC. */
5126 switch (state
->connector
->connector_type
) {
5127 case DRM_MODE_CONNECTOR_HDMIA
:
5128 out
->hb0
= 0x87; /* type */
5129 out
->hb1
= 0x01; /* version */
5130 out
->hb2
= 0x1A; /* length */
5131 out
->sb
[0] = buf
[3]; /* checksum */
5135 case DRM_MODE_CONNECTOR_DisplayPort
:
5136 case DRM_MODE_CONNECTOR_eDP
:
5137 out
->hb0
= 0x00; /* sdp id, zero */
5138 out
->hb1
= 0x87; /* type */
5139 out
->hb2
= 0x1D; /* payload len - 1 */
5140 out
->hb3
= (0x13 << 2); /* sdp version */
5141 out
->sb
[0] = 0x01; /* version */
5142 out
->sb
[1] = 0x1A; /* length */
5150 memcpy(&out
->sb
[i
], &buf
[4], 26);
5153 print_hex_dump(KERN_DEBUG
, "HDR SB:", DUMP_PREFIX_NONE
, 16, 1, out
->sb
,
5154 sizeof(out
->sb
), false);
5160 is_hdr_metadata_different(const struct drm_connector_state
*old_state
,
5161 const struct drm_connector_state
*new_state
)
5163 struct drm_property_blob
*old_blob
= old_state
->hdr_output_metadata
;
5164 struct drm_property_blob
*new_blob
= new_state
->hdr_output_metadata
;
5166 if (old_blob
!= new_blob
) {
5167 if (old_blob
&& new_blob
&&
5168 old_blob
->length
== new_blob
->length
)
5169 return memcmp(old_blob
->data
, new_blob
->data
,
5179 amdgpu_dm_connector_atomic_check(struct drm_connector
*conn
,
5180 struct drm_atomic_state
*state
)
5182 struct drm_connector_state
*new_con_state
=
5183 drm_atomic_get_new_connector_state(state
, conn
);
5184 struct drm_connector_state
*old_con_state
=
5185 drm_atomic_get_old_connector_state(state
, conn
);
5186 struct drm_crtc
*crtc
= new_con_state
->crtc
;
5187 struct drm_crtc_state
*new_crtc_state
;
5193 if (is_hdr_metadata_different(old_con_state
, new_con_state
)) {
5194 struct dc_info_packet hdr_infopacket
;
5196 ret
= fill_hdr_info_packet(new_con_state
, &hdr_infopacket
);
5200 new_crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
5201 if (IS_ERR(new_crtc_state
))
5202 return PTR_ERR(new_crtc_state
);
5205 * DC considers the stream backends changed if the
5206 * static metadata changes. Forcing the modeset also
5207 * gives a simple way for userspace to switch from
5208 * 8bpc to 10bpc when setting the metadata to enter
5211 * Changing the static metadata after it's been
5212 * set is permissible, however. So only force a
5213 * modeset if we're entering or exiting HDR.
5215 new_crtc_state
->mode_changed
=
5216 !old_con_state
->hdr_output_metadata
||
5217 !new_con_state
->hdr_output_metadata
;
5223 static const struct drm_connector_helper_funcs
5224 amdgpu_dm_connector_helper_funcs
= {
5226 * If hotplugging a second bigger display in FB Con mode, bigger resolution
5227 * modes will be filtered by drm_mode_validate_size(), and those modes
5228 * are missing after user start lightdm. So we need to renew modes list.
5229 * in get_modes call back, not just return the modes count
5231 .get_modes
= get_modes
,
5232 .mode_valid
= amdgpu_dm_connector_mode_valid
,
5233 .atomic_check
= amdgpu_dm_connector_atomic_check
,
5236 static void dm_crtc_helper_disable(struct drm_crtc
*crtc
)
5240 static bool does_crtc_have_active_cursor(struct drm_crtc_state
*new_crtc_state
)
5242 struct drm_device
*dev
= new_crtc_state
->crtc
->dev
;
5243 struct drm_plane
*plane
;
5245 drm_for_each_plane_mask(plane
, dev
, new_crtc_state
->plane_mask
) {
5246 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
5253 static int count_crtc_active_planes(struct drm_crtc_state
*new_crtc_state
)
5255 struct drm_atomic_state
*state
= new_crtc_state
->state
;
5256 struct drm_plane
*plane
;
5259 drm_for_each_plane_mask(plane
, state
->dev
, new_crtc_state
->plane_mask
) {
5260 struct drm_plane_state
*new_plane_state
;
5262 /* Cursor planes are "fake". */
5263 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
5266 new_plane_state
= drm_atomic_get_new_plane_state(state
, plane
);
5268 if (!new_plane_state
) {
5270 * The plane is enable on the CRTC and hasn't changed
5271 * state. This means that it previously passed
5272 * validation and is therefore enabled.
5278 /* We need a framebuffer to be considered enabled. */
5279 num_active
+= (new_plane_state
->fb
!= NULL
);
5286 * Sets whether interrupts should be enabled on a specific CRTC.
5287 * We require that the stream be enabled and that there exist active
5288 * DC planes on the stream.
5291 dm_update_crtc_interrupt_state(struct drm_crtc
*crtc
,
5292 struct drm_crtc_state
*new_crtc_state
)
5294 struct dm_crtc_state
*dm_new_crtc_state
=
5295 to_dm_crtc_state(new_crtc_state
);
5297 dm_new_crtc_state
->active_planes
= 0;
5298 dm_new_crtc_state
->interrupts_enabled
= false;
5300 if (!dm_new_crtc_state
->stream
)
5303 dm_new_crtc_state
->active_planes
=
5304 count_crtc_active_planes(new_crtc_state
);
5306 dm_new_crtc_state
->interrupts_enabled
=
5307 dm_new_crtc_state
->active_planes
> 0;
5310 static int dm_crtc_helper_atomic_check(struct drm_crtc
*crtc
,
5311 struct drm_crtc_state
*state
)
5313 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
5314 struct dc
*dc
= adev
->dm
.dc
;
5315 struct dm_crtc_state
*dm_crtc_state
= to_dm_crtc_state(state
);
5319 * Update interrupt state for the CRTC. This needs to happen whenever
5320 * the CRTC has changed or whenever any of its planes have changed.
5321 * Atomic check satisfies both of these requirements since the CRTC
5322 * is added to the state by DRM during drm_atomic_helper_check_planes.
5324 dm_update_crtc_interrupt_state(crtc
, state
);
5326 if (unlikely(!dm_crtc_state
->stream
&&
5327 modeset_required(state
, NULL
, dm_crtc_state
->stream
))) {
5332 /* In some use cases, like reset, no stream is attached */
5333 if (!dm_crtc_state
->stream
)
5337 * We want at least one hardware plane enabled to use
5338 * the stream with a cursor enabled.
5340 if (state
->enable
&& state
->active
&&
5341 does_crtc_have_active_cursor(state
) &&
5342 dm_crtc_state
->active_planes
== 0)
5345 if (dc_validate_stream(dc
, dm_crtc_state
->stream
) == DC_OK
)
5351 static bool dm_crtc_helper_mode_fixup(struct drm_crtc
*crtc
,
5352 const struct drm_display_mode
*mode
,
5353 struct drm_display_mode
*adjusted_mode
)
5358 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs
= {
5359 .disable
= dm_crtc_helper_disable
,
5360 .atomic_check
= dm_crtc_helper_atomic_check
,
5361 .mode_fixup
= dm_crtc_helper_mode_fixup
,
5362 .get_scanout_position
= amdgpu_crtc_get_scanout_position
,
5365 static void dm_encoder_helper_disable(struct drm_encoder
*encoder
)
5370 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth
)
5372 switch (display_color_depth
) {
5373 case COLOR_DEPTH_666
:
5375 case COLOR_DEPTH_888
:
5377 case COLOR_DEPTH_101010
:
5379 case COLOR_DEPTH_121212
:
5381 case COLOR_DEPTH_141414
:
5383 case COLOR_DEPTH_161616
:
5391 static int dm_encoder_helper_atomic_check(struct drm_encoder
*encoder
,
5392 struct drm_crtc_state
*crtc_state
,
5393 struct drm_connector_state
*conn_state
)
5395 struct drm_atomic_state
*state
= crtc_state
->state
;
5396 struct drm_connector
*connector
= conn_state
->connector
;
5397 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
5398 struct dm_connector_state
*dm_new_connector_state
= to_dm_connector_state(conn_state
);
5399 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->adjusted_mode
;
5400 struct drm_dp_mst_topology_mgr
*mst_mgr
;
5401 struct drm_dp_mst_port
*mst_port
;
5402 enum dc_color_depth color_depth
;
5404 bool is_y420
= false;
5406 if (!aconnector
->port
|| !aconnector
->dc_sink
)
5409 mst_port
= aconnector
->port
;
5410 mst_mgr
= &aconnector
->mst_port
->mst_mgr
;
5412 if (!crtc_state
->connectors_changed
&& !crtc_state
->mode_changed
)
5415 if (!state
->duplicated
) {
5416 int max_bpc
= conn_state
->max_requested_bpc
;
5417 is_y420
= drm_mode_is_420_also(&connector
->display_info
, adjusted_mode
) &&
5418 aconnector
->force_yuv420_output
;
5419 color_depth
= convert_color_depth_from_display_info(connector
,
5422 bpp
= convert_dc_color_depth_into_bpc(color_depth
) * 3;
5423 clock
= adjusted_mode
->clock
;
5424 dm_new_connector_state
->pbn
= drm_dp_calc_pbn_mode(clock
, bpp
, false);
5426 dm_new_connector_state
->vcpi_slots
= drm_dp_atomic_find_vcpi_slots(state
,
5429 dm_new_connector_state
->pbn
,
5431 if (dm_new_connector_state
->vcpi_slots
< 0) {
5432 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state
->vcpi_slots
);
5433 return dm_new_connector_state
->vcpi_slots
;
5438 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs
= {
5439 .disable
= dm_encoder_helper_disable
,
5440 .atomic_check
= dm_encoder_helper_atomic_check
5443 #if defined(CONFIG_DRM_AMD_DC_DCN)
5444 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state
*state
,
5445 struct dc_state
*dc_state
)
5447 struct dc_stream_state
*stream
= NULL
;
5448 struct drm_connector
*connector
;
5449 struct drm_connector_state
*new_con_state
, *old_con_state
;
5450 struct amdgpu_dm_connector
*aconnector
;
5451 struct dm_connector_state
*dm_conn_state
;
5452 int i
, j
, clock
, bpp
;
5453 int vcpi
, pbn_div
, pbn
= 0;
5455 for_each_oldnew_connector_in_state(state
, connector
, old_con_state
, new_con_state
, i
) {
5457 aconnector
= to_amdgpu_dm_connector(connector
);
5459 if (!aconnector
->port
)
5462 if (!new_con_state
|| !new_con_state
->crtc
)
5465 dm_conn_state
= to_dm_connector_state(new_con_state
);
5467 for (j
= 0; j
< dc_state
->stream_count
; j
++) {
5468 stream
= dc_state
->streams
[j
];
5472 if ((struct amdgpu_dm_connector
*)stream
->dm_stream_context
== aconnector
)
5481 if (stream
->timing
.flags
.DSC
!= 1) {
5482 drm_dp_mst_atomic_enable_dsc(state
,
5490 pbn_div
= dm_mst_get_pbn_divider(stream
->link
);
5491 bpp
= stream
->timing
.dsc_cfg
.bits_per_pixel
;
5492 clock
= stream
->timing
.pix_clk_100hz
/ 10;
5493 pbn
= drm_dp_calc_pbn_mode(clock
, bpp
, true);
5494 vcpi
= drm_dp_mst_atomic_enable_dsc(state
,
5501 dm_conn_state
->pbn
= pbn
;
5502 dm_conn_state
->vcpi_slots
= vcpi
;
5508 static void dm_drm_plane_reset(struct drm_plane
*plane
)
5510 struct dm_plane_state
*amdgpu_state
= NULL
;
5513 plane
->funcs
->atomic_destroy_state(plane
, plane
->state
);
5515 amdgpu_state
= kzalloc(sizeof(*amdgpu_state
), GFP_KERNEL
);
5516 WARN_ON(amdgpu_state
== NULL
);
5519 __drm_atomic_helper_plane_reset(plane
, &amdgpu_state
->base
);
5522 static struct drm_plane_state
*
5523 dm_drm_plane_duplicate_state(struct drm_plane
*plane
)
5525 struct dm_plane_state
*dm_plane_state
, *old_dm_plane_state
;
5527 old_dm_plane_state
= to_dm_plane_state(plane
->state
);
5528 dm_plane_state
= kzalloc(sizeof(*dm_plane_state
), GFP_KERNEL
);
5529 if (!dm_plane_state
)
5532 __drm_atomic_helper_plane_duplicate_state(plane
, &dm_plane_state
->base
);
5534 if (old_dm_plane_state
->dc_state
) {
5535 dm_plane_state
->dc_state
= old_dm_plane_state
->dc_state
;
5536 dc_plane_state_retain(dm_plane_state
->dc_state
);
5539 return &dm_plane_state
->base
;
5542 void dm_drm_plane_destroy_state(struct drm_plane
*plane
,
5543 struct drm_plane_state
*state
)
5545 struct dm_plane_state
*dm_plane_state
= to_dm_plane_state(state
);
5547 if (dm_plane_state
->dc_state
)
5548 dc_plane_state_release(dm_plane_state
->dc_state
);
5550 drm_atomic_helper_plane_destroy_state(plane
, state
);
5553 static const struct drm_plane_funcs dm_plane_funcs
= {
5554 .update_plane
= drm_atomic_helper_update_plane
,
5555 .disable_plane
= drm_atomic_helper_disable_plane
,
5556 .destroy
= drm_primary_helper_destroy
,
5557 .reset
= dm_drm_plane_reset
,
5558 .atomic_duplicate_state
= dm_drm_plane_duplicate_state
,
5559 .atomic_destroy_state
= dm_drm_plane_destroy_state
,
5562 static int dm_plane_helper_prepare_fb(struct drm_plane
*plane
,
5563 struct drm_plane_state
*new_state
)
5565 struct amdgpu_framebuffer
*afb
;
5566 struct drm_gem_object
*obj
;
5567 struct amdgpu_device
*adev
;
5568 struct amdgpu_bo
*rbo
;
5569 struct dm_plane_state
*dm_plane_state_new
, *dm_plane_state_old
;
5570 struct list_head list
;
5571 struct ttm_validate_buffer tv
;
5572 struct ww_acquire_ctx ticket
;
5573 uint64_t tiling_flags
;
5576 bool tmz_surface
= false;
5577 bool force_disable_dcc
= false;
5579 dm_plane_state_old
= to_dm_plane_state(plane
->state
);
5580 dm_plane_state_new
= to_dm_plane_state(new_state
);
5582 if (!new_state
->fb
) {
5583 DRM_DEBUG_DRIVER("No FB bound\n");
5587 afb
= to_amdgpu_framebuffer(new_state
->fb
);
5588 obj
= new_state
->fb
->obj
[0];
5589 rbo
= gem_to_amdgpu_bo(obj
);
5590 adev
= amdgpu_ttm_adev(rbo
->tbo
.bdev
);
5591 INIT_LIST_HEAD(&list
);
5595 list_add(&tv
.head
, &list
);
5597 r
= ttm_eu_reserve_buffers(&ticket
, &list
, false, NULL
);
5599 dev_err(adev
->dev
, "fail to reserve bo (%d)\n", r
);
5603 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
5604 domain
= amdgpu_display_supported_domains(adev
, rbo
->flags
);
5606 domain
= AMDGPU_GEM_DOMAIN_VRAM
;
5608 r
= amdgpu_bo_pin(rbo
, domain
);
5609 if (unlikely(r
!= 0)) {
5610 if (r
!= -ERESTARTSYS
)
5611 DRM_ERROR("Failed to pin framebuffer with error %d\n", r
);
5612 ttm_eu_backoff_reservation(&ticket
, &list
);
5616 r
= amdgpu_ttm_alloc_gart(&rbo
->tbo
);
5617 if (unlikely(r
!= 0)) {
5618 amdgpu_bo_unpin(rbo
);
5619 ttm_eu_backoff_reservation(&ticket
, &list
);
5620 DRM_ERROR("%p bind failed\n", rbo
);
5624 amdgpu_bo_get_tiling_flags(rbo
, &tiling_flags
);
5626 tmz_surface
= amdgpu_bo_encrypted(rbo
);
5628 ttm_eu_backoff_reservation(&ticket
, &list
);
5630 afb
->address
= amdgpu_bo_gpu_offset(rbo
);
5634 if (dm_plane_state_new
->dc_state
&&
5635 dm_plane_state_old
->dc_state
!= dm_plane_state_new
->dc_state
) {
5636 struct dc_plane_state
*plane_state
= dm_plane_state_new
->dc_state
;
5638 force_disable_dcc
= adev
->asic_type
== CHIP_RAVEN
&& adev
->in_suspend
;
5639 fill_plane_buffer_attributes(
5640 adev
, afb
, plane_state
->format
, plane_state
->rotation
,
5641 tiling_flags
, &plane_state
->tiling_info
,
5642 &plane_state
->plane_size
, &plane_state
->dcc
,
5643 &plane_state
->address
, tmz_surface
,
5650 static void dm_plane_helper_cleanup_fb(struct drm_plane
*plane
,
5651 struct drm_plane_state
*old_state
)
5653 struct amdgpu_bo
*rbo
;
5659 rbo
= gem_to_amdgpu_bo(old_state
->fb
->obj
[0]);
5660 r
= amdgpu_bo_reserve(rbo
, false);
5662 DRM_ERROR("failed to reserve rbo before unpin\n");
5666 amdgpu_bo_unpin(rbo
);
5667 amdgpu_bo_unreserve(rbo
);
5668 amdgpu_bo_unref(&rbo
);
5671 static int dm_plane_atomic_check(struct drm_plane
*plane
,
5672 struct drm_plane_state
*state
)
5674 struct amdgpu_device
*adev
= plane
->dev
->dev_private
;
5675 struct dc
*dc
= adev
->dm
.dc
;
5676 struct dm_plane_state
*dm_plane_state
;
5677 struct dc_scaling_info scaling_info
;
5680 dm_plane_state
= to_dm_plane_state(state
);
5682 if (!dm_plane_state
->dc_state
)
5685 ret
= fill_dc_scaling_info(state
, &scaling_info
);
5689 if (dc_validate_plane(dc
, dm_plane_state
->dc_state
) == DC_OK
)
5695 static int dm_plane_atomic_async_check(struct drm_plane
*plane
,
5696 struct drm_plane_state
*new_plane_state
)
5698 /* Only support async updates on cursor planes. */
5699 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
5705 static void dm_plane_atomic_async_update(struct drm_plane
*plane
,
5706 struct drm_plane_state
*new_state
)
5708 struct drm_plane_state
*old_state
=
5709 drm_atomic_get_old_plane_state(new_state
->state
, plane
);
5711 swap(plane
->state
->fb
, new_state
->fb
);
5713 plane
->state
->src_x
= new_state
->src_x
;
5714 plane
->state
->src_y
= new_state
->src_y
;
5715 plane
->state
->src_w
= new_state
->src_w
;
5716 plane
->state
->src_h
= new_state
->src_h
;
5717 plane
->state
->crtc_x
= new_state
->crtc_x
;
5718 plane
->state
->crtc_y
= new_state
->crtc_y
;
5719 plane
->state
->crtc_w
= new_state
->crtc_w
;
5720 plane
->state
->crtc_h
= new_state
->crtc_h
;
5722 handle_cursor_update(plane
, old_state
);
5725 static const struct drm_plane_helper_funcs dm_plane_helper_funcs
= {
5726 .prepare_fb
= dm_plane_helper_prepare_fb
,
5727 .cleanup_fb
= dm_plane_helper_cleanup_fb
,
5728 .atomic_check
= dm_plane_atomic_check
,
5729 .atomic_async_check
= dm_plane_atomic_async_check
,
5730 .atomic_async_update
= dm_plane_atomic_async_update
5734 * TODO: these are currently initialized to rgb formats only.
5735 * For future use cases we should either initialize them dynamically based on
5736 * plane capabilities, or initialize this array to all formats, so internal drm
5737 * check will succeed, and let DC implement proper check
5739 static const uint32_t rgb_formats
[] = {
5740 DRM_FORMAT_XRGB8888
,
5741 DRM_FORMAT_ARGB8888
,
5742 DRM_FORMAT_RGBA8888
,
5743 DRM_FORMAT_XRGB2101010
,
5744 DRM_FORMAT_XBGR2101010
,
5745 DRM_FORMAT_ARGB2101010
,
5746 DRM_FORMAT_ABGR2101010
,
5747 DRM_FORMAT_XBGR8888
,
5748 DRM_FORMAT_ABGR8888
,
5752 static const uint32_t overlay_formats
[] = {
5753 DRM_FORMAT_XRGB8888
,
5754 DRM_FORMAT_ARGB8888
,
5755 DRM_FORMAT_RGBA8888
,
5756 DRM_FORMAT_XBGR8888
,
5757 DRM_FORMAT_ABGR8888
,
5761 static const u32 cursor_formats
[] = {
5765 static int get_plane_formats(const struct drm_plane
*plane
,
5766 const struct dc_plane_cap
*plane_cap
,
5767 uint32_t *formats
, int max_formats
)
5769 int i
, num_formats
= 0;
5772 * TODO: Query support for each group of formats directly from
5773 * DC plane caps. This will require adding more formats to the
5777 switch (plane
->type
) {
5778 case DRM_PLANE_TYPE_PRIMARY
:
5779 for (i
= 0; i
< ARRAY_SIZE(rgb_formats
); ++i
) {
5780 if (num_formats
>= max_formats
)
5783 formats
[num_formats
++] = rgb_formats
[i
];
5786 if (plane_cap
&& plane_cap
->pixel_format_support
.nv12
)
5787 formats
[num_formats
++] = DRM_FORMAT_NV12
;
5788 if (plane_cap
&& plane_cap
->pixel_format_support
.p010
)
5789 formats
[num_formats
++] = DRM_FORMAT_P010
;
5790 if (plane_cap
&& plane_cap
->pixel_format_support
.fp16
) {
5791 formats
[num_formats
++] = DRM_FORMAT_XRGB16161616F
;
5792 formats
[num_formats
++] = DRM_FORMAT_ARGB16161616F
;
5793 formats
[num_formats
++] = DRM_FORMAT_XBGR16161616F
;
5794 formats
[num_formats
++] = DRM_FORMAT_ABGR16161616F
;
5798 case DRM_PLANE_TYPE_OVERLAY
:
5799 for (i
= 0; i
< ARRAY_SIZE(overlay_formats
); ++i
) {
5800 if (num_formats
>= max_formats
)
5803 formats
[num_formats
++] = overlay_formats
[i
];
5807 case DRM_PLANE_TYPE_CURSOR
:
5808 for (i
= 0; i
< ARRAY_SIZE(cursor_formats
); ++i
) {
5809 if (num_formats
>= max_formats
)
5812 formats
[num_formats
++] = cursor_formats
[i
];
5820 static int amdgpu_dm_plane_init(struct amdgpu_display_manager
*dm
,
5821 struct drm_plane
*plane
,
5822 unsigned long possible_crtcs
,
5823 const struct dc_plane_cap
*plane_cap
)
5825 uint32_t formats
[32];
5829 num_formats
= get_plane_formats(plane
, plane_cap
, formats
,
5830 ARRAY_SIZE(formats
));
5832 res
= drm_universal_plane_init(dm
->adev
->ddev
, plane
, possible_crtcs
,
5833 &dm_plane_funcs
, formats
, num_formats
,
5834 NULL
, plane
->type
, NULL
);
5838 if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
&&
5839 plane_cap
&& plane_cap
->per_pixel_alpha
) {
5840 unsigned int blend_caps
= BIT(DRM_MODE_BLEND_PIXEL_NONE
) |
5841 BIT(DRM_MODE_BLEND_PREMULTI
);
5843 drm_plane_create_alpha_property(plane
);
5844 drm_plane_create_blend_mode_property(plane
, blend_caps
);
5847 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
&&
5849 (plane_cap
->pixel_format_support
.nv12
||
5850 plane_cap
->pixel_format_support
.p010
)) {
5851 /* This only affects YUV formats. */
5852 drm_plane_create_color_properties(
5854 BIT(DRM_COLOR_YCBCR_BT601
) |
5855 BIT(DRM_COLOR_YCBCR_BT709
) |
5856 BIT(DRM_COLOR_YCBCR_BT2020
),
5857 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE
) |
5858 BIT(DRM_COLOR_YCBCR_FULL_RANGE
),
5859 DRM_COLOR_YCBCR_BT709
, DRM_COLOR_YCBCR_LIMITED_RANGE
);
5862 drm_plane_helper_add(plane
, &dm_plane_helper_funcs
);
5864 /* Create (reset) the plane state */
5865 if (plane
->funcs
->reset
)
5866 plane
->funcs
->reset(plane
);
5871 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager
*dm
,
5872 struct drm_plane
*plane
,
5873 uint32_t crtc_index
)
5875 struct amdgpu_crtc
*acrtc
= NULL
;
5876 struct drm_plane
*cursor_plane
;
5880 cursor_plane
= kzalloc(sizeof(*cursor_plane
), GFP_KERNEL
);
5884 cursor_plane
->type
= DRM_PLANE_TYPE_CURSOR
;
5885 res
= amdgpu_dm_plane_init(dm
, cursor_plane
, 0, NULL
);
5887 acrtc
= kzalloc(sizeof(struct amdgpu_crtc
), GFP_KERNEL
);
5891 res
= drm_crtc_init_with_planes(
5896 &amdgpu_dm_crtc_funcs
, NULL
);
5901 drm_crtc_helper_add(&acrtc
->base
, &amdgpu_dm_crtc_helper_funcs
);
5903 /* Create (reset) the plane state */
5904 if (acrtc
->base
.funcs
->reset
)
5905 acrtc
->base
.funcs
->reset(&acrtc
->base
);
5907 acrtc
->max_cursor_width
= dm
->adev
->dm
.dc
->caps
.max_cursor_size
;
5908 acrtc
->max_cursor_height
= dm
->adev
->dm
.dc
->caps
.max_cursor_size
;
5910 acrtc
->crtc_id
= crtc_index
;
5911 acrtc
->base
.enabled
= false;
5912 acrtc
->otg_inst
= -1;
5914 dm
->adev
->mode_info
.crtcs
[crtc_index
] = acrtc
;
5915 drm_crtc_enable_color_mgmt(&acrtc
->base
, MAX_COLOR_LUT_ENTRIES
,
5916 true, MAX_COLOR_LUT_ENTRIES
);
5917 drm_mode_crtc_set_gamma_size(&acrtc
->base
, MAX_COLOR_LEGACY_LUT_ENTRIES
);
5923 kfree(cursor_plane
);
5928 static int to_drm_connector_type(enum signal_type st
)
5931 case SIGNAL_TYPE_HDMI_TYPE_A
:
5932 return DRM_MODE_CONNECTOR_HDMIA
;
5933 case SIGNAL_TYPE_EDP
:
5934 return DRM_MODE_CONNECTOR_eDP
;
5935 case SIGNAL_TYPE_LVDS
:
5936 return DRM_MODE_CONNECTOR_LVDS
;
5937 case SIGNAL_TYPE_RGB
:
5938 return DRM_MODE_CONNECTOR_VGA
;
5939 case SIGNAL_TYPE_DISPLAY_PORT
:
5940 case SIGNAL_TYPE_DISPLAY_PORT_MST
:
5941 return DRM_MODE_CONNECTOR_DisplayPort
;
5942 case SIGNAL_TYPE_DVI_DUAL_LINK
:
5943 case SIGNAL_TYPE_DVI_SINGLE_LINK
:
5944 return DRM_MODE_CONNECTOR_DVID
;
5945 case SIGNAL_TYPE_VIRTUAL
:
5946 return DRM_MODE_CONNECTOR_VIRTUAL
;
5949 return DRM_MODE_CONNECTOR_Unknown
;
5953 static struct drm_encoder
*amdgpu_dm_connector_to_encoder(struct drm_connector
*connector
)
5955 struct drm_encoder
*encoder
;
5957 /* There is only one encoder per connector */
5958 drm_connector_for_each_possible_encoder(connector
, encoder
)
5964 static void amdgpu_dm_get_native_mode(struct drm_connector
*connector
)
5966 struct drm_encoder
*encoder
;
5967 struct amdgpu_encoder
*amdgpu_encoder
;
5969 encoder
= amdgpu_dm_connector_to_encoder(connector
);
5971 if (encoder
== NULL
)
5974 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
5976 amdgpu_encoder
->native_mode
.clock
= 0;
5978 if (!list_empty(&connector
->probed_modes
)) {
5979 struct drm_display_mode
*preferred_mode
= NULL
;
5981 list_for_each_entry(preferred_mode
,
5982 &connector
->probed_modes
,
5984 if (preferred_mode
->type
& DRM_MODE_TYPE_PREFERRED
)
5985 amdgpu_encoder
->native_mode
= *preferred_mode
;
5993 static struct drm_display_mode
*
5994 amdgpu_dm_create_common_mode(struct drm_encoder
*encoder
,
5996 int hdisplay
, int vdisplay
)
5998 struct drm_device
*dev
= encoder
->dev
;
5999 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
6000 struct drm_display_mode
*mode
= NULL
;
6001 struct drm_display_mode
*native_mode
= &amdgpu_encoder
->native_mode
;
6003 mode
= drm_mode_duplicate(dev
, native_mode
);
6008 mode
->hdisplay
= hdisplay
;
6009 mode
->vdisplay
= vdisplay
;
6010 mode
->type
&= ~DRM_MODE_TYPE_PREFERRED
;
6011 strscpy(mode
->name
, name
, DRM_DISPLAY_MODE_LEN
);
6017 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder
*encoder
,
6018 struct drm_connector
*connector
)
6020 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
6021 struct drm_display_mode
*mode
= NULL
;
6022 struct drm_display_mode
*native_mode
= &amdgpu_encoder
->native_mode
;
6023 struct amdgpu_dm_connector
*amdgpu_dm_connector
=
6024 to_amdgpu_dm_connector(connector
);
6028 char name
[DRM_DISPLAY_MODE_LEN
];
6031 } common_modes
[] = {
6032 { "640x480", 640, 480},
6033 { "800x600", 800, 600},
6034 { "1024x768", 1024, 768},
6035 { "1280x720", 1280, 720},
6036 { "1280x800", 1280, 800},
6037 {"1280x1024", 1280, 1024},
6038 { "1440x900", 1440, 900},
6039 {"1680x1050", 1680, 1050},
6040 {"1600x1200", 1600, 1200},
6041 {"1920x1080", 1920, 1080},
6042 {"1920x1200", 1920, 1200}
6045 n
= ARRAY_SIZE(common_modes
);
6047 for (i
= 0; i
< n
; i
++) {
6048 struct drm_display_mode
*curmode
= NULL
;
6049 bool mode_existed
= false;
6051 if (common_modes
[i
].w
> native_mode
->hdisplay
||
6052 common_modes
[i
].h
> native_mode
->vdisplay
||
6053 (common_modes
[i
].w
== native_mode
->hdisplay
&&
6054 common_modes
[i
].h
== native_mode
->vdisplay
))
6057 list_for_each_entry(curmode
, &connector
->probed_modes
, head
) {
6058 if (common_modes
[i
].w
== curmode
->hdisplay
&&
6059 common_modes
[i
].h
== curmode
->vdisplay
) {
6060 mode_existed
= true;
6068 mode
= amdgpu_dm_create_common_mode(encoder
,
6069 common_modes
[i
].name
, common_modes
[i
].w
,
6071 drm_mode_probed_add(connector
, mode
);
6072 amdgpu_dm_connector
->num_modes
++;
6076 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector
*connector
,
6079 struct amdgpu_dm_connector
*amdgpu_dm_connector
=
6080 to_amdgpu_dm_connector(connector
);
6083 /* empty probed_modes */
6084 INIT_LIST_HEAD(&connector
->probed_modes
);
6085 amdgpu_dm_connector
->num_modes
=
6086 drm_add_edid_modes(connector
, edid
);
6088 /* sorting the probed modes before calling function
6089 * amdgpu_dm_get_native_mode() since EDID can have
6090 * more than one preferred mode. The modes that are
6091 * later in the probed mode list could be of higher
6092 * and preferred resolution. For example, 3840x2160
6093 * resolution in base EDID preferred timing and 4096x2160
6094 * preferred resolution in DID extension block later.
6096 drm_mode_sort(&connector
->probed_modes
);
6097 amdgpu_dm_get_native_mode(connector
);
6099 amdgpu_dm_connector
->num_modes
= 0;
6103 static int amdgpu_dm_connector_get_modes(struct drm_connector
*connector
)
6105 struct amdgpu_dm_connector
*amdgpu_dm_connector
=
6106 to_amdgpu_dm_connector(connector
);
6107 struct drm_encoder
*encoder
;
6108 struct edid
*edid
= amdgpu_dm_connector
->edid
;
6110 encoder
= amdgpu_dm_connector_to_encoder(connector
);
6112 if (!edid
|| !drm_edid_is_valid(edid
)) {
6113 amdgpu_dm_connector
->num_modes
=
6114 drm_add_modes_noedid(connector
, 640, 480);
6116 amdgpu_dm_connector_ddc_get_modes(connector
, edid
);
6117 amdgpu_dm_connector_add_common_modes(encoder
, connector
);
6119 amdgpu_dm_fbc_init(connector
);
6121 return amdgpu_dm_connector
->num_modes
;
6124 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager
*dm
,
6125 struct amdgpu_dm_connector
*aconnector
,
6127 struct dc_link
*link
,
6130 struct amdgpu_device
*adev
= dm
->ddev
->dev_private
;
6133 * Some of the properties below require access to state, like bpc.
6134 * Allocate some default initial connector state with our reset helper.
6136 if (aconnector
->base
.funcs
->reset
)
6137 aconnector
->base
.funcs
->reset(&aconnector
->base
);
6139 aconnector
->connector_id
= link_index
;
6140 aconnector
->dc_link
= link
;
6141 aconnector
->base
.interlace_allowed
= false;
6142 aconnector
->base
.doublescan_allowed
= false;
6143 aconnector
->base
.stereo_allowed
= false;
6144 aconnector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
6145 aconnector
->hpd
.hpd
= AMDGPU_HPD_NONE
; /* not used */
6146 aconnector
->audio_inst
= -1;
6147 mutex_init(&aconnector
->hpd_lock
);
6150 * configure support HPD hot plug connector_>polled default value is 0
6151 * which means HPD hot plug not supported
6153 switch (connector_type
) {
6154 case DRM_MODE_CONNECTOR_HDMIA
:
6155 aconnector
->base
.polled
= DRM_CONNECTOR_POLL_HPD
;
6156 aconnector
->base
.ycbcr_420_allowed
=
6157 link
->link_enc
->features
.hdmi_ycbcr420_supported
? true : false;
6159 case DRM_MODE_CONNECTOR_DisplayPort
:
6160 aconnector
->base
.polled
= DRM_CONNECTOR_POLL_HPD
;
6161 aconnector
->base
.ycbcr_420_allowed
=
6162 link
->link_enc
->features
.dp_ycbcr420_supported
? true : false;
6164 case DRM_MODE_CONNECTOR_DVID
:
6165 aconnector
->base
.polled
= DRM_CONNECTOR_POLL_HPD
;
6171 drm_object_attach_property(&aconnector
->base
.base
,
6172 dm
->ddev
->mode_config
.scaling_mode_property
,
6173 DRM_MODE_SCALE_NONE
);
6175 drm_object_attach_property(&aconnector
->base
.base
,
6176 adev
->mode_info
.underscan_property
,
6178 drm_object_attach_property(&aconnector
->base
.base
,
6179 adev
->mode_info
.underscan_hborder_property
,
6181 drm_object_attach_property(&aconnector
->base
.base
,
6182 adev
->mode_info
.underscan_vborder_property
,
6185 if (!aconnector
->mst_port
)
6186 drm_connector_attach_max_bpc_property(&aconnector
->base
, 8, 16);
6188 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
6189 aconnector
->base
.state
->max_bpc
= (connector_type
== DRM_MODE_CONNECTOR_eDP
) ? 16 : 8;
6190 aconnector
->base
.state
->max_requested_bpc
= aconnector
->base
.state
->max_bpc
;
6192 if (connector_type
== DRM_MODE_CONNECTOR_eDP
&&
6193 dc_is_dmcu_initialized(adev
->dm
.dc
)) {
6194 drm_object_attach_property(&aconnector
->base
.base
,
6195 adev
->mode_info
.abm_level_property
, 0);
6198 if (connector_type
== DRM_MODE_CONNECTOR_HDMIA
||
6199 connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
6200 connector_type
== DRM_MODE_CONNECTOR_eDP
) {
6201 drm_object_attach_property(
6202 &aconnector
->base
.base
,
6203 dm
->ddev
->mode_config
.hdr_output_metadata_property
, 0);
6205 if (!aconnector
->mst_port
)
6206 drm_connector_attach_vrr_capable_property(&aconnector
->base
);
6208 #ifdef CONFIG_DRM_AMD_DC_HDCP
6209 if (adev
->dm
.hdcp_workqueue
)
6210 drm_connector_attach_content_protection_property(&aconnector
->base
, true);
6215 static int amdgpu_dm_i2c_xfer(struct i2c_adapter
*i2c_adap
,
6216 struct i2c_msg
*msgs
, int num
)
6218 struct amdgpu_i2c_adapter
*i2c
= i2c_get_adapdata(i2c_adap
);
6219 struct ddc_service
*ddc_service
= i2c
->ddc_service
;
6220 struct i2c_command cmd
;
6224 cmd
.payloads
= kcalloc(num
, sizeof(struct i2c_payload
), GFP_KERNEL
);
6229 cmd
.number_of_payloads
= num
;
6230 cmd
.engine
= I2C_COMMAND_ENGINE_DEFAULT
;
6233 for (i
= 0; i
< num
; i
++) {
6234 cmd
.payloads
[i
].write
= !(msgs
[i
].flags
& I2C_M_RD
);
6235 cmd
.payloads
[i
].address
= msgs
[i
].addr
;
6236 cmd
.payloads
[i
].length
= msgs
[i
].len
;
6237 cmd
.payloads
[i
].data
= msgs
[i
].buf
;
6241 ddc_service
->ctx
->dc
,
6242 ddc_service
->ddc_pin
->hw_info
.ddc_channel
,
6246 kfree(cmd
.payloads
);
6250 static u32
amdgpu_dm_i2c_func(struct i2c_adapter
*adap
)
6252 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
6255 static const struct i2c_algorithm amdgpu_dm_i2c_algo
= {
6256 .master_xfer
= amdgpu_dm_i2c_xfer
,
6257 .functionality
= amdgpu_dm_i2c_func
,
6260 static struct amdgpu_i2c_adapter
*
6261 create_i2c(struct ddc_service
*ddc_service
,
6265 struct amdgpu_device
*adev
= ddc_service
->ctx
->driver_context
;
6266 struct amdgpu_i2c_adapter
*i2c
;
6268 i2c
= kzalloc(sizeof(struct amdgpu_i2c_adapter
), GFP_KERNEL
);
6271 i2c
->base
.owner
= THIS_MODULE
;
6272 i2c
->base
.class = I2C_CLASS_DDC
;
6273 i2c
->base
.dev
.parent
= &adev
->pdev
->dev
;
6274 i2c
->base
.algo
= &amdgpu_dm_i2c_algo
;
6275 snprintf(i2c
->base
.name
, sizeof(i2c
->base
.name
), "AMDGPU DM i2c hw bus %d", link_index
);
6276 i2c_set_adapdata(&i2c
->base
, i2c
);
6277 i2c
->ddc_service
= ddc_service
;
6278 i2c
->ddc_service
->ddc_pin
->hw_info
.ddc_channel
= link_index
;
6285 * Note: this function assumes that dc_link_detect() was called for the
6286 * dc_link which will be represented by this aconnector.
6288 static int amdgpu_dm_connector_init(struct amdgpu_display_manager
*dm
,
6289 struct amdgpu_dm_connector
*aconnector
,
6290 uint32_t link_index
,
6291 struct amdgpu_encoder
*aencoder
)
6295 struct dc
*dc
= dm
->dc
;
6296 struct dc_link
*link
= dc_get_link_at_index(dc
, link_index
);
6297 struct amdgpu_i2c_adapter
*i2c
;
6299 link
->priv
= aconnector
;
6301 DRM_DEBUG_DRIVER("%s()\n", __func__
);
6303 i2c
= create_i2c(link
->ddc
, link
->link_index
, &res
);
6305 DRM_ERROR("Failed to create i2c adapter data\n");
6309 aconnector
->i2c
= i2c
;
6310 res
= i2c_add_adapter(&i2c
->base
);
6313 DRM_ERROR("Failed to register hw i2c %d\n", link
->link_index
);
6317 connector_type
= to_drm_connector_type(link
->connector_signal
);
6319 res
= drm_connector_init_with_ddc(
6322 &amdgpu_dm_connector_funcs
,
6327 DRM_ERROR("connector_init failed\n");
6328 aconnector
->connector_id
= -1;
6332 drm_connector_helper_add(
6334 &amdgpu_dm_connector_helper_funcs
);
6336 amdgpu_dm_connector_init_helper(
6343 drm_connector_attach_encoder(
6344 &aconnector
->base
, &aencoder
->base
);
6346 if (connector_type
== DRM_MODE_CONNECTOR_DisplayPort
6347 || connector_type
== DRM_MODE_CONNECTOR_eDP
)
6348 amdgpu_dm_initialize_dp_connector(dm
, aconnector
, link
->link_index
);
6353 aconnector
->i2c
= NULL
;
6358 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device
*adev
)
6360 switch (adev
->mode_info
.num_crtc
) {
6377 static int amdgpu_dm_encoder_init(struct drm_device
*dev
,
6378 struct amdgpu_encoder
*aencoder
,
6379 uint32_t link_index
)
6381 struct amdgpu_device
*adev
= dev
->dev_private
;
6383 int res
= drm_encoder_init(dev
,
6385 &amdgpu_dm_encoder_funcs
,
6386 DRM_MODE_ENCODER_TMDS
,
6389 aencoder
->base
.possible_crtcs
= amdgpu_dm_get_encoder_crtc_mask(adev
);
6392 aencoder
->encoder_id
= link_index
;
6394 aencoder
->encoder_id
= -1;
6396 drm_encoder_helper_add(&aencoder
->base
, &amdgpu_dm_encoder_helper_funcs
);
6401 static void manage_dm_interrupts(struct amdgpu_device
*adev
,
6402 struct amdgpu_crtc
*acrtc
,
6406 * this is not correct translation but will work as soon as VBLANK
6407 * constant is the same as PFLIP
6410 amdgpu_display_crtc_idx_to_irq_type(
6415 drm_crtc_vblank_on(&acrtc
->base
);
6418 &adev
->pageflip_irq
,
6424 &adev
->pageflip_irq
,
6426 drm_crtc_vblank_off(&acrtc
->base
);
6431 is_scaling_state_different(const struct dm_connector_state
*dm_state
,
6432 const struct dm_connector_state
*old_dm_state
)
6434 if (dm_state
->scaling
!= old_dm_state
->scaling
)
6436 if (!dm_state
->underscan_enable
&& old_dm_state
->underscan_enable
) {
6437 if (old_dm_state
->underscan_hborder
!= 0 && old_dm_state
->underscan_vborder
!= 0)
6439 } else if (dm_state
->underscan_enable
&& !old_dm_state
->underscan_enable
) {
6440 if (dm_state
->underscan_hborder
!= 0 && dm_state
->underscan_vborder
!= 0)
6442 } else if (dm_state
->underscan_hborder
!= old_dm_state
->underscan_hborder
||
6443 dm_state
->underscan_vborder
!= old_dm_state
->underscan_vborder
)
6448 #ifdef CONFIG_DRM_AMD_DC_HDCP
6449 static bool is_content_protection_different(struct drm_connector_state
*state
,
6450 const struct drm_connector_state
*old_state
,
6451 const struct drm_connector
*connector
, struct hdcp_workqueue
*hdcp_w
)
6453 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
6455 if (old_state
->hdcp_content_type
!= state
->hdcp_content_type
&&
6456 state
->content_protection
!= DRM_MODE_CONTENT_PROTECTION_UNDESIRED
) {
6457 state
->content_protection
= DRM_MODE_CONTENT_PROTECTION_DESIRED
;
6461 /* CP is being re enabled, ignore this */
6462 if (old_state
->content_protection
== DRM_MODE_CONTENT_PROTECTION_ENABLED
&&
6463 state
->content_protection
== DRM_MODE_CONTENT_PROTECTION_DESIRED
) {
6464 state
->content_protection
= DRM_MODE_CONTENT_PROTECTION_ENABLED
;
6468 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */
6469 if (old_state
->content_protection
== DRM_MODE_CONTENT_PROTECTION_UNDESIRED
&&
6470 state
->content_protection
== DRM_MODE_CONTENT_PROTECTION_ENABLED
)
6471 state
->content_protection
= DRM_MODE_CONTENT_PROTECTION_DESIRED
;
6473 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
6474 * hot-plug, headless s3, dpms
6476 if (state
->content_protection
== DRM_MODE_CONTENT_PROTECTION_DESIRED
&& connector
->dpms
== DRM_MODE_DPMS_ON
&&
6477 aconnector
->dc_sink
!= NULL
)
6480 if (old_state
->content_protection
== state
->content_protection
)
6483 if (state
->content_protection
== DRM_MODE_CONTENT_PROTECTION_UNDESIRED
)
6490 static void remove_stream(struct amdgpu_device
*adev
,
6491 struct amdgpu_crtc
*acrtc
,
6492 struct dc_stream_state
*stream
)
6494 /* this is the update mode case */
6496 acrtc
->otg_inst
= -1;
6497 acrtc
->enabled
= false;
6500 static int get_cursor_position(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
6501 struct dc_cursor_position
*position
)
6503 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
6505 int xorigin
= 0, yorigin
= 0;
6507 position
->enable
= false;
6511 if (!crtc
|| !plane
->state
->fb
)
6514 if ((plane
->state
->crtc_w
> amdgpu_crtc
->max_cursor_width
) ||
6515 (plane
->state
->crtc_h
> amdgpu_crtc
->max_cursor_height
)) {
6516 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
6518 plane
->state
->crtc_w
,
6519 plane
->state
->crtc_h
);
6523 x
= plane
->state
->crtc_x
;
6524 y
= plane
->state
->crtc_y
;
6526 if (x
<= -amdgpu_crtc
->max_cursor_width
||
6527 y
<= -amdgpu_crtc
->max_cursor_height
)
6531 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
6535 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
6538 position
->enable
= true;
6539 position
->translate_by_source
= true;
6542 position
->x_hotspot
= xorigin
;
6543 position
->y_hotspot
= yorigin
;
6548 static void handle_cursor_update(struct drm_plane
*plane
,
6549 struct drm_plane_state
*old_plane_state
)
6551 struct amdgpu_device
*adev
= plane
->dev
->dev_private
;
6552 struct amdgpu_framebuffer
*afb
= to_amdgpu_framebuffer(plane
->state
->fb
);
6553 struct drm_crtc
*crtc
= afb
? plane
->state
->crtc
: old_plane_state
->crtc
;
6554 struct dm_crtc_state
*crtc_state
= crtc
? to_dm_crtc_state(crtc
->state
) : NULL
;
6555 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
6556 uint64_t address
= afb
? afb
->address
: 0;
6557 struct dc_cursor_position position
;
6558 struct dc_cursor_attributes attributes
;
6561 if (!plane
->state
->fb
&& !old_plane_state
->fb
)
6564 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
6566 amdgpu_crtc
->crtc_id
,
6567 plane
->state
->crtc_w
,
6568 plane
->state
->crtc_h
);
6570 ret
= get_cursor_position(plane
, crtc
, &position
);
6574 if (!position
.enable
) {
6575 /* turn off cursor */
6576 if (crtc_state
&& crtc_state
->stream
) {
6577 mutex_lock(&adev
->dm
.dc_lock
);
6578 dc_stream_set_cursor_position(crtc_state
->stream
,
6580 mutex_unlock(&adev
->dm
.dc_lock
);
6585 amdgpu_crtc
->cursor_width
= plane
->state
->crtc_w
;
6586 amdgpu_crtc
->cursor_height
= plane
->state
->crtc_h
;
6588 memset(&attributes
, 0, sizeof(attributes
));
6589 attributes
.address
.high_part
= upper_32_bits(address
);
6590 attributes
.address
.low_part
= lower_32_bits(address
);
6591 attributes
.width
= plane
->state
->crtc_w
;
6592 attributes
.height
= plane
->state
->crtc_h
;
6593 attributes
.color_format
= CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA
;
6594 attributes
.rotation_angle
= 0;
6595 attributes
.attribute_flags
.value
= 0;
6597 attributes
.pitch
= attributes
.width
;
6599 if (crtc_state
->stream
) {
6600 mutex_lock(&adev
->dm
.dc_lock
);
6601 if (!dc_stream_set_cursor_attributes(crtc_state
->stream
,
6603 DRM_ERROR("DC failed to set cursor attributes\n");
6605 if (!dc_stream_set_cursor_position(crtc_state
->stream
,
6607 DRM_ERROR("DC failed to set cursor position\n");
6608 mutex_unlock(&adev
->dm
.dc_lock
);
6612 static void prepare_flip_isr(struct amdgpu_crtc
*acrtc
)
6615 assert_spin_locked(&acrtc
->base
.dev
->event_lock
);
6616 WARN_ON(acrtc
->event
);
6618 acrtc
->event
= acrtc
->base
.state
->event
;
6620 /* Set the flip status */
6621 acrtc
->pflip_status
= AMDGPU_FLIP_SUBMITTED
;
6623 /* Mark this event as consumed */
6624 acrtc
->base
.state
->event
= NULL
;
6626 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
6630 static void update_freesync_state_on_stream(
6631 struct amdgpu_display_manager
*dm
,
6632 struct dm_crtc_state
*new_crtc_state
,
6633 struct dc_stream_state
*new_stream
,
6634 struct dc_plane_state
*surface
,
6635 u32 flip_timestamp_in_us
)
6637 struct mod_vrr_params vrr_params
;
6638 struct dc_info_packet vrr_infopacket
= {0};
6639 struct amdgpu_device
*adev
= dm
->adev
;
6640 unsigned long flags
;
6646 * TODO: Determine why min/max totals and vrefresh can be 0 here.
6647 * For now it's sufficient to just guard against these conditions.
6650 if (!new_stream
->timing
.h_total
|| !new_stream
->timing
.v_total
)
6653 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
6654 vrr_params
= new_crtc_state
->vrr_params
;
6657 mod_freesync_handle_preflip(
6658 dm
->freesync_module
,
6661 flip_timestamp_in_us
,
6664 if (adev
->family
< AMDGPU_FAMILY_AI
&&
6665 amdgpu_dm_vrr_active(new_crtc_state
)) {
6666 mod_freesync_handle_v_update(dm
->freesync_module
,
6667 new_stream
, &vrr_params
);
6669 /* Need to call this before the frame ends. */
6670 dc_stream_adjust_vmin_vmax(dm
->dc
,
6671 new_crtc_state
->stream
,
6672 &vrr_params
.adjust
);
6676 mod_freesync_build_vrr_infopacket(
6677 dm
->freesync_module
,
6681 TRANSFER_FUNC_UNKNOWN
,
6684 new_crtc_state
->freesync_timing_changed
|=
6685 (memcmp(&new_crtc_state
->vrr_params
.adjust
,
6687 sizeof(vrr_params
.adjust
)) != 0);
6689 new_crtc_state
->freesync_vrr_info_changed
|=
6690 (memcmp(&new_crtc_state
->vrr_infopacket
,
6692 sizeof(vrr_infopacket
)) != 0);
6694 new_crtc_state
->vrr_params
= vrr_params
;
6695 new_crtc_state
->vrr_infopacket
= vrr_infopacket
;
6697 new_stream
->adjust
= new_crtc_state
->vrr_params
.adjust
;
6698 new_stream
->vrr_infopacket
= vrr_infopacket
;
6700 if (new_crtc_state
->freesync_vrr_info_changed
)
6701 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
6702 new_crtc_state
->base
.crtc
->base
.id
,
6703 (int)new_crtc_state
->base
.vrr_enabled
,
6704 (int)vrr_params
.state
);
6706 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
6709 static void pre_update_freesync_state_on_stream(
6710 struct amdgpu_display_manager
*dm
,
6711 struct dm_crtc_state
*new_crtc_state
)
6713 struct dc_stream_state
*new_stream
= new_crtc_state
->stream
;
6714 struct mod_vrr_params vrr_params
;
6715 struct mod_freesync_config config
= new_crtc_state
->freesync_config
;
6716 struct amdgpu_device
*adev
= dm
->adev
;
6717 unsigned long flags
;
6723 * TODO: Determine why min/max totals and vrefresh can be 0 here.
6724 * For now it's sufficient to just guard against these conditions.
6726 if (!new_stream
->timing
.h_total
|| !new_stream
->timing
.v_total
)
6729 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
6730 vrr_params
= new_crtc_state
->vrr_params
;
6732 if (new_crtc_state
->vrr_supported
&&
6733 config
.min_refresh_in_uhz
&&
6734 config
.max_refresh_in_uhz
) {
6735 config
.state
= new_crtc_state
->base
.vrr_enabled
?
6736 VRR_STATE_ACTIVE_VARIABLE
:
6739 config
.state
= VRR_STATE_UNSUPPORTED
;
6742 mod_freesync_build_vrr_params(dm
->freesync_module
,
6744 &config
, &vrr_params
);
6746 new_crtc_state
->freesync_timing_changed
|=
6747 (memcmp(&new_crtc_state
->vrr_params
.adjust
,
6749 sizeof(vrr_params
.adjust
)) != 0);
6751 new_crtc_state
->vrr_params
= vrr_params
;
6752 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
6755 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state
*old_state
,
6756 struct dm_crtc_state
*new_state
)
6758 bool old_vrr_active
= amdgpu_dm_vrr_active(old_state
);
6759 bool new_vrr_active
= amdgpu_dm_vrr_active(new_state
);
6761 if (!old_vrr_active
&& new_vrr_active
) {
6762 /* Transition VRR inactive -> active:
6763 * While VRR is active, we must not disable vblank irq, as a
6764 * reenable after disable would compute bogus vblank/pflip
6765 * timestamps if it likely happened inside display front-porch.
6767 * We also need vupdate irq for the actual core vblank handling
6770 dm_set_vupdate_irq(new_state
->base
.crtc
, true);
6771 drm_crtc_vblank_get(new_state
->base
.crtc
);
6772 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
6773 __func__
, new_state
->base
.crtc
->base
.id
);
6774 } else if (old_vrr_active
&& !new_vrr_active
) {
6775 /* Transition VRR active -> inactive:
6776 * Allow vblank irq disable again for fixed refresh rate.
6778 dm_set_vupdate_irq(new_state
->base
.crtc
, false);
6779 drm_crtc_vblank_put(new_state
->base
.crtc
);
6780 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
6781 __func__
, new_state
->base
.crtc
->base
.id
);
6785 static void amdgpu_dm_commit_cursors(struct drm_atomic_state
*state
)
6787 struct drm_plane
*plane
;
6788 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
6792 * TODO: Make this per-stream so we don't issue redundant updates for
6793 * commits with multiple streams.
6795 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
,
6797 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
6798 handle_cursor_update(plane
, old_plane_state
);
6801 static void amdgpu_dm_commit_planes(struct drm_atomic_state
*state
,
6802 struct dc_state
*dc_state
,
6803 struct drm_device
*dev
,
6804 struct amdgpu_display_manager
*dm
,
6805 struct drm_crtc
*pcrtc
,
6806 bool wait_for_vblank
)
6809 uint64_t timestamp_ns
;
6810 struct drm_plane
*plane
;
6811 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
6812 struct amdgpu_crtc
*acrtc_attach
= to_amdgpu_crtc(pcrtc
);
6813 struct drm_crtc_state
*new_pcrtc_state
=
6814 drm_atomic_get_new_crtc_state(state
, pcrtc
);
6815 struct dm_crtc_state
*acrtc_state
= to_dm_crtc_state(new_pcrtc_state
);
6816 struct dm_crtc_state
*dm_old_crtc_state
=
6817 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state
, pcrtc
));
6818 int planes_count
= 0, vpos
, hpos
;
6820 unsigned long flags
;
6821 struct amdgpu_bo
*abo
;
6822 uint64_t tiling_flags
;
6823 bool tmz_surface
= false;
6824 uint32_t target_vblank
, last_flip_vblank
;
6825 bool vrr_active
= amdgpu_dm_vrr_active(acrtc_state
);
6826 bool pflip_present
= false;
6828 struct dc_surface_update surface_updates
[MAX_SURFACES
];
6829 struct dc_plane_info plane_infos
[MAX_SURFACES
];
6830 struct dc_scaling_info scaling_infos
[MAX_SURFACES
];
6831 struct dc_flip_addrs flip_addrs
[MAX_SURFACES
];
6832 struct dc_stream_update stream_update
;
6835 bundle
= kzalloc(sizeof(*bundle
), GFP_KERNEL
);
6838 dm_error("Failed to allocate update bundle\n");
6843 * Disable the cursor first if we're disabling all the planes.
6844 * It'll remain on the screen after the planes are re-enabled
6847 if (acrtc_state
->active_planes
== 0)
6848 amdgpu_dm_commit_cursors(state
);
6850 /* update planes when needed */
6851 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
) {
6852 struct drm_crtc
*crtc
= new_plane_state
->crtc
;
6853 struct drm_crtc_state
*new_crtc_state
;
6854 struct drm_framebuffer
*fb
= new_plane_state
->fb
;
6855 bool plane_needs_flip
;
6856 struct dc_plane_state
*dc_plane
;
6857 struct dm_plane_state
*dm_new_plane_state
= to_dm_plane_state(new_plane_state
);
6859 /* Cursor plane is handled after stream updates */
6860 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
6863 if (!fb
|| !crtc
|| pcrtc
!= crtc
)
6866 new_crtc_state
= drm_atomic_get_new_crtc_state(state
, crtc
);
6867 if (!new_crtc_state
->active
)
6870 dc_plane
= dm_new_plane_state
->dc_state
;
6872 bundle
->surface_updates
[planes_count
].surface
= dc_plane
;
6873 if (new_pcrtc_state
->color_mgmt_changed
) {
6874 bundle
->surface_updates
[planes_count
].gamma
= dc_plane
->gamma_correction
;
6875 bundle
->surface_updates
[planes_count
].in_transfer_func
= dc_plane
->in_transfer_func
;
6876 bundle
->surface_updates
[planes_count
].gamut_remap_matrix
= &dc_plane
->gamut_remap_matrix
;
6879 fill_dc_scaling_info(new_plane_state
,
6880 &bundle
->scaling_infos
[planes_count
]);
6882 bundle
->surface_updates
[planes_count
].scaling_info
=
6883 &bundle
->scaling_infos
[planes_count
];
6885 plane_needs_flip
= old_plane_state
->fb
&& new_plane_state
->fb
;
6887 pflip_present
= pflip_present
|| plane_needs_flip
;
6889 if (!plane_needs_flip
) {
6894 abo
= gem_to_amdgpu_bo(fb
->obj
[0]);
6897 * Wait for all fences on this FB. Do limited wait to avoid
6898 * deadlock during GPU reset when this fence will not signal
6899 * but we hold reservation lock for the BO.
6901 r
= dma_resv_wait_timeout_rcu(abo
->tbo
.base
.resv
, true,
6903 msecs_to_jiffies(5000));
6904 if (unlikely(r
<= 0))
6905 DRM_ERROR("Waiting for fences timed out!");
6908 * TODO This might fail and hence better not used, wait
6909 * explicitly on fences instead
6910 * and in general should be called for
6911 * blocking commit to as per framework helpers
6913 r
= amdgpu_bo_reserve(abo
, true);
6914 if (unlikely(r
!= 0))
6915 DRM_ERROR("failed to reserve buffer before flip\n");
6917 amdgpu_bo_get_tiling_flags(abo
, &tiling_flags
);
6919 tmz_surface
= amdgpu_bo_encrypted(abo
);
6921 amdgpu_bo_unreserve(abo
);
6923 fill_dc_plane_info_and_addr(
6924 dm
->adev
, new_plane_state
, tiling_flags
,
6925 &bundle
->plane_infos
[planes_count
],
6926 &bundle
->flip_addrs
[planes_count
].address
,
6930 DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",
6931 new_plane_state
->plane
->index
,
6932 bundle
->plane_infos
[planes_count
].dcc
.enable
);
6934 bundle
->surface_updates
[planes_count
].plane_info
=
6935 &bundle
->plane_infos
[planes_count
];
6938 * Only allow immediate flips for fast updates that don't
6939 * change FB pitch, DCC state, rotation or mirroing.
6941 bundle
->flip_addrs
[planes_count
].flip_immediate
=
6942 crtc
->state
->async_flip
&&
6943 acrtc_state
->update_type
== UPDATE_TYPE_FAST
;
6945 timestamp_ns
= ktime_get_ns();
6946 bundle
->flip_addrs
[planes_count
].flip_timestamp_in_us
= div_u64(timestamp_ns
, 1000);
6947 bundle
->surface_updates
[planes_count
].flip_addr
= &bundle
->flip_addrs
[planes_count
];
6948 bundle
->surface_updates
[planes_count
].surface
= dc_plane
;
6950 if (!bundle
->surface_updates
[planes_count
].surface
) {
6951 DRM_ERROR("No surface for CRTC: id=%d\n",
6952 acrtc_attach
->crtc_id
);
6956 if (plane
== pcrtc
->primary
)
6957 update_freesync_state_on_stream(
6960 acrtc_state
->stream
,
6962 bundle
->flip_addrs
[planes_count
].flip_timestamp_in_us
);
6964 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
6966 bundle
->flip_addrs
[planes_count
].address
.grph
.addr
.high_part
,
6967 bundle
->flip_addrs
[planes_count
].address
.grph
.addr
.low_part
);
6973 if (pflip_present
) {
6975 /* Use old throttling in non-vrr fixed refresh rate mode
6976 * to keep flip scheduling based on target vblank counts
6977 * working in a backwards compatible way, e.g., for
6978 * clients using the GLX_OML_sync_control extension or
6979 * DRI3/Present extension with defined target_msc.
6981 last_flip_vblank
= amdgpu_get_vblank_counter_kms(pcrtc
);
6984 /* For variable refresh rate mode only:
6985 * Get vblank of last completed flip to avoid > 1 vrr
6986 * flips per video frame by use of throttling, but allow
6987 * flip programming anywhere in the possibly large
6988 * variable vrr vblank interval for fine-grained flip
6989 * timing control and more opportunity to avoid stutter
6990 * on late submission of flips.
6992 spin_lock_irqsave(&pcrtc
->dev
->event_lock
, flags
);
6993 last_flip_vblank
= acrtc_attach
->last_flip_vblank
;
6994 spin_unlock_irqrestore(&pcrtc
->dev
->event_lock
, flags
);
6997 target_vblank
= last_flip_vblank
+ wait_for_vblank
;
7000 * Wait until we're out of the vertical blank period before the one
7001 * targeted by the flip
7003 while ((acrtc_attach
->enabled
&&
7004 (amdgpu_display_get_crtc_scanoutpos(dm
->ddev
, acrtc_attach
->crtc_id
,
7005 0, &vpos
, &hpos
, NULL
,
7006 NULL
, &pcrtc
->hwmode
)
7007 & (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_IN_VBLANK
)) ==
7008 (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_IN_VBLANK
) &&
7009 (int)(target_vblank
-
7010 amdgpu_get_vblank_counter_kms(pcrtc
)) > 0)) {
7011 usleep_range(1000, 1100);
7014 if (acrtc_attach
->base
.state
->event
) {
7015 drm_crtc_vblank_get(pcrtc
);
7017 spin_lock_irqsave(&pcrtc
->dev
->event_lock
, flags
);
7019 WARN_ON(acrtc_attach
->pflip_status
!= AMDGPU_FLIP_NONE
);
7020 prepare_flip_isr(acrtc_attach
);
7022 spin_unlock_irqrestore(&pcrtc
->dev
->event_lock
, flags
);
7025 if (acrtc_state
->stream
) {
7026 if (acrtc_state
->freesync_vrr_info_changed
)
7027 bundle
->stream_update
.vrr_infopacket
=
7028 &acrtc_state
->stream
->vrr_infopacket
;
7032 /* Update the planes if changed or disable if we don't have any. */
7033 if ((planes_count
|| acrtc_state
->active_planes
== 0) &&
7034 acrtc_state
->stream
) {
7035 bundle
->stream_update
.stream
= acrtc_state
->stream
;
7036 if (new_pcrtc_state
->mode_changed
) {
7037 bundle
->stream_update
.src
= acrtc_state
->stream
->src
;
7038 bundle
->stream_update
.dst
= acrtc_state
->stream
->dst
;
7041 if (new_pcrtc_state
->color_mgmt_changed
) {
7043 * TODO: This isn't fully correct since we've actually
7044 * already modified the stream in place.
7046 bundle
->stream_update
.gamut_remap
=
7047 &acrtc_state
->stream
->gamut_remap_matrix
;
7048 bundle
->stream_update
.output_csc_transform
=
7049 &acrtc_state
->stream
->csc_color_matrix
;
7050 bundle
->stream_update
.out_transfer_func
=
7051 acrtc_state
->stream
->out_transfer_func
;
7054 acrtc_state
->stream
->abm_level
= acrtc_state
->abm_level
;
7055 if (acrtc_state
->abm_level
!= dm_old_crtc_state
->abm_level
)
7056 bundle
->stream_update
.abm_level
= &acrtc_state
->abm_level
;
7059 * If FreeSync state on the stream has changed then we need to
7060 * re-adjust the min/max bounds now that DC doesn't handle this
7061 * as part of commit.
7063 if (amdgpu_dm_vrr_active(dm_old_crtc_state
) !=
7064 amdgpu_dm_vrr_active(acrtc_state
)) {
7065 spin_lock_irqsave(&pcrtc
->dev
->event_lock
, flags
);
7066 dc_stream_adjust_vmin_vmax(
7067 dm
->dc
, acrtc_state
->stream
,
7068 &acrtc_state
->vrr_params
.adjust
);
7069 spin_unlock_irqrestore(&pcrtc
->dev
->event_lock
, flags
);
7071 mutex_lock(&dm
->dc_lock
);
7072 if ((acrtc_state
->update_type
> UPDATE_TYPE_FAST
) &&
7073 acrtc_state
->stream
->link
->psr_settings
.psr_allow_active
)
7074 amdgpu_dm_psr_disable(acrtc_state
->stream
);
7076 dc_commit_updates_for_stream(dm
->dc
,
7077 bundle
->surface_updates
,
7079 acrtc_state
->stream
,
7080 &bundle
->stream_update
,
7083 if ((acrtc_state
->update_type
> UPDATE_TYPE_FAST
) &&
7084 acrtc_state
->stream
->link
->psr_settings
.psr_version
!= DC_PSR_VERSION_UNSUPPORTED
&&
7085 !acrtc_state
->stream
->link
->psr_settings
.psr_feature_enabled
)
7086 amdgpu_dm_link_setup_psr(acrtc_state
->stream
);
7087 else if ((acrtc_state
->update_type
== UPDATE_TYPE_FAST
) &&
7088 acrtc_state
->stream
->link
->psr_settings
.psr_feature_enabled
&&
7089 !acrtc_state
->stream
->link
->psr_settings
.psr_allow_active
) {
7090 amdgpu_dm_psr_enable(acrtc_state
->stream
);
7093 mutex_unlock(&dm
->dc_lock
);
7097 * Update cursor state *after* programming all the planes.
7098 * This avoids redundant programming in the case where we're going
7099 * to be disabling a single plane - those pipes are being disabled.
7101 if (acrtc_state
->active_planes
)
7102 amdgpu_dm_commit_cursors(state
);
7108 static void amdgpu_dm_commit_audio(struct drm_device
*dev
,
7109 struct drm_atomic_state
*state
)
7111 struct amdgpu_device
*adev
= dev
->dev_private
;
7112 struct amdgpu_dm_connector
*aconnector
;
7113 struct drm_connector
*connector
;
7114 struct drm_connector_state
*old_con_state
, *new_con_state
;
7115 struct drm_crtc_state
*new_crtc_state
;
7116 struct dm_crtc_state
*new_dm_crtc_state
;
7117 const struct dc_stream_status
*status
;
7120 /* Notify device removals. */
7121 for_each_oldnew_connector_in_state(state
, connector
, old_con_state
, new_con_state
, i
) {
7122 if (old_con_state
->crtc
!= new_con_state
->crtc
) {
7123 /* CRTC changes require notification. */
7127 if (!new_con_state
->crtc
)
7130 new_crtc_state
= drm_atomic_get_new_crtc_state(
7131 state
, new_con_state
->crtc
);
7133 if (!new_crtc_state
)
7136 if (!drm_atomic_crtc_needs_modeset(new_crtc_state
))
7140 aconnector
= to_amdgpu_dm_connector(connector
);
7142 mutex_lock(&adev
->dm
.audio_lock
);
7143 inst
= aconnector
->audio_inst
;
7144 aconnector
->audio_inst
= -1;
7145 mutex_unlock(&adev
->dm
.audio_lock
);
7147 amdgpu_dm_audio_eld_notify(adev
, inst
);
7150 /* Notify audio device additions. */
7151 for_each_new_connector_in_state(state
, connector
, new_con_state
, i
) {
7152 if (!new_con_state
->crtc
)
7155 new_crtc_state
= drm_atomic_get_new_crtc_state(
7156 state
, new_con_state
->crtc
);
7158 if (!new_crtc_state
)
7161 if (!drm_atomic_crtc_needs_modeset(new_crtc_state
))
7164 new_dm_crtc_state
= to_dm_crtc_state(new_crtc_state
);
7165 if (!new_dm_crtc_state
->stream
)
7168 status
= dc_stream_get_status(new_dm_crtc_state
->stream
);
7172 aconnector
= to_amdgpu_dm_connector(connector
);
7174 mutex_lock(&adev
->dm
.audio_lock
);
7175 inst
= status
->audio_inst
;
7176 aconnector
->audio_inst
= inst
;
7177 mutex_unlock(&adev
->dm
.audio_lock
);
7179 amdgpu_dm_audio_eld_notify(adev
, inst
);
7184 * Enable interrupts on CRTCs that are newly active, undergone
7185 * a modeset, or have active planes again.
7187 * Done in two passes, based on the for_modeset flag:
7188 * Pass 1: For CRTCs going through modeset
7189 * Pass 2: For CRTCs going from 0 to n active planes
7191 * Interrupts can only be enabled after the planes are programmed,
7192 * so this requires a two-pass approach since we don't want to
7193 * just defer the interrupts until after commit planes every time.
7195 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device
*dev
,
7196 struct drm_atomic_state
*state
,
7199 struct amdgpu_device
*adev
= dev
->dev_private
;
7200 struct drm_crtc
*crtc
;
7201 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
7203 #ifdef CONFIG_DEBUG_FS
7204 enum amdgpu_dm_pipe_crc_source source
;
7207 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
,
7208 new_crtc_state
, i
) {
7209 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
7210 struct dm_crtc_state
*dm_new_crtc_state
=
7211 to_dm_crtc_state(new_crtc_state
);
7212 struct dm_crtc_state
*dm_old_crtc_state
=
7213 to_dm_crtc_state(old_crtc_state
);
7214 bool modeset
= drm_atomic_crtc_needs_modeset(new_crtc_state
);
7217 run_pass
= (for_modeset
&& modeset
) ||
7218 (!for_modeset
&& !modeset
&&
7219 !dm_old_crtc_state
->interrupts_enabled
);
7224 if (!dm_new_crtc_state
->interrupts_enabled
)
7227 manage_dm_interrupts(adev
, acrtc
, true);
7229 #ifdef CONFIG_DEBUG_FS
7230 /* The stream has changed so CRC capture needs to re-enabled. */
7231 source
= dm_new_crtc_state
->crc_src
;
7232 if (amdgpu_dm_is_valid_crc_source(source
)) {
7233 amdgpu_dm_crtc_configure_crc_source(
7234 crtc
, dm_new_crtc_state
,
7235 dm_new_crtc_state
->crc_src
);
7242 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
7243 * @crtc_state: the DRM CRTC state
7244 * @stream_state: the DC stream state.
7246 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
7247 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
7249 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state
*crtc_state
,
7250 struct dc_stream_state
*stream_state
)
7252 stream_state
->mode_changed
= drm_atomic_crtc_needs_modeset(crtc_state
);
7255 static int amdgpu_dm_atomic_commit(struct drm_device
*dev
,
7256 struct drm_atomic_state
*state
,
7259 struct drm_crtc
*crtc
;
7260 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
7261 struct amdgpu_device
*adev
= dev
->dev_private
;
7265 * We evade vblank and pflip interrupts on CRTCs that are undergoing
7266 * a modeset, being disabled, or have no active planes.
7268 * It's done in atomic commit rather than commit tail for now since
7269 * some of these interrupt handlers access the current CRTC state and
7270 * potentially the stream pointer itself.
7272 * Since the atomic state is swapped within atomic commit and not within
7273 * commit tail this would leave to new state (that hasn't been committed yet)
7274 * being accesssed from within the handlers.
7276 * TODO: Fix this so we can do this in commit tail and not have to block
7279 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
7280 struct dm_crtc_state
*dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
7281 struct dm_crtc_state
*dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
7282 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
7284 if (dm_old_crtc_state
->interrupts_enabled
&&
7285 (!dm_new_crtc_state
->interrupts_enabled
||
7286 drm_atomic_crtc_needs_modeset(new_crtc_state
)))
7287 manage_dm_interrupts(adev
, acrtc
, false);
7290 * Add check here for SoC's that support hardware cursor plane, to
7291 * unset legacy_cursor_update
7294 return drm_atomic_helper_commit(dev
, state
, nonblock
);
7296 /*TODO Handle EINTR, reenable IRQ*/
7300 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
7301 * @state: The atomic state to commit
7303 * This will tell DC to commit the constructed DC state from atomic_check,
7304 * programming the hardware. Any failures here implies a hardware failure, since
7305 * atomic check should have filtered anything non-kosher.
7307 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state
*state
)
7309 struct drm_device
*dev
= state
->dev
;
7310 struct amdgpu_device
*adev
= dev
->dev_private
;
7311 struct amdgpu_display_manager
*dm
= &adev
->dm
;
7312 struct dm_atomic_state
*dm_state
;
7313 struct dc_state
*dc_state
= NULL
, *dc_state_temp
= NULL
;
7315 struct drm_crtc
*crtc
;
7316 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
7317 unsigned long flags
;
7318 bool wait_for_vblank
= true;
7319 struct drm_connector
*connector
;
7320 struct drm_connector_state
*old_con_state
, *new_con_state
;
7321 struct dm_crtc_state
*dm_old_crtc_state
, *dm_new_crtc_state
;
7322 int crtc_disable_count
= 0;
7324 drm_atomic_helper_update_legacy_modeset_state(dev
, state
);
7326 dm_state
= dm_atomic_get_new_state(state
);
7327 if (dm_state
&& dm_state
->context
) {
7328 dc_state
= dm_state
->context
;
7330 /* No state changes, retain current state. */
7331 dc_state_temp
= dc_create_state(dm
->dc
);
7332 ASSERT(dc_state_temp
);
7333 dc_state
= dc_state_temp
;
7334 dc_resource_state_copy_construct_current(dm
->dc
, dc_state
);
7337 /* update changed items */
7338 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
7339 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
7341 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
7342 dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
7345 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
7346 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
7347 "connectors_changed:%d\n",
7349 new_crtc_state
->enable
,
7350 new_crtc_state
->active
,
7351 new_crtc_state
->planes_changed
,
7352 new_crtc_state
->mode_changed
,
7353 new_crtc_state
->active_changed
,
7354 new_crtc_state
->connectors_changed
);
7356 /* Copy all transient state flags into dc state */
7357 if (dm_new_crtc_state
->stream
) {
7358 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state
->base
,
7359 dm_new_crtc_state
->stream
);
7362 /* handles headless hotplug case, updating new_state and
7363 * aconnector as needed
7366 if (modeset_required(new_crtc_state
, dm_new_crtc_state
->stream
, dm_old_crtc_state
->stream
)) {
7368 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc
->crtc_id
, acrtc
);
7370 if (!dm_new_crtc_state
->stream
) {
7372 * this could happen because of issues with
7373 * userspace notifications delivery.
7374 * In this case userspace tries to set mode on
7375 * display which is disconnected in fact.
7376 * dc_sink is NULL in this case on aconnector.
7377 * We expect reset mode will come soon.
7379 * This can also happen when unplug is done
7380 * during resume sequence ended
7382 * In this case, we want to pretend we still
7383 * have a sink to keep the pipe running so that
7384 * hw state is consistent with the sw state
7386 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
7387 __func__
, acrtc
->base
.base
.id
);
7391 if (dm_old_crtc_state
->stream
)
7392 remove_stream(adev
, acrtc
, dm_old_crtc_state
->stream
);
7394 pm_runtime_get_noresume(dev
->dev
);
7396 acrtc
->enabled
= true;
7397 acrtc
->hw_mode
= new_crtc_state
->mode
;
7398 crtc
->hwmode
= new_crtc_state
->mode
;
7399 } else if (modereset_required(new_crtc_state
)) {
7400 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc
->crtc_id
, acrtc
);
7401 /* i.e. reset mode */
7402 if (dm_old_crtc_state
->stream
) {
7403 if (dm_old_crtc_state
->stream
->link
->psr_settings
.psr_allow_active
)
7404 amdgpu_dm_psr_disable(dm_old_crtc_state
->stream
);
7406 remove_stream(adev
, acrtc
, dm_old_crtc_state
->stream
);
7409 } /* for_each_crtc_in_state() */
7412 dm_enable_per_frame_crtc_master_sync(dc_state
);
7413 mutex_lock(&dm
->dc_lock
);
7414 WARN_ON(!dc_commit_state(dm
->dc
, dc_state
));
7415 mutex_unlock(&dm
->dc_lock
);
7418 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
7419 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
7421 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
7423 if (dm_new_crtc_state
->stream
!= NULL
) {
7424 const struct dc_stream_status
*status
=
7425 dc_stream_get_status(dm_new_crtc_state
->stream
);
7428 status
= dc_stream_get_status_from_state(dc_state
,
7429 dm_new_crtc_state
->stream
);
7432 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state
->stream
, acrtc
);
7434 acrtc
->otg_inst
= status
->primary_otg_inst
;
7437 #ifdef CONFIG_DRM_AMD_DC_HDCP
7438 for_each_oldnew_connector_in_state(state
, connector
, old_con_state
, new_con_state
, i
) {
7439 struct dm_connector_state
*dm_new_con_state
= to_dm_connector_state(new_con_state
);
7440 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(dm_new_con_state
->base
.crtc
);
7441 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
7443 new_crtc_state
= NULL
;
7446 new_crtc_state
= drm_atomic_get_new_crtc_state(state
, &acrtc
->base
);
7448 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
7450 if (dm_new_crtc_state
&& dm_new_crtc_state
->stream
== NULL
&&
7451 connector
->state
->content_protection
== DRM_MODE_CONTENT_PROTECTION_ENABLED
) {
7452 hdcp_reset_display(adev
->dm
.hdcp_workqueue
, aconnector
->dc_link
->link_index
);
7453 new_con_state
->content_protection
= DRM_MODE_CONTENT_PROTECTION_DESIRED
;
7457 if (is_content_protection_different(new_con_state
, old_con_state
, connector
, adev
->dm
.hdcp_workqueue
))
7458 hdcp_update_display(
7459 adev
->dm
.hdcp_workqueue
, aconnector
->dc_link
->link_index
, aconnector
,
7460 new_con_state
->hdcp_content_type
,
7461 new_con_state
->content_protection
== DRM_MODE_CONTENT_PROTECTION_DESIRED
? true
7466 /* Handle connector state changes */
7467 for_each_oldnew_connector_in_state(state
, connector
, old_con_state
, new_con_state
, i
) {
7468 struct dm_connector_state
*dm_new_con_state
= to_dm_connector_state(new_con_state
);
7469 struct dm_connector_state
*dm_old_con_state
= to_dm_connector_state(old_con_state
);
7470 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(dm_new_con_state
->base
.crtc
);
7471 struct dc_surface_update dummy_updates
[MAX_SURFACES
];
7472 struct dc_stream_update stream_update
;
7473 struct dc_info_packet hdr_packet
;
7474 struct dc_stream_status
*status
= NULL
;
7475 bool abm_changed
, hdr_changed
, scaling_changed
;
7477 memset(&dummy_updates
, 0, sizeof(dummy_updates
));
7478 memset(&stream_update
, 0, sizeof(stream_update
));
7481 new_crtc_state
= drm_atomic_get_new_crtc_state(state
, &acrtc
->base
);
7482 old_crtc_state
= drm_atomic_get_old_crtc_state(state
, &acrtc
->base
);
7485 /* Skip any modesets/resets */
7486 if (!acrtc
|| drm_atomic_crtc_needs_modeset(new_crtc_state
))
7489 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
7490 dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
7492 scaling_changed
= is_scaling_state_different(dm_new_con_state
,
7495 abm_changed
= dm_new_crtc_state
->abm_level
!=
7496 dm_old_crtc_state
->abm_level
;
7499 is_hdr_metadata_different(old_con_state
, new_con_state
);
7501 if (!scaling_changed
&& !abm_changed
&& !hdr_changed
)
7504 stream_update
.stream
= dm_new_crtc_state
->stream
;
7505 if (scaling_changed
) {
7506 update_stream_scaling_settings(&dm_new_con_state
->base
.crtc
->mode
,
7507 dm_new_con_state
, dm_new_crtc_state
->stream
);
7509 stream_update
.src
= dm_new_crtc_state
->stream
->src
;
7510 stream_update
.dst
= dm_new_crtc_state
->stream
->dst
;
7514 dm_new_crtc_state
->stream
->abm_level
= dm_new_crtc_state
->abm_level
;
7516 stream_update
.abm_level
= &dm_new_crtc_state
->abm_level
;
7520 fill_hdr_info_packet(new_con_state
, &hdr_packet
);
7521 stream_update
.hdr_static_metadata
= &hdr_packet
;
7524 status
= dc_stream_get_status(dm_new_crtc_state
->stream
);
7526 WARN_ON(!status
->plane_count
);
7529 * TODO: DC refuses to perform stream updates without a dc_surface_update.
7530 * Here we create an empty update on each plane.
7531 * To fix this, DC should permit updating only stream properties.
7533 for (j
= 0; j
< status
->plane_count
; j
++)
7534 dummy_updates
[j
].surface
= status
->plane_states
[0];
7537 mutex_lock(&dm
->dc_lock
);
7538 dc_commit_updates_for_stream(dm
->dc
,
7540 status
->plane_count
,
7541 dm_new_crtc_state
->stream
,
7544 mutex_unlock(&dm
->dc_lock
);
7547 /* Count number of newly disabled CRTCs for dropping PM refs later. */
7548 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
,
7549 new_crtc_state
, i
) {
7550 if (old_crtc_state
->active
&& !new_crtc_state
->active
)
7551 crtc_disable_count
++;
7553 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
7554 dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
7556 /* Update freesync active state. */
7557 pre_update_freesync_state_on_stream(dm
, dm_new_crtc_state
);
7559 /* Handle vrr on->off / off->on transitions */
7560 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state
,
7564 /* Enable interrupts for CRTCs going through a modeset. */
7565 amdgpu_dm_enable_crtc_interrupts(dev
, state
, true);
7567 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, j
)
7568 if (new_crtc_state
->async_flip
)
7569 wait_for_vblank
= false;
7571 /* update planes when needed per crtc*/
7572 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, j
) {
7573 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
7575 if (dm_new_crtc_state
->stream
)
7576 amdgpu_dm_commit_planes(state
, dc_state
, dev
,
7577 dm
, crtc
, wait_for_vblank
);
7580 /* Enable interrupts for CRTCs going from 0 to n active planes. */
7581 amdgpu_dm_enable_crtc_interrupts(dev
, state
, false);
7583 /* Update audio instances for each connector. */
7584 amdgpu_dm_commit_audio(dev
, state
);
7587 * send vblank event on all events not handled in flip and
7588 * mark consumed event for drm_atomic_helper_commit_hw_done
7590 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
7591 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
7593 if (new_crtc_state
->event
)
7594 drm_send_event_locked(dev
, &new_crtc_state
->event
->base
);
7596 new_crtc_state
->event
= NULL
;
7598 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
7600 /* Signal HW programming completion */
7601 drm_atomic_helper_commit_hw_done(state
);
7603 if (wait_for_vblank
)
7604 drm_atomic_helper_wait_for_flip_done(dev
, state
);
7606 drm_atomic_helper_cleanup_planes(dev
, state
);
7609 * Finally, drop a runtime PM reference for each newly disabled CRTC,
7610 * so we can put the GPU into runtime suspend if we're not driving any
7613 for (i
= 0; i
< crtc_disable_count
; i
++)
7614 pm_runtime_put_autosuspend(dev
->dev
);
7615 pm_runtime_mark_last_busy(dev
->dev
);
7618 dc_release_state(dc_state_temp
);
7622 static int dm_force_atomic_commit(struct drm_connector
*connector
)
7625 struct drm_device
*ddev
= connector
->dev
;
7626 struct drm_atomic_state
*state
= drm_atomic_state_alloc(ddev
);
7627 struct amdgpu_crtc
*disconnected_acrtc
= to_amdgpu_crtc(connector
->encoder
->crtc
);
7628 struct drm_plane
*plane
= disconnected_acrtc
->base
.primary
;
7629 struct drm_connector_state
*conn_state
;
7630 struct drm_crtc_state
*crtc_state
;
7631 struct drm_plane_state
*plane_state
;
7636 state
->acquire_ctx
= ddev
->mode_config
.acquire_ctx
;
7638 /* Construct an atomic state to restore previous display setting */
7641 * Attach connectors to drm_atomic_state
7643 conn_state
= drm_atomic_get_connector_state(state
, connector
);
7645 ret
= PTR_ERR_OR_ZERO(conn_state
);
7649 /* Attach crtc to drm_atomic_state*/
7650 crtc_state
= drm_atomic_get_crtc_state(state
, &disconnected_acrtc
->base
);
7652 ret
= PTR_ERR_OR_ZERO(crtc_state
);
7656 /* force a restore */
7657 crtc_state
->mode_changed
= true;
7659 /* Attach plane to drm_atomic_state */
7660 plane_state
= drm_atomic_get_plane_state(state
, plane
);
7662 ret
= PTR_ERR_OR_ZERO(plane_state
);
7667 /* Call commit internally with the state we just constructed */
7668 ret
= drm_atomic_commit(state
);
7673 DRM_ERROR("Restoring old state failed with %i\n", ret
);
7674 drm_atomic_state_put(state
);
7680 * This function handles all cases when set mode does not come upon hotplug.
7681 * This includes when a display is unplugged then plugged back into the
7682 * same port and when running without usermode desktop manager supprot
7684 void dm_restore_drm_connector_state(struct drm_device
*dev
,
7685 struct drm_connector
*connector
)
7687 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
7688 struct amdgpu_crtc
*disconnected_acrtc
;
7689 struct dm_crtc_state
*acrtc_state
;
7691 if (!aconnector
->dc_sink
|| !connector
->state
|| !connector
->encoder
)
7694 disconnected_acrtc
= to_amdgpu_crtc(connector
->encoder
->crtc
);
7695 if (!disconnected_acrtc
)
7698 acrtc_state
= to_dm_crtc_state(disconnected_acrtc
->base
.state
);
7699 if (!acrtc_state
->stream
)
7703 * If the previous sink is not released and different from the current,
7704 * we deduce we are in a state where we can not rely on usermode call
7705 * to turn on the display, so we do it here
7707 if (acrtc_state
->stream
->sink
!= aconnector
->dc_sink
)
7708 dm_force_atomic_commit(&aconnector
->base
);
7712 * Grabs all modesetting locks to serialize against any blocking commits,
7713 * Waits for completion of all non blocking commits.
7715 static int do_aquire_global_lock(struct drm_device
*dev
,
7716 struct drm_atomic_state
*state
)
7718 struct drm_crtc
*crtc
;
7719 struct drm_crtc_commit
*commit
;
7723 * Adding all modeset locks to aquire_ctx will
7724 * ensure that when the framework release it the
7725 * extra locks we are locking here will get released to
7727 ret
= drm_modeset_lock_all_ctx(dev
, state
->acquire_ctx
);
7731 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7732 spin_lock(&crtc
->commit_lock
);
7733 commit
= list_first_entry_or_null(&crtc
->commit_list
,
7734 struct drm_crtc_commit
, commit_entry
);
7736 drm_crtc_commit_get(commit
);
7737 spin_unlock(&crtc
->commit_lock
);
7743 * Make sure all pending HW programming completed and
7746 ret
= wait_for_completion_interruptible_timeout(&commit
->hw_done
, 10*HZ
);
7749 ret
= wait_for_completion_interruptible_timeout(
7750 &commit
->flip_done
, 10*HZ
);
7753 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
7754 "timed out\n", crtc
->base
.id
, crtc
->name
);
7756 drm_crtc_commit_put(commit
);
7759 return ret
< 0 ? ret
: 0;
7762 static void get_freesync_config_for_crtc(
7763 struct dm_crtc_state
*new_crtc_state
,
7764 struct dm_connector_state
*new_con_state
)
7766 struct mod_freesync_config config
= {0};
7767 struct amdgpu_dm_connector
*aconnector
=
7768 to_amdgpu_dm_connector(new_con_state
->base
.connector
);
7769 struct drm_display_mode
*mode
= &new_crtc_state
->base
.mode
;
7770 int vrefresh
= drm_mode_vrefresh(mode
);
7772 new_crtc_state
->vrr_supported
= new_con_state
->freesync_capable
&&
7773 vrefresh
>= aconnector
->min_vfreq
&&
7774 vrefresh
<= aconnector
->max_vfreq
;
7776 if (new_crtc_state
->vrr_supported
) {
7777 new_crtc_state
->stream
->ignore_msa_timing_param
= true;
7778 config
.state
= new_crtc_state
->base
.vrr_enabled
?
7779 VRR_STATE_ACTIVE_VARIABLE
:
7781 config
.min_refresh_in_uhz
=
7782 aconnector
->min_vfreq
* 1000000;
7783 config
.max_refresh_in_uhz
=
7784 aconnector
->max_vfreq
* 1000000;
7785 config
.vsif_supported
= true;
7789 new_crtc_state
->freesync_config
= config
;
7792 static void reset_freesync_config_for_crtc(
7793 struct dm_crtc_state
*new_crtc_state
)
7795 new_crtc_state
->vrr_supported
= false;
7797 memset(&new_crtc_state
->vrr_params
, 0,
7798 sizeof(new_crtc_state
->vrr_params
));
7799 memset(&new_crtc_state
->vrr_infopacket
, 0,
7800 sizeof(new_crtc_state
->vrr_infopacket
));
7803 static int dm_update_crtc_state(struct amdgpu_display_manager
*dm
,
7804 struct drm_atomic_state
*state
,
7805 struct drm_crtc
*crtc
,
7806 struct drm_crtc_state
*old_crtc_state
,
7807 struct drm_crtc_state
*new_crtc_state
,
7809 bool *lock_and_validation_needed
)
7811 struct dm_atomic_state
*dm_state
= NULL
;
7812 struct dm_crtc_state
*dm_old_crtc_state
, *dm_new_crtc_state
;
7813 struct dc_stream_state
*new_stream
;
7817 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
7818 * update changed items
7820 struct amdgpu_crtc
*acrtc
= NULL
;
7821 struct amdgpu_dm_connector
*aconnector
= NULL
;
7822 struct drm_connector_state
*drm_new_conn_state
= NULL
, *drm_old_conn_state
= NULL
;
7823 struct dm_connector_state
*dm_new_conn_state
= NULL
, *dm_old_conn_state
= NULL
;
7827 dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
7828 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
7829 acrtc
= to_amdgpu_crtc(crtc
);
7830 aconnector
= amdgpu_dm_find_first_crtc_matching_connector(state
, crtc
);
7832 /* TODO This hack should go away */
7833 if (aconnector
&& enable
) {
7834 /* Make sure fake sink is created in plug-in scenario */
7835 drm_new_conn_state
= drm_atomic_get_new_connector_state(state
,
7837 drm_old_conn_state
= drm_atomic_get_old_connector_state(state
,
7840 if (IS_ERR(drm_new_conn_state
)) {
7841 ret
= PTR_ERR_OR_ZERO(drm_new_conn_state
);
7845 dm_new_conn_state
= to_dm_connector_state(drm_new_conn_state
);
7846 dm_old_conn_state
= to_dm_connector_state(drm_old_conn_state
);
7848 if (!drm_atomic_crtc_needs_modeset(new_crtc_state
))
7851 new_stream
= create_validate_stream_for_sink(aconnector
,
7852 &new_crtc_state
->mode
,
7854 dm_old_crtc_state
->stream
);
7857 * we can have no stream on ACTION_SET if a display
7858 * was disconnected during S3, in this case it is not an
7859 * error, the OS will be updated after detection, and
7860 * will do the right thing on next atomic commit
7864 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
7865 __func__
, acrtc
->base
.base
.id
);
7870 dm_new_crtc_state
->abm_level
= dm_new_conn_state
->abm_level
;
7872 ret
= fill_hdr_info_packet(drm_new_conn_state
,
7873 &new_stream
->hdr_static_metadata
);
7878 * If we already removed the old stream from the context
7879 * (and set the new stream to NULL) then we can't reuse
7880 * the old stream even if the stream and scaling are unchanged.
7881 * We'll hit the BUG_ON and black screen.
7883 * TODO: Refactor this function to allow this check to work
7884 * in all conditions.
7886 if (dm_new_crtc_state
->stream
&&
7887 dc_is_stream_unchanged(new_stream
, dm_old_crtc_state
->stream
) &&
7888 dc_is_stream_scaling_unchanged(new_stream
, dm_old_crtc_state
->stream
)) {
7889 new_crtc_state
->mode_changed
= false;
7890 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
7891 new_crtc_state
->mode_changed
);
7895 /* mode_changed flag may get updated above, need to check again */
7896 if (!drm_atomic_crtc_needs_modeset(new_crtc_state
))
7900 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
7901 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
7902 "connectors_changed:%d\n",
7904 new_crtc_state
->enable
,
7905 new_crtc_state
->active
,
7906 new_crtc_state
->planes_changed
,
7907 new_crtc_state
->mode_changed
,
7908 new_crtc_state
->active_changed
,
7909 new_crtc_state
->connectors_changed
);
7911 /* Remove stream for any changed/disabled CRTC */
7914 if (!dm_old_crtc_state
->stream
)
7917 ret
= dm_atomic_get_state(state
, &dm_state
);
7921 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
7924 /* i.e. reset mode */
7925 if (dc_remove_stream_from_ctx(
7928 dm_old_crtc_state
->stream
) != DC_OK
) {
7933 dc_stream_release(dm_old_crtc_state
->stream
);
7934 dm_new_crtc_state
->stream
= NULL
;
7936 reset_freesync_config_for_crtc(dm_new_crtc_state
);
7938 *lock_and_validation_needed
= true;
7940 } else {/* Add stream for any updated/enabled CRTC */
7942 * Quick fix to prevent NULL pointer on new_stream when
7943 * added MST connectors not found in existing crtc_state in the chained mode
7944 * TODO: need to dig out the root cause of that
7946 if (!aconnector
|| (!aconnector
->dc_sink
&& aconnector
->mst_port
))
7949 if (modereset_required(new_crtc_state
))
7952 if (modeset_required(new_crtc_state
, new_stream
,
7953 dm_old_crtc_state
->stream
)) {
7955 WARN_ON(dm_new_crtc_state
->stream
);
7957 ret
= dm_atomic_get_state(state
, &dm_state
);
7961 dm_new_crtc_state
->stream
= new_stream
;
7963 dc_stream_retain(new_stream
);
7965 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
7968 if (dc_add_stream_to_ctx(
7971 dm_new_crtc_state
->stream
) != DC_OK
) {
7976 *lock_and_validation_needed
= true;
7981 /* Release extra reference */
7983 dc_stream_release(new_stream
);
7986 * We want to do dc stream updates that do not require a
7987 * full modeset below.
7989 if (!(enable
&& aconnector
&& new_crtc_state
->enable
&&
7990 new_crtc_state
->active
))
7993 * Given above conditions, the dc state cannot be NULL because:
7994 * 1. We're in the process of enabling CRTCs (just been added
7995 * to the dc context, or already is on the context)
7996 * 2. Has a valid connector attached, and
7997 * 3. Is currently active and enabled.
7998 * => The dc stream state currently exists.
8000 BUG_ON(dm_new_crtc_state
->stream
== NULL
);
8002 /* Scaling or underscan settings */
8003 if (is_scaling_state_different(dm_old_conn_state
, dm_new_conn_state
))
8004 update_stream_scaling_settings(
8005 &new_crtc_state
->mode
, dm_new_conn_state
, dm_new_crtc_state
->stream
);
8008 dm_new_crtc_state
->abm_level
= dm_new_conn_state
->abm_level
;
8011 * Color management settings. We also update color properties
8012 * when a modeset is needed, to ensure it gets reprogrammed.
8014 if (dm_new_crtc_state
->base
.color_mgmt_changed
||
8015 drm_atomic_crtc_needs_modeset(new_crtc_state
)) {
8016 ret
= amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state
);
8021 /* Update Freesync settings. */
8022 get_freesync_config_for_crtc(dm_new_crtc_state
,
8029 dc_stream_release(new_stream
);
8033 static bool should_reset_plane(struct drm_atomic_state
*state
,
8034 struct drm_plane
*plane
,
8035 struct drm_plane_state
*old_plane_state
,
8036 struct drm_plane_state
*new_plane_state
)
8038 struct drm_plane
*other
;
8039 struct drm_plane_state
*old_other_state
, *new_other_state
;
8040 struct drm_crtc_state
*new_crtc_state
;
8044 * TODO: Remove this hack once the checks below are sufficient
8045 * enough to determine when we need to reset all the planes on
8048 if (state
->allow_modeset
)
8051 /* Exit early if we know that we're adding or removing the plane. */
8052 if (old_plane_state
->crtc
!= new_plane_state
->crtc
)
8055 /* old crtc == new_crtc == NULL, plane not in context. */
8056 if (!new_plane_state
->crtc
)
8060 drm_atomic_get_new_crtc_state(state
, new_plane_state
->crtc
);
8062 if (!new_crtc_state
)
8065 /* CRTC Degamma changes currently require us to recreate planes. */
8066 if (new_crtc_state
->color_mgmt_changed
)
8069 if (drm_atomic_crtc_needs_modeset(new_crtc_state
))
8073 * If there are any new primary or overlay planes being added or
8074 * removed then the z-order can potentially change. To ensure
8075 * correct z-order and pipe acquisition the current DC architecture
8076 * requires us to remove and recreate all existing planes.
8078 * TODO: Come up with a more elegant solution for this.
8080 for_each_oldnew_plane_in_state(state
, other
, old_other_state
, new_other_state
, i
) {
8081 if (other
->type
== DRM_PLANE_TYPE_CURSOR
)
8084 if (old_other_state
->crtc
!= new_plane_state
->crtc
&&
8085 new_other_state
->crtc
!= new_plane_state
->crtc
)
8088 if (old_other_state
->crtc
!= new_other_state
->crtc
)
8091 /* TODO: Remove this once we can handle fast format changes. */
8092 if (old_other_state
->fb
&& new_other_state
->fb
&&
8093 old_other_state
->fb
->format
!= new_other_state
->fb
->format
)
8100 static int dm_update_plane_state(struct dc
*dc
,
8101 struct drm_atomic_state
*state
,
8102 struct drm_plane
*plane
,
8103 struct drm_plane_state
*old_plane_state
,
8104 struct drm_plane_state
*new_plane_state
,
8106 bool *lock_and_validation_needed
)
8109 struct dm_atomic_state
*dm_state
= NULL
;
8110 struct drm_crtc
*new_plane_crtc
, *old_plane_crtc
;
8111 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
8112 struct dm_crtc_state
*dm_new_crtc_state
, *dm_old_crtc_state
;
8113 struct dm_plane_state
*dm_new_plane_state
, *dm_old_plane_state
;
8114 struct amdgpu_crtc
*new_acrtc
;
8119 new_plane_crtc
= new_plane_state
->crtc
;
8120 old_plane_crtc
= old_plane_state
->crtc
;
8121 dm_new_plane_state
= to_dm_plane_state(new_plane_state
);
8122 dm_old_plane_state
= to_dm_plane_state(old_plane_state
);
8124 /*TODO Implement better atomic check for cursor plane */
8125 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
) {
8126 if (!enable
|| !new_plane_crtc
||
8127 drm_atomic_plane_disabling(plane
->state
, new_plane_state
))
8130 new_acrtc
= to_amdgpu_crtc(new_plane_crtc
);
8132 if ((new_plane_state
->crtc_w
> new_acrtc
->max_cursor_width
) ||
8133 (new_plane_state
->crtc_h
> new_acrtc
->max_cursor_height
)) {
8134 DRM_DEBUG_ATOMIC("Bad cursor size %d x %d\n",
8135 new_plane_state
->crtc_w
, new_plane_state
->crtc_h
);
8142 needs_reset
= should_reset_plane(state
, plane
, old_plane_state
,
8145 /* Remove any changed/removed planes */
8150 if (!old_plane_crtc
)
8153 old_crtc_state
= drm_atomic_get_old_crtc_state(
8154 state
, old_plane_crtc
);
8155 dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
8157 if (!dm_old_crtc_state
->stream
)
8160 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
8161 plane
->base
.id
, old_plane_crtc
->base
.id
);
8163 ret
= dm_atomic_get_state(state
, &dm_state
);
8167 if (!dc_remove_plane_from_context(
8169 dm_old_crtc_state
->stream
,
8170 dm_old_plane_state
->dc_state
,
8171 dm_state
->context
)) {
8178 dc_plane_state_release(dm_old_plane_state
->dc_state
);
8179 dm_new_plane_state
->dc_state
= NULL
;
8181 *lock_and_validation_needed
= true;
8183 } else { /* Add new planes */
8184 struct dc_plane_state
*dc_new_plane_state
;
8186 if (drm_atomic_plane_disabling(plane
->state
, new_plane_state
))
8189 if (!new_plane_crtc
)
8192 new_crtc_state
= drm_atomic_get_new_crtc_state(state
, new_plane_crtc
);
8193 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
8195 if (!dm_new_crtc_state
->stream
)
8201 WARN_ON(dm_new_plane_state
->dc_state
);
8203 dc_new_plane_state
= dc_create_plane_state(dc
);
8204 if (!dc_new_plane_state
)
8207 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
8208 plane
->base
.id
, new_plane_crtc
->base
.id
);
8210 ret
= fill_dc_plane_attributes(
8211 new_plane_crtc
->dev
->dev_private
,
8216 dc_plane_state_release(dc_new_plane_state
);
8220 ret
= dm_atomic_get_state(state
, &dm_state
);
8222 dc_plane_state_release(dc_new_plane_state
);
8227 * Any atomic check errors that occur after this will
8228 * not need a release. The plane state will be attached
8229 * to the stream, and therefore part of the atomic
8230 * state. It'll be released when the atomic state is
8233 if (!dc_add_plane_to_context(
8235 dm_new_crtc_state
->stream
,
8237 dm_state
->context
)) {
8239 dc_plane_state_release(dc_new_plane_state
);
8243 dm_new_plane_state
->dc_state
= dc_new_plane_state
;
8245 /* Tell DC to do a full surface update every time there
8246 * is a plane change. Inefficient, but works for now.
8248 dm_new_plane_state
->dc_state
->update_flags
.bits
.full_update
= 1;
8250 *lock_and_validation_needed
= true;
8258 dm_determine_update_type_for_commit(struct amdgpu_display_manager
*dm
,
8259 struct drm_atomic_state
*state
,
8260 enum surface_update_type
*out_type
)
8262 struct dc
*dc
= dm
->dc
;
8263 struct dm_atomic_state
*dm_state
= NULL
, *old_dm_state
= NULL
;
8264 int i
, j
, num_plane
, ret
= 0;
8265 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
8266 struct dm_plane_state
*new_dm_plane_state
, *old_dm_plane_state
;
8267 struct drm_crtc
*new_plane_crtc
;
8268 struct drm_plane
*plane
;
8270 struct drm_crtc
*crtc
;
8271 struct drm_crtc_state
*new_crtc_state
, *old_crtc_state
;
8272 struct dm_crtc_state
*new_dm_crtc_state
, *old_dm_crtc_state
;
8273 struct dc_stream_status
*status
= NULL
;
8274 enum surface_update_type update_type
= UPDATE_TYPE_FAST
;
8275 struct surface_info_bundle
{
8276 struct dc_surface_update surface_updates
[MAX_SURFACES
];
8277 struct dc_plane_info plane_infos
[MAX_SURFACES
];
8278 struct dc_scaling_info scaling_infos
[MAX_SURFACES
];
8279 struct dc_flip_addrs flip_addrs
[MAX_SURFACES
];
8280 struct dc_stream_update stream_update
;
8283 bundle
= kzalloc(sizeof(*bundle
), GFP_KERNEL
);
8286 DRM_ERROR("Failed to allocate update bundle\n");
8287 /* Set type to FULL to avoid crashing in DC*/
8288 update_type
= UPDATE_TYPE_FULL
;
8292 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
8294 memset(bundle
, 0, sizeof(struct surface_info_bundle
));
8296 new_dm_crtc_state
= to_dm_crtc_state(new_crtc_state
);
8297 old_dm_crtc_state
= to_dm_crtc_state(old_crtc_state
);
8300 if (new_dm_crtc_state
->stream
!= old_dm_crtc_state
->stream
) {
8301 update_type
= UPDATE_TYPE_FULL
;
8305 if (!new_dm_crtc_state
->stream
)
8308 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, j
) {
8309 const struct amdgpu_framebuffer
*amdgpu_fb
=
8310 to_amdgpu_framebuffer(new_plane_state
->fb
);
8311 struct dc_plane_info
*plane_info
= &bundle
->plane_infos
[num_plane
];
8312 struct dc_flip_addrs
*flip_addr
= &bundle
->flip_addrs
[num_plane
];
8313 struct dc_scaling_info
*scaling_info
= &bundle
->scaling_infos
[num_plane
];
8314 uint64_t tiling_flags
;
8315 bool tmz_surface
= false;
8317 new_plane_crtc
= new_plane_state
->crtc
;
8318 new_dm_plane_state
= to_dm_plane_state(new_plane_state
);
8319 old_dm_plane_state
= to_dm_plane_state(old_plane_state
);
8321 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
8324 if (new_dm_plane_state
->dc_state
!= old_dm_plane_state
->dc_state
) {
8325 update_type
= UPDATE_TYPE_FULL
;
8329 if (crtc
!= new_plane_crtc
)
8332 bundle
->surface_updates
[num_plane
].surface
=
8333 new_dm_plane_state
->dc_state
;
8335 if (new_crtc_state
->mode_changed
) {
8336 bundle
->stream_update
.dst
= new_dm_crtc_state
->stream
->dst
;
8337 bundle
->stream_update
.src
= new_dm_crtc_state
->stream
->src
;
8340 if (new_crtc_state
->color_mgmt_changed
) {
8341 bundle
->surface_updates
[num_plane
].gamma
=
8342 new_dm_plane_state
->dc_state
->gamma_correction
;
8343 bundle
->surface_updates
[num_plane
].in_transfer_func
=
8344 new_dm_plane_state
->dc_state
->in_transfer_func
;
8345 bundle
->surface_updates
[num_plane
].gamut_remap_matrix
=
8346 &new_dm_plane_state
->dc_state
->gamut_remap_matrix
;
8347 bundle
->stream_update
.gamut_remap
=
8348 &new_dm_crtc_state
->stream
->gamut_remap_matrix
;
8349 bundle
->stream_update
.output_csc_transform
=
8350 &new_dm_crtc_state
->stream
->csc_color_matrix
;
8351 bundle
->stream_update
.out_transfer_func
=
8352 new_dm_crtc_state
->stream
->out_transfer_func
;
8355 ret
= fill_dc_scaling_info(new_plane_state
,
8360 bundle
->surface_updates
[num_plane
].scaling_info
= scaling_info
;
8363 ret
= get_fb_info(amdgpu_fb
, &tiling_flags
, &tmz_surface
);
8367 ret
= fill_dc_plane_info_and_addr(
8368 dm
->adev
, new_plane_state
, tiling_flags
,
8370 &flip_addr
->address
, tmz_surface
,
8375 bundle
->surface_updates
[num_plane
].plane_info
= plane_info
;
8376 bundle
->surface_updates
[num_plane
].flip_addr
= flip_addr
;
8385 ret
= dm_atomic_get_state(state
, &dm_state
);
8389 old_dm_state
= dm_atomic_get_old_state(state
);
8390 if (!old_dm_state
) {
8395 status
= dc_stream_get_status_from_state(old_dm_state
->context
,
8396 new_dm_crtc_state
->stream
);
8397 bundle
->stream_update
.stream
= new_dm_crtc_state
->stream
;
8399 * TODO: DC modifies the surface during this call so we need
8400 * to lock here - find a way to do this without locking.
8402 mutex_lock(&dm
->dc_lock
);
8403 update_type
= dc_check_update_surfaces_for_stream(
8404 dc
, bundle
->surface_updates
, num_plane
,
8405 &bundle
->stream_update
, status
);
8406 mutex_unlock(&dm
->dc_lock
);
8408 if (update_type
> UPDATE_TYPE_MED
) {
8409 update_type
= UPDATE_TYPE_FULL
;
8417 *out_type
= update_type
;
8421 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state
*state
, struct drm_crtc
*crtc
)
8423 struct drm_connector
*connector
;
8424 struct drm_connector_state
*conn_state
;
8425 struct amdgpu_dm_connector
*aconnector
= NULL
;
8427 for_each_new_connector_in_state(state
, connector
, conn_state
, i
) {
8428 if (conn_state
->crtc
!= crtc
)
8431 aconnector
= to_amdgpu_dm_connector(connector
);
8432 if (!aconnector
->port
|| !aconnector
->mst_port
)
8441 return drm_dp_mst_add_affected_dsc_crtcs(state
, &aconnector
->mst_port
->mst_mgr
);
8445 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
8446 * @dev: The DRM device
8447 * @state: The atomic state to commit
8449 * Validate that the given atomic state is programmable by DC into hardware.
8450 * This involves constructing a &struct dc_state reflecting the new hardware
8451 * state we wish to commit, then querying DC to see if it is programmable. It's
8452 * important not to modify the existing DC state. Otherwise, atomic_check
8453 * may unexpectedly commit hardware changes.
8455 * When validating the DC state, it's important that the right locks are
8456 * acquired. For full updates case which removes/adds/updates streams on one
8457 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
8458 * that any such full update commit will wait for completion of any outstanding
8459 * flip using DRMs synchronization events. See
8460 * dm_determine_update_type_for_commit()
8462 * Note that DM adds the affected connectors for all CRTCs in state, when that
8463 * might not seem necessary. This is because DC stream creation requires the
8464 * DC sink, which is tied to the DRM connector state. Cleaning this up should
8465 * be possible but non-trivial - a possible TODO item.
8467 * Return: -Error code if validation failed.
8469 static int amdgpu_dm_atomic_check(struct drm_device
*dev
,
8470 struct drm_atomic_state
*state
)
8472 struct amdgpu_device
*adev
= dev
->dev_private
;
8473 struct dm_atomic_state
*dm_state
= NULL
;
8474 struct dc
*dc
= adev
->dm
.dc
;
8475 struct drm_connector
*connector
;
8476 struct drm_connector_state
*old_con_state
, *new_con_state
;
8477 struct drm_crtc
*crtc
;
8478 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
8479 struct drm_plane
*plane
;
8480 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
8481 enum surface_update_type update_type
= UPDATE_TYPE_FAST
;
8482 enum surface_update_type overall_update_type
= UPDATE_TYPE_FAST
;
8487 * This bool will be set for true for any modeset/reset
8488 * or plane update which implies non fast surface update.
8490 bool lock_and_validation_needed
= false;
8492 ret
= drm_atomic_helper_check_modeset(dev
, state
);
8496 if (adev
->asic_type
>= CHIP_NAVI10
) {
8497 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
8498 if (drm_atomic_crtc_needs_modeset(new_crtc_state
)) {
8499 ret
= add_affected_mst_dsc_crtcs(state
, crtc
);
8506 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
8507 if (!drm_atomic_crtc_needs_modeset(new_crtc_state
) &&
8508 !new_crtc_state
->color_mgmt_changed
&&
8509 old_crtc_state
->vrr_enabled
== new_crtc_state
->vrr_enabled
)
8512 if (!new_crtc_state
->enable
)
8515 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
8519 ret
= drm_atomic_add_affected_planes(state
, crtc
);
8525 * Add all primary and overlay planes on the CRTC to the state
8526 * whenever a plane is enabled to maintain correct z-ordering
8527 * and to enable fast surface updates.
8529 drm_for_each_crtc(crtc
, dev
) {
8530 bool modified
= false;
8532 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
) {
8533 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
8536 if (new_plane_state
->crtc
== crtc
||
8537 old_plane_state
->crtc
== crtc
) {
8546 drm_for_each_plane_mask(plane
, state
->dev
, crtc
->state
->plane_mask
) {
8547 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
8551 drm_atomic_get_plane_state(state
, plane
);
8553 if (IS_ERR(new_plane_state
)) {
8554 ret
= PTR_ERR(new_plane_state
);
8560 /* Remove exiting planes if they are modified */
8561 for_each_oldnew_plane_in_state_reverse(state
, plane
, old_plane_state
, new_plane_state
, i
) {
8562 ret
= dm_update_plane_state(dc
, state
, plane
,
8566 &lock_and_validation_needed
);
8571 /* Disable all crtcs which require disable */
8572 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
8573 ret
= dm_update_crtc_state(&adev
->dm
, state
, crtc
,
8577 &lock_and_validation_needed
);
8582 /* Enable all crtcs which require enable */
8583 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
8584 ret
= dm_update_crtc_state(&adev
->dm
, state
, crtc
,
8588 &lock_and_validation_needed
);
8593 /* Add new/modified planes */
8594 for_each_oldnew_plane_in_state_reverse(state
, plane
, old_plane_state
, new_plane_state
, i
) {
8595 ret
= dm_update_plane_state(dc
, state
, plane
,
8599 &lock_and_validation_needed
);
8604 /* Run this here since we want to validate the streams we created */
8605 ret
= drm_atomic_helper_check_planes(dev
, state
);
8609 if (state
->legacy_cursor_update
) {
8611 * This is a fast cursor update coming from the plane update
8612 * helper, check if it can be done asynchronously for better
8615 state
->async_update
=
8616 !drm_atomic_helper_async_check(dev
, state
);
8619 * Skip the remaining global validation if this is an async
8620 * update. Cursor updates can be done without affecting
8621 * state or bandwidth calcs and this avoids the performance
8622 * penalty of locking the private state object and
8623 * allocating a new dc_state.
8625 if (state
->async_update
)
8629 /* Check scaling and underscan changes*/
8630 /* TODO Removed scaling changes validation due to inability to commit
8631 * new stream into context w\o causing full reset. Need to
8632 * decide how to handle.
8634 for_each_oldnew_connector_in_state(state
, connector
, old_con_state
, new_con_state
, i
) {
8635 struct dm_connector_state
*dm_old_con_state
= to_dm_connector_state(old_con_state
);
8636 struct dm_connector_state
*dm_new_con_state
= to_dm_connector_state(new_con_state
);
8637 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(dm_new_con_state
->base
.crtc
);
8639 /* Skip any modesets/resets */
8640 if (!acrtc
|| drm_atomic_crtc_needs_modeset(
8641 drm_atomic_get_new_crtc_state(state
, &acrtc
->base
)))
8644 /* Skip any thing not scale or underscan changes */
8645 if (!is_scaling_state_different(dm_new_con_state
, dm_old_con_state
))
8648 overall_update_type
= UPDATE_TYPE_FULL
;
8649 lock_and_validation_needed
= true;
8652 ret
= dm_determine_update_type_for_commit(&adev
->dm
, state
, &update_type
);
8656 if (overall_update_type
< update_type
)
8657 overall_update_type
= update_type
;
8660 * lock_and_validation_needed was an old way to determine if we need to set
8661 * the global lock. Leaving it in to check if we broke any corner cases
8662 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
8663 * lock_and_validation_needed false = UPDATE_TYPE_FAST
8665 if (lock_and_validation_needed
&& overall_update_type
<= UPDATE_TYPE_FAST
)
8666 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
8668 if (overall_update_type
> UPDATE_TYPE_FAST
) {
8669 ret
= dm_atomic_get_state(state
, &dm_state
);
8673 ret
= do_aquire_global_lock(dev
, state
);
8677 #if defined(CONFIG_DRM_AMD_DC_DCN)
8678 if (!compute_mst_dsc_configs_for_state(state
, dm_state
->context
))
8681 ret
= dm_update_mst_vcpi_slots_for_dsc(state
, dm_state
->context
);
8687 * Perform validation of MST topology in the state:
8688 * We need to perform MST atomic check before calling
8689 * dc_validate_global_state(), or there is a chance
8690 * to get stuck in an infinite loop and hang eventually.
8692 ret
= drm_dp_mst_atomic_check(state
);
8696 if (dc_validate_global_state(dc
, dm_state
->context
, false) != DC_OK
) {
8702 * The commit is a fast update. Fast updates shouldn't change
8703 * the DC context, affect global validation, and can have their
8704 * commit work done in parallel with other commits not touching
8705 * the same resource. If we have a new DC context as part of
8706 * the DM atomic state from validation we need to free it and
8707 * retain the existing one instead.
8709 struct dm_atomic_state
*new_dm_state
, *old_dm_state
;
8711 new_dm_state
= dm_atomic_get_new_state(state
);
8712 old_dm_state
= dm_atomic_get_old_state(state
);
8714 if (new_dm_state
&& old_dm_state
) {
8715 if (new_dm_state
->context
)
8716 dc_release_state(new_dm_state
->context
);
8718 new_dm_state
->context
= old_dm_state
->context
;
8720 if (old_dm_state
->context
)
8721 dc_retain_state(old_dm_state
->context
);
8725 /* Store the overall update type for use later in atomic check. */
8726 for_each_new_crtc_in_state (state
, crtc
, new_crtc_state
, i
) {
8727 struct dm_crtc_state
*dm_new_crtc_state
=
8728 to_dm_crtc_state(new_crtc_state
);
8730 dm_new_crtc_state
->update_type
= (int)overall_update_type
;
8733 /* Must be success */
8738 if (ret
== -EDEADLK
)
8739 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
8740 else if (ret
== -EINTR
|| ret
== -EAGAIN
|| ret
== -ERESTARTSYS
)
8741 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
8743 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret
);
8748 static bool is_dp_capable_without_timing_msa(struct dc
*dc
,
8749 struct amdgpu_dm_connector
*amdgpu_dm_connector
)
8752 bool capable
= false;
8754 if (amdgpu_dm_connector
->dc_link
&&
8755 dm_helpers_dp_read_dpcd(
8757 amdgpu_dm_connector
->dc_link
,
8758 DP_DOWN_STREAM_PORT_COUNT
,
8760 sizeof(dpcd_data
))) {
8761 capable
= (dpcd_data
& DP_MSA_TIMING_PAR_IGNORED
) ? true:false;
8766 void amdgpu_dm_update_freesync_caps(struct drm_connector
*connector
,
8770 bool edid_check_required
;
8771 struct detailed_timing
*timing
;
8772 struct detailed_non_pixel
*data
;
8773 struct detailed_data_monitor_range
*range
;
8774 struct amdgpu_dm_connector
*amdgpu_dm_connector
=
8775 to_amdgpu_dm_connector(connector
);
8776 struct dm_connector_state
*dm_con_state
= NULL
;
8778 struct drm_device
*dev
= connector
->dev
;
8779 struct amdgpu_device
*adev
= dev
->dev_private
;
8780 bool freesync_capable
= false;
8782 if (!connector
->state
) {
8783 DRM_ERROR("%s - Connector has no state", __func__
);
8788 dm_con_state
= to_dm_connector_state(connector
->state
);
8790 amdgpu_dm_connector
->min_vfreq
= 0;
8791 amdgpu_dm_connector
->max_vfreq
= 0;
8792 amdgpu_dm_connector
->pixel_clock_mhz
= 0;
8797 dm_con_state
= to_dm_connector_state(connector
->state
);
8799 edid_check_required
= false;
8800 if (!amdgpu_dm_connector
->dc_sink
) {
8801 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
8804 if (!adev
->dm
.freesync_module
)
8807 * if edid non zero restrict freesync only for dp and edp
8810 if (amdgpu_dm_connector
->dc_sink
->sink_signal
== SIGNAL_TYPE_DISPLAY_PORT
8811 || amdgpu_dm_connector
->dc_sink
->sink_signal
== SIGNAL_TYPE_EDP
) {
8812 edid_check_required
= is_dp_capable_without_timing_msa(
8814 amdgpu_dm_connector
);
8817 if (edid_check_required
== true && (edid
->version
> 1 ||
8818 (edid
->version
== 1 && edid
->revision
> 1))) {
8819 for (i
= 0; i
< 4; i
++) {
8821 timing
= &edid
->detailed_timings
[i
];
8822 data
= &timing
->data
.other_data
;
8823 range
= &data
->data
.range
;
8825 * Check if monitor has continuous frequency mode
8827 if (data
->type
!= EDID_DETAIL_MONITOR_RANGE
)
8830 * Check for flag range limits only. If flag == 1 then
8831 * no additional timing information provided.
8832 * Default GTF, GTF Secondary curve and CVT are not
8835 if (range
->flags
!= 1)
8838 amdgpu_dm_connector
->min_vfreq
= range
->min_vfreq
;
8839 amdgpu_dm_connector
->max_vfreq
= range
->max_vfreq
;
8840 amdgpu_dm_connector
->pixel_clock_mhz
=
8841 range
->pixel_clock_mhz
* 10;
8845 if (amdgpu_dm_connector
->max_vfreq
-
8846 amdgpu_dm_connector
->min_vfreq
> 10) {
8848 freesync_capable
= true;
8854 dm_con_state
->freesync_capable
= freesync_capable
;
8856 if (connector
->vrr_capable_property
)
8857 drm_connector_set_vrr_capable_property(connector
,
8861 static void amdgpu_dm_set_psr_caps(struct dc_link
*link
)
8863 uint8_t dpcd_data
[EDP_PSR_RECEIVER_CAP_SIZE
];
8865 if (!(link
->connector_signal
& SIGNAL_TYPE_EDP
))
8867 if (link
->type
== dc_connection_none
)
8869 if (dm_helpers_dp_read_dpcd(NULL
, link
, DP_PSR_SUPPORT
,
8870 dpcd_data
, sizeof(dpcd_data
))) {
8871 link
->dpcd_caps
.psr_caps
.psr_version
= dpcd_data
[0];
8873 if (dpcd_data
[0] == 0) {
8874 link
->psr_settings
.psr_version
= DC_PSR_VERSION_UNSUPPORTED
;
8875 link
->psr_settings
.psr_feature_enabled
= false;
8877 link
->psr_settings
.psr_version
= DC_PSR_VERSION_1
;
8878 link
->psr_settings
.psr_feature_enabled
= true;
8881 DRM_INFO("PSR support:%d\n", link
->psr_settings
.psr_feature_enabled
);
8886 * amdgpu_dm_link_setup_psr() - configure psr link
8887 * @stream: stream state
8889 * Return: true if success
8891 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state
*stream
)
8893 struct dc_link
*link
= NULL
;
8894 struct psr_config psr_config
= {0};
8895 struct psr_context psr_context
= {0};
8901 link
= stream
->link
;
8903 psr_config
.psr_version
= link
->dpcd_caps
.psr_caps
.psr_version
;
8905 if (psr_config
.psr_version
> 0) {
8906 psr_config
.psr_exit_link_training_required
= 0x1;
8907 psr_config
.psr_frame_capture_indication_req
= 0;
8908 psr_config
.psr_rfb_setup_time
= 0x37;
8909 psr_config
.psr_sdp_transmit_line_num_deadline
= 0x20;
8910 psr_config
.allow_smu_optimizations
= 0x0;
8912 ret
= dc_link_setup_psr(link
, stream
, &psr_config
, &psr_context
);
8915 DRM_DEBUG_DRIVER("PSR link: %d\n", link
->psr_settings
.psr_feature_enabled
);
8921 * amdgpu_dm_psr_enable() - enable psr f/w
8922 * @stream: stream state
8924 * Return: true if success
8926 bool amdgpu_dm_psr_enable(struct dc_stream_state
*stream
)
8928 struct dc_link
*link
= stream
->link
;
8929 unsigned int vsync_rate_hz
= 0;
8930 struct dc_static_screen_params params
= {0};
8931 /* Calculate number of static frames before generating interrupt to
8934 // Init fail safe of 2 frames static
8935 unsigned int num_frames_static
= 2;
8937 DRM_DEBUG_DRIVER("Enabling psr...\n");
8939 vsync_rate_hz
= div64_u64(div64_u64((
8940 stream
->timing
.pix_clk_100hz
* 100),
8941 stream
->timing
.v_total
),
8942 stream
->timing
.h_total
);
8945 * Calculate number of frames such that at least 30 ms of time has
8948 if (vsync_rate_hz
!= 0) {
8949 unsigned int frame_time_microsec
= 1000000 / vsync_rate_hz
;
8950 num_frames_static
= (30000 / frame_time_microsec
) + 1;
8953 params
.triggers
.cursor_update
= true;
8954 params
.triggers
.overlay_update
= true;
8955 params
.triggers
.surface_update
= true;
8956 params
.num_frames
= num_frames_static
;
8958 dc_stream_set_static_screen_params(link
->ctx
->dc
,
8962 return dc_link_set_psr_allow_active(link
, true, false);
8966 * amdgpu_dm_psr_disable() - disable psr f/w
8967 * @stream: stream state
8969 * Return: true if success
8971 static bool amdgpu_dm_psr_disable(struct dc_stream_state
*stream
)
8974 DRM_DEBUG_DRIVER("Disabling psr...\n");
8976 return dc_link_set_psr_allow_active(stream
->link
, false, true);