drivers/gpu/drm/amd/display/dc/dc.h

   1 /*
   2  * Copyright 2012-14 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_INTERFACE_H_
  27 #define DC_INTERFACE_H_
  28
  29 #include "dc_types.h"
  30 #include "grph_object_defs.h"
  31 #include "logger_types.h"
  32 #include "gpio_types.h"
  33 #include "link_service_types.h"
  34 #include "grph_object_ctrl_defs.h"
  35 #include <inc/hw/opp.h>
  36
  37 #include "inc/hw_sequencer.h"
  38 #include "inc/compressor.h"
  39 #include "inc/hw/dmcu.h"
  40 #include "dml/display_mode_lib.h"
  41
  42 #define DC_VER "3.2.17"
  43
  44 #define MAX_SURFACES 3
  45 #define MAX_STREAMS 6
  46 #define MAX_SINKS_PER_LINK 4
  47
  48 /*******************************************************************************
  49  * Display Core Interfaces
  50  ******************************************************************************/
  51 struct dc_versions {
  52         const char *dc_ver;
  53         struct dmcu_version dmcu_version;
  54 };
  55
  56 struct dc_caps {
  57         uint32_t max_streams;
  58         uint32_t max_links;
  59         uint32_t max_audios;
  60         uint32_t max_slave_planes;
  61         uint32_t max_planes;
  62         uint32_t max_downscale_ratio;
  63         uint32_t i2c_speed_in_khz;
  64         uint32_t dmdata_alloc_size;
  65         unsigned int max_cursor_size;
  66         unsigned int max_video_width;
  67         int linear_pitch_alignment;
  68         bool dcc_const_color;
  69         bool dynamic_audio;
  70         bool is_apu;
  71         bool dual_link_dvi;
  72         bool post_blend_color_processing;
  73         bool force_dp_tps4_for_cp2520;
  74         bool disable_dp_clk_share;
  75         bool psp_setup_panel_mode;
  76 };
  77
  78 struct dc_dcc_surface_param {
  79         struct dc_size surface_size;
  80         enum surface_pixel_format format;
  81         enum swizzle_mode_values swizzle_mode;
  82         enum dc_scan_direction scan;
  83 };
  84
  85 struct dc_dcc_setting {
  86         unsigned int max_compressed_blk_size;
  87         unsigned int max_uncompressed_blk_size;
  88         bool independent_64b_blks;
  89 };
  90
  91 struct dc_surface_dcc_cap {
  92         union {
  93                 struct {
  94                         struct dc_dcc_setting rgb;
  95                 } grph;
  96
  97                 struct {
  98                         struct dc_dcc_setting luma;
  99                         struct dc_dcc_setting chroma;
 100                 } video;
 101         };
 102
 103         bool capable;
 104         bool const_color_support;
 105 };
 106
 107 struct dc_static_screen_events {
 108         bool force_trigger;
 109         bool cursor_update;
 110         bool surface_update;
 111         bool overlay_update;
 112 };
 113
 114
 115 /* Surface update type is used by dc_update_surfaces_and_stream
 116  * The update type is determined at the very beginning of the function based
 117  * on parameters passed in and decides how much programming (or updating) is
 118  * going to be done during the call.
 119  *
 120  * UPDATE_TYPE_FAST is used for really fast updates that do not require much
 121  * logical calculations or hardware register programming. This update MUST be
 122  * ISR safe on windows. Currently fast update will only be used to flip surface
 123  * address.
 124  *
 125  * UPDATE_TYPE_MED is used for slower updates which require significant hw
 126  * re-programming however do not affect bandwidth consumption or clock
 127  * requirements. At present, this is the level at which front end updates
 128  * that do not require us to run bw_calcs happen. These are in/out transfer func
 129  * updates, viewport offset changes, recout size changes and pixel depth changes.
 130  * This update can be done at ISR, but we want to minimize how often this happens.
 131  *
 132  * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
 133  * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
 134  * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
 135  * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
 136  * a full update. This cannot be done at ISR level and should be a rare event.
 137  * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
 138  * underscan we don't expect to see this call at all.
 139  */
 140
 141 enum surface_update_type {
 142         UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
 143         UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
 144         UPDATE_TYPE_FULL, /* may need to shuffle resources */
 145 };
 146
 147 /* Forward declaration*/
 148 struct dc;
 149 struct dc_plane_state;
 150 struct dc_state;
 151
 152
 153 struct dc_cap_funcs {
 154         bool (*get_dcc_compression_cap)(const struct dc *dc,
 155                         const struct dc_dcc_surface_param *input,
 156                         struct dc_surface_dcc_cap *output);
 157 };
 158
 159 struct link_training_settings;
 160
 161
 162 /* Structure to hold configuration flags set by dm at dc creation. */
 163 struct dc_config {
 164         bool gpu_vm_support;
 165         bool disable_disp_pll_sharing;
 166         bool fbc_support;
 167 };
 168
 169 enum visual_confirm {
 170         VISUAL_CONFIRM_DISABLE = 0,
 171         VISUAL_CONFIRM_SURFACE = 1,
 172         VISUAL_CONFIRM_HDR = 2,
 173 };
 174
 175 enum dcc_option {
 176         DCC_ENABLE = 0,
 177         DCC_DISABLE = 1,
 178         DCC_HALF_REQ_DISALBE = 2,
 179 };
 180
 181 enum pipe_split_policy {
 182         MPC_SPLIT_DYNAMIC = 0,
 183         MPC_SPLIT_AVOID = 1,
 184         MPC_SPLIT_AVOID_MULT_DISP = 2,
 185 };
 186
 187 enum wm_report_mode {
 188         WM_REPORT_DEFAULT = 0,
 189         WM_REPORT_OVERRIDE = 1,
 190 };
 191
 192 /*
 193  * For any clocks that may differ per pipe
 194  * only the max is stored in this structure
 195  */
 196 struct dc_clocks {
 197         int dispclk_khz;
 198         int max_supported_dppclk_khz;
 199         int dppclk_khz;
 200         int dcfclk_khz;
 201         int socclk_khz;
 202         int dcfclk_deep_sleep_khz;
 203         int fclk_khz;
 204         int phyclk_khz;
 205         int dramclk_khz;
 206 };
 207
 208 struct dc_debug_options {
 209         enum visual_confirm visual_confirm;
 210         bool sanity_checks;
 211         bool max_disp_clk;
 212         bool surface_trace;
 213         bool timing_trace;
 214         bool clock_trace;
 215         bool validation_trace;
 216         bool bandwidth_calcs_trace;
 217         int max_downscale_src_width;
 218
 219         /* stutter efficiency related */
 220         bool disable_stutter;
 221         bool use_max_lb;
 222         enum dcc_option disable_dcc;
 223         enum pipe_split_policy pipe_split_policy;
 224         bool force_single_disp_pipe_split;
 225         bool voltage_align_fclk;
 226
 227         bool disable_dfs_bypass;
 228         bool disable_dpp_power_gate;
 229         bool disable_hubp_power_gate;
 230         bool disable_pplib_wm_range;
 231         enum wm_report_mode pplib_wm_report_mode;
 232         unsigned int min_disp_clk_khz;
 233         int sr_exit_time_dpm0_ns;
 234         int sr_enter_plus_exit_time_dpm0_ns;
 235         int sr_exit_time_ns;
 236         int sr_enter_plus_exit_time_ns;
 237         int urgent_latency_ns;
 238         int percent_of_ideal_drambw;
 239         int dram_clock_change_latency_ns;
 240         bool optimized_watermark;
 241         int always_scale;
 242         bool disable_pplib_clock_request;
 243         bool disable_clock_gate;
 244         bool disable_dmcu;
 245         bool disable_psr;
 246         bool force_abm_enable;
 247         bool disable_stereo_support;
 248         bool vsr_support;
 249         bool performance_trace;
 250         bool az_endpoint_mute_only;
 251         bool always_use_regamma;
 252         bool p010_mpo_support;
 253         bool recovery_enabled;
 254         bool avoid_vbios_exec_table;
 255         bool scl_reset_length10;
 256         bool hdmi20_disable;
 257         bool skip_detection_link_training;
 258         unsigned int force_odm_combine; //bit vector based on otg inst
 259         unsigned int force_fclk_khz;
 260 };
 261
 262 struct dc_debug_data {
 263         uint32_t ltFailCount;
 264         uint32_t i2cErrorCount;
 265         uint32_t auxErrorCount;
 266 };
 267
 268 struct dc_state;
 269 struct resource_pool;
 270 struct dce_hwseq;
 271 struct dc {
 272         struct dc_versions versions;
 273         struct dc_caps caps;
 274         struct dc_cap_funcs cap_funcs;
 275         struct dc_config config;
 276         struct dc_debug_options debug;
 277         struct dc_context *ctx;
 278
 279         uint8_t link_count;
 280         struct dc_link *links[MAX_PIPES * 2];
 281
 282         struct dc_state *current_state;
 283         struct resource_pool *res_pool;
 284
 285         /* Display Engine Clock levels */
 286         struct dm_pp_clock_levels sclk_lvls;
 287
 288         /* Inputs into BW and WM calculations. */
 289         struct bw_calcs_dceip *bw_dceip;
 290         struct bw_calcs_vbios *bw_vbios;
 291 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 292         struct dcn_soc_bounding_box *dcn_soc;
 293         struct dcn_ip_params *dcn_ip;
 294         struct display_mode_lib dml;
 295 #endif
 296
 297         /* HW functions */
 298         struct hw_sequencer_funcs hwss;
 299         struct dce_hwseq *hwseq;
 300
 301         bool optimized_required;
 302
 303         /* FBC compressor */
 304         struct compressor *fbc_compressor;
 305
 306         struct dc_debug_data debug_data;
 307
 308         const char *build_id;
 309 };
 310
 311 enum frame_buffer_mode {
 312         FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
 313         FRAME_BUFFER_MODE_ZFB_ONLY,
 314         FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
 315 } ;
 316
 317 struct dchub_init_data {
 318         int64_t zfb_phys_addr_base;
 319         int64_t zfb_mc_base_addr;
 320         uint64_t zfb_size_in_byte;
 321         enum frame_buffer_mode fb_mode;
 322         bool dchub_initialzied;
 323         bool dchub_info_valid;
 324 };
 325
 326 struct dc_init_data {
 327         struct hw_asic_id asic_id;
 328         void *driver; /* ctx */
 329         struct cgs_device *cgs_device;
 330
 331         int num_virtual_links;
 332         /*
 333          * If 'vbios_override' not NULL, it will be called instead
 334          * of the real VBIOS. Intended use is Diagnostics on FPGA.
 335          */
 336         struct dc_bios *vbios_override;
 337         enum dce_environment dce_environment;
 338
 339         struct dc_config flags;
 340         uint32_t log_mask;
 341 };
 342
 343 struct dc_callback_init {
 344         uint8_t reserved;
 345 };
 346
 347 struct dc *dc_create(const struct dc_init_data *init_params);
 348 void dc_init_callbacks(struct dc *dc,
 349                 const struct dc_callback_init *init_params);
 350 void dc_destroy(struct dc **dc);
 351
 352 /*******************************************************************************
 353  * Surface Interfaces
 354  ******************************************************************************/
 355
 356 enum {
 357         TRANSFER_FUNC_POINTS = 1025
 358 };
 359
 360 struct dc_hdr_static_metadata {
 361         /* display chromaticities and white point in units of 0.00001 */
 362         unsigned int chromaticity_green_x;
 363         unsigned int chromaticity_green_y;
 364         unsigned int chromaticity_blue_x;
 365         unsigned int chromaticity_blue_y;
 366         unsigned int chromaticity_red_x;
 367         unsigned int chromaticity_red_y;
 368         unsigned int chromaticity_white_point_x;
 369         unsigned int chromaticity_white_point_y;
 370
 371         uint32_t min_luminance;
 372         uint32_t max_luminance;
 373         uint32_t maximum_content_light_level;
 374         uint32_t maximum_frame_average_light_level;
 375 };
 376
 377 enum dc_transfer_func_type {
 378         TF_TYPE_PREDEFINED,
 379         TF_TYPE_DISTRIBUTED_POINTS,
 380         TF_TYPE_BYPASS,
 381         TF_TYPE_HWPWL
 382 };
 383
 384 struct dc_transfer_func_distributed_points {
 385         struct fixed31_32 red[TRANSFER_FUNC_POINTS];
 386         struct fixed31_32 green[TRANSFER_FUNC_POINTS];
 387         struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
 388
 389         uint16_t end_exponent;
 390         uint16_t x_point_at_y1_red;
 391         uint16_t x_point_at_y1_green;
 392         uint16_t x_point_at_y1_blue;
 393 };
 394
 395 enum dc_transfer_func_predefined {
 396         TRANSFER_FUNCTION_SRGB,
 397         TRANSFER_FUNCTION_BT709,
 398         TRANSFER_FUNCTION_PQ,
 399         TRANSFER_FUNCTION_LINEAR,
 400         TRANSFER_FUNCTION_UNITY,
 401         TRANSFER_FUNCTION_HLG,
 402         TRANSFER_FUNCTION_HLG12,
 403         TRANSFER_FUNCTION_GAMMA22
 404 };
 405
 406 struct dc_transfer_func {
 407         struct kref refcount;
 408         enum dc_transfer_func_type type;
 409         enum dc_transfer_func_predefined tf;
 410         /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
 411         uint32_t sdr_ref_white_level;
 412         struct dc_context *ctx;
 413         union {
 414                 struct pwl_params pwl;
 415                 struct dc_transfer_func_distributed_points tf_pts;
 416         };
 417 };
 418
 419 /*
 420  * This structure is filled in by dc_surface_get_status and contains
 421  * the last requested address and the currently active address so the called
 422  * can determine if there are any outstanding flips
 423  */
 424 struct dc_plane_status {
 425         struct dc_plane_address requested_address;
 426         struct dc_plane_address current_address;
 427         bool is_flip_pending;
 428         bool is_right_eye;
 429 };
 430
 431 union surface_update_flags {
 432
 433         struct {
 434                 /* Medium updates */
 435                 uint32_t dcc_change:1;
 436                 uint32_t color_space_change:1;
 437                 uint32_t horizontal_mirror_change:1;
 438                 uint32_t per_pixel_alpha_change:1;
 439                 uint32_t global_alpha_change:1;
 440                 uint32_t rotation_change:1;
 441                 uint32_t swizzle_change:1;
 442                 uint32_t scaling_change:1;
 443                 uint32_t position_change:1;
 444                 uint32_t in_transfer_func_change:1;
 445                 uint32_t input_csc_change:1;
 446                 uint32_t coeff_reduction_change:1;
 447                 uint32_t output_tf_change:1;
 448                 uint32_t pixel_format_change:1;
 449                 uint32_t plane_size_change:1;
 450
 451                 /* Full updates */
 452                 uint32_t new_plane:1;
 453                 uint32_t bpp_change:1;
 454                 uint32_t gamma_change:1;
 455                 uint32_t bandwidth_change:1;
 456                 uint32_t clock_change:1;
 457                 uint32_t stereo_format_change:1;
 458                 uint32_t full_update:1;
 459         } bits;
 460
 461         uint32_t raw;
 462 };
 463
 464 struct dc_plane_state {
 465         struct dc_plane_address address;
 466         struct dc_plane_flip_time time;
 467         struct scaling_taps scaling_quality;
 468         struct rect src_rect;
 469         struct rect dst_rect;
 470         struct rect clip_rect;
 471
 472         union plane_size plane_size;
 473         union dc_tiling_info tiling_info;
 474
 475         struct dc_plane_dcc_param dcc;
 476
 477         struct dc_gamma *gamma_correction;
 478         struct dc_transfer_func *in_transfer_func;
 479         struct dc_bias_and_scale *bias_and_scale;
 480         struct dc_csc_transform input_csc_color_matrix;
 481         struct fixed31_32 coeff_reduction_factor;
 482         uint32_t sdr_white_level;
 483
 484         // TODO: No longer used, remove
 485         struct dc_hdr_static_metadata hdr_static_ctx;
 486
 487         enum dc_color_space color_space;
 488
 489         enum surface_pixel_format format;
 490         enum dc_rotation_angle rotation;
 491         enum plane_stereo_format stereo_format;
 492
 493         bool is_tiling_rotated;
 494         bool per_pixel_alpha;
 495         bool global_alpha;
 496         int  global_alpha_value;
 497         bool visible;
 498         bool flip_immediate;
 499         bool horizontal_mirror;
 500
 501         union surface_update_flags update_flags;
 502         /* private to DC core */
 503         struct dc_plane_status status;
 504         struct dc_context *ctx;
 505
 506         /* HACK: Workaround for forcing full reprogramming under some conditions */
 507         bool force_full_update;
 508
 509         /* private to dc_surface.c */
 510         enum dc_irq_source irq_source;
 511         struct kref refcount;
 512 };
 513
 514 struct dc_plane_info {
 515         union plane_size plane_size;
 516         union dc_tiling_info tiling_info;
 517         struct dc_plane_dcc_param dcc;
 518         enum surface_pixel_format format;
 519         enum dc_rotation_angle rotation;
 520         enum plane_stereo_format stereo_format;
 521         enum dc_color_space color_space;
 522         unsigned int sdr_white_level;
 523         bool horizontal_mirror;
 524         bool visible;
 525         bool per_pixel_alpha;
 526         bool global_alpha;
 527         int  global_alpha_value;
 528         bool input_csc_enabled;
 529 };
 530
 531 struct dc_scaling_info {
 532         struct rect src_rect;
 533         struct rect dst_rect;
 534         struct rect clip_rect;
 535         struct scaling_taps scaling_quality;
 536 };
 537
 538 struct dc_surface_update {
 539         struct dc_plane_state *surface;
 540
 541         /* isr safe update parameters.  null means no updates */
 542         const struct dc_flip_addrs *flip_addr;
 543         const struct dc_plane_info *plane_info;
 544         const struct dc_scaling_info *scaling_info;
 545
 546         /* following updates require alloc/sleep/spin that is not isr safe,
 547          * null means no updates
 548          */
 549         const struct dc_gamma *gamma;
 550         const struct dc_transfer_func *in_transfer_func;
 551
 552         const struct dc_csc_transform *input_csc_color_matrix;
 553         const struct fixed31_32 *coeff_reduction_factor;
 554 };
 555
 556 /*
 557  * Create a new surface with default parameters;
 558  */
 559 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
 560 const struct dc_plane_status *dc_plane_get_status(
 561                 const struct dc_plane_state *plane_state);
 562
 563 void dc_plane_state_retain(struct dc_plane_state *plane_state);
 564 void dc_plane_state_release(struct dc_plane_state *plane_state);
 565
 566 void dc_gamma_retain(struct dc_gamma *dc_gamma);
 567 void dc_gamma_release(struct dc_gamma **dc_gamma);
 568 struct dc_gamma *dc_create_gamma(void);
 569
 570 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
 571 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
 572 struct dc_transfer_func *dc_create_transfer_func(void);
 573
 574 /*
 575  * This structure holds a surface address.  There could be multiple addresses
 576  * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
 577  * as frame durations and DCC format can also be set.
 578  */
 579 struct dc_flip_addrs {
 580         struct dc_plane_address address;
 581         unsigned int flip_timestamp_in_us;
 582         bool flip_immediate;
 583         /* TODO: add flip duration for FreeSync */
 584 };
 585
 586 bool dc_post_update_surfaces_to_stream(
 587                 struct dc *dc);
 588
 589 #include "dc_stream.h"
 590
 591 /*
 592  * Structure to store surface/stream associations for validation
 593  */
 594 struct dc_validation_set {
 595         struct dc_stream_state *stream;
 596         struct dc_plane_state *plane_states[MAX_SURFACES];
 597         uint8_t plane_count;
 598 };
 599
 600 bool dc_validate_seamless_boot_timing(struct dc *dc,
 601                                 const struct dc_sink *sink,
 602                                 struct dc_crtc_timing *crtc_timing);
 603
 604 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
 605
 606 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
 607
 608 enum dc_status dc_validate_global_state(
 609                 struct dc *dc,
 610                 struct dc_state *new_ctx);
 611
 612
 613 void dc_resource_state_construct(
 614                 const struct dc *dc,
 615                 struct dc_state *dst_ctx);
 616
 617 void dc_resource_state_copy_construct(
 618                 const struct dc_state *src_ctx,
 619                 struct dc_state *dst_ctx);
 620
 621 void dc_resource_state_copy_construct_current(
 622                 const struct dc *dc,
 623                 struct dc_state *dst_ctx);
 624
 625 void dc_resource_state_destruct(struct dc_state *context);
 626
 627 /*
 628  * TODO update to make it about validation sets
 629  * Set up streams and links associated to drive sinks
 630  * The streams parameter is an absolute set of all active streams.
 631  *
 632  * After this call:
 633  *   Phy, Encoder, Timing Generator are programmed and enabled.
 634  *   New streams are enabled with blank stream; no memory read.
 635  */
 636 bool dc_commit_state(struct dc *dc, struct dc_state *context);
 637
 638
 639 struct dc_state *dc_create_state(void);
 640 void dc_retain_state(struct dc_state *context);
 641 void dc_release_state(struct dc_state *context);
 642
 643 /*******************************************************************************
 644  * Link Interfaces
 645  ******************************************************************************/
 646
 647 struct dpcd_caps {
 648         union dpcd_rev dpcd_rev;
 649         union max_lane_count max_ln_count;
 650         union max_down_spread max_down_spread;
 651
 652         /* dongle type (DP converter, CV smart dongle) */
 653         enum display_dongle_type dongle_type;
 654         /* Dongle's downstream count. */
 655         union sink_count sink_count;
 656         /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 657         indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
 658         struct dc_dongle_caps dongle_caps;
 659
 660         uint32_t sink_dev_id;
 661         int8_t sink_dev_id_str[6];
 662         int8_t sink_hw_revision;
 663         int8_t sink_fw_revision[2];
 664
 665         uint32_t branch_dev_id;
 666         int8_t branch_dev_name[6];
 667         int8_t branch_hw_revision;
 668         int8_t branch_fw_revision[2];
 669         uint8_t link_rate_set;
 670
 671         bool allow_invalid_MSA_timing_param;
 672         bool panel_mode_edp;
 673         bool dpcd_display_control_capable;
 674 };
 675
 676 #include "dc_link.h"
 677
 678 /*******************************************************************************
 679  * Sink Interfaces - A sink corresponds to a display output device
 680  ******************************************************************************/
 681
 682 struct dc_container_id {
 683         // 128bit GUID in binary form
 684         unsigned char  guid[16];
 685         // 8 byte port ID -> ELD.PortID
 686         unsigned int   portId[2];
 687         // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
 688         unsigned short manufacturerName;
 689         // 2 byte product code -> ELD.ProductCode
 690         unsigned short productCode;
 691 };
 692
 693
 694
 695 /*
 696  * The sink structure contains EDID and other display device properties
 697  */
 698 struct dc_sink {
 699         enum signal_type sink_signal;
 700         struct dc_edid dc_edid; /* raw edid */
 701         struct dc_edid_caps edid_caps; /* parse display caps */
 702         struct dc_container_id *dc_container_id;
 703         uint32_t dongle_max_pix_clk;
 704         void *priv;
 705         struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
 706         bool converter_disable_audio;
 707
 708         /* private to DC core */
 709         struct dc_link *link;
 710         struct dc_context *ctx;
 711
 712         uint32_t sink_id;
 713
 714         /* private to dc_sink.c */
 715         // refcount must be the last member in dc_sink, since we want the
 716         // sink structure to be logically cloneable up to (but not including)
 717         // refcount
 718         struct kref refcount;
 719 };
 720
 721 void dc_sink_retain(struct dc_sink *sink);
 722 void dc_sink_release(struct dc_sink *sink);
 723
 724 struct dc_sink_init_data {
 725         enum signal_type sink_signal;
 726         struct dc_link *link;
 727         uint32_t dongle_max_pix_clk;
 728         bool converter_disable_audio;
 729 };
 730
 731 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
 732
 733 /* Newer interfaces  */
 734 struct dc_cursor {
 735         struct dc_plane_address address;
 736         struct dc_cursor_attributes attributes;
 737 };
 738
 739
 740 /*******************************************************************************
 741  * Interrupt interfaces
 742  ******************************************************************************/
 743 enum dc_irq_source dc_interrupt_to_irq_source(
 744                 struct dc *dc,
 745                 uint32_t src_id,
 746                 uint32_t ext_id);
 747 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
 748 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
 749 enum dc_irq_source dc_get_hpd_irq_source_at_index(
 750                 struct dc *dc, uint32_t link_index);
 751
 752 /*******************************************************************************
 753  * Power Interfaces
 754  ******************************************************************************/
 755
 756 void dc_set_power_state(
 757                 struct dc *dc,
 758                 enum dc_acpi_cm_power_state power_state);
 759 void dc_resume(struct dc *dc);
 760 unsigned int dc_get_current_backlight_pwm(struct dc *dc);
 761 unsigned int dc_get_target_backlight_pwm(struct dc *dc);
 762
 763 bool dc_is_dmcu_initialized(struct dc *dc);
 764
 765 #endif /* DC_INTERFACE_H_ */