2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dma-resv.h>
28 #include <linux/i2c.h>
29 #include <linux/input.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
35 #include <drm/display/drm_dp_helper.h>
36 #include <drm/display/drm_dp_tunnel.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_atomic_helper.h>
39 #include <drm/drm_atomic_uapi.h>
40 #include <drm/drm_damage_helper.h>
41 #include <drm/drm_edid.h>
42 #include <drm/drm_fourcc.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
46 #include "gem/i915_gem_lmem.h"
47 #include "gem/i915_gem_object.h"
52 #include "i915_config.h"
55 #include "i915_utils.h"
56 #include "i9xx_plane.h"
58 #include "intel_atomic.h"
59 #include "intel_atomic_plane.h"
60 #include "intel_audio.h"
62 #include "intel_cdclk.h"
63 #include "intel_clock_gating.h"
64 #include "intel_color.h"
65 #include "intel_crt.h"
66 #include "intel_crtc.h"
67 #include "intel_crtc_state_dump.h"
68 #include "intel_ddi.h"
70 #include "intel_display_driver.h"
71 #include "intel_display_power.h"
72 #include "intel_display_types.h"
73 #include "intel_dmc.h"
75 #include "intel_dp_link_training.h"
76 #include "intel_dp_mst.h"
77 #include "intel_dp_tunnel.h"
78 #include "intel_dpll.h"
79 #include "intel_dpll_mgr.h"
80 #include "intel_dpt.h"
81 #include "intel_dpt_common.h"
82 #include "intel_drrs.h"
83 #include "intel_dsb.h"
84 #include "intel_dsi.h"
85 #include "intel_dvo.h"
87 #include "intel_fbc.h"
88 #include "intel_fbdev.h"
89 #include "intel_fdi.h"
90 #include "intel_fifo_underrun.h"
91 #include "intel_frontbuffer.h"
92 #include "intel_hdmi.h"
93 #include "intel_hotplug.h"
94 #include "intel_link_bw.h"
95 #include "intel_lvds.h"
96 #include "intel_lvds_regs.h"
97 #include "intel_modeset_setup.h"
98 #include "intel_modeset_verify.h"
99 #include "intel_overlay.h"
100 #include "intel_panel.h"
101 #include "intel_pch_display.h"
102 #include "intel_pch_refclk.h"
103 #include "intel_pcode.h"
104 #include "intel_pipe_crc.h"
105 #include "intel_plane_initial.h"
106 #include "intel_pmdemand.h"
107 #include "intel_pps.h"
108 #include "intel_psr.h"
109 #include "intel_psr_regs.h"
110 #include "intel_sdvo.h"
111 #include "intel_snps_phy.h"
112 #include "intel_tc.h"
113 #include "intel_tv.h"
114 #include "intel_vblank.h"
115 #include "intel_vdsc.h"
116 #include "intel_vdsc_regs.h"
117 #include "intel_vga.h"
118 #include "intel_vrr.h"
119 #include "intel_wm.h"
120 #include "skl_scaler.h"
121 #include "skl_universal_plane.h"
122 #include "skl_watermark.h"
124 #include "vlv_dsi_pll.h"
125 #include "vlv_dsi_regs.h"
126 #include "vlv_sideband.h"
128 static void intel_set_transcoder_timings(const struct intel_crtc_state
*crtc_state
);
129 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
);
130 static void hsw_set_transconf(const struct intel_crtc_state
*crtc_state
);
131 static void bdw_set_pipe_misc(const struct intel_crtc_state
*crtc_state
);
133 /* returns HPLL frequency in kHz */
134 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
)
136 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
138 /* Obtain SKU information */
139 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
140 CCK_FUSE_HPLL_FREQ_MASK
;
142 return vco_freq
[hpll_freq
] * 1000;
145 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
146 const char *name
, u32 reg
, int ref_freq
)
151 val
= vlv_cck_read(dev_priv
, reg
);
152 divider
= val
& CCK_FREQUENCY_VALUES
;
154 drm_WARN(&dev_priv
->drm
, (val
& CCK_FREQUENCY_STATUS
) !=
155 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
156 "%s change in progress\n", name
);
158 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
161 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
162 const char *name
, u32 reg
)
166 vlv_cck_get(dev_priv
);
168 if (dev_priv
->hpll_freq
== 0)
169 dev_priv
->hpll_freq
= vlv_get_hpll_vco(dev_priv
);
171 hpll
= vlv_get_cck_clock(dev_priv
, name
, reg
, dev_priv
->hpll_freq
);
173 vlv_cck_put(dev_priv
);
178 void intel_update_czclk(struct drm_i915_private
*dev_priv
)
180 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
183 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
184 CCK_CZ_CLOCK_CONTROL
);
186 drm_dbg(&dev_priv
->drm
, "CZ clock rate: %d kHz\n",
187 dev_priv
->czclk_freq
);
190 static bool is_hdr_mode(const struct intel_crtc_state
*crtc_state
)
192 return (crtc_state
->active_planes
&
193 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR
))) == 0;
196 /* WA Display #0827: Gen9:all */
198 skl_wa_827(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool enable
)
200 intel_de_rmw(dev_priv
, CLKGATE_DIS_PSL(pipe
),
201 DUPS1_GATING_DIS
| DUPS2_GATING_DIS
,
202 enable
? DUPS1_GATING_DIS
| DUPS2_GATING_DIS
: 0);
205 /* Wa_2006604312:icl,ehl */
207 icl_wa_scalerclkgating(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
210 intel_de_rmw(dev_priv
, CLKGATE_DIS_PSL(pipe
),
212 enable
? DPFR_GATING_DIS
: 0);
215 /* Wa_1604331009:icl,jsl,ehl */
217 icl_wa_cursorclkgating(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
220 intel_de_rmw(dev_priv
, CLKGATE_DIS_PSL(pipe
),
222 enable
? CURSOR_GATING_DIS
: 0);
226 is_trans_port_sync_slave(const struct intel_crtc_state
*crtc_state
)
228 return crtc_state
->master_transcoder
!= INVALID_TRANSCODER
;
232 is_trans_port_sync_master(const struct intel_crtc_state
*crtc_state
)
234 return crtc_state
->sync_mode_slaves_mask
!= 0;
238 is_trans_port_sync_mode(const struct intel_crtc_state
*crtc_state
)
240 return is_trans_port_sync_master(crtc_state
) ||
241 is_trans_port_sync_slave(crtc_state
);
244 static enum pipe
bigjoiner_master_pipe(const struct intel_crtc_state
*crtc_state
)
246 return ffs(crtc_state
->bigjoiner_pipes
) - 1;
249 u8
intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state
*crtc_state
)
251 if (crtc_state
->bigjoiner_pipes
)
252 return crtc_state
->bigjoiner_pipes
& ~BIT(bigjoiner_master_pipe(crtc_state
));
257 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state
*crtc_state
)
259 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
261 return crtc_state
->bigjoiner_pipes
&&
262 crtc
->pipe
!= bigjoiner_master_pipe(crtc_state
);
265 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state
*crtc_state
)
267 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
269 return crtc_state
->bigjoiner_pipes
&&
270 crtc
->pipe
== bigjoiner_master_pipe(crtc_state
);
273 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state
*crtc_state
)
275 return hweight8(crtc_state
->bigjoiner_pipes
);
278 struct intel_crtc
*intel_master_crtc(const struct intel_crtc_state
*crtc_state
)
280 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
282 if (intel_crtc_is_bigjoiner_slave(crtc_state
))
283 return intel_crtc_for_pipe(i915
, bigjoiner_master_pipe(crtc_state
));
285 return to_intel_crtc(crtc_state
->uapi
.crtc
);
289 intel_wait_for_pipe_off(const struct intel_crtc_state
*old_crtc_state
)
291 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
292 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
294 if (DISPLAY_VER(dev_priv
) >= 4) {
295 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
297 /* Wait for the Pipe State to go off */
298 if (intel_de_wait_for_clear(dev_priv
, TRANSCONF(cpu_transcoder
),
299 TRANSCONF_STATE_ENABLE
, 100))
300 drm_WARN(&dev_priv
->drm
, 1, "pipe_off wait timed out\n");
302 intel_wait_for_pipe_scanline_stopped(crtc
);
306 void assert_transcoder(struct drm_i915_private
*dev_priv
,
307 enum transcoder cpu_transcoder
, bool state
)
310 enum intel_display_power_domain power_domain
;
311 intel_wakeref_t wakeref
;
313 /* we keep both pipes enabled on 830 */
314 if (IS_I830(dev_priv
))
317 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
318 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
320 u32 val
= intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
));
321 cur_state
= !!(val
& TRANSCONF_ENABLE
);
323 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
328 I915_STATE_WARN(dev_priv
, cur_state
!= state
,
329 "transcoder %s assertion failure (expected %s, current %s)\n",
330 transcoder_name(cpu_transcoder
), str_on_off(state
),
331 str_on_off(cur_state
));
334 static void assert_plane(struct intel_plane
*plane
, bool state
)
336 struct drm_i915_private
*i915
= to_i915(plane
->base
.dev
);
340 cur_state
= plane
->get_hw_state(plane
, &pipe
);
342 I915_STATE_WARN(i915
, cur_state
!= state
,
343 "%s assertion failure (expected %s, current %s)\n",
344 plane
->base
.name
, str_on_off(state
),
345 str_on_off(cur_state
));
348 #define assert_plane_enabled(p) assert_plane(p, true)
349 #define assert_plane_disabled(p) assert_plane(p, false)
351 static void assert_planes_disabled(struct intel_crtc
*crtc
)
353 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
354 struct intel_plane
*plane
;
356 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
)
357 assert_plane_disabled(plane
);
360 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
361 struct intel_digital_port
*dig_port
,
362 unsigned int expected_mask
)
367 switch (dig_port
->base
.port
) {
369 MISSING_CASE(dig_port
->base
.port
);
372 port_mask
= DPLL_PORTB_READY_MASK
;
376 port_mask
= DPLL_PORTC_READY_MASK
;
381 port_mask
= DPLL_PORTD_READY_MASK
;
382 dpll_reg
= DPIO_PHY_STATUS
;
386 if (intel_de_wait_for_register(dev_priv
, dpll_reg
,
387 port_mask
, expected_mask
, 1000))
388 drm_WARN(&dev_priv
->drm
, 1,
389 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
390 dig_port
->base
.base
.base
.id
, dig_port
->base
.base
.name
,
391 intel_de_read(dev_priv
, dpll_reg
) & port_mask
,
395 void intel_enable_transcoder(const struct intel_crtc_state
*new_crtc_state
)
397 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
398 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
399 enum transcoder cpu_transcoder
= new_crtc_state
->cpu_transcoder
;
400 enum pipe pipe
= crtc
->pipe
;
403 drm_dbg_kms(&dev_priv
->drm
, "enabling pipe %c\n", pipe_name(pipe
));
405 assert_planes_disabled(crtc
);
408 * A pipe without a PLL won't actually be able to drive bits from
409 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
412 if (HAS_GMCH(dev_priv
)) {
413 if (intel_crtc_has_type(new_crtc_state
, INTEL_OUTPUT_DSI
))
414 assert_dsi_pll_enabled(dev_priv
);
416 assert_pll_enabled(dev_priv
, pipe
);
418 if (new_crtc_state
->has_pch_encoder
) {
419 /* if driving the PCH, we need FDI enabled */
420 assert_fdi_rx_pll_enabled(dev_priv
,
421 intel_crtc_pch_transcoder(crtc
));
422 assert_fdi_tx_pll_enabled(dev_priv
,
423 (enum pipe
) cpu_transcoder
);
425 /* FIXME: assert CPU port conditions for SNB+ */
428 /* Wa_22012358565:adl-p */
429 if (DISPLAY_VER(dev_priv
) == 13)
430 intel_de_rmw(dev_priv
, PIPE_ARB_CTL(pipe
),
431 0, PIPE_ARB_USE_PROG_SLOTS
);
433 val
= intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
));
434 if (val
& TRANSCONF_ENABLE
) {
435 /* we keep both pipes enabled on 830 */
436 drm_WARN_ON(&dev_priv
->drm
, !IS_I830(dev_priv
));
440 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
),
441 val
| TRANSCONF_ENABLE
);
442 intel_de_posting_read(dev_priv
, TRANSCONF(cpu_transcoder
));
445 * Until the pipe starts PIPEDSL reads will return a stale value,
446 * which causes an apparent vblank timestamp jump when PIPEDSL
447 * resets to its proper value. That also messes up the frame count
448 * when it's derived from the timestamps. So let's wait for the
449 * pipe to start properly before we call drm_crtc_vblank_on()
451 if (intel_crtc_max_vblank_count(new_crtc_state
) == 0)
452 intel_wait_for_pipe_scanline_moving(crtc
);
455 void intel_disable_transcoder(const struct intel_crtc_state
*old_crtc_state
)
457 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
458 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
459 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
460 enum pipe pipe
= crtc
->pipe
;
463 drm_dbg_kms(&dev_priv
->drm
, "disabling pipe %c\n", pipe_name(pipe
));
466 * Make sure planes won't keep trying to pump pixels to us,
467 * or we might hang the display.
469 assert_planes_disabled(crtc
);
471 val
= intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
));
472 if ((val
& TRANSCONF_ENABLE
) == 0)
476 * Double wide has implications for planes
477 * so best keep it disabled when not needed.
479 if (old_crtc_state
->double_wide
)
480 val
&= ~TRANSCONF_DOUBLE_WIDE
;
482 /* Don't disable pipe or pipe PLLs if needed */
483 if (!IS_I830(dev_priv
))
484 val
&= ~TRANSCONF_ENABLE
;
486 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
), val
);
488 if (DISPLAY_VER(dev_priv
) >= 12)
489 intel_de_rmw(dev_priv
, hsw_chicken_trans_reg(dev_priv
, cpu_transcoder
),
490 FECSTALL_DIS_DPTSTREAM_DPTTG
, 0);
492 if ((val
& TRANSCONF_ENABLE
) == 0)
493 intel_wait_for_pipe_off(old_crtc_state
);
496 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
498 unsigned int size
= 0;
501 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
502 size
+= rot_info
->plane
[i
].dst_stride
* rot_info
->plane
[i
].width
;
507 unsigned int intel_remapped_info_size(const struct intel_remapped_info
*rem_info
)
509 unsigned int size
= 0;
512 for (i
= 0 ; i
< ARRAY_SIZE(rem_info
->plane
); i
++) {
513 unsigned int plane_size
;
515 if (rem_info
->plane
[i
].linear
)
516 plane_size
= rem_info
->plane
[i
].size
;
518 plane_size
= rem_info
->plane
[i
].dst_stride
* rem_info
->plane
[i
].height
;
523 if (rem_info
->plane_alignment
)
524 size
= ALIGN(size
, rem_info
->plane_alignment
);
532 bool intel_plane_uses_fence(const struct intel_plane_state
*plane_state
)
534 struct intel_plane
*plane
= to_intel_plane(plane_state
->uapi
.plane
);
535 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
537 return DISPLAY_VER(dev_priv
) < 4 ||
539 plane_state
->view
.gtt
.type
== I915_GTT_VIEW_NORMAL
);
543 * Convert the x/y offsets into a linear offset.
544 * Only valid with 0/180 degree rotation, which is fine since linear
545 * offset is only used with linear buffers on pre-hsw and tiled buffers
546 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
548 u32
intel_fb_xy_to_linear(int x
, int y
,
549 const struct intel_plane_state
*state
,
552 const struct drm_framebuffer
*fb
= state
->hw
.fb
;
553 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
554 unsigned int pitch
= state
->view
.color_plane
[color_plane
].mapping_stride
;
556 return y
* pitch
+ x
* cpp
;
560 * Add the x/y offsets derived from fb->offsets[] to the user
561 * specified plane src x/y offsets. The resulting x/y offsets
562 * specify the start of scanout from the beginning of the gtt mapping.
564 void intel_add_fb_offsets(int *x
, int *y
,
565 const struct intel_plane_state
*state
,
569 *x
+= state
->view
.color_plane
[color_plane
].x
;
570 *y
+= state
->view
.color_plane
[color_plane
].y
;
573 u32
intel_plane_fb_max_stride(struct drm_i915_private
*dev_priv
,
574 u32 pixel_format
, u64 modifier
)
576 struct intel_crtc
*crtc
;
577 struct intel_plane
*plane
;
579 if (!HAS_DISPLAY(dev_priv
))
583 * We assume the primary plane for pipe A has
584 * the highest stride limits of them all,
585 * if in case pipe A is disabled, use the first pipe from pipe_mask.
587 crtc
= intel_first_crtc(dev_priv
);
591 plane
= to_intel_plane(crtc
->base
.primary
);
593 return plane
->max_stride(plane
, pixel_format
, modifier
,
597 void intel_set_plane_visible(struct intel_crtc_state
*crtc_state
,
598 struct intel_plane_state
*plane_state
,
601 struct intel_plane
*plane
= to_intel_plane(plane_state
->uapi
.plane
);
603 plane_state
->uapi
.visible
= visible
;
606 crtc_state
->uapi
.plane_mask
|= drm_plane_mask(&plane
->base
);
608 crtc_state
->uapi
.plane_mask
&= ~drm_plane_mask(&plane
->base
);
611 void intel_plane_fixup_bitmasks(struct intel_crtc_state
*crtc_state
)
613 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
614 struct drm_plane
*plane
;
617 * Active_planes aliases if multiple "primary" or cursor planes
618 * have been used on the same (or wrong) pipe. plane_mask uses
619 * unique ids, hence we can use that to reconstruct active_planes.
621 crtc_state
->enabled_planes
= 0;
622 crtc_state
->active_planes
= 0;
624 drm_for_each_plane_mask(plane
, &dev_priv
->drm
,
625 crtc_state
->uapi
.plane_mask
) {
626 crtc_state
->enabled_planes
|= BIT(to_intel_plane(plane
)->id
);
627 crtc_state
->active_planes
|= BIT(to_intel_plane(plane
)->id
);
631 void intel_plane_disable_noatomic(struct intel_crtc
*crtc
,
632 struct intel_plane
*plane
)
634 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
635 struct intel_crtc_state
*crtc_state
=
636 to_intel_crtc_state(crtc
->base
.state
);
637 struct intel_plane_state
*plane_state
=
638 to_intel_plane_state(plane
->base
.state
);
640 drm_dbg_kms(&dev_priv
->drm
,
641 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
642 plane
->base
.base
.id
, plane
->base
.name
,
643 crtc
->base
.base
.id
, crtc
->base
.name
);
645 intel_set_plane_visible(crtc_state
, plane_state
, false);
646 intel_plane_fixup_bitmasks(crtc_state
);
647 crtc_state
->data_rate
[plane
->id
] = 0;
648 crtc_state
->data_rate_y
[plane
->id
] = 0;
649 crtc_state
->rel_data_rate
[plane
->id
] = 0;
650 crtc_state
->rel_data_rate_y
[plane
->id
] = 0;
651 crtc_state
->min_cdclk
[plane
->id
] = 0;
653 if ((crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)) == 0 &&
654 hsw_ips_disable(crtc_state
)) {
655 crtc_state
->ips_enabled
= false;
656 intel_crtc_wait_for_next_vblank(crtc
);
660 * Vblank time updates from the shadow to live plane control register
661 * are blocked if the memory self-refresh mode is active at that
662 * moment. So to make sure the plane gets truly disabled, disable
663 * first the self-refresh mode. The self-refresh enable bit in turn
664 * will be checked/applied by the HW only at the next frame start
665 * event which is after the vblank start event, so we need to have a
666 * wait-for-vblank between disabling the plane and the pipe.
668 if (HAS_GMCH(dev_priv
) &&
669 intel_set_memory_cxsr(dev_priv
, false))
670 intel_crtc_wait_for_next_vblank(crtc
);
673 * Gen2 reports pipe underruns whenever all planes are disabled.
674 * So disable underrun reporting before all the planes get disabled.
676 if (DISPLAY_VER(dev_priv
) == 2 && !crtc_state
->active_planes
)
677 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
679 intel_plane_disable_arm(plane
, crtc_state
);
680 intel_crtc_wait_for_next_vblank(crtc
);
684 intel_plane_fence_y_offset(const struct intel_plane_state
*plane_state
)
688 intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
689 plane_state
->view
.color_plane
[0].offset
, 0);
694 static void icl_set_pipe_chicken(const struct intel_crtc_state
*crtc_state
)
696 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
697 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
698 enum pipe pipe
= crtc
->pipe
;
701 tmp
= intel_de_read(dev_priv
, PIPE_CHICKEN(pipe
));
704 * Display WA #1153: icl
705 * enable hardware to bypass the alpha math
706 * and rounding for per-pixel values 00 and 0xff
708 tmp
|= PER_PIXEL_ALPHA_BYPASS_EN
;
710 * Display WA # 1605353570: icl
711 * Set the pixel rounding bit to 1 for allowing
712 * passthrough of Frame buffer pixels unmodified
715 tmp
|= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU
;
718 * Underrun recovery must always be disabled on display 13+.
719 * DG2 chicken bit meaning is inverted compared to other platforms.
721 if (IS_DG2(dev_priv
))
722 tmp
&= ~UNDERRUN_RECOVERY_ENABLE_DG2
;
723 else if (DISPLAY_VER(dev_priv
) >= 13)
724 tmp
|= UNDERRUN_RECOVERY_DISABLE_ADLP
;
726 /* Wa_14010547955:dg2 */
727 if (IS_DG2(dev_priv
))
728 tmp
|= DG2_RENDER_CCSTAG_4_3_EN
;
730 intel_de_write(dev_priv
, PIPE_CHICKEN(pipe
), tmp
);
733 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
735 struct drm_crtc
*crtc
;
738 drm_for_each_crtc(crtc
, &dev_priv
->drm
) {
739 struct drm_crtc_commit
*commit
;
740 spin_lock(&crtc
->commit_lock
);
741 commit
= list_first_entry_or_null(&crtc
->commit_list
,
742 struct drm_crtc_commit
, commit_entry
);
743 cleanup_done
= commit
?
744 try_wait_for_completion(&commit
->cleanup_done
) : true;
745 spin_unlock(&crtc
->commit_lock
);
750 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc
));
759 * Finds the encoder associated with the given CRTC. This can only be
760 * used when we know that the CRTC isn't feeding multiple encoders!
762 struct intel_encoder
*
763 intel_get_crtc_new_encoder(const struct intel_atomic_state
*state
,
764 const struct intel_crtc_state
*crtc_state
)
766 const struct drm_connector_state
*connector_state
;
767 const struct drm_connector
*connector
;
768 struct intel_encoder
*encoder
= NULL
;
769 struct intel_crtc
*master_crtc
;
770 int num_encoders
= 0;
773 master_crtc
= intel_master_crtc(crtc_state
);
775 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
776 if (connector_state
->crtc
!= &master_crtc
->base
)
779 encoder
= to_intel_encoder(connector_state
->best_encoder
);
783 drm_WARN(state
->base
.dev
, num_encoders
!= 1,
784 "%d encoders for pipe %c\n",
785 num_encoders
, pipe_name(master_crtc
->pipe
));
790 static void ilk_pfit_enable(const struct intel_crtc_state
*crtc_state
)
792 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
793 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
794 const struct drm_rect
*dst
= &crtc_state
->pch_pfit
.dst
;
795 enum pipe pipe
= crtc
->pipe
;
796 int width
= drm_rect_width(dst
);
797 int height
= drm_rect_height(dst
);
801 if (!crtc_state
->pch_pfit
.enabled
)
804 /* Force use of hard-coded filter coefficients
805 * as some pre-programmed values are broken,
808 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
809 intel_de_write_fw(dev_priv
, PF_CTL(pipe
), PF_ENABLE
|
810 PF_FILTER_MED_3x3
| PF_PIPE_SEL_IVB(pipe
));
812 intel_de_write_fw(dev_priv
, PF_CTL(pipe
), PF_ENABLE
|
814 intel_de_write_fw(dev_priv
, PF_WIN_POS(pipe
),
815 PF_WIN_XPOS(x
) | PF_WIN_YPOS(y
));
816 intel_de_write_fw(dev_priv
, PF_WIN_SZ(pipe
),
817 PF_WIN_XSIZE(width
) | PF_WIN_YSIZE(height
));
820 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*crtc
)
823 (void) intel_overlay_switch_off(crtc
->overlay
);
825 /* Let userspace switch the overlay on again. In most cases userspace
826 * has to recompute where to put it anyway.
830 static bool needs_nv12_wa(const struct intel_crtc_state
*crtc_state
)
832 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
834 if (!crtc_state
->nv12_planes
)
837 /* WA Display #0827: Gen9:all */
838 if (DISPLAY_VER(dev_priv
) == 9)
844 static bool needs_scalerclk_wa(const struct intel_crtc_state
*crtc_state
)
846 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
848 /* Wa_2006604312:icl,ehl */
849 if (crtc_state
->scaler_state
.scaler_users
> 0 && DISPLAY_VER(dev_priv
) == 11)
855 static bool needs_cursorclk_wa(const struct intel_crtc_state
*crtc_state
)
857 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
859 /* Wa_1604331009:icl,jsl,ehl */
860 if (is_hdr_mode(crtc_state
) &&
861 crtc_state
->active_planes
& BIT(PLANE_CURSOR
) &&
862 DISPLAY_VER(dev_priv
) == 11)
868 static void intel_async_flip_vtd_wa(struct drm_i915_private
*i915
,
869 enum pipe pipe
, bool enable
)
871 if (DISPLAY_VER(i915
) == 9) {
873 * "Plane N strech max must be programmed to 11b (x1)
874 * when Async flips are enabled on that plane."
876 intel_de_rmw(i915
, CHICKEN_PIPESL_1(pipe
),
877 SKL_PLANE1_STRETCH_MAX_MASK
,
878 enable
? SKL_PLANE1_STRETCH_MAX_X1
: SKL_PLANE1_STRETCH_MAX_X8
);
880 /* Also needed on HSW/BDW albeit undocumented */
881 intel_de_rmw(i915
, CHICKEN_PIPESL_1(pipe
),
882 HSW_PRI_STRETCH_MAX_MASK
,
883 enable
? HSW_PRI_STRETCH_MAX_X1
: HSW_PRI_STRETCH_MAX_X8
);
887 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state
*crtc_state
)
889 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
891 return crtc_state
->uapi
.async_flip
&& i915_vtd_active(i915
) &&
892 (DISPLAY_VER(i915
) == 9 || IS_BROADWELL(i915
) || IS_HASWELL(i915
));
895 static void intel_encoders_audio_enable(struct intel_atomic_state
*state
,
896 struct intel_crtc
*crtc
)
898 const struct intel_crtc_state
*crtc_state
=
899 intel_atomic_get_new_crtc_state(state
, crtc
);
900 const struct drm_connector_state
*conn_state
;
901 struct drm_connector
*conn
;
904 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
905 struct intel_encoder
*encoder
=
906 to_intel_encoder(conn_state
->best_encoder
);
908 if (conn_state
->crtc
!= &crtc
->base
)
911 if (encoder
->audio_enable
)
912 encoder
->audio_enable(encoder
, crtc_state
, conn_state
);
916 static void intel_encoders_audio_disable(struct intel_atomic_state
*state
,
917 struct intel_crtc
*crtc
)
919 const struct intel_crtc_state
*old_crtc_state
=
920 intel_atomic_get_old_crtc_state(state
, crtc
);
921 const struct drm_connector_state
*old_conn_state
;
922 struct drm_connector
*conn
;
925 for_each_old_connector_in_state(&state
->base
, conn
, old_conn_state
, i
) {
926 struct intel_encoder
*encoder
=
927 to_intel_encoder(old_conn_state
->best_encoder
);
929 if (old_conn_state
->crtc
!= &crtc
->base
)
932 if (encoder
->audio_disable
)
933 encoder
->audio_disable(encoder
, old_crtc_state
, old_conn_state
);
937 #define is_enabling(feature, old_crtc_state, new_crtc_state) \
938 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
939 (new_crtc_state)->feature)
940 #define is_disabling(feature, old_crtc_state, new_crtc_state) \
941 ((old_crtc_state)->feature && \
942 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
944 static bool planes_enabling(const struct intel_crtc_state
*old_crtc_state
,
945 const struct intel_crtc_state
*new_crtc_state
)
947 if (!new_crtc_state
->hw
.active
)
950 return is_enabling(active_planes
, old_crtc_state
, new_crtc_state
);
953 static bool planes_disabling(const struct intel_crtc_state
*old_crtc_state
,
954 const struct intel_crtc_state
*new_crtc_state
)
956 if (!old_crtc_state
->hw
.active
)
959 return is_disabling(active_planes
, old_crtc_state
, new_crtc_state
);
962 static bool vrr_params_changed(const struct intel_crtc_state
*old_crtc_state
,
963 const struct intel_crtc_state
*new_crtc_state
)
965 return old_crtc_state
->vrr
.flipline
!= new_crtc_state
->vrr
.flipline
||
966 old_crtc_state
->vrr
.vmin
!= new_crtc_state
->vrr
.vmin
||
967 old_crtc_state
->vrr
.vmax
!= new_crtc_state
->vrr
.vmax
||
968 old_crtc_state
->vrr
.guardband
!= new_crtc_state
->vrr
.guardband
||
969 old_crtc_state
->vrr
.pipeline_full
!= new_crtc_state
->vrr
.pipeline_full
;
972 static bool vrr_enabling(const struct intel_crtc_state
*old_crtc_state
,
973 const struct intel_crtc_state
*new_crtc_state
)
975 if (!new_crtc_state
->hw
.active
)
978 return is_enabling(vrr
.enable
, old_crtc_state
, new_crtc_state
) ||
979 (new_crtc_state
->vrr
.enable
&&
980 (new_crtc_state
->update_m_n
|| new_crtc_state
->update_lrr
||
981 vrr_params_changed(old_crtc_state
, new_crtc_state
)));
984 static bool vrr_disabling(const struct intel_crtc_state
*old_crtc_state
,
985 const struct intel_crtc_state
*new_crtc_state
)
987 if (!old_crtc_state
->hw
.active
)
990 return is_disabling(vrr
.enable
, old_crtc_state
, new_crtc_state
) ||
991 (old_crtc_state
->vrr
.enable
&&
992 (new_crtc_state
->update_m_n
|| new_crtc_state
->update_lrr
||
993 vrr_params_changed(old_crtc_state
, new_crtc_state
)));
996 static bool audio_enabling(const struct intel_crtc_state
*old_crtc_state
,
997 const struct intel_crtc_state
*new_crtc_state
)
999 if (!new_crtc_state
->hw
.active
)
1002 return is_enabling(has_audio
, old_crtc_state
, new_crtc_state
) ||
1003 (new_crtc_state
->has_audio
&&
1004 memcmp(old_crtc_state
->eld
, new_crtc_state
->eld
, MAX_ELD_BYTES
) != 0);
1007 static bool audio_disabling(const struct intel_crtc_state
*old_crtc_state
,
1008 const struct intel_crtc_state
*new_crtc_state
)
1010 if (!old_crtc_state
->hw
.active
)
1013 return is_disabling(has_audio
, old_crtc_state
, new_crtc_state
) ||
1014 (old_crtc_state
->has_audio
&&
1015 memcmp(old_crtc_state
->eld
, new_crtc_state
->eld
, MAX_ELD_BYTES
) != 0);
1021 static void intel_post_plane_update(struct intel_atomic_state
*state
,
1022 struct intel_crtc
*crtc
)
1024 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
1025 const struct intel_crtc_state
*old_crtc_state
=
1026 intel_atomic_get_old_crtc_state(state
, crtc
);
1027 const struct intel_crtc_state
*new_crtc_state
=
1028 intel_atomic_get_new_crtc_state(state
, crtc
);
1029 enum pipe pipe
= crtc
->pipe
;
1031 intel_psr_post_plane_update(state
, crtc
);
1033 intel_frontbuffer_flip(dev_priv
, new_crtc_state
->fb_bits
);
1035 if (new_crtc_state
->update_wm_post
&& new_crtc_state
->hw
.active
)
1036 intel_update_watermarks(dev_priv
);
1038 intel_fbc_post_update(state
, crtc
);
1040 if (needs_async_flip_vtd_wa(old_crtc_state
) &&
1041 !needs_async_flip_vtd_wa(new_crtc_state
))
1042 intel_async_flip_vtd_wa(dev_priv
, pipe
, false);
1044 if (needs_nv12_wa(old_crtc_state
) &&
1045 !needs_nv12_wa(new_crtc_state
))
1046 skl_wa_827(dev_priv
, pipe
, false);
1048 if (needs_scalerclk_wa(old_crtc_state
) &&
1049 !needs_scalerclk_wa(new_crtc_state
))
1050 icl_wa_scalerclkgating(dev_priv
, pipe
, false);
1052 if (needs_cursorclk_wa(old_crtc_state
) &&
1053 !needs_cursorclk_wa(new_crtc_state
))
1054 icl_wa_cursorclkgating(dev_priv
, pipe
, false);
1056 if (intel_crtc_needs_color_update(new_crtc_state
))
1057 intel_color_post_update(new_crtc_state
);
1059 if (audio_enabling(old_crtc_state
, new_crtc_state
))
1060 intel_encoders_audio_enable(state
, crtc
);
1063 static void intel_crtc_enable_flip_done(struct intel_atomic_state
*state
,
1064 struct intel_crtc
*crtc
)
1066 const struct intel_crtc_state
*crtc_state
=
1067 intel_atomic_get_new_crtc_state(state
, crtc
);
1068 u8 update_planes
= crtc_state
->update_planes
;
1069 const struct intel_plane_state __maybe_unused
*plane_state
;
1070 struct intel_plane
*plane
;
1073 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
1074 if (plane
->pipe
== crtc
->pipe
&&
1075 update_planes
& BIT(plane
->id
))
1076 plane
->enable_flip_done(plane
);
1080 static void intel_crtc_disable_flip_done(struct intel_atomic_state
*state
,
1081 struct intel_crtc
*crtc
)
1083 const struct intel_crtc_state
*crtc_state
=
1084 intel_atomic_get_new_crtc_state(state
, crtc
);
1085 u8 update_planes
= crtc_state
->update_planes
;
1086 const struct intel_plane_state __maybe_unused
*plane_state
;
1087 struct intel_plane
*plane
;
1090 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
1091 if (plane
->pipe
== crtc
->pipe
&&
1092 update_planes
& BIT(plane
->id
))
1093 plane
->disable_flip_done(plane
);
1097 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state
*state
,
1098 struct intel_crtc
*crtc
)
1100 const struct intel_crtc_state
*old_crtc_state
=
1101 intel_atomic_get_old_crtc_state(state
, crtc
);
1102 const struct intel_crtc_state
*new_crtc_state
=
1103 intel_atomic_get_new_crtc_state(state
, crtc
);
1104 u8 disable_async_flip_planes
= old_crtc_state
->async_flip_planes
&
1105 ~new_crtc_state
->async_flip_planes
;
1106 const struct intel_plane_state
*old_plane_state
;
1107 struct intel_plane
*plane
;
1108 bool need_vbl_wait
= false;
1111 for_each_old_intel_plane_in_state(state
, plane
, old_plane_state
, i
) {
1112 if (plane
->need_async_flip_disable_wa
&&
1113 plane
->pipe
== crtc
->pipe
&&
1114 disable_async_flip_planes
& BIT(plane
->id
)) {
1116 * Apart from the async flip bit we want to
1117 * preserve the old state for the plane.
1119 plane
->async_flip(plane
, old_crtc_state
,
1120 old_plane_state
, false);
1121 need_vbl_wait
= true;
1126 intel_crtc_wait_for_next_vblank(crtc
);
1129 static void intel_pre_plane_update(struct intel_atomic_state
*state
,
1130 struct intel_crtc
*crtc
)
1132 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
1133 const struct intel_crtc_state
*old_crtc_state
=
1134 intel_atomic_get_old_crtc_state(state
, crtc
);
1135 const struct intel_crtc_state
*new_crtc_state
=
1136 intel_atomic_get_new_crtc_state(state
, crtc
);
1137 enum pipe pipe
= crtc
->pipe
;
1139 if (vrr_disabling(old_crtc_state
, new_crtc_state
)) {
1140 intel_vrr_disable(old_crtc_state
);
1141 intel_crtc_update_active_timings(old_crtc_state
, false);
1144 if (audio_disabling(old_crtc_state
, new_crtc_state
))
1145 intel_encoders_audio_disable(state
, crtc
);
1147 intel_drrs_deactivate(old_crtc_state
);
1149 intel_psr_pre_plane_update(state
, crtc
);
1151 if (hsw_ips_pre_update(state
, crtc
))
1152 intel_crtc_wait_for_next_vblank(crtc
);
1154 if (intel_fbc_pre_update(state
, crtc
))
1155 intel_crtc_wait_for_next_vblank(crtc
);
1157 if (!needs_async_flip_vtd_wa(old_crtc_state
) &&
1158 needs_async_flip_vtd_wa(new_crtc_state
))
1159 intel_async_flip_vtd_wa(dev_priv
, pipe
, true);
1161 /* Display WA 827 */
1162 if (!needs_nv12_wa(old_crtc_state
) &&
1163 needs_nv12_wa(new_crtc_state
))
1164 skl_wa_827(dev_priv
, pipe
, true);
1166 /* Wa_2006604312:icl,ehl */
1167 if (!needs_scalerclk_wa(old_crtc_state
) &&
1168 needs_scalerclk_wa(new_crtc_state
))
1169 icl_wa_scalerclkgating(dev_priv
, pipe
, true);
1171 /* Wa_1604331009:icl,jsl,ehl */
1172 if (!needs_cursorclk_wa(old_crtc_state
) &&
1173 needs_cursorclk_wa(new_crtc_state
))
1174 icl_wa_cursorclkgating(dev_priv
, pipe
, true);
1177 * Vblank time updates from the shadow to live plane control register
1178 * are blocked if the memory self-refresh mode is active at that
1179 * moment. So to make sure the plane gets truly disabled, disable
1180 * first the self-refresh mode. The self-refresh enable bit in turn
1181 * will be checked/applied by the HW only at the next frame start
1182 * event which is after the vblank start event, so we need to have a
1183 * wait-for-vblank between disabling the plane and the pipe.
1185 if (HAS_GMCH(dev_priv
) && old_crtc_state
->hw
.active
&&
1186 new_crtc_state
->disable_cxsr
&& intel_set_memory_cxsr(dev_priv
, false))
1187 intel_crtc_wait_for_next_vblank(crtc
);
1190 * IVB workaround: must disable low power watermarks for at least
1191 * one frame before enabling scaling. LP watermarks can be re-enabled
1192 * when scaling is disabled.
1194 * WaCxSRDisabledForSpriteScaling:ivb
1196 if (old_crtc_state
->hw
.active
&&
1197 new_crtc_state
->disable_lp_wm
&& ilk_disable_lp_wm(dev_priv
))
1198 intel_crtc_wait_for_next_vblank(crtc
);
1201 * If we're doing a modeset we don't need to do any
1202 * pre-vblank watermark programming here.
1204 if (!intel_crtc_needs_modeset(new_crtc_state
)) {
1206 * For platforms that support atomic watermarks, program the
1207 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
1208 * will be the intermediate values that are safe for both pre- and
1209 * post- vblank; when vblank happens, the 'active' values will be set
1210 * to the final 'target' values and we'll do this again to get the
1211 * optimal watermarks. For gen9+ platforms, the values we program here
1212 * will be the final target values which will get automatically latched
1213 * at vblank time; no further programming will be necessary.
1215 * If a platform hasn't been transitioned to atomic watermarks yet,
1216 * we'll continue to update watermarks the old way, if flags tell
1219 if (!intel_initial_watermarks(state
, crtc
))
1220 if (new_crtc_state
->update_wm_pre
)
1221 intel_update_watermarks(dev_priv
);
1225 * Gen2 reports pipe underruns whenever all planes are disabled.
1226 * So disable underrun reporting before all the planes get disabled.
1228 * We do this after .initial_watermarks() so that we have a
1229 * chance of catching underruns with the intermediate watermarks
1230 * vs. the old plane configuration.
1232 if (DISPLAY_VER(dev_priv
) == 2 && planes_disabling(old_crtc_state
, new_crtc_state
))
1233 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
1236 * WA for platforms where async address update enable bit
1237 * is double buffered and only latched at start of vblank.
1239 if (old_crtc_state
->async_flip_planes
& ~new_crtc_state
->async_flip_planes
)
1240 intel_crtc_async_flip_disable_wa(state
, crtc
);
1243 static void intel_crtc_disable_planes(struct intel_atomic_state
*state
,
1244 struct intel_crtc
*crtc
)
1246 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1247 const struct intel_crtc_state
*new_crtc_state
=
1248 intel_atomic_get_new_crtc_state(state
, crtc
);
1249 unsigned int update_mask
= new_crtc_state
->update_planes
;
1250 const struct intel_plane_state
*old_plane_state
;
1251 struct intel_plane
*plane
;
1252 unsigned fb_bits
= 0;
1255 intel_crtc_dpms_overlay_disable(crtc
);
1257 for_each_old_intel_plane_in_state(state
, plane
, old_plane_state
, i
) {
1258 if (crtc
->pipe
!= plane
->pipe
||
1259 !(update_mask
& BIT(plane
->id
)))
1262 intel_plane_disable_arm(plane
, new_crtc_state
);
1264 if (old_plane_state
->uapi
.visible
)
1265 fb_bits
|= plane
->frontbuffer_bit
;
1268 intel_frontbuffer_flip(dev_priv
, fb_bits
);
1271 static void intel_encoders_update_prepare(struct intel_atomic_state
*state
)
1273 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
1274 struct intel_crtc_state
*new_crtc_state
, *old_crtc_state
;
1275 struct intel_crtc
*crtc
;
1279 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1280 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1282 if (i915
->display
.dpll
.mgr
) {
1283 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
1284 if (intel_crtc_needs_modeset(new_crtc_state
))
1287 new_crtc_state
->shared_dpll
= old_crtc_state
->shared_dpll
;
1288 new_crtc_state
->dpll_hw_state
= old_crtc_state
->dpll_hw_state
;
1293 static void intel_encoders_pre_pll_enable(struct intel_atomic_state
*state
,
1294 struct intel_crtc
*crtc
)
1296 const struct intel_crtc_state
*crtc_state
=
1297 intel_atomic_get_new_crtc_state(state
, crtc
);
1298 const struct drm_connector_state
*conn_state
;
1299 struct drm_connector
*conn
;
1302 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
1303 struct intel_encoder
*encoder
=
1304 to_intel_encoder(conn_state
->best_encoder
);
1306 if (conn_state
->crtc
!= &crtc
->base
)
1309 if (encoder
->pre_pll_enable
)
1310 encoder
->pre_pll_enable(state
, encoder
,
1311 crtc_state
, conn_state
);
1315 static void intel_encoders_pre_enable(struct intel_atomic_state
*state
,
1316 struct intel_crtc
*crtc
)
1318 const struct intel_crtc_state
*crtc_state
=
1319 intel_atomic_get_new_crtc_state(state
, crtc
);
1320 const struct drm_connector_state
*conn_state
;
1321 struct drm_connector
*conn
;
1324 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
1325 struct intel_encoder
*encoder
=
1326 to_intel_encoder(conn_state
->best_encoder
);
1328 if (conn_state
->crtc
!= &crtc
->base
)
1331 if (encoder
->pre_enable
)
1332 encoder
->pre_enable(state
, encoder
,
1333 crtc_state
, conn_state
);
1337 static void intel_encoders_enable(struct intel_atomic_state
*state
,
1338 struct intel_crtc
*crtc
)
1340 const struct intel_crtc_state
*crtc_state
=
1341 intel_atomic_get_new_crtc_state(state
, crtc
);
1342 const struct drm_connector_state
*conn_state
;
1343 struct drm_connector
*conn
;
1346 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
1347 struct intel_encoder
*encoder
=
1348 to_intel_encoder(conn_state
->best_encoder
);
1350 if (conn_state
->crtc
!= &crtc
->base
)
1353 if (encoder
->enable
)
1354 encoder
->enable(state
, encoder
,
1355 crtc_state
, conn_state
);
1356 intel_opregion_notify_encoder(encoder
, true);
1360 static void intel_encoders_disable(struct intel_atomic_state
*state
,
1361 struct intel_crtc
*crtc
)
1363 const struct intel_crtc_state
*old_crtc_state
=
1364 intel_atomic_get_old_crtc_state(state
, crtc
);
1365 const struct drm_connector_state
*old_conn_state
;
1366 struct drm_connector
*conn
;
1369 for_each_old_connector_in_state(&state
->base
, conn
, old_conn_state
, i
) {
1370 struct intel_encoder
*encoder
=
1371 to_intel_encoder(old_conn_state
->best_encoder
);
1373 if (old_conn_state
->crtc
!= &crtc
->base
)
1376 intel_opregion_notify_encoder(encoder
, false);
1377 if (encoder
->disable
)
1378 encoder
->disable(state
, encoder
,
1379 old_crtc_state
, old_conn_state
);
1383 static void intel_encoders_post_disable(struct intel_atomic_state
*state
,
1384 struct intel_crtc
*crtc
)
1386 const struct intel_crtc_state
*old_crtc_state
=
1387 intel_atomic_get_old_crtc_state(state
, crtc
);
1388 const struct drm_connector_state
*old_conn_state
;
1389 struct drm_connector
*conn
;
1392 for_each_old_connector_in_state(&state
->base
, conn
, old_conn_state
, i
) {
1393 struct intel_encoder
*encoder
=
1394 to_intel_encoder(old_conn_state
->best_encoder
);
1396 if (old_conn_state
->crtc
!= &crtc
->base
)
1399 if (encoder
->post_disable
)
1400 encoder
->post_disable(state
, encoder
,
1401 old_crtc_state
, old_conn_state
);
1405 static void intel_encoders_post_pll_disable(struct intel_atomic_state
*state
,
1406 struct intel_crtc
*crtc
)
1408 const struct intel_crtc_state
*old_crtc_state
=
1409 intel_atomic_get_old_crtc_state(state
, crtc
);
1410 const struct drm_connector_state
*old_conn_state
;
1411 struct drm_connector
*conn
;
1414 for_each_old_connector_in_state(&state
->base
, conn
, old_conn_state
, i
) {
1415 struct intel_encoder
*encoder
=
1416 to_intel_encoder(old_conn_state
->best_encoder
);
1418 if (old_conn_state
->crtc
!= &crtc
->base
)
1421 if (encoder
->post_pll_disable
)
1422 encoder
->post_pll_disable(state
, encoder
,
1423 old_crtc_state
, old_conn_state
);
1427 static void intel_encoders_update_pipe(struct intel_atomic_state
*state
,
1428 struct intel_crtc
*crtc
)
1430 const struct intel_crtc_state
*crtc_state
=
1431 intel_atomic_get_new_crtc_state(state
, crtc
);
1432 const struct drm_connector_state
*conn_state
;
1433 struct drm_connector
*conn
;
1436 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
1437 struct intel_encoder
*encoder
=
1438 to_intel_encoder(conn_state
->best_encoder
);
1440 if (conn_state
->crtc
!= &crtc
->base
)
1443 if (encoder
->update_pipe
)
1444 encoder
->update_pipe(state
, encoder
,
1445 crtc_state
, conn_state
);
1449 static void intel_disable_primary_plane(const struct intel_crtc_state
*crtc_state
)
1451 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1452 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
1454 plane
->disable_arm(plane
, crtc_state
);
1457 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state
)
1459 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1460 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1462 if (crtc_state
->has_pch_encoder
) {
1463 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
1464 &crtc_state
->fdi_m_n
);
1465 } else if (intel_crtc_has_dp_encoder(crtc_state
)) {
1466 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
1467 &crtc_state
->dp_m_n
);
1468 intel_cpu_transcoder_set_m2_n2(crtc
, cpu_transcoder
,
1469 &crtc_state
->dp_m2_n2
);
1472 intel_set_transcoder_timings(crtc_state
);
1474 ilk_set_pipeconf(crtc_state
);
1477 static void ilk_crtc_enable(struct intel_atomic_state
*state
,
1478 struct intel_crtc
*crtc
)
1480 const struct intel_crtc_state
*new_crtc_state
=
1481 intel_atomic_get_new_crtc_state(state
, crtc
);
1482 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1483 enum pipe pipe
= crtc
->pipe
;
1485 if (drm_WARN_ON(&dev_priv
->drm
, crtc
->active
))
1489 * Sometimes spurious CPU pipe underruns happen during FDI
1490 * training, at least with VGA+HDMI cloning. Suppress them.
1492 * On ILK we get an occasional spurious CPU pipe underruns
1493 * between eDP port A enable and vdd enable. Also PCH port
1494 * enable seems to result in the occasional CPU pipe underrun.
1496 * Spurious PCH underruns also occur during PCH enabling.
1498 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
1499 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
1501 ilk_configure_cpu_transcoder(new_crtc_state
);
1503 intel_set_pipe_src_size(new_crtc_state
);
1505 crtc
->active
= true;
1507 intel_encoders_pre_enable(state
, crtc
);
1509 if (new_crtc_state
->has_pch_encoder
) {
1510 ilk_pch_pre_enable(state
, crtc
);
1512 assert_fdi_tx_disabled(dev_priv
, pipe
);
1513 assert_fdi_rx_disabled(dev_priv
, pipe
);
1516 ilk_pfit_enable(new_crtc_state
);
1519 * On ILK+ LUT must be loaded before the pipe is running but with
1522 intel_color_load_luts(new_crtc_state
);
1523 intel_color_commit_noarm(new_crtc_state
);
1524 intel_color_commit_arm(new_crtc_state
);
1525 /* update DSPCNTR to configure gamma for pipe bottom color */
1526 intel_disable_primary_plane(new_crtc_state
);
1528 intel_initial_watermarks(state
, crtc
);
1529 intel_enable_transcoder(new_crtc_state
);
1531 if (new_crtc_state
->has_pch_encoder
)
1532 ilk_pch_enable(state
, crtc
);
1534 intel_crtc_vblank_on(new_crtc_state
);
1536 intel_encoders_enable(state
, crtc
);
1538 if (HAS_PCH_CPT(dev_priv
))
1539 intel_wait_for_pipe_scanline_moving(crtc
);
1542 * Must wait for vblank to avoid spurious PCH FIFO underruns.
1543 * And a second vblank wait is needed at least on ILK with
1544 * some interlaced HDMI modes. Let's do the double wait always
1545 * in case there are more corner cases we don't know about.
1547 if (new_crtc_state
->has_pch_encoder
) {
1548 intel_crtc_wait_for_next_vblank(crtc
);
1549 intel_crtc_wait_for_next_vblank(crtc
);
1551 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
1552 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
1555 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private
*dev_priv
,
1556 enum pipe pipe
, bool apply
)
1558 u32 val
= intel_de_read(dev_priv
, CLKGATE_DIS_PSL(pipe
));
1559 u32 mask
= DPF_GATING_DIS
| DPF_RAM_GATING_DIS
| DPFR_GATING_DIS
;
1566 intel_de_write(dev_priv
, CLKGATE_DIS_PSL(pipe
), val
);
1569 static void hsw_set_linetime_wm(const struct intel_crtc_state
*crtc_state
)
1571 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1572 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1574 intel_de_write(dev_priv
, WM_LINETIME(crtc
->pipe
),
1575 HSW_LINETIME(crtc_state
->linetime
) |
1576 HSW_IPS_LINETIME(crtc_state
->ips_linetime
));
1579 static void hsw_set_frame_start_delay(const struct intel_crtc_state
*crtc_state
)
1581 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1582 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
1584 intel_de_rmw(i915
, hsw_chicken_trans_reg(i915
, crtc_state
->cpu_transcoder
),
1585 HSW_FRAME_START_DELAY_MASK
,
1586 HSW_FRAME_START_DELAY(crtc_state
->framestart_delay
- 1));
1589 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state
*state
,
1590 const struct intel_crtc_state
*crtc_state
)
1592 struct intel_crtc
*master_crtc
= intel_master_crtc(crtc_state
);
1595 * Enable sequence steps 1-7 on bigjoiner master
1597 if (intel_crtc_is_bigjoiner_slave(crtc_state
))
1598 intel_encoders_pre_pll_enable(state
, master_crtc
);
1600 if (crtc_state
->shared_dpll
)
1601 intel_enable_shared_dpll(crtc_state
);
1603 if (intel_crtc_is_bigjoiner_slave(crtc_state
))
1604 intel_encoders_pre_enable(state
, master_crtc
);
1607 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state
)
1609 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1610 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1611 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1613 if (crtc_state
->has_pch_encoder
) {
1614 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
1615 &crtc_state
->fdi_m_n
);
1616 } else if (intel_crtc_has_dp_encoder(crtc_state
)) {
1617 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
1618 &crtc_state
->dp_m_n
);
1619 intel_cpu_transcoder_set_m2_n2(crtc
, cpu_transcoder
,
1620 &crtc_state
->dp_m2_n2
);
1623 intel_set_transcoder_timings(crtc_state
);
1624 if (HAS_VRR(dev_priv
))
1625 intel_vrr_set_transcoder_timings(crtc_state
);
1627 if (cpu_transcoder
!= TRANSCODER_EDP
)
1628 intel_de_write(dev_priv
, TRANS_MULT(cpu_transcoder
),
1629 crtc_state
->pixel_multiplier
- 1);
1631 hsw_set_frame_start_delay(crtc_state
);
1633 hsw_set_transconf(crtc_state
);
1636 static void hsw_crtc_enable(struct intel_atomic_state
*state
,
1637 struct intel_crtc
*crtc
)
1639 const struct intel_crtc_state
*new_crtc_state
=
1640 intel_atomic_get_new_crtc_state(state
, crtc
);
1641 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1642 enum pipe pipe
= crtc
->pipe
, hsw_workaround_pipe
;
1643 enum transcoder cpu_transcoder
= new_crtc_state
->cpu_transcoder
;
1644 bool psl_clkgate_wa
;
1646 if (drm_WARN_ON(&dev_priv
->drm
, crtc
->active
))
1649 intel_dmc_enable_pipe(dev_priv
, crtc
->pipe
);
1651 if (!new_crtc_state
->bigjoiner_pipes
) {
1652 intel_encoders_pre_pll_enable(state
, crtc
);
1654 if (new_crtc_state
->shared_dpll
)
1655 intel_enable_shared_dpll(new_crtc_state
);
1657 intel_encoders_pre_enable(state
, crtc
);
1659 icl_ddi_bigjoiner_pre_enable(state
, new_crtc_state
);
1662 intel_dsc_enable(new_crtc_state
);
1664 if (DISPLAY_VER(dev_priv
) >= 13)
1665 intel_uncompressed_joiner_enable(new_crtc_state
);
1667 intel_set_pipe_src_size(new_crtc_state
);
1668 if (DISPLAY_VER(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
1669 bdw_set_pipe_misc(new_crtc_state
);
1671 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state
) &&
1672 !transcoder_is_dsi(cpu_transcoder
))
1673 hsw_configure_cpu_transcoder(new_crtc_state
);
1675 crtc
->active
= true;
1677 /* Display WA #1180: WaDisableScalarClockGating: glk */
1678 psl_clkgate_wa
= DISPLAY_VER(dev_priv
) == 10 &&
1679 new_crtc_state
->pch_pfit
.enabled
;
1681 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, true);
1683 if (DISPLAY_VER(dev_priv
) >= 9)
1684 skl_pfit_enable(new_crtc_state
);
1686 ilk_pfit_enable(new_crtc_state
);
1689 * On ILK+ LUT must be loaded before the pipe is running but with
1692 intel_color_load_luts(new_crtc_state
);
1693 intel_color_commit_noarm(new_crtc_state
);
1694 intel_color_commit_arm(new_crtc_state
);
1695 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1696 if (DISPLAY_VER(dev_priv
) < 9)
1697 intel_disable_primary_plane(new_crtc_state
);
1699 hsw_set_linetime_wm(new_crtc_state
);
1701 if (DISPLAY_VER(dev_priv
) >= 11)
1702 icl_set_pipe_chicken(new_crtc_state
);
1704 intel_initial_watermarks(state
, crtc
);
1706 if (intel_crtc_is_bigjoiner_slave(new_crtc_state
))
1707 intel_crtc_vblank_on(new_crtc_state
);
1709 intel_encoders_enable(state
, crtc
);
1711 if (psl_clkgate_wa
) {
1712 intel_crtc_wait_for_next_vblank(crtc
);
1713 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, false);
1716 /* If we change the relative order between pipe/planes enabling, we need
1717 * to change the workaround. */
1718 hsw_workaround_pipe
= new_crtc_state
->hsw_workaround_pipe
;
1719 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
1720 struct intel_crtc
*wa_crtc
;
1722 wa_crtc
= intel_crtc_for_pipe(dev_priv
, hsw_workaround_pipe
);
1724 intel_crtc_wait_for_next_vblank(wa_crtc
);
1725 intel_crtc_wait_for_next_vblank(wa_crtc
);
1729 void ilk_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
1731 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
1732 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1733 enum pipe pipe
= crtc
->pipe
;
1735 /* To avoid upsetting the power well on haswell only disable the pfit if
1736 * it's in use. The hw state code will make sure we get this right. */
1737 if (!old_crtc_state
->pch_pfit
.enabled
)
1740 intel_de_write_fw(dev_priv
, PF_CTL(pipe
), 0);
1741 intel_de_write_fw(dev_priv
, PF_WIN_POS(pipe
), 0);
1742 intel_de_write_fw(dev_priv
, PF_WIN_SZ(pipe
), 0);
1745 static void ilk_crtc_disable(struct intel_atomic_state
*state
,
1746 struct intel_crtc
*crtc
)
1748 const struct intel_crtc_state
*old_crtc_state
=
1749 intel_atomic_get_old_crtc_state(state
, crtc
);
1750 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1751 enum pipe pipe
= crtc
->pipe
;
1754 * Sometimes spurious CPU pipe underruns happen when the
1755 * pipe is already disabled, but FDI RX/TX is still enabled.
1756 * Happens at least with VGA+HDMI cloning. Suppress them.
1758 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
1759 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
1761 intel_encoders_disable(state
, crtc
);
1763 intel_crtc_vblank_off(old_crtc_state
);
1765 intel_disable_transcoder(old_crtc_state
);
1767 ilk_pfit_disable(old_crtc_state
);
1769 if (old_crtc_state
->has_pch_encoder
)
1770 ilk_pch_disable(state
, crtc
);
1772 intel_encoders_post_disable(state
, crtc
);
1774 if (old_crtc_state
->has_pch_encoder
)
1775 ilk_pch_post_disable(state
, crtc
);
1777 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
1778 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
1780 intel_disable_shared_dpll(old_crtc_state
);
1783 static void hsw_crtc_disable(struct intel_atomic_state
*state
,
1784 struct intel_crtc
*crtc
)
1786 const struct intel_crtc_state
*old_crtc_state
=
1787 intel_atomic_get_old_crtc_state(state
, crtc
);
1788 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
1791 * FIXME collapse everything to one hook.
1792 * Need care with mst->ddi interactions.
1794 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state
)) {
1795 intel_encoders_disable(state
, crtc
);
1796 intel_encoders_post_disable(state
, crtc
);
1799 intel_disable_shared_dpll(old_crtc_state
);
1801 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state
)) {
1802 struct intel_crtc
*slave_crtc
;
1804 intel_encoders_post_pll_disable(state
, crtc
);
1806 intel_dmc_disable_pipe(i915
, crtc
->pipe
);
1808 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, slave_crtc
,
1809 intel_crtc_bigjoiner_slave_pipes(old_crtc_state
))
1810 intel_dmc_disable_pipe(i915
, slave_crtc
->pipe
);
1814 static void i9xx_pfit_enable(const struct intel_crtc_state
*crtc_state
)
1816 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1817 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1819 if (!crtc_state
->gmch_pfit
.control
)
1823 * The panel fitter should only be adjusted whilst the pipe is disabled,
1824 * according to register description and PRM.
1826 drm_WARN_ON(&dev_priv
->drm
,
1827 intel_de_read(dev_priv
, PFIT_CONTROL
) & PFIT_ENABLE
);
1828 assert_transcoder_disabled(dev_priv
, crtc_state
->cpu_transcoder
);
1830 intel_de_write(dev_priv
, PFIT_PGM_RATIOS
,
1831 crtc_state
->gmch_pfit
.pgm_ratios
);
1832 intel_de_write(dev_priv
, PFIT_CONTROL
, crtc_state
->gmch_pfit
.control
);
1834 /* Border color in case we don't scale up to the full screen. Black by
1835 * default, change to something else for debugging. */
1836 intel_de_write(dev_priv
, BCLRPAT(crtc
->pipe
), 0);
1839 bool intel_phy_is_combo(struct drm_i915_private
*dev_priv
, enum phy phy
)
1841 if (phy
== PHY_NONE
)
1843 else if (IS_ALDERLAKE_S(dev_priv
))
1844 return phy
<= PHY_E
;
1845 else if (IS_DG1(dev_priv
) || IS_ROCKETLAKE(dev_priv
))
1846 return phy
<= PHY_D
;
1847 else if (IS_JASPERLAKE(dev_priv
) || IS_ELKHARTLAKE(dev_priv
))
1848 return phy
<= PHY_C
;
1849 else if (IS_ALDERLAKE_P(dev_priv
) || IS_DISPLAY_VER(dev_priv
, 11, 12))
1850 return phy
<= PHY_B
;
1853 * DG2 outputs labelled as "combo PHY" in the bspec use
1854 * SNPS PHYs with completely different programming,
1855 * hence we always return false here.
1860 bool intel_phy_is_tc(struct drm_i915_private
*dev_priv
, enum phy phy
)
1863 * DG2's "TC1", although TC-capable output, doesn't share the same flow
1864 * as other platforms on the display engine side and rather rely on the
1865 * SNPS PHY, that is programmed separately
1867 if (IS_DG2(dev_priv
))
1870 if (DISPLAY_VER(dev_priv
) >= 13)
1871 return phy
>= PHY_F
&& phy
<= PHY_I
;
1872 else if (IS_TIGERLAKE(dev_priv
))
1873 return phy
>= PHY_D
&& phy
<= PHY_I
;
1874 else if (IS_ICELAKE(dev_priv
))
1875 return phy
>= PHY_C
&& phy
<= PHY_F
;
1880 bool intel_phy_is_snps(struct drm_i915_private
*dev_priv
, enum phy phy
)
1883 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
1884 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
1886 return IS_DG2(dev_priv
) && phy
> PHY_NONE
&& phy
<= PHY_E
;
1889 enum phy
intel_port_to_phy(struct drm_i915_private
*i915
, enum port port
)
1891 if (DISPLAY_VER(i915
) >= 13 && port
>= PORT_D_XELPD
)
1892 return PHY_D
+ port
- PORT_D_XELPD
;
1893 else if (DISPLAY_VER(i915
) >= 13 && port
>= PORT_TC1
)
1894 return PHY_F
+ port
- PORT_TC1
;
1895 else if (IS_ALDERLAKE_S(i915
) && port
>= PORT_TC1
)
1896 return PHY_B
+ port
- PORT_TC1
;
1897 else if ((IS_DG1(i915
) || IS_ROCKETLAKE(i915
)) && port
>= PORT_TC1
)
1898 return PHY_C
+ port
- PORT_TC1
;
1899 else if ((IS_JASPERLAKE(i915
) || IS_ELKHARTLAKE(i915
)) &&
1903 return PHY_A
+ port
- PORT_A
;
1906 enum tc_port
intel_port_to_tc(struct drm_i915_private
*dev_priv
, enum port port
)
1908 if (!intel_phy_is_tc(dev_priv
, intel_port_to_phy(dev_priv
, port
)))
1909 return TC_PORT_NONE
;
1911 if (DISPLAY_VER(dev_priv
) >= 12)
1912 return TC_PORT_1
+ port
- PORT_TC1
;
1914 return TC_PORT_1
+ port
- PORT_C
;
1917 enum intel_display_power_domain
1918 intel_aux_power_domain(struct intel_digital_port
*dig_port
)
1920 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1922 if (intel_tc_port_in_tbt_alt_mode(dig_port
))
1923 return intel_display_power_tbt_aux_domain(i915
, dig_port
->aux_ch
);
1925 return intel_display_power_legacy_aux_domain(i915
, dig_port
->aux_ch
);
1928 static void get_crtc_power_domains(struct intel_crtc_state
*crtc_state
,
1929 struct intel_power_domain_mask
*mask
)
1931 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1932 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1933 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1934 struct drm_encoder
*encoder
;
1935 enum pipe pipe
= crtc
->pipe
;
1937 bitmap_zero(mask
->bits
, POWER_DOMAIN_NUM
);
1939 if (!crtc_state
->hw
.active
)
1942 set_bit(POWER_DOMAIN_PIPE(pipe
), mask
->bits
);
1943 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder
), mask
->bits
);
1944 if (crtc_state
->pch_pfit
.enabled
||
1945 crtc_state
->pch_pfit
.force_thru
)
1946 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
), mask
->bits
);
1948 drm_for_each_encoder_mask(encoder
, &dev_priv
->drm
,
1949 crtc_state
->uapi
.encoder_mask
) {
1950 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1952 set_bit(intel_encoder
->power_domain
, mask
->bits
);
1955 if (HAS_DDI(dev_priv
) && crtc_state
->has_audio
)
1956 set_bit(POWER_DOMAIN_AUDIO_MMIO
, mask
->bits
);
1958 if (crtc_state
->shared_dpll
)
1959 set_bit(POWER_DOMAIN_DISPLAY_CORE
, mask
->bits
);
1961 if (crtc_state
->dsc
.compression_enable
)
1962 set_bit(intel_dsc_power_domain(crtc
, cpu_transcoder
), mask
->bits
);
1965 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state
*crtc_state
,
1966 struct intel_power_domain_mask
*old_domains
)
1968 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1969 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1970 enum intel_display_power_domain domain
;
1971 struct intel_power_domain_mask domains
, new_domains
;
1973 get_crtc_power_domains(crtc_state
, &domains
);
1975 bitmap_andnot(new_domains
.bits
,
1977 crtc
->enabled_power_domains
.mask
.bits
,
1979 bitmap_andnot(old_domains
->bits
,
1980 crtc
->enabled_power_domains
.mask
.bits
,
1984 for_each_power_domain(domain
, &new_domains
)
1985 intel_display_power_get_in_set(dev_priv
,
1986 &crtc
->enabled_power_domains
,
1990 void intel_modeset_put_crtc_power_domains(struct intel_crtc
*crtc
,
1991 struct intel_power_domain_mask
*domains
)
1993 intel_display_power_put_mask_in_set(to_i915(crtc
->base
.dev
),
1994 &crtc
->enabled_power_domains
,
1998 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state
)
2000 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2001 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2003 if (intel_crtc_has_dp_encoder(crtc_state
)) {
2004 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
2005 &crtc_state
->dp_m_n
);
2006 intel_cpu_transcoder_set_m2_n2(crtc
, cpu_transcoder
,
2007 &crtc_state
->dp_m2_n2
);
2010 intel_set_transcoder_timings(crtc_state
);
2012 i9xx_set_pipeconf(crtc_state
);
2015 static void valleyview_crtc_enable(struct intel_atomic_state
*state
,
2016 struct intel_crtc
*crtc
)
2018 const struct intel_crtc_state
*new_crtc_state
=
2019 intel_atomic_get_new_crtc_state(state
, crtc
);
2020 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2021 enum pipe pipe
= crtc
->pipe
;
2023 if (drm_WARN_ON(&dev_priv
->drm
, crtc
->active
))
2026 i9xx_configure_cpu_transcoder(new_crtc_state
);
2028 intel_set_pipe_src_size(new_crtc_state
);
2030 intel_de_write(dev_priv
, VLV_PIPE_MSA_MISC(pipe
), 0);
2032 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
2033 intel_de_write(dev_priv
, CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
2034 intel_de_write(dev_priv
, CHV_CANVAS(pipe
), 0);
2037 crtc
->active
= true;
2039 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
2041 intel_encoders_pre_pll_enable(state
, crtc
);
2043 if (IS_CHERRYVIEW(dev_priv
))
2044 chv_enable_pll(new_crtc_state
);
2046 vlv_enable_pll(new_crtc_state
);
2048 intel_encoders_pre_enable(state
, crtc
);
2050 i9xx_pfit_enable(new_crtc_state
);
2052 intel_color_load_luts(new_crtc_state
);
2053 intel_color_commit_noarm(new_crtc_state
);
2054 intel_color_commit_arm(new_crtc_state
);
2055 /* update DSPCNTR to configure gamma for pipe bottom color */
2056 intel_disable_primary_plane(new_crtc_state
);
2058 intel_initial_watermarks(state
, crtc
);
2059 intel_enable_transcoder(new_crtc_state
);
2061 intel_crtc_vblank_on(new_crtc_state
);
2063 intel_encoders_enable(state
, crtc
);
2066 static void i9xx_crtc_enable(struct intel_atomic_state
*state
,
2067 struct intel_crtc
*crtc
)
2069 const struct intel_crtc_state
*new_crtc_state
=
2070 intel_atomic_get_new_crtc_state(state
, crtc
);
2071 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2072 enum pipe pipe
= crtc
->pipe
;
2074 if (drm_WARN_ON(&dev_priv
->drm
, crtc
->active
))
2077 i9xx_configure_cpu_transcoder(new_crtc_state
);
2079 intel_set_pipe_src_size(new_crtc_state
);
2081 crtc
->active
= true;
2083 if (DISPLAY_VER(dev_priv
) != 2)
2084 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
2086 intel_encoders_pre_enable(state
, crtc
);
2088 i9xx_enable_pll(new_crtc_state
);
2090 i9xx_pfit_enable(new_crtc_state
);
2092 intel_color_load_luts(new_crtc_state
);
2093 intel_color_commit_noarm(new_crtc_state
);
2094 intel_color_commit_arm(new_crtc_state
);
2095 /* update DSPCNTR to configure gamma for pipe bottom color */
2096 intel_disable_primary_plane(new_crtc_state
);
2098 if (!intel_initial_watermarks(state
, crtc
))
2099 intel_update_watermarks(dev_priv
);
2100 intel_enable_transcoder(new_crtc_state
);
2102 intel_crtc_vblank_on(new_crtc_state
);
2104 intel_encoders_enable(state
, crtc
);
2106 /* prevents spurious underruns */
2107 if (DISPLAY_VER(dev_priv
) == 2)
2108 intel_crtc_wait_for_next_vblank(crtc
);
2111 static void i9xx_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
2113 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
2114 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2116 if (!old_crtc_state
->gmch_pfit
.control
)
2119 assert_transcoder_disabled(dev_priv
, old_crtc_state
->cpu_transcoder
);
2121 drm_dbg_kms(&dev_priv
->drm
, "disabling pfit, current: 0x%08x\n",
2122 intel_de_read(dev_priv
, PFIT_CONTROL
));
2123 intel_de_write(dev_priv
, PFIT_CONTROL
, 0);
2126 static void i9xx_crtc_disable(struct intel_atomic_state
*state
,
2127 struct intel_crtc
*crtc
)
2129 struct intel_crtc_state
*old_crtc_state
=
2130 intel_atomic_get_old_crtc_state(state
, crtc
);
2131 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2132 enum pipe pipe
= crtc
->pipe
;
2135 * On gen2 planes are double buffered but the pipe isn't, so we must
2136 * wait for planes to fully turn off before disabling the pipe.
2138 if (DISPLAY_VER(dev_priv
) == 2)
2139 intel_crtc_wait_for_next_vblank(crtc
);
2141 intel_encoders_disable(state
, crtc
);
2143 intel_crtc_vblank_off(old_crtc_state
);
2145 intel_disable_transcoder(old_crtc_state
);
2147 i9xx_pfit_disable(old_crtc_state
);
2149 intel_encoders_post_disable(state
, crtc
);
2151 if (!intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DSI
)) {
2152 if (IS_CHERRYVIEW(dev_priv
))
2153 chv_disable_pll(dev_priv
, pipe
);
2154 else if (IS_VALLEYVIEW(dev_priv
))
2155 vlv_disable_pll(dev_priv
, pipe
);
2157 i9xx_disable_pll(old_crtc_state
);
2160 intel_encoders_post_pll_disable(state
, crtc
);
2162 if (DISPLAY_VER(dev_priv
) != 2)
2163 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
2165 if (!dev_priv
->display
.funcs
.wm
->initial_watermarks
)
2166 intel_update_watermarks(dev_priv
);
2168 /* clock the pipe down to 640x480@60 to potentially save power */
2169 if (IS_I830(dev_priv
))
2170 i830_enable_pipe(dev_priv
, pipe
);
2173 void intel_encoder_destroy(struct drm_encoder
*encoder
)
2175 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
2177 drm_encoder_cleanup(encoder
);
2178 kfree(intel_encoder
);
2181 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
2183 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2185 /* GDG double wide on either pipe, otherwise pipe A only */
2186 return DISPLAY_VER(dev_priv
) < 4 &&
2187 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
2190 static u32
ilk_pipe_pixel_rate(const struct intel_crtc_state
*crtc_state
)
2192 u32 pixel_rate
= crtc_state
->hw
.pipe_mode
.crtc_clock
;
2193 struct drm_rect src
;
2196 * We only use IF-ID interlacing. If we ever use
2197 * PF-ID we'll need to adjust the pixel_rate here.
2200 if (!crtc_state
->pch_pfit
.enabled
)
2203 drm_rect_init(&src
, 0, 0,
2204 drm_rect_width(&crtc_state
->pipe_src
) << 16,
2205 drm_rect_height(&crtc_state
->pipe_src
) << 16);
2207 return intel_adjusted_rate(&src
, &crtc_state
->pch_pfit
.dst
,
2211 static void intel_mode_from_crtc_timings(struct drm_display_mode
*mode
,
2212 const struct drm_display_mode
*timings
)
2214 mode
->hdisplay
= timings
->crtc_hdisplay
;
2215 mode
->htotal
= timings
->crtc_htotal
;
2216 mode
->hsync_start
= timings
->crtc_hsync_start
;
2217 mode
->hsync_end
= timings
->crtc_hsync_end
;
2219 mode
->vdisplay
= timings
->crtc_vdisplay
;
2220 mode
->vtotal
= timings
->crtc_vtotal
;
2221 mode
->vsync_start
= timings
->crtc_vsync_start
;
2222 mode
->vsync_end
= timings
->crtc_vsync_end
;
2224 mode
->flags
= timings
->flags
;
2225 mode
->type
= DRM_MODE_TYPE_DRIVER
;
2227 mode
->clock
= timings
->crtc_clock
;
2229 drm_mode_set_name(mode
);
2232 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state
*crtc_state
)
2234 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
2236 if (HAS_GMCH(dev_priv
))
2237 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2238 crtc_state
->pixel_rate
=
2239 crtc_state
->hw
.pipe_mode
.crtc_clock
;
2241 crtc_state
->pixel_rate
=
2242 ilk_pipe_pixel_rate(crtc_state
);
2245 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state
*crtc_state
,
2246 struct drm_display_mode
*mode
)
2248 int num_pipes
= intel_bigjoiner_num_pipes(crtc_state
);
2253 mode
->crtc_clock
/= num_pipes
;
2254 mode
->crtc_hdisplay
/= num_pipes
;
2255 mode
->crtc_hblank_start
/= num_pipes
;
2256 mode
->crtc_hblank_end
/= num_pipes
;
2257 mode
->crtc_hsync_start
/= num_pipes
;
2258 mode
->crtc_hsync_end
/= num_pipes
;
2259 mode
->crtc_htotal
/= num_pipes
;
2262 static void intel_splitter_adjust_timings(const struct intel_crtc_state
*crtc_state
,
2263 struct drm_display_mode
*mode
)
2265 int overlap
= crtc_state
->splitter
.pixel_overlap
;
2266 int n
= crtc_state
->splitter
.link_count
;
2268 if (!crtc_state
->splitter
.enable
)
2272 * eDP MSO uses segment timings from EDID for transcoder
2273 * timings, but full mode for everything else.
2275 * h_full = (h_segment - pixel_overlap) * link_count
2277 mode
->crtc_hdisplay
= (mode
->crtc_hdisplay
- overlap
) * n
;
2278 mode
->crtc_hblank_start
= (mode
->crtc_hblank_start
- overlap
) * n
;
2279 mode
->crtc_hblank_end
= (mode
->crtc_hblank_end
- overlap
) * n
;
2280 mode
->crtc_hsync_start
= (mode
->crtc_hsync_start
- overlap
) * n
;
2281 mode
->crtc_hsync_end
= (mode
->crtc_hsync_end
- overlap
) * n
;
2282 mode
->crtc_htotal
= (mode
->crtc_htotal
- overlap
) * n
;
2283 mode
->crtc_clock
*= n
;
2286 static void intel_crtc_readout_derived_state(struct intel_crtc_state
*crtc_state
)
2288 struct drm_display_mode
*mode
= &crtc_state
->hw
.mode
;
2289 struct drm_display_mode
*pipe_mode
= &crtc_state
->hw
.pipe_mode
;
2290 struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
2293 * Start with the adjusted_mode crtc timings, which
2294 * have been filled with the transcoder timings.
2296 drm_mode_copy(pipe_mode
, adjusted_mode
);
2298 /* Expand MSO per-segment transcoder timings to full */
2299 intel_splitter_adjust_timings(crtc_state
, pipe_mode
);
2302 * We want the full numbers in adjusted_mode normal timings,
2303 * adjusted_mode crtc timings are left with the raw transcoder
2306 intel_mode_from_crtc_timings(adjusted_mode
, pipe_mode
);
2308 /* Populate the "user" mode with full numbers */
2309 drm_mode_copy(mode
, pipe_mode
);
2310 intel_mode_from_crtc_timings(mode
, mode
);
2311 mode
->hdisplay
= drm_rect_width(&crtc_state
->pipe_src
) *
2312 (intel_bigjoiner_num_pipes(crtc_state
) ?: 1);
2313 mode
->vdisplay
= drm_rect_height(&crtc_state
->pipe_src
);
2315 /* Derive per-pipe timings in case bigjoiner is used */
2316 intel_bigjoiner_adjust_timings(crtc_state
, pipe_mode
);
2317 intel_mode_from_crtc_timings(pipe_mode
, pipe_mode
);
2319 intel_crtc_compute_pixel_rate(crtc_state
);
2322 void intel_encoder_get_config(struct intel_encoder
*encoder
,
2323 struct intel_crtc_state
*crtc_state
)
2325 encoder
->get_config(encoder
, crtc_state
);
2327 intel_crtc_readout_derived_state(crtc_state
);
2330 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state
*crtc_state
)
2332 int num_pipes
= intel_bigjoiner_num_pipes(crtc_state
);
2338 width
= drm_rect_width(&crtc_state
->pipe_src
);
2339 height
= drm_rect_height(&crtc_state
->pipe_src
);
2341 drm_rect_init(&crtc_state
->pipe_src
, 0, 0,
2342 width
/ num_pipes
, height
);
2345 static int intel_crtc_compute_pipe_src(struct intel_crtc_state
*crtc_state
)
2347 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2348 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2350 intel_bigjoiner_compute_pipe_src(crtc_state
);
2353 * Pipe horizontal size must be even in:
2355 * - LVDS dual channel mode
2356 * - Double wide pipe
2358 if (drm_rect_width(&crtc_state
->pipe_src
) & 1) {
2359 if (crtc_state
->double_wide
) {
2360 drm_dbg_kms(&i915
->drm
,
2361 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2362 crtc
->base
.base
.id
, crtc
->base
.name
);
2366 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
2367 intel_is_dual_link_lvds(i915
)) {
2368 drm_dbg_kms(&i915
->drm
,
2369 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2370 crtc
->base
.base
.id
, crtc
->base
.name
);
2378 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state
*crtc_state
)
2380 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2381 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2382 struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
2383 struct drm_display_mode
*pipe_mode
= &crtc_state
->hw
.pipe_mode
;
2384 int clock_limit
= i915
->max_dotclk_freq
;
2387 * Start with the adjusted_mode crtc timings, which
2388 * have been filled with the transcoder timings.
2390 drm_mode_copy(pipe_mode
, adjusted_mode
);
2392 /* Expand MSO per-segment transcoder timings to full */
2393 intel_splitter_adjust_timings(crtc_state
, pipe_mode
);
2395 /* Derive per-pipe timings in case bigjoiner is used */
2396 intel_bigjoiner_adjust_timings(crtc_state
, pipe_mode
);
2397 intel_mode_from_crtc_timings(pipe_mode
, pipe_mode
);
2399 if (DISPLAY_VER(i915
) < 4) {
2400 clock_limit
= i915
->display
.cdclk
.max_cdclk_freq
* 9 / 10;
2403 * Enable double wide mode when the dot clock
2404 * is > 90% of the (display) core speed.
2406 if (intel_crtc_supports_double_wide(crtc
) &&
2407 pipe_mode
->crtc_clock
> clock_limit
) {
2408 clock_limit
= i915
->max_dotclk_freq
;
2409 crtc_state
->double_wide
= true;
2413 if (pipe_mode
->crtc_clock
> clock_limit
) {
2414 drm_dbg_kms(&i915
->drm
,
2415 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2416 crtc
->base
.base
.id
, crtc
->base
.name
,
2417 pipe_mode
->crtc_clock
, clock_limit
,
2418 str_yes_no(crtc_state
->double_wide
));
2425 static int intel_crtc_compute_config(struct intel_atomic_state
*state
,
2426 struct intel_crtc
*crtc
)
2428 struct intel_crtc_state
*crtc_state
=
2429 intel_atomic_get_new_crtc_state(state
, crtc
);
2432 ret
= intel_dpll_crtc_compute_clock(state
, crtc
);
2436 ret
= intel_crtc_compute_pipe_src(crtc_state
);
2440 ret
= intel_crtc_compute_pipe_mode(crtc_state
);
2444 intel_crtc_compute_pixel_rate(crtc_state
);
2446 if (crtc_state
->has_pch_encoder
)
2447 return ilk_fdi_compute_config(crtc
, crtc_state
);
2453 intel_reduce_m_n_ratio(u32
*num
, u32
*den
)
2455 while (*num
> DATA_LINK_M_N_MASK
||
2456 *den
> DATA_LINK_M_N_MASK
) {
2462 static void compute_m_n(u32
*ret_m
, u32
*ret_n
,
2463 u32 m
, u32 n
, u32 constant_n
)
2466 *ret_n
= constant_n
;
2468 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
2470 *ret_m
= div_u64(mul_u32_u32(m
, *ret_n
), n
);
2471 intel_reduce_m_n_ratio(ret_m
, ret_n
);
2475 intel_link_compute_m_n(u16 bits_per_pixel_x16
, int nlanes
,
2476 int pixel_clock
, int link_clock
,
2478 struct intel_link_m_n
*m_n
)
2480 u32 link_symbol_clock
= intel_dp_link_symbol_clock(link_clock
);
2481 u32 data_m
= intel_dp_effective_data_rate(pixel_clock
, bits_per_pixel_x16
,
2483 u32 data_n
= drm_dp_max_dprx_data_rate(link_clock
, nlanes
);
2486 * Windows/BIOS uses fixed M/N values always. Follow suit.
2488 * Also several DP dongles in particular seem to be fussy
2489 * about too large link M/N values. Presumably the 20bit
2490 * value used by Windows/BIOS is acceptable to everyone.
2493 compute_m_n(&m_n
->data_m
, &m_n
->data_n
,
2497 compute_m_n(&m_n
->link_m
, &m_n
->link_n
,
2498 pixel_clock
, link_symbol_clock
,
2502 void intel_panel_sanitize_ssc(struct drm_i915_private
*dev_priv
)
2505 * There may be no VBT; and if the BIOS enabled SSC we can
2506 * just keep using it to avoid unnecessary flicker. Whereas if the
2507 * BIOS isn't using it, don't assume it will work even if the VBT
2508 * indicates as much.
2510 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
2511 bool bios_lvds_use_ssc
= intel_de_read(dev_priv
,
2515 if (dev_priv
->display
.vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
2516 drm_dbg_kms(&dev_priv
->drm
,
2517 "SSC %s by BIOS, overriding VBT which says %s\n",
2518 str_enabled_disabled(bios_lvds_use_ssc
),
2519 str_enabled_disabled(dev_priv
->display
.vbt
.lvds_use_ssc
));
2520 dev_priv
->display
.vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
2525 void intel_zero_m_n(struct intel_link_m_n
*m_n
)
2527 /* corresponds to 0 register value */
2528 memset(m_n
, 0, sizeof(*m_n
));
2532 void intel_set_m_n(struct drm_i915_private
*i915
,
2533 const struct intel_link_m_n
*m_n
,
2534 i915_reg_t data_m_reg
, i915_reg_t data_n_reg
,
2535 i915_reg_t link_m_reg
, i915_reg_t link_n_reg
)
2537 intel_de_write(i915
, data_m_reg
, TU_SIZE(m_n
->tu
) | m_n
->data_m
);
2538 intel_de_write(i915
, data_n_reg
, m_n
->data_n
);
2539 intel_de_write(i915
, link_m_reg
, m_n
->link_m
);
2541 * On BDW+ writing LINK_N arms the double buffered update
2542 * of all the M/N registers, so it must be written last.
2544 intel_de_write(i915
, link_n_reg
, m_n
->link_n
);
2547 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private
*dev_priv
,
2548 enum transcoder transcoder
)
2550 if (IS_HASWELL(dev_priv
))
2551 return transcoder
== TRANSCODER_EDP
;
2553 return IS_DISPLAY_VER(dev_priv
, 5, 7) || IS_CHERRYVIEW(dev_priv
);
2556 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc
*crtc
,
2557 enum transcoder transcoder
,
2558 const struct intel_link_m_n
*m_n
)
2560 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2561 enum pipe pipe
= crtc
->pipe
;
2563 if (DISPLAY_VER(dev_priv
) >= 5)
2564 intel_set_m_n(dev_priv
, m_n
,
2565 PIPE_DATA_M1(transcoder
), PIPE_DATA_N1(transcoder
),
2566 PIPE_LINK_M1(transcoder
), PIPE_LINK_N1(transcoder
));
2568 intel_set_m_n(dev_priv
, m_n
,
2569 PIPE_DATA_M_G4X(pipe
), PIPE_DATA_N_G4X(pipe
),
2570 PIPE_LINK_M_G4X(pipe
), PIPE_LINK_N_G4X(pipe
));
2573 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc
*crtc
,
2574 enum transcoder transcoder
,
2575 const struct intel_link_m_n
*m_n
)
2577 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2579 if (!intel_cpu_transcoder_has_m2_n2(dev_priv
, transcoder
))
2582 intel_set_m_n(dev_priv
, m_n
,
2583 PIPE_DATA_M2(transcoder
), PIPE_DATA_N2(transcoder
),
2584 PIPE_LINK_M2(transcoder
), PIPE_LINK_N2(transcoder
));
2587 static void intel_set_transcoder_timings(const struct intel_crtc_state
*crtc_state
)
2589 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2590 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2591 enum pipe pipe
= crtc
->pipe
;
2592 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2593 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
2594 u32 crtc_vdisplay
, crtc_vtotal
, crtc_vblank_start
, crtc_vblank_end
;
2597 /* We need to be careful not to changed the adjusted mode, for otherwise
2598 * the hw state checker will get angry at the mismatch. */
2599 crtc_vdisplay
= adjusted_mode
->crtc_vdisplay
;
2600 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
2601 crtc_vblank_start
= adjusted_mode
->crtc_vblank_start
;
2602 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
2604 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
2605 /* the chip adds 2 halflines automatically */
2607 crtc_vblank_end
-= 1;
2609 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
2610 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
2612 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
2613 adjusted_mode
->crtc_htotal
/ 2;
2615 vsyncshift
+= adjusted_mode
->crtc_htotal
;
2619 * VBLANK_START no longer works on ADL+, instead we must use
2620 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2622 if (DISPLAY_VER(dev_priv
) >= 13) {
2623 intel_de_write(dev_priv
, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder
),
2624 crtc_vblank_start
- crtc_vdisplay
);
2627 * VBLANK_START not used by hw, just clear it
2628 * to make it stand out in register dumps.
2630 crtc_vblank_start
= 1;
2633 if (DISPLAY_VER(dev_priv
) >= 4)
2634 intel_de_write(dev_priv
, TRANS_VSYNCSHIFT(cpu_transcoder
),
2637 intel_de_write(dev_priv
, TRANS_HTOTAL(cpu_transcoder
),
2638 HACTIVE(adjusted_mode
->crtc_hdisplay
- 1) |
2639 HTOTAL(adjusted_mode
->crtc_htotal
- 1));
2640 intel_de_write(dev_priv
, TRANS_HBLANK(cpu_transcoder
),
2641 HBLANK_START(adjusted_mode
->crtc_hblank_start
- 1) |
2642 HBLANK_END(adjusted_mode
->crtc_hblank_end
- 1));
2643 intel_de_write(dev_priv
, TRANS_HSYNC(cpu_transcoder
),
2644 HSYNC_START(adjusted_mode
->crtc_hsync_start
- 1) |
2645 HSYNC_END(adjusted_mode
->crtc_hsync_end
- 1));
2647 intel_de_write(dev_priv
, TRANS_VTOTAL(cpu_transcoder
),
2648 VACTIVE(crtc_vdisplay
- 1) |
2649 VTOTAL(crtc_vtotal
- 1));
2650 intel_de_write(dev_priv
, TRANS_VBLANK(cpu_transcoder
),
2651 VBLANK_START(crtc_vblank_start
- 1) |
2652 VBLANK_END(crtc_vblank_end
- 1));
2653 intel_de_write(dev_priv
, TRANS_VSYNC(cpu_transcoder
),
2654 VSYNC_START(adjusted_mode
->crtc_vsync_start
- 1) |
2655 VSYNC_END(adjusted_mode
->crtc_vsync_end
- 1));
2657 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2658 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2659 * documented on the DDI_FUNC_CTL register description, EDP Input Select
2661 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
2662 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
2663 intel_de_write(dev_priv
, TRANS_VTOTAL(pipe
),
2664 VACTIVE(crtc_vdisplay
- 1) |
2665 VTOTAL(crtc_vtotal
- 1));
2668 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state
*crtc_state
)
2670 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2671 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2672 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2673 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
2674 u32 crtc_vdisplay
, crtc_vtotal
, crtc_vblank_start
, crtc_vblank_end
;
2676 crtc_vdisplay
= adjusted_mode
->crtc_vdisplay
;
2677 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
2678 crtc_vblank_start
= adjusted_mode
->crtc_vblank_start
;
2679 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
2681 drm_WARN_ON(&dev_priv
->drm
, adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
);
2684 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2685 * But let's write it anyway to keep the state checker happy.
2687 intel_de_write(dev_priv
, TRANS_VBLANK(cpu_transcoder
),
2688 VBLANK_START(crtc_vblank_start
- 1) |
2689 VBLANK_END(crtc_vblank_end
- 1));
2691 * The double buffer latch point for TRANS_VTOTAL
2692 * is the transcoder's undelayed vblank.
2694 intel_de_write(dev_priv
, TRANS_VTOTAL(cpu_transcoder
),
2695 VACTIVE(crtc_vdisplay
- 1) |
2696 VTOTAL(crtc_vtotal
- 1));
2699 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
)
2701 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2702 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2703 int width
= drm_rect_width(&crtc_state
->pipe_src
);
2704 int height
= drm_rect_height(&crtc_state
->pipe_src
);
2705 enum pipe pipe
= crtc
->pipe
;
2707 /* pipesrc controls the size that is scaled from, which should
2708 * always be the user's requested size.
2710 intel_de_write(dev_priv
, PIPESRC(pipe
),
2711 PIPESRC_WIDTH(width
- 1) | PIPESRC_HEIGHT(height
- 1));
2713 if (!crtc_state
->enable_psr2_su_region_et
)
2716 width
= drm_rect_width(&crtc_state
->psr2_su_area
);
2717 height
= drm_rect_height(&crtc_state
->psr2_su_area
);
2719 intel_de_write(dev_priv
, PIPE_SRCSZ_ERLY_TPT(pipe
),
2720 PIPESRC_WIDTH(width
- 1) | PIPESRC_HEIGHT(height
- 1));
2723 static bool intel_pipe_is_interlaced(const struct intel_crtc_state
*crtc_state
)
2725 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
2726 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2728 if (DISPLAY_VER(dev_priv
) == 2)
2731 if (DISPLAY_VER(dev_priv
) >= 9 ||
2732 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
2733 return intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
)) & TRANSCONF_INTERLACE_MASK_HSW
;
2735 return intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
)) & TRANSCONF_INTERLACE_MASK
;
2738 static void intel_get_transcoder_timings(struct intel_crtc
*crtc
,
2739 struct intel_crtc_state
*pipe_config
)
2741 struct drm_device
*dev
= crtc
->base
.dev
;
2742 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2743 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
2744 struct drm_display_mode
*adjusted_mode
= &pipe_config
->hw
.adjusted_mode
;
2747 tmp
= intel_de_read(dev_priv
, TRANS_HTOTAL(cpu_transcoder
));
2748 adjusted_mode
->crtc_hdisplay
= REG_FIELD_GET(HACTIVE_MASK
, tmp
) + 1;
2749 adjusted_mode
->crtc_htotal
= REG_FIELD_GET(HTOTAL_MASK
, tmp
) + 1;
2751 if (!transcoder_is_dsi(cpu_transcoder
)) {
2752 tmp
= intel_de_read(dev_priv
, TRANS_HBLANK(cpu_transcoder
));
2753 adjusted_mode
->crtc_hblank_start
= REG_FIELD_GET(HBLANK_START_MASK
, tmp
) + 1;
2754 adjusted_mode
->crtc_hblank_end
= REG_FIELD_GET(HBLANK_END_MASK
, tmp
) + 1;
2757 tmp
= intel_de_read(dev_priv
, TRANS_HSYNC(cpu_transcoder
));
2758 adjusted_mode
->crtc_hsync_start
= REG_FIELD_GET(HSYNC_START_MASK
, tmp
) + 1;
2759 adjusted_mode
->crtc_hsync_end
= REG_FIELD_GET(HSYNC_END_MASK
, tmp
) + 1;
2761 tmp
= intel_de_read(dev_priv
, TRANS_VTOTAL(cpu_transcoder
));
2762 adjusted_mode
->crtc_vdisplay
= REG_FIELD_GET(VACTIVE_MASK
, tmp
) + 1;
2763 adjusted_mode
->crtc_vtotal
= REG_FIELD_GET(VTOTAL_MASK
, tmp
) + 1;
2765 /* FIXME TGL+ DSI transcoders have this! */
2766 if (!transcoder_is_dsi(cpu_transcoder
)) {
2767 tmp
= intel_de_read(dev_priv
, TRANS_VBLANK(cpu_transcoder
));
2768 adjusted_mode
->crtc_vblank_start
= REG_FIELD_GET(VBLANK_START_MASK
, tmp
) + 1;
2769 adjusted_mode
->crtc_vblank_end
= REG_FIELD_GET(VBLANK_END_MASK
, tmp
) + 1;
2771 tmp
= intel_de_read(dev_priv
, TRANS_VSYNC(cpu_transcoder
));
2772 adjusted_mode
->crtc_vsync_start
= REG_FIELD_GET(VSYNC_START_MASK
, tmp
) + 1;
2773 adjusted_mode
->crtc_vsync_end
= REG_FIELD_GET(VSYNC_END_MASK
, tmp
) + 1;
2775 if (intel_pipe_is_interlaced(pipe_config
)) {
2776 adjusted_mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
2777 adjusted_mode
->crtc_vtotal
+= 1;
2778 adjusted_mode
->crtc_vblank_end
+= 1;
2781 if (DISPLAY_VER(dev_priv
) >= 13 && !transcoder_is_dsi(cpu_transcoder
))
2782 adjusted_mode
->crtc_vblank_start
=
2783 adjusted_mode
->crtc_vdisplay
+
2784 intel_de_read(dev_priv
, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder
));
2787 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state
*crtc_state
)
2789 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2790 int num_pipes
= intel_bigjoiner_num_pipes(crtc_state
);
2791 enum pipe master_pipe
, pipe
= crtc
->pipe
;
2797 master_pipe
= bigjoiner_master_pipe(crtc_state
);
2798 width
= drm_rect_width(&crtc_state
->pipe_src
);
2800 drm_rect_translate_to(&crtc_state
->pipe_src
,
2801 (pipe
- master_pipe
) * width
, 0);
2804 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
2805 struct intel_crtc_state
*pipe_config
)
2807 struct drm_device
*dev
= crtc
->base
.dev
;
2808 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2811 tmp
= intel_de_read(dev_priv
, PIPESRC(crtc
->pipe
));
2813 drm_rect_init(&pipe_config
->pipe_src
, 0, 0,
2814 REG_FIELD_GET(PIPESRC_WIDTH_MASK
, tmp
) + 1,
2815 REG_FIELD_GET(PIPESRC_HEIGHT_MASK
, tmp
) + 1);
2817 intel_bigjoiner_adjust_pipe_src(pipe_config
);
2820 void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
2822 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2823 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2824 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2828 * - We keep both pipes enabled on 830
2829 * - During modeset the pipe is still disabled and must remain so
2830 * - During fastset the pipe is already enabled and must remain so
2832 if (IS_I830(dev_priv
) || !intel_crtc_needs_modeset(crtc_state
))
2833 val
|= TRANSCONF_ENABLE
;
2835 if (crtc_state
->double_wide
)
2836 val
|= TRANSCONF_DOUBLE_WIDE
;
2838 /* only g4x and later have fancy bpc/dither controls */
2839 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
2840 IS_CHERRYVIEW(dev_priv
)) {
2841 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2842 if (crtc_state
->dither
&& crtc_state
->pipe_bpp
!= 30)
2843 val
|= TRANSCONF_DITHER_EN
|
2844 TRANSCONF_DITHER_TYPE_SP
;
2846 switch (crtc_state
->pipe_bpp
) {
2848 /* Case prevented by intel_choose_pipe_bpp_dither. */
2849 MISSING_CASE(crtc_state
->pipe_bpp
);
2852 val
|= TRANSCONF_BPC_6
;
2855 val
|= TRANSCONF_BPC_8
;
2858 val
|= TRANSCONF_BPC_10
;
2863 if (crtc_state
->hw
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2864 if (DISPLAY_VER(dev_priv
) < 4 ||
2865 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
2866 val
|= TRANSCONF_INTERLACE_W_FIELD_INDICATION
;
2868 val
|= TRANSCONF_INTERLACE_W_SYNC_SHIFT
;
2870 val
|= TRANSCONF_INTERLACE_PROGRESSIVE
;
2873 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
2874 crtc_state
->limited_color_range
)
2875 val
|= TRANSCONF_COLOR_RANGE_SELECT
;
2877 val
|= TRANSCONF_GAMMA_MODE(crtc_state
->gamma_mode
);
2879 if (crtc_state
->wgc_enable
)
2880 val
|= TRANSCONF_WGC_ENABLE
;
2882 val
|= TRANSCONF_FRAME_START_DELAY(crtc_state
->framestart_delay
- 1);
2884 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
), val
);
2885 intel_de_posting_read(dev_priv
, TRANSCONF(cpu_transcoder
));
2888 static bool i9xx_has_pfit(struct drm_i915_private
*dev_priv
)
2890 if (IS_I830(dev_priv
))
2893 return DISPLAY_VER(dev_priv
) >= 4 ||
2894 IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
2897 static void i9xx_get_pfit_config(struct intel_crtc_state
*crtc_state
)
2899 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2900 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2904 if (!i9xx_has_pfit(dev_priv
))
2907 tmp
= intel_de_read(dev_priv
, PFIT_CONTROL
);
2908 if (!(tmp
& PFIT_ENABLE
))
2911 /* Check whether the pfit is attached to our pipe. */
2912 if (DISPLAY_VER(dev_priv
) >= 4)
2913 pipe
= REG_FIELD_GET(PFIT_PIPE_MASK
, tmp
);
2917 if (pipe
!= crtc
->pipe
)
2920 crtc_state
->gmch_pfit
.control
= tmp
;
2921 crtc_state
->gmch_pfit
.pgm_ratios
=
2922 intel_de_read(dev_priv
, PFIT_PGM_RATIOS
);
2925 static enum intel_output_format
2926 bdw_get_pipe_misc_output_format(struct intel_crtc
*crtc
)
2928 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2931 tmp
= intel_de_read(dev_priv
, PIPE_MISC(crtc
->pipe
));
2933 if (tmp
& PIPE_MISC_YUV420_ENABLE
) {
2934 /* We support 4:2:0 in full blend mode only */
2935 drm_WARN_ON(&dev_priv
->drm
,
2936 (tmp
& PIPE_MISC_YUV420_MODE_FULL_BLEND
) == 0);
2938 return INTEL_OUTPUT_FORMAT_YCBCR420
;
2939 } else if (tmp
& PIPE_MISC_OUTPUT_COLORSPACE_YUV
) {
2940 return INTEL_OUTPUT_FORMAT_YCBCR444
;
2942 return INTEL_OUTPUT_FORMAT_RGB
;
2946 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
2947 struct intel_crtc_state
*pipe_config
)
2949 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2950 enum intel_display_power_domain power_domain
;
2951 intel_wakeref_t wakeref
;
2955 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
2956 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
2960 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
2961 pipe_config
->sink_format
= pipe_config
->output_format
;
2962 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
2963 pipe_config
->shared_dpll
= NULL
;
2967 tmp
= intel_de_read(dev_priv
, TRANSCONF(pipe_config
->cpu_transcoder
));
2968 if (!(tmp
& TRANSCONF_ENABLE
))
2971 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
2972 IS_CHERRYVIEW(dev_priv
)) {
2973 switch (tmp
& TRANSCONF_BPC_MASK
) {
2974 case TRANSCONF_BPC_6
:
2975 pipe_config
->pipe_bpp
= 18;
2977 case TRANSCONF_BPC_8
:
2978 pipe_config
->pipe_bpp
= 24;
2980 case TRANSCONF_BPC_10
:
2981 pipe_config
->pipe_bpp
= 30;
2989 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
2990 (tmp
& TRANSCONF_COLOR_RANGE_SELECT
))
2991 pipe_config
->limited_color_range
= true;
2993 pipe_config
->gamma_mode
= REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX
, tmp
);
2995 pipe_config
->framestart_delay
= REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK
, tmp
) + 1;
2997 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
2998 (tmp
& TRANSCONF_WGC_ENABLE
))
2999 pipe_config
->wgc_enable
= true;
3001 intel_color_get_config(pipe_config
);
3003 if (DISPLAY_VER(dev_priv
) < 4)
3004 pipe_config
->double_wide
= tmp
& TRANSCONF_DOUBLE_WIDE
;
3006 intel_get_transcoder_timings(crtc
, pipe_config
);
3007 intel_get_pipe_src_size(crtc
, pipe_config
);
3009 i9xx_get_pfit_config(pipe_config
);
3011 if (DISPLAY_VER(dev_priv
) >= 4) {
3012 /* No way to read it out on pipes B and C */
3013 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
3014 tmp
= dev_priv
->display
.state
.chv_dpll_md
[crtc
->pipe
];
3016 tmp
= intel_de_read(dev_priv
, DPLL_MD(crtc
->pipe
));
3017 pipe_config
->pixel_multiplier
=
3018 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
3019 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
3020 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
3021 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
3022 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
3023 tmp
= intel_de_read(dev_priv
, DPLL(crtc
->pipe
));
3024 pipe_config
->pixel_multiplier
=
3025 ((tmp
& SDVO_MULTIPLIER_MASK
)
3026 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
3028 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3029 * port and will be fixed up in the encoder->get_config
3031 pipe_config
->pixel_multiplier
= 1;
3033 pipe_config
->dpll_hw_state
.dpll
= intel_de_read(dev_priv
,
3035 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
3036 pipe_config
->dpll_hw_state
.fp0
= intel_de_read(dev_priv
,
3038 pipe_config
->dpll_hw_state
.fp1
= intel_de_read(dev_priv
,
3041 /* Mask out read-only status bits. */
3042 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
3043 DPLL_PORTC_READY_MASK
|
3044 DPLL_PORTB_READY_MASK
);
3047 if (IS_CHERRYVIEW(dev_priv
))
3048 chv_crtc_clock_get(crtc
, pipe_config
);
3049 else if (IS_VALLEYVIEW(dev_priv
))
3050 vlv_crtc_clock_get(crtc
, pipe_config
);
3052 i9xx_crtc_clock_get(crtc
, pipe_config
);
3055 * Normally the dotclock is filled in by the encoder .get_config()
3056 * but in case the pipe is enabled w/o any ports we need a sane
3059 pipe_config
->hw
.adjusted_mode
.crtc_clock
=
3060 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
3065 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
3070 void ilk_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
3072 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3073 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3074 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
3078 * - During modeset the pipe is still disabled and must remain so
3079 * - During fastset the pipe is already enabled and must remain so
3081 if (!intel_crtc_needs_modeset(crtc_state
))
3082 val
|= TRANSCONF_ENABLE
;
3084 switch (crtc_state
->pipe_bpp
) {
3086 /* Case prevented by intel_choose_pipe_bpp_dither. */
3087 MISSING_CASE(crtc_state
->pipe_bpp
);
3090 val
|= TRANSCONF_BPC_6
;
3093 val
|= TRANSCONF_BPC_8
;
3096 val
|= TRANSCONF_BPC_10
;
3099 val
|= TRANSCONF_BPC_12
;
3103 if (crtc_state
->dither
)
3104 val
|= TRANSCONF_DITHER_EN
| TRANSCONF_DITHER_TYPE_SP
;
3106 if (crtc_state
->hw
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3107 val
|= TRANSCONF_INTERLACE_IF_ID_ILK
;
3109 val
|= TRANSCONF_INTERLACE_PF_PD_ILK
;
3112 * This would end up with an odd purple hue over
3113 * the entire display. Make sure we don't do it.
3115 drm_WARN_ON(&dev_priv
->drm
, crtc_state
->limited_color_range
&&
3116 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
);
3118 if (crtc_state
->limited_color_range
&&
3119 !intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
3120 val
|= TRANSCONF_COLOR_RANGE_SELECT
;
3122 if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
)
3123 val
|= TRANSCONF_OUTPUT_COLORSPACE_YUV709
;
3125 val
|= TRANSCONF_GAMMA_MODE(crtc_state
->gamma_mode
);
3127 val
|= TRANSCONF_FRAME_START_DELAY(crtc_state
->framestart_delay
- 1);
3128 val
|= TRANSCONF_MSA_TIMING_DELAY(crtc_state
->msa_timing_delay
);
3130 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
), val
);
3131 intel_de_posting_read(dev_priv
, TRANSCONF(cpu_transcoder
));
3134 static void hsw_set_transconf(const struct intel_crtc_state
*crtc_state
)
3136 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3137 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3138 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
3142 * - During modeset the pipe is still disabled and must remain so
3143 * - During fastset the pipe is already enabled and must remain so
3145 if (!intel_crtc_needs_modeset(crtc_state
))
3146 val
|= TRANSCONF_ENABLE
;
3148 if (IS_HASWELL(dev_priv
) && crtc_state
->dither
)
3149 val
|= TRANSCONF_DITHER_EN
| TRANSCONF_DITHER_TYPE_SP
;
3151 if (crtc_state
->hw
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3152 val
|= TRANSCONF_INTERLACE_IF_ID_ILK
;
3154 val
|= TRANSCONF_INTERLACE_PF_PD_ILK
;
3156 if (IS_HASWELL(dev_priv
) &&
3157 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
)
3158 val
|= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW
;
3160 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
), val
);
3161 intel_de_posting_read(dev_priv
, TRANSCONF(cpu_transcoder
));
3164 static void bdw_set_pipe_misc(const struct intel_crtc_state
*crtc_state
)
3166 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3167 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3170 switch (crtc_state
->pipe_bpp
) {
3172 val
|= PIPE_MISC_BPC_6
;
3175 val
|= PIPE_MISC_BPC_8
;
3178 val
|= PIPE_MISC_BPC_10
;
3181 /* Port output 12BPC defined for ADLP+ */
3182 if (DISPLAY_VER(dev_priv
) >= 13)
3183 val
|= PIPE_MISC_BPC_12_ADLP
;
3186 MISSING_CASE(crtc_state
->pipe_bpp
);
3190 if (crtc_state
->dither
)
3191 val
|= PIPE_MISC_DITHER_ENABLE
| PIPE_MISC_DITHER_TYPE_SP
;
3193 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
3194 crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
)
3195 val
|= PIPE_MISC_OUTPUT_COLORSPACE_YUV
;
3197 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
3198 val
|= PIPE_MISC_YUV420_ENABLE
|
3199 PIPE_MISC_YUV420_MODE_FULL_BLEND
;
3201 if (DISPLAY_VER(dev_priv
) >= 11 && is_hdr_mode(crtc_state
))
3202 val
|= PIPE_MISC_HDR_MODE_PRECISION
;
3204 if (DISPLAY_VER(dev_priv
) >= 12)
3205 val
|= PIPE_MISC_PIXEL_ROUNDING_TRUNC
;
3207 /* allow PSR with sprite enabled */
3208 if (IS_BROADWELL(dev_priv
))
3209 val
|= PIPE_MISC_PSR_MASK_SPRITE_ENABLE
;
3211 intel_de_write(dev_priv
, PIPE_MISC(crtc
->pipe
), val
);
3214 int bdw_get_pipe_misc_bpp(struct intel_crtc
*crtc
)
3216 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3219 tmp
= intel_de_read(dev_priv
, PIPE_MISC(crtc
->pipe
));
3221 switch (tmp
& PIPE_MISC_BPC_MASK
) {
3222 case PIPE_MISC_BPC_6
:
3224 case PIPE_MISC_BPC_8
:
3226 case PIPE_MISC_BPC_10
:
3229 * PORT OUTPUT 12 BPC defined for ADLP+.
3232 * For previous platforms with DSI interface, bits 5:7
3233 * are used for storing pipe_bpp irrespective of dithering.
3234 * Since the value of 12 BPC is not defined for these bits
3235 * on older platforms, need to find a workaround for 12 BPC
3236 * MIPI DSI HW readout.
3238 case PIPE_MISC_BPC_12_ADLP
:
3239 if (DISPLAY_VER(dev_priv
) >= 13)
3248 int ilk_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
3251 * Account for spread spectrum to avoid
3252 * oversubscribing the link. Max center spread
3253 * is 2.5%; use 5% for safety's sake.
3255 u32 bps
= target_clock
* bpp
* 21 / 20;
3256 return DIV_ROUND_UP(bps
, link_bw
* 8);
3259 void intel_get_m_n(struct drm_i915_private
*i915
,
3260 struct intel_link_m_n
*m_n
,
3261 i915_reg_t data_m_reg
, i915_reg_t data_n_reg
,
3262 i915_reg_t link_m_reg
, i915_reg_t link_n_reg
)
3264 m_n
->link_m
= intel_de_read(i915
, link_m_reg
) & DATA_LINK_M_N_MASK
;
3265 m_n
->link_n
= intel_de_read(i915
, link_n_reg
) & DATA_LINK_M_N_MASK
;
3266 m_n
->data_m
= intel_de_read(i915
, data_m_reg
) & DATA_LINK_M_N_MASK
;
3267 m_n
->data_n
= intel_de_read(i915
, data_n_reg
) & DATA_LINK_M_N_MASK
;
3268 m_n
->tu
= REG_FIELD_GET(TU_SIZE_MASK
, intel_de_read(i915
, data_m_reg
)) + 1;
3271 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc
*crtc
,
3272 enum transcoder transcoder
,
3273 struct intel_link_m_n
*m_n
)
3275 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3276 enum pipe pipe
= crtc
->pipe
;
3278 if (DISPLAY_VER(dev_priv
) >= 5)
3279 intel_get_m_n(dev_priv
, m_n
,
3280 PIPE_DATA_M1(transcoder
), PIPE_DATA_N1(transcoder
),
3281 PIPE_LINK_M1(transcoder
), PIPE_LINK_N1(transcoder
));
3283 intel_get_m_n(dev_priv
, m_n
,
3284 PIPE_DATA_M_G4X(pipe
), PIPE_DATA_N_G4X(pipe
),
3285 PIPE_LINK_M_G4X(pipe
), PIPE_LINK_N_G4X(pipe
));
3288 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc
*crtc
,
3289 enum transcoder transcoder
,
3290 struct intel_link_m_n
*m_n
)
3292 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3294 if (!intel_cpu_transcoder_has_m2_n2(dev_priv
, transcoder
))
3297 intel_get_m_n(dev_priv
, m_n
,
3298 PIPE_DATA_M2(transcoder
), PIPE_DATA_N2(transcoder
),
3299 PIPE_LINK_M2(transcoder
), PIPE_LINK_N2(transcoder
));
3302 static void ilk_get_pfit_config(struct intel_crtc_state
*crtc_state
)
3304 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3305 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3309 ctl
= intel_de_read(dev_priv
, PF_CTL(crtc
->pipe
));
3310 if ((ctl
& PF_ENABLE
) == 0)
3313 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
3314 pipe
= REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB
, ctl
);
3318 crtc_state
->pch_pfit
.enabled
= true;
3320 pos
= intel_de_read(dev_priv
, PF_WIN_POS(crtc
->pipe
));
3321 size
= intel_de_read(dev_priv
, PF_WIN_SZ(crtc
->pipe
));
3323 drm_rect_init(&crtc_state
->pch_pfit
.dst
,
3324 REG_FIELD_GET(PF_WIN_XPOS_MASK
, pos
),
3325 REG_FIELD_GET(PF_WIN_YPOS_MASK
, pos
),
3326 REG_FIELD_GET(PF_WIN_XSIZE_MASK
, size
),
3327 REG_FIELD_GET(PF_WIN_YSIZE_MASK
, size
));
3330 * We currently do not free assignements of panel fitters on
3331 * ivb/hsw (since we don't use the higher upscaling modes which
3332 * differentiates them) so just WARN about this case for now.
3334 drm_WARN_ON(&dev_priv
->drm
, pipe
!= crtc
->pipe
);
3337 static bool ilk_get_pipe_config(struct intel_crtc
*crtc
,
3338 struct intel_crtc_state
*pipe_config
)
3340 struct drm_device
*dev
= crtc
->base
.dev
;
3341 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3342 enum intel_display_power_domain power_domain
;
3343 intel_wakeref_t wakeref
;
3347 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
3348 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
3352 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
3353 pipe_config
->shared_dpll
= NULL
;
3356 tmp
= intel_de_read(dev_priv
, TRANSCONF(pipe_config
->cpu_transcoder
));
3357 if (!(tmp
& TRANSCONF_ENABLE
))
3360 switch (tmp
& TRANSCONF_BPC_MASK
) {
3361 case TRANSCONF_BPC_6
:
3362 pipe_config
->pipe_bpp
= 18;
3364 case TRANSCONF_BPC_8
:
3365 pipe_config
->pipe_bpp
= 24;
3367 case TRANSCONF_BPC_10
:
3368 pipe_config
->pipe_bpp
= 30;
3370 case TRANSCONF_BPC_12
:
3371 pipe_config
->pipe_bpp
= 36;
3377 if (tmp
& TRANSCONF_COLOR_RANGE_SELECT
)
3378 pipe_config
->limited_color_range
= true;
3380 switch (tmp
& TRANSCONF_OUTPUT_COLORSPACE_MASK
) {
3381 case TRANSCONF_OUTPUT_COLORSPACE_YUV601
:
3382 case TRANSCONF_OUTPUT_COLORSPACE_YUV709
:
3383 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_YCBCR444
;
3386 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
3390 pipe_config
->sink_format
= pipe_config
->output_format
;
3392 pipe_config
->gamma_mode
= REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK
, tmp
);
3394 pipe_config
->framestart_delay
= REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK
, tmp
) + 1;
3396 pipe_config
->msa_timing_delay
= REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK
, tmp
);
3398 intel_color_get_config(pipe_config
);
3400 pipe_config
->pixel_multiplier
= 1;
3402 ilk_pch_get_config(pipe_config
);
3404 intel_get_transcoder_timings(crtc
, pipe_config
);
3405 intel_get_pipe_src_size(crtc
, pipe_config
);
3407 ilk_get_pfit_config(pipe_config
);
3412 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
3417 static u8
bigjoiner_pipes(struct drm_i915_private
*i915
)
3421 if (DISPLAY_VER(i915
) >= 12)
3422 pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
) | BIT(PIPE_D
);
3423 else if (DISPLAY_VER(i915
) >= 11)
3424 pipes
= BIT(PIPE_B
) | BIT(PIPE_C
);
3428 return pipes
& DISPLAY_RUNTIME_INFO(i915
)->pipe_mask
;
3431 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private
*dev_priv
,
3432 enum transcoder cpu_transcoder
)
3434 enum intel_display_power_domain power_domain
;
3435 intel_wakeref_t wakeref
;
3438 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
3440 with_intel_display_power_if_enabled(dev_priv
, power_domain
, wakeref
)
3441 tmp
= intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(cpu_transcoder
));
3443 return tmp
& TRANS_DDI_FUNC_ENABLE
;
3446 static void enabled_bigjoiner_pipes(struct drm_i915_private
*dev_priv
,
3447 u8
*master_pipes
, u8
*slave_pipes
)
3449 struct intel_crtc
*crtc
;
3454 for_each_intel_crtc_in_pipe_mask(&dev_priv
->drm
, crtc
,
3455 bigjoiner_pipes(dev_priv
)) {
3456 enum intel_display_power_domain power_domain
;
3457 enum pipe pipe
= crtc
->pipe
;
3458 intel_wakeref_t wakeref
;
3460 power_domain
= intel_dsc_power_domain(crtc
, (enum transcoder
) pipe
);
3461 with_intel_display_power_if_enabled(dev_priv
, power_domain
, wakeref
) {
3462 u32 tmp
= intel_de_read(dev_priv
, ICL_PIPE_DSS_CTL1(pipe
));
3464 if (!(tmp
& BIG_JOINER_ENABLE
))
3467 if (tmp
& MASTER_BIG_JOINER_ENABLE
)
3468 *master_pipes
|= BIT(pipe
);
3470 *slave_pipes
|= BIT(pipe
);
3473 if (DISPLAY_VER(dev_priv
) < 13)
3476 power_domain
= POWER_DOMAIN_PIPE(pipe
);
3477 with_intel_display_power_if_enabled(dev_priv
, power_domain
, wakeref
) {
3478 u32 tmp
= intel_de_read(dev_priv
, ICL_PIPE_DSS_CTL1(pipe
));
3480 if (tmp
& UNCOMPRESSED_JOINER_MASTER
)
3481 *master_pipes
|= BIT(pipe
);
3482 if (tmp
& UNCOMPRESSED_JOINER_SLAVE
)
3483 *slave_pipes
|= BIT(pipe
);
3487 /* Bigjoiner pipes should always be consecutive master and slave */
3488 drm_WARN(&dev_priv
->drm
, *slave_pipes
!= *master_pipes
<< 1,
3489 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3490 *master_pipes
, *slave_pipes
);
3493 static enum pipe
get_bigjoiner_master_pipe(enum pipe pipe
, u8 master_pipes
, u8 slave_pipes
)
3495 if ((slave_pipes
& BIT(pipe
)) == 0)
3498 /* ignore everything above our pipe */
3499 master_pipes
&= ~GENMASK(7, pipe
);
3501 /* highest remaining bit should be our master pipe */
3502 return fls(master_pipes
) - 1;
3505 static u8
get_bigjoiner_slave_pipes(enum pipe pipe
, u8 master_pipes
, u8 slave_pipes
)
3507 enum pipe master_pipe
, next_master_pipe
;
3509 master_pipe
= get_bigjoiner_master_pipe(pipe
, master_pipes
, slave_pipes
);
3511 if ((master_pipes
& BIT(master_pipe
)) == 0)
3514 /* ignore our master pipe and everything below it */
3515 master_pipes
&= ~GENMASK(master_pipe
, 0);
3516 /* make sure a high bit is set for the ffs() */
3517 master_pipes
|= BIT(7);
3518 /* lowest remaining bit should be the next master pipe */
3519 next_master_pipe
= ffs(master_pipes
) - 1;
3521 return slave_pipes
& GENMASK(next_master_pipe
- 1, master_pipe
);
3524 static u8
hsw_panel_transcoders(struct drm_i915_private
*i915
)
3526 u8 panel_transcoder_mask
= BIT(TRANSCODER_EDP
);
3528 if (DISPLAY_VER(i915
) >= 11)
3529 panel_transcoder_mask
|= BIT(TRANSCODER_DSI_0
) | BIT(TRANSCODER_DSI_1
);
3531 return panel_transcoder_mask
;
3534 static u8
hsw_enabled_transcoders(struct intel_crtc
*crtc
)
3536 struct drm_device
*dev
= crtc
->base
.dev
;
3537 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3538 u8 panel_transcoder_mask
= hsw_panel_transcoders(dev_priv
);
3539 enum transcoder cpu_transcoder
;
3540 u8 master_pipes
, slave_pipes
;
3541 u8 enabled_transcoders
= 0;
3544 * XXX: Do intel_display_power_get_if_enabled before reading this (for
3545 * consistency and less surprising code; it's in always on power).
3547 for_each_cpu_transcoder_masked(dev_priv
, cpu_transcoder
,
3548 panel_transcoder_mask
) {
3549 enum intel_display_power_domain power_domain
;
3550 intel_wakeref_t wakeref
;
3551 enum pipe trans_pipe
;
3554 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
3555 with_intel_display_power_if_enabled(dev_priv
, power_domain
, wakeref
)
3556 tmp
= intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(cpu_transcoder
));
3558 if (!(tmp
& TRANS_DDI_FUNC_ENABLE
))
3561 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
3564 "unknown pipe linked to transcoder %s\n",
3565 transcoder_name(cpu_transcoder
));
3567 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
3568 case TRANS_DDI_EDP_INPUT_A_ON
:
3569 trans_pipe
= PIPE_A
;
3571 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
3572 trans_pipe
= PIPE_B
;
3574 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
3575 trans_pipe
= PIPE_C
;
3577 case TRANS_DDI_EDP_INPUT_D_ONOFF
:
3578 trans_pipe
= PIPE_D
;
3582 if (trans_pipe
== crtc
->pipe
)
3583 enabled_transcoders
|= BIT(cpu_transcoder
);
3586 /* single pipe or bigjoiner master */
3587 cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
3588 if (transcoder_ddi_func_is_enabled(dev_priv
, cpu_transcoder
))
3589 enabled_transcoders
|= BIT(cpu_transcoder
);
3591 /* bigjoiner slave -> consider the master pipe's transcoder as well */
3592 enabled_bigjoiner_pipes(dev_priv
, &master_pipes
, &slave_pipes
);
3593 if (slave_pipes
& BIT(crtc
->pipe
)) {
3594 cpu_transcoder
= (enum transcoder
)
3595 get_bigjoiner_master_pipe(crtc
->pipe
, master_pipes
, slave_pipes
);
3596 if (transcoder_ddi_func_is_enabled(dev_priv
, cpu_transcoder
))
3597 enabled_transcoders
|= BIT(cpu_transcoder
);
3600 return enabled_transcoders
;
3603 static bool has_edp_transcoders(u8 enabled_transcoders
)
3605 return enabled_transcoders
& BIT(TRANSCODER_EDP
);
3608 static bool has_dsi_transcoders(u8 enabled_transcoders
)
3610 return enabled_transcoders
& (BIT(TRANSCODER_DSI_0
) |
3611 BIT(TRANSCODER_DSI_1
));
3614 static bool has_pipe_transcoders(u8 enabled_transcoders
)
3616 return enabled_transcoders
& ~(BIT(TRANSCODER_EDP
) |
3617 BIT(TRANSCODER_DSI_0
) |
3618 BIT(TRANSCODER_DSI_1
));
3621 static void assert_enabled_transcoders(struct drm_i915_private
*i915
,
3622 u8 enabled_transcoders
)
3624 /* Only one type of transcoder please */
3625 drm_WARN_ON(&i915
->drm
,
3626 has_edp_transcoders(enabled_transcoders
) +
3627 has_dsi_transcoders(enabled_transcoders
) +
3628 has_pipe_transcoders(enabled_transcoders
) > 1);
3630 /* Only DSI transcoders can be ganged */
3631 drm_WARN_ON(&i915
->drm
,
3632 !has_dsi_transcoders(enabled_transcoders
) &&
3633 !is_power_of_2(enabled_transcoders
));
3636 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
3637 struct intel_crtc_state
*pipe_config
,
3638 struct intel_display_power_domain_set
*power_domain_set
)
3640 struct drm_device
*dev
= crtc
->base
.dev
;
3641 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3642 unsigned long enabled_transcoders
;
3645 enabled_transcoders
= hsw_enabled_transcoders(crtc
);
3646 if (!enabled_transcoders
)
3649 assert_enabled_transcoders(dev_priv
, enabled_transcoders
);
3652 * With the exception of DSI we should only ever have
3653 * a single enabled transcoder. With DSI let's just
3654 * pick the first one.
3656 pipe_config
->cpu_transcoder
= ffs(enabled_transcoders
) - 1;
3658 if (!intel_display_power_get_in_set_if_enabled(dev_priv
, power_domain_set
,
3659 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
3662 if (hsw_panel_transcoders(dev_priv
) & BIT(pipe_config
->cpu_transcoder
)) {
3663 tmp
= intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
3665 if ((tmp
& TRANS_DDI_EDP_INPUT_MASK
) == TRANS_DDI_EDP_INPUT_A_ONOFF
)
3666 pipe_config
->pch_pfit
.force_thru
= true;
3669 tmp
= intel_de_read(dev_priv
, TRANSCONF(pipe_config
->cpu_transcoder
));
3671 return tmp
& TRANSCONF_ENABLE
;
3674 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
3675 struct intel_crtc_state
*pipe_config
,
3676 struct intel_display_power_domain_set
*power_domain_set
)
3678 struct drm_device
*dev
= crtc
->base
.dev
;
3679 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3680 enum transcoder cpu_transcoder
;
3684 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
3686 cpu_transcoder
= TRANSCODER_DSI_A
;
3688 cpu_transcoder
= TRANSCODER_DSI_C
;
3690 if (!intel_display_power_get_in_set_if_enabled(dev_priv
, power_domain_set
,
3691 POWER_DOMAIN_TRANSCODER(cpu_transcoder
)))
3695 * The PLL needs to be enabled with a valid divider
3696 * configuration, otherwise accessing DSI registers will hang
3697 * the machine. See BSpec North Display Engine
3698 * registers/MIPI[BXT]. We can break out here early, since we
3699 * need the same DSI PLL to be enabled for both DSI ports.
3701 if (!bxt_dsi_pll_is_enabled(dev_priv
))
3704 /* XXX: this works for video mode only */
3705 tmp
= intel_de_read(dev_priv
, BXT_MIPI_PORT_CTRL(port
));
3706 if (!(tmp
& DPI_ENABLE
))
3709 tmp
= intel_de_read(dev_priv
, MIPI_CTRL(port
));
3710 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
3713 pipe_config
->cpu_transcoder
= cpu_transcoder
;
3717 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
3720 static void intel_bigjoiner_get_config(struct intel_crtc_state
*crtc_state
)
3722 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3723 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
3724 u8 master_pipes
, slave_pipes
;
3725 enum pipe pipe
= crtc
->pipe
;
3727 enabled_bigjoiner_pipes(i915
, &master_pipes
, &slave_pipes
);
3729 if (((master_pipes
| slave_pipes
) & BIT(pipe
)) == 0)
3732 crtc_state
->bigjoiner_pipes
=
3733 BIT(get_bigjoiner_master_pipe(pipe
, master_pipes
, slave_pipes
)) |
3734 get_bigjoiner_slave_pipes(pipe
, master_pipes
, slave_pipes
);
3737 static bool hsw_get_pipe_config(struct intel_crtc
*crtc
,
3738 struct intel_crtc_state
*pipe_config
)
3740 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3744 if (!intel_display_power_get_in_set_if_enabled(dev_priv
, &crtc
->hw_readout_power_domains
,
3745 POWER_DOMAIN_PIPE(crtc
->pipe
)))
3748 pipe_config
->shared_dpll
= NULL
;
3750 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &crtc
->hw_readout_power_domains
);
3752 if ((IS_GEMINILAKE(dev_priv
) || IS_BROXTON(dev_priv
)) &&
3753 bxt_get_dsi_transcoder_state(crtc
, pipe_config
, &crtc
->hw_readout_power_domains
)) {
3754 drm_WARN_ON(&dev_priv
->drm
, active
);
3761 intel_bigjoiner_get_config(pipe_config
);
3762 intel_dsc_get_config(pipe_config
);
3764 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
) ||
3765 DISPLAY_VER(dev_priv
) >= 11)
3766 intel_get_transcoder_timings(crtc
, pipe_config
);
3768 if (HAS_VRR(dev_priv
) && !transcoder_is_dsi(pipe_config
->cpu_transcoder
))
3769 intel_vrr_get_config(pipe_config
);
3771 intel_get_pipe_src_size(crtc
, pipe_config
);
3773 if (IS_HASWELL(dev_priv
)) {
3774 u32 tmp
= intel_de_read(dev_priv
,
3775 TRANSCONF(pipe_config
->cpu_transcoder
));
3777 if (tmp
& TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW
)
3778 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_YCBCR444
;
3780 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
3782 pipe_config
->output_format
=
3783 bdw_get_pipe_misc_output_format(crtc
);
3786 pipe_config
->sink_format
= pipe_config
->output_format
;
3788 intel_color_get_config(pipe_config
);
3790 tmp
= intel_de_read(dev_priv
, WM_LINETIME(crtc
->pipe
));
3791 pipe_config
->linetime
= REG_FIELD_GET(HSW_LINETIME_MASK
, tmp
);
3792 if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
3793 pipe_config
->ips_linetime
=
3794 REG_FIELD_GET(HSW_IPS_LINETIME_MASK
, tmp
);
3796 if (intel_display_power_get_in_set_if_enabled(dev_priv
, &crtc
->hw_readout_power_domains
,
3797 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
))) {
3798 if (DISPLAY_VER(dev_priv
) >= 9)
3799 skl_scaler_get_config(pipe_config
);
3801 ilk_get_pfit_config(pipe_config
);
3804 hsw_ips_get_config(pipe_config
);
3806 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
3807 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
3808 pipe_config
->pixel_multiplier
=
3809 intel_de_read(dev_priv
,
3810 TRANS_MULT(pipe_config
->cpu_transcoder
)) + 1;
3812 pipe_config
->pixel_multiplier
= 1;
3815 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
3816 tmp
= intel_de_read(dev_priv
, hsw_chicken_trans_reg(dev_priv
, pipe_config
->cpu_transcoder
));
3818 pipe_config
->framestart_delay
= REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK
, tmp
) + 1;
3820 /* no idea if this is correct */
3821 pipe_config
->framestart_delay
= 1;
3825 intel_display_power_put_all_in_set(dev_priv
, &crtc
->hw_readout_power_domains
);
3830 bool intel_crtc_get_pipe_config(struct intel_crtc_state
*crtc_state
)
3832 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3833 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
3835 if (!i915
->display
.funcs
.display
->get_pipe_config(crtc
, crtc_state
))
3838 crtc_state
->hw
.active
= true;
3840 intel_crtc_readout_derived_state(crtc_state
);
3845 int intel_dotclock_calculate(int link_freq
,
3846 const struct intel_link_m_n
*m_n
)
3849 * The calculation for the data clock -> pixel clock is:
3850 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
3851 * But we want to avoid losing precison if possible, so:
3852 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
3854 * and for link freq (10kbs units) -> pixel clock it is:
3855 * link_symbol_clock = link_freq * 10 / link_symbol_size
3856 * pixel_clock = (m * link_symbol_clock) / n
3857 * or for more precision:
3858 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
3864 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n
->link_m
, link_freq
* 10),
3865 m_n
->link_n
* intel_dp_link_symbol_size(link_freq
));
3868 int intel_crtc_dotclock(const struct intel_crtc_state
*pipe_config
)
3872 if (intel_crtc_has_dp_encoder(pipe_config
))
3873 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
3874 &pipe_config
->dp_m_n
);
3875 else if (pipe_config
->has_hdmi_sink
&& pipe_config
->pipe_bpp
> 24)
3876 dotclock
= DIV_ROUND_CLOSEST(pipe_config
->port_clock
* 24,
3877 pipe_config
->pipe_bpp
);
3879 dotclock
= pipe_config
->port_clock
;
3881 if (pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
&&
3882 !intel_crtc_has_dp_encoder(pipe_config
))
3885 if (pipe_config
->pixel_multiplier
)
3886 dotclock
/= pipe_config
->pixel_multiplier
;
3891 /* Returns the currently programmed mode of the given encoder. */
3892 struct drm_display_mode
*
3893 intel_encoder_current_mode(struct intel_encoder
*encoder
)
3895 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3896 struct intel_crtc_state
*crtc_state
;
3897 struct drm_display_mode
*mode
;
3898 struct intel_crtc
*crtc
;
3901 if (!encoder
->get_hw_state(encoder
, &pipe
))
3904 crtc
= intel_crtc_for_pipe(dev_priv
, pipe
);
3906 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
3910 crtc_state
= intel_crtc_state_alloc(crtc
);
3916 if (!intel_crtc_get_pipe_config(crtc_state
)) {
3917 intel_crtc_destroy_state(&crtc
->base
, &crtc_state
->uapi
);
3922 intel_encoder_get_config(encoder
, crtc_state
);
3924 intel_mode_from_crtc_timings(mode
, &crtc_state
->hw
.adjusted_mode
);
3926 intel_crtc_destroy_state(&crtc
->base
, &crtc_state
->uapi
);
3931 static bool encoders_cloneable(const struct intel_encoder
*a
,
3932 const struct intel_encoder
*b
)
3934 /* masks could be asymmetric, so check both ways */
3935 return a
== b
|| (a
->cloneable
& BIT(b
->type
) &&
3936 b
->cloneable
& BIT(a
->type
));
3939 static bool check_single_encoder_cloning(struct intel_atomic_state
*state
,
3940 struct intel_crtc
*crtc
,
3941 struct intel_encoder
*encoder
)
3943 struct intel_encoder
*source_encoder
;
3944 struct drm_connector
*connector
;
3945 struct drm_connector_state
*connector_state
;
3948 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
3949 if (connector_state
->crtc
!= &crtc
->base
)
3953 to_intel_encoder(connector_state
->best_encoder
);
3954 if (!encoders_cloneable(encoder
, source_encoder
))
3961 static int icl_add_linked_planes(struct intel_atomic_state
*state
)
3963 struct intel_plane
*plane
, *linked
;
3964 struct intel_plane_state
*plane_state
, *linked_plane_state
;
3967 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
3968 linked
= plane_state
->planar_linked_plane
;
3973 linked_plane_state
= intel_atomic_get_plane_state(state
, linked
);
3974 if (IS_ERR(linked_plane_state
))
3975 return PTR_ERR(linked_plane_state
);
3977 drm_WARN_ON(state
->base
.dev
,
3978 linked_plane_state
->planar_linked_plane
!= plane
);
3979 drm_WARN_ON(state
->base
.dev
,
3980 linked_plane_state
->planar_slave
== plane_state
->planar_slave
);
3986 static int icl_check_nv12_planes(struct intel_crtc_state
*crtc_state
)
3988 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3989 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3990 struct intel_atomic_state
*state
= to_intel_atomic_state(crtc_state
->uapi
.state
);
3991 struct intel_plane
*plane
, *linked
;
3992 struct intel_plane_state
*plane_state
;
3995 if (DISPLAY_VER(dev_priv
) < 11)
3999 * Destroy all old plane links and make the slave plane invisible
4000 * in the crtc_state->active_planes mask.
4002 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
4003 if (plane
->pipe
!= crtc
->pipe
|| !plane_state
->planar_linked_plane
)
4006 plane_state
->planar_linked_plane
= NULL
;
4007 if (plane_state
->planar_slave
&& !plane_state
->uapi
.visible
) {
4008 crtc_state
->enabled_planes
&= ~BIT(plane
->id
);
4009 crtc_state
->active_planes
&= ~BIT(plane
->id
);
4010 crtc_state
->update_planes
|= BIT(plane
->id
);
4011 crtc_state
->data_rate
[plane
->id
] = 0;
4012 crtc_state
->rel_data_rate
[plane
->id
] = 0;
4015 plane_state
->planar_slave
= false;
4018 if (!crtc_state
->nv12_planes
)
4021 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
4022 struct intel_plane_state
*linked_state
= NULL
;
4024 if (plane
->pipe
!= crtc
->pipe
||
4025 !(crtc_state
->nv12_planes
& BIT(plane
->id
)))
4028 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, linked
) {
4029 if (!icl_is_nv12_y_plane(dev_priv
, linked
->id
))
4032 if (crtc_state
->active_planes
& BIT(linked
->id
))
4035 linked_state
= intel_atomic_get_plane_state(state
, linked
);
4036 if (IS_ERR(linked_state
))
4037 return PTR_ERR(linked_state
);
4042 if (!linked_state
) {
4043 drm_dbg_kms(&dev_priv
->drm
,
4044 "Need %d free Y planes for planar YUV\n",
4045 hweight8(crtc_state
->nv12_planes
));
4050 plane_state
->planar_linked_plane
= linked
;
4052 linked_state
->planar_slave
= true;
4053 linked_state
->planar_linked_plane
= plane
;
4054 crtc_state
->enabled_planes
|= BIT(linked
->id
);
4055 crtc_state
->active_planes
|= BIT(linked
->id
);
4056 crtc_state
->update_planes
|= BIT(linked
->id
);
4057 crtc_state
->data_rate
[linked
->id
] =
4058 crtc_state
->data_rate_y
[plane
->id
];
4059 crtc_state
->rel_data_rate
[linked
->id
] =
4060 crtc_state
->rel_data_rate_y
[plane
->id
];
4061 drm_dbg_kms(&dev_priv
->drm
, "Using %s as Y plane for %s\n",
4062 linked
->base
.name
, plane
->base
.name
);
4064 /* Copy parameters to slave plane */
4065 linked_state
->ctl
= plane_state
->ctl
| PLANE_CTL_YUV420_Y_PLANE
;
4066 linked_state
->color_ctl
= plane_state
->color_ctl
;
4067 linked_state
->view
= plane_state
->view
;
4068 linked_state
->decrypt
= plane_state
->decrypt
;
4070 intel_plane_copy_hw_state(linked_state
, plane_state
);
4071 linked_state
->uapi
.src
= plane_state
->uapi
.src
;
4072 linked_state
->uapi
.dst
= plane_state
->uapi
.dst
;
4074 if (icl_is_hdr_plane(dev_priv
, plane
->id
)) {
4075 if (linked
->id
== PLANE_SPRITE5
)
4076 plane_state
->cus_ctl
|= PLANE_CUS_Y_PLANE_7_ICL
;
4077 else if (linked
->id
== PLANE_SPRITE4
)
4078 plane_state
->cus_ctl
|= PLANE_CUS_Y_PLANE_6_ICL
;
4079 else if (linked
->id
== PLANE_SPRITE3
)
4080 plane_state
->cus_ctl
|= PLANE_CUS_Y_PLANE_5_RKL
;
4081 else if (linked
->id
== PLANE_SPRITE2
)
4082 plane_state
->cus_ctl
|= PLANE_CUS_Y_PLANE_4_RKL
;
4084 MISSING_CASE(linked
->id
);
4091 static bool c8_planes_changed(const struct intel_crtc_state
*new_crtc_state
)
4093 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
4094 struct intel_atomic_state
*state
=
4095 to_intel_atomic_state(new_crtc_state
->uapi
.state
);
4096 const struct intel_crtc_state
*old_crtc_state
=
4097 intel_atomic_get_old_crtc_state(state
, crtc
);
4099 return !old_crtc_state
->c8_planes
!= !new_crtc_state
->c8_planes
;
4102 static u16
hsw_linetime_wm(const struct intel_crtc_state
*crtc_state
)
4104 const struct drm_display_mode
*pipe_mode
=
4105 &crtc_state
->hw
.pipe_mode
;
4108 if (!crtc_state
->hw
.enable
)
4111 linetime_wm
= DIV_ROUND_CLOSEST(pipe_mode
->crtc_htotal
* 1000 * 8,
4112 pipe_mode
->crtc_clock
);
4114 return min(linetime_wm
, 0x1ff);
4117 static u16
hsw_ips_linetime_wm(const struct intel_crtc_state
*crtc_state
,
4118 const struct intel_cdclk_state
*cdclk_state
)
4120 const struct drm_display_mode
*pipe_mode
=
4121 &crtc_state
->hw
.pipe_mode
;
4124 if (!crtc_state
->hw
.enable
)
4127 linetime_wm
= DIV_ROUND_CLOSEST(pipe_mode
->crtc_htotal
* 1000 * 8,
4128 cdclk_state
->logical
.cdclk
);
4130 return min(linetime_wm
, 0x1ff);
4133 static u16
skl_linetime_wm(const struct intel_crtc_state
*crtc_state
)
4135 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
4136 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4137 const struct drm_display_mode
*pipe_mode
=
4138 &crtc_state
->hw
.pipe_mode
;
4141 if (!crtc_state
->hw
.enable
)
4144 linetime_wm
= DIV_ROUND_UP(pipe_mode
->crtc_htotal
* 1000 * 8,
4145 crtc_state
->pixel_rate
);
4147 /* Display WA #1135: BXT:ALL GLK:ALL */
4148 if ((IS_GEMINILAKE(dev_priv
) || IS_BROXTON(dev_priv
)) &&
4149 skl_watermark_ipc_enabled(dev_priv
))
4152 return min(linetime_wm
, 0x1ff);
4155 static int hsw_compute_linetime_wm(struct intel_atomic_state
*state
,
4156 struct intel_crtc
*crtc
)
4158 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4159 struct intel_crtc_state
*crtc_state
=
4160 intel_atomic_get_new_crtc_state(state
, crtc
);
4161 const struct intel_cdclk_state
*cdclk_state
;
4163 if (DISPLAY_VER(dev_priv
) >= 9)
4164 crtc_state
->linetime
= skl_linetime_wm(crtc_state
);
4166 crtc_state
->linetime
= hsw_linetime_wm(crtc_state
);
4168 if (!hsw_crtc_supports_ips(crtc
))
4171 cdclk_state
= intel_atomic_get_cdclk_state(state
);
4172 if (IS_ERR(cdclk_state
))
4173 return PTR_ERR(cdclk_state
);
4175 crtc_state
->ips_linetime
= hsw_ips_linetime_wm(crtc_state
,
4181 static int intel_crtc_atomic_check(struct intel_atomic_state
*state
,
4182 struct intel_crtc
*crtc
)
4184 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4185 struct intel_crtc_state
*crtc_state
=
4186 intel_atomic_get_new_crtc_state(state
, crtc
);
4189 if (DISPLAY_VER(dev_priv
) < 5 && !IS_G4X(dev_priv
) &&
4190 intel_crtc_needs_modeset(crtc_state
) &&
4191 !crtc_state
->hw
.active
)
4192 crtc_state
->update_wm_post
= true;
4194 if (intel_crtc_needs_modeset(crtc_state
)) {
4195 ret
= intel_dpll_crtc_get_shared_dpll(state
, crtc
);
4201 * May need to update pipe gamma enable bits
4202 * when C8 planes are getting enabled/disabled.
4204 if (c8_planes_changed(crtc_state
))
4205 crtc_state
->uapi
.color_mgmt_changed
= true;
4207 if (intel_crtc_needs_color_update(crtc_state
)) {
4208 ret
= intel_color_check(crtc_state
);
4213 ret
= intel_compute_pipe_wm(state
, crtc
);
4215 drm_dbg_kms(&dev_priv
->drm
,
4216 "Target pipe watermarks are invalid\n");
4221 * Calculate 'intermediate' watermarks that satisfy both the
4222 * old state and the new state. We can program these
4225 ret
= intel_compute_intermediate_wm(state
, crtc
);
4227 drm_dbg_kms(&dev_priv
->drm
,
4228 "No valid intermediate pipe watermarks are possible\n");
4232 if (DISPLAY_VER(dev_priv
) >= 9) {
4233 if (intel_crtc_needs_modeset(crtc_state
) ||
4234 intel_crtc_needs_fastset(crtc_state
)) {
4235 ret
= skl_update_scaler_crtc(crtc_state
);
4240 ret
= intel_atomic_setup_scalers(dev_priv
, crtc
, crtc_state
);
4245 if (HAS_IPS(dev_priv
)) {
4246 ret
= hsw_ips_compute_config(state
, crtc
);
4251 if (DISPLAY_VER(dev_priv
) >= 9 ||
4252 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
)) {
4253 ret
= hsw_compute_linetime_wm(state
, crtc
);
4259 ret
= intel_psr2_sel_fetch_update(state
, crtc
);
4267 compute_sink_pipe_bpp(const struct drm_connector_state
*conn_state
,
4268 struct intel_crtc_state
*crtc_state
)
4270 struct drm_connector
*connector
= conn_state
->connector
;
4271 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
4272 const struct drm_display_info
*info
= &connector
->display_info
;
4275 switch (conn_state
->max_bpc
) {
4289 MISSING_CASE(conn_state
->max_bpc
);
4293 if (bpp
< crtc_state
->pipe_bpp
) {
4294 drm_dbg_kms(&i915
->drm
,
4295 "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4296 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4297 connector
->base
.id
, connector
->name
,
4299 3 * conn_state
->max_requested_bpc
,
4300 crtc_state
->pipe_bpp
);
4302 crtc_state
->pipe_bpp
= bpp
;
4309 compute_baseline_pipe_bpp(struct intel_atomic_state
*state
,
4310 struct intel_crtc
*crtc
)
4312 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4313 struct intel_crtc_state
*crtc_state
=
4314 intel_atomic_get_new_crtc_state(state
, crtc
);
4315 struct drm_connector
*connector
;
4316 struct drm_connector_state
*connector_state
;
4319 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
4320 IS_CHERRYVIEW(dev_priv
)))
4322 else if (DISPLAY_VER(dev_priv
) >= 5)
4327 crtc_state
->pipe_bpp
= bpp
;
4329 /* Clamp display bpp to connector max bpp */
4330 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
4333 if (connector_state
->crtc
!= &crtc
->base
)
4336 ret
= compute_sink_pipe_bpp(connector_state
, crtc_state
);
4344 static bool check_digital_port_conflicts(struct intel_atomic_state
*state
)
4346 struct drm_device
*dev
= state
->base
.dev
;
4347 struct drm_connector
*connector
;
4348 struct drm_connector_list_iter conn_iter
;
4349 unsigned int used_ports
= 0;
4350 unsigned int used_mst_ports
= 0;
4354 * We're going to peek into connector->state,
4355 * hence connection_mutex must be held.
4357 drm_modeset_lock_assert_held(&dev
->mode_config
.connection_mutex
);
4360 * Walk the connector list instead of the encoder
4361 * list to detect the problem on ddi platforms
4362 * where there's just one encoder per digital port.
4364 drm_connector_list_iter_begin(dev
, &conn_iter
);
4365 drm_for_each_connector_iter(connector
, &conn_iter
) {
4366 struct drm_connector_state
*connector_state
;
4367 struct intel_encoder
*encoder
;
4370 drm_atomic_get_new_connector_state(&state
->base
,
4372 if (!connector_state
)
4373 connector_state
= connector
->state
;
4375 if (!connector_state
->best_encoder
)
4378 encoder
= to_intel_encoder(connector_state
->best_encoder
);
4380 drm_WARN_ON(dev
, !connector_state
->crtc
);
4382 switch (encoder
->type
) {
4383 case INTEL_OUTPUT_DDI
:
4384 if (drm_WARN_ON(dev
, !HAS_DDI(to_i915(dev
))))
4387 case INTEL_OUTPUT_DP
:
4388 case INTEL_OUTPUT_HDMI
:
4389 case INTEL_OUTPUT_EDP
:
4390 /* the same port mustn't appear more than once */
4391 if (used_ports
& BIT(encoder
->port
))
4394 used_ports
|= BIT(encoder
->port
);
4396 case INTEL_OUTPUT_DP_MST
:
4404 drm_connector_list_iter_end(&conn_iter
);
4406 /* can't mix MST and SST/HDMI on the same port */
4407 if (used_ports
& used_mst_ports
)
4414 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state
*state
,
4415 struct intel_crtc
*crtc
)
4417 struct intel_crtc_state
*crtc_state
=
4418 intel_atomic_get_new_crtc_state(state
, crtc
);
4420 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state
));
4422 drm_property_replace_blob(&crtc_state
->hw
.degamma_lut
,
4423 crtc_state
->uapi
.degamma_lut
);
4424 drm_property_replace_blob(&crtc_state
->hw
.gamma_lut
,
4425 crtc_state
->uapi
.gamma_lut
);
4426 drm_property_replace_blob(&crtc_state
->hw
.ctm
,
4427 crtc_state
->uapi
.ctm
);
4431 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state
*state
,
4432 struct intel_crtc
*crtc
)
4434 struct intel_crtc_state
*crtc_state
=
4435 intel_atomic_get_new_crtc_state(state
, crtc
);
4437 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state
));
4439 crtc_state
->hw
.enable
= crtc_state
->uapi
.enable
;
4440 crtc_state
->hw
.active
= crtc_state
->uapi
.active
;
4441 drm_mode_copy(&crtc_state
->hw
.mode
,
4442 &crtc_state
->uapi
.mode
);
4443 drm_mode_copy(&crtc_state
->hw
.adjusted_mode
,
4444 &crtc_state
->uapi
.adjusted_mode
);
4445 crtc_state
->hw
.scaling_filter
= crtc_state
->uapi
.scaling_filter
;
4447 intel_crtc_copy_uapi_to_hw_state_nomodeset(state
, crtc
);
4451 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state
*state
,
4452 struct intel_crtc
*slave_crtc
)
4454 struct intel_crtc_state
*slave_crtc_state
=
4455 intel_atomic_get_new_crtc_state(state
, slave_crtc
);
4456 struct intel_crtc
*master_crtc
= intel_master_crtc(slave_crtc_state
);
4457 const struct intel_crtc_state
*master_crtc_state
=
4458 intel_atomic_get_new_crtc_state(state
, master_crtc
);
4460 drm_property_replace_blob(&slave_crtc_state
->hw
.degamma_lut
,
4461 master_crtc_state
->hw
.degamma_lut
);
4462 drm_property_replace_blob(&slave_crtc_state
->hw
.gamma_lut
,
4463 master_crtc_state
->hw
.gamma_lut
);
4464 drm_property_replace_blob(&slave_crtc_state
->hw
.ctm
,
4465 master_crtc_state
->hw
.ctm
);
4467 slave_crtc_state
->uapi
.color_mgmt_changed
= master_crtc_state
->uapi
.color_mgmt_changed
;
4471 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state
*state
,
4472 struct intel_crtc
*slave_crtc
)
4474 struct intel_crtc_state
*slave_crtc_state
=
4475 intel_atomic_get_new_crtc_state(state
, slave_crtc
);
4476 struct intel_crtc
*master_crtc
= intel_master_crtc(slave_crtc_state
);
4477 const struct intel_crtc_state
*master_crtc_state
=
4478 intel_atomic_get_new_crtc_state(state
, master_crtc
);
4479 struct intel_crtc_state
*saved_state
;
4481 WARN_ON(master_crtc_state
->bigjoiner_pipes
!=
4482 slave_crtc_state
->bigjoiner_pipes
);
4484 saved_state
= kmemdup(master_crtc_state
, sizeof(*saved_state
), GFP_KERNEL
);
4488 /* preserve some things from the slave's original crtc state */
4489 saved_state
->uapi
= slave_crtc_state
->uapi
;
4490 saved_state
->scaler_state
= slave_crtc_state
->scaler_state
;
4491 saved_state
->shared_dpll
= slave_crtc_state
->shared_dpll
;
4492 saved_state
->crc_enabled
= slave_crtc_state
->crc_enabled
;
4494 intel_crtc_free_hw_state(slave_crtc_state
);
4495 if (slave_crtc_state
->dp_tunnel_ref
.tunnel
)
4496 drm_dp_tunnel_ref_put(&slave_crtc_state
->dp_tunnel_ref
);
4497 memcpy(slave_crtc_state
, saved_state
, sizeof(*slave_crtc_state
));
4500 /* Re-init hw state */
4501 memset(&slave_crtc_state
->hw
, 0, sizeof(slave_crtc_state
->hw
));
4502 slave_crtc_state
->hw
.enable
= master_crtc_state
->hw
.enable
;
4503 slave_crtc_state
->hw
.active
= master_crtc_state
->hw
.active
;
4504 drm_mode_copy(&slave_crtc_state
->hw
.mode
,
4505 &master_crtc_state
->hw
.mode
);
4506 drm_mode_copy(&slave_crtc_state
->hw
.pipe_mode
,
4507 &master_crtc_state
->hw
.pipe_mode
);
4508 drm_mode_copy(&slave_crtc_state
->hw
.adjusted_mode
,
4509 &master_crtc_state
->hw
.adjusted_mode
);
4510 slave_crtc_state
->hw
.scaling_filter
= master_crtc_state
->hw
.scaling_filter
;
4512 if (master_crtc_state
->dp_tunnel_ref
.tunnel
)
4513 drm_dp_tunnel_ref_get(master_crtc_state
->dp_tunnel_ref
.tunnel
,
4514 &slave_crtc_state
->dp_tunnel_ref
);
4516 copy_bigjoiner_crtc_state_nomodeset(state
, slave_crtc
);
4518 slave_crtc_state
->uapi
.mode_changed
= master_crtc_state
->uapi
.mode_changed
;
4519 slave_crtc_state
->uapi
.connectors_changed
= master_crtc_state
->uapi
.connectors_changed
;
4520 slave_crtc_state
->uapi
.active_changed
= master_crtc_state
->uapi
.active_changed
;
4522 WARN_ON(master_crtc_state
->bigjoiner_pipes
!=
4523 slave_crtc_state
->bigjoiner_pipes
);
4529 intel_crtc_prepare_cleared_state(struct intel_atomic_state
*state
,
4530 struct intel_crtc
*crtc
)
4532 struct intel_crtc_state
*crtc_state
=
4533 intel_atomic_get_new_crtc_state(state
, crtc
);
4534 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4535 struct intel_crtc_state
*saved_state
;
4537 saved_state
= intel_crtc_state_alloc(crtc
);
4541 /* free the old crtc_state->hw members */
4542 intel_crtc_free_hw_state(crtc_state
);
4544 intel_dp_tunnel_atomic_clear_stream_bw(state
, crtc_state
);
4546 /* FIXME: before the switch to atomic started, a new pipe_config was
4547 * kzalloc'd. Code that depends on any field being zero should be
4548 * fixed, so that the crtc_state can be safely duplicated. For now,
4549 * only fields that are know to not cause problems are preserved. */
4551 saved_state
->uapi
= crtc_state
->uapi
;
4552 saved_state
->inherited
= crtc_state
->inherited
;
4553 saved_state
->scaler_state
= crtc_state
->scaler_state
;
4554 saved_state
->shared_dpll
= crtc_state
->shared_dpll
;
4555 saved_state
->dpll_hw_state
= crtc_state
->dpll_hw_state
;
4556 memcpy(saved_state
->icl_port_dplls
, crtc_state
->icl_port_dplls
,
4557 sizeof(saved_state
->icl_port_dplls
));
4558 saved_state
->crc_enabled
= crtc_state
->crc_enabled
;
4559 if (IS_G4X(dev_priv
) ||
4560 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4561 saved_state
->wm
= crtc_state
->wm
;
4563 memcpy(crtc_state
, saved_state
, sizeof(*crtc_state
));
4566 intel_crtc_copy_uapi_to_hw_state_modeset(state
, crtc
);
4572 intel_modeset_pipe_config(struct intel_atomic_state
*state
,
4573 struct intel_crtc
*crtc
,
4574 const struct intel_link_bw_limits
*limits
)
4576 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
4577 struct intel_crtc_state
*crtc_state
=
4578 intel_atomic_get_new_crtc_state(state
, crtc
);
4579 struct drm_connector
*connector
;
4580 struct drm_connector_state
*connector_state
;
4581 int pipe_src_w
, pipe_src_h
;
4582 int base_bpp
, ret
, i
;
4584 crtc_state
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
4586 crtc_state
->framestart_delay
= 1;
4589 * Sanitize sync polarity flags based on requested ones. If neither
4590 * positive or negative polarity is requested, treat this as meaning
4591 * negative polarity.
4593 if (!(crtc_state
->hw
.adjusted_mode
.flags
&
4594 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
4595 crtc_state
->hw
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
4597 if (!(crtc_state
->hw
.adjusted_mode
.flags
&
4598 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
4599 crtc_state
->hw
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
4601 ret
= compute_baseline_pipe_bpp(state
, crtc
);
4605 crtc_state
->fec_enable
= limits
->force_fec_pipes
& BIT(crtc
->pipe
);
4606 crtc_state
->max_link_bpp_x16
= limits
->max_bpp_x16
[crtc
->pipe
];
4608 if (crtc_state
->pipe_bpp
> to_bpp_int(crtc_state
->max_link_bpp_x16
)) {
4609 drm_dbg_kms(&i915
->drm
,
4610 "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT
"\n",
4611 crtc
->base
.base
.id
, crtc
->base
.name
,
4612 BPP_X16_ARGS(crtc_state
->max_link_bpp_x16
));
4613 crtc_state
->bw_constrained
= true;
4616 base_bpp
= crtc_state
->pipe_bpp
;
4619 * Determine the real pipe dimensions. Note that stereo modes can
4620 * increase the actual pipe size due to the frame doubling and
4621 * insertion of additional space for blanks between the frame. This
4622 * is stored in the crtc timings. We use the requested mode to do this
4623 * computation to clearly distinguish it from the adjusted mode, which
4624 * can be changed by the connectors in the below retry loop.
4626 drm_mode_get_hv_timing(&crtc_state
->hw
.mode
,
4627 &pipe_src_w
, &pipe_src_h
);
4628 drm_rect_init(&crtc_state
->pipe_src
, 0, 0,
4629 pipe_src_w
, pipe_src_h
);
4631 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
4632 struct intel_encoder
*encoder
=
4633 to_intel_encoder(connector_state
->best_encoder
);
4635 if (connector_state
->crtc
!= &crtc
->base
)
4638 if (!check_single_encoder_cloning(state
, crtc
, encoder
)) {
4639 drm_dbg_kms(&i915
->drm
,
4640 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4641 encoder
->base
.base
.id
, encoder
->base
.name
);
4646 * Determine output_types before calling the .compute_config()
4647 * hooks so that the hooks can use this information safely.
4649 if (encoder
->compute_output_type
)
4650 crtc_state
->output_types
|=
4651 BIT(encoder
->compute_output_type(encoder
, crtc_state
,
4654 crtc_state
->output_types
|= BIT(encoder
->type
);
4657 /* Ensure the port clock defaults are reset when retrying. */
4658 crtc_state
->port_clock
= 0;
4659 crtc_state
->pixel_multiplier
= 1;
4661 /* Fill in default crtc timings, allow encoders to overwrite them. */
4662 drm_mode_set_crtcinfo(&crtc_state
->hw
.adjusted_mode
,
4663 CRTC_STEREO_DOUBLE
);
4665 /* Pass our mode to the connectors and the CRTC to give them a chance to
4666 * adjust it according to limitations or connector properties, and also
4667 * a chance to reject the mode entirely.
4669 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
4670 struct intel_encoder
*encoder
=
4671 to_intel_encoder(connector_state
->best_encoder
);
4673 if (connector_state
->crtc
!= &crtc
->base
)
4676 ret
= encoder
->compute_config(encoder
, crtc_state
,
4678 if (ret
== -EDEADLK
)
4681 drm_dbg_kms(&i915
->drm
, "[ENCODER:%d:%s] config failure: %d\n",
4682 encoder
->base
.base
.id
, encoder
->base
.name
, ret
);
4687 /* Set default port clock if not overwritten by the encoder. Needs to be
4688 * done afterwards in case the encoder adjusts the mode. */
4689 if (!crtc_state
->port_clock
)
4690 crtc_state
->port_clock
= crtc_state
->hw
.adjusted_mode
.crtc_clock
4691 * crtc_state
->pixel_multiplier
;
4693 ret
= intel_crtc_compute_config(state
, crtc
);
4694 if (ret
== -EDEADLK
)
4697 drm_dbg_kms(&i915
->drm
, "[CRTC:%d:%s] config failure: %d\n",
4698 crtc
->base
.base
.id
, crtc
->base
.name
, ret
);
4702 /* Dithering seems to not pass-through bits correctly when it should, so
4703 * only enable it on 6bpc panels and when its not a compliance
4704 * test requesting 6bpc video pattern.
4706 crtc_state
->dither
= (crtc_state
->pipe_bpp
== 6*3) &&
4707 !crtc_state
->dither_force_disable
;
4708 drm_dbg_kms(&i915
->drm
,
4709 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4710 crtc
->base
.base
.id
, crtc
->base
.name
,
4711 base_bpp
, crtc_state
->pipe_bpp
, crtc_state
->dither
);
4717 intel_modeset_pipe_config_late(struct intel_atomic_state
*state
,
4718 struct intel_crtc
*crtc
)
4720 struct intel_crtc_state
*crtc_state
=
4721 intel_atomic_get_new_crtc_state(state
, crtc
);
4722 struct drm_connector_state
*conn_state
;
4723 struct drm_connector
*connector
;
4726 intel_bigjoiner_adjust_pipe_src(crtc_state
);
4728 for_each_new_connector_in_state(&state
->base
, connector
,
4730 struct intel_encoder
*encoder
=
4731 to_intel_encoder(conn_state
->best_encoder
);
4734 if (conn_state
->crtc
!= &crtc
->base
||
4735 !encoder
->compute_config_late
)
4738 ret
= encoder
->compute_config_late(encoder
, crtc_state
,
4747 bool intel_fuzzy_clock_check(int clock1
, int clock2
)
4751 if (clock1
== clock2
)
4754 if (!clock1
|| !clock2
)
4757 diff
= abs(clock1
- clock2
);
4759 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
4766 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
4767 const struct intel_link_m_n
*m2_n2
)
4769 return m_n
->tu
== m2_n2
->tu
&&
4770 m_n
->data_m
== m2_n2
->data_m
&&
4771 m_n
->data_n
== m2_n2
->data_n
&&
4772 m_n
->link_m
== m2_n2
->link_m
&&
4773 m_n
->link_n
== m2_n2
->link_n
;
4777 intel_compare_infoframe(const union hdmi_infoframe
*a
,
4778 const union hdmi_infoframe
*b
)
4780 return memcmp(a
, b
, sizeof(*a
)) == 0;
4784 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp
*a
,
4785 const struct drm_dp_vsc_sdp
*b
)
4787 return a
->pixelformat
== b
->pixelformat
&&
4788 a
->colorimetry
== b
->colorimetry
&&
4790 a
->dynamic_range
== b
->dynamic_range
&&
4791 a
->content_type
== b
->content_type
;
4795 intel_compare_buffer(const u8
*a
, const u8
*b
, size_t len
)
4797 return memcmp(a
, b
, len
) == 0;
4801 pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv
,
4802 bool fastset
, const char *name
,
4803 const union hdmi_infoframe
*a
,
4804 const union hdmi_infoframe
*b
)
4807 if (!drm_debug_enabled(DRM_UT_KMS
))
4810 drm_dbg_kms(&dev_priv
->drm
,
4811 "fastset requirement not met in %s infoframe\n", name
);
4812 drm_dbg_kms(&dev_priv
->drm
, "expected:\n");
4813 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, a
);
4814 drm_dbg_kms(&dev_priv
->drm
, "found:\n");
4815 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, b
);
4817 drm_err(&dev_priv
->drm
, "mismatch in %s infoframe\n", name
);
4818 drm_err(&dev_priv
->drm
, "expected:\n");
4819 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, a
);
4820 drm_err(&dev_priv
->drm
, "found:\n");
4821 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, b
);
4826 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private
*i915
,
4827 bool fastset
, const char *name
,
4828 const struct drm_dp_vsc_sdp
*a
,
4829 const struct drm_dp_vsc_sdp
*b
)
4831 struct drm_printer p
;
4834 p
= drm_dbg_printer(&i915
->drm
, DRM_UT_KMS
, NULL
);
4836 drm_printf(&p
, "fastset requirement not met in %s dp sdp\n", name
);
4838 p
= drm_err_printer(&i915
->drm
, NULL
);
4840 drm_printf(&p
, "mismatch in %s dp sdp\n", name
);
4843 drm_printf(&p
, "expected:\n");
4844 drm_dp_vsc_sdp_log(&p
, a
);
4845 drm_printf(&p
, "found:\n");
4846 drm_dp_vsc_sdp_log(&p
, b
);
4849 /* Returns the length up to and including the last differing byte */
4851 memcmp_diff_len(const u8
*a
, const u8
*b
, size_t len
)
4855 for (i
= len
- 1; i
>= 0; i
--) {
4864 pipe_config_buffer_mismatch(bool fastset
, const struct intel_crtc
*crtc
,
4866 const u8
*a
, const u8
*b
, size_t len
)
4868 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4871 if (!drm_debug_enabled(DRM_UT_KMS
))
4874 /* only dump up to the last difference */
4875 len
= memcmp_diff_len(a
, b
, len
);
4877 drm_dbg_kms(&dev_priv
->drm
,
4878 "[CRTC:%d:%s] fastset requirement not met in %s buffer\n",
4879 crtc
->base
.base
.id
, crtc
->base
.name
, name
);
4880 print_hex_dump(KERN_DEBUG
, "expected: ", DUMP_PREFIX_NONE
,
4881 16, 0, a
, len
, false);
4882 print_hex_dump(KERN_DEBUG
, "found: ", DUMP_PREFIX_NONE
,
4883 16, 0, b
, len
, false);
4885 /* only dump up to the last difference */
4886 len
= memcmp_diff_len(a
, b
, len
);
4888 drm_err(&dev_priv
->drm
, "[CRTC:%d:%s] mismatch in %s buffer\n",
4889 crtc
->base
.base
.id
, crtc
->base
.name
, name
);
4890 print_hex_dump(KERN_ERR
, "expected: ", DUMP_PREFIX_NONE
,
4891 16, 0, a
, len
, false);
4892 print_hex_dump(KERN_ERR
, "found: ", DUMP_PREFIX_NONE
,
4893 16, 0, b
, len
, false);
4897 static void __printf(4, 5)
4898 pipe_config_mismatch(bool fastset
, const struct intel_crtc
*crtc
,
4899 const char *name
, const char *format
, ...)
4901 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
4902 struct va_format vaf
;
4905 va_start(args
, format
);
4910 drm_dbg_kms(&i915
->drm
,
4911 "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4912 crtc
->base
.base
.id
, crtc
->base
.name
, name
, &vaf
);
4914 drm_err(&i915
->drm
, "[CRTC:%d:%s] mismatch in %s %pV\n",
4915 crtc
->base
.base
.id
, crtc
->base
.name
, name
, &vaf
);
4921 pipe_config_pll_mismatch(bool fastset
,
4922 const struct intel_crtc
*crtc
,
4924 const struct intel_dpll_hw_state
*a
,
4925 const struct intel_dpll_hw_state
*b
)
4927 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
4930 if (!drm_debug_enabled(DRM_UT_KMS
))
4933 drm_dbg_kms(&i915
->drm
,
4934 "[CRTC:%d:%s] fastset requirement not met in %s\n",
4935 crtc
->base
.base
.id
, crtc
->base
.name
, name
);
4936 drm_dbg_kms(&i915
->drm
, "expected:\n");
4937 intel_dpll_dump_hw_state(i915
, a
);
4938 drm_dbg_kms(&i915
->drm
, "found:\n");
4939 intel_dpll_dump_hw_state(i915
, b
);
4941 drm_err(&i915
->drm
, "[CRTC:%d:%s] mismatch in %s buffer\n",
4942 crtc
->base
.base
.id
, crtc
->base
.name
, name
);
4943 drm_err(&i915
->drm
, "expected:\n");
4944 intel_dpll_dump_hw_state(i915
, a
);
4945 drm_err(&i915
->drm
, "found:\n");
4946 intel_dpll_dump_hw_state(i915
, b
);
4951 intel_pipe_config_compare(const struct intel_crtc_state
*current_config
,
4952 const struct intel_crtc_state
*pipe_config
,
4955 struct drm_i915_private
*dev_priv
= to_i915(current_config
->uapi
.crtc
->dev
);
4956 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->uapi
.crtc
);
4959 #define PIPE_CONF_CHECK_X(name) do { \
4960 if (current_config->name != pipe_config->name) { \
4961 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4962 __stringify(name) " is bool"); \
4963 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4964 "(expected 0x%08x, found 0x%08x)", \
4965 current_config->name, \
4966 pipe_config->name); \
4971 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
4972 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
4973 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4974 __stringify(name) " is bool"); \
4975 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4976 "(expected 0x%08x, found 0x%08x)", \
4977 current_config->name & (mask), \
4978 pipe_config->name & (mask)); \
4983 #define PIPE_CONF_CHECK_I(name) do { \
4984 if (current_config->name != pipe_config->name) { \
4985 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4986 __stringify(name) " is bool"); \
4987 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4988 "(expected %i, found %i)", \
4989 current_config->name, \
4990 pipe_config->name); \
4995 #define PIPE_CONF_CHECK_BOOL(name) do { \
4996 if (current_config->name != pipe_config->name) { \
4997 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
4998 __stringify(name) " is not bool"); \
4999 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5000 "(expected %s, found %s)", \
5001 str_yes_no(current_config->name), \
5002 str_yes_no(pipe_config->name)); \
5007 #define PIPE_CONF_CHECK_P(name) do { \
5008 if (current_config->name != pipe_config->name) { \
5009 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5010 "(expected %p, found %p)", \
5011 current_config->name, \
5012 pipe_config->name); \
5017 #define PIPE_CONF_CHECK_M_N(name) do { \
5018 if (!intel_compare_link_m_n(¤t_config->name, \
5019 &pipe_config->name)) { \
5020 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5021 "(expected tu %i data %i/%i link %i/%i, " \
5022 "found tu %i, data %i/%i link %i/%i)", \
5023 current_config->name.tu, \
5024 current_config->name.data_m, \
5025 current_config->name.data_n, \
5026 current_config->name.link_m, \
5027 current_config->name.link_n, \
5028 pipe_config->name.tu, \
5029 pipe_config->name.data_m, \
5030 pipe_config->name.data_n, \
5031 pipe_config->name.link_m, \
5032 pipe_config->name.link_n); \
5037 #define PIPE_CONF_CHECK_PLL(name) do { \
5038 if (!intel_dpll_compare_hw_state(dev_priv, ¤t_config->name, \
5039 &pipe_config->name)) { \
5040 pipe_config_pll_mismatch(fastset, crtc, __stringify(name), \
5041 ¤t_config->name, \
5042 &pipe_config->name); \
5047 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5048 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5049 PIPE_CONF_CHECK_I(name.crtc_htotal); \
5050 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5051 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5052 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5053 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5054 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5055 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5056 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5057 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5058 if (!fastset || !pipe_config->update_lrr) { \
5059 PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5060 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5064 #define PIPE_CONF_CHECK_RECT(name) do { \
5065 PIPE_CONF_CHECK_I(name.x1); \
5066 PIPE_CONF_CHECK_I(name.x2); \
5067 PIPE_CONF_CHECK_I(name.y1); \
5068 PIPE_CONF_CHECK_I(name.y2); \
5071 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5072 if ((current_config->name ^ pipe_config->name) & (mask)) { \
5073 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5074 "(%x) (expected %i, found %i)", \
5076 current_config->name & (mask), \
5077 pipe_config->name & (mask)); \
5082 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5083 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
5084 &pipe_config->infoframes.name)) { \
5085 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5086 ¤t_config->infoframes.name, \
5087 &pipe_config->infoframes.name); \
5092 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5093 if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
5094 &pipe_config->infoframes.name)) { \
5095 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5096 ¤t_config->infoframes.name, \
5097 &pipe_config->infoframes.name); \
5102 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5103 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5104 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5105 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5106 pipe_config_buffer_mismatch(fastset, crtc, __stringify(name), \
5107 current_config->name, \
5108 pipe_config->name, \
5114 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5115 if (current_config->gamma_mode == pipe_config->gamma_mode && \
5116 !intel_color_lut_equal(current_config, \
5117 current_config->lut, pipe_config->lut, \
5118 is_pre_csc_lut)) { \
5119 pipe_config_mismatch(fastset, crtc, __stringify(lut), \
5120 "hw_state doesn't match sw_state"); \
5125 #define PIPE_CONF_CHECK_CSC(name) do { \
5126 PIPE_CONF_CHECK_X(name.preoff[0]); \
5127 PIPE_CONF_CHECK_X(name.preoff[1]); \
5128 PIPE_CONF_CHECK_X(name.preoff[2]); \
5129 PIPE_CONF_CHECK_X(name.coeff[0]); \
5130 PIPE_CONF_CHECK_X(name.coeff[1]); \
5131 PIPE_CONF_CHECK_X(name.coeff[2]); \
5132 PIPE_CONF_CHECK_X(name.coeff[3]); \
5133 PIPE_CONF_CHECK_X(name.coeff[4]); \
5134 PIPE_CONF_CHECK_X(name.coeff[5]); \
5135 PIPE_CONF_CHECK_X(name.coeff[6]); \
5136 PIPE_CONF_CHECK_X(name.coeff[7]); \
5137 PIPE_CONF_CHECK_X(name.coeff[8]); \
5138 PIPE_CONF_CHECK_X(name.postoff[0]); \
5139 PIPE_CONF_CHECK_X(name.postoff[1]); \
5140 PIPE_CONF_CHECK_X(name.postoff[2]); \
5143 #define PIPE_CONF_QUIRK(quirk) \
5144 ((current_config->quirks | pipe_config->quirks) & (quirk))
5146 PIPE_CONF_CHECK_BOOL(hw
.enable
);
5147 PIPE_CONF_CHECK_BOOL(hw
.active
);
5149 PIPE_CONF_CHECK_I(cpu_transcoder
);
5150 PIPE_CONF_CHECK_I(mst_master_transcoder
);
5152 PIPE_CONF_CHECK_BOOL(has_pch_encoder
);
5153 PIPE_CONF_CHECK_I(fdi_lanes
);
5154 PIPE_CONF_CHECK_M_N(fdi_m_n
);
5156 PIPE_CONF_CHECK_I(lane_count
);
5157 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
5159 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv
)) {
5160 if (!fastset
|| !pipe_config
->update_m_n
)
5161 PIPE_CONF_CHECK_M_N(dp_m_n
);
5163 PIPE_CONF_CHECK_M_N(dp_m_n
);
5164 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
5167 PIPE_CONF_CHECK_X(output_types
);
5169 PIPE_CONF_CHECK_I(framestart_delay
);
5170 PIPE_CONF_CHECK_I(msa_timing_delay
);
5172 PIPE_CONF_CHECK_TIMINGS(hw
.pipe_mode
);
5173 PIPE_CONF_CHECK_TIMINGS(hw
.adjusted_mode
);
5175 PIPE_CONF_CHECK_I(pixel_multiplier
);
5177 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5178 DRM_MODE_FLAG_INTERLACE
);
5180 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
5181 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5182 DRM_MODE_FLAG_PHSYNC
);
5183 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5184 DRM_MODE_FLAG_NHSYNC
);
5185 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5186 DRM_MODE_FLAG_PVSYNC
);
5187 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5188 DRM_MODE_FLAG_NVSYNC
);
5191 PIPE_CONF_CHECK_I(output_format
);
5192 PIPE_CONF_CHECK_BOOL(has_hdmi_sink
);
5193 if ((DISPLAY_VER(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
5194 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5195 PIPE_CONF_CHECK_BOOL(limited_color_range
);
5197 PIPE_CONF_CHECK_BOOL(hdmi_scrambling
);
5198 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio
);
5199 PIPE_CONF_CHECK_BOOL(has_infoframe
);
5200 PIPE_CONF_CHECK_BOOL(enhanced_framing
);
5201 PIPE_CONF_CHECK_BOOL(fec_enable
);
5204 PIPE_CONF_CHECK_BOOL(has_audio
);
5205 PIPE_CONF_CHECK_BUFFER(eld
, MAX_ELD_BYTES
);
5208 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
5209 /* pfit ratios are autocomputed by the hw on gen4+ */
5210 if (DISPLAY_VER(dev_priv
) < 4)
5211 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
5212 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
5215 * Changing the EDP transcoder input mux
5216 * (A_ONOFF vs. A_ON) requires a full modeset.
5218 PIPE_CONF_CHECK_BOOL(pch_pfit
.force_thru
);
5221 PIPE_CONF_CHECK_RECT(pipe_src
);
5223 PIPE_CONF_CHECK_BOOL(pch_pfit
.enabled
);
5224 PIPE_CONF_CHECK_RECT(pch_pfit
.dst
);
5226 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
5227 PIPE_CONF_CHECK_I(pixel_rate
);
5229 PIPE_CONF_CHECK_X(gamma_mode
);
5230 if (IS_CHERRYVIEW(dev_priv
))
5231 PIPE_CONF_CHECK_X(cgm_mode
);
5233 PIPE_CONF_CHECK_X(csc_mode
);
5234 PIPE_CONF_CHECK_BOOL(gamma_enable
);
5235 PIPE_CONF_CHECK_BOOL(csc_enable
);
5236 PIPE_CONF_CHECK_BOOL(wgc_enable
);
5238 PIPE_CONF_CHECK_I(linetime
);
5239 PIPE_CONF_CHECK_I(ips_linetime
);
5241 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut
, true);
5242 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut
, false);
5244 PIPE_CONF_CHECK_CSC(csc
);
5245 PIPE_CONF_CHECK_CSC(output_csc
);
5248 PIPE_CONF_CHECK_BOOL(double_wide
);
5250 if (dev_priv
->display
.dpll
.mgr
)
5251 PIPE_CONF_CHECK_P(shared_dpll
);
5253 /* FIXME convert everything over the dpll_mgr */
5254 if (dev_priv
->display
.dpll
.mgr
|| HAS_GMCH(dev_priv
))
5255 PIPE_CONF_CHECK_PLL(dpll_hw_state
);
5257 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
5258 PIPE_CONF_CHECK_X(dsi_pll
.div
);
5260 if (IS_G4X(dev_priv
) || DISPLAY_VER(dev_priv
) >= 5)
5261 PIPE_CONF_CHECK_I(pipe_bpp
);
5263 if (!fastset
|| !pipe_config
->update_m_n
) {
5264 PIPE_CONF_CHECK_I(hw
.pipe_mode
.crtc_clock
);
5265 PIPE_CONF_CHECK_I(hw
.adjusted_mode
.crtc_clock
);
5267 PIPE_CONF_CHECK_I(port_clock
);
5269 PIPE_CONF_CHECK_I(min_voltage_level
);
5271 if (current_config
->has_psr
|| pipe_config
->has_psr
)
5272 PIPE_CONF_CHECK_X_WITH_MASK(infoframes
.enable
,
5273 ~intel_hdmi_infoframe_enable(DP_SDP_VSC
));
5275 PIPE_CONF_CHECK_X(infoframes
.enable
);
5277 PIPE_CONF_CHECK_X(infoframes
.gcp
);
5278 PIPE_CONF_CHECK_INFOFRAME(avi
);
5279 PIPE_CONF_CHECK_INFOFRAME(spd
);
5280 PIPE_CONF_CHECK_INFOFRAME(hdmi
);
5281 PIPE_CONF_CHECK_INFOFRAME(drm
);
5282 PIPE_CONF_CHECK_DP_VSC_SDP(vsc
);
5284 PIPE_CONF_CHECK_X(sync_mode_slaves_mask
);
5285 PIPE_CONF_CHECK_I(master_transcoder
);
5286 PIPE_CONF_CHECK_X(bigjoiner_pipes
);
5288 PIPE_CONF_CHECK_BOOL(dsc
.config
.block_pred_enable
);
5289 PIPE_CONF_CHECK_BOOL(dsc
.config
.convert_rgb
);
5290 PIPE_CONF_CHECK_BOOL(dsc
.config
.simple_422
);
5291 PIPE_CONF_CHECK_BOOL(dsc
.config
.native_422
);
5292 PIPE_CONF_CHECK_BOOL(dsc
.config
.native_420
);
5293 PIPE_CONF_CHECK_BOOL(dsc
.config
.vbr_enable
);
5294 PIPE_CONF_CHECK_I(dsc
.config
.line_buf_depth
);
5295 PIPE_CONF_CHECK_I(dsc
.config
.bits_per_component
);
5296 PIPE_CONF_CHECK_I(dsc
.config
.pic_width
);
5297 PIPE_CONF_CHECK_I(dsc
.config
.pic_height
);
5298 PIPE_CONF_CHECK_I(dsc
.config
.slice_width
);
5299 PIPE_CONF_CHECK_I(dsc
.config
.slice_height
);
5300 PIPE_CONF_CHECK_I(dsc
.config
.initial_dec_delay
);
5301 PIPE_CONF_CHECK_I(dsc
.config
.initial_xmit_delay
);
5302 PIPE_CONF_CHECK_I(dsc
.config
.scale_decrement_interval
);
5303 PIPE_CONF_CHECK_I(dsc
.config
.scale_increment_interval
);
5304 PIPE_CONF_CHECK_I(dsc
.config
.initial_scale_value
);
5305 PIPE_CONF_CHECK_I(dsc
.config
.first_line_bpg_offset
);
5306 PIPE_CONF_CHECK_I(dsc
.config
.flatness_min_qp
);
5307 PIPE_CONF_CHECK_I(dsc
.config
.flatness_max_qp
);
5308 PIPE_CONF_CHECK_I(dsc
.config
.slice_bpg_offset
);
5309 PIPE_CONF_CHECK_I(dsc
.config
.nfl_bpg_offset
);
5310 PIPE_CONF_CHECK_I(dsc
.config
.initial_offset
);
5311 PIPE_CONF_CHECK_I(dsc
.config
.final_offset
);
5312 PIPE_CONF_CHECK_I(dsc
.config
.rc_model_size
);
5313 PIPE_CONF_CHECK_I(dsc
.config
.rc_quant_incr_limit0
);
5314 PIPE_CONF_CHECK_I(dsc
.config
.rc_quant_incr_limit1
);
5315 PIPE_CONF_CHECK_I(dsc
.config
.slice_chunk_size
);
5316 PIPE_CONF_CHECK_I(dsc
.config
.second_line_bpg_offset
);
5317 PIPE_CONF_CHECK_I(dsc
.config
.nsl_bpg_offset
);
5319 PIPE_CONF_CHECK_BOOL(dsc
.compression_enable
);
5320 PIPE_CONF_CHECK_BOOL(dsc
.dsc_split
);
5321 PIPE_CONF_CHECK_I(dsc
.compressed_bpp_x16
);
5323 PIPE_CONF_CHECK_BOOL(splitter
.enable
);
5324 PIPE_CONF_CHECK_I(splitter
.link_count
);
5325 PIPE_CONF_CHECK_I(splitter
.pixel_overlap
);
5328 PIPE_CONF_CHECK_BOOL(vrr
.enable
);
5329 PIPE_CONF_CHECK_I(vrr
.vmin
);
5330 PIPE_CONF_CHECK_I(vrr
.vmax
);
5331 PIPE_CONF_CHECK_I(vrr
.flipline
);
5332 PIPE_CONF_CHECK_I(vrr
.pipeline_full
);
5333 PIPE_CONF_CHECK_I(vrr
.guardband
);
5336 #undef PIPE_CONF_CHECK_X
5337 #undef PIPE_CONF_CHECK_I
5338 #undef PIPE_CONF_CHECK_BOOL
5339 #undef PIPE_CONF_CHECK_P
5340 #undef PIPE_CONF_CHECK_FLAGS
5341 #undef PIPE_CONF_CHECK_COLOR_LUT
5342 #undef PIPE_CONF_CHECK_TIMINGS
5343 #undef PIPE_CONF_CHECK_RECT
5344 #undef PIPE_CONF_QUIRK
5350 intel_verify_planes(struct intel_atomic_state
*state
)
5352 struct intel_plane
*plane
;
5353 const struct intel_plane_state
*plane_state
;
5356 for_each_new_intel_plane_in_state(state
, plane
,
5358 assert_plane(plane
, plane_state
->planar_slave
||
5359 plane_state
->uapi
.visible
);
5362 static int intel_modeset_pipe(struct intel_atomic_state
*state
,
5363 struct intel_crtc_state
*crtc_state
,
5366 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5367 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
5370 drm_dbg_kms(&i915
->drm
, "[CRTC:%d:%s] Full modeset due to %s\n",
5371 crtc
->base
.base
.id
, crtc
->base
.name
, reason
);
5373 ret
= drm_atomic_add_affected_connectors(&state
->base
,
5378 ret
= intel_dp_tunnel_atomic_add_state_for_crtc(state
, crtc
);
5382 ret
= intel_dp_mst_add_topology_state_for_crtc(state
, crtc
);
5386 ret
= intel_atomic_add_affected_planes(state
, crtc
);
5390 crtc_state
->uapi
.mode_changed
= true;
5396 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5397 * @state: intel atomic state
5398 * @reason: the reason for the full modeset
5399 * @mask: mask of pipes to modeset
5401 * Add pipes in @mask to @state and force a full modeset on the enabled ones
5402 * due to the description in @reason.
5403 * This function can be called only before new plane states are computed.
5405 * Returns 0 in case of success, negative error code otherwise.
5407 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state
*state
,
5408 const char *reason
, u8 mask
)
5410 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5411 struct intel_crtc
*crtc
;
5413 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, crtc
, mask
) {
5414 struct intel_crtc_state
*crtc_state
;
5417 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
5418 if (IS_ERR(crtc_state
))
5419 return PTR_ERR(crtc_state
);
5421 if (!crtc_state
->hw
.enable
||
5422 intel_crtc_needs_modeset(crtc_state
))
5425 ret
= intel_modeset_pipe(state
, crtc_state
, reason
);
5434 intel_crtc_flag_modeset(struct intel_crtc_state
*crtc_state
)
5436 crtc_state
->uapi
.mode_changed
= true;
5438 crtc_state
->update_pipe
= false;
5439 crtc_state
->update_m_n
= false;
5440 crtc_state
->update_lrr
= false;
5444 * intel_modeset_all_pipes_late - force a full modeset on all pipes
5445 * @state: intel atomic state
5446 * @reason: the reason for the full modeset
5448 * Add all pipes to @state and force a full modeset on the active ones due to
5449 * the description in @reason.
5450 * This function can be called only after new plane states are computed already.
5452 * Returns 0 in case of success, negative error code otherwise.
5454 int intel_modeset_all_pipes_late(struct intel_atomic_state
*state
,
5457 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5458 struct intel_crtc
*crtc
;
5460 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
5461 struct intel_crtc_state
*crtc_state
;
5464 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
5465 if (IS_ERR(crtc_state
))
5466 return PTR_ERR(crtc_state
);
5468 if (!crtc_state
->hw
.active
||
5469 intel_crtc_needs_modeset(crtc_state
))
5472 ret
= intel_modeset_pipe(state
, crtc_state
, reason
);
5476 intel_crtc_flag_modeset(crtc_state
);
5478 crtc_state
->update_planes
|= crtc_state
->active_planes
;
5479 crtc_state
->async_flip_planes
= 0;
5480 crtc_state
->do_async_flip
= false;
5487 * This implements the workaround described in the "notes" section of the mode
5488 * set sequence documentation. When going from no pipes or single pipe to
5489 * multiple pipes, and planes are enabled after the pipe, we need to wait at
5490 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5492 static int hsw_mode_set_planes_workaround(struct intel_atomic_state
*state
)
5494 struct intel_crtc_state
*crtc_state
;
5495 struct intel_crtc
*crtc
;
5496 struct intel_crtc_state
*first_crtc_state
= NULL
;
5497 struct intel_crtc_state
*other_crtc_state
= NULL
;
5498 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
5501 /* look at all crtc's that are going to be enabled in during modeset */
5502 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5503 if (!crtc_state
->hw
.active
||
5504 !intel_crtc_needs_modeset(crtc_state
))
5507 if (first_crtc_state
) {
5508 other_crtc_state
= crtc_state
;
5511 first_crtc_state
= crtc_state
;
5512 first_pipe
= crtc
->pipe
;
5516 /* No workaround needed? */
5517 if (!first_crtc_state
)
5520 /* w/a possibly needed, check how many crtc's are already enabled. */
5521 for_each_intel_crtc(state
->base
.dev
, crtc
) {
5522 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
5523 if (IS_ERR(crtc_state
))
5524 return PTR_ERR(crtc_state
);
5526 crtc_state
->hsw_workaround_pipe
= INVALID_PIPE
;
5528 if (!crtc_state
->hw
.active
||
5529 intel_crtc_needs_modeset(crtc_state
))
5532 /* 2 or more enabled crtcs means no need for w/a */
5533 if (enabled_pipe
!= INVALID_PIPE
)
5536 enabled_pipe
= crtc
->pipe
;
5539 if (enabled_pipe
!= INVALID_PIPE
)
5540 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
5541 else if (other_crtc_state
)
5542 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
5547 u8
intel_calc_active_pipes(struct intel_atomic_state
*state
,
5550 const struct intel_crtc_state
*crtc_state
;
5551 struct intel_crtc
*crtc
;
5554 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5555 if (crtc_state
->hw
.active
)
5556 active_pipes
|= BIT(crtc
->pipe
);
5558 active_pipes
&= ~BIT(crtc
->pipe
);
5561 return active_pipes
;
5564 static int intel_modeset_checks(struct intel_atomic_state
*state
)
5566 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5568 state
->modeset
= true;
5570 if (IS_HASWELL(dev_priv
))
5571 return hsw_mode_set_planes_workaround(state
);
5576 static void intel_crtc_check_fastset(const struct intel_crtc_state
*old_crtc_state
,
5577 struct intel_crtc_state
*new_crtc_state
)
5579 struct drm_i915_private
*i915
= to_i915(old_crtc_state
->uapi
.crtc
->dev
);
5581 /* only allow LRR when the timings stay within the VRR range */
5582 if (old_crtc_state
->vrr
.in_range
!= new_crtc_state
->vrr
.in_range
)
5583 new_crtc_state
->update_lrr
= false;
5585 if (!intel_pipe_config_compare(old_crtc_state
, new_crtc_state
, true))
5586 drm_dbg_kms(&i915
->drm
, "fastset requirement not met, forcing full modeset\n");
5588 new_crtc_state
->uapi
.mode_changed
= false;
5590 if (intel_compare_link_m_n(&old_crtc_state
->dp_m_n
,
5591 &new_crtc_state
->dp_m_n
))
5592 new_crtc_state
->update_m_n
= false;
5594 if ((old_crtc_state
->hw
.adjusted_mode
.crtc_vtotal
== new_crtc_state
->hw
.adjusted_mode
.crtc_vtotal
&&
5595 old_crtc_state
->hw
.adjusted_mode
.crtc_vblank_end
== new_crtc_state
->hw
.adjusted_mode
.crtc_vblank_end
))
5596 new_crtc_state
->update_lrr
= false;
5598 if (intel_crtc_needs_modeset(new_crtc_state
))
5599 intel_crtc_flag_modeset(new_crtc_state
);
5601 new_crtc_state
->update_pipe
= true;
5604 static int intel_crtc_add_planes_to_state(struct intel_atomic_state
*state
,
5605 struct intel_crtc
*crtc
,
5608 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5609 struct intel_plane
*plane
;
5611 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
) {
5612 struct intel_plane_state
*plane_state
;
5614 if ((plane_ids_mask
& BIT(plane
->id
)) == 0)
5617 plane_state
= intel_atomic_get_plane_state(state
, plane
);
5618 if (IS_ERR(plane_state
))
5619 return PTR_ERR(plane_state
);
5625 int intel_atomic_add_affected_planes(struct intel_atomic_state
*state
,
5626 struct intel_crtc
*crtc
)
5628 const struct intel_crtc_state
*old_crtc_state
=
5629 intel_atomic_get_old_crtc_state(state
, crtc
);
5630 const struct intel_crtc_state
*new_crtc_state
=
5631 intel_atomic_get_new_crtc_state(state
, crtc
);
5633 return intel_crtc_add_planes_to_state(state
, crtc
,
5634 old_crtc_state
->enabled_planes
|
5635 new_crtc_state
->enabled_planes
);
5638 static bool active_planes_affects_min_cdclk(struct drm_i915_private
*dev_priv
)
5640 /* See {hsw,vlv,ivb}_plane_ratio() */
5641 return IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
) ||
5642 IS_CHERRYVIEW(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
5643 IS_IVYBRIDGE(dev_priv
);
5646 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state
*state
,
5647 struct intel_crtc
*crtc
,
5648 struct intel_crtc
*other
)
5650 const struct intel_plane_state __maybe_unused
*plane_state
;
5651 struct intel_plane
*plane
;
5655 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
5656 if (plane
->pipe
== crtc
->pipe
)
5657 plane_ids
|= BIT(plane
->id
);
5660 return intel_crtc_add_planes_to_state(state
, other
, plane_ids
);
5663 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state
*state
)
5665 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5666 const struct intel_crtc_state
*crtc_state
;
5667 struct intel_crtc
*crtc
;
5670 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5671 struct intel_crtc
*other
;
5673 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, other
,
5674 crtc_state
->bigjoiner_pipes
) {
5680 ret
= intel_crtc_add_bigjoiner_planes(state
, crtc
, other
);
5689 static int intel_atomic_check_planes(struct intel_atomic_state
*state
)
5691 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5692 struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
5693 struct intel_plane_state __maybe_unused
*plane_state
;
5694 struct intel_plane
*plane
;
5695 struct intel_crtc
*crtc
;
5698 ret
= icl_add_linked_planes(state
);
5702 ret
= intel_bigjoiner_add_affected_planes(state
);
5706 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
5707 ret
= intel_plane_atomic_check(state
, plane
);
5709 drm_dbg_atomic(&dev_priv
->drm
,
5710 "[PLANE:%d:%s] atomic driver check failed\n",
5711 plane
->base
.base
.id
, plane
->base
.name
);
5716 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
5717 new_crtc_state
, i
) {
5718 u8 old_active_planes
, new_active_planes
;
5720 ret
= icl_check_nv12_planes(new_crtc_state
);
5725 * On some platforms the number of active planes affects
5726 * the planes' minimum cdclk calculation. Add such planes
5727 * to the state before we compute the minimum cdclk.
5729 if (!active_planes_affects_min_cdclk(dev_priv
))
5732 old_active_planes
= old_crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
);
5733 new_active_planes
= new_crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
);
5735 if (hweight8(old_active_planes
) == hweight8(new_active_planes
))
5738 ret
= intel_crtc_add_planes_to_state(state
, crtc
, new_active_planes
);
5746 static int intel_atomic_check_crtcs(struct intel_atomic_state
*state
)
5748 struct intel_crtc_state __maybe_unused
*crtc_state
;
5749 struct intel_crtc
*crtc
;
5752 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5753 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
5756 ret
= intel_crtc_atomic_check(state
, crtc
);
5758 drm_dbg_atomic(&i915
->drm
,
5759 "[CRTC:%d:%s] atomic driver check failed\n",
5760 crtc
->base
.base
.id
, crtc
->base
.name
);
5768 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state
*state
,
5771 const struct intel_crtc_state
*new_crtc_state
;
5772 struct intel_crtc
*crtc
;
5775 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
5776 if (new_crtc_state
->hw
.enable
&&
5777 transcoders
& BIT(new_crtc_state
->cpu_transcoder
) &&
5778 intel_crtc_needs_modeset(new_crtc_state
))
5785 static bool intel_pipes_need_modeset(struct intel_atomic_state
*state
,
5788 const struct intel_crtc_state
*new_crtc_state
;
5789 struct intel_crtc
*crtc
;
5792 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
5793 if (new_crtc_state
->hw
.enable
&&
5794 pipes
& BIT(crtc
->pipe
) &&
5795 intel_crtc_needs_modeset(new_crtc_state
))
5802 static int intel_atomic_check_bigjoiner(struct intel_atomic_state
*state
,
5803 struct intel_crtc
*master_crtc
)
5805 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5806 struct intel_crtc_state
*master_crtc_state
=
5807 intel_atomic_get_new_crtc_state(state
, master_crtc
);
5808 struct intel_crtc
*slave_crtc
;
5810 if (!master_crtc_state
->bigjoiner_pipes
)
5814 if (drm_WARN_ON(&i915
->drm
,
5815 master_crtc
->pipe
!= bigjoiner_master_pipe(master_crtc_state
)))
5818 if (master_crtc_state
->bigjoiner_pipes
& ~bigjoiner_pipes(i915
)) {
5819 drm_dbg_kms(&i915
->drm
,
5820 "[CRTC:%d:%s] Cannot act as big joiner master "
5821 "(need 0x%x as pipes, only 0x%x possible)\n",
5822 master_crtc
->base
.base
.id
, master_crtc
->base
.name
,
5823 master_crtc_state
->bigjoiner_pipes
, bigjoiner_pipes(i915
));
5827 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, slave_crtc
,
5828 intel_crtc_bigjoiner_slave_pipes(master_crtc_state
)) {
5829 struct intel_crtc_state
*slave_crtc_state
;
5832 slave_crtc_state
= intel_atomic_get_crtc_state(&state
->base
, slave_crtc
);
5833 if (IS_ERR(slave_crtc_state
))
5834 return PTR_ERR(slave_crtc_state
);
5836 /* master being enabled, slave was already configured? */
5837 if (slave_crtc_state
->uapi
.enable
) {
5838 drm_dbg_kms(&i915
->drm
,
5839 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
5840 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
5841 slave_crtc
->base
.base
.id
, slave_crtc
->base
.name
,
5842 master_crtc
->base
.base
.id
, master_crtc
->base
.name
);
5847 * The state copy logic assumes the master crtc gets processed
5848 * before the slave crtc during the main compute_config loop.
5849 * This works because the crtcs are created in pipe order,
5850 * and the hardware requires master pipe < slave pipe as well.
5851 * Should that change we need to rethink the logic.
5853 if (WARN_ON(drm_crtc_index(&master_crtc
->base
) >
5854 drm_crtc_index(&slave_crtc
->base
)))
5857 drm_dbg_kms(&i915
->drm
,
5858 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
5859 slave_crtc
->base
.base
.id
, slave_crtc
->base
.name
,
5860 master_crtc
->base
.base
.id
, master_crtc
->base
.name
);
5862 slave_crtc_state
->bigjoiner_pipes
=
5863 master_crtc_state
->bigjoiner_pipes
;
5865 ret
= copy_bigjoiner_crtc_state_modeset(state
, slave_crtc
);
5873 static void kill_bigjoiner_slave(struct intel_atomic_state
*state
,
5874 struct intel_crtc
*master_crtc
)
5876 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5877 struct intel_crtc_state
*master_crtc_state
=
5878 intel_atomic_get_new_crtc_state(state
, master_crtc
);
5879 struct intel_crtc
*slave_crtc
;
5881 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, slave_crtc
,
5882 intel_crtc_bigjoiner_slave_pipes(master_crtc_state
)) {
5883 struct intel_crtc_state
*slave_crtc_state
=
5884 intel_atomic_get_new_crtc_state(state
, slave_crtc
);
5886 slave_crtc_state
->bigjoiner_pipes
= 0;
5888 intel_crtc_copy_uapi_to_hw_state_modeset(state
, slave_crtc
);
5891 master_crtc_state
->bigjoiner_pipes
= 0;
5895 * DOC: asynchronous flip implementation
5897 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5898 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5899 * Correspondingly, support is currently added for primary plane only.
5901 * Async flip can only change the plane surface address, so anything else
5902 * changing is rejected from the intel_async_flip_check_hw() function.
5903 * Once this check is cleared, flip done interrupt is enabled using
5904 * the intel_crtc_enable_flip_done() function.
5906 * As soon as the surface address register is written, flip done interrupt is
5907 * generated and the requested events are sent to the usersapce in the interrupt
5908 * handler itself. The timestamp and sequence sent during the flip done event
5909 * correspond to the last vblank and have no relation to the actual time when
5910 * the flip done event was sent.
5912 static int intel_async_flip_check_uapi(struct intel_atomic_state
*state
,
5913 struct intel_crtc
*crtc
)
5915 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5916 const struct intel_crtc_state
*new_crtc_state
=
5917 intel_atomic_get_new_crtc_state(state
, crtc
);
5918 const struct intel_plane_state
*old_plane_state
;
5919 struct intel_plane_state
*new_plane_state
;
5920 struct intel_plane
*plane
;
5923 if (!new_crtc_state
->uapi
.async_flip
)
5926 if (!new_crtc_state
->uapi
.active
) {
5927 drm_dbg_kms(&i915
->drm
,
5928 "[CRTC:%d:%s] not active\n",
5929 crtc
->base
.base
.id
, crtc
->base
.name
);
5933 if (intel_crtc_needs_modeset(new_crtc_state
)) {
5934 drm_dbg_kms(&i915
->drm
,
5935 "[CRTC:%d:%s] modeset required\n",
5936 crtc
->base
.base
.id
, crtc
->base
.name
);
5941 * FIXME: Bigjoiner+async flip is busted currently.
5942 * Remove this check once the issues are fixed.
5944 if (new_crtc_state
->bigjoiner_pipes
) {
5945 drm_dbg_kms(&i915
->drm
,
5946 "[CRTC:%d:%s] async flip disallowed with bigjoiner\n",
5947 crtc
->base
.base
.id
, crtc
->base
.name
);
5951 for_each_oldnew_intel_plane_in_state(state
, plane
, old_plane_state
,
5952 new_plane_state
, i
) {
5953 if (plane
->pipe
!= crtc
->pipe
)
5957 * TODO: Async flip is only supported through the page flip IOCTL
5958 * as of now. So support currently added for primary plane only.
5959 * Support for other planes on platforms on which supports
5960 * this(vlv/chv and icl+) should be added when async flip is
5961 * enabled in the atomic IOCTL path.
5963 if (!plane
->async_flip
) {
5964 drm_dbg_kms(&i915
->drm
,
5965 "[PLANE:%d:%s] async flip not supported\n",
5966 plane
->base
.base
.id
, plane
->base
.name
);
5970 if (!old_plane_state
->uapi
.fb
|| !new_plane_state
->uapi
.fb
) {
5971 drm_dbg_kms(&i915
->drm
,
5972 "[PLANE:%d:%s] no old or new framebuffer\n",
5973 plane
->base
.base
.id
, plane
->base
.name
);
5981 static int intel_async_flip_check_hw(struct intel_atomic_state
*state
, struct intel_crtc
*crtc
)
5983 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5984 const struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
5985 const struct intel_plane_state
*new_plane_state
, *old_plane_state
;
5986 struct intel_plane
*plane
;
5989 old_crtc_state
= intel_atomic_get_old_crtc_state(state
, crtc
);
5990 new_crtc_state
= intel_atomic_get_new_crtc_state(state
, crtc
);
5992 if (!new_crtc_state
->uapi
.async_flip
)
5995 if (!new_crtc_state
->hw
.active
) {
5996 drm_dbg_kms(&i915
->drm
,
5997 "[CRTC:%d:%s] not active\n",
5998 crtc
->base
.base
.id
, crtc
->base
.name
);
6002 if (intel_crtc_needs_modeset(new_crtc_state
)) {
6003 drm_dbg_kms(&i915
->drm
,
6004 "[CRTC:%d:%s] modeset required\n",
6005 crtc
->base
.base
.id
, crtc
->base
.name
);
6009 if (old_crtc_state
->active_planes
!= new_crtc_state
->active_planes
) {
6010 drm_dbg_kms(&i915
->drm
,
6011 "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6012 crtc
->base
.base
.id
, crtc
->base
.name
);
6016 for_each_oldnew_intel_plane_in_state(state
, plane
, old_plane_state
,
6017 new_plane_state
, i
) {
6018 if (plane
->pipe
!= crtc
->pipe
)
6022 * Only async flip capable planes should be in the state
6023 * if we're really about to ask the hardware to perform
6024 * an async flip. We should never get this far otherwise.
6026 if (drm_WARN_ON(&i915
->drm
,
6027 new_crtc_state
->do_async_flip
&& !plane
->async_flip
))
6031 * Only check async flip capable planes other planes
6032 * may be involved in the initial commit due to
6033 * the wm0/ddb optimization.
6035 * TODO maybe should track which planes actually
6036 * were requested to do the async flip...
6038 if (!plane
->async_flip
)
6042 * FIXME: This check is kept generic for all platforms.
6043 * Need to verify this for all gen9 platforms to enable
6044 * this selectively if required.
6046 switch (new_plane_state
->hw
.fb
->modifier
) {
6047 case DRM_FORMAT_MOD_LINEAR
:
6049 * FIXME: Async on Linear buffer is supported on ICL as
6050 * but with additional alignment and fbc restrictions
6051 * need to be taken care of. These aren't applicable for
6054 if (DISPLAY_VER(i915
) < 12) {
6055 drm_dbg_kms(&i915
->drm
,
6056 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
6057 plane
->base
.base
.id
, plane
->base
.name
,
6058 new_plane_state
->hw
.fb
->modifier
, DISPLAY_VER(i915
));
6063 case I915_FORMAT_MOD_X_TILED
:
6064 case I915_FORMAT_MOD_Y_TILED
:
6065 case I915_FORMAT_MOD_Yf_TILED
:
6066 case I915_FORMAT_MOD_4_TILED
:
6069 drm_dbg_kms(&i915
->drm
,
6070 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
6071 plane
->base
.base
.id
, plane
->base
.name
,
6072 new_plane_state
->hw
.fb
->modifier
);
6076 if (new_plane_state
->hw
.fb
->format
->num_planes
> 1) {
6077 drm_dbg_kms(&i915
->drm
,
6078 "[PLANE:%d:%s] Planar formats do not support async flips\n",
6079 plane
->base
.base
.id
, plane
->base
.name
);
6083 if (old_plane_state
->view
.color_plane
[0].mapping_stride
!=
6084 new_plane_state
->view
.color_plane
[0].mapping_stride
) {
6085 drm_dbg_kms(&i915
->drm
,
6086 "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6087 plane
->base
.base
.id
, plane
->base
.name
);
6091 if (old_plane_state
->hw
.fb
->modifier
!=
6092 new_plane_state
->hw
.fb
->modifier
) {
6093 drm_dbg_kms(&i915
->drm
,
6094 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6095 plane
->base
.base
.id
, plane
->base
.name
);
6099 if (old_plane_state
->hw
.fb
->format
!=
6100 new_plane_state
->hw
.fb
->format
) {
6101 drm_dbg_kms(&i915
->drm
,
6102 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6103 plane
->base
.base
.id
, plane
->base
.name
);
6107 if (old_plane_state
->hw
.rotation
!=
6108 new_plane_state
->hw
.rotation
) {
6109 drm_dbg_kms(&i915
->drm
,
6110 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6111 plane
->base
.base
.id
, plane
->base
.name
);
6115 if (!drm_rect_equals(&old_plane_state
->uapi
.src
, &new_plane_state
->uapi
.src
) ||
6116 !drm_rect_equals(&old_plane_state
->uapi
.dst
, &new_plane_state
->uapi
.dst
)) {
6117 drm_dbg_kms(&i915
->drm
,
6118 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6119 plane
->base
.base
.id
, plane
->base
.name
);
6123 if (old_plane_state
->hw
.alpha
!= new_plane_state
->hw
.alpha
) {
6124 drm_dbg_kms(&i915
->drm
,
6125 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6126 plane
->base
.base
.id
, plane
->base
.name
);
6130 if (old_plane_state
->hw
.pixel_blend_mode
!=
6131 new_plane_state
->hw
.pixel_blend_mode
) {
6132 drm_dbg_kms(&i915
->drm
,
6133 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6134 plane
->base
.base
.id
, plane
->base
.name
);
6138 if (old_plane_state
->hw
.color_encoding
!= new_plane_state
->hw
.color_encoding
) {
6139 drm_dbg_kms(&i915
->drm
,
6140 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6141 plane
->base
.base
.id
, plane
->base
.name
);
6145 if (old_plane_state
->hw
.color_range
!= new_plane_state
->hw
.color_range
) {
6146 drm_dbg_kms(&i915
->drm
,
6147 "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6148 plane
->base
.base
.id
, plane
->base
.name
);
6152 /* plane decryption is allow to change only in synchronous flips */
6153 if (old_plane_state
->decrypt
!= new_plane_state
->decrypt
) {
6154 drm_dbg_kms(&i915
->drm
,
6155 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6156 plane
->base
.base
.id
, plane
->base
.name
);
6164 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state
*state
)
6166 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
6167 struct intel_crtc_state
*crtc_state
;
6168 struct intel_crtc
*crtc
;
6169 u8 affected_pipes
= 0;
6170 u8 modeset_pipes
= 0;
6173 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6174 affected_pipes
|= crtc_state
->bigjoiner_pipes
;
6175 if (intel_crtc_needs_modeset(crtc_state
))
6176 modeset_pipes
|= crtc_state
->bigjoiner_pipes
;
6179 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, crtc
, affected_pipes
) {
6180 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
6181 if (IS_ERR(crtc_state
))
6182 return PTR_ERR(crtc_state
);
6185 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, crtc
, modeset_pipes
) {
6188 crtc_state
= intel_atomic_get_new_crtc_state(state
, crtc
);
6190 crtc_state
->uapi
.mode_changed
= true;
6192 ret
= drm_atomic_add_affected_connectors(&state
->base
, &crtc
->base
);
6196 ret
= intel_atomic_add_affected_planes(state
, crtc
);
6201 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6202 /* Kill old bigjoiner link, we may re-establish afterwards */
6203 if (intel_crtc_needs_modeset(crtc_state
) &&
6204 intel_crtc_is_bigjoiner_master(crtc_state
))
6205 kill_bigjoiner_slave(state
, crtc
);
6211 static int intel_atomic_check_config(struct intel_atomic_state
*state
,
6212 struct intel_link_bw_limits
*limits
,
6213 enum pipe
*failed_pipe
)
6215 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
6216 struct intel_crtc_state
*new_crtc_state
;
6217 struct intel_crtc
*crtc
;
6221 *failed_pipe
= INVALID_PIPE
;
6223 ret
= intel_bigjoiner_add_affected_crtcs(state
);
6227 ret
= intel_fdi_add_affected_crtcs(state
);
6231 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6232 if (!intel_crtc_needs_modeset(new_crtc_state
)) {
6233 if (intel_crtc_is_bigjoiner_slave(new_crtc_state
))
6234 copy_bigjoiner_crtc_state_nomodeset(state
, crtc
);
6236 intel_crtc_copy_uapi_to_hw_state_nomodeset(state
, crtc
);
6240 if (intel_crtc_is_bigjoiner_slave(new_crtc_state
)) {
6241 drm_WARN_ON(&i915
->drm
, new_crtc_state
->uapi
.enable
);
6245 ret
= intel_crtc_prepare_cleared_state(state
, crtc
);
6249 if (!new_crtc_state
->hw
.enable
)
6252 ret
= intel_modeset_pipe_config(state
, crtc
, limits
);
6256 ret
= intel_atomic_check_bigjoiner(state
, crtc
);
6262 *failed_pipe
= crtc
->pipe
;
6267 static int intel_atomic_check_config_and_link(struct intel_atomic_state
*state
)
6269 struct intel_link_bw_limits new_limits
;
6270 struct intel_link_bw_limits old_limits
;
6273 intel_link_bw_init_limits(state
, &new_limits
);
6274 old_limits
= new_limits
;
6277 enum pipe failed_pipe
;
6279 ret
= intel_atomic_check_config(state
, &new_limits
,
6283 * The bpp limit for a pipe is below the minimum it supports, set the
6284 * limit to the minimum and recalculate the config.
6286 if (ret
== -EINVAL
&&
6287 intel_link_bw_set_bpp_limit_for_pipe(state
,
6296 old_limits
= new_limits
;
6298 ret
= intel_link_bw_atomic_check(state
, &new_limits
);
6306 * intel_atomic_check - validate state object
6308 * @_state: state to validate
6310 int intel_atomic_check(struct drm_device
*dev
,
6311 struct drm_atomic_state
*_state
)
6313 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6314 struct intel_atomic_state
*state
= to_intel_atomic_state(_state
);
6315 struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
6316 struct intel_crtc
*crtc
;
6318 bool any_ms
= false;
6320 if (!intel_display_driver_check_access(dev_priv
))
6323 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6324 new_crtc_state
, i
) {
6326 * crtc's state no longer considered to be inherited
6327 * after the first userspace/client initiated commit.
6329 if (!state
->internal
)
6330 new_crtc_state
->inherited
= false;
6332 if (new_crtc_state
->inherited
!= old_crtc_state
->inherited
)
6333 new_crtc_state
->uapi
.mode_changed
= true;
6335 if (new_crtc_state
->uapi
.scaling_filter
!=
6336 old_crtc_state
->uapi
.scaling_filter
)
6337 new_crtc_state
->uapi
.mode_changed
= true;
6340 intel_vrr_check_modeset(state
);
6342 ret
= drm_atomic_helper_check_modeset(dev
, &state
->base
);
6346 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6347 ret
= intel_async_flip_check_uapi(state
, crtc
);
6352 ret
= intel_atomic_check_config_and_link(state
);
6356 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6357 new_crtc_state
, i
) {
6358 if (!intel_crtc_needs_modeset(new_crtc_state
))
6361 if (new_crtc_state
->hw
.enable
) {
6362 ret
= intel_modeset_pipe_config_late(state
, crtc
);
6367 intel_crtc_check_fastset(old_crtc_state
, new_crtc_state
);
6371 * Check if fastset is allowed by external dependencies like other
6372 * pipes and transcoders.
6374 * Right now it only forces a fullmodeset when the MST master
6375 * transcoder did not changed but the pipe of the master transcoder
6376 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6377 * in case of port synced crtcs, if one of the synced crtcs
6378 * needs a full modeset, all other synced crtcs should be
6379 * forced a full modeset.
6381 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6382 if (!new_crtc_state
->hw
.enable
|| intel_crtc_needs_modeset(new_crtc_state
))
6385 if (intel_dp_mst_crtc_needs_modeset(state
, crtc
))
6386 intel_crtc_flag_modeset(new_crtc_state
);
6388 if (intel_dp_mst_is_slave_trans(new_crtc_state
)) {
6389 enum transcoder master
= new_crtc_state
->mst_master_transcoder
;
6391 if (intel_cpu_transcoders_need_modeset(state
, BIT(master
)))
6392 intel_crtc_flag_modeset(new_crtc_state
);
6395 if (is_trans_port_sync_mode(new_crtc_state
)) {
6396 u8 trans
= new_crtc_state
->sync_mode_slaves_mask
;
6398 if (new_crtc_state
->master_transcoder
!= INVALID_TRANSCODER
)
6399 trans
|= BIT(new_crtc_state
->master_transcoder
);
6401 if (intel_cpu_transcoders_need_modeset(state
, trans
))
6402 intel_crtc_flag_modeset(new_crtc_state
);
6405 if (new_crtc_state
->bigjoiner_pipes
) {
6406 if (intel_pipes_need_modeset(state
, new_crtc_state
->bigjoiner_pipes
))
6407 intel_crtc_flag_modeset(new_crtc_state
);
6411 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6412 new_crtc_state
, i
) {
6413 if (!intel_crtc_needs_modeset(new_crtc_state
))
6418 intel_release_shared_dplls(state
, crtc
);
6421 if (any_ms
&& !check_digital_port_conflicts(state
)) {
6422 drm_dbg_kms(&dev_priv
->drm
,
6423 "rejecting conflicting digital port configuration\n");
6428 ret
= intel_atomic_check_planes(state
);
6432 ret
= intel_compute_global_watermarks(state
);
6436 ret
= intel_bw_atomic_check(state
);
6440 ret
= intel_cdclk_atomic_check(state
, &any_ms
);
6444 if (intel_any_crtc_needs_modeset(state
))
6448 ret
= intel_modeset_checks(state
);
6452 ret
= intel_modeset_calc_cdclk(state
);
6457 ret
= intel_pmdemand_atomic_check(state
);
6461 ret
= intel_atomic_check_crtcs(state
);
6465 ret
= intel_fbc_atomic_check(state
);
6469 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6470 new_crtc_state
, i
) {
6471 intel_color_assert_luts(new_crtc_state
);
6473 ret
= intel_async_flip_check_hw(state
, crtc
);
6477 /* Either full modeset or fastset (or neither), never both */
6478 drm_WARN_ON(&dev_priv
->drm
,
6479 intel_crtc_needs_modeset(new_crtc_state
) &&
6480 intel_crtc_needs_fastset(new_crtc_state
));
6482 if (!intel_crtc_needs_modeset(new_crtc_state
) &&
6483 !intel_crtc_needs_fastset(new_crtc_state
))
6486 intel_crtc_state_dump(new_crtc_state
, state
,
6487 intel_crtc_needs_modeset(new_crtc_state
) ?
6488 "modeset" : "fastset");
6494 if (ret
== -EDEADLK
)
6498 * FIXME would probably be nice to know which crtc specifically
6499 * caused the failure, in cases where we can pinpoint it.
6501 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6503 intel_crtc_state_dump(new_crtc_state
, state
, "failed");
6508 static int intel_atomic_prepare_commit(struct intel_atomic_state
*state
)
6510 struct intel_crtc_state
*crtc_state
;
6511 struct intel_crtc
*crtc
;
6514 ret
= drm_atomic_helper_prepare_planes(state
->base
.dev
, &state
->base
);
6518 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6519 if (intel_crtc_needs_color_update(crtc_state
))
6520 intel_color_prepare_commit(crtc_state
);
6526 void intel_crtc_arm_fifo_underrun(struct intel_crtc
*crtc
,
6527 struct intel_crtc_state
*crtc_state
)
6529 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6531 if (DISPLAY_VER(dev_priv
) != 2 || crtc_state
->active_planes
)
6532 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
6534 if (crtc_state
->has_pch_encoder
) {
6535 enum pipe pch_transcoder
=
6536 intel_crtc_pch_transcoder(crtc
);
6538 intel_set_pch_fifo_underrun_reporting(dev_priv
, pch_transcoder
, true);
6542 static void intel_pipe_fastset(const struct intel_crtc_state
*old_crtc_state
,
6543 const struct intel_crtc_state
*new_crtc_state
)
6545 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
6546 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6549 * Update pipe size and adjust fitter if needed: the reason for this is
6550 * that in compute_mode_changes we check the native mode (not the pfit
6551 * mode) to see if we can flip rather than do a full mode set. In the
6552 * fastboot case, we'll flip, but if we don't update the pipesrc and
6553 * pfit state, we'll end up with a big fb scanned out into the wrong
6556 intel_set_pipe_src_size(new_crtc_state
);
6558 /* on skylake this is done by detaching scalers */
6559 if (DISPLAY_VER(dev_priv
) >= 9) {
6560 if (new_crtc_state
->pch_pfit
.enabled
)
6561 skl_pfit_enable(new_crtc_state
);
6562 } else if (HAS_PCH_SPLIT(dev_priv
)) {
6563 if (new_crtc_state
->pch_pfit
.enabled
)
6564 ilk_pfit_enable(new_crtc_state
);
6565 else if (old_crtc_state
->pch_pfit
.enabled
)
6566 ilk_pfit_disable(old_crtc_state
);
6570 * The register is supposedly single buffered so perhaps
6571 * not 100% correct to do this here. But SKL+ calculate
6572 * this based on the adjust pixel rate so pfit changes do
6573 * affect it and so it must be updated for fastsets.
6574 * HSW/BDW only really need this here for fastboot, after
6575 * that the value should not change without a full modeset.
6577 if (DISPLAY_VER(dev_priv
) >= 9 ||
6578 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
6579 hsw_set_linetime_wm(new_crtc_state
);
6581 if (new_crtc_state
->update_m_n
)
6582 intel_cpu_transcoder_set_m1_n1(crtc
, new_crtc_state
->cpu_transcoder
,
6583 &new_crtc_state
->dp_m_n
);
6585 if (new_crtc_state
->update_lrr
)
6586 intel_set_transcoder_timings_lrr(new_crtc_state
);
6589 static void commit_pipe_pre_planes(struct intel_atomic_state
*state
,
6590 struct intel_crtc
*crtc
)
6592 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6593 const struct intel_crtc_state
*old_crtc_state
=
6594 intel_atomic_get_old_crtc_state(state
, crtc
);
6595 const struct intel_crtc_state
*new_crtc_state
=
6596 intel_atomic_get_new_crtc_state(state
, crtc
);
6597 bool modeset
= intel_crtc_needs_modeset(new_crtc_state
);
6600 * During modesets pipe configuration was programmed as the
6604 if (intel_crtc_needs_color_update(new_crtc_state
))
6605 intel_color_commit_arm(new_crtc_state
);
6607 if (DISPLAY_VER(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
6608 bdw_set_pipe_misc(new_crtc_state
);
6610 if (intel_crtc_needs_fastset(new_crtc_state
))
6611 intel_pipe_fastset(old_crtc_state
, new_crtc_state
);
6614 intel_psr2_program_trans_man_trk_ctl(new_crtc_state
);
6616 intel_atomic_update_watermarks(state
, crtc
);
6619 static void commit_pipe_post_planes(struct intel_atomic_state
*state
,
6620 struct intel_crtc
*crtc
)
6622 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6623 const struct intel_crtc_state
*old_crtc_state
=
6624 intel_atomic_get_old_crtc_state(state
, crtc
);
6625 const struct intel_crtc_state
*new_crtc_state
=
6626 intel_atomic_get_new_crtc_state(state
, crtc
);
6629 * Disable the scaler(s) after the plane(s) so that we don't
6630 * get a catastrophic underrun even if the two operations
6631 * end up happening in two different frames.
6633 if (DISPLAY_VER(dev_priv
) >= 9 &&
6634 !intel_crtc_needs_modeset(new_crtc_state
))
6635 skl_detach_scalers(new_crtc_state
);
6637 if (vrr_enabling(old_crtc_state
, new_crtc_state
))
6638 intel_vrr_enable(new_crtc_state
);
6641 static void intel_enable_crtc(struct intel_atomic_state
*state
,
6642 struct intel_crtc
*crtc
)
6644 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6645 const struct intel_crtc_state
*new_crtc_state
=
6646 intel_atomic_get_new_crtc_state(state
, crtc
);
6648 if (!intel_crtc_needs_modeset(new_crtc_state
))
6651 /* VRR will be enable later, if required */
6652 intel_crtc_update_active_timings(new_crtc_state
, false);
6654 dev_priv
->display
.funcs
.display
->crtc_enable(state
, crtc
);
6656 if (intel_crtc_is_bigjoiner_slave(new_crtc_state
))
6659 /* vblanks work again, re-enable pipe CRC. */
6660 intel_crtc_enable_pipe_crc(crtc
);
6663 static void intel_pre_update_crtc(struct intel_atomic_state
*state
,
6664 struct intel_crtc
*crtc
)
6666 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
6667 const struct intel_crtc_state
*old_crtc_state
=
6668 intel_atomic_get_old_crtc_state(state
, crtc
);
6669 struct intel_crtc_state
*new_crtc_state
=
6670 intel_atomic_get_new_crtc_state(state
, crtc
);
6671 bool modeset
= intel_crtc_needs_modeset(new_crtc_state
);
6673 if (old_crtc_state
->inherited
||
6674 intel_crtc_needs_modeset(new_crtc_state
)) {
6676 intel_dpt_configure(crtc
);
6680 if (new_crtc_state
->preload_luts
&&
6681 intel_crtc_needs_color_update(new_crtc_state
))
6682 intel_color_load_luts(new_crtc_state
);
6684 intel_pre_plane_update(state
, crtc
);
6686 if (intel_crtc_needs_fastset(new_crtc_state
))
6687 intel_encoders_update_pipe(state
, crtc
);
6689 if (DISPLAY_VER(i915
) >= 11 &&
6690 intel_crtc_needs_fastset(new_crtc_state
))
6691 icl_set_pipe_chicken(new_crtc_state
);
6693 if (vrr_params_changed(old_crtc_state
, new_crtc_state
))
6694 intel_vrr_set_transcoder_timings(new_crtc_state
);
6697 intel_fbc_update(state
, crtc
);
6699 drm_WARN_ON(&i915
->drm
, !intel_display_power_is_enabled(i915
, POWER_DOMAIN_DC_OFF
));
6702 intel_crtc_needs_color_update(new_crtc_state
))
6703 intel_color_commit_noarm(new_crtc_state
);
6705 intel_crtc_planes_update_noarm(state
, crtc
);
6708 static void intel_update_crtc(struct intel_atomic_state
*state
,
6709 struct intel_crtc
*crtc
)
6711 const struct intel_crtc_state
*old_crtc_state
=
6712 intel_atomic_get_old_crtc_state(state
, crtc
);
6713 struct intel_crtc_state
*new_crtc_state
=
6714 intel_atomic_get_new_crtc_state(state
, crtc
);
6716 /* Perform vblank evasion around commit operation */
6717 intel_pipe_update_start(state
, crtc
);
6719 commit_pipe_pre_planes(state
, crtc
);
6721 intel_crtc_planes_update_arm(state
, crtc
);
6723 commit_pipe_post_planes(state
, crtc
);
6725 intel_pipe_update_end(state
, crtc
);
6728 * VRR/Seamless M/N update may need to update frame timings.
6730 * FIXME Should be synchronized with the start of vblank somehow...
6732 if (vrr_enabling(old_crtc_state
, new_crtc_state
) ||
6733 new_crtc_state
->update_m_n
|| new_crtc_state
->update_lrr
)
6734 intel_crtc_update_active_timings(new_crtc_state
,
6735 new_crtc_state
->vrr
.enable
);
6738 * We usually enable FIFO underrun interrupts as part of the
6739 * CRTC enable sequence during modesets. But when we inherit a
6740 * valid pipe configuration from the BIOS we need to take care
6741 * of enabling them on the CRTC's first fastset.
6743 if (intel_crtc_needs_fastset(new_crtc_state
) &&
6744 old_crtc_state
->inherited
)
6745 intel_crtc_arm_fifo_underrun(crtc
, new_crtc_state
);
6748 static void intel_old_crtc_state_disables(struct intel_atomic_state
*state
,
6749 struct intel_crtc_state
*old_crtc_state
,
6750 struct intel_crtc_state
*new_crtc_state
,
6751 struct intel_crtc
*crtc
)
6753 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6756 * We need to disable pipe CRC before disabling the pipe,
6757 * or we race against vblank off.
6759 intel_crtc_disable_pipe_crc(crtc
);
6761 dev_priv
->display
.funcs
.display
->crtc_disable(state
, crtc
);
6762 crtc
->active
= false;
6763 intel_fbc_disable(crtc
);
6765 if (!new_crtc_state
->hw
.active
)
6766 intel_initial_watermarks(state
, crtc
);
6769 static void intel_commit_modeset_disables(struct intel_atomic_state
*state
)
6771 struct intel_crtc_state
*new_crtc_state
, *old_crtc_state
;
6772 struct intel_crtc
*crtc
;
6776 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6777 new_crtc_state
, i
) {
6778 if (!intel_crtc_needs_modeset(new_crtc_state
))
6781 intel_pre_plane_update(state
, crtc
);
6783 if (!old_crtc_state
->hw
.active
)
6786 intel_crtc_disable_planes(state
, crtc
);
6789 /* Only disable port sync and MST slaves */
6790 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6791 new_crtc_state
, i
) {
6792 if (!intel_crtc_needs_modeset(new_crtc_state
))
6795 if (!old_crtc_state
->hw
.active
)
6798 /* In case of Transcoder port Sync master slave CRTCs can be
6799 * assigned in any order and we need to make sure that
6800 * slave CRTCs are disabled first and then master CRTC since
6801 * Slave vblanks are masked till Master Vblanks.
6803 if (!is_trans_port_sync_slave(old_crtc_state
) &&
6804 !intel_dp_mst_is_slave_trans(old_crtc_state
) &&
6805 !intel_crtc_is_bigjoiner_slave(old_crtc_state
))
6808 intel_old_crtc_state_disables(state
, old_crtc_state
,
6809 new_crtc_state
, crtc
);
6810 handled
|= BIT(crtc
->pipe
);
6813 /* Disable everything else left on */
6814 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6815 new_crtc_state
, i
) {
6816 if (!intel_crtc_needs_modeset(new_crtc_state
) ||
6817 (handled
& BIT(crtc
->pipe
)))
6820 if (!old_crtc_state
->hw
.active
)
6823 intel_old_crtc_state_disables(state
, old_crtc_state
,
6824 new_crtc_state
, crtc
);
6828 static void intel_commit_modeset_enables(struct intel_atomic_state
*state
)
6830 struct intel_crtc_state
*new_crtc_state
;
6831 struct intel_crtc
*crtc
;
6834 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6835 if (!new_crtc_state
->hw
.active
)
6838 intel_enable_crtc(state
, crtc
);
6839 intel_pre_update_crtc(state
, crtc
);
6842 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6843 if (!new_crtc_state
->hw
.active
)
6846 intel_update_crtc(state
, crtc
);
6850 static void skl_commit_modeset_enables(struct intel_atomic_state
*state
)
6852 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6853 struct intel_crtc
*crtc
;
6854 struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
6855 struct skl_ddb_entry entries
[I915_MAX_PIPES
] = {};
6856 u8 update_pipes
= 0, modeset_pipes
= 0;
6859 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
6860 enum pipe pipe
= crtc
->pipe
;
6862 if (!new_crtc_state
->hw
.active
)
6865 /* ignore allocations for crtc's that have been turned off. */
6866 if (!intel_crtc_needs_modeset(new_crtc_state
)) {
6867 entries
[pipe
] = old_crtc_state
->wm
.skl
.ddb
;
6868 update_pipes
|= BIT(pipe
);
6870 modeset_pipes
|= BIT(pipe
);
6875 * Whenever the number of active pipes changes, we need to make sure we
6876 * update the pipes in the right order so that their ddb allocations
6877 * never overlap with each other between CRTC updates. Otherwise we'll
6878 * cause pipe underruns and other bad stuff.
6880 * So first lets enable all pipes that do not need a fullmodeset as
6881 * those don't have any external dependency.
6883 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6884 enum pipe pipe
= crtc
->pipe
;
6886 if ((update_pipes
& BIT(pipe
)) == 0)
6889 intel_pre_update_crtc(state
, crtc
);
6892 while (update_pipes
) {
6893 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6894 new_crtc_state
, i
) {
6895 enum pipe pipe
= crtc
->pipe
;
6897 if ((update_pipes
& BIT(pipe
)) == 0)
6900 if (skl_ddb_allocation_overlaps(&new_crtc_state
->wm
.skl
.ddb
,
6901 entries
, I915_MAX_PIPES
, pipe
))
6904 entries
[pipe
] = new_crtc_state
->wm
.skl
.ddb
;
6905 update_pipes
&= ~BIT(pipe
);
6907 intel_update_crtc(state
, crtc
);
6910 * If this is an already active pipe, it's DDB changed,
6911 * and this isn't the last pipe that needs updating
6912 * then we need to wait for a vblank to pass for the
6913 * new ddb allocation to take effect.
6915 if (!skl_ddb_entry_equal(&new_crtc_state
->wm
.skl
.ddb
,
6916 &old_crtc_state
->wm
.skl
.ddb
) &&
6917 (update_pipes
| modeset_pipes
))
6918 intel_crtc_wait_for_next_vblank(crtc
);
6922 update_pipes
= modeset_pipes
;
6925 * Enable all pipes that needs a modeset and do not depends on other
6928 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6929 enum pipe pipe
= crtc
->pipe
;
6931 if ((modeset_pipes
& BIT(pipe
)) == 0)
6934 if (intel_dp_mst_is_slave_trans(new_crtc_state
) ||
6935 is_trans_port_sync_master(new_crtc_state
) ||
6936 intel_crtc_is_bigjoiner_master(new_crtc_state
))
6939 modeset_pipes
&= ~BIT(pipe
);
6941 intel_enable_crtc(state
, crtc
);
6945 * Then we enable all remaining pipes that depend on other
6946 * pipes: MST slaves and port sync masters, big joiner master
6948 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6949 enum pipe pipe
= crtc
->pipe
;
6951 if ((modeset_pipes
& BIT(pipe
)) == 0)
6954 modeset_pipes
&= ~BIT(pipe
);
6956 intel_enable_crtc(state
, crtc
);
6960 * Finally we do the plane updates/etc. for all pipes that got enabled.
6962 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6963 enum pipe pipe
= crtc
->pipe
;
6965 if ((update_pipes
& BIT(pipe
)) == 0)
6968 intel_pre_update_crtc(state
, crtc
);
6971 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6972 enum pipe pipe
= crtc
->pipe
;
6974 if ((update_pipes
& BIT(pipe
)) == 0)
6977 drm_WARN_ON(&dev_priv
->drm
, skl_ddb_allocation_overlaps(&new_crtc_state
->wm
.skl
.ddb
,
6978 entries
, I915_MAX_PIPES
, pipe
));
6980 entries
[pipe
] = new_crtc_state
->wm
.skl
.ddb
;
6981 update_pipes
&= ~BIT(pipe
);
6983 intel_update_crtc(state
, crtc
);
6986 drm_WARN_ON(&dev_priv
->drm
, modeset_pipes
);
6987 drm_WARN_ON(&dev_priv
->drm
, update_pipes
);
6990 static void intel_atomic_commit_fence_wait(struct intel_atomic_state
*intel_state
)
6992 struct drm_i915_private
*i915
= to_i915(intel_state
->base
.dev
);
6993 struct drm_plane
*plane
;
6994 struct drm_plane_state
*new_plane_state
;
6997 for_each_new_plane_in_state(&intel_state
->base
, plane
, new_plane_state
, i
) {
6998 if (new_plane_state
->fence
) {
6999 ret
= dma_fence_wait_timeout(new_plane_state
->fence
, false,
7000 i915_fence_timeout(i915
));
7004 dma_fence_put(new_plane_state
->fence
);
7005 new_plane_state
->fence
= NULL
;
7010 static void intel_atomic_cleanup_work(struct work_struct
*work
)
7012 struct intel_atomic_state
*state
=
7013 container_of(work
, struct intel_atomic_state
, base
.commit_work
);
7014 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
7015 struct intel_crtc_state
*old_crtc_state
;
7016 struct intel_crtc
*crtc
;
7019 for_each_old_intel_crtc_in_state(state
, crtc
, old_crtc_state
, i
)
7020 intel_color_cleanup_commit(old_crtc_state
);
7022 drm_atomic_helper_cleanup_planes(&i915
->drm
, &state
->base
);
7023 drm_atomic_helper_commit_cleanup_done(&state
->base
);
7024 drm_atomic_state_put(&state
->base
);
7027 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state
*state
)
7029 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
7030 struct intel_plane
*plane
;
7031 struct intel_plane_state
*plane_state
;
7034 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
7035 struct drm_framebuffer
*fb
= plane_state
->hw
.fb
;
7042 cc_plane
= intel_fb_rc_ccs_cc_plane(fb
);
7047 * The layout of the fast clear color value expected by HW
7048 * (the DRM ABI requiring this value to be located in fb at
7049 * offset 0 of cc plane, plane #2 previous generations or
7050 * plane #1 for flat ccs):
7051 * - 4 x 4 bytes per-channel value
7052 * (in surface type specific float/int format provided by the fb user)
7053 * - 8 bytes native color value used by the display
7054 * (converted/written by GPU during a fast clear operation using the
7055 * above per-channel values)
7057 * The commit's FB prepare hook already ensured that FB obj is pinned and the
7058 * caller made sure that the object is synced wrt. the related color clear value
7061 ret
= i915_gem_object_read_from_page(intel_fb_obj(fb
),
7062 fb
->offsets
[cc_plane
] + 16,
7063 &plane_state
->ccval
,
7064 sizeof(plane_state
->ccval
));
7065 /* The above could only fail if the FB obj has an unexpected backing store type. */
7066 drm_WARN_ON(&i915
->drm
, ret
);
7070 static void intel_atomic_commit_tail(struct intel_atomic_state
*state
)
7072 struct drm_device
*dev
= state
->base
.dev
;
7073 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7074 struct intel_crtc_state
*new_crtc_state
, *old_crtc_state
;
7075 struct intel_crtc
*crtc
;
7076 struct intel_power_domain_mask put_domains
[I915_MAX_PIPES
] = {};
7077 intel_wakeref_t wakeref
= 0;
7080 intel_atomic_commit_fence_wait(state
);
7082 drm_atomic_helper_wait_for_dependencies(&state
->base
);
7083 drm_dp_mst_atomic_wait_for_dependencies(&state
->base
);
7084 intel_atomic_global_state_wait_for_dependencies(state
);
7087 * During full modesets we write a lot of registers, wait
7088 * for PLLs, etc. Doing that while DC states are enabled
7089 * is not a good idea.
7091 * During fastsets and other updates we also need to
7092 * disable DC states due to the following scenario:
7093 * 1. DC5 exit and PSR exit happen
7094 * 2. Some or all _noarm() registers are written
7095 * 3. Due to some long delay PSR is re-entered
7096 * 4. DC5 entry -> DMC saves the already written new
7097 * _noarm() registers and the old not yet written
7099 * 5. DC5 exit -> DMC restores a mixture of old and
7100 * new register values and arms the update
7101 * 6. PSR exit -> hardware latches a mixture of old and
7102 * new register values -> corrupted frame, or worse
7103 * 7. New _arm() registers are finally written
7104 * 8. Hardware finally latches a complete set of new
7105 * register values, and subsequent frames will be OK again
7107 * Also note that due to the pipe CSC hardware issues on
7108 * SKL/GLK DC states must remain off until the pipe CSC
7109 * state readout has happened. Otherwise we risk corrupting
7110 * the CSC latched register values with the readout (see
7111 * skl_read_csc() and skl_color_commit_noarm()).
7113 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_DC_OFF
);
7115 intel_atomic_prepare_plane_clear_colors(state
);
7117 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
7118 new_crtc_state
, i
) {
7119 if (intel_crtc_needs_modeset(new_crtc_state
) ||
7120 intel_crtc_needs_fastset(new_crtc_state
))
7121 intel_modeset_get_crtc_power_domains(new_crtc_state
, &put_domains
[crtc
->pipe
]);
7124 intel_commit_modeset_disables(state
);
7126 intel_dp_tunnel_atomic_alloc_bw(state
);
7128 /* FIXME: Eventually get rid of our crtc->config pointer */
7129 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
7130 crtc
->config
= new_crtc_state
;
7133 * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7134 * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7135 * index, cdclk/ddiclk frequencies are supposed to be configured before
7136 * the cdclk config is set.
7138 intel_pmdemand_pre_plane_update(state
);
7140 if (state
->modeset
) {
7141 drm_atomic_helper_update_legacy_modeset_state(dev
, &state
->base
);
7143 intel_set_cdclk_pre_plane_update(state
);
7145 intel_modeset_verify_disabled(state
);
7148 intel_sagv_pre_plane_update(state
);
7150 /* Complete the events for pipes that have now been disabled */
7151 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
7152 bool modeset
= intel_crtc_needs_modeset(new_crtc_state
);
7154 /* Complete events for now disable pipes here. */
7155 if (modeset
&& !new_crtc_state
->hw
.active
&& new_crtc_state
->uapi
.event
) {
7156 spin_lock_irq(&dev
->event_lock
);
7157 drm_crtc_send_vblank_event(&crtc
->base
,
7158 new_crtc_state
->uapi
.event
);
7159 spin_unlock_irq(&dev
->event_lock
);
7161 new_crtc_state
->uapi
.event
= NULL
;
7165 intel_encoders_update_prepare(state
);
7167 intel_dbuf_pre_plane_update(state
);
7168 intel_mbus_dbox_update(state
);
7170 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
7171 if (new_crtc_state
->do_async_flip
)
7172 intel_crtc_enable_flip_done(state
, crtc
);
7175 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7176 dev_priv
->display
.funcs
.display
->commit_modeset_enables(state
);
7179 intel_set_cdclk_post_plane_update(state
);
7181 intel_wait_for_vblank_workers(state
);
7183 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7184 * already, but still need the state for the delayed optimization. To
7186 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7187 * - schedule that vblank worker _before_ calling hw_done
7188 * - at the start of commit_tail, cancel it _synchrously
7189 * - switch over to the vblank wait helper in the core after that since
7190 * we don't need out special handling any more.
7192 drm_atomic_helper_wait_for_flip_done(dev
, &state
->base
);
7194 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
7195 if (new_crtc_state
->do_async_flip
)
7196 intel_crtc_disable_flip_done(state
, crtc
);
7198 intel_color_wait_commit(new_crtc_state
);
7202 * Now that the vblank has passed, we can go ahead and program the
7203 * optimal watermarks on platforms that need two-step watermark
7206 * TODO: Move this (and other cleanup) to an async worker eventually.
7208 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
7209 new_crtc_state
, i
) {
7211 * Gen2 reports pipe underruns whenever all planes are disabled.
7212 * So re-enable underrun reporting after some planes get enabled.
7214 * We do this before .optimize_watermarks() so that we have a
7215 * chance of catching underruns with the intermediate watermarks
7216 * vs. the new plane configuration.
7218 if (DISPLAY_VER(dev_priv
) == 2 && planes_enabling(old_crtc_state
, new_crtc_state
))
7219 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
7221 intel_optimize_watermarks(state
, crtc
);
7224 intel_dbuf_post_plane_update(state
);
7226 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
7227 intel_post_plane_update(state
, crtc
);
7229 intel_modeset_put_crtc_power_domains(crtc
, &put_domains
[crtc
->pipe
]);
7231 intel_modeset_verify_crtc(state
, crtc
);
7233 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7234 hsw_ips_post_update(state
, crtc
);
7237 * Activate DRRS after state readout to avoid
7238 * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7240 intel_drrs_activate(new_crtc_state
);
7243 * DSB cleanup is done in cleanup_work aligning with framebuffer
7244 * cleanup. So copy and reset the dsb structure to sync with
7245 * commit_done and later do dsb cleanup in cleanup_work.
7247 * FIXME get rid of this funny new->old swapping
7249 old_crtc_state
->dsb
= fetch_and_zero(&new_crtc_state
->dsb
);
7252 /* Underruns don't always raise interrupts, so check manually */
7253 intel_check_cpu_fifo_underruns(dev_priv
);
7254 intel_check_pch_fifo_underruns(dev_priv
);
7257 intel_verify_planes(state
);
7259 intel_sagv_post_plane_update(state
);
7260 intel_pmdemand_post_plane_update(state
);
7262 drm_atomic_helper_commit_hw_done(&state
->base
);
7263 intel_atomic_global_state_commit_done(state
);
7265 if (state
->modeset
) {
7266 /* As one of the primary mmio accessors, KMS has a high
7267 * likelihood of triggering bugs in unclaimed access. After we
7268 * finish modesetting, see if an error has been flagged, and if
7269 * so enable debugging for the next modeset - and hope we catch
7272 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv
->uncore
);
7275 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7276 * toggling overhead at and above 60 FPS.
7278 intel_display_power_put_async_delay(dev_priv
, POWER_DOMAIN_DC_OFF
, wakeref
, 17);
7279 intel_runtime_pm_put(&dev_priv
->runtime_pm
, state
->wakeref
);
7282 * Defer the cleanup of the old state to a separate worker to not
7283 * impede the current task (userspace for blocking modesets) that
7284 * are executed inline. For out-of-line asynchronous modesets/flips,
7285 * deferring to a new worker seems overkill, but we would place a
7286 * schedule point (cond_resched()) here anyway to keep latencies
7289 INIT_WORK(&state
->base
.commit_work
, intel_atomic_cleanup_work
);
7290 queue_work(system_highpri_wq
, &state
->base
.commit_work
);
7293 static void intel_atomic_commit_work(struct work_struct
*work
)
7295 struct intel_atomic_state
*state
=
7296 container_of(work
, struct intel_atomic_state
, base
.commit_work
);
7298 intel_atomic_commit_tail(state
);
7301 static void intel_atomic_track_fbs(struct intel_atomic_state
*state
)
7303 struct intel_plane_state
*old_plane_state
, *new_plane_state
;
7304 struct intel_plane
*plane
;
7307 for_each_oldnew_intel_plane_in_state(state
, plane
, old_plane_state
,
7309 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state
->hw
.fb
),
7310 to_intel_frontbuffer(new_plane_state
->hw
.fb
),
7311 plane
->frontbuffer_bit
);
7314 static int intel_atomic_setup_commit(struct intel_atomic_state
*state
, bool nonblock
)
7318 ret
= drm_atomic_helper_setup_commit(&state
->base
, nonblock
);
7322 ret
= intel_atomic_global_state_setup_commit(state
);
7329 static int intel_atomic_swap_state(struct intel_atomic_state
*state
)
7333 ret
= drm_atomic_helper_swap_state(&state
->base
, true);
7337 intel_atomic_swap_global_state(state
);
7339 intel_shared_dpll_swap_state(state
);
7341 intel_atomic_track_fbs(state
);
7346 int intel_atomic_commit(struct drm_device
*dev
, struct drm_atomic_state
*_state
,
7349 struct intel_atomic_state
*state
= to_intel_atomic_state(_state
);
7350 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7353 state
->wakeref
= intel_runtime_pm_get(&dev_priv
->runtime_pm
);
7356 * The intel_legacy_cursor_update() fast path takes care
7357 * of avoiding the vblank waits for simple cursor
7358 * movement and flips. For cursor on/off and size changes,
7359 * we want to perform the vblank waits so that watermark
7360 * updates happen during the correct frames. Gen9+ have
7361 * double buffered watermarks and so shouldn't need this.
7363 * Unset state->legacy_cursor_update before the call to
7364 * drm_atomic_helper_setup_commit() because otherwise
7365 * drm_atomic_helper_wait_for_flip_done() is a noop and
7366 * we get FIFO underruns because we didn't wait
7369 * FIXME doing watermarks and fb cleanup from a vblank worker
7370 * (assuming we had any) would solve these problems.
7372 if (DISPLAY_VER(dev_priv
) < 9 && state
->base
.legacy_cursor_update
) {
7373 struct intel_crtc_state
*new_crtc_state
;
7374 struct intel_crtc
*crtc
;
7377 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
7378 if (new_crtc_state
->wm
.need_postvbl_update
||
7379 new_crtc_state
->update_wm_post
)
7380 state
->base
.legacy_cursor_update
= false;
7383 ret
= intel_atomic_prepare_commit(state
);
7385 drm_dbg_atomic(&dev_priv
->drm
,
7386 "Preparing state failed with %i\n", ret
);
7387 intel_runtime_pm_put(&dev_priv
->runtime_pm
, state
->wakeref
);
7391 ret
= intel_atomic_setup_commit(state
, nonblock
);
7393 ret
= intel_atomic_swap_state(state
);
7396 struct intel_crtc_state
*new_crtc_state
;
7397 struct intel_crtc
*crtc
;
7400 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
7401 intel_color_cleanup_commit(new_crtc_state
);
7403 drm_atomic_helper_unprepare_planes(dev
, &state
->base
);
7404 intel_runtime_pm_put(&dev_priv
->runtime_pm
, state
->wakeref
);
7408 drm_atomic_state_get(&state
->base
);
7409 INIT_WORK(&state
->base
.commit_work
, intel_atomic_commit_work
);
7411 if (nonblock
&& state
->modeset
) {
7412 queue_work(dev_priv
->display
.wq
.modeset
, &state
->base
.commit_work
);
7413 } else if (nonblock
) {
7414 queue_work(dev_priv
->display
.wq
.flip
, &state
->base
.commit_work
);
7417 flush_workqueue(dev_priv
->display
.wq
.modeset
);
7418 intel_atomic_commit_tail(state
);
7425 * intel_plane_destroy - destroy a plane
7426 * @plane: plane to destroy
7428 * Common destruction function for all types of planes (primary, cursor,
7431 void intel_plane_destroy(struct drm_plane
*plane
)
7433 drm_plane_cleanup(plane
);
7434 kfree(to_intel_plane(plane
));
7437 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device
*dev
, void *data
,
7438 struct drm_file
*file
)
7440 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
7441 struct drm_crtc
*drmmode_crtc
;
7442 struct intel_crtc
*crtc
;
7444 drmmode_crtc
= drm_crtc_find(dev
, file
, pipe_from_crtc_id
->crtc_id
);
7448 crtc
= to_intel_crtc(drmmode_crtc
);
7449 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
7454 static u32
intel_encoder_possible_clones(struct intel_encoder
*encoder
)
7456 struct drm_device
*dev
= encoder
->base
.dev
;
7457 struct intel_encoder
*source_encoder
;
7458 u32 possible_clones
= 0;
7460 for_each_intel_encoder(dev
, source_encoder
) {
7461 if (encoders_cloneable(encoder
, source_encoder
))
7462 possible_clones
|= drm_encoder_mask(&source_encoder
->base
);
7465 return possible_clones
;
7468 static u32
intel_encoder_possible_crtcs(struct intel_encoder
*encoder
)
7470 struct drm_device
*dev
= encoder
->base
.dev
;
7471 struct intel_crtc
*crtc
;
7472 u32 possible_crtcs
= 0;
7474 for_each_intel_crtc_in_pipe_mask(dev
, crtc
, encoder
->pipe_mask
)
7475 possible_crtcs
|= drm_crtc_mask(&crtc
->base
);
7477 return possible_crtcs
;
7480 static bool ilk_has_edp_a(struct drm_i915_private
*dev_priv
)
7482 if (!IS_MOBILE(dev_priv
))
7485 if ((intel_de_read(dev_priv
, DP_A
) & DP_DETECTED
) == 0)
7488 if (IS_IRONLAKE(dev_priv
) && (intel_de_read(dev_priv
, FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
7494 static bool intel_ddi_crt_present(struct drm_i915_private
*dev_priv
)
7496 if (DISPLAY_VER(dev_priv
) >= 9)
7499 if (IS_HASWELL_ULT(dev_priv
) || IS_BROADWELL_ULT(dev_priv
))
7502 if (HAS_PCH_LPT_H(dev_priv
) &&
7503 intel_de_read(dev_priv
, SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
7506 /* DDI E can't be used if DDI A requires 4 lanes */
7507 if (intel_de_read(dev_priv
, DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
7510 if (!dev_priv
->display
.vbt
.int_crt_support
)
7516 bool assert_port_valid(struct drm_i915_private
*i915
, enum port port
)
7518 return !drm_WARN(&i915
->drm
, !(DISPLAY_RUNTIME_INFO(i915
)->port_mask
& BIT(port
)),
7519 "Platform does not support port %c\n", port_name(port
));
7522 void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
7524 struct intel_encoder
*encoder
;
7525 bool dpd_is_edp
= false;
7527 intel_pps_unlock_regs_wa(dev_priv
);
7529 if (!HAS_DISPLAY(dev_priv
))
7532 if (HAS_DDI(dev_priv
)) {
7533 if (intel_ddi_crt_present(dev_priv
))
7534 intel_crt_init(dev_priv
);
7536 intel_bios_for_each_encoder(dev_priv
, intel_ddi_init
);
7538 if (IS_GEMINILAKE(dev_priv
) || IS_BROXTON(dev_priv
))
7539 vlv_dsi_init(dev_priv
);
7540 } else if (HAS_PCH_SPLIT(dev_priv
)) {
7544 * intel_edp_init_connector() depends on this completing first,
7545 * to prevent the registration of both eDP and LVDS and the
7546 * incorrect sharing of the PPS.
7548 intel_lvds_init(dev_priv
);
7549 intel_crt_init(dev_priv
);
7551 dpd_is_edp
= intel_dp_is_port_edp(dev_priv
, PORT_D
);
7553 if (ilk_has_edp_a(dev_priv
))
7554 g4x_dp_init(dev_priv
, DP_A
, PORT_A
);
7556 if (intel_de_read(dev_priv
, PCH_HDMIB
) & SDVO_DETECTED
) {
7557 /* PCH SDVOB multiplex with HDMIB */
7558 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
7560 g4x_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
7561 if (!found
&& (intel_de_read(dev_priv
, PCH_DP_B
) & DP_DETECTED
))
7562 g4x_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
7565 if (intel_de_read(dev_priv
, PCH_HDMIC
) & SDVO_DETECTED
)
7566 g4x_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
7568 if (!dpd_is_edp
&& intel_de_read(dev_priv
, PCH_HDMID
) & SDVO_DETECTED
)
7569 g4x_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
7571 if (intel_de_read(dev_priv
, PCH_DP_C
) & DP_DETECTED
)
7572 g4x_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
7574 if (intel_de_read(dev_priv
, PCH_DP_D
) & DP_DETECTED
)
7575 g4x_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
7576 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
7577 bool has_edp
, has_port
;
7579 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->display
.vbt
.int_crt_support
)
7580 intel_crt_init(dev_priv
);
7583 * The DP_DETECTED bit is the latched state of the DDC
7584 * SDA pin at boot. However since eDP doesn't require DDC
7585 * (no way to plug in a DP->HDMI dongle) the DDC pins for
7586 * eDP ports may have been muxed to an alternate function.
7587 * Thus we can't rely on the DP_DETECTED bit alone to detect
7588 * eDP ports. Consult the VBT as well as DP_DETECTED to
7591 * Sadly the straps seem to be missing sometimes even for HDMI
7592 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7593 * and VBT for the presence of the port. Additionally we can't
7594 * trust the port type the VBT declares as we've seen at least
7595 * HDMI ports that the VBT claim are DP or eDP.
7597 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_B
);
7598 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
7599 if (intel_de_read(dev_priv
, VLV_DP_B
) & DP_DETECTED
|| has_port
)
7600 has_edp
&= g4x_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
7601 if ((intel_de_read(dev_priv
, VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
7602 g4x_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
7604 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_C
);
7605 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
7606 if (intel_de_read(dev_priv
, VLV_DP_C
) & DP_DETECTED
|| has_port
)
7607 has_edp
&= g4x_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
7608 if ((intel_de_read(dev_priv
, VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
7609 g4x_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
7611 if (IS_CHERRYVIEW(dev_priv
)) {
7613 * eDP not supported on port D,
7614 * so no need to worry about it
7616 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
7617 if (intel_de_read(dev_priv
, CHV_DP_D
) & DP_DETECTED
|| has_port
)
7618 g4x_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
7619 if (intel_de_read(dev_priv
, CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
7620 g4x_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
7623 vlv_dsi_init(dev_priv
);
7624 } else if (IS_PINEVIEW(dev_priv
)) {
7625 intel_lvds_init(dev_priv
);
7626 intel_crt_init(dev_priv
);
7627 } else if (IS_DISPLAY_VER(dev_priv
, 3, 4)) {
7630 if (IS_MOBILE(dev_priv
))
7631 intel_lvds_init(dev_priv
);
7633 intel_crt_init(dev_priv
);
7635 if (intel_de_read(dev_priv
, GEN3_SDVOB
) & SDVO_DETECTED
) {
7636 drm_dbg_kms(&dev_priv
->drm
, "probing SDVOB\n");
7637 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
7638 if (!found
&& IS_G4X(dev_priv
)) {
7639 drm_dbg_kms(&dev_priv
->drm
,
7640 "probing HDMI on SDVOB\n");
7641 g4x_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
7644 if (!found
&& IS_G4X(dev_priv
))
7645 g4x_dp_init(dev_priv
, DP_B
, PORT_B
);
7648 /* Before G4X SDVOC doesn't have its own detect register */
7650 if (intel_de_read(dev_priv
, GEN3_SDVOB
) & SDVO_DETECTED
) {
7651 drm_dbg_kms(&dev_priv
->drm
, "probing SDVOC\n");
7652 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
7655 if (!found
&& (intel_de_read(dev_priv
, GEN3_SDVOC
) & SDVO_DETECTED
)) {
7657 if (IS_G4X(dev_priv
)) {
7658 drm_dbg_kms(&dev_priv
->drm
,
7659 "probing HDMI on SDVOC\n");
7660 g4x_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
7662 if (IS_G4X(dev_priv
))
7663 g4x_dp_init(dev_priv
, DP_C
, PORT_C
);
7666 if (IS_G4X(dev_priv
) && (intel_de_read(dev_priv
, DP_D
) & DP_DETECTED
))
7667 g4x_dp_init(dev_priv
, DP_D
, PORT_D
);
7669 if (SUPPORTS_TV(dev_priv
))
7670 intel_tv_init(dev_priv
);
7671 } else if (DISPLAY_VER(dev_priv
) == 2) {
7672 if (IS_I85X(dev_priv
))
7673 intel_lvds_init(dev_priv
);
7675 intel_crt_init(dev_priv
);
7676 intel_dvo_init(dev_priv
);
7679 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
7680 encoder
->base
.possible_crtcs
=
7681 intel_encoder_possible_crtcs(encoder
);
7682 encoder
->base
.possible_clones
=
7683 intel_encoder_possible_clones(encoder
);
7686 intel_init_pch_refclk(dev_priv
);
7688 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
7691 static int max_dotclock(struct drm_i915_private
*i915
)
7693 int max_dotclock
= i915
->max_dotclk_freq
;
7695 /* icl+ might use bigjoiner */
7696 if (DISPLAY_VER(i915
) >= 11)
7699 return max_dotclock
;
7702 enum drm_mode_status
intel_mode_valid(struct drm_device
*dev
,
7703 const struct drm_display_mode
*mode
)
7705 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7706 int hdisplay_max
, htotal_max
;
7707 int vdisplay_max
, vtotal_max
;
7710 * Can't reject DBLSCAN here because Xorg ddxen can add piles
7711 * of DBLSCAN modes to the output's mode list when they detect
7712 * the scaling mode property on the connector. And they don't
7713 * ask the kernel to validate those modes in any way until
7714 * modeset time at which point the client gets a protocol error.
7715 * So in order to not upset those clients we silently ignore the
7716 * DBLSCAN flag on such connectors. For other connectors we will
7717 * reject modes with the DBLSCAN flag in encoder->compute_config().
7718 * And we always reject DBLSCAN modes in connector->mode_valid()
7719 * as we never want such modes on the connector's mode list.
7722 if (mode
->vscan
> 1)
7723 return MODE_NO_VSCAN
;
7725 if (mode
->flags
& DRM_MODE_FLAG_HSKEW
)
7726 return MODE_H_ILLEGAL
;
7728 if (mode
->flags
& (DRM_MODE_FLAG_CSYNC
|
7729 DRM_MODE_FLAG_NCSYNC
|
7730 DRM_MODE_FLAG_PCSYNC
))
7733 if (mode
->flags
& (DRM_MODE_FLAG_BCAST
|
7734 DRM_MODE_FLAG_PIXMUX
|
7735 DRM_MODE_FLAG_CLKDIV2
))
7739 * Reject clearly excessive dotclocks early to
7740 * avoid having to worry about huge integers later.
7742 if (mode
->clock
> max_dotclock(dev_priv
))
7743 return MODE_CLOCK_HIGH
;
7745 /* Transcoder timing limits */
7746 if (DISPLAY_VER(dev_priv
) >= 11) {
7747 hdisplay_max
= 16384;
7748 vdisplay_max
= 8192;
7751 } else if (DISPLAY_VER(dev_priv
) >= 9 ||
7752 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
)) {
7753 hdisplay_max
= 8192; /* FDI max 4096 handled elsewhere */
7754 vdisplay_max
= 4096;
7757 } else if (DISPLAY_VER(dev_priv
) >= 3) {
7758 hdisplay_max
= 4096;
7759 vdisplay_max
= 4096;
7763 hdisplay_max
= 2048;
7764 vdisplay_max
= 2048;
7769 if (mode
->hdisplay
> hdisplay_max
||
7770 mode
->hsync_start
> htotal_max
||
7771 mode
->hsync_end
> htotal_max
||
7772 mode
->htotal
> htotal_max
)
7773 return MODE_H_ILLEGAL
;
7775 if (mode
->vdisplay
> vdisplay_max
||
7776 mode
->vsync_start
> vtotal_max
||
7777 mode
->vsync_end
> vtotal_max
||
7778 mode
->vtotal
> vtotal_max
)
7779 return MODE_V_ILLEGAL
;
7784 enum drm_mode_status
intel_cpu_transcoder_mode_valid(struct drm_i915_private
*dev_priv
,
7785 const struct drm_display_mode
*mode
)
7788 * Additional transcoder timing limits,
7789 * excluding BXT/GLK DSI transcoders.
7791 if (DISPLAY_VER(dev_priv
) >= 5) {
7792 if (mode
->hdisplay
< 64 ||
7793 mode
->htotal
- mode
->hdisplay
< 32)
7794 return MODE_H_ILLEGAL
;
7796 if (mode
->vtotal
- mode
->vdisplay
< 5)
7797 return MODE_V_ILLEGAL
;
7799 if (mode
->htotal
- mode
->hdisplay
< 32)
7800 return MODE_H_ILLEGAL
;
7802 if (mode
->vtotal
- mode
->vdisplay
< 3)
7803 return MODE_V_ILLEGAL
;
7807 * Cantiga+ cannot handle modes with a hsync front porch of 0.
7808 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7810 if ((DISPLAY_VER(dev_priv
) >= 5 || IS_G4X(dev_priv
)) &&
7811 mode
->hsync_start
== mode
->hdisplay
)
7812 return MODE_H_ILLEGAL
;
7817 enum drm_mode_status
7818 intel_mode_valid_max_plane_size(struct drm_i915_private
*dev_priv
,
7819 const struct drm_display_mode
*mode
,
7822 int plane_width_max
, plane_height_max
;
7825 * intel_mode_valid() should be
7826 * sufficient on older platforms.
7828 if (DISPLAY_VER(dev_priv
) < 9)
7832 * Most people will probably want a fullscreen
7833 * plane so let's not advertize modes that are
7836 if (DISPLAY_VER(dev_priv
) >= 11) {
7837 plane_width_max
= 5120 << bigjoiner
;
7838 plane_height_max
= 4320;
7840 plane_width_max
= 5120;
7841 plane_height_max
= 4096;
7844 if (mode
->hdisplay
> plane_width_max
)
7845 return MODE_H_ILLEGAL
;
7847 if (mode
->vdisplay
> plane_height_max
)
7848 return MODE_V_ILLEGAL
;
7853 static const struct intel_display_funcs skl_display_funcs
= {
7854 .get_pipe_config
= hsw_get_pipe_config
,
7855 .crtc_enable
= hsw_crtc_enable
,
7856 .crtc_disable
= hsw_crtc_disable
,
7857 .commit_modeset_enables
= skl_commit_modeset_enables
,
7858 .get_initial_plane_config
= skl_get_initial_plane_config
,
7859 .fixup_initial_plane_config
= skl_fixup_initial_plane_config
,
7862 static const struct intel_display_funcs ddi_display_funcs
= {
7863 .get_pipe_config
= hsw_get_pipe_config
,
7864 .crtc_enable
= hsw_crtc_enable
,
7865 .crtc_disable
= hsw_crtc_disable
,
7866 .commit_modeset_enables
= intel_commit_modeset_enables
,
7867 .get_initial_plane_config
= i9xx_get_initial_plane_config
,
7868 .fixup_initial_plane_config
= i9xx_fixup_initial_plane_config
,
7871 static const struct intel_display_funcs pch_split_display_funcs
= {
7872 .get_pipe_config
= ilk_get_pipe_config
,
7873 .crtc_enable
= ilk_crtc_enable
,
7874 .crtc_disable
= ilk_crtc_disable
,
7875 .commit_modeset_enables
= intel_commit_modeset_enables
,
7876 .get_initial_plane_config
= i9xx_get_initial_plane_config
,
7877 .fixup_initial_plane_config
= i9xx_fixup_initial_plane_config
,
7880 static const struct intel_display_funcs vlv_display_funcs
= {
7881 .get_pipe_config
= i9xx_get_pipe_config
,
7882 .crtc_enable
= valleyview_crtc_enable
,
7883 .crtc_disable
= i9xx_crtc_disable
,
7884 .commit_modeset_enables
= intel_commit_modeset_enables
,
7885 .get_initial_plane_config
= i9xx_get_initial_plane_config
,
7886 .fixup_initial_plane_config
= i9xx_fixup_initial_plane_config
,
7889 static const struct intel_display_funcs i9xx_display_funcs
= {
7890 .get_pipe_config
= i9xx_get_pipe_config
,
7891 .crtc_enable
= i9xx_crtc_enable
,
7892 .crtc_disable
= i9xx_crtc_disable
,
7893 .commit_modeset_enables
= intel_commit_modeset_enables
,
7894 .get_initial_plane_config
= i9xx_get_initial_plane_config
,
7895 .fixup_initial_plane_config
= i9xx_fixup_initial_plane_config
,
7899 * intel_init_display_hooks - initialize the display modesetting hooks
7900 * @dev_priv: device private
7902 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
7904 if (DISPLAY_VER(dev_priv
) >= 9) {
7905 dev_priv
->display
.funcs
.display
= &skl_display_funcs
;
7906 } else if (HAS_DDI(dev_priv
)) {
7907 dev_priv
->display
.funcs
.display
= &ddi_display_funcs
;
7908 } else if (HAS_PCH_SPLIT(dev_priv
)) {
7909 dev_priv
->display
.funcs
.display
= &pch_split_display_funcs
;
7910 } else if (IS_CHERRYVIEW(dev_priv
) ||
7911 IS_VALLEYVIEW(dev_priv
)) {
7912 dev_priv
->display
.funcs
.display
= &vlv_display_funcs
;
7914 dev_priv
->display
.funcs
.display
= &i9xx_display_funcs
;
7918 int intel_initial_commit(struct drm_device
*dev
)
7920 struct drm_atomic_state
*state
= NULL
;
7921 struct drm_modeset_acquire_ctx ctx
;
7922 struct intel_crtc
*crtc
;
7925 state
= drm_atomic_state_alloc(dev
);
7929 drm_modeset_acquire_init(&ctx
, 0);
7931 state
->acquire_ctx
= &ctx
;
7932 to_intel_atomic_state(state
)->internal
= true;
7935 for_each_intel_crtc(dev
, crtc
) {
7936 struct intel_crtc_state
*crtc_state
=
7937 intel_atomic_get_crtc_state(state
, crtc
);
7939 if (IS_ERR(crtc_state
)) {
7940 ret
= PTR_ERR(crtc_state
);
7944 if (crtc_state
->hw
.active
) {
7945 struct intel_encoder
*encoder
;
7947 ret
= drm_atomic_add_affected_planes(state
, &crtc
->base
);
7952 * FIXME hack to force a LUT update to avoid the
7953 * plane update forcing the pipe gamma on without
7954 * having a proper LUT loaded. Remove once we
7955 * have readout for pipe gamma enable.
7957 crtc_state
->uapi
.color_mgmt_changed
= true;
7959 for_each_intel_encoder_mask(dev
, encoder
,
7960 crtc_state
->uapi
.encoder_mask
) {
7961 if (encoder
->initial_fastset_check
&&
7962 !encoder
->initial_fastset_check(encoder
, crtc_state
)) {
7963 ret
= drm_atomic_add_affected_connectors(state
,
7972 ret
= drm_atomic_commit(state
);
7975 if (ret
== -EDEADLK
) {
7976 drm_atomic_state_clear(state
);
7977 drm_modeset_backoff(&ctx
);
7981 drm_atomic_state_put(state
);
7983 drm_modeset_drop_locks(&ctx
);
7984 drm_modeset_acquire_fini(&ctx
);
7989 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
7991 struct intel_crtc
*crtc
= intel_crtc_for_pipe(dev_priv
, pipe
);
7992 enum transcoder cpu_transcoder
= (enum transcoder
)pipe
;
7993 /* 640x480@60Hz, ~25175 kHz */
7994 struct dpll clock
= {
8004 drm_WARN_ON(&dev_priv
->drm
,
8005 i9xx_calc_dpll_params(48000, &clock
) != 25154);
8007 drm_dbg_kms(&dev_priv
->drm
,
8008 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8009 pipe_name(pipe
), clock
.vco
, clock
.dot
);
8011 fp
= i9xx_dpll_compute_fp(&clock
);
8012 dpll
= DPLL_DVO_2X_MODE
|
8014 ((clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
) |
8015 PLL_P2_DIVIDE_BY_4
|
8016 PLL_REF_INPUT_DREFCLK
|
8019 intel_de_write(dev_priv
, TRANS_HTOTAL(cpu_transcoder
),
8020 HACTIVE(640 - 1) | HTOTAL(800 - 1));
8021 intel_de_write(dev_priv
, TRANS_HBLANK(cpu_transcoder
),
8022 HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8023 intel_de_write(dev_priv
, TRANS_HSYNC(cpu_transcoder
),
8024 HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8025 intel_de_write(dev_priv
, TRANS_VTOTAL(cpu_transcoder
),
8026 VACTIVE(480 - 1) | VTOTAL(525 - 1));
8027 intel_de_write(dev_priv
, TRANS_VBLANK(cpu_transcoder
),
8028 VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8029 intel_de_write(dev_priv
, TRANS_VSYNC(cpu_transcoder
),
8030 VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8031 intel_de_write(dev_priv
, PIPESRC(pipe
),
8032 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8034 intel_de_write(dev_priv
, FP0(pipe
), fp
);
8035 intel_de_write(dev_priv
, FP1(pipe
), fp
);
8038 * Apparently we need to have VGA mode enabled prior to changing
8039 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8040 * dividers, even though the register value does change.
8042 intel_de_write(dev_priv
, DPLL(pipe
), dpll
& ~DPLL_VGA_MODE_DIS
);
8043 intel_de_write(dev_priv
, DPLL(pipe
), dpll
);
8045 /* Wait for the clocks to stabilize. */
8046 intel_de_posting_read(dev_priv
, DPLL(pipe
));
8049 /* The pixel multiplier can only be updated once the
8050 * DPLL is enabled and the clocks are stable.
8052 * So write it again.
8054 intel_de_write(dev_priv
, DPLL(pipe
), dpll
);
8056 /* We do this three times for luck */
8057 for (i
= 0; i
< 3 ; i
++) {
8058 intel_de_write(dev_priv
, DPLL(pipe
), dpll
);
8059 intel_de_posting_read(dev_priv
, DPLL(pipe
));
8060 udelay(150); /* wait for warmup */
8063 intel_de_write(dev_priv
, TRANSCONF(pipe
), TRANSCONF_ENABLE
);
8064 intel_de_posting_read(dev_priv
, TRANSCONF(pipe
));
8066 intel_wait_for_pipe_scanline_moving(crtc
);
8069 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
8071 struct intel_crtc
*crtc
= intel_crtc_for_pipe(dev_priv
, pipe
);
8073 drm_dbg_kms(&dev_priv
->drm
, "disabling pipe %c due to force quirk\n",
8076 drm_WARN_ON(&dev_priv
->drm
,
8077 intel_de_read(dev_priv
, DSPCNTR(PLANE_A
)) & DISP_ENABLE
);
8078 drm_WARN_ON(&dev_priv
->drm
,
8079 intel_de_read(dev_priv
, DSPCNTR(PLANE_B
)) & DISP_ENABLE
);
8080 drm_WARN_ON(&dev_priv
->drm
,
8081 intel_de_read(dev_priv
, DSPCNTR(PLANE_C
)) & DISP_ENABLE
);
8082 drm_WARN_ON(&dev_priv
->drm
,
8083 intel_de_read(dev_priv
, CURCNTR(PIPE_A
)) & MCURSOR_MODE_MASK
);
8084 drm_WARN_ON(&dev_priv
->drm
,
8085 intel_de_read(dev_priv
, CURCNTR(PIPE_B
)) & MCURSOR_MODE_MASK
);
8087 intel_de_write(dev_priv
, TRANSCONF(pipe
), 0);
8088 intel_de_posting_read(dev_priv
, TRANSCONF(pipe
));
8090 intel_wait_for_pipe_scanline_stopped(crtc
);
8092 intel_de_write(dev_priv
, DPLL(pipe
), DPLL_VGA_MODE_DIS
);
8093 intel_de_posting_read(dev_priv
, DPLL(pipe
));
8096 void intel_hpd_poll_fini(struct drm_i915_private
*i915
)
8098 struct intel_connector
*connector
;
8099 struct drm_connector_list_iter conn_iter
;
8101 /* Kill all the work that may have been queued by hpd. */
8102 drm_connector_list_iter_begin(&i915
->drm
, &conn_iter
);
8103 for_each_intel_connector_iter(connector
, &conn_iter
) {
8104 if (connector
->modeset_retry_work
.func
&&
8105 cancel_work_sync(&connector
->modeset_retry_work
))
8106 drm_connector_put(&connector
->base
);
8107 if (connector
->hdcp
.shim
) {
8108 cancel_delayed_work_sync(&connector
->hdcp
.check_work
);
8109 cancel_work_sync(&connector
->hdcp
.prop_work
);
8112 drm_connector_list_iter_end(&conn_iter
);
8115 bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*i915
)
8117 return DISPLAY_VER(i915
) >= 6 && i915_vtd_active(i915
);