drivers/gpu/drm/i915/gvt/fb_decoder.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Kevin Tian <kevin.tian@intel.com>
  25  *
  26  * Contributors:
  27  *    Bing Niu <bing.niu@intel.com>
  28  *    Xu Han <xu.han@intel.com>
  29  *    Ping Gao <ping.a.gao@intel.com>
  30  *    Xiaoguang Chen <xiaoguang.chen@intel.com>
  31  *    Yang Liu <yang2.liu@intel.com>
  32  *    Tina Zhang <tina.zhang@intel.com>
  33  *
  34  */
  35
  36 #include <uapi/drm/drm_fourcc.h>
  37 #include "i915_drv.h"
  38 #include "gvt.h"
  39 #include "i915_pvinfo.h"
  40
  41 #define PRIMARY_FORMAT_NUM      16
  42 struct pixel_format {
  43         int     drm_format;     /* Pixel format in DRM definition */
  44         int     bpp;            /* Bits per pixel, 0 indicates invalid */
  45         char    *desc;          /* The description */
  46 };
  47
  48 static struct pixel_format bdw_pixel_formats[] = {
  49         {DRM_FORMAT_C8, 8, "8-bit Indexed"},
  50         {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
  51         {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
  52         {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
  53
  54         {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
  55         {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
  56
  57         /* non-supported format has bpp default to 0 */
  58         {0, 0, NULL},
  59 };
  60
  61 static struct pixel_format skl_pixel_formats[] = {
  62         {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
  63         {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
  64         {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
  65         {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
  66
  67         {DRM_FORMAT_C8, 8, "8-bit Indexed"},
  68         {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
  69         {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
  70         {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
  71
  72         {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
  73         {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
  74         {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
  75         {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
  76
  77         /* non-supported format has bpp default to 0 */
  78         {0, 0, NULL},
  79 };
  80
  81 static int bdw_format_to_drm(int format)
  82 {
  83         int bdw_pixel_formats_index = 6;
  84
  85         switch (format) {
  86         case DISPPLANE_8BPP:
  87                 bdw_pixel_formats_index = 0;
  88                 break;
  89         case DISPPLANE_BGRX565:
  90                 bdw_pixel_formats_index = 1;
  91                 break;
  92         case DISPPLANE_BGRX888:
  93                 bdw_pixel_formats_index = 2;
  94                 break;
  95         case DISPPLANE_RGBX101010:
  96                 bdw_pixel_formats_index = 3;
  97                 break;
  98         case DISPPLANE_BGRX101010:
  99                 bdw_pixel_formats_index = 4;
 100                 break;
 101         case DISPPLANE_RGBX888:
 102                 bdw_pixel_formats_index = 5;
 103                 break;
 104
 105         default:
 106                 break;
 107         }
 108
 109         return bdw_pixel_formats_index;
 110 }
 111
 112 static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
 113         int yuv_order)
 114 {
 115         int skl_pixel_formats_index = 12;
 116
 117         switch (format) {
 118         case PLANE_CTL_FORMAT_INDEXED:
 119                 skl_pixel_formats_index = 4;
 120                 break;
 121         case PLANE_CTL_FORMAT_RGB_565:
 122                 skl_pixel_formats_index = 5;
 123                 break;
 124         case PLANE_CTL_FORMAT_XRGB_8888:
 125                 if (rgb_order)
 126                         skl_pixel_formats_index = alpha ? 6 : 7;
 127                 else
 128                         skl_pixel_formats_index = alpha ? 8 : 9;
 129                 break;
 130         case PLANE_CTL_FORMAT_XRGB_2101010:
 131                 skl_pixel_formats_index = rgb_order ? 10 : 11;
 132                 break;
 133         case PLANE_CTL_FORMAT_YUV422:
 134                 skl_pixel_formats_index = yuv_order >> 16;
 135                 if (skl_pixel_formats_index > 3)
 136                         return -EINVAL;
 137                 break;
 138
 139         default:
 140                 break;
 141         }
 142
 143         return skl_pixel_formats_index;
 144 }
 145
 146 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
 147         u32 tiled, int stride_mask, int bpp)
 148 {
 149         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 150
 151         u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
 152         u32 stride = stride_reg;
 153
 154         if (INTEL_GEN(dev_priv) >= 9) {
 155                 switch (tiled) {
 156                 case PLANE_CTL_TILED_LINEAR:
 157                         stride = stride_reg * 64;
 158                         break;
 159                 case PLANE_CTL_TILED_X:
 160                         stride = stride_reg * 512;
 161                         break;
 162                 case PLANE_CTL_TILED_Y:
 163                         stride = stride_reg * 128;
 164                         break;
 165                 case PLANE_CTL_TILED_YF:
 166                         if (bpp == 8)
 167                                 stride = stride_reg * 64;
 168                         else if (bpp == 16 || bpp == 32 || bpp == 64)
 169                                 stride = stride_reg * 128;
 170                         else
 171                                 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
 172                         break;
 173                 default:
 174                         gvt_dbg_core("skl: unsupported tile format:%x\n",
 175                                 tiled);
 176                 }
 177         }
 178
 179         return stride;
 180 }
 181
 182 static int get_active_pipe(struct intel_vgpu *vgpu)
 183 {
 184         int i;
 185
 186         for (i = 0; i < I915_MAX_PIPES; i++)
 187                 if (pipe_is_enabled(vgpu, i))
 188                         break;
 189
 190         return i;
 191 }
 192
 193 /**
 194  * intel_vgpu_decode_primary_plane - Decode primary plane
 195  * @vgpu: input vgpu
 196  * @plane: primary plane to save decoded info
 197  * This function is called for decoding plane
 198  *
 199  * Returns:
 200  * 0 on success, non-zero if failed.
 201  */
 202 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
 203         struct intel_vgpu_primary_plane_format *plane)
 204 {
 205         u32 val, fmt;
 206         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 207         int pipe;
 208
 209         pipe = get_active_pipe(vgpu);
 210         if (pipe >= I915_MAX_PIPES)
 211                 return -ENODEV;
 212
 213         val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
 214         plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
 215         if (!plane->enabled)
 216                 return -ENODEV;
 217
 218         if (INTEL_GEN(dev_priv) >= 9) {
 219                 plane->tiled = val & PLANE_CTL_TILED_MASK;
 220                 fmt = skl_format_to_drm(
 221                         val & PLANE_CTL_FORMAT_MASK,
 222                         val & PLANE_CTL_ORDER_RGBX,
 223                         val & PLANE_CTL_ALPHA_MASK,
 224                         val & PLANE_CTL_YUV422_ORDER_MASK);
 225
 226                 if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
 227                         gvt_vgpu_err("Out-of-bounds pixel format index\n");
 228                         return -EINVAL;
 229                 }
 230
 231                 plane->bpp = skl_pixel_formats[fmt].bpp;
 232                 plane->drm_format = skl_pixel_formats[fmt].drm_format;
 233         } else {
 234                 plane->tiled = val & DISPPLANE_TILED;
 235                 fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
 236                 plane->bpp = bdw_pixel_formats[fmt].bpp;
 237                 plane->drm_format = bdw_pixel_formats[fmt].drm_format;
 238         }
 239
 240         if (!plane->bpp) {
 241                 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
 242                 return -EINVAL;
 243         }
 244
 245         plane->hw_format = fmt;
 246
 247         plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
 248         if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
 249                 return  -EINVAL;
 250
 251         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
 252         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
 253                 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
 254                                 plane->base);
 255                 return  -EINVAL;
 256         }
 257
 258         plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
 259                 (INTEL_GEN(dev_priv) >= 9) ?
 260                         (_PRI_PLANE_STRIDE_MASK >> 6) :
 261                                 _PRI_PLANE_STRIDE_MASK, plane->bpp);
 262
 263         plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
 264                 _PIPE_H_SRCSZ_SHIFT;
 265         plane->width += 1;
 266         plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
 267                         _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
 268         plane->height += 1;     /* raw height is one minus the real value */
 269
 270         val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
 271         plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
 272                 _PRI_PLANE_X_OFF_SHIFT;
 273         plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
 274                 _PRI_PLANE_Y_OFF_SHIFT;
 275
 276         return 0;
 277 }
 278
 279 #define CURSOR_FORMAT_NUM       (1 << 6)
 280 struct cursor_mode_format {
 281         int     drm_format;     /* Pixel format in DRM definition */
 282         u8      bpp;            /* Bits per pixel; 0 indicates invalid */
 283         u32     width;          /* In pixel */
 284         u32     height;         /* In lines */
 285         char    *desc;          /* The description */
 286 };
 287
 288 static struct cursor_mode_format cursor_pixel_formats[] = {
 289         {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
 290         {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
 291         {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
 292         {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
 293
 294         /* non-supported format has bpp default to 0 */
 295         {0, 0, 0, 0, NULL},
 296 };
 297
 298 static int cursor_mode_to_drm(int mode)
 299 {
 300         int cursor_pixel_formats_index = 4;
 301
 302         switch (mode) {
 303         case MCURSOR_MODE_128_ARGB_AX:
 304                 cursor_pixel_formats_index = 0;
 305                 break;
 306         case MCURSOR_MODE_256_ARGB_AX:
 307                 cursor_pixel_formats_index = 1;
 308                 break;
 309         case MCURSOR_MODE_64_ARGB_AX:
 310                 cursor_pixel_formats_index = 2;
 311                 break;
 312         case MCURSOR_MODE_64_32B_AX:
 313                 cursor_pixel_formats_index = 3;
 314                 break;
 315
 316         default:
 317                 break;
 318         }
 319
 320         return cursor_pixel_formats_index;
 321 }
 322
 323 /**
 324  * intel_vgpu_decode_cursor_plane - Decode sprite plane
 325  * @vgpu: input vgpu
 326  * @plane: cursor plane to save decoded info
 327  * This function is called for decoding plane
 328  *
 329  * Returns:
 330  * 0 on success, non-zero if failed.
 331  */
 332 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
 333         struct intel_vgpu_cursor_plane_format *plane)
 334 {
 335         u32 val, mode, index;
 336         u32 alpha_plane, alpha_force;
 337         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 338         int pipe;
 339
 340         pipe = get_active_pipe(vgpu);
 341         if (pipe >= I915_MAX_PIPES)
 342                 return -ENODEV;
 343
 344         val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
 345         mode = val & MCURSOR_MODE;
 346         plane->enabled = (mode != MCURSOR_MODE_DISABLE);
 347         if (!plane->enabled)
 348                 return -ENODEV;
 349
 350         index = cursor_mode_to_drm(mode);
 351
 352         if (!cursor_pixel_formats[index].bpp) {
 353                 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
 354                 return -EINVAL;
 355         }
 356         plane->mode = mode;
 357         plane->bpp = cursor_pixel_formats[index].bpp;
 358         plane->drm_format = cursor_pixel_formats[index].drm_format;
 359         plane->width = cursor_pixel_formats[index].width;
 360         plane->height = cursor_pixel_formats[index].height;
 361
 362         alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
 363                                 _CURSOR_ALPHA_PLANE_SHIFT;
 364         alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
 365                                 _CURSOR_ALPHA_FORCE_SHIFT;
 366         if (alpha_plane || alpha_force)
 367                 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
 368                         alpha_plane, alpha_force);
 369
 370         plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
 371         if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
 372                 return  -EINVAL;
 373
 374         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
 375         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
 376                 gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
 377                                 plane->base);
 378                 return  -EINVAL;
 379         }
 380
 381         val = vgpu_vreg_t(vgpu, CURPOS(pipe));
 382         plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
 383         plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
 384         plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
 385         plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
 386
 387         plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
 388         plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));
 389         return 0;
 390 }
 391
 392 #define SPRITE_FORMAT_NUM       (1 << 3)
 393
 394 static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
 395         [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
 396         [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
 397         [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
 398         [0x4] = {DRM_FORMAT_AYUV, 32,
 399                 "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
 400 };
 401
 402 /**
 403  * intel_vgpu_decode_sprite_plane - Decode sprite plane
 404  * @vgpu: input vgpu
 405  * @plane: sprite plane to save decoded info
 406  * This function is called for decoding plane
 407  *
 408  * Returns:
 409  * 0 on success, non-zero if failed.
 410  */
 411 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
 412         struct intel_vgpu_sprite_plane_format *plane)
 413 {
 414         u32 val, fmt;
 415         u32 color_order, yuv_order;
 416         int drm_format;
 417         int pipe;
 418
 419         pipe = get_active_pipe(vgpu);
 420         if (pipe >= I915_MAX_PIPES)
 421                 return -ENODEV;
 422
 423         val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
 424         plane->enabled = !!(val & SPRITE_ENABLE);
 425         if (!plane->enabled)
 426                 return -ENODEV;
 427
 428         plane->tiled = !!(val & SPRITE_TILED);
 429         color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
 430         yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
 431                                 _SPRITE_YUV_ORDER_SHIFT;
 432
 433         fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
 434         if (!sprite_pixel_formats[fmt].bpp) {
 435                 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
 436                 return -EINVAL;
 437         }
 438         plane->hw_format = fmt;
 439         plane->bpp = sprite_pixel_formats[fmt].bpp;
 440         drm_format = sprite_pixel_formats[fmt].drm_format;
 441
 442         /* Order of RGB values in an RGBxxx buffer may be ordered RGB or
 443          * BGR depending on the state of the color_order field
 444          */
 445         if (!color_order) {
 446                 if (drm_format == DRM_FORMAT_XRGB2101010)
 447                         drm_format = DRM_FORMAT_XBGR2101010;
 448                 else if (drm_format == DRM_FORMAT_XRGB8888)
 449                         drm_format = DRM_FORMAT_XBGR8888;
 450         }
 451
 452         if (drm_format == DRM_FORMAT_YUV422) {
 453                 switch (yuv_order) {
 454                 case 0:
 455                         drm_format = DRM_FORMAT_YUYV;
 456                         break;
 457                 case 1:
 458                         drm_format = DRM_FORMAT_UYVY;
 459                         break;
 460                 case 2:
 461                         drm_format = DRM_FORMAT_YVYU;
 462                         break;
 463                 case 3:
 464                         drm_format = DRM_FORMAT_VYUY;
 465                         break;
 466                 default:
 467                         /* yuv_order has only 2 bits */
 468                         break;
 469                 }
 470         }
 471
 472         plane->drm_format = drm_format;
 473
 474         plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
 475         if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
 476                 return  -EINVAL;
 477
 478         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
 479         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
 480                 gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n",
 481                                 plane->base);
 482                 return  -EINVAL;
 483         }
 484
 485         plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &
 486                                 _SPRITE_STRIDE_MASK;
 487
 488         val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));
 489         plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
 490                 _SPRITE_SIZE_HEIGHT_SHIFT;
 491         plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
 492                 _SPRITE_SIZE_WIDTH_SHIFT;
 493         plane->height += 1;     /* raw height is one minus the real value */
 494         plane->width += 1;      /* raw width is one minus the real value */
 495
 496         val = vgpu_vreg_t(vgpu, SPRPOS(pipe));
 497         plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
 498         plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
 499
 500         val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));
 501         plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
 502                            _SPRITE_OFFSET_START_X_SHIFT;
 503         plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
 504                            _SPRITE_OFFSET_START_Y_SHIFT;
 505
 506         return 0;
 507 }