2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Zhi Wang <zhi.a.wang@intel.com>
27 * Ping Gao <ping.a.gao@intel.com>
28 * Tina Zhang <tina.zhang@intel.com>
29 * Chanbin Du <changbin.du@intel.com>
30 * Min He <min.he@intel.com>
31 * Bing Niu <bing.niu@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
36 #include <linux/kthread.h>
38 #include "gem/i915_gem_pm.h"
39 #include "gt/intel_context.h"
40 #include "gt/intel_ring.h"
43 #include "i915_gem_gtt.h"
46 #define RING_CTX_OFF(x) \
47 offsetof(struct execlist_ring_context, x)
49 static void set_context_pdp_root_pointer(
50 struct execlist_ring_context
*ring_context
,
55 for (i
= 0; i
< 8; i
++)
56 ring_context
->pdps
[i
].val
= pdp
[7 - i
];
59 static void update_shadow_pdps(struct intel_vgpu_workload
*workload
)
61 struct drm_i915_gem_object
*ctx_obj
=
62 workload
->req
->context
->state
->obj
;
63 struct execlist_ring_context
*shadow_ring_context
;
66 if (WARN_ON(!workload
->shadow_mm
))
69 if (WARN_ON(!atomic_read(&workload
->shadow_mm
->pincount
)))
72 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
73 shadow_ring_context
= kmap(page
);
74 set_context_pdp_root_pointer(shadow_ring_context
,
75 (void *)workload
->shadow_mm
->ppgtt_mm
.shadow_pdps
);
80 * when populating shadow ctx from guest, we should not overrride oa related
81 * registers, so that they will not be overlapped by guest oa configs. Thus
82 * made it possible to capture oa data from host for both host and guests.
84 static void sr_oa_regs(struct intel_vgpu_workload
*workload
,
85 u32
*reg_state
, bool save
)
87 struct drm_i915_private
*dev_priv
= workload
->vgpu
->gvt
->gt
->i915
;
88 u32 ctx_oactxctrl
= dev_priv
->perf
.ctx_oactxctrl_offset
;
89 u32 ctx_flexeu0
= dev_priv
->perf
.ctx_flexeu0_offset
;
92 i915_mmio_reg_offset(EU_PERF_CNTL0
),
93 i915_mmio_reg_offset(EU_PERF_CNTL1
),
94 i915_mmio_reg_offset(EU_PERF_CNTL2
),
95 i915_mmio_reg_offset(EU_PERF_CNTL3
),
96 i915_mmio_reg_offset(EU_PERF_CNTL4
),
97 i915_mmio_reg_offset(EU_PERF_CNTL5
),
98 i915_mmio_reg_offset(EU_PERF_CNTL6
),
101 if (workload
->engine
->id
!= RCS0
)
105 workload
->oactxctrl
= reg_state
[ctx_oactxctrl
+ 1];
107 for (i
= 0; i
< ARRAY_SIZE(workload
->flex_mmio
); i
++) {
108 u32 state_offset
= ctx_flexeu0
+ i
* 2;
110 workload
->flex_mmio
[i
] = reg_state
[state_offset
+ 1];
113 reg_state
[ctx_oactxctrl
] =
114 i915_mmio_reg_offset(GEN8_OACTXCONTROL
);
115 reg_state
[ctx_oactxctrl
+ 1] = workload
->oactxctrl
;
117 for (i
= 0; i
< ARRAY_SIZE(workload
->flex_mmio
); i
++) {
118 u32 state_offset
= ctx_flexeu0
+ i
* 2;
119 u32 mmio
= flex_mmio
[i
];
121 reg_state
[state_offset
] = mmio
;
122 reg_state
[state_offset
+ 1] = workload
->flex_mmio
[i
];
127 static int populate_shadow_context(struct intel_vgpu_workload
*workload
)
129 struct intel_vgpu
*vgpu
= workload
->vgpu
;
130 struct intel_gvt
*gvt
= vgpu
->gvt
;
131 struct drm_i915_gem_object
*ctx_obj
=
132 workload
->req
->context
->state
->obj
;
133 struct execlist_ring_context
*shadow_ring_context
;
136 unsigned long context_gpa
, context_page_num
;
139 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
140 shadow_ring_context
= kmap(page
);
142 sr_oa_regs(workload
, (u32
*)shadow_ring_context
, true);
143 #define COPY_REG(name) \
144 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
145 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
146 #define COPY_REG_MASKED(name) {\
147 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
148 + RING_CTX_OFF(name.val),\
149 &shadow_ring_context->name.val, 4);\
150 shadow_ring_context->name.val |= 0xffff << 16;\
153 COPY_REG_MASKED(ctx_ctrl
);
154 COPY_REG(ctx_timestamp
);
156 if (workload
->engine
->id
== RCS0
) {
157 COPY_REG(bb_per_ctx_ptr
);
158 COPY_REG(rcs_indirect_ctx
);
159 COPY_REG(rcs_indirect_ctx_offset
);
162 #undef COPY_REG_MASKED
164 intel_gvt_hypervisor_read_gpa(vgpu
,
165 workload
->ring_context_gpa
+
166 sizeof(*shadow_ring_context
),
167 (void *)shadow_ring_context
+
168 sizeof(*shadow_ring_context
),
169 I915_GTT_PAGE_SIZE
- sizeof(*shadow_ring_context
));
171 sr_oa_regs(workload
, (u32
*)shadow_ring_context
, false);
174 if (IS_RESTORE_INHIBIT(shadow_ring_context
->ctx_ctrl
.val
))
177 gvt_dbg_sched("ring %s workload lrca %x",
178 workload
->engine
->name
,
179 workload
->ctx_desc
.lrca
);
181 context_page_num
= workload
->engine
->context_size
;
182 context_page_num
= context_page_num
>> PAGE_SHIFT
;
184 if (IS_BROADWELL(gvt
->gt
->i915
) && workload
->engine
->id
== RCS0
)
185 context_page_num
= 19;
188 while (i
< context_page_num
) {
189 context_gpa
= intel_vgpu_gma_to_gpa(vgpu
->gtt
.ggtt_mm
,
190 (u32
)((workload
->ctx_desc
.lrca
+ i
) <<
191 I915_GTT_PAGE_SHIFT
));
192 if (context_gpa
== INTEL_GVT_INVALID_ADDR
) {
193 gvt_vgpu_err("Invalid guest context descriptor\n");
197 page
= i915_gem_object_get_page(ctx_obj
, i
);
199 intel_gvt_hypervisor_read_gpa(vgpu
, context_gpa
, dst
,
207 static inline bool is_gvt_request(struct i915_request
*rq
)
209 return intel_context_force_single_submission(rq
->context
);
212 static void save_ring_hw_state(struct intel_vgpu
*vgpu
,
213 const struct intel_engine_cs
*engine
)
215 struct intel_uncore
*uncore
= engine
->uncore
;
218 reg
= RING_INSTDONE(engine
->mmio_base
);
219 vgpu_vreg(vgpu
, i915_mmio_reg_offset(reg
)) =
220 intel_uncore_read(uncore
, reg
);
222 reg
= RING_ACTHD(engine
->mmio_base
);
223 vgpu_vreg(vgpu
, i915_mmio_reg_offset(reg
)) =
224 intel_uncore_read(uncore
, reg
);
226 reg
= RING_ACTHD_UDW(engine
->mmio_base
);
227 vgpu_vreg(vgpu
, i915_mmio_reg_offset(reg
)) =
228 intel_uncore_read(uncore
, reg
);
231 static int shadow_context_status_change(struct notifier_block
*nb
,
232 unsigned long action
, void *data
)
234 struct i915_request
*rq
= data
;
235 struct intel_gvt
*gvt
= container_of(nb
, struct intel_gvt
,
236 shadow_ctx_notifier_block
[rq
->engine
->id
]);
237 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
238 enum intel_engine_id ring_id
= rq
->engine
->id
;
239 struct intel_vgpu_workload
*workload
;
242 if (!is_gvt_request(rq
)) {
243 spin_lock_irqsave(&scheduler
->mmio_context_lock
, flags
);
244 if (action
== INTEL_CONTEXT_SCHEDULE_IN
&&
245 scheduler
->engine_owner
[ring_id
]) {
246 /* Switch ring from vGPU to host. */
247 intel_gvt_switch_mmio(scheduler
->engine_owner
[ring_id
],
249 scheduler
->engine_owner
[ring_id
] = NULL
;
251 spin_unlock_irqrestore(&scheduler
->mmio_context_lock
, flags
);
256 workload
= scheduler
->current_workload
[ring_id
];
257 if (unlikely(!workload
))
261 case INTEL_CONTEXT_SCHEDULE_IN
:
262 spin_lock_irqsave(&scheduler
->mmio_context_lock
, flags
);
263 if (workload
->vgpu
!= scheduler
->engine_owner
[ring_id
]) {
264 /* Switch ring from host to vGPU or vGPU to vGPU. */
265 intel_gvt_switch_mmio(scheduler
->engine_owner
[ring_id
],
266 workload
->vgpu
, rq
->engine
);
267 scheduler
->engine_owner
[ring_id
] = workload
->vgpu
;
269 gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
270 ring_id
, workload
->vgpu
->id
);
271 spin_unlock_irqrestore(&scheduler
->mmio_context_lock
, flags
);
272 atomic_set(&workload
->shadow_ctx_active
, 1);
274 case INTEL_CONTEXT_SCHEDULE_OUT
:
275 save_ring_hw_state(workload
->vgpu
, rq
->engine
);
276 atomic_set(&workload
->shadow_ctx_active
, 0);
278 case INTEL_CONTEXT_SCHEDULE_PREEMPTED
:
279 save_ring_hw_state(workload
->vgpu
, rq
->engine
);
285 wake_up(&workload
->shadow_ctx_status_wq
);
290 shadow_context_descriptor_update(struct intel_context
*ce
,
291 struct intel_vgpu_workload
*workload
)
293 u64 desc
= ce
->lrc
.desc
;
296 * Update bits 0-11 of the context descriptor which includes flags
297 * like GEN8_CTX_* cached in desc_template
299 desc
&= ~(0x3ull
<< GEN8_CTX_ADDRESSING_MODE_SHIFT
);
300 desc
|= (u64
)workload
->ctx_desc
.addressing_mode
<<
301 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
306 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload
*workload
)
308 struct intel_vgpu
*vgpu
= workload
->vgpu
;
309 struct i915_request
*req
= workload
->req
;
310 void *shadow_ring_buffer_va
;
314 if (IS_GEN(req
->i915
, 9) && is_inhibit_context(req
->context
))
315 intel_vgpu_restore_inhibit_context(vgpu
, req
);
318 * To track whether a request has started on HW, we can emit a
319 * breadcrumb at the beginning of the request and check its
320 * timeline's HWSP to see if the breadcrumb has advanced past the
321 * start of this request. Actually, the request must have the
322 * init_breadcrumb if its timeline set has_init_bread_crumb, or the
323 * scheduler might get a wrong state of it during reset. Since the
324 * requests from gvt always set the has_init_breadcrumb flag, here
325 * need to do the emit_init_breadcrumb for all the requests.
327 if (req
->engine
->emit_init_breadcrumb
) {
328 err
= req
->engine
->emit_init_breadcrumb(req
);
330 gvt_vgpu_err("fail to emit init breadcrumb\n");
335 /* allocate shadow ring buffer */
336 cs
= intel_ring_begin(workload
->req
, workload
->rb_len
/ sizeof(u32
));
338 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n",
343 shadow_ring_buffer_va
= workload
->shadow_ring_buffer_va
;
345 /* get shadow ring buffer va */
346 workload
->shadow_ring_buffer_va
= cs
;
348 memcpy(cs
, shadow_ring_buffer_va
,
351 cs
+= workload
->rb_len
/ sizeof(u32
);
352 intel_ring_advance(workload
->req
, cs
);
357 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx
*wa_ctx
)
359 if (!wa_ctx
->indirect_ctx
.obj
)
362 i915_gem_object_unpin_map(wa_ctx
->indirect_ctx
.obj
);
363 i915_gem_object_put(wa_ctx
->indirect_ctx
.obj
);
365 wa_ctx
->indirect_ctx
.obj
= NULL
;
366 wa_ctx
->indirect_ctx
.shadow_va
= NULL
;
369 static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload
*workload
,
370 struct intel_context
*ce
)
372 struct intel_vgpu_mm
*mm
= workload
->shadow_mm
;
373 struct i915_ppgtt
*ppgtt
= i915_vm_to_ppgtt(ce
->vm
);
376 if (mm
->ppgtt_mm
.root_entry_type
== GTT_TYPE_PPGTT_ROOT_L4_ENTRY
) {
377 px_dma(ppgtt
->pd
) = mm
->ppgtt_mm
.shadow_pdps
[0];
379 for (i
= 0; i
< GVT_RING_CTX_NR_PDPS
; i
++) {
380 struct i915_page_directory
* const pd
=
381 i915_pd_entry(ppgtt
->pd
, i
);
382 /* skip now as current i915 ppgtt alloc won't allocate
383 top level pdp for non 4-level table, won't impact
387 px_dma(pd
) = mm
->ppgtt_mm
.shadow_pdps
[i
];
393 intel_gvt_workload_req_alloc(struct intel_vgpu_workload
*workload
)
395 struct intel_vgpu
*vgpu
= workload
->vgpu
;
396 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
397 struct i915_request
*rq
;
402 rq
= i915_request_create(s
->shadow
[workload
->engine
->id
]);
404 gvt_vgpu_err("fail to allocate gem request\n");
408 workload
->req
= i915_request_get(rq
);
413 * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
414 * shadow it as well, include ringbuffer,wa_ctx and ctx.
415 * @workload: an abstract entity for each execlist submission.
417 * This function is called before the workload submitting to i915, to make
418 * sure the content of the workload is valid.
420 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload
*workload
)
422 struct intel_vgpu
*vgpu
= workload
->vgpu
;
423 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
426 lockdep_assert_held(&vgpu
->vgpu_lock
);
428 if (workload
->shadow
)
431 if (!test_and_set_bit(workload
->engine
->id
, s
->shadow_ctx_desc_updated
))
432 shadow_context_descriptor_update(s
->shadow
[workload
->engine
->id
],
435 ret
= intel_gvt_scan_and_shadow_ringbuffer(workload
);
439 if (workload
->engine
->id
== RCS0
&&
440 workload
->wa_ctx
.indirect_ctx
.size
) {
441 ret
= intel_gvt_scan_and_shadow_wa_ctx(&workload
->wa_ctx
);
446 workload
->shadow
= true;
450 release_shadow_wa_ctx(&workload
->wa_ctx
);
454 static void release_shadow_batch_buffer(struct intel_vgpu_workload
*workload
);
456 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload
*workload
)
458 struct intel_gvt
*gvt
= workload
->vgpu
->gvt
;
459 const int gmadr_bytes
= gvt
->device_info
.gmadr_bytes_in_cmd
;
460 struct intel_vgpu_shadow_bb
*bb
;
463 list_for_each_entry(bb
, &workload
->shadow_bb
, list
) {
464 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
465 * is only updated into ring_scan_buffer, not real ring address
466 * allocated in later copy_workload_to_ring_buffer. pls be noted
467 * shadow_ring_buffer_va is now pointed to real ring buffer va
468 * in copy_workload_to_ring_buffer.
472 bb
->bb_start_cmd_va
= workload
->shadow_ring_buffer_va
476 /* for non-priv bb, scan&shadow is only for
477 * debugging purpose, so the content of shadow bb
478 * is the same as original bb. Therefore,
479 * here, rather than switch to shadow bb's gma
480 * address, we directly use original batch buffer's
481 * gma address, and send original bb to hardware
484 if (bb
->clflush
& CLFLUSH_AFTER
) {
485 drm_clflush_virt_range(bb
->va
,
487 bb
->clflush
&= ~CLFLUSH_AFTER
;
489 i915_gem_object_finish_access(bb
->obj
);
490 bb
->accessing
= false;
493 bb
->vma
= i915_gem_object_ggtt_pin(bb
->obj
,
495 if (IS_ERR(bb
->vma
)) {
496 ret
= PTR_ERR(bb
->vma
);
500 /* relocate shadow batch buffer */
501 bb
->bb_start_cmd_va
[1] = i915_ggtt_offset(bb
->vma
);
502 if (gmadr_bytes
== 8)
503 bb
->bb_start_cmd_va
[2] = 0;
505 /* No one is going to touch shadow bb from now on. */
506 if (bb
->clflush
& CLFLUSH_AFTER
) {
507 drm_clflush_virt_range(bb
->va
,
509 bb
->clflush
&= ~CLFLUSH_AFTER
;
512 ret
= i915_gem_object_set_to_gtt_domain(bb
->obj
,
517 ret
= i915_vma_move_to_active(bb
->vma
,
523 i915_gem_object_finish_access(bb
->obj
);
524 bb
->accessing
= false;
529 release_shadow_batch_buffer(workload
);
533 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx
*wa_ctx
)
535 struct intel_vgpu_workload
*workload
=
536 container_of(wa_ctx
, struct intel_vgpu_workload
, wa_ctx
);
537 struct i915_request
*rq
= workload
->req
;
538 struct execlist_ring_context
*shadow_ring_context
=
539 (struct execlist_ring_context
*)rq
->context
->lrc_reg_state
;
541 shadow_ring_context
->bb_per_ctx_ptr
.val
=
542 (shadow_ring_context
->bb_per_ctx_ptr
.val
&
543 (~PER_CTX_ADDR_MASK
)) | wa_ctx
->per_ctx
.shadow_gma
;
544 shadow_ring_context
->rcs_indirect_ctx
.val
=
545 (shadow_ring_context
->rcs_indirect_ctx
.val
&
546 (~INDIRECT_CTX_ADDR_MASK
)) | wa_ctx
->indirect_ctx
.shadow_gma
;
549 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx
*wa_ctx
)
551 struct i915_vma
*vma
;
552 unsigned char *per_ctx_va
=
553 (unsigned char *)wa_ctx
->indirect_ctx
.shadow_va
+
554 wa_ctx
->indirect_ctx
.size
;
556 if (wa_ctx
->indirect_ctx
.size
== 0)
559 vma
= i915_gem_object_ggtt_pin(wa_ctx
->indirect_ctx
.obj
, NULL
,
560 0, CACHELINE_BYTES
, 0);
564 /* FIXME: we are not tracking our pinned VMA leaving it
565 * up to the core to fix up the stray pin_count upon
569 wa_ctx
->indirect_ctx
.shadow_gma
= i915_ggtt_offset(vma
);
571 wa_ctx
->per_ctx
.shadow_gma
= *((unsigned int *)per_ctx_va
+ 1);
572 memset(per_ctx_va
, 0, CACHELINE_BYTES
);
574 update_wa_ctx_2_shadow_ctx(wa_ctx
);
578 static void update_vreg_in_ctx(struct intel_vgpu_workload
*workload
)
580 vgpu_vreg_t(workload
->vgpu
, RING_START(workload
->engine
->mmio_base
)) =
584 static void release_shadow_batch_buffer(struct intel_vgpu_workload
*workload
)
586 struct intel_vgpu_shadow_bb
*bb
, *pos
;
588 if (list_empty(&workload
->shadow_bb
))
591 bb
= list_first_entry(&workload
->shadow_bb
,
592 struct intel_vgpu_shadow_bb
, list
);
594 list_for_each_entry_safe(bb
, pos
, &workload
->shadow_bb
, list
) {
597 i915_gem_object_finish_access(bb
->obj
);
599 if (bb
->va
&& !IS_ERR(bb
->va
))
600 i915_gem_object_unpin_map(bb
->obj
);
602 if (bb
->vma
&& !IS_ERR(bb
->vma
)) {
603 i915_vma_unpin(bb
->vma
);
604 i915_vma_close(bb
->vma
);
606 i915_gem_object_put(bb
->obj
);
613 static int prepare_workload(struct intel_vgpu_workload
*workload
)
615 struct intel_vgpu
*vgpu
= workload
->vgpu
;
616 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
619 ret
= intel_vgpu_pin_mm(workload
->shadow_mm
);
621 gvt_vgpu_err("fail to vgpu pin mm\n");
625 if (workload
->shadow_mm
->type
!= INTEL_GVT_MM_PPGTT
||
626 !workload
->shadow_mm
->ppgtt_mm
.shadowed
) {
627 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
631 update_shadow_pdps(workload
);
633 set_context_ppgtt_from_shadow(workload
, s
->shadow
[workload
->engine
->id
]);
635 ret
= intel_vgpu_sync_oos_pages(workload
->vgpu
);
637 gvt_vgpu_err("fail to vgpu sync oos pages\n");
641 ret
= intel_vgpu_flush_post_shadow(workload
->vgpu
);
643 gvt_vgpu_err("fail to flush post shadow\n");
647 ret
= copy_workload_to_ring_buffer(workload
);
649 gvt_vgpu_err("fail to generate request\n");
653 ret
= prepare_shadow_batch_buffer(workload
);
655 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
659 ret
= prepare_shadow_wa_ctx(&workload
->wa_ctx
);
661 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
662 goto err_shadow_batch
;
665 if (workload
->prepare
) {
666 ret
= workload
->prepare(workload
);
668 goto err_shadow_wa_ctx
;
673 release_shadow_wa_ctx(&workload
->wa_ctx
);
675 release_shadow_batch_buffer(workload
);
677 intel_vgpu_unpin_mm(workload
->shadow_mm
);
681 static int dispatch_workload(struct intel_vgpu_workload
*workload
)
683 struct intel_vgpu
*vgpu
= workload
->vgpu
;
684 struct i915_request
*rq
;
687 gvt_dbg_sched("ring id %s prepare to dispatch workload %p\n",
688 workload
->engine
->name
, workload
);
690 mutex_lock(&vgpu
->vgpu_lock
);
692 ret
= intel_gvt_workload_req_alloc(workload
);
696 ret
= intel_gvt_scan_and_shadow_workload(workload
);
700 ret
= populate_shadow_context(workload
);
702 release_shadow_wa_ctx(&workload
->wa_ctx
);
706 ret
= prepare_workload(workload
);
709 /* We might still need to add request with
710 * clean ctx to retire it properly..
712 rq
= fetch_and_zero(&workload
->req
);
713 i915_request_put(rq
);
716 if (!IS_ERR_OR_NULL(workload
->req
)) {
717 gvt_dbg_sched("ring id %s submit workload to i915 %p\n",
718 workload
->engine
->name
, workload
->req
);
719 i915_request_add(workload
->req
);
720 workload
->dispatched
= true;
724 workload
->status
= ret
;
725 mutex_unlock(&vgpu
->vgpu_lock
);
729 static struct intel_vgpu_workload
*
730 pick_next_workload(struct intel_gvt
*gvt
, struct intel_engine_cs
*engine
)
732 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
733 struct intel_vgpu_workload
*workload
= NULL
;
735 mutex_lock(&gvt
->sched_lock
);
738 * no current vgpu / will be scheduled out / no workload
741 if (!scheduler
->current_vgpu
) {
742 gvt_dbg_sched("ring %s stop - no current vgpu\n", engine
->name
);
746 if (scheduler
->need_reschedule
) {
747 gvt_dbg_sched("ring %s stop - will reschedule\n", engine
->name
);
751 if (!scheduler
->current_vgpu
->active
||
752 list_empty(workload_q_head(scheduler
->current_vgpu
, engine
)))
756 * still have current workload, maybe the workload disptacher
757 * fail to submit it for some reason, resubmit it.
759 if (scheduler
->current_workload
[engine
->id
]) {
760 workload
= scheduler
->current_workload
[engine
->id
];
761 gvt_dbg_sched("ring %s still have current workload %p\n",
762 engine
->name
, workload
);
767 * pick a workload as current workload
768 * once current workload is set, schedule policy routines
769 * will wait the current workload is finished when trying to
770 * schedule out a vgpu.
772 scheduler
->current_workload
[engine
->id
] =
773 list_first_entry(workload_q_head(scheduler
->current_vgpu
,
775 struct intel_vgpu_workload
, list
);
777 workload
= scheduler
->current_workload
[engine
->id
];
779 gvt_dbg_sched("ring %s pick new workload %p\n", engine
->name
, workload
);
781 atomic_inc(&workload
->vgpu
->submission
.running_workload_num
);
783 mutex_unlock(&gvt
->sched_lock
);
787 static void update_guest_context(struct intel_vgpu_workload
*workload
)
789 struct i915_request
*rq
= workload
->req
;
790 struct intel_vgpu
*vgpu
= workload
->vgpu
;
791 struct drm_i915_gem_object
*ctx_obj
= rq
->context
->state
->obj
;
792 struct execlist_ring_context
*shadow_ring_context
;
795 unsigned long context_gpa
, context_page_num
;
801 gvt_dbg_sched("ring id %d workload lrca %x\n", rq
->engine
->id
,
802 workload
->ctx_desc
.lrca
);
804 head
= workload
->rb_head
;
805 tail
= workload
->rb_tail
;
806 wrap_count
= workload
->guest_rb_head
>> RB_HEAD_WRAP_CNT_OFF
;
809 if (wrap_count
== RB_HEAD_WRAP_CNT_MAX
)
815 head
= (wrap_count
<< RB_HEAD_WRAP_CNT_OFF
) | tail
;
817 ring_base
= rq
->engine
->mmio_base
;
818 vgpu_vreg_t(vgpu
, RING_TAIL(ring_base
)) = tail
;
819 vgpu_vreg_t(vgpu
, RING_HEAD(ring_base
)) = head
;
821 context_page_num
= rq
->engine
->context_size
;
822 context_page_num
= context_page_num
>> PAGE_SHIFT
;
824 if (IS_BROADWELL(rq
->i915
) && rq
->engine
->id
== RCS0
)
825 context_page_num
= 19;
829 while (i
< context_page_num
) {
830 context_gpa
= intel_vgpu_gma_to_gpa(vgpu
->gtt
.ggtt_mm
,
831 (u32
)((workload
->ctx_desc
.lrca
+ i
) <<
832 I915_GTT_PAGE_SHIFT
));
833 if (context_gpa
== INTEL_GVT_INVALID_ADDR
) {
834 gvt_vgpu_err("invalid guest context descriptor\n");
838 page
= i915_gem_object_get_page(ctx_obj
, i
);
840 intel_gvt_hypervisor_write_gpa(vgpu
, context_gpa
, src
,
846 intel_gvt_hypervisor_write_gpa(vgpu
, workload
->ring_context_gpa
+
847 RING_CTX_OFF(ring_header
.val
), &workload
->rb_tail
, 4);
849 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
850 shadow_ring_context
= kmap(page
);
852 #define COPY_REG(name) \
853 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
854 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
857 COPY_REG(ctx_timestamp
);
861 intel_gvt_hypervisor_write_gpa(vgpu
,
862 workload
->ring_context_gpa
+
863 sizeof(*shadow_ring_context
),
864 (void *)shadow_ring_context
+
865 sizeof(*shadow_ring_context
),
866 I915_GTT_PAGE_SIZE
- sizeof(*shadow_ring_context
));
871 void intel_vgpu_clean_workloads(struct intel_vgpu
*vgpu
,
872 intel_engine_mask_t engine_mask
)
874 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
875 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->gt
->i915
;
876 struct intel_engine_cs
*engine
;
877 struct intel_vgpu_workload
*pos
, *n
;
878 intel_engine_mask_t tmp
;
880 /* free the unsubmited workloads in the queues. */
881 for_each_engine_masked(engine
, &dev_priv
->gt
, engine_mask
, tmp
) {
882 list_for_each_entry_safe(pos
, n
,
883 &s
->workload_q_head
[engine
->id
], list
) {
884 list_del_init(&pos
->list
);
885 intel_vgpu_destroy_workload(pos
);
887 clear_bit(engine
->id
, s
->shadow_ctx_desc_updated
);
891 static void complete_current_workload(struct intel_gvt
*gvt
, int ring_id
)
893 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
894 struct intel_vgpu_workload
*workload
=
895 scheduler
->current_workload
[ring_id
];
896 struct intel_vgpu
*vgpu
= workload
->vgpu
;
897 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
898 struct i915_request
*rq
= workload
->req
;
901 mutex_lock(&vgpu
->vgpu_lock
);
902 mutex_lock(&gvt
->sched_lock
);
904 /* For the workload w/ request, needs to wait for the context
905 * switch to make sure request is completed.
906 * For the workload w/o request, directly complete the workload.
909 wait_event(workload
->shadow_ctx_status_wq
,
910 !atomic_read(&workload
->shadow_ctx_active
));
912 /* If this request caused GPU hang, req->fence.error will
913 * be set to -EIO. Use -EIO to set workload status so
914 * that when this request caused GPU hang, didn't trigger
915 * context switch interrupt to guest.
917 if (likely(workload
->status
== -EINPROGRESS
)) {
918 if (workload
->req
->fence
.error
== -EIO
)
919 workload
->status
= -EIO
;
921 workload
->status
= 0;
924 if (!workload
->status
&&
925 !(vgpu
->resetting_eng
& BIT(ring_id
))) {
926 update_guest_context(workload
);
928 for_each_set_bit(event
, workload
->pending_events
,
930 intel_vgpu_trigger_virtual_event(vgpu
, event
);
933 i915_request_put(fetch_and_zero(&workload
->req
));
936 gvt_dbg_sched("ring id %d complete workload %p status %d\n",
937 ring_id
, workload
, workload
->status
);
939 scheduler
->current_workload
[ring_id
] = NULL
;
941 list_del_init(&workload
->list
);
943 if (workload
->status
|| vgpu
->resetting_eng
& BIT(ring_id
)) {
944 /* if workload->status is not successful means HW GPU
945 * has occurred GPU hang or something wrong with i915/GVT,
946 * and GVT won't inject context switch interrupt to guest.
947 * So this error is a vGPU hang actually to the guest.
948 * According to this we should emunlate a vGPU hang. If
949 * there are pending workloads which are already submitted
950 * from guest, we should clean them up like HW GPU does.
952 * if it is in middle of engine resetting, the pending
953 * workloads won't be submitted to HW GPU and will be
954 * cleaned up during the resetting process later, so doing
955 * the workload clean up here doesn't have any impact.
957 intel_vgpu_clean_workloads(vgpu
, BIT(ring_id
));
960 workload
->complete(workload
);
962 atomic_dec(&s
->running_workload_num
);
963 wake_up(&scheduler
->workload_complete_wq
);
965 if (gvt
->scheduler
.need_reschedule
)
966 intel_gvt_request_service(gvt
, INTEL_GVT_REQUEST_EVENT_SCHED
);
968 mutex_unlock(&gvt
->sched_lock
);
969 mutex_unlock(&vgpu
->vgpu_lock
);
972 static int workload_thread(void *arg
)
974 struct intel_engine_cs
*engine
= arg
;
975 const bool need_force_wake
= INTEL_GEN(engine
->i915
) >= 9;
976 struct intel_gvt
*gvt
= engine
->i915
->gvt
;
977 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
978 struct intel_vgpu_workload
*workload
= NULL
;
979 struct intel_vgpu
*vgpu
= NULL
;
981 DEFINE_WAIT_FUNC(wait
, woken_wake_function
);
983 gvt_dbg_core("workload thread for ring %s started\n", engine
->name
);
985 while (!kthread_should_stop()) {
986 intel_wakeref_t wakeref
;
988 add_wait_queue(&scheduler
->waitq
[engine
->id
], &wait
);
990 workload
= pick_next_workload(gvt
, engine
);
993 wait_woken(&wait
, TASK_INTERRUPTIBLE
,
994 MAX_SCHEDULE_TIMEOUT
);
995 } while (!kthread_should_stop());
996 remove_wait_queue(&scheduler
->waitq
[engine
->id
], &wait
);
1001 gvt_dbg_sched("ring %s next workload %p vgpu %d\n",
1002 engine
->name
, workload
,
1003 workload
->vgpu
->id
);
1005 wakeref
= intel_runtime_pm_get(engine
->uncore
->rpm
);
1007 gvt_dbg_sched("ring %s will dispatch workload %p\n",
1008 engine
->name
, workload
);
1010 if (need_force_wake
)
1011 intel_uncore_forcewake_get(engine
->uncore
,
1014 * Update the vReg of the vGPU which submitted this
1015 * workload. The vGPU may use these registers for checking
1016 * the context state. The value comes from GPU commands
1019 update_vreg_in_ctx(workload
);
1021 ret
= dispatch_workload(workload
);
1024 vgpu
= workload
->vgpu
;
1025 gvt_vgpu_err("fail to dispatch workload, skip\n");
1029 gvt_dbg_sched("ring %s wait workload %p\n",
1030 engine
->name
, workload
);
1031 i915_request_wait(workload
->req
, 0, MAX_SCHEDULE_TIMEOUT
);
1034 gvt_dbg_sched("will complete workload %p, status: %d\n",
1035 workload
, workload
->status
);
1037 complete_current_workload(gvt
, engine
->id
);
1039 if (need_force_wake
)
1040 intel_uncore_forcewake_put(engine
->uncore
,
1043 intel_runtime_pm_put(engine
->uncore
->rpm
, wakeref
);
1044 if (ret
&& (vgpu_is_vm_unhealthy(ret
)))
1045 enter_failsafe_mode(vgpu
, GVT_FAILSAFE_GUEST_ERR
);
1050 void intel_gvt_wait_vgpu_idle(struct intel_vgpu
*vgpu
)
1052 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
1053 struct intel_gvt
*gvt
= vgpu
->gvt
;
1054 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
1056 if (atomic_read(&s
->running_workload_num
)) {
1057 gvt_dbg_sched("wait vgpu idle\n");
1059 wait_event(scheduler
->workload_complete_wq
,
1060 !atomic_read(&s
->running_workload_num
));
1064 void intel_gvt_clean_workload_scheduler(struct intel_gvt
*gvt
)
1066 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
1067 struct intel_engine_cs
*engine
;
1068 enum intel_engine_id i
;
1070 gvt_dbg_core("clean workload scheduler\n");
1072 for_each_engine(engine
, gvt
->gt
, i
) {
1073 atomic_notifier_chain_unregister(
1074 &engine
->context_status_notifier
,
1075 &gvt
->shadow_ctx_notifier_block
[i
]);
1076 kthread_stop(scheduler
->thread
[i
]);
1080 int intel_gvt_init_workload_scheduler(struct intel_gvt
*gvt
)
1082 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
1083 struct intel_engine_cs
*engine
;
1084 enum intel_engine_id i
;
1087 gvt_dbg_core("init workload scheduler\n");
1089 init_waitqueue_head(&scheduler
->workload_complete_wq
);
1091 for_each_engine(engine
, gvt
->gt
, i
) {
1092 init_waitqueue_head(&scheduler
->waitq
[i
]);
1094 scheduler
->thread
[i
] = kthread_run(workload_thread
, engine
,
1095 "gvt:%s", engine
->name
);
1096 if (IS_ERR(scheduler
->thread
[i
])) {
1097 gvt_err("fail to create workload thread\n");
1098 ret
= PTR_ERR(scheduler
->thread
[i
]);
1102 gvt
->shadow_ctx_notifier_block
[i
].notifier_call
=
1103 shadow_context_status_change
;
1104 atomic_notifier_chain_register(&engine
->context_status_notifier
,
1105 &gvt
->shadow_ctx_notifier_block
[i
]);
1111 intel_gvt_clean_workload_scheduler(gvt
);
1116 i915_context_ppgtt_root_restore(struct intel_vgpu_submission
*s
,
1117 struct i915_ppgtt
*ppgtt
)
1121 if (i915_vm_is_4lvl(&ppgtt
->vm
)) {
1122 px_dma(ppgtt
->pd
) = s
->i915_context_pml4
;
1124 for (i
= 0; i
< GEN8_3LVL_PDPES
; i
++) {
1125 struct i915_page_directory
* const pd
=
1126 i915_pd_entry(ppgtt
->pd
, i
);
1128 px_dma(pd
) = s
->i915_context_pdps
[i
];
1134 * intel_vgpu_clean_submission - free submission-related resource for vGPU
1137 * This function is called when a vGPU is being destroyed.
1140 void intel_vgpu_clean_submission(struct intel_vgpu
*vgpu
)
1142 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
1143 struct intel_engine_cs
*engine
;
1144 enum intel_engine_id id
;
1146 intel_vgpu_select_submission_ops(vgpu
, ALL_ENGINES
, 0);
1148 i915_context_ppgtt_root_restore(s
, i915_vm_to_ppgtt(s
->shadow
[0]->vm
));
1149 for_each_engine(engine
, vgpu
->gvt
->gt
, id
)
1150 intel_context_unpin(s
->shadow
[id
]);
1152 kmem_cache_destroy(s
->workloads
);
1157 * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1159 * @engine_mask: engines expected to be reset
1161 * This function is called when a vGPU is being destroyed.
1164 void intel_vgpu_reset_submission(struct intel_vgpu
*vgpu
,
1165 intel_engine_mask_t engine_mask
)
1167 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
1172 intel_vgpu_clean_workloads(vgpu
, engine_mask
);
1173 s
->ops
->reset(vgpu
, engine_mask
);
1177 i915_context_ppgtt_root_save(struct intel_vgpu_submission
*s
,
1178 struct i915_ppgtt
*ppgtt
)
1182 if (i915_vm_is_4lvl(&ppgtt
->vm
)) {
1183 s
->i915_context_pml4
= px_dma(ppgtt
->pd
);
1185 for (i
= 0; i
< GEN8_3LVL_PDPES
; i
++) {
1186 struct i915_page_directory
* const pd
=
1187 i915_pd_entry(ppgtt
->pd
, i
);
1189 s
->i915_context_pdps
[i
] = px_dma(pd
);
1195 * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1198 * This function is called when a vGPU is being created.
1201 * Zero on success, negative error code if failed.
1204 int intel_vgpu_setup_submission(struct intel_vgpu
*vgpu
)
1206 struct drm_i915_private
*i915
= vgpu
->gvt
->gt
->i915
;
1207 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
1208 struct intel_engine_cs
*engine
;
1209 struct i915_ppgtt
*ppgtt
;
1210 enum intel_engine_id i
;
1213 ppgtt
= i915_ppgtt_create(&i915
->gt
);
1215 return PTR_ERR(ppgtt
);
1217 i915_context_ppgtt_root_save(s
, ppgtt
);
1219 for_each_engine(engine
, vgpu
->gvt
->gt
, i
) {
1220 struct intel_context
*ce
;
1222 INIT_LIST_HEAD(&s
->workload_q_head
[i
]);
1223 s
->shadow
[i
] = ERR_PTR(-EINVAL
);
1225 ce
= intel_context_create(engine
);
1228 goto out_shadow_ctx
;
1231 i915_vm_put(ce
->vm
);
1232 ce
->vm
= i915_vm_get(&ppgtt
->vm
);
1233 intel_context_set_single_submission(ce
);
1235 /* Max ring buffer size */
1236 if (!intel_uc_wants_guc_submission(&engine
->gt
->uc
)) {
1237 const unsigned int ring_size
= 512 * SZ_4K
;
1239 ce
->ring
= __intel_context_ring_size(ring_size
);
1242 ret
= intel_context_pin(ce
);
1243 intel_context_put(ce
);
1245 goto out_shadow_ctx
;
1250 bitmap_zero(s
->shadow_ctx_desc_updated
, I915_NUM_ENGINES
);
1252 s
->workloads
= kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1253 sizeof(struct intel_vgpu_workload
), 0,
1255 offsetof(struct intel_vgpu_workload
, rb_tail
),
1256 sizeof_field(struct intel_vgpu_workload
, rb_tail
),
1259 if (!s
->workloads
) {
1261 goto out_shadow_ctx
;
1264 atomic_set(&s
->running_workload_num
, 0);
1265 bitmap_zero(s
->tlb_handle_pending
, I915_NUM_ENGINES
);
1267 i915_vm_put(&ppgtt
->vm
);
1271 i915_context_ppgtt_root_restore(s
, ppgtt
);
1272 for_each_engine(engine
, vgpu
->gvt
->gt
, i
) {
1273 if (IS_ERR(s
->shadow
[i
]))
1276 intel_context_unpin(s
->shadow
[i
]);
1277 intel_context_put(s
->shadow
[i
]);
1279 i915_vm_put(&ppgtt
->vm
);
1284 * intel_vgpu_select_submission_ops - select virtual submission interface
1286 * @engine_mask: either ALL_ENGINES or target engine mask
1287 * @interface: expected vGPU virtual submission interface
1289 * This function is called when guest configures submission interface.
1292 * Zero on success, negative error code if failed.
1295 int intel_vgpu_select_submission_ops(struct intel_vgpu
*vgpu
,
1296 intel_engine_mask_t engine_mask
,
1297 unsigned int interface
)
1299 struct drm_i915_private
*i915
= vgpu
->gvt
->gt
->i915
;
1300 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
1301 const struct intel_vgpu_submission_ops
*ops
[] = {
1302 [INTEL_VGPU_EXECLIST_SUBMISSION
] =
1303 &intel_vgpu_execlist_submission_ops
,
1307 if (drm_WARN_ON(&i915
->drm
, interface
>= ARRAY_SIZE(ops
)))
1310 if (drm_WARN_ON(&i915
->drm
,
1311 interface
== 0 && engine_mask
!= ALL_ENGINES
))
1315 s
->ops
->clean(vgpu
, engine_mask
);
1317 if (interface
== 0) {
1319 s
->virtual_submission_interface
= 0;
1321 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu
->id
);
1325 ret
= ops
[interface
]->init(vgpu
, engine_mask
);
1329 s
->ops
= ops
[interface
];
1330 s
->virtual_submission_interface
= interface
;
1333 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1334 vgpu
->id
, s
->ops
->name
);
1340 * intel_vgpu_destroy_workload - destroy a vGPU workload
1341 * @workload: workload to destroy
1343 * This function is called when destroy a vGPU workload.
1346 void intel_vgpu_destroy_workload(struct intel_vgpu_workload
*workload
)
1348 struct intel_vgpu_submission
*s
= &workload
->vgpu
->submission
;
1350 release_shadow_batch_buffer(workload
);
1351 release_shadow_wa_ctx(&workload
->wa_ctx
);
1353 if (workload
->shadow_mm
)
1354 intel_vgpu_mm_put(workload
->shadow_mm
);
1356 kmem_cache_free(s
->workloads
, workload
);
1359 static struct intel_vgpu_workload
*
1360 alloc_workload(struct intel_vgpu
*vgpu
)
1362 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
1363 struct intel_vgpu_workload
*workload
;
1365 workload
= kmem_cache_zalloc(s
->workloads
, GFP_KERNEL
);
1367 return ERR_PTR(-ENOMEM
);
1369 INIT_LIST_HEAD(&workload
->list
);
1370 INIT_LIST_HEAD(&workload
->shadow_bb
);
1372 init_waitqueue_head(&workload
->shadow_ctx_status_wq
);
1373 atomic_set(&workload
->shadow_ctx_active
, 0);
1375 workload
->status
= -EINPROGRESS
;
1376 workload
->vgpu
= vgpu
;
1381 #define RING_CTX_OFF(x) \
1382 offsetof(struct execlist_ring_context, x)
1384 static void read_guest_pdps(struct intel_vgpu
*vgpu
,
1385 u64 ring_context_gpa
, u32 pdp
[8])
1390 gpa
= ring_context_gpa
+ RING_CTX_OFF(pdps
[0].val
);
1392 for (i
= 0; i
< 8; i
++)
1393 intel_gvt_hypervisor_read_gpa(vgpu
,
1394 gpa
+ i
* 8, &pdp
[7 - i
], 4);
1397 static int prepare_mm(struct intel_vgpu_workload
*workload
)
1399 struct execlist_ctx_descriptor_format
*desc
= &workload
->ctx_desc
;
1400 struct intel_vgpu_mm
*mm
;
1401 struct intel_vgpu
*vgpu
= workload
->vgpu
;
1402 enum intel_gvt_gtt_type root_entry_type
;
1403 u64 pdps
[GVT_RING_CTX_NR_PDPS
];
1405 switch (desc
->addressing_mode
) {
1406 case 1: /* legacy 32-bit */
1407 root_entry_type
= GTT_TYPE_PPGTT_ROOT_L3_ENTRY
;
1409 case 3: /* legacy 64-bit */
1410 root_entry_type
= GTT_TYPE_PPGTT_ROOT_L4_ENTRY
;
1413 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1417 read_guest_pdps(workload
->vgpu
, workload
->ring_context_gpa
, (void *)pdps
);
1419 mm
= intel_vgpu_get_ppgtt_mm(workload
->vgpu
, root_entry_type
, pdps
);
1423 workload
->shadow_mm
= mm
;
1427 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1428 ((a)->lrca == (b)->lrca))
1431 * intel_vgpu_create_workload - create a vGPU workload
1433 * @engine: the engine
1434 * @desc: a guest context descriptor
1436 * This function is called when creating a vGPU workload.
1439 * struct intel_vgpu_workload * on success, negative error code in
1440 * pointer if failed.
1443 struct intel_vgpu_workload
*
1444 intel_vgpu_create_workload(struct intel_vgpu
*vgpu
,
1445 const struct intel_engine_cs
*engine
,
1446 struct execlist_ctx_descriptor_format
*desc
)
1448 struct intel_vgpu_submission
*s
= &vgpu
->submission
;
1449 struct list_head
*q
= workload_q_head(vgpu
, engine
);
1450 struct intel_vgpu_workload
*last_workload
= NULL
;
1451 struct intel_vgpu_workload
*workload
= NULL
;
1452 u64 ring_context_gpa
;
1453 u32 head
, tail
, start
, ctl
, ctx_ctl
, per_ctx
, indirect_ctx
;
1457 ring_context_gpa
= intel_vgpu_gma_to_gpa(vgpu
->gtt
.ggtt_mm
,
1458 (u32
)((desc
->lrca
+ 1) << I915_GTT_PAGE_SHIFT
));
1459 if (ring_context_gpa
== INTEL_GVT_INVALID_ADDR
) {
1460 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc
->lrca
);
1461 return ERR_PTR(-EINVAL
);
1464 intel_gvt_hypervisor_read_gpa(vgpu
, ring_context_gpa
+
1465 RING_CTX_OFF(ring_header
.val
), &head
, 4);
1467 intel_gvt_hypervisor_read_gpa(vgpu
, ring_context_gpa
+
1468 RING_CTX_OFF(ring_tail
.val
), &tail
, 4);
1472 head
&= RB_HEAD_OFF_MASK
;
1473 tail
&= RB_TAIL_OFF_MASK
;
1475 list_for_each_entry_reverse(last_workload
, q
, list
) {
1477 if (same_context(&last_workload
->ctx_desc
, desc
)) {
1478 gvt_dbg_el("ring %s cur workload == last\n",
1480 gvt_dbg_el("ctx head %x real head %lx\n", head
,
1481 last_workload
->rb_tail
);
1483 * cannot use guest context head pointer here,
1484 * as it might not be updated at this time
1486 head
= last_workload
->rb_tail
;
1491 gvt_dbg_el("ring %s begin a new workload\n", engine
->name
);
1493 /* record some ring buffer register values for scan and shadow */
1494 intel_gvt_hypervisor_read_gpa(vgpu
, ring_context_gpa
+
1495 RING_CTX_OFF(rb_start
.val
), &start
, 4);
1496 intel_gvt_hypervisor_read_gpa(vgpu
, ring_context_gpa
+
1497 RING_CTX_OFF(rb_ctrl
.val
), &ctl
, 4);
1498 intel_gvt_hypervisor_read_gpa(vgpu
, ring_context_gpa
+
1499 RING_CTX_OFF(ctx_ctrl
.val
), &ctx_ctl
, 4);
1501 if (!intel_gvt_ggtt_validate_range(vgpu
, start
,
1502 _RING_CTL_BUF_SIZE(ctl
))) {
1503 gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start
);
1504 return ERR_PTR(-EINVAL
);
1507 workload
= alloc_workload(vgpu
);
1508 if (IS_ERR(workload
))
1511 workload
->engine
= engine
;
1512 workload
->ctx_desc
= *desc
;
1513 workload
->ring_context_gpa
= ring_context_gpa
;
1514 workload
->rb_head
= head
;
1515 workload
->guest_rb_head
= guest_head
;
1516 workload
->rb_tail
= tail
;
1517 workload
->rb_start
= start
;
1518 workload
->rb_ctl
= ctl
;
1520 if (engine
->id
== RCS0
) {
1521 intel_gvt_hypervisor_read_gpa(vgpu
, ring_context_gpa
+
1522 RING_CTX_OFF(bb_per_ctx_ptr
.val
), &per_ctx
, 4);
1523 intel_gvt_hypervisor_read_gpa(vgpu
, ring_context_gpa
+
1524 RING_CTX_OFF(rcs_indirect_ctx
.val
), &indirect_ctx
, 4);
1526 workload
->wa_ctx
.indirect_ctx
.guest_gma
=
1527 indirect_ctx
& INDIRECT_CTX_ADDR_MASK
;
1528 workload
->wa_ctx
.indirect_ctx
.size
=
1529 (indirect_ctx
& INDIRECT_CTX_SIZE_MASK
) *
1532 if (workload
->wa_ctx
.indirect_ctx
.size
!= 0) {
1533 if (!intel_gvt_ggtt_validate_range(vgpu
,
1534 workload
->wa_ctx
.indirect_ctx
.guest_gma
,
1535 workload
->wa_ctx
.indirect_ctx
.size
)) {
1536 gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
1537 workload
->wa_ctx
.indirect_ctx
.guest_gma
);
1538 kmem_cache_free(s
->workloads
, workload
);
1539 return ERR_PTR(-EINVAL
);
1543 workload
->wa_ctx
.per_ctx
.guest_gma
=
1544 per_ctx
& PER_CTX_ADDR_MASK
;
1545 workload
->wa_ctx
.per_ctx
.valid
= per_ctx
& 1;
1546 if (workload
->wa_ctx
.per_ctx
.valid
) {
1547 if (!intel_gvt_ggtt_validate_range(vgpu
,
1548 workload
->wa_ctx
.per_ctx
.guest_gma
,
1550 gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
1551 workload
->wa_ctx
.per_ctx
.guest_gma
);
1552 kmem_cache_free(s
->workloads
, workload
);
1553 return ERR_PTR(-EINVAL
);
1558 gvt_dbg_el("workload %p ring %s head %x tail %x start %x ctl %x\n",
1559 workload
, engine
->name
, head
, tail
, start
, ctl
);
1561 ret
= prepare_mm(workload
);
1563 kmem_cache_free(s
->workloads
, workload
);
1564 return ERR_PTR(ret
);
1567 /* Only scan and shadow the first workload in the queue
1568 * as there is only one pre-allocated buf-obj for shadow.
1570 if (list_empty(q
)) {
1571 intel_wakeref_t wakeref
;
1573 with_intel_runtime_pm(engine
->gt
->uncore
->rpm
, wakeref
)
1574 ret
= intel_gvt_scan_and_shadow_workload(workload
);
1578 if (vgpu_is_vm_unhealthy(ret
))
1579 enter_failsafe_mode(vgpu
, GVT_FAILSAFE_GUEST_ERR
);
1580 intel_vgpu_destroy_workload(workload
);
1581 return ERR_PTR(ret
);
1588 * intel_vgpu_queue_workload - Qeue a vGPU workload
1589 * @workload: the workload to queue in
1591 void intel_vgpu_queue_workload(struct intel_vgpu_workload
*workload
)
1593 list_add_tail(&workload
->list
,
1594 workload_q_head(workload
->vgpu
, workload
->engine
));
1595 intel_gvt_kick_schedule(workload
->vgpu
->gvt
);
1596 wake_up(&workload
->vgpu
->gvt
->scheduler
.waitq
[workload
->engine
->id
]);