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Merge branch 'linux-4.20' of git://github.com/skeggsb/linux into drm-fixes
[thirdparty/linux.git] / drivers / gpu / drm / nouveau / dispnv50 / disp.c
1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "disp.h"
25 #include "atom.h"
26 #include "core.h"
27 #include "head.h"
28 #include "wndw.h"
29
30 #include <linux/dma-mapping.h>
31 #include <linux/hdmi.h>
32
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_plane_helper.h>
39 #include <drm/drm_scdc_helper.h>
40 #include <drm/drm_edid.h>
41
42 #include <nvif/class.h>
43 #include <nvif/cl0002.h>
44 #include <nvif/cl5070.h>
45 #include <nvif/cl507d.h>
46 #include <nvif/event.h>
47
48 #include "nouveau_drv.h"
49 #include "nouveau_dma.h"
50 #include "nouveau_gem.h"
51 #include "nouveau_connector.h"
52 #include "nouveau_encoder.h"
53 #include "nouveau_fence.h"
54 #include "nouveau_fbcon.h"
55
56 #include <subdev/bios/dp.h>
57
58 /******************************************************************************
59 * Atomic state
60 *****************************************************************************/
61
62 struct nv50_outp_atom {
63 struct list_head head;
64
65 struct drm_encoder *encoder;
66 bool flush_disable;
67
68 union nv50_outp_atom_mask {
69 struct {
70 bool ctrl:1;
71 };
72 u8 mask;
73 } set, clr;
74 };
75
76 /******************************************************************************
77 * EVO channel
78 *****************************************************************************/
79
80 static int
81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
82 const s32 *oclass, u8 head, void *data, u32 size,
83 struct nv50_chan *chan)
84 {
85 struct nvif_sclass *sclass;
86 int ret, i, n;
87
88 chan->device = device;
89
90 ret = n = nvif_object_sclass_get(disp, &sclass);
91 if (ret < 0)
92 return ret;
93
94 while (oclass[0]) {
95 for (i = 0; i < n; i++) {
96 if (sclass[i].oclass == oclass[0]) {
97 ret = nvif_object_init(disp, 0, oclass[0],
98 data, size, &chan->user);
99 if (ret == 0)
100 nvif_object_map(&chan->user, NULL, 0);
101 nvif_object_sclass_put(&sclass);
102 return ret;
103 }
104 }
105 oclass++;
106 }
107
108 nvif_object_sclass_put(&sclass);
109 return -ENOSYS;
110 }
111
112 static void
113 nv50_chan_destroy(struct nv50_chan *chan)
114 {
115 nvif_object_fini(&chan->user);
116 }
117
118 /******************************************************************************
119 * DMA EVO channel
120 *****************************************************************************/
121
122 void
123 nv50_dmac_destroy(struct nv50_dmac *dmac)
124 {
125 nvif_object_fini(&dmac->vram);
126 nvif_object_fini(&dmac->sync);
127
128 nv50_chan_destroy(&dmac->base);
129
130 nvif_mem_fini(&dmac->push);
131 }
132
133 int
134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
135 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
136 struct nv50_dmac *dmac)
137 {
138 struct nouveau_cli *cli = (void *)device->object.client;
139 struct nv50_disp_core_channel_dma_v0 *args = data;
140 u8 type = NVIF_MEM_COHERENT;
141 int ret;
142
143 mutex_init(&dmac->lock);
144
145 /* Pascal added support for 47-bit physical addresses, but some
146 * parts of EVO still only accept 40-bit PAs.
147 *
148 * To avoid issues on systems with large amounts of RAM, and on
149 * systems where an IOMMU maps pages at a high address, we need
150 * to allocate push buffers in VRAM instead.
151 *
152 * This appears to match NVIDIA's behaviour on Pascal.
153 */
154 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
155 type |= NVIF_MEM_VRAM;
156
157 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
158 if (ret)
159 return ret;
160
161 dmac->ptr = dmac->push.object.map.ptr;
162
163 args->pushbuf = nvif_handle(&dmac->push.object);
164
165 ret = nv50_chan_create(device, disp, oclass, head, data, size,
166 &dmac->base);
167 if (ret)
168 return ret;
169
170 if (!syncbuf)
171 return 0;
172
173 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
174 &(struct nv_dma_v0) {
175 .target = NV_DMA_V0_TARGET_VRAM,
176 .access = NV_DMA_V0_ACCESS_RDWR,
177 .start = syncbuf + 0x0000,
178 .limit = syncbuf + 0x0fff,
179 }, sizeof(struct nv_dma_v0),
180 &dmac->sync);
181 if (ret)
182 return ret;
183
184 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
185 &(struct nv_dma_v0) {
186 .target = NV_DMA_V0_TARGET_VRAM,
187 .access = NV_DMA_V0_ACCESS_RDWR,
188 .start = 0,
189 .limit = device->info.ram_user - 1,
190 }, sizeof(struct nv_dma_v0),
191 &dmac->vram);
192 if (ret)
193 return ret;
194
195 return ret;
196 }
197
198 /******************************************************************************
199 * EVO channel helpers
200 *****************************************************************************/
201 static void
202 evo_flush(struct nv50_dmac *dmac)
203 {
204 /* Push buffer fetches are not coherent with BAR1, we need to ensure
205 * writes have been flushed right through to VRAM before writing PUT.
206 */
207 if (dmac->push.type & NVIF_MEM_VRAM) {
208 struct nvif_device *device = dmac->base.device;
209 nvif_wr32(&device->object, 0x070000, 0x00000001);
210 nvif_msec(device, 2000,
211 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
212 break;
213 );
214 }
215 }
216
217 u32 *
218 evo_wait(struct nv50_dmac *evoc, int nr)
219 {
220 struct nv50_dmac *dmac = evoc;
221 struct nvif_device *device = dmac->base.device;
222 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
223
224 mutex_lock(&dmac->lock);
225 if (put + nr >= (PAGE_SIZE / 4) - 8) {
226 dmac->ptr[put] = 0x20000000;
227 evo_flush(dmac);
228
229 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
230 if (nvif_msec(device, 2000,
231 if (!nvif_rd32(&dmac->base.user, 0x0004))
232 break;
233 ) < 0) {
234 mutex_unlock(&dmac->lock);
235 pr_err("nouveau: evo channel stalled\n");
236 return NULL;
237 }
238
239 put = 0;
240 }
241
242 return dmac->ptr + put;
243 }
244
245 void
246 evo_kick(u32 *push, struct nv50_dmac *evoc)
247 {
248 struct nv50_dmac *dmac = evoc;
249
250 evo_flush(dmac);
251
252 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
253 mutex_unlock(&dmac->lock);
254 }
255
256 /******************************************************************************
257 * Output path helpers
258 *****************************************************************************/
259 static void
260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
261 {
262 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
263 struct {
264 struct nv50_disp_mthd_v1 base;
265 } args = {
266 .base.version = 1,
267 .base.method = NV50_DISP_MTHD_V1_RELEASE,
268 .base.hasht = nv_encoder->dcb->hasht,
269 .base.hashm = nv_encoder->dcb->hashm,
270 };
271
272 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
273 nv_encoder->or = -1;
274 nv_encoder->link = 0;
275 }
276
277 static int
278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
279 {
280 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
281 struct nv50_disp *disp = nv50_disp(drm->dev);
282 struct {
283 struct nv50_disp_mthd_v1 base;
284 struct nv50_disp_acquire_v0 info;
285 } args = {
286 .base.version = 1,
287 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
288 .base.hasht = nv_encoder->dcb->hasht,
289 .base.hashm = nv_encoder->dcb->hashm,
290 };
291 int ret;
292
293 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
294 if (ret) {
295 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
296 return ret;
297 }
298
299 nv_encoder->or = args.info.or;
300 nv_encoder->link = args.info.link;
301 return 0;
302 }
303
304 static int
305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
306 struct drm_crtc_state *crtc_state,
307 struct drm_connector_state *conn_state,
308 struct drm_display_mode *native_mode)
309 {
310 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
311 struct drm_display_mode *mode = &crtc_state->mode;
312 struct drm_connector *connector = conn_state->connector;
313 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
314 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
315
316 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
317 asyc->scaler.full = false;
318 if (!native_mode)
319 return 0;
320
321 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
322 switch (connector->connector_type) {
323 case DRM_MODE_CONNECTOR_LVDS:
324 case DRM_MODE_CONNECTOR_eDP:
325 /* Force use of scaler for non-EDID modes. */
326 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
327 break;
328 mode = native_mode;
329 asyc->scaler.full = true;
330 break;
331 default:
332 break;
333 }
334 } else {
335 mode = native_mode;
336 }
337
338 if (!drm_mode_equal(adjusted_mode, mode)) {
339 drm_mode_copy(adjusted_mode, mode);
340 crtc_state->mode_changed = true;
341 }
342
343 return 0;
344 }
345
346 static int
347 nv50_outp_atomic_check(struct drm_encoder *encoder,
348 struct drm_crtc_state *crtc_state,
349 struct drm_connector_state *conn_state)
350 {
351 struct nouveau_connector *nv_connector =
352 nouveau_connector(conn_state->connector);
353 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
354 nv_connector->native_mode);
355 }
356
357 /******************************************************************************
358 * DAC
359 *****************************************************************************/
360 static void
361 nv50_dac_disable(struct drm_encoder *encoder)
362 {
363 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
364 struct nv50_core *core = nv50_disp(encoder->dev)->core;
365 if (nv_encoder->crtc)
366 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
367 nv_encoder->crtc = NULL;
368 nv50_outp_release(nv_encoder);
369 }
370
371 static void
372 nv50_dac_enable(struct drm_encoder *encoder)
373 {
374 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
375 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
376 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
377 struct nv50_core *core = nv50_disp(encoder->dev)->core;
378
379 nv50_outp_acquire(nv_encoder);
380
381 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
382 asyh->or.depth = 0;
383
384 nv_encoder->crtc = encoder->crtc;
385 }
386
387 static enum drm_connector_status
388 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
389 {
390 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
391 struct nv50_disp *disp = nv50_disp(encoder->dev);
392 struct {
393 struct nv50_disp_mthd_v1 base;
394 struct nv50_disp_dac_load_v0 load;
395 } args = {
396 .base.version = 1,
397 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
398 .base.hasht = nv_encoder->dcb->hasht,
399 .base.hashm = nv_encoder->dcb->hashm,
400 };
401 int ret;
402
403 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
404 if (args.load.data == 0)
405 args.load.data = 340;
406
407 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
408 if (ret || !args.load.load)
409 return connector_status_disconnected;
410
411 return connector_status_connected;
412 }
413
414 static const struct drm_encoder_helper_funcs
415 nv50_dac_help = {
416 .atomic_check = nv50_outp_atomic_check,
417 .enable = nv50_dac_enable,
418 .disable = nv50_dac_disable,
419 .detect = nv50_dac_detect
420 };
421
422 static void
423 nv50_dac_destroy(struct drm_encoder *encoder)
424 {
425 drm_encoder_cleanup(encoder);
426 kfree(encoder);
427 }
428
429 static const struct drm_encoder_funcs
430 nv50_dac_func = {
431 .destroy = nv50_dac_destroy,
432 };
433
434 static int
435 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
436 {
437 struct nouveau_drm *drm = nouveau_drm(connector->dev);
438 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
439 struct nvkm_i2c_bus *bus;
440 struct nouveau_encoder *nv_encoder;
441 struct drm_encoder *encoder;
442 int type = DRM_MODE_ENCODER_DAC;
443
444 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
445 if (!nv_encoder)
446 return -ENOMEM;
447 nv_encoder->dcb = dcbe;
448
449 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
450 if (bus)
451 nv_encoder->i2c = &bus->i2c;
452
453 encoder = to_drm_encoder(nv_encoder);
454 encoder->possible_crtcs = dcbe->heads;
455 encoder->possible_clones = 0;
456 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
457 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
458 drm_encoder_helper_add(encoder, &nv50_dac_help);
459
460 drm_connector_attach_encoder(connector, encoder);
461 return 0;
462 }
463
464 /******************************************************************************
465 * Audio
466 *****************************************************************************/
467 static void
468 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
469 {
470 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
471 struct nv50_disp *disp = nv50_disp(encoder->dev);
472 struct {
473 struct nv50_disp_mthd_v1 base;
474 struct nv50_disp_sor_hda_eld_v0 eld;
475 } args = {
476 .base.version = 1,
477 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
478 .base.hasht = nv_encoder->dcb->hasht,
479 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
480 (0x0100 << nv_crtc->index),
481 };
482
483 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
484 }
485
486 static void
487 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
488 {
489 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
490 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
491 struct nouveau_connector *nv_connector;
492 struct nv50_disp *disp = nv50_disp(encoder->dev);
493 struct __packed {
494 struct {
495 struct nv50_disp_mthd_v1 mthd;
496 struct nv50_disp_sor_hda_eld_v0 eld;
497 } base;
498 u8 data[sizeof(nv_connector->base.eld)];
499 } args = {
500 .base.mthd.version = 1,
501 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
502 .base.mthd.hasht = nv_encoder->dcb->hasht,
503 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
504 (0x0100 << nv_crtc->index),
505 };
506
507 nv_connector = nouveau_encoder_connector_get(nv_encoder);
508 if (!drm_detect_monitor_audio(nv_connector->edid))
509 return;
510
511 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
512
513 nvif_mthd(&disp->disp->object, 0, &args,
514 sizeof(args.base) + drm_eld_size(args.data));
515 }
516
517 /******************************************************************************
518 * HDMI
519 *****************************************************************************/
520 static void
521 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
522 {
523 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
524 struct nv50_disp *disp = nv50_disp(encoder->dev);
525 struct {
526 struct nv50_disp_mthd_v1 base;
527 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
528 } args = {
529 .base.version = 1,
530 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
531 .base.hasht = nv_encoder->dcb->hasht,
532 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
533 (0x0100 << nv_crtc->index),
534 };
535
536 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
537 }
538
539 static void
540 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
541 {
542 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
543 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
544 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
545 struct nv50_disp *disp = nv50_disp(encoder->dev);
546 struct {
547 struct nv50_disp_mthd_v1 base;
548 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
549 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
550 } args = {
551 .base.version = 1,
552 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
553 .base.hasht = nv_encoder->dcb->hasht,
554 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
555 (0x0100 << nv_crtc->index),
556 .pwr.state = 1,
557 .pwr.rekey = 56, /* binary driver, and tegra, constant */
558 };
559 struct nouveau_connector *nv_connector;
560 struct drm_hdmi_info *hdmi;
561 u32 max_ac_packet;
562 union hdmi_infoframe avi_frame;
563 union hdmi_infoframe vendor_frame;
564 bool scdc_supported, high_tmds_clock_ratio = false, scrambling = false;
565 u8 config;
566 int ret;
567 int size;
568
569 nv_connector = nouveau_encoder_connector_get(nv_encoder);
570 if (!drm_detect_hdmi_monitor(nv_connector->edid))
571 return;
572
573 hdmi = &nv_connector->base.display_info.hdmi;
574 scdc_supported = hdmi->scdc.supported;
575
576 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
577 scdc_supported);
578 if (!ret) {
579 /* We have an AVI InfoFrame, populate it to the display */
580 args.pwr.avi_infoframe_length
581 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
582 }
583
584 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
585 &nv_connector->base, mode);
586 if (!ret) {
587 /* We have a Vendor InfoFrame, populate it to the display */
588 args.pwr.vendor_infoframe_length
589 = hdmi_infoframe_pack(&vendor_frame,
590 args.infoframes
591 + args.pwr.avi_infoframe_length,
592 17);
593 }
594
595 max_ac_packet = mode->htotal - mode->hdisplay;
596 max_ac_packet -= args.pwr.rekey;
597 max_ac_packet -= 18; /* constant from tegra */
598 args.pwr.max_ac_packet = max_ac_packet / 32;
599
600 if (hdmi->scdc.scrambling.supported) {
601 high_tmds_clock_ratio = mode->clock > 340000;
602 scrambling = high_tmds_clock_ratio ||
603 hdmi->scdc.scrambling.low_rates;
604 }
605
606 args.pwr.scdc =
607 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
608 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
609
610 size = sizeof(args.base)
611 + sizeof(args.pwr)
612 + args.pwr.avi_infoframe_length
613 + args.pwr.vendor_infoframe_length;
614 nvif_mthd(&disp->disp->object, 0, &args, size);
615
616 nv50_audio_enable(encoder, mode);
617
618 /* If SCDC is supported by the downstream monitor, update
619 * divider / scrambling settings to what we programmed above.
620 */
621 if (!hdmi->scdc.scrambling.supported)
622 return;
623
624 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
625 if (ret < 0) {
626 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
627 return;
628 }
629 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
630 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
631 config |= SCDC_SCRAMBLING_ENABLE * scrambling;
632 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
633 if (ret < 0)
634 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
635 config, ret);
636 }
637
638 /******************************************************************************
639 * MST
640 *****************************************************************************/
641 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
642 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
643 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
644
645 struct nv50_mstm {
646 struct nouveau_encoder *outp;
647
648 struct drm_dp_mst_topology_mgr mgr;
649 struct nv50_msto *msto[4];
650
651 bool modified;
652 bool disabled;
653 int links;
654 };
655
656 struct nv50_mstc {
657 struct nv50_mstm *mstm;
658 struct drm_dp_mst_port *port;
659 struct drm_connector connector;
660
661 struct drm_display_mode *native;
662 struct edid *edid;
663
664 int pbn;
665 };
666
667 struct nv50_msto {
668 struct drm_encoder encoder;
669
670 struct nv50_head *head;
671 struct nv50_mstc *mstc;
672 bool disabled;
673 };
674
675 static struct drm_dp_payload *
676 nv50_msto_payload(struct nv50_msto *msto)
677 {
678 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
679 struct nv50_mstc *mstc = msto->mstc;
680 struct nv50_mstm *mstm = mstc->mstm;
681 int vcpi = mstc->port->vcpi.vcpi, i;
682
683 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
684 for (i = 0; i < mstm->mgr.max_payloads; i++) {
685 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
686 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
687 mstm->outp->base.base.name, i, payload->vcpi,
688 payload->start_slot, payload->num_slots);
689 }
690
691 for (i = 0; i < mstm->mgr.max_payloads; i++) {
692 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
693 if (payload->vcpi == vcpi)
694 return payload;
695 }
696
697 return NULL;
698 }
699
700 static void
701 nv50_msto_cleanup(struct nv50_msto *msto)
702 {
703 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
704 struct nv50_mstc *mstc = msto->mstc;
705 struct nv50_mstm *mstm = mstc->mstm;
706
707 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
708 if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
709 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
710 if (msto->disabled) {
711 msto->mstc = NULL;
712 msto->head = NULL;
713 msto->disabled = false;
714 }
715 }
716
717 static void
718 nv50_msto_prepare(struct nv50_msto *msto)
719 {
720 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
721 struct nv50_mstc *mstc = msto->mstc;
722 struct nv50_mstm *mstm = mstc->mstm;
723 struct {
724 struct nv50_disp_mthd_v1 base;
725 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
726 } args = {
727 .base.version = 1,
728 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
729 .base.hasht = mstm->outp->dcb->hasht,
730 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
731 (0x0100 << msto->head->base.index),
732 };
733
734 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
735 if (mstc->port && mstc->port->vcpi.vcpi > 0) {
736 struct drm_dp_payload *payload = nv50_msto_payload(msto);
737 if (payload) {
738 args.vcpi.start_slot = payload->start_slot;
739 args.vcpi.num_slots = payload->num_slots;
740 args.vcpi.pbn = mstc->port->vcpi.pbn;
741 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
742 }
743 }
744
745 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
746 msto->encoder.name, msto->head->base.base.name,
747 args.vcpi.start_slot, args.vcpi.num_slots,
748 args.vcpi.pbn, args.vcpi.aligned_pbn);
749 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
750 }
751
752 static int
753 nv50_msto_atomic_check(struct drm_encoder *encoder,
754 struct drm_crtc_state *crtc_state,
755 struct drm_connector_state *conn_state)
756 {
757 struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
758 struct nv50_mstm *mstm = mstc->mstm;
759 int bpp = conn_state->connector->display_info.bpc * 3;
760 int slots;
761
762 mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
763
764 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
765 if (slots < 0)
766 return slots;
767
768 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
769 mstc->native);
770 }
771
772 static void
773 nv50_msto_enable(struct drm_encoder *encoder)
774 {
775 struct nv50_head *head = nv50_head(encoder->crtc);
776 struct nv50_msto *msto = nv50_msto(encoder);
777 struct nv50_mstc *mstc = NULL;
778 struct nv50_mstm *mstm = NULL;
779 struct drm_connector *connector;
780 struct drm_connector_list_iter conn_iter;
781 u8 proto, depth;
782 int slots;
783 bool r;
784
785 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
786 drm_for_each_connector_iter(connector, &conn_iter) {
787 if (connector->state->best_encoder == &msto->encoder) {
788 mstc = nv50_mstc(connector);
789 mstm = mstc->mstm;
790 break;
791 }
792 }
793 drm_connector_list_iter_end(&conn_iter);
794
795 if (WARN_ON(!mstc))
796 return;
797
798 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
799 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
800 WARN_ON(!r);
801
802 if (!mstm->links++)
803 nv50_outp_acquire(mstm->outp);
804
805 if (mstm->outp->link & 1)
806 proto = 0x8;
807 else
808 proto = 0x9;
809
810 switch (mstc->connector.display_info.bpc) {
811 case 6: depth = 0x2; break;
812 case 8: depth = 0x5; break;
813 case 10:
814 default: depth = 0x6; break;
815 }
816
817 mstm->outp->update(mstm->outp, head->base.index,
818 nv50_head_atom(head->base.base.state), proto, depth);
819
820 msto->head = head;
821 msto->mstc = mstc;
822 mstm->modified = true;
823 }
824
825 static void
826 nv50_msto_disable(struct drm_encoder *encoder)
827 {
828 struct nv50_msto *msto = nv50_msto(encoder);
829 struct nv50_mstc *mstc = msto->mstc;
830 struct nv50_mstm *mstm = mstc->mstm;
831
832 if (mstc->port)
833 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
834
835 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
836 mstm->modified = true;
837 if (!--mstm->links)
838 mstm->disabled = true;
839 msto->disabled = true;
840 }
841
842 static const struct drm_encoder_helper_funcs
843 nv50_msto_help = {
844 .disable = nv50_msto_disable,
845 .enable = nv50_msto_enable,
846 .atomic_check = nv50_msto_atomic_check,
847 };
848
849 static void
850 nv50_msto_destroy(struct drm_encoder *encoder)
851 {
852 struct nv50_msto *msto = nv50_msto(encoder);
853 drm_encoder_cleanup(&msto->encoder);
854 kfree(msto);
855 }
856
857 static const struct drm_encoder_funcs
858 nv50_msto = {
859 .destroy = nv50_msto_destroy,
860 };
861
862 static int
863 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
864 struct nv50_msto **pmsto)
865 {
866 struct nv50_msto *msto;
867 int ret;
868
869 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
870 return -ENOMEM;
871
872 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
873 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
874 if (ret) {
875 kfree(*pmsto);
876 *pmsto = NULL;
877 return ret;
878 }
879
880 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
881 msto->encoder.possible_crtcs = heads;
882 return 0;
883 }
884
885 static struct drm_encoder *
886 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
887 struct drm_connector_state *connector_state)
888 {
889 struct nv50_head *head = nv50_head(connector_state->crtc);
890 struct nv50_mstc *mstc = nv50_mstc(connector);
891
892 return &mstc->mstm->msto[head->base.index]->encoder;
893 }
894
895 static struct drm_encoder *
896 nv50_mstc_best_encoder(struct drm_connector *connector)
897 {
898 struct nv50_mstc *mstc = nv50_mstc(connector);
899
900 return &mstc->mstm->msto[0]->encoder;
901 }
902
903 static enum drm_mode_status
904 nv50_mstc_mode_valid(struct drm_connector *connector,
905 struct drm_display_mode *mode)
906 {
907 return MODE_OK;
908 }
909
910 static int
911 nv50_mstc_get_modes(struct drm_connector *connector)
912 {
913 struct nv50_mstc *mstc = nv50_mstc(connector);
914 int ret = 0;
915
916 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
917 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
918 if (mstc->edid)
919 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
920
921 if (!mstc->connector.display_info.bpc)
922 mstc->connector.display_info.bpc = 8;
923
924 if (mstc->native)
925 drm_mode_destroy(mstc->connector.dev, mstc->native);
926 mstc->native = nouveau_conn_native_mode(&mstc->connector);
927 return ret;
928 }
929
930 static const struct drm_connector_helper_funcs
931 nv50_mstc_help = {
932 .get_modes = nv50_mstc_get_modes,
933 .mode_valid = nv50_mstc_mode_valid,
934 .best_encoder = nv50_mstc_best_encoder,
935 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
936 };
937
938 static enum drm_connector_status
939 nv50_mstc_detect(struct drm_connector *connector, bool force)
940 {
941 struct nv50_mstc *mstc = nv50_mstc(connector);
942 enum drm_connector_status conn_status;
943 int ret;
944
945 if (!mstc->port)
946 return connector_status_disconnected;
947
948 ret = pm_runtime_get_sync(connector->dev->dev);
949 if (ret < 0 && ret != -EACCES)
950 return connector_status_disconnected;
951
952 conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr,
953 mstc->port);
954
955 pm_runtime_mark_last_busy(connector->dev->dev);
956 pm_runtime_put_autosuspend(connector->dev->dev);
957 return conn_status;
958 }
959
960 static void
961 nv50_mstc_destroy(struct drm_connector *connector)
962 {
963 struct nv50_mstc *mstc = nv50_mstc(connector);
964 drm_connector_cleanup(&mstc->connector);
965 kfree(mstc);
966 }
967
968 static const struct drm_connector_funcs
969 nv50_mstc = {
970 .reset = nouveau_conn_reset,
971 .detect = nv50_mstc_detect,
972 .fill_modes = drm_helper_probe_single_connector_modes,
973 .destroy = nv50_mstc_destroy,
974 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
975 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
976 .atomic_set_property = nouveau_conn_atomic_set_property,
977 .atomic_get_property = nouveau_conn_atomic_get_property,
978 };
979
980 static int
981 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
982 const char *path, struct nv50_mstc **pmstc)
983 {
984 struct drm_device *dev = mstm->outp->base.base.dev;
985 struct nv50_mstc *mstc;
986 int ret, i;
987
988 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
989 return -ENOMEM;
990 mstc->mstm = mstm;
991 mstc->port = port;
992
993 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
994 DRM_MODE_CONNECTOR_DisplayPort);
995 if (ret) {
996 kfree(*pmstc);
997 *pmstc = NULL;
998 return ret;
999 }
1000
1001 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1002
1003 mstc->connector.funcs->reset(&mstc->connector);
1004 nouveau_conn_attach_properties(&mstc->connector);
1005
1006 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
1007 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1008
1009 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1010 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1011 drm_connector_set_path_property(&mstc->connector, path);
1012 return 0;
1013 }
1014
1015 static void
1016 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1017 {
1018 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1019 struct drm_encoder *encoder;
1020 int ret;
1021
1022 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1023 ret = drm_dp_check_act_status(&mstm->mgr);
1024
1025 ret = drm_dp_update_payload_part2(&mstm->mgr);
1026
1027 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1028 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1029 struct nv50_msto *msto = nv50_msto(encoder);
1030 struct nv50_mstc *mstc = msto->mstc;
1031 if (mstc && mstc->mstm == mstm)
1032 nv50_msto_cleanup(msto);
1033 }
1034 }
1035
1036 mstm->modified = false;
1037 }
1038
1039 static void
1040 nv50_mstm_prepare(struct nv50_mstm *mstm)
1041 {
1042 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1043 struct drm_encoder *encoder;
1044 int ret;
1045
1046 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1047 ret = drm_dp_update_payload_part1(&mstm->mgr);
1048
1049 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1050 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1051 struct nv50_msto *msto = nv50_msto(encoder);
1052 struct nv50_mstc *mstc = msto->mstc;
1053 if (mstc && mstc->mstm == mstm)
1054 nv50_msto_prepare(msto);
1055 }
1056 }
1057
1058 if (mstm->disabled) {
1059 if (!mstm->links)
1060 nv50_outp_release(mstm->outp);
1061 mstm->disabled = false;
1062 }
1063 }
1064
1065 static void
1066 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
1067 {
1068 struct nv50_mstm *mstm = nv50_mstm(mgr);
1069 drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
1070 }
1071
1072 static void
1073 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1074 struct drm_connector *connector)
1075 {
1076 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1077 struct nv50_mstc *mstc = nv50_mstc(connector);
1078
1079 drm_connector_unregister(&mstc->connector);
1080
1081 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1082
1083 drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1084 mstc->port = NULL;
1085 drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1086
1087 drm_connector_put(&mstc->connector);
1088 }
1089
1090 static void
1091 nv50_mstm_register_connector(struct drm_connector *connector)
1092 {
1093 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1094
1095 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1096
1097 drm_connector_register(connector);
1098 }
1099
1100 static struct drm_connector *
1101 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1102 struct drm_dp_mst_port *port, const char *path)
1103 {
1104 struct nv50_mstm *mstm = nv50_mstm(mgr);
1105 struct nv50_mstc *mstc;
1106 int ret;
1107
1108 ret = nv50_mstc_new(mstm, port, path, &mstc);
1109 if (ret) {
1110 if (mstc)
1111 mstc->connector.funcs->destroy(&mstc->connector);
1112 return NULL;
1113 }
1114
1115 return &mstc->connector;
1116 }
1117
1118 static const struct drm_dp_mst_topology_cbs
1119 nv50_mstm = {
1120 .add_connector = nv50_mstm_add_connector,
1121 .register_connector = nv50_mstm_register_connector,
1122 .destroy_connector = nv50_mstm_destroy_connector,
1123 .hotplug = nv50_mstm_hotplug,
1124 };
1125
1126 void
1127 nv50_mstm_service(struct nv50_mstm *mstm)
1128 {
1129 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1130 bool handled = true;
1131 int ret;
1132 u8 esi[8] = {};
1133
1134 if (!aux)
1135 return;
1136
1137 while (handled) {
1138 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1139 if (ret != 8) {
1140 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1141 return;
1142 }
1143
1144 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1145 if (!handled)
1146 break;
1147
1148 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1149 }
1150 }
1151
1152 void
1153 nv50_mstm_remove(struct nv50_mstm *mstm)
1154 {
1155 if (mstm)
1156 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1157 }
1158
1159 static int
1160 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1161 {
1162 struct nouveau_encoder *outp = mstm->outp;
1163 struct {
1164 struct nv50_disp_mthd_v1 base;
1165 struct nv50_disp_sor_dp_mst_link_v0 mst;
1166 } args = {
1167 .base.version = 1,
1168 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1169 .base.hasht = outp->dcb->hasht,
1170 .base.hashm = outp->dcb->hashm,
1171 .mst.state = state,
1172 };
1173 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1174 struct nvif_object *disp = &drm->display->disp.object;
1175 int ret;
1176
1177 if (dpcd >= 0x12) {
1178 /* Even if we're enabling MST, start with disabling the
1179 * branching unit to clear any sink-side MST topology state
1180 * that wasn't set by us
1181 */
1182 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1183 if (ret < 0)
1184 return ret;
1185
1186 if (state) {
1187 /* Now, start initializing */
1188 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1189 DP_MST_EN);
1190 if (ret < 0)
1191 return ret;
1192 }
1193 }
1194
1195 return nvif_mthd(disp, 0, &args, sizeof(args));
1196 }
1197
1198 int
1199 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1200 {
1201 struct drm_dp_aux *aux;
1202 int ret;
1203 bool old_state, new_state;
1204 u8 mstm_ctrl;
1205
1206 if (!mstm)
1207 return 0;
1208
1209 mutex_lock(&mstm->mgr.lock);
1210
1211 old_state = mstm->mgr.mst_state;
1212 new_state = old_state;
1213 aux = mstm->mgr.aux;
1214
1215 if (old_state) {
1216 /* Just check that the MST hub is still as we expect it */
1217 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1218 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1219 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1220 new_state = false;
1221 }
1222 } else if (dpcd[0] >= 0x12) {
1223 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1224 if (ret < 0)
1225 goto probe_error;
1226
1227 if (!(dpcd[1] & DP_MST_CAP))
1228 dpcd[0] = 0x11;
1229 else
1230 new_state = allow;
1231 }
1232
1233 if (new_state == old_state) {
1234 mutex_unlock(&mstm->mgr.lock);
1235 return new_state;
1236 }
1237
1238 ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1239 if (ret)
1240 goto probe_error;
1241
1242 mutex_unlock(&mstm->mgr.lock);
1243
1244 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1245 if (ret)
1246 return nv50_mstm_enable(mstm, dpcd[0], 0);
1247
1248 return new_state;
1249
1250 probe_error:
1251 mutex_unlock(&mstm->mgr.lock);
1252 return ret;
1253 }
1254
1255 static void
1256 nv50_mstm_fini(struct nv50_mstm *mstm)
1257 {
1258 if (mstm && mstm->mgr.mst_state)
1259 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1260 }
1261
1262 static void
1263 nv50_mstm_init(struct nv50_mstm *mstm)
1264 {
1265 if (mstm && mstm->mgr.mst_state)
1266 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1267 }
1268
1269 static void
1270 nv50_mstm_del(struct nv50_mstm **pmstm)
1271 {
1272 struct nv50_mstm *mstm = *pmstm;
1273 if (mstm) {
1274 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1275 kfree(*pmstm);
1276 *pmstm = NULL;
1277 }
1278 }
1279
1280 static int
1281 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1282 int conn_base_id, struct nv50_mstm **pmstm)
1283 {
1284 const int max_payloads = hweight8(outp->dcb->heads);
1285 struct drm_device *dev = outp->base.base.dev;
1286 struct nv50_mstm *mstm;
1287 int ret, i;
1288 u8 dpcd;
1289
1290 /* This is a workaround for some monitors not functioning
1291 * correctly in MST mode on initial module load. I think
1292 * some bad interaction with the VBIOS may be responsible.
1293 *
1294 * A good ol' off and on again seems to work here ;)
1295 */
1296 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1297 if (ret >= 0 && dpcd >= 0x12)
1298 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1299
1300 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1301 return -ENOMEM;
1302 mstm->outp = outp;
1303 mstm->mgr.cbs = &nv50_mstm;
1304
1305 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1306 max_payloads, conn_base_id);
1307 if (ret)
1308 return ret;
1309
1310 for (i = 0; i < max_payloads; i++) {
1311 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1312 i, &mstm->msto[i]);
1313 if (ret)
1314 return ret;
1315 }
1316
1317 return 0;
1318 }
1319
1320 /******************************************************************************
1321 * SOR
1322 *****************************************************************************/
1323 static void
1324 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1325 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1326 {
1327 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1328 struct nv50_core *core = disp->core;
1329
1330 if (!asyh) {
1331 nv_encoder->ctrl &= ~BIT(head);
1332 if (!(nv_encoder->ctrl & 0x0000000f))
1333 nv_encoder->ctrl = 0;
1334 } else {
1335 nv_encoder->ctrl |= proto << 8;
1336 nv_encoder->ctrl |= BIT(head);
1337 asyh->or.depth = depth;
1338 }
1339
1340 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1341 }
1342
1343 static void
1344 nv50_sor_disable(struct drm_encoder *encoder)
1345 {
1346 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1347 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1348
1349 nv_encoder->crtc = NULL;
1350
1351 if (nv_crtc) {
1352 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1353 u8 pwr;
1354
1355 if (aux) {
1356 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1357 if (ret == 0) {
1358 pwr &= ~DP_SET_POWER_MASK;
1359 pwr |= DP_SET_POWER_D3;
1360 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1361 }
1362 }
1363
1364 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1365 nv50_audio_disable(encoder, nv_crtc);
1366 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1367 nv50_outp_release(nv_encoder);
1368 }
1369 }
1370
1371 static void
1372 nv50_sor_enable(struct drm_encoder *encoder)
1373 {
1374 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1375 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1376 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1377 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1378 struct {
1379 struct nv50_disp_mthd_v1 base;
1380 struct nv50_disp_sor_lvds_script_v0 lvds;
1381 } lvds = {
1382 .base.version = 1,
1383 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1384 .base.hasht = nv_encoder->dcb->hasht,
1385 .base.hashm = nv_encoder->dcb->hashm,
1386 };
1387 struct nv50_disp *disp = nv50_disp(encoder->dev);
1388 struct drm_device *dev = encoder->dev;
1389 struct nouveau_drm *drm = nouveau_drm(dev);
1390 struct nouveau_connector *nv_connector;
1391 struct nvbios *bios = &drm->vbios;
1392 u8 proto = 0xf;
1393 u8 depth = 0x0;
1394
1395 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1396 nv_encoder->crtc = encoder->crtc;
1397 nv50_outp_acquire(nv_encoder);
1398
1399 switch (nv_encoder->dcb->type) {
1400 case DCB_OUTPUT_TMDS:
1401 if (nv_encoder->link & 1) {
1402 proto = 0x1;
1403 /* Only enable dual-link if:
1404 * - Need to (i.e. rate > 165MHz)
1405 * - DCB says we can
1406 * - Not an HDMI monitor, since there's no dual-link
1407 * on HDMI.
1408 */
1409 if (mode->clock >= 165000 &&
1410 nv_encoder->dcb->duallink_possible &&
1411 !drm_detect_hdmi_monitor(nv_connector->edid))
1412 proto |= 0x4;
1413 } else {
1414 proto = 0x2;
1415 }
1416
1417 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1418 break;
1419 case DCB_OUTPUT_LVDS:
1420 proto = 0x0;
1421
1422 if (bios->fp_no_ddc) {
1423 if (bios->fp.dual_link)
1424 lvds.lvds.script |= 0x0100;
1425 if (bios->fp.if_is_24bit)
1426 lvds.lvds.script |= 0x0200;
1427 } else {
1428 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1429 if (((u8 *)nv_connector->edid)[121] == 2)
1430 lvds.lvds.script |= 0x0100;
1431 } else
1432 if (mode->clock >= bios->fp.duallink_transition_clk) {
1433 lvds.lvds.script |= 0x0100;
1434 }
1435
1436 if (lvds.lvds.script & 0x0100) {
1437 if (bios->fp.strapless_is_24bit & 2)
1438 lvds.lvds.script |= 0x0200;
1439 } else {
1440 if (bios->fp.strapless_is_24bit & 1)
1441 lvds.lvds.script |= 0x0200;
1442 }
1443
1444 if (nv_connector->base.display_info.bpc == 8)
1445 lvds.lvds.script |= 0x0200;
1446 }
1447
1448 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1449 break;
1450 case DCB_OUTPUT_DP:
1451 if (nv_connector->base.display_info.bpc == 6)
1452 depth = 0x2;
1453 else
1454 if (nv_connector->base.display_info.bpc == 8)
1455 depth = 0x5;
1456 else
1457 depth = 0x6;
1458
1459 if (nv_encoder->link & 1)
1460 proto = 0x8;
1461 else
1462 proto = 0x9;
1463
1464 nv50_audio_enable(encoder, mode);
1465 break;
1466 default:
1467 BUG();
1468 break;
1469 }
1470
1471 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1472 }
1473
1474 static const struct drm_encoder_helper_funcs
1475 nv50_sor_help = {
1476 .atomic_check = nv50_outp_atomic_check,
1477 .enable = nv50_sor_enable,
1478 .disable = nv50_sor_disable,
1479 };
1480
1481 static void
1482 nv50_sor_destroy(struct drm_encoder *encoder)
1483 {
1484 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1485 nv50_mstm_del(&nv_encoder->dp.mstm);
1486 drm_encoder_cleanup(encoder);
1487 kfree(encoder);
1488 }
1489
1490 static const struct drm_encoder_funcs
1491 nv50_sor_func = {
1492 .destroy = nv50_sor_destroy,
1493 };
1494
1495 static int
1496 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1497 {
1498 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1499 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1500 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1501 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1502 struct nouveau_encoder *nv_encoder;
1503 struct drm_encoder *encoder;
1504 u8 ver, hdr, cnt, len;
1505 u32 data;
1506 int type, ret;
1507
1508 switch (dcbe->type) {
1509 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1510 case DCB_OUTPUT_TMDS:
1511 case DCB_OUTPUT_DP:
1512 default:
1513 type = DRM_MODE_ENCODER_TMDS;
1514 break;
1515 }
1516
1517 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1518 if (!nv_encoder)
1519 return -ENOMEM;
1520 nv_encoder->dcb = dcbe;
1521 nv_encoder->update = nv50_sor_update;
1522
1523 encoder = to_drm_encoder(nv_encoder);
1524 encoder->possible_crtcs = dcbe->heads;
1525 encoder->possible_clones = 0;
1526 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1527 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1528 drm_encoder_helper_add(encoder, &nv50_sor_help);
1529
1530 drm_connector_attach_encoder(connector, encoder);
1531
1532 if (dcbe->type == DCB_OUTPUT_DP) {
1533 struct nv50_disp *disp = nv50_disp(encoder->dev);
1534 struct nvkm_i2c_aux *aux =
1535 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1536 if (aux) {
1537 if (disp->disp->object.oclass < GF110_DISP) {
1538 /* HW has no support for address-only
1539 * transactions, so we're required to
1540 * use custom I2C-over-AUX code.
1541 */
1542 nv_encoder->i2c = &aux->i2c;
1543 } else {
1544 nv_encoder->i2c = &nv_connector->aux.ddc;
1545 }
1546 nv_encoder->aux = aux;
1547 }
1548
1549 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1550 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1551 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1552 nv_connector->base.base.id,
1553 &nv_encoder->dp.mstm);
1554 if (ret)
1555 return ret;
1556 }
1557 } else {
1558 struct nvkm_i2c_bus *bus =
1559 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1560 if (bus)
1561 nv_encoder->i2c = &bus->i2c;
1562 }
1563
1564 return 0;
1565 }
1566
1567 /******************************************************************************
1568 * PIOR
1569 *****************************************************************************/
1570 static int
1571 nv50_pior_atomic_check(struct drm_encoder *encoder,
1572 struct drm_crtc_state *crtc_state,
1573 struct drm_connector_state *conn_state)
1574 {
1575 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1576 if (ret)
1577 return ret;
1578 crtc_state->adjusted_mode.clock *= 2;
1579 return 0;
1580 }
1581
1582 static void
1583 nv50_pior_disable(struct drm_encoder *encoder)
1584 {
1585 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1586 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1587 if (nv_encoder->crtc)
1588 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1589 nv_encoder->crtc = NULL;
1590 nv50_outp_release(nv_encoder);
1591 }
1592
1593 static void
1594 nv50_pior_enable(struct drm_encoder *encoder)
1595 {
1596 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1597 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1598 struct nouveau_connector *nv_connector;
1599 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1600 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1601 u8 owner = 1 << nv_crtc->index;
1602 u8 proto;
1603
1604 nv50_outp_acquire(nv_encoder);
1605
1606 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1607 switch (nv_connector->base.display_info.bpc) {
1608 case 10: asyh->or.depth = 0x6; break;
1609 case 8: asyh->or.depth = 0x5; break;
1610 case 6: asyh->or.depth = 0x2; break;
1611 default: asyh->or.depth = 0x0; break;
1612 }
1613
1614 switch (nv_encoder->dcb->type) {
1615 case DCB_OUTPUT_TMDS:
1616 case DCB_OUTPUT_DP:
1617 proto = 0x0;
1618 break;
1619 default:
1620 BUG();
1621 break;
1622 }
1623
1624 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1625 nv_encoder->crtc = encoder->crtc;
1626 }
1627
1628 static const struct drm_encoder_helper_funcs
1629 nv50_pior_help = {
1630 .atomic_check = nv50_pior_atomic_check,
1631 .enable = nv50_pior_enable,
1632 .disable = nv50_pior_disable,
1633 };
1634
1635 static void
1636 nv50_pior_destroy(struct drm_encoder *encoder)
1637 {
1638 drm_encoder_cleanup(encoder);
1639 kfree(encoder);
1640 }
1641
1642 static const struct drm_encoder_funcs
1643 nv50_pior_func = {
1644 .destroy = nv50_pior_destroy,
1645 };
1646
1647 static int
1648 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1649 {
1650 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1651 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1652 struct nvkm_i2c_bus *bus = NULL;
1653 struct nvkm_i2c_aux *aux = NULL;
1654 struct i2c_adapter *ddc;
1655 struct nouveau_encoder *nv_encoder;
1656 struct drm_encoder *encoder;
1657 int type;
1658
1659 switch (dcbe->type) {
1660 case DCB_OUTPUT_TMDS:
1661 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1662 ddc = bus ? &bus->i2c : NULL;
1663 type = DRM_MODE_ENCODER_TMDS;
1664 break;
1665 case DCB_OUTPUT_DP:
1666 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1667 ddc = aux ? &aux->i2c : NULL;
1668 type = DRM_MODE_ENCODER_TMDS;
1669 break;
1670 default:
1671 return -ENODEV;
1672 }
1673
1674 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1675 if (!nv_encoder)
1676 return -ENOMEM;
1677 nv_encoder->dcb = dcbe;
1678 nv_encoder->i2c = ddc;
1679 nv_encoder->aux = aux;
1680
1681 encoder = to_drm_encoder(nv_encoder);
1682 encoder->possible_crtcs = dcbe->heads;
1683 encoder->possible_clones = 0;
1684 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1685 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1686 drm_encoder_helper_add(encoder, &nv50_pior_help);
1687
1688 drm_connector_attach_encoder(connector, encoder);
1689 return 0;
1690 }
1691
1692 /******************************************************************************
1693 * Atomic
1694 *****************************************************************************/
1695
1696 static void
1697 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1698 {
1699 struct nouveau_drm *drm = nouveau_drm(state->dev);
1700 struct nv50_disp *disp = nv50_disp(drm->dev);
1701 struct nv50_core *core = disp->core;
1702 struct nv50_mstm *mstm;
1703 struct drm_encoder *encoder;
1704
1705 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1706
1707 drm_for_each_encoder(encoder, drm->dev) {
1708 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1709 mstm = nouveau_encoder(encoder)->dp.mstm;
1710 if (mstm && mstm->modified)
1711 nv50_mstm_prepare(mstm);
1712 }
1713 }
1714
1715 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1716 core->func->update(core, interlock, true);
1717 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1718 disp->core->chan.base.device))
1719 NV_ERROR(drm, "core notifier timeout\n");
1720
1721 drm_for_each_encoder(encoder, drm->dev) {
1722 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1723 mstm = nouveau_encoder(encoder)->dp.mstm;
1724 if (mstm && mstm->modified)
1725 nv50_mstm_cleanup(mstm);
1726 }
1727 }
1728 }
1729
1730 static void
1731 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1732 {
1733 struct drm_plane_state *new_plane_state;
1734 struct drm_plane *plane;
1735 int i;
1736
1737 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1738 struct nv50_wndw *wndw = nv50_wndw(plane);
1739 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1740 if (wndw->func->update)
1741 wndw->func->update(wndw, interlock);
1742 }
1743 }
1744 }
1745
1746 static void
1747 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1748 {
1749 struct drm_device *dev = state->dev;
1750 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1751 struct drm_crtc *crtc;
1752 struct drm_plane_state *new_plane_state;
1753 struct drm_plane *plane;
1754 struct nouveau_drm *drm = nouveau_drm(dev);
1755 struct nv50_disp *disp = nv50_disp(dev);
1756 struct nv50_atom *atom = nv50_atom(state);
1757 struct nv50_outp_atom *outp, *outt;
1758 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1759 int i;
1760
1761 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1762 drm_atomic_helper_wait_for_fences(dev, state, false);
1763 drm_atomic_helper_wait_for_dependencies(state);
1764 drm_atomic_helper_update_legacy_modeset_state(dev, state);
1765
1766 if (atom->lock_core)
1767 mutex_lock(&disp->mutex);
1768
1769 /* Disable head(s). */
1770 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1771 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1772 struct nv50_head *head = nv50_head(crtc);
1773
1774 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1775 asyh->clr.mask, asyh->set.mask);
1776 if (old_crtc_state->active && !new_crtc_state->active)
1777 drm_crtc_vblank_off(crtc);
1778
1779 if (asyh->clr.mask) {
1780 nv50_head_flush_clr(head, asyh, atom->flush_disable);
1781 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1782 }
1783 }
1784
1785 /* Disable plane(s). */
1786 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1787 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1788 struct nv50_wndw *wndw = nv50_wndw(plane);
1789
1790 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1791 asyw->clr.mask, asyw->set.mask);
1792 if (!asyw->clr.mask)
1793 continue;
1794
1795 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1796 }
1797
1798 /* Disable output path(s). */
1799 list_for_each_entry(outp, &atom->outp, head) {
1800 const struct drm_encoder_helper_funcs *help;
1801 struct drm_encoder *encoder;
1802
1803 encoder = outp->encoder;
1804 help = encoder->helper_private;
1805
1806 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1807 outp->clr.mask, outp->set.mask);
1808
1809 if (outp->clr.mask) {
1810 help->disable(encoder);
1811 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1812 if (outp->flush_disable) {
1813 nv50_disp_atomic_commit_wndw(state, interlock);
1814 nv50_disp_atomic_commit_core(state, interlock);
1815 memset(interlock, 0x00, sizeof(interlock));
1816 }
1817 }
1818 }
1819
1820 /* Flush disable. */
1821 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1822 if (atom->flush_disable) {
1823 nv50_disp_atomic_commit_wndw(state, interlock);
1824 nv50_disp_atomic_commit_core(state, interlock);
1825 memset(interlock, 0x00, sizeof(interlock));
1826 }
1827 }
1828
1829 /* Update output path(s). */
1830 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1831 const struct drm_encoder_helper_funcs *help;
1832 struct drm_encoder *encoder;
1833
1834 encoder = outp->encoder;
1835 help = encoder->helper_private;
1836
1837 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1838 outp->set.mask, outp->clr.mask);
1839
1840 if (outp->set.mask) {
1841 help->enable(encoder);
1842 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1843 }
1844
1845 list_del(&outp->head);
1846 kfree(outp);
1847 }
1848
1849 /* Update head(s). */
1850 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1851 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1852 struct nv50_head *head = nv50_head(crtc);
1853
1854 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1855 asyh->set.mask, asyh->clr.mask);
1856
1857 if (asyh->set.mask) {
1858 nv50_head_flush_set(head, asyh);
1859 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1860 }
1861
1862 if (new_crtc_state->active) {
1863 if (!old_crtc_state->active)
1864 drm_crtc_vblank_on(crtc);
1865 if (new_crtc_state->event)
1866 drm_crtc_vblank_get(crtc);
1867 }
1868 }
1869
1870 /* Update plane(s). */
1871 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1872 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1873 struct nv50_wndw *wndw = nv50_wndw(plane);
1874
1875 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1876 asyw->set.mask, asyw->clr.mask);
1877 if ( !asyw->set.mask &&
1878 (!asyw->clr.mask || atom->flush_disable))
1879 continue;
1880
1881 nv50_wndw_flush_set(wndw, interlock, asyw);
1882 }
1883
1884 /* Flush update. */
1885 nv50_disp_atomic_commit_wndw(state, interlock);
1886
1887 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1888 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1889 interlock[NV50_DISP_INTERLOCK_OVLY] ||
1890 interlock[NV50_DISP_INTERLOCK_WNDW] ||
1891 !atom->state.legacy_cursor_update)
1892 nv50_disp_atomic_commit_core(state, interlock);
1893 else
1894 disp->core->func->update(disp->core, interlock, false);
1895 }
1896
1897 if (atom->lock_core)
1898 mutex_unlock(&disp->mutex);
1899
1900 /* Wait for HW to signal completion. */
1901 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1902 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1903 struct nv50_wndw *wndw = nv50_wndw(plane);
1904 int ret = nv50_wndw_wait_armed(wndw, asyw);
1905 if (ret)
1906 NV_ERROR(drm, "%s: timeout\n", plane->name);
1907 }
1908
1909 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1910 if (new_crtc_state->event) {
1911 unsigned long flags;
1912 /* Get correct count/ts if racing with vblank irq */
1913 if (new_crtc_state->active)
1914 drm_crtc_accurate_vblank_count(crtc);
1915 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1916 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1917 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1918
1919 new_crtc_state->event = NULL;
1920 if (new_crtc_state->active)
1921 drm_crtc_vblank_put(crtc);
1922 }
1923 }
1924
1925 drm_atomic_helper_commit_hw_done(state);
1926 drm_atomic_helper_cleanup_planes(dev, state);
1927 drm_atomic_helper_commit_cleanup_done(state);
1928 drm_atomic_state_put(state);
1929 }
1930
1931 static void
1932 nv50_disp_atomic_commit_work(struct work_struct *work)
1933 {
1934 struct drm_atomic_state *state =
1935 container_of(work, typeof(*state), commit_work);
1936 nv50_disp_atomic_commit_tail(state);
1937 }
1938
1939 static int
1940 nv50_disp_atomic_commit(struct drm_device *dev,
1941 struct drm_atomic_state *state, bool nonblock)
1942 {
1943 struct nouveau_drm *drm = nouveau_drm(dev);
1944 struct drm_plane_state *new_plane_state;
1945 struct drm_plane *plane;
1946 struct drm_crtc *crtc;
1947 bool active = false;
1948 int ret, i;
1949
1950 ret = pm_runtime_get_sync(dev->dev);
1951 if (ret < 0 && ret != -EACCES)
1952 return ret;
1953
1954 ret = drm_atomic_helper_setup_commit(state, nonblock);
1955 if (ret)
1956 goto done;
1957
1958 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
1959
1960 ret = drm_atomic_helper_prepare_planes(dev, state);
1961 if (ret)
1962 goto done;
1963
1964 if (!nonblock) {
1965 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
1966 if (ret)
1967 goto err_cleanup;
1968 }
1969
1970 ret = drm_atomic_helper_swap_state(state, true);
1971 if (ret)
1972 goto err_cleanup;
1973
1974 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1975 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1976 struct nv50_wndw *wndw = nv50_wndw(plane);
1977
1978 if (asyw->set.image)
1979 nv50_wndw_ntfy_enable(wndw, asyw);
1980 }
1981
1982 drm_atomic_state_get(state);
1983
1984 if (nonblock)
1985 queue_work(system_unbound_wq, &state->commit_work);
1986 else
1987 nv50_disp_atomic_commit_tail(state);
1988
1989 drm_for_each_crtc(crtc, dev) {
1990 if (crtc->state->active) {
1991 if (!drm->have_disp_power_ref) {
1992 drm->have_disp_power_ref = true;
1993 return 0;
1994 }
1995 active = true;
1996 break;
1997 }
1998 }
1999
2000 if (!active && drm->have_disp_power_ref) {
2001 pm_runtime_put_autosuspend(dev->dev);
2002 drm->have_disp_power_ref = false;
2003 }
2004
2005 err_cleanup:
2006 if (ret)
2007 drm_atomic_helper_cleanup_planes(dev, state);
2008 done:
2009 pm_runtime_put_autosuspend(dev->dev);
2010 return ret;
2011 }
2012
2013 static struct nv50_outp_atom *
2014 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2015 {
2016 struct nv50_outp_atom *outp;
2017
2018 list_for_each_entry(outp, &atom->outp, head) {
2019 if (outp->encoder == encoder)
2020 return outp;
2021 }
2022
2023 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2024 if (!outp)
2025 return ERR_PTR(-ENOMEM);
2026
2027 list_add(&outp->head, &atom->outp);
2028 outp->encoder = encoder;
2029 return outp;
2030 }
2031
2032 static int
2033 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2034 struct drm_connector_state *old_connector_state)
2035 {
2036 struct drm_encoder *encoder = old_connector_state->best_encoder;
2037 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2038 struct drm_crtc *crtc;
2039 struct nv50_outp_atom *outp;
2040
2041 if (!(crtc = old_connector_state->crtc))
2042 return 0;
2043
2044 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2045 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2046 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2047 outp = nv50_disp_outp_atomic_add(atom, encoder);
2048 if (IS_ERR(outp))
2049 return PTR_ERR(outp);
2050
2051 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2052 outp->flush_disable = true;
2053 atom->flush_disable = true;
2054 }
2055 outp->clr.ctrl = true;
2056 atom->lock_core = true;
2057 }
2058
2059 return 0;
2060 }
2061
2062 static int
2063 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2064 struct drm_connector_state *connector_state)
2065 {
2066 struct drm_encoder *encoder = connector_state->best_encoder;
2067 struct drm_crtc_state *new_crtc_state;
2068 struct drm_crtc *crtc;
2069 struct nv50_outp_atom *outp;
2070
2071 if (!(crtc = connector_state->crtc))
2072 return 0;
2073
2074 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2075 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2076 outp = nv50_disp_outp_atomic_add(atom, encoder);
2077 if (IS_ERR(outp))
2078 return PTR_ERR(outp);
2079
2080 outp->set.ctrl = true;
2081 atom->lock_core = true;
2082 }
2083
2084 return 0;
2085 }
2086
2087 static int
2088 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2089 {
2090 struct nv50_atom *atom = nv50_atom(state);
2091 struct drm_connector_state *old_connector_state, *new_connector_state;
2092 struct drm_connector *connector;
2093 struct drm_crtc_state *new_crtc_state;
2094 struct drm_crtc *crtc;
2095 int ret, i;
2096
2097 /* We need to handle colour management on a per-plane basis. */
2098 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2099 if (new_crtc_state->color_mgmt_changed) {
2100 ret = drm_atomic_add_affected_planes(state, crtc);
2101 if (ret)
2102 return ret;
2103 }
2104 }
2105
2106 ret = drm_atomic_helper_check(dev, state);
2107 if (ret)
2108 return ret;
2109
2110 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2111 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2112 if (ret)
2113 return ret;
2114
2115 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2116 if (ret)
2117 return ret;
2118 }
2119
2120 return 0;
2121 }
2122
2123 static void
2124 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2125 {
2126 struct nv50_atom *atom = nv50_atom(state);
2127 struct nv50_outp_atom *outp, *outt;
2128
2129 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2130 list_del(&outp->head);
2131 kfree(outp);
2132 }
2133
2134 drm_atomic_state_default_clear(state);
2135 }
2136
2137 static void
2138 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2139 {
2140 struct nv50_atom *atom = nv50_atom(state);
2141 drm_atomic_state_default_release(&atom->state);
2142 kfree(atom);
2143 }
2144
2145 static struct drm_atomic_state *
2146 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2147 {
2148 struct nv50_atom *atom;
2149 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2150 drm_atomic_state_init(dev, &atom->state) < 0) {
2151 kfree(atom);
2152 return NULL;
2153 }
2154 INIT_LIST_HEAD(&atom->outp);
2155 return &atom->state;
2156 }
2157
2158 static const struct drm_mode_config_funcs
2159 nv50_disp_func = {
2160 .fb_create = nouveau_user_framebuffer_create,
2161 .output_poll_changed = nouveau_fbcon_output_poll_changed,
2162 .atomic_check = nv50_disp_atomic_check,
2163 .atomic_commit = nv50_disp_atomic_commit,
2164 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2165 .atomic_state_clear = nv50_disp_atomic_state_clear,
2166 .atomic_state_free = nv50_disp_atomic_state_free,
2167 };
2168
2169 /******************************************************************************
2170 * Init
2171 *****************************************************************************/
2172
2173 void
2174 nv50_display_fini(struct drm_device *dev)
2175 {
2176 struct nouveau_encoder *nv_encoder;
2177 struct drm_encoder *encoder;
2178 struct drm_plane *plane;
2179
2180 drm_for_each_plane(plane, dev) {
2181 struct nv50_wndw *wndw = nv50_wndw(plane);
2182 if (plane->funcs != &nv50_wndw)
2183 continue;
2184 nv50_wndw_fini(wndw);
2185 }
2186
2187 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2188 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2189 nv_encoder = nouveau_encoder(encoder);
2190 nv50_mstm_fini(nv_encoder->dp.mstm);
2191 }
2192 }
2193 }
2194
2195 int
2196 nv50_display_init(struct drm_device *dev)
2197 {
2198 struct nv50_core *core = nv50_disp(dev)->core;
2199 struct drm_encoder *encoder;
2200 struct drm_plane *plane;
2201
2202 core->func->init(core);
2203
2204 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2205 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2206 struct nouveau_encoder *nv_encoder =
2207 nouveau_encoder(encoder);
2208 nv50_mstm_init(nv_encoder->dp.mstm);
2209 }
2210 }
2211
2212 drm_for_each_plane(plane, dev) {
2213 struct nv50_wndw *wndw = nv50_wndw(plane);
2214 if (plane->funcs != &nv50_wndw)
2215 continue;
2216 nv50_wndw_init(wndw);
2217 }
2218
2219 return 0;
2220 }
2221
2222 void
2223 nv50_display_destroy(struct drm_device *dev)
2224 {
2225 struct nv50_disp *disp = nv50_disp(dev);
2226
2227 nv50_core_del(&disp->core);
2228
2229 nouveau_bo_unmap(disp->sync);
2230 if (disp->sync)
2231 nouveau_bo_unpin(disp->sync);
2232 nouveau_bo_ref(NULL, &disp->sync);
2233
2234 nouveau_display(dev)->priv = NULL;
2235 kfree(disp);
2236 }
2237
2238 int
2239 nv50_display_create(struct drm_device *dev)
2240 {
2241 struct nvif_device *device = &nouveau_drm(dev)->client.device;
2242 struct nouveau_drm *drm = nouveau_drm(dev);
2243 struct dcb_table *dcb = &drm->vbios.dcb;
2244 struct drm_connector *connector, *tmp;
2245 struct nv50_disp *disp;
2246 struct dcb_output *dcbe;
2247 int crtcs, ret, i;
2248
2249 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2250 if (!disp)
2251 return -ENOMEM;
2252
2253 mutex_init(&disp->mutex);
2254
2255 nouveau_display(dev)->priv = disp;
2256 nouveau_display(dev)->dtor = nv50_display_destroy;
2257 nouveau_display(dev)->init = nv50_display_init;
2258 nouveau_display(dev)->fini = nv50_display_fini;
2259 disp->disp = &nouveau_display(dev)->disp;
2260 dev->mode_config.funcs = &nv50_disp_func;
2261 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2262
2263 /* small shared memory area we use for notifiers and semaphores */
2264 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2265 0, 0x0000, NULL, NULL, &disp->sync);
2266 if (!ret) {
2267 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2268 if (!ret) {
2269 ret = nouveau_bo_map(disp->sync);
2270 if (ret)
2271 nouveau_bo_unpin(disp->sync);
2272 }
2273 if (ret)
2274 nouveau_bo_ref(NULL, &disp->sync);
2275 }
2276
2277 if (ret)
2278 goto out;
2279
2280 /* allocate master evo channel */
2281 ret = nv50_core_new(drm, &disp->core);
2282 if (ret)
2283 goto out;
2284
2285 /* create crtc objects to represent the hw heads */
2286 if (disp->disp->object.oclass >= GV100_DISP)
2287 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2288 else
2289 if (disp->disp->object.oclass >= GF110_DISP)
2290 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2291 else
2292 crtcs = 0x3;
2293
2294 for (i = 0; i < fls(crtcs); i++) {
2295 if (!(crtcs & (1 << i)))
2296 continue;
2297 ret = nv50_head_create(dev, i);
2298 if (ret)
2299 goto out;
2300 }
2301
2302 /* create encoder/connector objects based on VBIOS DCB table */
2303 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2304 connector = nouveau_connector_create(dev, dcbe->connector);
2305 if (IS_ERR(connector))
2306 continue;
2307
2308 if (dcbe->location == DCB_LOC_ON_CHIP) {
2309 switch (dcbe->type) {
2310 case DCB_OUTPUT_TMDS:
2311 case DCB_OUTPUT_LVDS:
2312 case DCB_OUTPUT_DP:
2313 ret = nv50_sor_create(connector, dcbe);
2314 break;
2315 case DCB_OUTPUT_ANALOG:
2316 ret = nv50_dac_create(connector, dcbe);
2317 break;
2318 default:
2319 ret = -ENODEV;
2320 break;
2321 }
2322 } else {
2323 ret = nv50_pior_create(connector, dcbe);
2324 }
2325
2326 if (ret) {
2327 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2328 dcbe->location, dcbe->type,
2329 ffs(dcbe->or) - 1, ret);
2330 ret = 0;
2331 }
2332 }
2333
2334 /* cull any connectors we created that don't have an encoder */
2335 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2336 if (connector->encoder_ids[0])
2337 continue;
2338
2339 NV_WARN(drm, "%s has no encoders, removing\n",
2340 connector->name);
2341 connector->funcs->destroy(connector);
2342 }
2343
2344 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2345 dev->vblank_disable_immediate = true;
2346
2347 out:
2348 if (ret)
2349 nv50_display_destroy(dev);
2350 return ret;
2351 }
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