1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 Free Electrons
4 * Copyright (C) 2015 NextThing Co
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <drm/drm_atomic_helper.h>
11 #include <drm/drm_connector.h>
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_encoder.h>
14 #include <drm/drm_modes.h>
15 #include <drm/drm_of.h>
16 #include <drm/drm_panel.h>
17 #include <drm/drm_probe_helper.h>
19 #include <uapi/drm/drm_mode.h>
21 #include <linux/component.h>
22 #include <linux/ioport.h>
23 #include <linux/of_address.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
29 #include "sun4i_crtc.h"
30 #include "sun4i_dotclock.h"
31 #include "sun4i_drv.h"
32 #include "sun4i_lvds.h"
33 #include "sun4i_rgb.h"
34 #include "sun4i_tcon.h"
35 #include "sun6i_mipi_dsi.h"
36 #include "sun8i_tcon_top.h"
37 #include "sunxi_engine.h"
39 static struct drm_connector
*sun4i_tcon_get_connector(const struct drm_encoder
*encoder
)
41 struct drm_connector
*connector
;
42 struct drm_connector_list_iter iter
;
44 drm_connector_list_iter_begin(encoder
->dev
, &iter
);
45 drm_for_each_connector_iter(connector
, &iter
)
46 if (connector
->encoder
== encoder
) {
47 drm_connector_list_iter_end(&iter
);
50 drm_connector_list_iter_end(&iter
);
55 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder
*encoder
)
57 struct drm_connector
*connector
;
58 struct drm_display_info
*info
;
60 connector
= sun4i_tcon_get_connector(encoder
);
64 info
= &connector
->display_info
;
65 if (info
->num_bus_formats
!= 1)
68 switch (info
->bus_formats
[0]) {
69 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
:
72 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA
:
73 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
:
80 static void sun4i_tcon_channel_set_status(struct sun4i_tcon
*tcon
, int channel
,
87 WARN_ON(!tcon
->quirks
->has_channel_0
);
88 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_CTL_REG
,
89 SUN4I_TCON0_CTL_TCON_ENABLE
,
90 enabled
? SUN4I_TCON0_CTL_TCON_ENABLE
: 0);
94 WARN_ON(!tcon
->quirks
->has_channel_1
);
95 regmap_update_bits(tcon
->regs
, SUN4I_TCON1_CTL_REG
,
96 SUN4I_TCON1_CTL_TCON_ENABLE
,
97 enabled
? SUN4I_TCON1_CTL_TCON_ENABLE
: 0);
101 DRM_WARN("Unknown channel... doing nothing\n");
106 clk_prepare_enable(clk
);
107 clk_rate_exclusive_get(clk
);
109 clk_rate_exclusive_put(clk
);
110 clk_disable_unprepare(clk
);
114 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon
*tcon
,
115 const struct drm_encoder
*encoder
,
121 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_LVDS_IF_REG
,
122 SUN4I_TCON0_LVDS_IF_EN
,
123 SUN4I_TCON0_LVDS_IF_EN
);
126 * As their name suggest, these values only apply to the A31
127 * and later SoCs. We'll have to rework this when merging
128 * support for the older SoCs.
130 regmap_write(tcon
->regs
, SUN4I_TCON0_LVDS_ANA0_REG
,
131 SUN6I_TCON0_LVDS_ANA0_C(2) |
132 SUN6I_TCON0_LVDS_ANA0_V(3) |
133 SUN6I_TCON0_LVDS_ANA0_PD(2) |
134 SUN6I_TCON0_LVDS_ANA0_EN_LDO
);
137 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_LVDS_ANA0_REG
,
138 SUN6I_TCON0_LVDS_ANA0_EN_MB
,
139 SUN6I_TCON0_LVDS_ANA0_EN_MB
);
142 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_LVDS_ANA0_REG
,
143 SUN6I_TCON0_LVDS_ANA0_EN_DRVC
,
144 SUN6I_TCON0_LVDS_ANA0_EN_DRVC
);
146 if (sun4i_tcon_get_pixel_depth(encoder
) == 18)
151 regmap_write_bits(tcon
->regs
, SUN4I_TCON0_LVDS_ANA0_REG
,
152 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
153 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val
));
155 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_LVDS_IF_REG
,
156 SUN4I_TCON0_LVDS_IF_EN
, 0);
160 void sun4i_tcon_set_status(struct sun4i_tcon
*tcon
,
161 const struct drm_encoder
*encoder
,
164 bool is_lvds
= false;
167 switch (encoder
->encoder_type
) {
168 case DRM_MODE_ENCODER_LVDS
:
171 case DRM_MODE_ENCODER_DSI
:
172 case DRM_MODE_ENCODER_NONE
:
175 case DRM_MODE_ENCODER_TMDS
:
176 case DRM_MODE_ENCODER_TVDAC
:
180 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
184 if (is_lvds
&& !enabled
)
185 sun4i_tcon_lvds_set_status(tcon
, encoder
, false);
187 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GCTL_REG
,
188 SUN4I_TCON_GCTL_TCON_ENABLE
,
189 enabled
? SUN4I_TCON_GCTL_TCON_ENABLE
: 0);
191 if (is_lvds
&& enabled
)
192 sun4i_tcon_lvds_set_status(tcon
, encoder
, true);
194 sun4i_tcon_channel_set_status(tcon
, channel
, enabled
);
197 void sun4i_tcon_enable_vblank(struct sun4i_tcon
*tcon
, bool enable
)
201 DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable
? "En" : "Dis");
203 mask
= SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
204 SUN4I_TCON_GINT0_VBLANK_ENABLE(1) |
205 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE
;
210 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GINT0_REG
, mask
, val
);
212 EXPORT_SYMBOL(sun4i_tcon_enable_vblank
);
215 * This function is a helper for TCON output muxing. The TCON output
216 * muxing control register in earlier SoCs (without the TCON TOP block)
217 * are located in TCON0. This helper returns a pointer to TCON0's
218 * sun4i_tcon structure, or NULL if not found.
220 static struct sun4i_tcon
*sun4i_get_tcon0(struct drm_device
*drm
)
222 struct sun4i_drv
*drv
= drm
->dev_private
;
223 struct sun4i_tcon
*tcon
;
225 list_for_each_entry(tcon
, &drv
->tcon_list
, list
)
230 "TCON0 not found, display output muxing may not work\n");
235 static void sun4i_tcon_set_mux(struct sun4i_tcon
*tcon
, int channel
,
236 const struct drm_encoder
*encoder
)
240 if (tcon
->quirks
->set_mux
)
241 ret
= tcon
->quirks
->set_mux(tcon
, encoder
);
243 DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
244 encoder
->name
, encoder
->crtc
->name
, ret
);
247 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode
*mode
,
250 int delay
= mode
->vtotal
- mode
->vdisplay
;
252 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
258 delay
= min(delay
, 30);
260 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel
, delay
);
265 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon
*tcon
,
266 const struct drm_display_mode
*mode
)
268 /* Configure the dot clock */
269 clk_set_rate(tcon
->dclk
, mode
->crtc_clock
* 1000);
271 /* Set the resolution */
272 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC0_REG
,
273 SUN4I_TCON0_BASIC0_X(mode
->crtc_hdisplay
) |
274 SUN4I_TCON0_BASIC0_Y(mode
->crtc_vdisplay
));
277 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon
*tcon
,
278 const struct drm_connector
*connector
)
283 /* XXX Would this ever happen? */
288 * FIXME: Undocumented bits
290 * The whole dithering process and these parameters are not
291 * explained in the vendor documents or BSP kernel code.
293 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_SEED_PR_REG
, 0x11111111);
294 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_SEED_PG_REG
, 0x11111111);
295 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_SEED_PB_REG
, 0x11111111);
296 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_SEED_LR_REG
, 0x11111111);
297 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_SEED_LG_REG
, 0x11111111);
298 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_SEED_LB_REG
, 0x11111111);
299 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_TBL0_REG
, 0x01010000);
300 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_TBL1_REG
, 0x15151111);
301 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_TBL2_REG
, 0x57575555);
302 regmap_write(tcon
->regs
, SUN4I_TCON0_FRM_TBL3_REG
, 0x7f7f7777);
304 /* Do dithering if panel only supports 6 bits per color */
305 if (connector
->display_info
.bpc
== 6)
306 val
|= SUN4I_TCON0_FRM_CTL_EN
;
308 if (connector
->display_info
.num_bus_formats
== 1)
309 bus_format
= connector
->display_info
.bus_formats
[0];
311 /* Check the connection format */
312 switch (bus_format
) {
313 case MEDIA_BUS_FMT_RGB565_1X16
:
314 /* R and B components are only 5 bits deep */
315 val
|= SUN4I_TCON0_FRM_CTL_MODE_R
;
316 val
|= SUN4I_TCON0_FRM_CTL_MODE_B
;
317 case MEDIA_BUS_FMT_RGB666_1X18
:
318 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
:
319 /* Fall through: enable dithering */
320 val
|= SUN4I_TCON0_FRM_CTL_EN
;
324 /* Write dithering settings */
325 regmap_write(tcon
->regs
, SUN4I_TCON_FRM_CTL_REG
, val
);
328 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon
*tcon
,
329 const struct drm_encoder
*encoder
,
330 const struct drm_display_mode
*mode
)
332 /* TODO support normal CPU interface modes */
333 struct sun6i_dsi
*dsi
= encoder_to_sun6i_dsi(encoder
);
334 struct mipi_dsi_device
*device
= dsi
->device
;
335 u8 bpp
= mipi_dsi_pixel_format_to_bpp(device
->format
);
336 u8 lanes
= device
->lanes
;
337 u32 block_space
, start_delay
;
340 tcon
->dclk_min_div
= SUN6I_DSI_TCON_DIV
;
341 tcon
->dclk_max_div
= SUN6I_DSI_TCON_DIV
;
343 sun4i_tcon0_mode_set_common(tcon
, mode
);
345 /* Set dithering if needed */
346 sun4i_tcon0_mode_set_dithering(tcon
, sun4i_tcon_get_connector(encoder
));
348 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_CTL_REG
,
349 SUN4I_TCON0_CTL_IF_MASK
,
350 SUN4I_TCON0_CTL_IF_8080
);
352 regmap_write(tcon
->regs
, SUN4I_TCON_ECC_FIFO_REG
,
353 SUN4I_TCON_ECC_FIFO_EN
);
355 regmap_write(tcon
->regs
, SUN4I_TCON0_CPU_IF_REG
,
356 SUN4I_TCON0_CPU_IF_MODE_DSI
|
357 SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH
|
358 SUN4I_TCON0_CPU_IF_TRI_FIFO_EN
|
359 SUN4I_TCON0_CPU_IF_TRI_EN
);
362 * This looks suspicious, but it works...
364 * The datasheet says that this should be set higher than 20 *
365 * pixel cycle, but it's not clear what a pixel cycle is.
367 regmap_read(tcon
->regs
, SUN4I_TCON0_DCLK_REG
, &tcon_div
);
368 tcon_div
&= GENMASK(6, 0);
369 block_space
= mode
->htotal
* bpp
/ (tcon_div
* lanes
);
370 block_space
-= mode
->hdisplay
+ 40;
372 regmap_write(tcon
->regs
, SUN4I_TCON0_CPU_TRI0_REG
,
373 SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space
) |
374 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode
->hdisplay
));
376 regmap_write(tcon
->regs
, SUN4I_TCON0_CPU_TRI1_REG
,
377 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode
->vdisplay
));
379 start_delay
= (mode
->crtc_vtotal
- mode
->crtc_vdisplay
- 10 - 1);
380 start_delay
= start_delay
* mode
->crtc_htotal
* 149;
381 start_delay
= start_delay
/ (mode
->crtc_clock
/ 1000) / 8;
382 regmap_write(tcon
->regs
, SUN4I_TCON0_CPU_TRI2_REG
,
383 SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) |
384 SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay
));
387 * The Allwinner BSP has a comment that the period should be
388 * the display clock * 15, but uses an hardcoded 3000...
390 regmap_write(tcon
->regs
, SUN4I_TCON_SAFE_PERIOD_REG
,
391 SUN4I_TCON_SAFE_PERIOD_NUM(3000) |
392 SUN4I_TCON_SAFE_PERIOD_MODE(3));
394 /* Enable the output on the pins */
395 regmap_write(tcon
->regs
, SUN4I_TCON0_IO_TRI_REG
,
399 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon
*tcon
,
400 const struct drm_encoder
*encoder
,
401 const struct drm_display_mode
*mode
)
407 WARN_ON(!tcon
->quirks
->has_channel_0
);
409 tcon
->dclk_min_div
= 7;
410 tcon
->dclk_max_div
= 7;
411 sun4i_tcon0_mode_set_common(tcon
, mode
);
413 /* Set dithering if needed */
414 sun4i_tcon0_mode_set_dithering(tcon
, sun4i_tcon_get_connector(encoder
));
416 /* Adjust clock delay */
417 clk_delay
= sun4i_tcon_get_clk_delay(mode
, 0);
418 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_CTL_REG
,
419 SUN4I_TCON0_CTL_CLK_DELAY_MASK
,
420 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay
));
423 * This is called a backporch in the register documentation,
424 * but it really is the back porch + hsync
426 bp
= mode
->crtc_htotal
- mode
->crtc_hsync_start
;
427 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
428 mode
->crtc_htotal
, bp
);
430 /* Set horizontal display timings */
431 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC1_REG
,
432 SUN4I_TCON0_BASIC1_H_TOTAL(mode
->htotal
) |
433 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp
));
436 * This is called a backporch in the register documentation,
437 * but it really is the back porch + hsync
439 bp
= mode
->crtc_vtotal
- mode
->crtc_vsync_start
;
440 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
441 mode
->crtc_vtotal
, bp
);
443 /* Set vertical display timings */
444 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC2_REG
,
445 SUN4I_TCON0_BASIC2_V_TOTAL(mode
->crtc_vtotal
* 2) |
446 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp
));
448 reg
= SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0
|
449 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL
|
450 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL
;
451 if (sun4i_tcon_get_pixel_depth(encoder
) == 24)
452 reg
|= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS
;
454 reg
|= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS
;
456 regmap_write(tcon
->regs
, SUN4I_TCON0_LVDS_IF_REG
, reg
);
458 /* Setup the polarity of the various signals */
459 if (!(mode
->flags
& DRM_MODE_FLAG_PHSYNC
))
460 val
|= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE
;
462 if (!(mode
->flags
& DRM_MODE_FLAG_PVSYNC
))
463 val
|= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE
;
465 regmap_write(tcon
->regs
, SUN4I_TCON0_IO_POL_REG
, val
);
467 /* Map output pins to channel 0 */
468 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GCTL_REG
,
469 SUN4I_TCON_GCTL_IOMAP_MASK
,
470 SUN4I_TCON_GCTL_IOMAP_TCON0
);
472 /* Enable the output on the pins */
473 regmap_write(tcon
->regs
, SUN4I_TCON0_IO_TRI_REG
, 0xe0000000);
476 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon
*tcon
,
477 const struct drm_encoder
*encoder
,
478 const struct drm_display_mode
*mode
)
480 struct drm_connector
*connector
= sun4i_tcon_get_connector(encoder
);
481 struct drm_display_info display_info
= connector
->display_info
;
482 unsigned int bp
, hsync
, vsync
;
486 WARN_ON(!tcon
->quirks
->has_channel_0
);
488 tcon
->dclk_min_div
= 6;
489 tcon
->dclk_max_div
= 127;
490 sun4i_tcon0_mode_set_common(tcon
, mode
);
492 /* Set dithering if needed */
493 sun4i_tcon0_mode_set_dithering(tcon
, connector
);
495 /* Adjust clock delay */
496 clk_delay
= sun4i_tcon_get_clk_delay(mode
, 0);
497 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_CTL_REG
,
498 SUN4I_TCON0_CTL_CLK_DELAY_MASK
,
499 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay
));
502 * This is called a backporch in the register documentation,
503 * but it really is the back porch + hsync
505 bp
= mode
->crtc_htotal
- mode
->crtc_hsync_start
;
506 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
507 mode
->crtc_htotal
, bp
);
509 /* Set horizontal display timings */
510 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC1_REG
,
511 SUN4I_TCON0_BASIC1_H_TOTAL(mode
->crtc_htotal
) |
512 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp
));
515 * This is called a backporch in the register documentation,
516 * but it really is the back porch + hsync
518 bp
= mode
->crtc_vtotal
- mode
->crtc_vsync_start
;
519 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
520 mode
->crtc_vtotal
, bp
);
522 /* Set vertical display timings */
523 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC2_REG
,
524 SUN4I_TCON0_BASIC2_V_TOTAL(mode
->crtc_vtotal
* 2) |
525 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp
));
527 /* Set Hsync and Vsync length */
528 hsync
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
529 vsync
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
530 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync
, vsync
);
531 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC3_REG
,
532 SUN4I_TCON0_BASIC3_V_SYNC(vsync
) |
533 SUN4I_TCON0_BASIC3_H_SYNC(hsync
));
535 /* Setup the polarity of the various signals */
536 if (mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
537 val
|= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE
;
539 if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
540 val
|= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE
;
542 if (display_info
.bus_flags
& DRM_BUS_FLAG_DE_LOW
)
543 val
|= SUN4I_TCON0_IO_POL_DE_NEGATIVE
;
546 * On A20 and similar SoCs, the only way to achieve Positive Edge
547 * (Rising Edge), is setting dclk clock phase to 2/3(240°).
548 * By default TCON works in Negative Edge(Falling Edge),
549 * this is why phase is set to 0 in that case.
550 * Unfortunately there's no way to logically invert dclk through
552 * The only acceptable way to work, triple checked with scope,
553 * is using clock phase set to 0° for Negative Edge and set to 240°
555 * On A33 and similar SoCs there would be a 90° phase option,
556 * but it divides also dclk by 2.
557 * Following code is a way to avoid quirks all around TCON
558 * and DOTCLOCK drivers.
560 if (display_info
.bus_flags
& DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
)
561 clk_set_phase(tcon
->dclk
, 240);
563 if (display_info
.bus_flags
& DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE
)
564 clk_set_phase(tcon
->dclk
, 0);
566 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_IO_POL_REG
,
567 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE
|
568 SUN4I_TCON0_IO_POL_VSYNC_POSITIVE
|
569 SUN4I_TCON0_IO_POL_DE_NEGATIVE
,
572 /* Map output pins to channel 0 */
573 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GCTL_REG
,
574 SUN4I_TCON_GCTL_IOMAP_MASK
,
575 SUN4I_TCON_GCTL_IOMAP_TCON0
);
577 /* Enable the output on the pins */
578 regmap_write(tcon
->regs
, SUN4I_TCON0_IO_TRI_REG
, 0);
581 static void sun4i_tcon1_mode_set(struct sun4i_tcon
*tcon
,
582 const struct drm_display_mode
*mode
)
584 unsigned int bp
, hsync
, vsync
, vtotal
;
588 WARN_ON(!tcon
->quirks
->has_channel_1
);
590 /* Configure the dot clock */
591 clk_set_rate(tcon
->sclk1
, mode
->crtc_clock
* 1000);
593 /* Adjust clock delay */
594 clk_delay
= sun4i_tcon_get_clk_delay(mode
, 1);
595 regmap_update_bits(tcon
->regs
, SUN4I_TCON1_CTL_REG
,
596 SUN4I_TCON1_CTL_CLK_DELAY_MASK
,
597 SUN4I_TCON1_CTL_CLK_DELAY(clk_delay
));
599 /* Set interlaced mode */
600 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
601 val
= SUN4I_TCON1_CTL_INTERLACE_ENABLE
;
604 regmap_update_bits(tcon
->regs
, SUN4I_TCON1_CTL_REG
,
605 SUN4I_TCON1_CTL_INTERLACE_ENABLE
,
608 /* Set the input resolution */
609 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC0_REG
,
610 SUN4I_TCON1_BASIC0_X(mode
->crtc_hdisplay
) |
611 SUN4I_TCON1_BASIC0_Y(mode
->crtc_vdisplay
));
613 /* Set the upscaling resolution */
614 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC1_REG
,
615 SUN4I_TCON1_BASIC1_X(mode
->crtc_hdisplay
) |
616 SUN4I_TCON1_BASIC1_Y(mode
->crtc_vdisplay
));
618 /* Set the output resolution */
619 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC2_REG
,
620 SUN4I_TCON1_BASIC2_X(mode
->crtc_hdisplay
) |
621 SUN4I_TCON1_BASIC2_Y(mode
->crtc_vdisplay
));
623 /* Set horizontal display timings */
624 bp
= mode
->crtc_htotal
- mode
->crtc_hsync_start
;
625 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
627 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC3_REG
,
628 SUN4I_TCON1_BASIC3_H_TOTAL(mode
->crtc_htotal
) |
629 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp
));
631 bp
= mode
->crtc_vtotal
- mode
->crtc_vsync_start
;
632 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
633 mode
->crtc_vtotal
, bp
);
636 * The vertical resolution needs to be doubled in all
637 * cases. We could use crtc_vtotal and always multiply by two,
638 * but that leads to a rounding error in interlace when vtotal
641 * This happens with TV's PAL for example, where vtotal will
642 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
643 * 624, which apparently confuses the hardware.
645 * To work around this, we will always use vtotal, and
646 * multiply by two only if we're not in interlace.
648 vtotal
= mode
->vtotal
;
649 if (!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
))
652 /* Set vertical display timings */
653 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC4_REG
,
654 SUN4I_TCON1_BASIC4_V_TOTAL(vtotal
) |
655 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp
));
657 /* Set Hsync and Vsync length */
658 hsync
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
659 vsync
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
660 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync
, vsync
);
661 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC5_REG
,
662 SUN4I_TCON1_BASIC5_V_SYNC(vsync
) |
663 SUN4I_TCON1_BASIC5_H_SYNC(hsync
));
665 /* Map output pins to channel 1 */
666 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GCTL_REG
,
667 SUN4I_TCON_GCTL_IOMAP_MASK
,
668 SUN4I_TCON_GCTL_IOMAP_TCON1
);
671 void sun4i_tcon_mode_set(struct sun4i_tcon
*tcon
,
672 const struct drm_encoder
*encoder
,
673 const struct drm_display_mode
*mode
)
675 switch (encoder
->encoder_type
) {
676 case DRM_MODE_ENCODER_DSI
:
677 /* DSI is tied to special case of CPU interface */
678 sun4i_tcon0_mode_set_cpu(tcon
, encoder
, mode
);
680 case DRM_MODE_ENCODER_LVDS
:
681 sun4i_tcon0_mode_set_lvds(tcon
, encoder
, mode
);
683 case DRM_MODE_ENCODER_NONE
:
684 sun4i_tcon0_mode_set_rgb(tcon
, encoder
, mode
);
685 sun4i_tcon_set_mux(tcon
, 0, encoder
);
687 case DRM_MODE_ENCODER_TVDAC
:
688 case DRM_MODE_ENCODER_TMDS
:
689 sun4i_tcon1_mode_set(tcon
, mode
);
690 sun4i_tcon_set_mux(tcon
, 1, encoder
);
693 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
696 EXPORT_SYMBOL(sun4i_tcon_mode_set
);
698 static void sun4i_tcon_finish_page_flip(struct drm_device
*dev
,
699 struct sun4i_crtc
*scrtc
)
703 spin_lock_irqsave(&dev
->event_lock
, flags
);
705 drm_crtc_send_vblank_event(&scrtc
->crtc
, scrtc
->event
);
706 drm_crtc_vblank_put(&scrtc
->crtc
);
709 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
712 static irqreturn_t
sun4i_tcon_handler(int irq
, void *private)
714 struct sun4i_tcon
*tcon
= private;
715 struct drm_device
*drm
= tcon
->drm
;
716 struct sun4i_crtc
*scrtc
= tcon
->crtc
;
717 struct sunxi_engine
*engine
= scrtc
->engine
;
720 regmap_read(tcon
->regs
, SUN4I_TCON_GINT0_REG
, &status
);
722 if (!(status
& (SUN4I_TCON_GINT0_VBLANK_INT(0) |
723 SUN4I_TCON_GINT0_VBLANK_INT(1) |
724 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT
)))
727 drm_crtc_handle_vblank(&scrtc
->crtc
);
728 sun4i_tcon_finish_page_flip(drm
, scrtc
);
730 /* Acknowledge the interrupt */
731 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GINT0_REG
,
732 SUN4I_TCON_GINT0_VBLANK_INT(0) |
733 SUN4I_TCON_GINT0_VBLANK_INT(1) |
734 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT
,
737 if (engine
->ops
->vblank_quirk
)
738 engine
->ops
->vblank_quirk(engine
);
743 static int sun4i_tcon_init_clocks(struct device
*dev
,
744 struct sun4i_tcon
*tcon
)
746 tcon
->clk
= devm_clk_get(dev
, "ahb");
747 if (IS_ERR(tcon
->clk
)) {
748 dev_err(dev
, "Couldn't get the TCON bus clock\n");
749 return PTR_ERR(tcon
->clk
);
751 clk_prepare_enable(tcon
->clk
);
753 if (tcon
->quirks
->has_channel_0
) {
754 tcon
->sclk0
= devm_clk_get(dev
, "tcon-ch0");
755 if (IS_ERR(tcon
->sclk0
)) {
756 dev_err(dev
, "Couldn't get the TCON channel 0 clock\n");
757 return PTR_ERR(tcon
->sclk0
);
760 clk_prepare_enable(tcon
->sclk0
);
762 if (tcon
->quirks
->has_channel_1
) {
763 tcon
->sclk1
= devm_clk_get(dev
, "tcon-ch1");
764 if (IS_ERR(tcon
->sclk1
)) {
765 dev_err(dev
, "Couldn't get the TCON channel 1 clock\n");
766 return PTR_ERR(tcon
->sclk1
);
773 static void sun4i_tcon_free_clocks(struct sun4i_tcon
*tcon
)
775 clk_disable_unprepare(tcon
->sclk0
);
776 clk_disable_unprepare(tcon
->clk
);
779 static int sun4i_tcon_init_irq(struct device
*dev
,
780 struct sun4i_tcon
*tcon
)
782 struct platform_device
*pdev
= to_platform_device(dev
);
785 irq
= platform_get_irq(pdev
, 0);
787 dev_err(dev
, "Couldn't retrieve the TCON interrupt\n");
791 ret
= devm_request_irq(dev
, irq
, sun4i_tcon_handler
, 0,
792 dev_name(dev
), tcon
);
794 dev_err(dev
, "Couldn't request the IRQ\n");
801 static struct regmap_config sun4i_tcon_regmap_config
= {
805 .max_register
= 0x800,
808 static int sun4i_tcon_init_regmap(struct device
*dev
,
809 struct sun4i_tcon
*tcon
)
811 struct platform_device
*pdev
= to_platform_device(dev
);
812 struct resource
*res
;
815 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
816 regs
= devm_ioremap_resource(dev
, res
);
818 return PTR_ERR(regs
);
820 tcon
->regs
= devm_regmap_init_mmio(dev
, regs
,
821 &sun4i_tcon_regmap_config
);
822 if (IS_ERR(tcon
->regs
)) {
823 dev_err(dev
, "Couldn't create the TCON regmap\n");
824 return PTR_ERR(tcon
->regs
);
827 /* Make sure the TCON is disabled and all IRQs are off */
828 regmap_write(tcon
->regs
, SUN4I_TCON_GCTL_REG
, 0);
829 regmap_write(tcon
->regs
, SUN4I_TCON_GINT0_REG
, 0);
830 regmap_write(tcon
->regs
, SUN4I_TCON_GINT1_REG
, 0);
832 /* Disable IO lines and set them to tristate */
833 regmap_write(tcon
->regs
, SUN4I_TCON0_IO_TRI_REG
, ~0);
834 regmap_write(tcon
->regs
, SUN4I_TCON1_IO_TRI_REG
, ~0);
840 * On SoCs with the old display pipeline design (Display Engine 1.0),
841 * the TCON is always tied to just one backend. Hence we can traverse
842 * the of_graph upwards to find the backend our tcon is connected to,
843 * and take its ID as our own.
845 * We can either identify backends from their compatible strings, which
846 * means maintaining a large list of them. Or, since the backend is
847 * registered and binded before the TCON, we can just go through the
848 * list of registered backends and compare the device node.
850 * As the structures now store engines instead of backends, here this
851 * function in fact searches the corresponding engine, and the ID is
852 * requested via the get_id function of the engine.
854 static struct sunxi_engine
*
855 sun4i_tcon_find_engine_traverse(struct sun4i_drv
*drv
,
856 struct device_node
*node
,
859 struct device_node
*port
, *ep
, *remote
;
860 struct sunxi_engine
*engine
= ERR_PTR(-EINVAL
);
863 port
= of_graph_get_port_by_id(node
, port_id
);
865 return ERR_PTR(-EINVAL
);
868 * This only works if there is only one path from the TCON
869 * to any display engine. Otherwise the probe order of the
870 * TCONs and display engines is not guaranteed. They may
871 * either bind to the wrong one, or worse, bind to the same
872 * one if additional checks are not done.
874 * Bail out if there are multiple input connections.
876 if (of_get_available_child_count(port
) != 1)
879 /* Get the first connection without specifying an ID */
880 ep
= of_get_next_available_child(port
, NULL
);
884 remote
= of_graph_get_remote_port_parent(ep
);
888 /* does this node match any registered engines? */
889 list_for_each_entry(engine
, &drv
->engine_list
, list
)
890 if (remote
== engine
->node
)
894 * According to device tree binding input ports have even id
895 * number and output ports have odd id. Since component with
896 * more than one input and one output (TCON TOP) exits, correct
897 * remote input id has to be calculated by subtracting 1 from
898 * remote output id. If this for some reason can't be done, 0
899 * is used as input port id.
902 port
= of_graph_get_remote_port(ep
);
903 if (!of_property_read_u32(port
, "reg", ®
) && reg
> 0)
906 /* keep looking through upstream ports */
907 engine
= sun4i_tcon_find_engine_traverse(drv
, remote
, reg
);
920 * The device tree binding says that the remote endpoint ID of any
921 * connection between components, up to and including the TCON, of
922 * the display pipeline should be equal to the actual ID of the local
923 * component. Thus we can look at any one of the input connections of
924 * the TCONs, and use that connection's remote endpoint ID as our own.
926 * Since the user of this function already finds the input port,
927 * the port is passed in directly without further checks.
929 static int sun4i_tcon_of_get_id_from_port(struct device_node
*port
)
931 struct device_node
*ep
;
934 /* try finding an upstream endpoint */
935 for_each_available_child_of_node(port
, ep
) {
936 struct device_node
*remote
;
939 remote
= of_graph_get_remote_endpoint(ep
);
943 ret
= of_property_read_u32(remote
, "reg", ®
);
954 * Once we know the TCON's id, we can look through the list of
955 * engines to find a matching one. We assume all engines have
956 * been probed and added to the list.
958 static struct sunxi_engine
*sun4i_tcon_get_engine_by_id(struct sun4i_drv
*drv
,
961 struct sunxi_engine
*engine
;
963 list_for_each_entry(engine
, &drv
->engine_list
, list
)
964 if (engine
->id
== id
)
967 return ERR_PTR(-EINVAL
);
970 static bool sun4i_tcon_connected_to_tcon_top(struct device_node
*node
)
972 struct device_node
*remote
;
975 remote
= of_graph_get_remote_node(node
, 0, -1);
977 ret
= !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP
) &&
978 of_match_node(sun8i_tcon_top_of_table
, remote
));
985 static int sun4i_tcon_get_index(struct sun4i_drv
*drv
)
987 struct list_head
*pos
;
991 * Because TCON is added to the list at the end of the probe
992 * (after this function is called), index of the current TCON
993 * will be same as current TCON list size.
995 list_for_each(pos
, &drv
->tcon_list
)
1002 * On SoCs with the old display pipeline design (Display Engine 1.0),
1003 * we assumed the TCON was always tied to just one backend. However
1004 * this proved not to be the case. On the A31, the TCON can select
1005 * either backend as its source. On the A20 (and likely on the A10),
1006 * the backend can choose which TCON to output to.
1008 * The device tree binding says that the remote endpoint ID of any
1009 * connection between components, up to and including the TCON, of
1010 * the display pipeline should be equal to the actual ID of the local
1011 * component. Thus we should be able to look at any one of the input
1012 * connections of the TCONs, and use that connection's remote endpoint
1015 * However the connections between the backend and TCON were assumed
1016 * to be always singular, and their endpoit IDs were all incorrectly
1017 * set to 0. This means for these old device trees, we cannot just look
1018 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
1019 * incorrectly identified as TCON0.
1021 * This function first checks if the TCON node has 2 input endpoints.
1022 * If so, then the device tree is a corrected version, and it will use
1023 * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
1024 * to fetch the ID and engine directly. If not, then it is likely an
1025 * old device trees, where the endpoint IDs were incorrect, but did not
1026 * have endpoint connections between the backend and TCON across
1027 * different display pipelines. It will fall back to the old method of
1028 * traversing the of_graph to try and find a matching engine by device
1031 * In the case of single display pipeline device trees, either method
1034 static struct sunxi_engine
*sun4i_tcon_find_engine(struct sun4i_drv
*drv
,
1035 struct device_node
*node
)
1037 struct device_node
*port
;
1038 struct sunxi_engine
*engine
;
1040 port
= of_graph_get_port_by_id(node
, 0);
1042 return ERR_PTR(-EINVAL
);
1045 * Is this a corrected device tree with cross pipeline
1046 * connections between the backend and TCON?
1048 if (of_get_child_count(port
) > 1) {
1052 * When pipeline has the same number of TCONs and engines which
1053 * are represented by frontends/backends (DE1) or mixers (DE2),
1054 * we match them by their respective IDs. However, if pipeline
1055 * contains TCON TOP, chances are that there are either more
1056 * TCONs than engines (R40) or TCONs with non-consecutive ids.
1057 * (H6). In that case it's easier just use TCON index in list
1058 * as an id. That means that on R40, any 2 TCONs can be enabled
1059 * in DT out of 4 (there are 2 mixers). Due to the design of
1060 * TCON TOP, remaining 2 TCONs can't be connected to anything
1063 if (sun4i_tcon_connected_to_tcon_top(node
))
1064 id
= sun4i_tcon_get_index(drv
);
1066 id
= sun4i_tcon_of_get_id_from_port(port
);
1068 /* Get our engine by matching our ID */
1069 engine
= sun4i_tcon_get_engine_by_id(drv
, id
);
1075 /* Fallback to old method by traversing input endpoints */
1077 return sun4i_tcon_find_engine_traverse(drv
, node
, 0);
1080 static int sun4i_tcon_bind(struct device
*dev
, struct device
*master
,
1083 struct drm_device
*drm
= data
;
1084 struct sun4i_drv
*drv
= drm
->dev_private
;
1085 struct sunxi_engine
*engine
;
1086 struct device_node
*remote
;
1087 struct sun4i_tcon
*tcon
;
1088 struct reset_control
*edp_rstc
;
1089 bool has_lvds_rst
, has_lvds_alt
, can_lvds
;
1092 engine
= sun4i_tcon_find_engine(drv
, dev
->of_node
);
1093 if (IS_ERR(engine
)) {
1094 dev_err(dev
, "Couldn't find matching engine\n");
1095 return -EPROBE_DEFER
;
1098 tcon
= devm_kzalloc(dev
, sizeof(*tcon
), GFP_KERNEL
);
1101 dev_set_drvdata(dev
, tcon
);
1104 tcon
->id
= engine
->id
;
1105 tcon
->quirks
= of_device_get_match_data(dev
);
1107 tcon
->lcd_rst
= devm_reset_control_get(dev
, "lcd");
1108 if (IS_ERR(tcon
->lcd_rst
)) {
1109 dev_err(dev
, "Couldn't get our reset line\n");
1110 return PTR_ERR(tcon
->lcd_rst
);
1113 if (tcon
->quirks
->needs_edp_reset
) {
1114 edp_rstc
= devm_reset_control_get_shared(dev
, "edp");
1115 if (IS_ERR(edp_rstc
)) {
1116 dev_err(dev
, "Couldn't get edp reset line\n");
1117 return PTR_ERR(edp_rstc
);
1120 ret
= reset_control_deassert(edp_rstc
);
1122 dev_err(dev
, "Couldn't deassert edp reset line\n");
1127 /* Make sure our TCON is reset */
1128 ret
= reset_control_reset(tcon
->lcd_rst
);
1130 dev_err(dev
, "Couldn't deassert our reset line\n");
1134 if (tcon
->quirks
->supports_lvds
) {
1136 * This can only be made optional since we've had DT
1137 * nodes without the LVDS reset properties.
1139 * If the property is missing, just disable LVDS, and
1142 tcon
->lvds_rst
= devm_reset_control_get_optional(dev
, "lvds");
1143 if (IS_ERR(tcon
->lvds_rst
)) {
1144 dev_err(dev
, "Couldn't get our reset line\n");
1145 return PTR_ERR(tcon
->lvds_rst
);
1146 } else if (tcon
->lvds_rst
) {
1147 has_lvds_rst
= true;
1148 reset_control_reset(tcon
->lvds_rst
);
1150 has_lvds_rst
= false;
1154 * This can only be made optional since we've had DT
1155 * nodes without the LVDS reset properties.
1157 * If the property is missing, just disable LVDS, and
1160 if (tcon
->quirks
->has_lvds_alt
) {
1161 tcon
->lvds_pll
= devm_clk_get(dev
, "lvds-alt");
1162 if (IS_ERR(tcon
->lvds_pll
)) {
1163 if (PTR_ERR(tcon
->lvds_pll
) == -ENOENT
) {
1164 has_lvds_alt
= false;
1166 dev_err(dev
, "Couldn't get the LVDS PLL\n");
1167 return PTR_ERR(tcon
->lvds_pll
);
1170 has_lvds_alt
= true;
1174 if (!has_lvds_rst
||
1175 (tcon
->quirks
->has_lvds_alt
&& !has_lvds_alt
)) {
1176 dev_warn(dev
, "Missing LVDS properties, Please upgrade your DT\n");
1177 dev_warn(dev
, "LVDS output disabled\n");
1186 ret
= sun4i_tcon_init_clocks(dev
, tcon
);
1188 dev_err(dev
, "Couldn't init our TCON clocks\n");
1189 goto err_assert_reset
;
1192 ret
= sun4i_tcon_init_regmap(dev
, tcon
);
1194 dev_err(dev
, "Couldn't init our TCON regmap\n");
1195 goto err_free_clocks
;
1198 if (tcon
->quirks
->has_channel_0
) {
1199 ret
= sun4i_dclk_create(dev
, tcon
);
1201 dev_err(dev
, "Couldn't create our TCON dot clock\n");
1202 goto err_free_clocks
;
1206 ret
= sun4i_tcon_init_irq(dev
, tcon
);
1208 dev_err(dev
, "Couldn't init our TCON interrupts\n");
1209 goto err_free_dotclock
;
1212 tcon
->crtc
= sun4i_crtc_init(drm
, engine
, tcon
);
1213 if (IS_ERR(tcon
->crtc
)) {
1214 dev_err(dev
, "Couldn't create our CRTC\n");
1215 ret
= PTR_ERR(tcon
->crtc
);
1216 goto err_free_dotclock
;
1219 if (tcon
->quirks
->has_channel_0
) {
1221 * If we have an LVDS panel connected to the TCON, we should
1222 * just probe the LVDS connector. Otherwise, just probe RGB as
1225 remote
= of_graph_get_remote_node(dev
->of_node
, 1, 0);
1226 if (of_device_is_compatible(remote
, "panel-lvds"))
1228 ret
= sun4i_lvds_init(drm
, tcon
);
1232 ret
= sun4i_rgb_init(drm
, tcon
);
1233 of_node_put(remote
);
1236 goto err_free_dotclock
;
1239 if (tcon
->quirks
->needs_de_be_mux
) {
1241 * We assume there is no dynamic muxing of backends
1242 * and TCONs, so we select the backend with same ID.
1244 * While dynamic selection might be interesting, since
1245 * the CRTC is tied to the TCON, while the layers are
1246 * tied to the backends, this means, we will need to
1247 * switch between groups of layers. There might not be
1248 * a way to represent this constraint in DRM.
1250 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_CTL_REG
,
1251 SUN4I_TCON0_CTL_SRC_SEL_MASK
,
1253 regmap_update_bits(tcon
->regs
, SUN4I_TCON1_CTL_REG
,
1254 SUN4I_TCON1_CTL_SRC_SEL_MASK
,
1258 list_add_tail(&tcon
->list
, &drv
->tcon_list
);
1263 if (tcon
->quirks
->has_channel_0
)
1264 sun4i_dclk_free(tcon
);
1266 sun4i_tcon_free_clocks(tcon
);
1268 reset_control_assert(tcon
->lcd_rst
);
1272 static void sun4i_tcon_unbind(struct device
*dev
, struct device
*master
,
1275 struct sun4i_tcon
*tcon
= dev_get_drvdata(dev
);
1277 list_del(&tcon
->list
);
1278 if (tcon
->quirks
->has_channel_0
)
1279 sun4i_dclk_free(tcon
);
1280 sun4i_tcon_free_clocks(tcon
);
1283 static const struct component_ops sun4i_tcon_ops
= {
1284 .bind
= sun4i_tcon_bind
,
1285 .unbind
= sun4i_tcon_unbind
,
1288 static int sun4i_tcon_probe(struct platform_device
*pdev
)
1290 struct device_node
*node
= pdev
->dev
.of_node
;
1291 const struct sun4i_tcon_quirks
*quirks
;
1292 struct drm_bridge
*bridge
;
1293 struct drm_panel
*panel
;
1296 quirks
= of_device_get_match_data(&pdev
->dev
);
1298 /* panels and bridges are present only on TCONs with channel 0 */
1299 if (quirks
->has_channel_0
) {
1300 ret
= drm_of_find_panel_or_bridge(node
, 1, 0, &panel
, &bridge
);
1301 if (ret
== -EPROBE_DEFER
)
1305 return component_add(&pdev
->dev
, &sun4i_tcon_ops
);
1308 static int sun4i_tcon_remove(struct platform_device
*pdev
)
1310 component_del(&pdev
->dev
, &sun4i_tcon_ops
);
1315 /* platform specific TCON muxing callbacks */
1316 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon
*tcon
,
1317 const struct drm_encoder
*encoder
)
1319 struct sun4i_tcon
*tcon0
= sun4i_get_tcon0(encoder
->dev
);
1325 switch (encoder
->encoder_type
) {
1326 case DRM_MODE_ENCODER_TMDS
:
1334 regmap_update_bits(tcon0
->regs
, SUN4I_TCON_MUX_CTRL_REG
,
1335 0x3 << shift
, tcon
->id
<< shift
);
1340 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon
*tcon
,
1341 const struct drm_encoder
*encoder
)
1345 if (encoder
->encoder_type
== DRM_MODE_ENCODER_TVDAC
)
1351 * FIXME: Undocumented bits
1353 return regmap_write(tcon
->regs
, SUN4I_TCON_MUX_CTRL_REG
, val
);
1356 static int sun6i_tcon_set_mux(struct sun4i_tcon
*tcon
,
1357 const struct drm_encoder
*encoder
)
1359 struct sun4i_tcon
*tcon0
= sun4i_get_tcon0(encoder
->dev
);
1365 switch (encoder
->encoder_type
) {
1366 case DRM_MODE_ENCODER_TMDS
:
1371 /* TODO A31 has MIPI DSI but A31s does not */
1375 regmap_update_bits(tcon0
->regs
, SUN4I_TCON_MUX_CTRL_REG
,
1376 0x3 << shift
, tcon
->id
<< shift
);
1381 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon
*tcon
,
1382 const struct drm_encoder
*encoder
)
1384 struct device_node
*port
, *remote
;
1385 struct platform_device
*pdev
;
1388 /* find TCON TOP platform device and TCON id */
1390 port
= of_graph_get_port_by_id(tcon
->dev
->of_node
, 0);
1394 id
= sun4i_tcon_of_get_id_from_port(port
);
1397 remote
= of_graph_get_remote_node(tcon
->dev
->of_node
, 0, -1);
1401 pdev
= of_find_device_by_node(remote
);
1402 of_node_put(remote
);
1406 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP
) &&
1407 encoder
->encoder_type
== DRM_MODE_ENCODER_TMDS
) {
1408 ret
= sun8i_tcon_top_set_hdmi_src(&pdev
->dev
, id
);
1413 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP
)) {
1414 ret
= sun8i_tcon_top_de_config(&pdev
->dev
, tcon
->id
, id
);
1422 static const struct sun4i_tcon_quirks sun4i_a10_quirks
= {
1423 .has_channel_0
= true,
1424 .has_channel_1
= true,
1425 .set_mux
= sun4i_a10_tcon_set_mux
,
1428 static const struct sun4i_tcon_quirks sun5i_a13_quirks
= {
1429 .has_channel_0
= true,
1430 .has_channel_1
= true,
1431 .set_mux
= sun5i_a13_tcon_set_mux
,
1434 static const struct sun4i_tcon_quirks sun6i_a31_quirks
= {
1435 .has_channel_0
= true,
1436 .has_channel_1
= true,
1437 .has_lvds_alt
= true,
1438 .needs_de_be_mux
= true,
1439 .set_mux
= sun6i_tcon_set_mux
,
1442 static const struct sun4i_tcon_quirks sun6i_a31s_quirks
= {
1443 .has_channel_0
= true,
1444 .has_channel_1
= true,
1445 .needs_de_be_mux
= true,
1448 static const struct sun4i_tcon_quirks sun7i_a20_quirks
= {
1449 .has_channel_0
= true,
1450 .has_channel_1
= true,
1451 /* Same display pipeline structure as A10 */
1452 .set_mux
= sun4i_a10_tcon_set_mux
,
1455 static const struct sun4i_tcon_quirks sun8i_a33_quirks
= {
1456 .has_channel_0
= true,
1457 .has_lvds_alt
= true,
1460 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks
= {
1461 .supports_lvds
= true,
1462 .has_channel_0
= true,
1465 static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks
= {
1466 .has_channel_1
= true,
1469 static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks
= {
1470 .has_channel_1
= true,
1471 .set_mux
= sun8i_r40_tcon_tv_set_mux
,
1474 static const struct sun4i_tcon_quirks sun8i_v3s_quirks
= {
1475 .has_channel_0
= true,
1478 static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks
= {
1479 .has_channel_0
= true,
1480 .needs_edp_reset
= true,
1483 static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks
= {
1484 .has_channel_1
= true,
1485 .needs_edp_reset
= true,
1488 /* sun4i_drv uses this list to check if a device node is a TCON */
1489 const struct of_device_id sun4i_tcon_of_table
[] = {
1490 { .compatible
= "allwinner,sun4i-a10-tcon", .data
= &sun4i_a10_quirks
},
1491 { .compatible
= "allwinner,sun5i-a13-tcon", .data
= &sun5i_a13_quirks
},
1492 { .compatible
= "allwinner,sun6i-a31-tcon", .data
= &sun6i_a31_quirks
},
1493 { .compatible
= "allwinner,sun6i-a31s-tcon", .data
= &sun6i_a31s_quirks
},
1494 { .compatible
= "allwinner,sun7i-a20-tcon", .data
= &sun7i_a20_quirks
},
1495 { .compatible
= "allwinner,sun8i-a23-tcon", .data
= &sun8i_a33_quirks
},
1496 { .compatible
= "allwinner,sun8i-a33-tcon", .data
= &sun8i_a33_quirks
},
1497 { .compatible
= "allwinner,sun8i-a83t-tcon-lcd", .data
= &sun8i_a83t_lcd_quirks
},
1498 { .compatible
= "allwinner,sun8i-a83t-tcon-tv", .data
= &sun8i_a83t_tv_quirks
},
1499 { .compatible
= "allwinner,sun8i-r40-tcon-tv", .data
= &sun8i_r40_tv_quirks
},
1500 { .compatible
= "allwinner,sun8i-v3s-tcon", .data
= &sun8i_v3s_quirks
},
1501 { .compatible
= "allwinner,sun9i-a80-tcon-lcd", .data
= &sun9i_a80_tcon_lcd_quirks
},
1502 { .compatible
= "allwinner,sun9i-a80-tcon-tv", .data
= &sun9i_a80_tcon_tv_quirks
},
1505 MODULE_DEVICE_TABLE(of
, sun4i_tcon_of_table
);
1506 EXPORT_SYMBOL(sun4i_tcon_of_table
);
1508 static struct platform_driver sun4i_tcon_platform_driver
= {
1509 .probe
= sun4i_tcon_probe
,
1510 .remove
= sun4i_tcon_remove
,
1512 .name
= "sun4i-tcon",
1513 .of_match_table
= sun4i_tcon_of_table
,
1516 module_platform_driver(sun4i_tcon_platform_driver
);
1518 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1519 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
1520 MODULE_LICENSE("GPL");