1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
14 #define DRV_MODULE_NAME "bnxt_en"
15 #define DRV_MODULE_VERSION "1.10.0"
18 #define DRV_VER_MIN 10
21 #include <linux/interrupt.h>
22 #include <linux/rhashtable.h>
23 #include <net/devlink.h>
24 #include <net/dst_metadata.h>
25 #include <net/switchdev.h>
27 #include <linux/net_dim.h>
30 __le32 tx_bd_len_flags_type
;
31 #define TX_BD_TYPE (0x3f << 0)
32 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
33 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
34 #define TX_BD_FLAGS_PACKET_END (1 << 6)
35 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
36 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
37 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
38 #define TX_BD_FLAGS_LHINT (3 << 13)
39 #define TX_BD_FLAGS_LHINT_SHIFT 13
40 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
41 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
42 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
43 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
44 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
45 #define TX_BD_LEN (0xffff << 16)
46 #define TX_BD_LEN_SHIFT 16
53 __le32 tx_bd_hsize_lflags
;
54 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
55 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
56 #define TX_BD_FLAGS_NO_CRC (1 << 2)
57 #define TX_BD_FLAGS_STAMP (1 << 3)
58 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
59 #define TX_BD_FLAGS_LSO (1 << 5)
60 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
61 #define TX_BD_FLAGS_T_IPID (1 << 7)
62 #define TX_BD_HSIZE (0xff << 16)
63 #define TX_BD_HSIZE_SHIFT 16
66 __le32 tx_bd_cfa_action
;
67 #define TX_BD_CFA_ACTION (0xffff << 16)
68 #define TX_BD_CFA_ACTION_SHIFT 16
70 __le32 tx_bd_cfa_meta
;
71 #define TX_BD_CFA_META_MASK 0xfffffff
72 #define TX_BD_CFA_META_VID_MASK 0xfff
73 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
74 #define TX_BD_CFA_META_PRI_SHIFT 12
75 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
76 #define TX_BD_CFA_META_TPID_SHIFT 16
77 #define TX_BD_CFA_META_KEY (0xf << 28)
78 #define TX_BD_CFA_META_KEY_SHIFT 28
79 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
83 __le32 rx_bd_len_flags_type
;
84 #define RX_BD_TYPE (0x3f << 0)
85 #define RX_BD_TYPE_RX_PACKET_BD 0x4
86 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
87 #define RX_BD_TYPE_RX_AGG_BD 0x6
88 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
89 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
90 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
91 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
92 #define RX_BD_FLAGS_SOP (1 << 6)
93 #define RX_BD_FLAGS_EOP (1 << 7)
94 #define RX_BD_FLAGS_BUFFERS (3 << 8)
95 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
96 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
97 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
98 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
99 #define RX_BD_LEN (0xffff << 16)
100 #define RX_BD_LEN_SHIFT 16
107 __le32 tx_cmp_flags_type
;
108 #define CMP_TYPE (0x3f << 0)
109 #define CMP_TYPE_TX_L2_CMP 0
110 #define CMP_TYPE_RX_L2_CMP 17
111 #define CMP_TYPE_RX_AGG_CMP 18
112 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
113 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
114 #define CMP_TYPE_STATUS_CMP 32
115 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
116 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
117 #define CMP_TYPE_ERROR_STATUS 48
118 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
119 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
120 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
121 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
122 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
124 #define TX_CMP_FLAGS_ERROR (1 << 6)
125 #define TX_CMP_FLAGS_PUSH (1 << 7)
128 __le32 tx_cmp_errors_v
;
129 #define TX_CMP_V (1 << 0)
130 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
131 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
132 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
133 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
134 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
135 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
136 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
137 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
138 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
140 __le32 tx_cmp_unsed_3
;
144 __le32 rx_cmp_len_flags_type
;
145 #define RX_CMP_CMP_TYPE (0x3f << 0)
146 #define RX_CMP_FLAGS_ERROR (1 << 6)
147 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
148 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
149 #define RX_CMP_FLAGS_UNUSED (1 << 11)
150 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
151 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
152 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
153 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
154 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
155 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
156 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
157 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
158 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
159 #define RX_CMP_LEN (0xffff << 16)
160 #define RX_CMP_LEN_SHIFT 16
163 __le32 rx_cmp_misc_v1
;
164 #define RX_CMP_V1 (1 << 0)
165 #define RX_CMP_AGG_BUFS (0x1f << 1)
166 #define RX_CMP_AGG_BUFS_SHIFT 1
167 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
168 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
169 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
170 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
172 __le32 rx_cmp_rss_hash
;
175 #define RX_CMP_HASH_VALID(rxcmp) \
176 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
178 #define RSS_PROFILE_ID_MASK 0x1f
180 #define RX_CMP_HASH_TYPE(rxcmp) \
181 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
182 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
185 __le32 rx_cmp_flags2
;
186 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
187 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
188 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
189 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
190 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
191 __le32 rx_cmp_meta_data
;
192 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
193 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
194 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
195 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
196 __le32 rx_cmp_cfa_code_errors_v2
;
197 #define RX_CMP_V (1 << 0)
198 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
199 #define RX_CMPL_ERRORS_SFT 1
200 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
201 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
202 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
203 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
204 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
205 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
206 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
207 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
208 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
209 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
210 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
211 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
212 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
213 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
214 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
217 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
218 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
219 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
220 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
221 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
222 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
223 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
224 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
225 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
226 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
227 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
229 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
230 #define RX_CMPL_CFA_CODE_SFT 16
232 __le32 rx_cmp_unused3
;
235 #define RX_CMP_L2_ERRORS \
236 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
238 #define RX_CMP_L4_CS_BITS \
239 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
241 #define RX_CMP_L4_CS_ERR_BITS \
242 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
244 #define RX_CMP_L4_CS_OK(rxcmp1) \
245 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
246 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
248 #define RX_CMP_ENCAP(rxcmp1) \
249 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
250 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
252 #define RX_CMP_CFA_CODE(rxcmpl1) \
253 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
254 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
257 __le32 rx_agg_cmp_len_flags_type
;
258 #define RX_AGG_CMP_TYPE (0x3f << 0)
259 #define RX_AGG_CMP_LEN (0xffff << 16)
260 #define RX_AGG_CMP_LEN_SHIFT 16
261 u32 rx_agg_cmp_opaque
;
263 #define RX_AGG_CMP_V (1 << 0)
264 __le32 rx_agg_cmp_unused
;
267 struct rx_tpa_start_cmp
{
268 __le32 rx_tpa_start_cmp_len_flags_type
;
269 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
270 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
271 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
272 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
273 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
274 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
275 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
276 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
277 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
278 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
279 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
280 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
281 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
282 #define RX_TPA_START_CMP_LEN (0xffff << 16)
283 #define RX_TPA_START_CMP_LEN_SHIFT 16
285 u32 rx_tpa_start_cmp_opaque
;
286 __le32 rx_tpa_start_cmp_misc_v1
;
287 #define RX_TPA_START_CMP_V1 (0x1 << 0)
288 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
289 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
290 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
291 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
293 __le32 rx_tpa_start_cmp_rss_hash
;
296 #define TPA_START_HASH_VALID(rx_tpa_start) \
297 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
298 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
300 #define TPA_START_HASH_TYPE(rx_tpa_start) \
301 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
302 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
303 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
305 #define TPA_START_AGG_ID(rx_tpa_start) \
306 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
307 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
309 struct rx_tpa_start_cmp_ext
{
310 __le32 rx_tpa_start_cmp_flags2
;
311 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
312 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
313 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
314 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
315 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
317 __le32 rx_tpa_start_cmp_metadata
;
318 __le32 rx_tpa_start_cmp_cfa_code_v2
;
319 #define RX_TPA_START_CMP_V2 (0x1 << 0)
320 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
321 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
322 __le32 rx_tpa_start_cmp_hdr_info
;
325 #define TPA_START_CFA_CODE(rx_tpa_start) \
326 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
327 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
329 #define TPA_START_IS_IPV6(rx_tpa_start) \
330 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
331 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
333 struct rx_tpa_end_cmp
{
334 __le32 rx_tpa_end_cmp_len_flags_type
;
335 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
336 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
337 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
338 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
339 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
340 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
341 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
342 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
343 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
344 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
345 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
346 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
347 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
348 #define RX_TPA_END_CMP_LEN (0xffff << 16)
349 #define RX_TPA_END_CMP_LEN_SHIFT 16
351 u32 rx_tpa_end_cmp_opaque
;
352 __le32 rx_tpa_end_cmp_misc_v1
;
353 #define RX_TPA_END_CMP_V1 (0x1 << 0)
354 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
355 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
356 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
357 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
358 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
359 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
360 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
361 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
363 __le32 rx_tpa_end_cmp_tsdelta
;
364 #define RX_TPA_END_GRO_TS (0x1 << 31)
367 #define TPA_END_AGG_ID(rx_tpa_end) \
368 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
369 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
371 #define TPA_END_TPA_SEGS(rx_tpa_end) \
372 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
373 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
375 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
376 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
377 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
379 #define TPA_END_GRO(rx_tpa_end) \
380 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
381 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
383 #define TPA_END_GRO_TS(rx_tpa_end) \
384 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
385 cpu_to_le32(RX_TPA_END_GRO_TS)))
387 struct rx_tpa_end_cmp_ext
{
388 __le32 rx_tpa_end_cmp_dup_acks
;
389 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
391 __le32 rx_tpa_end_cmp_seg_len
;
392 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
394 __le32 rx_tpa_end_cmp_errors_v2
;
395 #define RX_TPA_END_CMP_V2 (0x1 << 0)
396 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
397 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
399 u32 rx_tpa_end_cmp_start_opaque
;
402 #define TPA_END_ERRORS(rx_tpa_end_ext) \
403 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
404 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
408 #define NQ_CN_TYPE_MASK 0x3fUL
409 #define NQ_CN_TYPE_SFT 0
410 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
411 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
413 __le32 cq_handle_low
;
415 #define NQ_CN_V 0x1UL
416 __le32 cq_handle_high
;
419 #define DB_IDX_MASK 0xffffff
420 #define DB_IDX_VALID (0x1 << 26)
421 #define DB_IRQ_DIS (0x1 << 27)
422 #define DB_KEY_TX (0x0 << 28)
423 #define DB_KEY_RX (0x1 << 28)
424 #define DB_KEY_CP (0x2 << 28)
425 #define DB_KEY_ST (0x3 << 28)
426 #define DB_KEY_TX_PUSH (0x4 << 28)
427 #define DB_LONG_TX_PUSH (0x2 << 24)
429 #define BNXT_MIN_ROCE_CP_RINGS 2
430 #define BNXT_MIN_ROCE_STAT_CTXS 1
432 /* 64-bit doorbell */
433 #define DBR_INDEX_MASK 0x0000000000ffffffULL
434 #define DBR_XID_MASK 0x000fffff00000000ULL
435 #define DBR_XID_SFT 32
436 #define DBR_PATH_L2 (0x1ULL << 56)
437 #define DBR_TYPE_SQ (0x0ULL << 60)
438 #define DBR_TYPE_RQ (0x1ULL << 60)
439 #define DBR_TYPE_SRQ (0x2ULL << 60)
440 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
441 #define DBR_TYPE_CQ (0x4ULL << 60)
442 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
443 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
444 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
445 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
446 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
447 #define DBR_TYPE_NQ (0xaULL << 60)
448 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
449 #define DBR_TYPE_NULL (0xfULL << 60)
451 #define INVALID_HW_RING_ID ((u16)-1)
453 /* The hardware supports certain page sizes. Use the supported page sizes
454 * to allocate the rings.
456 #if (PAGE_SHIFT < 12)
457 #define BNXT_PAGE_SHIFT 12
458 #elif (PAGE_SHIFT <= 13)
459 #define BNXT_PAGE_SHIFT PAGE_SHIFT
460 #elif (PAGE_SHIFT < 16)
461 #define BNXT_PAGE_SHIFT 13
463 #define BNXT_PAGE_SHIFT 16
466 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
468 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
469 #if (PAGE_SHIFT > 15)
470 #define BNXT_RX_PAGE_SHIFT 15
472 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
475 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
477 #define BNXT_MAX_MTU 9500
478 #define BNXT_MAX_PAGE_MODE_MTU \
479 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
482 #define BNXT_MIN_PKT_SIZE 52
484 #define BNXT_DEFAULT_RX_RING_SIZE 511
485 #define BNXT_DEFAULT_TX_RING_SIZE 511
489 #if (BNXT_PAGE_SHIFT == 16)
490 #define MAX_RX_PAGES 1
491 #define MAX_RX_AGG_PAGES 4
492 #define MAX_TX_PAGES 1
493 #define MAX_CP_PAGES 8
495 #define MAX_RX_PAGES 8
496 #define MAX_RX_AGG_PAGES 32
497 #define MAX_TX_PAGES 8
498 #define MAX_CP_PAGES 64
501 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
502 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
503 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
505 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
506 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
508 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
510 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
511 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
513 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
515 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
516 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
517 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
519 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
520 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
522 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
523 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
525 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
526 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
528 #define TX_CMP_VALID(txcmp, raw_cons) \
529 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
530 !((raw_cons) & bp->cp_bit))
532 #define RX_CMP_VALID(rxcmp1, raw_cons) \
533 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
534 !((raw_cons) & bp->cp_bit))
536 #define RX_AGG_CMP_VALID(agg, raw_cons) \
537 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
538 !((raw_cons) & bp->cp_bit))
540 #define NQ_CMP_VALID(nqcmp, raw_cons) \
541 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
543 #define TX_CMP_TYPE(txcmp) \
544 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
546 #define RX_CMP_TYPE(rxcmp) \
547 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
549 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
551 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
553 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
555 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
556 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
557 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
558 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
560 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
561 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
562 #define DFLT_HWRM_CMD_TIMEOUT 500
563 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
564 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
565 #define HWRM_RESP_ERR_CODE_MASK 0xffff
566 #define HWRM_RESP_LEN_OFFSET 4
567 #define HWRM_RESP_LEN_MASK 0xffff0000
568 #define HWRM_RESP_LEN_SFT 16
569 #define HWRM_RESP_VALID_MASK 0xff000000
570 #define BNXT_HWRM_REQ_MAX_SIZE 128
571 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
572 BNXT_HWRM_REQ_MAX_SIZE)
573 #define HWRM_SHORT_MIN_TIMEOUT 3
574 #define HWRM_SHORT_MAX_TIMEOUT 10
575 #define HWRM_SHORT_TIMEOUT_COUNTER 5
577 #define HWRM_MIN_TIMEOUT 25
578 #define HWRM_MAX_TIMEOUT 40
580 #define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \
581 ((n) * HWRM_SHORT_MIN_TIMEOUT) : \
582 (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \
583 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
585 #define HWRM_VALID_BIT_DELAY_USEC 20
587 #define BNXT_HWRM_CHNL_CHIMP 0
588 #define BNXT_HWRM_CHNL_KONG 1
590 #define BNXT_RX_EVENT 1
591 #define BNXT_AGG_EVENT 2
592 #define BNXT_TX_EVENT 4
594 struct bnxt_sw_tx_bd
{
596 DEFINE_DMA_UNMAP_ADDR(mapping
);
600 unsigned short nr_frags
;
605 struct bnxt_sw_rx_bd
{
611 struct bnxt_sw_rx_agg_bd
{
617 struct bnxt_ring_mem_info
{
621 #define BNXT_RMEM_VALID_PTE_FLAG 1
622 #define BNXT_RMEM_RING_PTE_FLAG 2
623 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
631 dma_addr_t pg_tbl_map
;
637 struct bnxt_ring_struct
{
638 struct bnxt_ring_mem_info ring_mem
;
640 u16 fw_ring_id
; /* Ring id filled by Chimp FW */
643 u16 map_idx
; /* Used by cmpl rings */
651 __le32 tx_bd_len_flags_type
;
653 struct tx_bd_ext txbd2
;
656 struct tx_push_buffer
{
657 struct tx_push_bd push_bd
;
661 struct bnxt_db_info
{
662 void __iomem
*doorbell
;
669 struct bnxt_tx_ring_info
{
670 struct bnxt_napi
*bnapi
;
674 struct bnxt_db_info tx_db
;
676 struct tx_bd
*tx_desc_ring
[MAX_TX_PAGES
];
677 struct bnxt_sw_tx_bd
*tx_buf_ring
;
679 dma_addr_t tx_desc_mapping
[MAX_TX_PAGES
];
681 struct tx_push_buffer
*tx_push
;
682 dma_addr_t tx_push_mapping
;
685 #define BNXT_DEV_STATE_CLOSING 0x1
688 struct bnxt_ring_struct tx_ring_struct
;
691 #define BNXT_LEGACY_COAL_CMPL_PARAMS \
692 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
693 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
694 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
695 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
696 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
697 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
698 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
699 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
700 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
702 #define BNXT_COAL_CMPL_ENABLES \
703 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
704 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
705 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
706 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
708 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
709 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
711 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
712 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
714 struct bnxt_coal_cap
{
717 u16 num_cmpl_dma_aggr_max
;
718 u16 num_cmpl_dma_aggr_during_int_max
;
719 u16 cmpl_aggr_dma_tmr_max
;
720 u16 cmpl_aggr_dma_tmr_during_int_max
;
721 u16 int_lat_tmr_min_max
;
722 u16 int_lat_tmr_max_max
;
723 u16 num_cmpl_aggr_int_max
;
732 /* RING_IDLE enabled when coal ticks < idle_thresh */
738 struct bnxt_tpa_info
{
743 unsigned short gso_type
;
746 enum pkt_hash_types hash_type
;
750 #define BNXT_TPA_L4_SIZE(hdr_info) \
751 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
753 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
754 (((hdr_info) >> 18) & 0x1ff)
756 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
757 (((hdr_info) >> 9) & 0x1ff)
759 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
762 u16 cfa_code
; /* cfa_code in TPA start compl */
765 struct bnxt_rx_ring_info
{
766 struct bnxt_napi
*bnapi
;
771 struct bnxt_db_info rx_db
;
772 struct bnxt_db_info rx_agg_db
;
774 struct bpf_prog
*xdp_prog
;
776 struct rx_bd
*rx_desc_ring
[MAX_RX_PAGES
];
777 struct bnxt_sw_rx_bd
*rx_buf_ring
;
779 struct rx_bd
*rx_agg_desc_ring
[MAX_RX_AGG_PAGES
];
780 struct bnxt_sw_rx_agg_bd
*rx_agg_ring
;
782 unsigned long *rx_agg_bmap
;
783 u16 rx_agg_bmap_size
;
785 struct page
*rx_page
;
786 unsigned int rx_page_offset
;
788 dma_addr_t rx_desc_mapping
[MAX_RX_PAGES
];
789 dma_addr_t rx_agg_desc_mapping
[MAX_RX_AGG_PAGES
];
791 struct bnxt_tpa_info
*rx_tpa
;
793 struct bnxt_ring_struct rx_ring_struct
;
794 struct bnxt_ring_struct rx_agg_ring_struct
;
795 struct xdp_rxq_info xdp_rxq
;
798 struct bnxt_cp_ring_info
{
799 struct bnxt_napi
*bnapi
;
801 struct bnxt_db_info cp_db
;
806 u32 last_cp_raw_cons
;
808 struct bnxt_coal rx_ring_coal
;
816 struct tx_cmp
*cp_desc_ring
[MAX_CP_PAGES
];
817 struct nqe_cn
*nq_desc_ring
[MAX_CP_PAGES
];
820 dma_addr_t cp_desc_mapping
[MAX_CP_PAGES
];
822 struct ctx_hw_stats
*hw_stats
;
823 dma_addr_t hw_stats_map
;
825 u64 rx_l4_csum_errors
;
828 struct bnxt_ring_struct cp_ring_struct
;
830 struct bnxt_cp_ring_info
*cp_ring_arr
[2];
831 #define BNXT_RX_HDL 0
832 #define BNXT_TX_HDL 1
836 struct napi_struct napi
;
840 struct bnxt_cp_ring_info cp_ring
;
841 struct bnxt_rx_ring_info
*rx_ring
;
842 struct bnxt_tx_ring_info
*tx_ring
;
844 void (*tx_int
)(struct bnxt
*, struct bnxt_napi
*,
850 #define BNXT_NAPI_FLAG_XDP 0x1
856 irq_handler_t handler
;
860 char name
[IFNAMSIZ
+ 2];
861 cpumask_var_t cpu_mask
;
864 #define HWRM_RING_ALLOC_TX 0x1
865 #define HWRM_RING_ALLOC_RX 0x2
866 #define HWRM_RING_ALLOC_AGG 0x4
867 #define HWRM_RING_ALLOC_CMPL 0x8
868 #define HWRM_RING_ALLOC_NQ 0x10
870 #define INVALID_STATS_CTX_ID -1
872 struct bnxt_ring_grp_info
{
880 struct bnxt_vnic_info
{
881 u16 fw_vnic_id
; /* returned by Chimp during alloc */
882 #define BNXT_MAX_CTX_PER_VNIC 8
883 u16 fw_rss_cos_lb_ctx
[BNXT_MAX_CTX_PER_VNIC
];
885 #define BNXT_MAX_UC_ADDRS 4
886 __le64 fw_l2_filter_id
[BNXT_MAX_UC_ADDRS
];
887 /* index 0 always dev_addr */
892 dma_addr_t rss_table_dma_addr
;
894 dma_addr_t rss_hash_key_dma_addr
;
901 dma_addr_t mc_list_mapping
;
902 #define BNXT_MAX_MC_ADDRS 16
905 #define BNXT_VNIC_RSS_FLAG 1
906 #define BNXT_VNIC_RFS_FLAG 2
907 #define BNXT_VNIC_MCAST_FLAG 4
908 #define BNXT_VNIC_UCAST_FLAG 8
909 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
912 struct bnxt_hw_resc
{
921 u16 max_tx_sch_inputs
;
925 u16 min_hw_ring_grps
;
926 u16 max_hw_ring_grps
;
927 u16 resv_hw_ring_grps
;
941 #if defined(CONFIG_BNXT_SRIOV)
942 struct bnxt_vf_info
{
944 u8 mac_addr
[ETH_ALEN
]; /* PF assigned MAC Address */
945 u8 vf_mac_addr
[ETH_ALEN
]; /* VF assigned MAC address, only
950 #define BNXT_VF_QOS 0x1
951 #define BNXT_VF_SPOOFCHK 0x2
952 #define BNXT_VF_LINK_FORCED 0x4
953 #define BNXT_VF_LINK_UP 0x8
954 #define BNXT_VF_TRUST 0x10
955 u32 func_flags
; /* func cfg flags */
958 void *hwrm_cmd_req_addr
;
959 dma_addr_t hwrm_cmd_req_dma_addr
;
963 struct bnxt_pf_info
{
964 #define BNXT_FIRST_PF_FID 1
965 #define BNXT_FIRST_VF_FID 128
968 u8 mac_addr
[ETH_ALEN
];
972 u32 max_encap_records
;
973 u32 max_decap_records
;
978 unsigned long *vf_event_bmap
;
979 u16 hwrm_cmd_req_pages
;
981 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
982 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
983 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
984 void *hwrm_cmd_req_addr
[4];
985 dma_addr_t hwrm_cmd_req_dma_addr
[4];
986 struct bnxt_vf_info
*vf
;
989 struct bnxt_ntuple_filter
{
990 struct hlist_node hash
;
991 u8 dst_mac_addr
[ETH_ALEN
];
992 u8 src_mac_addr
[ETH_ALEN
];
993 struct flow_keys fkeys
;
1000 #define BNXT_FLTR_VALID 0
1001 #define BNXT_FLTR_UPDATE 1
1004 struct bnxt_link_info
{
1010 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1011 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1012 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1017 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1018 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1020 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1021 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1022 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1023 PORT_PHY_QCFG_RESP_PAUSE_TX)
1025 u8 auto_pause_setting
;
1026 u8 force_pause_setting
;
1029 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1030 (mode) <= BNXT_LINK_AUTO_MSK)
1031 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1032 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1033 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1034 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1035 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1036 #define PHY_VER_LEN 3
1037 u8 phy_ver
[PHY_VER_LEN
];
1039 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1040 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1041 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1042 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1043 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1044 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1045 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1046 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1047 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1048 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1050 u16 auto_link_speeds
; /* fw adv setting */
1051 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1052 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1053 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1054 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1055 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1056 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1057 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1058 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1059 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1060 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1061 u16 support_auto_speeds
;
1062 u16 lp_auto_link_speeds
;
1063 u16 force_link_speed
;
1067 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1068 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1069 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
1071 /* copy of requested setting from ethtool cmd */
1073 #define BNXT_AUTONEG_SPEED 1
1074 #define BNXT_AUTONEG_FLOW_CTRL 2
1078 u16 advertising
; /* user adv setting */
1079 bool force_link_chng
;
1082 unsigned long phy_retry_expires
;
1084 /* a copy of phy_qcfg output used to report link
1087 struct hwrm_port_phy_qcfg_output phy_qcfg_resp
;
1090 #define BNXT_MAX_QUEUE 8
1092 struct bnxt_queue_info
{
1097 #define BNXT_MAX_LED 4
1099 struct bnxt_led_info
{
1104 __le16 led_state_caps
;
1105 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1106 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1108 __le16 led_color_caps
;
1111 #define BNXT_MAX_TEST 8
1113 struct bnxt_test_info
{
1116 #define BNXT_TEST_FL_EXT_LPBK 0x1
1118 char string
[BNXT_MAX_TEST
][ETH_GSTRING_LEN
];
1121 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1122 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1123 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1124 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1125 #define BNXT_CAG_REG_BASE 0x300000
1127 #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1128 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1130 struct bnxt_tc_flow_stats
{
1135 struct bnxt_tc_info
{
1138 /* hash table to store TC offloaded flows */
1139 struct rhashtable flow_table
;
1140 struct rhashtable_params flow_ht_params
;
1142 /* hash table to store L2 keys of TC flows */
1143 struct rhashtable l2_table
;
1144 struct rhashtable_params l2_ht_params
;
1145 /* hash table to store L2 keys for TC tunnel decap */
1146 struct rhashtable decap_l2_table
;
1147 struct rhashtable_params decap_l2_ht_params
;
1148 /* hash table to store tunnel decap entries */
1149 struct rhashtable decap_table
;
1150 struct rhashtable_params decap_ht_params
;
1151 /* hash table to store tunnel encap entries */
1152 struct rhashtable encap_table
;
1153 struct rhashtable_params encap_ht_params
;
1155 /* lock to atomically add/del an l2 node when a flow is
1160 /* Fields used for batching stats query */
1161 struct rhashtable_iter iter
;
1162 #define BNXT_FLOW_STATS_BATCH_MAX 10
1163 struct bnxt_tc_stats_batch
{
1165 struct bnxt_tc_flow_stats hw_stats
;
1166 } stats_batch
[BNXT_FLOW_STATS_BATCH_MAX
];
1168 /* Stat counter mask (width) */
1173 struct bnxt_vf_rep_stats
{
1179 struct bnxt_vf_rep
{
1181 struct net_device
*dev
;
1182 struct metadata_dst
*dst
;
1187 struct bnxt_vf_rep_stats rx_stats
;
1188 struct bnxt_vf_rep_stats tx_stats
;
1191 #define PTU_PTE_VALID 0x1UL
1192 #define PTU_PTE_LAST 0x2UL
1193 #define PTU_PTE_NEXT_TO_LAST 0x4UL
1195 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1196 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1198 struct bnxt_ctx_pg_info
{
1201 void *ctx_pg_arr
[MAX_CTX_PAGES
];
1202 dma_addr_t ctx_dma_arr
[MAX_CTX_PAGES
];
1203 struct bnxt_ring_mem_info ring_mem
;
1204 struct bnxt_ctx_pg_info
**ctx_pg_tbl
;
1207 struct bnxt_ctx_mem_info
{
1209 u16 qp_min_qp1_entries
;
1210 u16 qp_max_l2_entries
;
1212 u16 srq_max_l2_entries
;
1213 u32 srq_max_entries
;
1215 u16 cq_max_l2_entries
;
1218 u16 vnic_max_vnic_entries
;
1219 u16 vnic_max_ring_table_entries
;
1220 u16 vnic_entry_size
;
1221 u32 stat_max_entries
;
1222 u16 stat_entry_size
;
1224 u32 tqm_min_entries_per_ring
;
1225 u32 tqm_max_entries_per_ring
;
1226 u32 mrav_max_entries
;
1227 u16 mrav_entry_size
;
1229 u32 tim_max_entries
;
1230 u8 tqm_entries_multiple
;
1233 #define BNXT_CTX_FLAG_INITED 0x01
1235 struct bnxt_ctx_pg_info qp_mem
;
1236 struct bnxt_ctx_pg_info srq_mem
;
1237 struct bnxt_ctx_pg_info cq_mem
;
1238 struct bnxt_ctx_pg_info vnic_mem
;
1239 struct bnxt_ctx_pg_info stat_mem
;
1240 struct bnxt_ctx_pg_info mrav_mem
;
1241 struct bnxt_ctx_pg_info tim_mem
;
1242 struct bnxt_ctx_pg_info
*tqm_mem
[9];
1252 #define CHIP_NUM_57301 0x16c8
1253 #define CHIP_NUM_57302 0x16c9
1254 #define CHIP_NUM_57304 0x16ca
1255 #define CHIP_NUM_58700 0x16cd
1256 #define CHIP_NUM_57402 0x16d0
1257 #define CHIP_NUM_57404 0x16d1
1258 #define CHIP_NUM_57406 0x16d2
1259 #define CHIP_NUM_57407 0x16d5
1261 #define CHIP_NUM_57311 0x16ce
1262 #define CHIP_NUM_57312 0x16cf
1263 #define CHIP_NUM_57314 0x16df
1264 #define CHIP_NUM_57317 0x16e0
1265 #define CHIP_NUM_57412 0x16d6
1266 #define CHIP_NUM_57414 0x16d7
1267 #define CHIP_NUM_57416 0x16d8
1268 #define CHIP_NUM_57417 0x16d9
1269 #define CHIP_NUM_57412L 0x16da
1270 #define CHIP_NUM_57414L 0x16db
1272 #define CHIP_NUM_5745X 0xd730
1274 #define CHIP_NUM_57500 0x1750
1276 #define CHIP_NUM_58802 0xd802
1277 #define CHIP_NUM_58804 0xd804
1278 #define CHIP_NUM_58808 0xd808
1280 #define BNXT_CHIP_NUM_5730X(chip_num) \
1281 ((chip_num) >= CHIP_NUM_57301 && \
1282 (chip_num) <= CHIP_NUM_57304)
1284 #define BNXT_CHIP_NUM_5740X(chip_num) \
1285 (((chip_num) >= CHIP_NUM_57402 && \
1286 (chip_num) <= CHIP_NUM_57406) || \
1287 (chip_num) == CHIP_NUM_57407)
1289 #define BNXT_CHIP_NUM_5731X(chip_num) \
1290 ((chip_num) == CHIP_NUM_57311 || \
1291 (chip_num) == CHIP_NUM_57312 || \
1292 (chip_num) == CHIP_NUM_57314 || \
1293 (chip_num) == CHIP_NUM_57317)
1295 #define BNXT_CHIP_NUM_5741X(chip_num) \
1296 ((chip_num) >= CHIP_NUM_57412 && \
1297 (chip_num) <= CHIP_NUM_57414L)
1299 #define BNXT_CHIP_NUM_58700(chip_num) \
1300 ((chip_num) == CHIP_NUM_58700)
1302 #define BNXT_CHIP_NUM_5745X(chip_num) \
1303 ((chip_num) == CHIP_NUM_5745X)
1305 #define BNXT_CHIP_NUM_57X0X(chip_num) \
1306 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1308 #define BNXT_CHIP_NUM_57X1X(chip_num) \
1309 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1311 #define BNXT_CHIP_NUM_588XX(chip_num) \
1312 ((chip_num) == CHIP_NUM_58802 || \
1313 (chip_num) == CHIP_NUM_58804 || \
1314 (chip_num) == CHIP_NUM_58808)
1316 struct net_device
*dev
;
1317 struct pci_dev
*pdev
;
1322 #define BNXT_FLAG_CHIP_P5 0x1
1323 #define BNXT_FLAG_VF 0x2
1324 #define BNXT_FLAG_LRO 0x4
1326 #define BNXT_FLAG_GRO 0x8
1328 /* Cannot support hardware GRO if CONFIG_INET is not set */
1329 #define BNXT_FLAG_GRO 0x0
1331 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1332 #define BNXT_FLAG_JUMBO 0x10
1333 #define BNXT_FLAG_STRIP_VLAN 0x20
1334 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1336 #define BNXT_FLAG_USING_MSIX 0x40
1337 #define BNXT_FLAG_MSIX_CAP 0x80
1338 #define BNXT_FLAG_RFS 0x100
1339 #define BNXT_FLAG_SHARED_RINGS 0x200
1340 #define BNXT_FLAG_PORT_STATS 0x400
1341 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1342 #define BNXT_FLAG_EEE_CAP 0x1000
1343 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1344 #define BNXT_FLAG_WOL_CAP 0x4000
1345 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1346 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1347 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1348 BNXT_FLAG_ROCEV2_CAP)
1349 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1350 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1351 #define BNXT_FLAG_MULTI_HOST 0x100000
1352 #define BNXT_FLAG_DOUBLE_DB 0x400000
1353 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1354 #define BNXT_FLAG_DIM 0x2000000
1355 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1356 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1358 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1360 BNXT_FLAG_STRIP_VLAN)
1362 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1363 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1364 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
1365 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1366 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1367 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1368 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1369 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
1370 !(bp->flags & BNXT_FLAG_CHIP_P5))
1372 /* Chip class phase 5 */
1373 #define BNXT_CHIP_P5(bp) \
1374 ((bp)->chip_num == CHIP_NUM_57500)
1376 /* Chip class phase 4.x */
1377 #define BNXT_CHIP_P4(bp) \
1378 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1379 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1380 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1381 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1382 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1384 #define BNXT_CHIP_P4_PLUS(bp) \
1385 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1387 struct bnxt_en_dev
*edev
;
1388 struct bnxt_en_dev
* (*ulp_probe
)(struct net_device
*);
1390 struct bnxt_napi
**bnapi
;
1392 struct bnxt_rx_ring_info
*rx_ring
;
1393 struct bnxt_tx_ring_info
*tx_ring
;
1396 struct sk_buff
* (*gro_func
)(struct bnxt_tpa_info
*, int, int,
1399 struct sk_buff
* (*rx_skb_func
)(struct bnxt
*,
1400 struct bnxt_rx_ring_info
*,
1401 u16
, void *, u8
*, dma_addr_t
,
1405 u32 rx_buf_use_size
; /* useable size */
1408 enum dma_data_direction rx_dir
;
1410 u32 rx_agg_ring_size
;
1413 u32 rx_agg_ring_mask
;
1415 int rx_agg_nr_pages
;
1423 int tx_nr_rings_per_tc
;
1424 int tx_nr_rings_xdp
;
1436 /* grp_info indexed by completion ring index */
1437 struct bnxt_ring_grp_info
*grp_info
;
1438 struct bnxt_vnic_info
*vnic_info
;
1444 u8 max_lltc
; /* lossless TCs */
1445 struct bnxt_queue_info q_info
[BNXT_MAX_QUEUE
];
1446 u8 tc_to_qidx
[BNXT_MAX_QUEUE
];
1447 u8 q_ids
[BNXT_MAX_QUEUE
];
1450 unsigned int current_interval
;
1451 #define BNXT_TIMER_INTERVAL HZ
1453 struct timer_list timer
;
1455 unsigned long state
;
1456 #define BNXT_STATE_OPEN 0
1457 #define BNXT_STATE_IN_SP_TASK 1
1458 #define BNXT_STATE_READ_STATS 2
1460 struct bnxt_irq
*irq_tbl
;
1462 u8 mac_addr
[ETH_ALEN
];
1464 #ifdef CONFIG_BNXT_DCB
1465 struct ieee_pfc
*ieee_pfc
;
1466 struct ieee_ets
*ieee_ets
;
1470 #endif /* CONFIG_BNXT_DCB */
1475 #define BNXT_FW_CAP_SHORT_CMD 0x00000001
1476 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
1477 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
1478 #define BNXT_FW_CAP_NEW_RM 0x00000008
1479 #define BNXT_FW_CAP_IF_CHANGE 0x00000010
1480 #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080
1481 #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400
1483 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1486 u16 hwrm_cmd_kong_seq
;
1487 u16 hwrm_intr_seq_id
;
1488 void *hwrm_short_cmd_req_addr
;
1489 dma_addr_t hwrm_short_cmd_req_dma_addr
;
1490 void *hwrm_cmd_resp_addr
;
1491 dma_addr_t hwrm_cmd_resp_dma_addr
;
1492 void *hwrm_cmd_kong_resp_addr
;
1493 dma_addr_t hwrm_cmd_kong_resp_dma_addr
;
1495 struct rtnl_link_stats64 net_stats_prev
;
1496 struct rx_port_stats
*hw_rx_port_stats
;
1497 struct tx_port_stats
*hw_tx_port_stats
;
1498 struct rx_port_stats_ext
*hw_rx_port_stats_ext
;
1499 struct tx_port_stats_ext
*hw_tx_port_stats_ext
;
1500 dma_addr_t hw_rx_port_stats_map
;
1501 dma_addr_t hw_tx_port_stats_map
;
1502 dma_addr_t hw_rx_port_stats_ext_map
;
1503 dma_addr_t hw_tx_port_stats_ext_map
;
1504 int hw_port_stats_size
;
1505 u16 fw_rx_stats_ext_size
;
1506 u16 fw_tx_stats_ext_size
;
1510 u16 hwrm_max_req_len
;
1511 u16 hwrm_max_ext_req_len
;
1512 int hwrm_cmd_timeout
;
1513 struct mutex hwrm_cmd_lock
; /* serialize hwrm messages */
1514 struct hwrm_ver_get_output ver_resp
;
1515 #define FW_VER_STR_LEN 32
1516 #define BC_HWRM_STR_LEN 21
1517 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1518 char fw_ver_str
[FW_VER_STR_LEN
];
1521 __le16 vxlan_fw_dst_port_id
;
1524 __le16 nge_fw_dst_port_id
;
1525 u8 port_partition_type
;
1529 struct bnxt_coal_cap coal_cap
;
1530 struct bnxt_coal rx_coal
;
1531 struct bnxt_coal tx_coal
;
1533 u32 stats_coal_ticks
;
1534 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1535 #define BNXT_MIN_STATS_COAL_TICKS 250000
1536 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1538 struct work_struct sp_task
;
1539 unsigned long sp_event
;
1540 #define BNXT_RX_MASK_SP_EVENT 0
1541 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1542 #define BNXT_LINK_CHNG_SP_EVENT 2
1543 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1544 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1545 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1546 #define BNXT_RESET_TASK_SP_EVENT 6
1547 #define BNXT_RST_RING_SP_EVENT 7
1548 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1549 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1550 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1551 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1552 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1553 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1554 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1555 #define BNXT_FLOW_STATS_SP_EVENT 15
1556 #define BNXT_UPDATE_PHY_SP_EVENT 16
1557 #define BNXT_RING_COAL_NOW_SP_EVENT 17
1559 struct bnxt_hw_resc hw_resc
;
1560 struct bnxt_pf_info pf
;
1561 struct bnxt_ctx_mem_info
*ctx
;
1562 #ifdef CONFIG_BNXT_SRIOV
1564 struct bnxt_vf_info vf
;
1565 wait_queue_head_t sriov_cfg_wait
;
1567 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1569 /* lock to protect VF-rep creation/cleanup via
1570 * multiple paths such as ->sriov_configure() and
1571 * devlink ->eswitch_mode_set()
1573 struct mutex sriov_lock
;
1576 #if BITS_PER_LONG == 32
1577 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1581 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1582 #define BNXT_NTP_FLTR_HASH_SIZE 512
1583 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1584 struct hlist_head ntp_fltr_hash_tbl
[BNXT_NTP_FLTR_HASH_SIZE
];
1585 spinlock_t ntp_fltr_lock
; /* for hash table add, del */
1587 unsigned long *ntp_fltr_bmap
;
1590 /* To protect link related settings during link changes and
1591 * ethtool settings changes.
1593 struct mutex link_lock
;
1594 struct bnxt_link_info link_info
;
1595 struct ethtool_eee eee
;
1600 struct bnxt_test_info
*test_info
;
1606 struct bnxt_led_info leds
[BNXT_MAX_LED
];
1608 struct bpf_prog
*xdp_prog
;
1610 /* devlink interface and vf-rep structs */
1612 enum devlink_eswitch_mode eswitch_mode
;
1613 struct bnxt_vf_rep
**vf_reps
; /* array of vf-rep ptrs */
1614 u16
*cfa_code_map
; /* cfa_code -> vf_idx map */
1616 struct bnxt_tc_info
*tc_info
;
1617 struct dentry
*debugfs_pdev
;
1618 struct dentry
*debugfs_dim
;
1619 struct device
*hwmon_dev
;
1622 #define BNXT_RX_STATS_OFFSET(counter) \
1623 (offsetof(struct rx_port_stats, counter) / 8)
1625 #define BNXT_TX_STATS_OFFSET(counter) \
1626 ((offsetof(struct tx_port_stats, counter) + \
1627 sizeof(struct rx_port_stats) + 512) / 8)
1629 #define BNXT_RX_STATS_EXT_OFFSET(counter) \
1630 (offsetof(struct rx_port_stats_ext, counter) / 8)
1632 #define BNXT_TX_STATS_EXT_OFFSET(counter) \
1633 (offsetof(struct tx_port_stats_ext, counter) / 8)
1635 #define I2C_DEV_ADDR_A0 0xa0
1636 #define I2C_DEV_ADDR_A2 0xa2
1637 #define SFF_DIAG_SUPPORT_OFFSET 0x5c
1638 #define SFF_MODULE_ID_SFP 0x3
1639 #define SFF_MODULE_ID_QSFP 0xc
1640 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1641 #define SFF_MODULE_ID_QSFP28 0x11
1642 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1644 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
1646 /* Tell compiler to fetch tx indices from memory. */
1649 return bp
->tx_ring_size
-
1650 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
1653 #if BITS_PER_LONG == 32
1654 #define writeq(val64, db) \
1656 spin_lock(&bp->db_lock); \
1657 writel((val64) & 0xffffffff, db); \
1658 writel((val64) >> 32, (db) + 4); \
1659 spin_unlock(&bp->db_lock); \
1662 #define writeq_relaxed writeq
1665 /* For TX and RX ring doorbells with no ordering guarantee*/
1666 static inline void bnxt_db_write_relaxed(struct bnxt
*bp
,
1667 struct bnxt_db_info
*db
, u32 idx
)
1669 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
1670 writeq_relaxed(db
->db_key64
| idx
, db
->doorbell
);
1672 u32 db_val
= db
->db_key32
| idx
;
1674 writel_relaxed(db_val
, db
->doorbell
);
1675 if (bp
->flags
& BNXT_FLAG_DOUBLE_DB
)
1676 writel_relaxed(db_val
, db
->doorbell
);
1680 /* For TX and RX ring doorbells */
1681 static inline void bnxt_db_write(struct bnxt
*bp
, struct bnxt_db_info
*db
,
1684 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
1685 writeq(db
->db_key64
| idx
, db
->doorbell
);
1687 u32 db_val
= db
->db_key32
| idx
;
1689 writel(db_val
, db
->doorbell
);
1690 if (bp
->flags
& BNXT_FLAG_DOUBLE_DB
)
1691 writel(db_val
, db
->doorbell
);
1695 static inline bool bnxt_cfa_hwrm_message(u16 req_type
)
1698 case HWRM_CFA_ENCAP_RECORD_ALLOC
:
1699 case HWRM_CFA_ENCAP_RECORD_FREE
:
1700 case HWRM_CFA_DECAP_FILTER_ALLOC
:
1701 case HWRM_CFA_DECAP_FILTER_FREE
:
1702 case HWRM_CFA_NTUPLE_FILTER_ALLOC
:
1703 case HWRM_CFA_NTUPLE_FILTER_FREE
:
1704 case HWRM_CFA_NTUPLE_FILTER_CFG
:
1705 case HWRM_CFA_EM_FLOW_ALLOC
:
1706 case HWRM_CFA_EM_FLOW_FREE
:
1707 case HWRM_CFA_EM_FLOW_CFG
:
1708 case HWRM_CFA_FLOW_ALLOC
:
1709 case HWRM_CFA_FLOW_FREE
:
1710 case HWRM_CFA_FLOW_INFO
:
1711 case HWRM_CFA_FLOW_FLUSH
:
1712 case HWRM_CFA_FLOW_STATS
:
1713 case HWRM_CFA_METER_PROFILE_ALLOC
:
1714 case HWRM_CFA_METER_PROFILE_FREE
:
1715 case HWRM_CFA_METER_PROFILE_CFG
:
1716 case HWRM_CFA_METER_INSTANCE_ALLOC
:
1717 case HWRM_CFA_METER_INSTANCE_FREE
:
1724 static inline bool bnxt_kong_hwrm_message(struct bnxt
*bp
, struct input
*req
)
1726 return (bp
->fw_cap
& BNXT_FW_CAP_KONG_MB_CHNL
&&
1727 bnxt_cfa_hwrm_message(le16_to_cpu(req
->req_type
)));
1730 static inline bool bnxt_hwrm_kong_chnl(struct bnxt
*bp
, struct input
*req
)
1732 return (bp
->fw_cap
& BNXT_FW_CAP_KONG_MB_CHNL
&&
1733 req
->resp_addr
== cpu_to_le64(bp
->hwrm_cmd_kong_resp_dma_addr
));
1736 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt
*bp
, void *req
)
1738 if (bnxt_hwrm_kong_chnl(bp
, (struct input
*)req
))
1739 return bp
->hwrm_cmd_kong_resp_addr
;
1741 return bp
->hwrm_cmd_resp_addr
;
1744 static inline u16
bnxt_get_hwrm_seq_id(struct bnxt
*bp
, u16 dst
)
1748 if (dst
== BNXT_HWRM_CHNL_CHIMP
)
1749 seq_id
= bp
->hwrm_cmd_seq
++;
1751 seq_id
= bp
->hwrm_cmd_kong_seq
++;
1755 extern const u16 bnxt_lhint_arr
[];
1757 int bnxt_alloc_rx_data(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
1758 u16 prod
, gfp_t gfp
);
1759 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
, void *data
);
1760 void bnxt_set_tpa_flags(struct bnxt
*bp
);
1761 void bnxt_set_ring_params(struct bnxt
*);
1762 int bnxt_set_rx_skb_mode(struct bnxt
*bp
, bool page_mode
);
1763 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*, void *, u16
, u16
, u16
);
1764 int _hwrm_send_message(struct bnxt
*, void *, u32
, int);
1765 int _hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 len
, int timeout
);
1766 int hwrm_send_message(struct bnxt
*, void *, u32
, int);
1767 int hwrm_send_message_silent(struct bnxt
*, void *, u32
, int);
1768 int bnxt_hwrm_func_rgtr_async_events(struct bnxt
*bp
, unsigned long *bmap
,
1770 int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
);
1771 int __bnxt_hwrm_get_tx_rings(struct bnxt
*bp
, u16 fid
, int *tx_rings
);
1772 int bnxt_nq_rings_in_use(struct bnxt
*bp
);
1773 int bnxt_hwrm_set_coal(struct bnxt
*);
1774 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt
*bp
);
1775 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt
*bp
);
1776 unsigned int bnxt_get_max_func_cp_rings(struct bnxt
*bp
);
1777 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt
*bp
);
1778 int bnxt_get_avail_msix(struct bnxt
*bp
, int num
);
1779 int bnxt_reserve_rings(struct bnxt
*bp
);
1780 void bnxt_tx_disable(struct bnxt
*bp
);
1781 void bnxt_tx_enable(struct bnxt
*bp
);
1782 int bnxt_hwrm_set_pause(struct bnxt
*);
1783 int bnxt_hwrm_set_link_setting(struct bnxt
*, bool, bool);
1784 int bnxt_hwrm_alloc_wol_fltr(struct bnxt
*bp
);
1785 int bnxt_hwrm_free_wol_fltr(struct bnxt
*bp
);
1786 int bnxt_hwrm_func_resc_qcaps(struct bnxt
*bp
, bool all
);
1787 int bnxt_hwrm_fw_set_time(struct bnxt
*);
1788 int bnxt_open_nic(struct bnxt
*, bool, bool);
1789 int bnxt_half_open_nic(struct bnxt
*bp
);
1790 void bnxt_half_close_nic(struct bnxt
*bp
);
1791 int bnxt_close_nic(struct bnxt
*, bool, bool);
1792 int bnxt_check_rings(struct bnxt
*bp
, int tx
, int rx
, bool sh
, int tcs
,
1794 int bnxt_setup_mq_tc(struct net_device
*dev
, u8 tc
);
1795 int bnxt_get_max_rings(struct bnxt
*, int *, int *, bool);
1796 int bnxt_restore_pf_fw_resources(struct bnxt
*bp
);
1797 int bnxt_port_attr_get(struct bnxt
*bp
, struct switchdev_attr
*attr
);
1798 void bnxt_dim_work(struct work_struct
*work
);
1799 int bnxt_hwrm_set_ring_coal(struct bnxt
*bp
, struct bnxt_napi
*bnapi
);