drivers/net/ethernet/mscc/ocelot.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
   2 /*
   3  * Microsemi Ocelot Switch driver
   4  *
   5  * Copyright (c) 2017 Microsemi Corporation
   6  */
   7
   8 #ifndef _MSCC_OCELOT_H_
   9 #define _MSCC_OCELOT_H_
  10
  11 #include <linux/bitops.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/if_vlan.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/regmap.h>
  16
  17 #include "ocelot_ana.h"
  18 #include "ocelot_dev.h"
  19 #include "ocelot_hsio.h"
  20 #include "ocelot_qsys.h"
  21 #include "ocelot_rew.h"
  22 #include "ocelot_sys.h"
  23 #include "ocelot_qs.h"
  24
  25 #define PGID_AGGR    64
  26 #define PGID_SRC     80
  27
  28 /* Reserved PGIDs */
  29 #define PGID_CPU     (PGID_AGGR - 5)
  30 #define PGID_UC      (PGID_AGGR - 4)
  31 #define PGID_MC      (PGID_AGGR - 3)
  32 #define PGID_MCIPV4  (PGID_AGGR - 2)
  33 #define PGID_MCIPV6  (PGID_AGGR - 1)
  34
  35 #define OCELOT_BUFFER_CELL_SZ 60
  36
  37 #define OCELOT_STATS_CHECK_DELAY (2 * HZ)
  38
  39 #define IFH_LEN 4
  40
  41 struct frame_info {
  42         u32 len;
  43         u16 port;
  44         u16 vid;
  45         u8 cpuq;
  46         u8 tag_type;
  47 };
  48
  49 #define IFH_INJ_BYPASS  BIT(31)
  50 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
  51
  52 #define IFH_TAG_TYPE_C 0
  53 #define IFH_TAG_TYPE_S 1
  54
  55 #define OCELOT_SPEED_2500 0
  56 #define OCELOT_SPEED_1000 1
  57 #define OCELOT_SPEED_100  2
  58 #define OCELOT_SPEED_10   3
  59
  60 #define TARGET_OFFSET 24
  61 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
  62 #define REG(reg, offset) [reg & REG_MASK] = offset
  63
  64 enum ocelot_target {
  65         ANA = 1,
  66         QS,
  67         QSYS,
  68         REW,
  69         SYS,
  70         HSIO,
  71         TARGET_MAX,
  72 };
  73
  74 enum ocelot_reg {
  75         ANA_ADVLEARN = ANA << TARGET_OFFSET,
  76         ANA_VLANMASK,
  77         ANA_PORT_B_DOMAIN,
  78         ANA_ANAGEFIL,
  79         ANA_ANEVENTS,
  80         ANA_STORMLIMIT_BURST,
  81         ANA_STORMLIMIT_CFG,
  82         ANA_ISOLATED_PORTS,
  83         ANA_COMMUNITY_PORTS,
  84         ANA_AUTOAGE,
  85         ANA_MACTOPTIONS,
  86         ANA_LEARNDISC,
  87         ANA_AGENCTRL,
  88         ANA_MIRRORPORTS,
  89         ANA_EMIRRORPORTS,
  90         ANA_FLOODING,
  91         ANA_FLOODING_IPMC,
  92         ANA_SFLOW_CFG,
  93         ANA_PORT_MODE,
  94         ANA_CUT_THRU_CFG,
  95         ANA_PGID_PGID,
  96         ANA_TABLES_ANMOVED,
  97         ANA_TABLES_MACHDATA,
  98         ANA_TABLES_MACLDATA,
  99         ANA_TABLES_STREAMDATA,
 100         ANA_TABLES_MACACCESS,
 101         ANA_TABLES_MACTINDX,
 102         ANA_TABLES_VLANACCESS,
 103         ANA_TABLES_VLANTIDX,
 104         ANA_TABLES_ISDXACCESS,
 105         ANA_TABLES_ISDXTIDX,
 106         ANA_TABLES_ENTRYLIM,
 107         ANA_TABLES_PTP_ID_HIGH,
 108         ANA_TABLES_PTP_ID_LOW,
 109         ANA_TABLES_STREAMACCESS,
 110         ANA_TABLES_STREAMTIDX,
 111         ANA_TABLES_SEQ_HISTORY,
 112         ANA_TABLES_SEQ_MASK,
 113         ANA_TABLES_SFID_MASK,
 114         ANA_TABLES_SFIDACCESS,
 115         ANA_TABLES_SFIDTIDX,
 116         ANA_MSTI_STATE,
 117         ANA_OAM_UPM_LM_CNT,
 118         ANA_SG_ACCESS_CTRL,
 119         ANA_SG_CONFIG_REG_1,
 120         ANA_SG_CONFIG_REG_2,
 121         ANA_SG_CONFIG_REG_3,
 122         ANA_SG_CONFIG_REG_4,
 123         ANA_SG_CONFIG_REG_5,
 124         ANA_SG_GCL_GS_CONFIG,
 125         ANA_SG_GCL_TI_CONFIG,
 126         ANA_SG_STATUS_REG_1,
 127         ANA_SG_STATUS_REG_2,
 128         ANA_SG_STATUS_REG_3,
 129         ANA_PORT_VLAN_CFG,
 130         ANA_PORT_DROP_CFG,
 131         ANA_PORT_QOS_CFG,
 132         ANA_PORT_VCAP_CFG,
 133         ANA_PORT_VCAP_S1_KEY_CFG,
 134         ANA_PORT_VCAP_S2_CFG,
 135         ANA_PORT_PCP_DEI_MAP,
 136         ANA_PORT_CPU_FWD_CFG,
 137         ANA_PORT_CPU_FWD_BPDU_CFG,
 138         ANA_PORT_CPU_FWD_GARP_CFG,
 139         ANA_PORT_CPU_FWD_CCM_CFG,
 140         ANA_PORT_PORT_CFG,
 141         ANA_PORT_POL_CFG,
 142         ANA_PORT_PTP_CFG,
 143         ANA_PORT_PTP_DLY1_CFG,
 144         ANA_PORT_PTP_DLY2_CFG,
 145         ANA_PORT_SFID_CFG,
 146         ANA_PFC_PFC_CFG,
 147         ANA_PFC_PFC_TIMER,
 148         ANA_IPT_OAM_MEP_CFG,
 149         ANA_IPT_IPT,
 150         ANA_PPT_PPT,
 151         ANA_FID_MAP_FID_MAP,
 152         ANA_AGGR_CFG,
 153         ANA_CPUQ_CFG,
 154         ANA_CPUQ_CFG2,
 155         ANA_CPUQ_8021_CFG,
 156         ANA_DSCP_CFG,
 157         ANA_DSCP_REWR_CFG,
 158         ANA_VCAP_RNG_TYPE_CFG,
 159         ANA_VCAP_RNG_VAL_CFG,
 160         ANA_VRAP_CFG,
 161         ANA_VRAP_HDR_DATA,
 162         ANA_VRAP_HDR_MASK,
 163         ANA_DISCARD_CFG,
 164         ANA_FID_CFG,
 165         ANA_POL_PIR_CFG,
 166         ANA_POL_CIR_CFG,
 167         ANA_POL_MODE_CFG,
 168         ANA_POL_PIR_STATE,
 169         ANA_POL_CIR_STATE,
 170         ANA_POL_STATE,
 171         ANA_POL_FLOWC,
 172         ANA_POL_HYST,
 173         ANA_POL_MISC_CFG,
 174         QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
 175         QS_XTR_RD,
 176         QS_XTR_FRM_PRUNING,
 177         QS_XTR_FLUSH,
 178         QS_XTR_DATA_PRESENT,
 179         QS_XTR_CFG,
 180         QS_INJ_GRP_CFG,
 181         QS_INJ_WR,
 182         QS_INJ_CTRL,
 183         QS_INJ_STATUS,
 184         QS_INJ_ERR,
 185         QS_INH_DBG,
 186         QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
 187         QSYS_SWITCH_PORT_MODE,
 188         QSYS_STAT_CNT_CFG,
 189         QSYS_EEE_CFG,
 190         QSYS_EEE_THRES,
 191         QSYS_IGR_NO_SHARING,
 192         QSYS_EGR_NO_SHARING,
 193         QSYS_SW_STATUS,
 194         QSYS_EXT_CPU_CFG,
 195         QSYS_PAD_CFG,
 196         QSYS_CPU_GROUP_MAP,
 197         QSYS_QMAP,
 198         QSYS_ISDX_SGRP,
 199         QSYS_TIMED_FRAME_ENTRY,
 200         QSYS_TFRM_MISC,
 201         QSYS_TFRM_PORT_DLY,
 202         QSYS_TFRM_TIMER_CFG_1,
 203         QSYS_TFRM_TIMER_CFG_2,
 204         QSYS_TFRM_TIMER_CFG_3,
 205         QSYS_TFRM_TIMER_CFG_4,
 206         QSYS_TFRM_TIMER_CFG_5,
 207         QSYS_TFRM_TIMER_CFG_6,
 208         QSYS_TFRM_TIMER_CFG_7,
 209         QSYS_TFRM_TIMER_CFG_8,
 210         QSYS_RED_PROFILE,
 211         QSYS_RES_QOS_MODE,
 212         QSYS_RES_CFG,
 213         QSYS_RES_STAT,
 214         QSYS_EGR_DROP_MODE,
 215         QSYS_EQ_CTRL,
 216         QSYS_EVENTS_CORE,
 217         QSYS_QMAXSDU_CFG_0,
 218         QSYS_QMAXSDU_CFG_1,
 219         QSYS_QMAXSDU_CFG_2,
 220         QSYS_QMAXSDU_CFG_3,
 221         QSYS_QMAXSDU_CFG_4,
 222         QSYS_QMAXSDU_CFG_5,
 223         QSYS_QMAXSDU_CFG_6,
 224         QSYS_QMAXSDU_CFG_7,
 225         QSYS_PREEMPTION_CFG,
 226         QSYS_CIR_CFG,
 227         QSYS_EIR_CFG,
 228         QSYS_SE_CFG,
 229         QSYS_SE_DWRR_CFG,
 230         QSYS_SE_CONNECT,
 231         QSYS_SE_DLB_SENSE,
 232         QSYS_CIR_STATE,
 233         QSYS_EIR_STATE,
 234         QSYS_SE_STATE,
 235         QSYS_HSCH_MISC_CFG,
 236         QSYS_TAG_CONFIG,
 237         QSYS_TAS_PARAM_CFG_CTRL,
 238         QSYS_PORT_MAX_SDU,
 239         QSYS_PARAM_CFG_REG_1,
 240         QSYS_PARAM_CFG_REG_2,
 241         QSYS_PARAM_CFG_REG_3,
 242         QSYS_PARAM_CFG_REG_4,
 243         QSYS_PARAM_CFG_REG_5,
 244         QSYS_GCL_CFG_REG_1,
 245         QSYS_GCL_CFG_REG_2,
 246         QSYS_PARAM_STATUS_REG_1,
 247         QSYS_PARAM_STATUS_REG_2,
 248         QSYS_PARAM_STATUS_REG_3,
 249         QSYS_PARAM_STATUS_REG_4,
 250         QSYS_PARAM_STATUS_REG_5,
 251         QSYS_PARAM_STATUS_REG_6,
 252         QSYS_PARAM_STATUS_REG_7,
 253         QSYS_PARAM_STATUS_REG_8,
 254         QSYS_PARAM_STATUS_REG_9,
 255         QSYS_GCL_STATUS_REG_1,
 256         QSYS_GCL_STATUS_REG_2,
 257         REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
 258         REW_TAG_CFG,
 259         REW_PORT_CFG,
 260         REW_DSCP_CFG,
 261         REW_PCP_DEI_QOS_MAP_CFG,
 262         REW_PTP_CFG,
 263         REW_PTP_DLY1_CFG,
 264         REW_RED_TAG_CFG,
 265         REW_DSCP_REMAP_DP1_CFG,
 266         REW_DSCP_REMAP_CFG,
 267         REW_STAT_CFG,
 268         REW_REW_STICKY,
 269         REW_PPT,
 270         SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
 271         SYS_COUNT_RX_UNICAST,
 272         SYS_COUNT_RX_MULTICAST,
 273         SYS_COUNT_RX_BROADCAST,
 274         SYS_COUNT_RX_SHORTS,
 275         SYS_COUNT_RX_FRAGMENTS,
 276         SYS_COUNT_RX_JABBERS,
 277         SYS_COUNT_RX_CRC_ALIGN_ERRS,
 278         SYS_COUNT_RX_SYM_ERRS,
 279         SYS_COUNT_RX_64,
 280         SYS_COUNT_RX_65_127,
 281         SYS_COUNT_RX_128_255,
 282         SYS_COUNT_RX_256_1023,
 283         SYS_COUNT_RX_1024_1526,
 284         SYS_COUNT_RX_1527_MAX,
 285         SYS_COUNT_RX_PAUSE,
 286         SYS_COUNT_RX_CONTROL,
 287         SYS_COUNT_RX_LONGS,
 288         SYS_COUNT_RX_CLASSIFIED_DROPS,
 289         SYS_COUNT_TX_OCTETS,
 290         SYS_COUNT_TX_UNICAST,
 291         SYS_COUNT_TX_MULTICAST,
 292         SYS_COUNT_TX_BROADCAST,
 293         SYS_COUNT_TX_COLLISION,
 294         SYS_COUNT_TX_DROPS,
 295         SYS_COUNT_TX_PAUSE,
 296         SYS_COUNT_TX_64,
 297         SYS_COUNT_TX_65_127,
 298         SYS_COUNT_TX_128_511,
 299         SYS_COUNT_TX_512_1023,
 300         SYS_COUNT_TX_1024_1526,
 301         SYS_COUNT_TX_1527_MAX,
 302         SYS_COUNT_TX_AGING,
 303         SYS_RESET_CFG,
 304         SYS_SR_ETYPE_CFG,
 305         SYS_VLAN_ETYPE_CFG,
 306         SYS_PORT_MODE,
 307         SYS_FRONT_PORT_MODE,
 308         SYS_FRM_AGING,
 309         SYS_STAT_CFG,
 310         SYS_SW_STATUS,
 311         SYS_MISC_CFG,
 312         SYS_REW_MAC_HIGH_CFG,
 313         SYS_REW_MAC_LOW_CFG,
 314         SYS_TIMESTAMP_OFFSET,
 315         SYS_CMID,
 316         SYS_PAUSE_CFG,
 317         SYS_PAUSE_TOT_CFG,
 318         SYS_ATOP,
 319         SYS_ATOP_TOT_CFG,
 320         SYS_MAC_FC_CFG,
 321         SYS_MMGT,
 322         SYS_MMGT_FAST,
 323         SYS_EVENTS_DIF,
 324         SYS_EVENTS_CORE,
 325         SYS_CNT,
 326         SYS_PTP_STATUS,
 327         SYS_PTP_TXSTAMP,
 328         SYS_PTP_NXT,
 329         SYS_PTP_CFG,
 330         SYS_RAM_INIT,
 331         SYS_CM_ADDR,
 332         SYS_CM_DATA_WR,
 333         SYS_CM_DATA_RD,
 334         SYS_CM_OP,
 335         SYS_CM_DATA,
 336         HSIO_PLL5G_CFG0 = HSIO << TARGET_OFFSET,
 337         HSIO_PLL5G_CFG1,
 338         HSIO_PLL5G_CFG2,
 339         HSIO_PLL5G_CFG3,
 340         HSIO_PLL5G_CFG4,
 341         HSIO_PLL5G_CFG5,
 342         HSIO_PLL5G_CFG6,
 343         HSIO_PLL5G_STATUS0,
 344         HSIO_PLL5G_STATUS1,
 345         HSIO_PLL5G_BIST_CFG0,
 346         HSIO_PLL5G_BIST_CFG1,
 347         HSIO_PLL5G_BIST_CFG2,
 348         HSIO_PLL5G_BIST_STAT0,
 349         HSIO_PLL5G_BIST_STAT1,
 350         HSIO_RCOMP_CFG0,
 351         HSIO_RCOMP_STATUS,
 352         HSIO_SYNC_ETH_CFG,
 353         HSIO_SYNC_ETH_PLL_CFG,
 354         HSIO_S1G_DES_CFG,
 355         HSIO_S1G_IB_CFG,
 356         HSIO_S1G_OB_CFG,
 357         HSIO_S1G_SER_CFG,
 358         HSIO_S1G_COMMON_CFG,
 359         HSIO_S1G_PLL_CFG,
 360         HSIO_S1G_PLL_STATUS,
 361         HSIO_S1G_DFT_CFG0,
 362         HSIO_S1G_DFT_CFG1,
 363         HSIO_S1G_DFT_CFG2,
 364         HSIO_S1G_TP_CFG,
 365         HSIO_S1G_RC_PLL_BIST_CFG,
 366         HSIO_S1G_MISC_CFG,
 367         HSIO_S1G_DFT_STATUS,
 368         HSIO_S1G_MISC_STATUS,
 369         HSIO_MCB_S1G_ADDR_CFG,
 370         HSIO_S6G_DIG_CFG,
 371         HSIO_S6G_DFT_CFG0,
 372         HSIO_S6G_DFT_CFG1,
 373         HSIO_S6G_DFT_CFG2,
 374         HSIO_S6G_TP_CFG0,
 375         HSIO_S6G_TP_CFG1,
 376         HSIO_S6G_RC_PLL_BIST_CFG,
 377         HSIO_S6G_MISC_CFG,
 378         HSIO_S6G_OB_ANEG_CFG,
 379         HSIO_S6G_DFT_STATUS,
 380         HSIO_S6G_ERR_CNT,
 381         HSIO_S6G_MISC_STATUS,
 382         HSIO_S6G_DES_CFG,
 383         HSIO_S6G_IB_CFG,
 384         HSIO_S6G_IB_CFG1,
 385         HSIO_S6G_IB_CFG2,
 386         HSIO_S6G_IB_CFG3,
 387         HSIO_S6G_IB_CFG4,
 388         HSIO_S6G_IB_CFG5,
 389         HSIO_S6G_OB_CFG,
 390         HSIO_S6G_OB_CFG1,
 391         HSIO_S6G_SER_CFG,
 392         HSIO_S6G_COMMON_CFG,
 393         HSIO_S6G_PLL_CFG,
 394         HSIO_S6G_ACJTAG_CFG,
 395         HSIO_S6G_GP_CFG,
 396         HSIO_S6G_IB_STATUS0,
 397         HSIO_S6G_IB_STATUS1,
 398         HSIO_S6G_ACJTAG_STATUS,
 399         HSIO_S6G_PLL_STATUS,
 400         HSIO_S6G_REVID,
 401         HSIO_MCB_S6G_ADDR_CFG,
 402         HSIO_HW_CFG,
 403         HSIO_HW_QSGMII_CFG,
 404         HSIO_HW_QSGMII_STAT,
 405         HSIO_CLK_CFG,
 406         HSIO_TEMP_SENSOR_CTRL,
 407         HSIO_TEMP_SENSOR_CFG,
 408         HSIO_TEMP_SENSOR_STAT,
 409 };
 410
 411 enum ocelot_regfield {
 412         ANA_ADVLEARN_VLAN_CHK,
 413         ANA_ADVLEARN_LEARN_MIRROR,
 414         ANA_ANEVENTS_FLOOD_DISCARD,
 415         ANA_ANEVENTS_MSTI_DROP,
 416         ANA_ANEVENTS_ACLKILL,
 417         ANA_ANEVENTS_ACLUSED,
 418         ANA_ANEVENTS_AUTOAGE,
 419         ANA_ANEVENTS_VS2TTL1,
 420         ANA_ANEVENTS_STORM_DROP,
 421         ANA_ANEVENTS_LEARN_DROP,
 422         ANA_ANEVENTS_AGED_ENTRY,
 423         ANA_ANEVENTS_CPU_LEARN_FAILED,
 424         ANA_ANEVENTS_AUTO_LEARN_FAILED,
 425         ANA_ANEVENTS_LEARN_REMOVE,
 426         ANA_ANEVENTS_AUTO_LEARNED,
 427         ANA_ANEVENTS_AUTO_MOVED,
 428         ANA_ANEVENTS_DROPPED,
 429         ANA_ANEVENTS_CLASSIFIED_DROP,
 430         ANA_ANEVENTS_CLASSIFIED_COPY,
 431         ANA_ANEVENTS_VLAN_DISCARD,
 432         ANA_ANEVENTS_FWD_DISCARD,
 433         ANA_ANEVENTS_MULTICAST_FLOOD,
 434         ANA_ANEVENTS_UNICAST_FLOOD,
 435         ANA_ANEVENTS_DEST_KNOWN,
 436         ANA_ANEVENTS_BUCKET3_MATCH,
 437         ANA_ANEVENTS_BUCKET2_MATCH,
 438         ANA_ANEVENTS_BUCKET1_MATCH,
 439         ANA_ANEVENTS_BUCKET0_MATCH,
 440         ANA_ANEVENTS_CPU_OPERATION,
 441         ANA_ANEVENTS_DMAC_LOOKUP,
 442         ANA_ANEVENTS_SMAC_LOOKUP,
 443         ANA_ANEVENTS_SEQ_GEN_ERR_0,
 444         ANA_ANEVENTS_SEQ_GEN_ERR_1,
 445         ANA_TABLES_MACACCESS_B_DOM,
 446         ANA_TABLES_MACTINDX_BUCKET,
 447         ANA_TABLES_MACTINDX_M_INDEX,
 448         QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
 449         QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
 450         QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
 451         QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
 452         QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
 453         SYS_RESET_CFG_CORE_ENA,
 454         SYS_RESET_CFG_MEM_ENA,
 455         SYS_RESET_CFG_MEM_INIT,
 456         REGFIELD_MAX
 457 };
 458
 459 struct ocelot_multicast {
 460         struct list_head list;
 461         unsigned char addr[ETH_ALEN];
 462         u16 vid;
 463         u16 ports;
 464 };
 465
 466 struct ocelot_port;
 467
 468 struct ocelot_stat_layout {
 469         u32 offset;
 470         char name[ETH_GSTRING_LEN];
 471 };
 472
 473 struct ocelot {
 474         struct device *dev;
 475
 476         struct regmap *targets[TARGET_MAX];
 477         struct regmap_field *regfields[REGFIELD_MAX];
 478         const u32 *const *map;
 479         const struct ocelot_stat_layout *stats_layout;
 480         unsigned int num_stats;
 481
 482         u8 base_mac[ETH_ALEN];
 483
 484         struct net_device *hw_bridge_dev;
 485         u16 bridge_mask;
 486         u16 bridge_fwd_mask;
 487
 488         struct workqueue_struct *ocelot_owq;
 489
 490         int shared_queue_sz;
 491
 492         u8 num_phys_ports;
 493         u8 num_cpu_ports;
 494         struct ocelot_port **ports;
 495
 496         u16 lags[16];
 497
 498         /* Keep track of the vlan port masks */
 499         u32 vlan_mask[VLAN_N_VID];
 500
 501         struct list_head multicast;
 502
 503         /* Workqueue to check statistics for overflow with its lock */
 504         struct mutex stats_lock;
 505         u64 *stats;
 506         struct delayed_work stats_work;
 507         struct workqueue_struct *stats_queue;
 508 };
 509
 510 struct ocelot_port {
 511         struct net_device *dev;
 512         struct ocelot *ocelot;
 513         struct phy_device *phy;
 514         void __iomem *regs;
 515         u8 chip_port;
 516         /* Keep a track of the mc addresses added to the mac table, so that they
 517          * can be removed when needed.
 518          */
 519         struct list_head mc;
 520
 521         /* Ingress default VLAN (pvid) */
 522         u16 pvid;
 523
 524         /* Egress default VLAN (vid) */
 525         u16 vid;
 526
 527         u8 vlan_aware;
 528
 529         u64 *stats;
 530 };
 531
 532 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
 533 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 534 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
 535 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
 536 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
 537
 538 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
 539 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 540 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
 541 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
 542 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
 543
 544 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 mask,
 545                      u32 offset);
 546 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 547 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
 548 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
 549 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
 550
 551 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
 552 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
 553
 554 int ocelot_regfields_init(struct ocelot *ocelot,
 555                           const struct reg_field *const regfields);
 556 struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
 557                                        struct platform_device *pdev,
 558                                        const char *name);
 559
 560 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
 561 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
 562
 563 int ocelot_init(struct ocelot *ocelot);
 564 void ocelot_deinit(struct ocelot *ocelot);
 565 int ocelot_chip_init(struct ocelot *ocelot);
 566 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
 567                       void __iomem *regs,
 568                       struct phy_device *phy);
 569
 570 extern struct notifier_block ocelot_netdevice_nb;
 571
 572 #endif