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[thirdparty/linux.git] / drivers / net / ethernet / renesas / ravb_main.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
3 *
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 *
8 * Based on the SuperH Ethernet driver
9 */
10
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/sys_soc.h>
32
33 #include <asm/div64.h>
34
35 #include "ravb.h"
36
37 #define RAVB_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR)
42
43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
44 "ch0", /* RAVB_BE */
45 "ch1", /* RAVB_NC */
46 };
47
48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
49 "ch18", /* RAVB_BE */
50 "ch19", /* RAVB_NC */
51 };
52
53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
54 u32 set)
55 {
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
57 }
58
59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
60 {
61 int i;
62
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
65 return 0;
66 udelay(10);
67 }
68 return -ETIMEDOUT;
69 }
70
71 static int ravb_config(struct net_device *ndev)
72 {
73 int error;
74
75 /* Set config mode */
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
79 if (error)
80 netdev_err(ndev, "failed to switch device to config mode\n");
81
82 return error;
83 }
84
85 static void ravb_set_rate(struct net_device *ndev)
86 {
87 struct ravb_private *priv = netdev_priv(ndev);
88
89 switch (priv->speed) {
90 case 100: /* 100BASE */
91 ravb_write(ndev, GECMR_SPEED_100, GECMR);
92 break;
93 case 1000: /* 1000BASE */
94 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
95 break;
96 }
97 }
98
99 static void ravb_set_buffer_align(struct sk_buff *skb)
100 {
101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
102
103 if (reserve)
104 skb_reserve(skb, RAVB_ALIGN - reserve);
105 }
106
107 /* Get MAC address from the MAC address registers
108 *
109 * Ethernet AVB device doesn't have ROM for MAC address.
110 * This function gets the MAC address that was used by a bootloader.
111 */
112 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
113 {
114 if (!IS_ERR(mac)) {
115 ether_addr_copy(ndev->dev_addr, mac);
116 } else {
117 u32 mahr = ravb_read(ndev, MAHR);
118 u32 malr = ravb_read(ndev, MALR);
119
120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
124 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
125 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
126 }
127 }
128
129 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
130 {
131 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
132 mdiobb);
133
134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
135 }
136
137 /* MDC pin control */
138 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
139 {
140 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
141 }
142
143 /* Data I/O pin control */
144 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
145 {
146 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
147 }
148
149 /* Set data bit */
150 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
151 {
152 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
153 }
154
155 /* Get data bit */
156 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
157 {
158 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
159 mdiobb);
160
161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
162 }
163
164 /* MDIO bus control struct */
165 static struct mdiobb_ops bb_ops = {
166 .owner = THIS_MODULE,
167 .set_mdc = ravb_set_mdc,
168 .set_mdio_dir = ravb_set_mdio_dir,
169 .set_mdio_data = ravb_set_mdio_data,
170 .get_mdio_data = ravb_get_mdio_data,
171 };
172
173 /* Free TX skb function for AVB-IP */
174 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
175 {
176 struct ravb_private *priv = netdev_priv(ndev);
177 struct net_device_stats *stats = &priv->stats[q];
178 int num_tx_desc = priv->num_tx_desc;
179 struct ravb_tx_desc *desc;
180 int free_num = 0;
181 int entry;
182 u32 size;
183
184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
185 bool txed;
186
187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
188 num_tx_desc);
189 desc = &priv->tx_ring[q][entry];
190 txed = desc->die_dt == DT_FEMPTY;
191 if (free_txed_only && !txed)
192 break;
193 /* Descriptor type must be checked before all other reads */
194 dma_rmb();
195 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
196 /* Free the original skb. */
197 if (priv->tx_skb[q][entry / num_tx_desc]) {
198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
199 size, DMA_TO_DEVICE);
200 /* Last packet descriptor? */
201 if (entry % num_tx_desc == num_tx_desc - 1) {
202 entry /= num_tx_desc;
203 dev_kfree_skb_any(priv->tx_skb[q][entry]);
204 priv->tx_skb[q][entry] = NULL;
205 if (txed)
206 stats->tx_packets++;
207 }
208 free_num++;
209 }
210 if (txed)
211 stats->tx_bytes += size;
212 desc->die_dt = DT_EEMPTY;
213 }
214 return free_num;
215 }
216
217 /* Free skb's and DMA buffers for Ethernet AVB */
218 static void ravb_ring_free(struct net_device *ndev, int q)
219 {
220 struct ravb_private *priv = netdev_priv(ndev);
221 int num_tx_desc = priv->num_tx_desc;
222 int ring_size;
223 int i;
224
225 if (priv->rx_ring[q]) {
226 for (i = 0; i < priv->num_rx_ring[q]; i++) {
227 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
228
229 if (!dma_mapping_error(ndev->dev.parent,
230 le32_to_cpu(desc->dptr)))
231 dma_unmap_single(ndev->dev.parent,
232 le32_to_cpu(desc->dptr),
233 priv->rx_buf_sz,
234 DMA_FROM_DEVICE);
235 }
236 ring_size = sizeof(struct ravb_ex_rx_desc) *
237 (priv->num_rx_ring[q] + 1);
238 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
239 priv->rx_desc_dma[q]);
240 priv->rx_ring[q] = NULL;
241 }
242
243 if (priv->tx_ring[q]) {
244 ravb_tx_free(ndev, q, false);
245
246 ring_size = sizeof(struct ravb_tx_desc) *
247 (priv->num_tx_ring[q] * num_tx_desc + 1);
248 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
249 priv->tx_desc_dma[q]);
250 priv->tx_ring[q] = NULL;
251 }
252
253 /* Free RX skb ringbuffer */
254 if (priv->rx_skb[q]) {
255 for (i = 0; i < priv->num_rx_ring[q]; i++)
256 dev_kfree_skb(priv->rx_skb[q][i]);
257 }
258 kfree(priv->rx_skb[q]);
259 priv->rx_skb[q] = NULL;
260
261 /* Free aligned TX buffers */
262 kfree(priv->tx_align[q]);
263 priv->tx_align[q] = NULL;
264
265 /* Free TX skb ringbuffer.
266 * SKBs are freed by ravb_tx_free() call above.
267 */
268 kfree(priv->tx_skb[q]);
269 priv->tx_skb[q] = NULL;
270 }
271
272 /* Format skb and descriptor buffer for Ethernet AVB */
273 static void ravb_ring_format(struct net_device *ndev, int q)
274 {
275 struct ravb_private *priv = netdev_priv(ndev);
276 int num_tx_desc = priv->num_tx_desc;
277 struct ravb_ex_rx_desc *rx_desc;
278 struct ravb_tx_desc *tx_desc;
279 struct ravb_desc *desc;
280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
282 num_tx_desc;
283 dma_addr_t dma_addr;
284 int i;
285
286 priv->cur_rx[q] = 0;
287 priv->cur_tx[q] = 0;
288 priv->dirty_rx[q] = 0;
289 priv->dirty_tx[q] = 0;
290
291 memset(priv->rx_ring[q], 0, rx_ring_size);
292 /* Build RX ring buffer */
293 for (i = 0; i < priv->num_rx_ring[q]; i++) {
294 /* RX descriptor */
295 rx_desc = &priv->rx_ring[q][i];
296 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
298 priv->rx_buf_sz,
299 DMA_FROM_DEVICE);
300 /* We just set the data size to 0 for a failed mapping which
301 * should prevent DMA from happening...
302 */
303 if (dma_mapping_error(ndev->dev.parent, dma_addr))
304 rx_desc->ds_cc = cpu_to_le16(0);
305 rx_desc->dptr = cpu_to_le32(dma_addr);
306 rx_desc->die_dt = DT_FEMPTY;
307 }
308 rx_desc = &priv->rx_ring[q][i];
309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
310 rx_desc->die_dt = DT_LINKFIX; /* type */
311
312 memset(priv->tx_ring[q], 0, tx_ring_size);
313 /* Build TX ring buffer */
314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
315 i++, tx_desc++) {
316 tx_desc->die_dt = DT_EEMPTY;
317 if (num_tx_desc > 1) {
318 tx_desc++;
319 tx_desc->die_dt = DT_EEMPTY;
320 }
321 }
322 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
323 tx_desc->die_dt = DT_LINKFIX; /* type */
324
325 /* RX descriptor base address for best effort */
326 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
327 desc->die_dt = DT_LINKFIX; /* type */
328 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
329
330 /* TX descriptor base address for best effort */
331 desc = &priv->desc_bat[q];
332 desc->die_dt = DT_LINKFIX; /* type */
333 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
334 }
335
336 /* Init skb and descriptor buffer for Ethernet AVB */
337 static int ravb_ring_init(struct net_device *ndev, int q)
338 {
339 struct ravb_private *priv = netdev_priv(ndev);
340 int num_tx_desc = priv->num_tx_desc;
341 struct sk_buff *skb;
342 int ring_size;
343 int i;
344
345 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) +
346 ETH_HLEN + VLAN_HLEN + sizeof(__sum16);
347
348 /* Allocate RX and TX skb rings */
349 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
350 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
351 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
352 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
353 if (!priv->rx_skb[q] || !priv->tx_skb[q])
354 goto error;
355
356 for (i = 0; i < priv->num_rx_ring[q]; i++) {
357 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1);
358 if (!skb)
359 goto error;
360 ravb_set_buffer_align(skb);
361 priv->rx_skb[q][i] = skb;
362 }
363
364 if (num_tx_desc > 1) {
365 /* Allocate rings for the aligned buffers */
366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
367 DPTR_ALIGN - 1, GFP_KERNEL);
368 if (!priv->tx_align[q])
369 goto error;
370 }
371
372 /* Allocate all RX descriptors. */
373 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
374 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
375 &priv->rx_desc_dma[q],
376 GFP_KERNEL);
377 if (!priv->rx_ring[q])
378 goto error;
379
380 priv->dirty_rx[q] = 0;
381
382 /* Allocate all TX descriptors. */
383 ring_size = sizeof(struct ravb_tx_desc) *
384 (priv->num_tx_ring[q] * num_tx_desc + 1);
385 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
386 &priv->tx_desc_dma[q],
387 GFP_KERNEL);
388 if (!priv->tx_ring[q])
389 goto error;
390
391 return 0;
392
393 error:
394 ravb_ring_free(ndev, q);
395
396 return -ENOMEM;
397 }
398
399 /* E-MAC init function */
400 static void ravb_emac_init(struct net_device *ndev)
401 {
402 /* Receive frame limit set register */
403 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
404
405 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
406 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
407 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
408 ECMR_TE | ECMR_RE, ECMR);
409
410 ravb_set_rate(ndev);
411
412 /* Set MAC address */
413 ravb_write(ndev,
414 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
415 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
416 ravb_write(ndev,
417 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
418
419 /* E-MAC status register clear */
420 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
421
422 /* E-MAC interrupt enable register */
423 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
424 }
425
426 /* Device init function for Ethernet AVB */
427 static int ravb_dmac_init(struct net_device *ndev)
428 {
429 struct ravb_private *priv = netdev_priv(ndev);
430 int error;
431
432 /* Set CONFIG mode */
433 error = ravb_config(ndev);
434 if (error)
435 return error;
436
437 error = ravb_ring_init(ndev, RAVB_BE);
438 if (error)
439 return error;
440 error = ravb_ring_init(ndev, RAVB_NC);
441 if (error) {
442 ravb_ring_free(ndev, RAVB_BE);
443 return error;
444 }
445
446 /* Descriptor format */
447 ravb_ring_format(ndev, RAVB_BE);
448 ravb_ring_format(ndev, RAVB_NC);
449
450 #if defined(__LITTLE_ENDIAN)
451 ravb_modify(ndev, CCC, CCC_BOC, 0);
452 #else
453 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
454 #endif
455
456 /* Set AVB RX */
457 ravb_write(ndev,
458 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
459
460 /* Set FIFO size */
461 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
462
463 /* Timestamp enable */
464 ravb_write(ndev, TCCR_TFEN, TCCR);
465
466 /* Interrupt init: */
467 if (priv->chip_id == RCAR_GEN3) {
468 /* Clear DIL.DPLx */
469 ravb_write(ndev, 0, DIL);
470 /* Set queue specific interrupt */
471 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
472 }
473 /* Frame receive */
474 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
475 /* Disable FIFO full warning */
476 ravb_write(ndev, 0, RIC1);
477 /* Receive FIFO full error, descriptor empty */
478 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
479 /* Frame transmitted, timestamp FIFO updated */
480 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
481
482 /* Setting the control will start the AVB-DMAC process. */
483 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
484
485 return 0;
486 }
487
488 static void ravb_get_tx_tstamp(struct net_device *ndev)
489 {
490 struct ravb_private *priv = netdev_priv(ndev);
491 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
492 struct skb_shared_hwtstamps shhwtstamps;
493 struct sk_buff *skb;
494 struct timespec64 ts;
495 u16 tag, tfa_tag;
496 int count;
497 u32 tfa2;
498
499 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
500 while (count--) {
501 tfa2 = ravb_read(ndev, TFA2);
502 tfa_tag = (tfa2 & TFA2_TST) >> 16;
503 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
504 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
505 ravb_read(ndev, TFA1);
506 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
507 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
508 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
509 list) {
510 skb = ts_skb->skb;
511 tag = ts_skb->tag;
512 list_del(&ts_skb->list);
513 kfree(ts_skb);
514 if (tag == tfa_tag) {
515 skb_tstamp_tx(skb, &shhwtstamps);
516 break;
517 }
518 }
519 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
520 }
521 }
522
523 static void ravb_rx_csum(struct sk_buff *skb)
524 {
525 u8 *hw_csum;
526
527 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
528 * appended to packet data
529 */
530 if (unlikely(skb->len < sizeof(__sum16)))
531 return;
532 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
533 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
534 skb->ip_summed = CHECKSUM_COMPLETE;
535 skb_trim(skb, skb->len - sizeof(__sum16));
536 }
537
538 /* Packet receive function for Ethernet AVB */
539 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
540 {
541 struct ravb_private *priv = netdev_priv(ndev);
542 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
543 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
544 priv->cur_rx[q];
545 struct net_device_stats *stats = &priv->stats[q];
546 struct ravb_ex_rx_desc *desc;
547 struct sk_buff *skb;
548 dma_addr_t dma_addr;
549 struct timespec64 ts;
550 u8 desc_status;
551 u16 pkt_len;
552 int limit;
553
554 boguscnt = min(boguscnt, *quota);
555 limit = boguscnt;
556 desc = &priv->rx_ring[q][entry];
557 while (desc->die_dt != DT_FEMPTY) {
558 /* Descriptor type must be checked before all other reads */
559 dma_rmb();
560 desc_status = desc->msc;
561 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
562
563 if (--boguscnt < 0)
564 break;
565
566 /* We use 0-byte descriptors to mark the DMA mapping errors */
567 if (!pkt_len)
568 continue;
569
570 if (desc_status & MSC_MC)
571 stats->multicast++;
572
573 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
574 MSC_CEEF)) {
575 stats->rx_errors++;
576 if (desc_status & MSC_CRC)
577 stats->rx_crc_errors++;
578 if (desc_status & MSC_RFE)
579 stats->rx_frame_errors++;
580 if (desc_status & (MSC_RTLF | MSC_RTSF))
581 stats->rx_length_errors++;
582 if (desc_status & MSC_CEEF)
583 stats->rx_missed_errors++;
584 } else {
585 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
586
587 skb = priv->rx_skb[q][entry];
588 priv->rx_skb[q][entry] = NULL;
589 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
590 priv->rx_buf_sz,
591 DMA_FROM_DEVICE);
592 get_ts &= (q == RAVB_NC) ?
593 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
594 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
595 if (get_ts) {
596 struct skb_shared_hwtstamps *shhwtstamps;
597
598 shhwtstamps = skb_hwtstamps(skb);
599 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
600 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
601 32) | le32_to_cpu(desc->ts_sl);
602 ts.tv_nsec = le32_to_cpu(desc->ts_n);
603 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
604 }
605
606 skb_put(skb, pkt_len);
607 skb->protocol = eth_type_trans(skb, ndev);
608 if (ndev->features & NETIF_F_RXCSUM)
609 ravb_rx_csum(skb);
610 napi_gro_receive(&priv->napi[q], skb);
611 stats->rx_packets++;
612 stats->rx_bytes += pkt_len;
613 }
614
615 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
616 desc = &priv->rx_ring[q][entry];
617 }
618
619 /* Refill the RX ring buffers. */
620 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
621 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
622 desc = &priv->rx_ring[q][entry];
623 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
624
625 if (!priv->rx_skb[q][entry]) {
626 skb = netdev_alloc_skb(ndev,
627 priv->rx_buf_sz +
628 RAVB_ALIGN - 1);
629 if (!skb)
630 break; /* Better luck next round. */
631 ravb_set_buffer_align(skb);
632 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
633 le16_to_cpu(desc->ds_cc),
634 DMA_FROM_DEVICE);
635 skb_checksum_none_assert(skb);
636 /* We just set the data size to 0 for a failed mapping
637 * which should prevent DMA from happening...
638 */
639 if (dma_mapping_error(ndev->dev.parent, dma_addr))
640 desc->ds_cc = cpu_to_le16(0);
641 desc->dptr = cpu_to_le32(dma_addr);
642 priv->rx_skb[q][entry] = skb;
643 }
644 /* Descriptor type must be set after all the above writes */
645 dma_wmb();
646 desc->die_dt = DT_FEMPTY;
647 }
648
649 *quota -= limit - (++boguscnt);
650
651 return boguscnt <= 0;
652 }
653
654 static void ravb_rcv_snd_disable(struct net_device *ndev)
655 {
656 /* Disable TX and RX */
657 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
658 }
659
660 static void ravb_rcv_snd_enable(struct net_device *ndev)
661 {
662 /* Enable TX and RX */
663 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
664 }
665
666 /* function for waiting dma process finished */
667 static int ravb_stop_dma(struct net_device *ndev)
668 {
669 int error;
670
671 /* Wait for stopping the hardware TX process */
672 error = ravb_wait(ndev, TCCR,
673 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
674 if (error)
675 return error;
676
677 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
678 0);
679 if (error)
680 return error;
681
682 /* Stop the E-MAC's RX/TX processes. */
683 ravb_rcv_snd_disable(ndev);
684
685 /* Wait for stopping the RX DMA process */
686 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
687 if (error)
688 return error;
689
690 /* Stop AVB-DMAC process */
691 return ravb_config(ndev);
692 }
693
694 /* E-MAC interrupt handler */
695 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
696 {
697 struct ravb_private *priv = netdev_priv(ndev);
698 u32 ecsr, psr;
699
700 ecsr = ravb_read(ndev, ECSR);
701 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
702
703 if (ecsr & ECSR_MPD)
704 pm_wakeup_event(&priv->pdev->dev, 0);
705 if (ecsr & ECSR_ICD)
706 ndev->stats.tx_carrier_errors++;
707 if (ecsr & ECSR_LCHNG) {
708 /* Link changed */
709 if (priv->no_avb_link)
710 return;
711 psr = ravb_read(ndev, PSR);
712 if (priv->avb_link_active_low)
713 psr ^= PSR_LMON;
714 if (!(psr & PSR_LMON)) {
715 /* DIsable RX and TX */
716 ravb_rcv_snd_disable(ndev);
717 } else {
718 /* Enable RX and TX */
719 ravb_rcv_snd_enable(ndev);
720 }
721 }
722 }
723
724 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
725 {
726 struct net_device *ndev = dev_id;
727 struct ravb_private *priv = netdev_priv(ndev);
728
729 spin_lock(&priv->lock);
730 ravb_emac_interrupt_unlocked(ndev);
731 spin_unlock(&priv->lock);
732 return IRQ_HANDLED;
733 }
734
735 /* Error interrupt handler */
736 static void ravb_error_interrupt(struct net_device *ndev)
737 {
738 struct ravb_private *priv = netdev_priv(ndev);
739 u32 eis, ris2;
740
741 eis = ravb_read(ndev, EIS);
742 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
743 if (eis & EIS_QFS) {
744 ris2 = ravb_read(ndev, RIS2);
745 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),
746 RIS2);
747
748 /* Receive Descriptor Empty int */
749 if (ris2 & RIS2_QFF0)
750 priv->stats[RAVB_BE].rx_over_errors++;
751
752 /* Receive Descriptor Empty int */
753 if (ris2 & RIS2_QFF1)
754 priv->stats[RAVB_NC].rx_over_errors++;
755
756 /* Receive FIFO Overflow int */
757 if (ris2 & RIS2_RFFF)
758 priv->rx_fifo_errors++;
759 }
760 }
761
762 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
763 {
764 struct ravb_private *priv = netdev_priv(ndev);
765 u32 ris0 = ravb_read(ndev, RIS0);
766 u32 ric0 = ravb_read(ndev, RIC0);
767 u32 tis = ravb_read(ndev, TIS);
768 u32 tic = ravb_read(ndev, TIC);
769
770 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
771 if (napi_schedule_prep(&priv->napi[q])) {
772 /* Mask RX and TX interrupts */
773 if (priv->chip_id == RCAR_GEN2) {
774 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
775 ravb_write(ndev, tic & ~BIT(q), TIC);
776 } else {
777 ravb_write(ndev, BIT(q), RID0);
778 ravb_write(ndev, BIT(q), TID);
779 }
780 __napi_schedule(&priv->napi[q]);
781 } else {
782 netdev_warn(ndev,
783 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
784 ris0, ric0);
785 netdev_warn(ndev,
786 " tx status 0x%08x, tx mask 0x%08x.\n",
787 tis, tic);
788 }
789 return true;
790 }
791 return false;
792 }
793
794 static bool ravb_timestamp_interrupt(struct net_device *ndev)
795 {
796 u32 tis = ravb_read(ndev, TIS);
797
798 if (tis & TIS_TFUF) {
799 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
800 ravb_get_tx_tstamp(ndev);
801 return true;
802 }
803 return false;
804 }
805
806 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
807 {
808 struct net_device *ndev = dev_id;
809 struct ravb_private *priv = netdev_priv(ndev);
810 irqreturn_t result = IRQ_NONE;
811 u32 iss;
812
813 spin_lock(&priv->lock);
814 /* Get interrupt status */
815 iss = ravb_read(ndev, ISS);
816
817 /* Received and transmitted interrupts */
818 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
819 int q;
820
821 /* Timestamp updated */
822 if (ravb_timestamp_interrupt(ndev))
823 result = IRQ_HANDLED;
824
825 /* Network control and best effort queue RX/TX */
826 for (q = RAVB_NC; q >= RAVB_BE; q--) {
827 if (ravb_queue_interrupt(ndev, q))
828 result = IRQ_HANDLED;
829 }
830 }
831
832 /* E-MAC status summary */
833 if (iss & ISS_MS) {
834 ravb_emac_interrupt_unlocked(ndev);
835 result = IRQ_HANDLED;
836 }
837
838 /* Error status summary */
839 if (iss & ISS_ES) {
840 ravb_error_interrupt(ndev);
841 result = IRQ_HANDLED;
842 }
843
844 /* gPTP interrupt status summary */
845 if (iss & ISS_CGIS) {
846 ravb_ptp_interrupt(ndev);
847 result = IRQ_HANDLED;
848 }
849
850 spin_unlock(&priv->lock);
851 return result;
852 }
853
854 /* Timestamp/Error/gPTP interrupt handler */
855 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
856 {
857 struct net_device *ndev = dev_id;
858 struct ravb_private *priv = netdev_priv(ndev);
859 irqreturn_t result = IRQ_NONE;
860 u32 iss;
861
862 spin_lock(&priv->lock);
863 /* Get interrupt status */
864 iss = ravb_read(ndev, ISS);
865
866 /* Timestamp updated */
867 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
868 result = IRQ_HANDLED;
869
870 /* Error status summary */
871 if (iss & ISS_ES) {
872 ravb_error_interrupt(ndev);
873 result = IRQ_HANDLED;
874 }
875
876 /* gPTP interrupt status summary */
877 if (iss & ISS_CGIS) {
878 ravb_ptp_interrupt(ndev);
879 result = IRQ_HANDLED;
880 }
881
882 spin_unlock(&priv->lock);
883 return result;
884 }
885
886 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
887 {
888 struct net_device *ndev = dev_id;
889 struct ravb_private *priv = netdev_priv(ndev);
890 irqreturn_t result = IRQ_NONE;
891
892 spin_lock(&priv->lock);
893
894 /* Network control/Best effort queue RX/TX */
895 if (ravb_queue_interrupt(ndev, q))
896 result = IRQ_HANDLED;
897
898 spin_unlock(&priv->lock);
899 return result;
900 }
901
902 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
903 {
904 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
905 }
906
907 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
908 {
909 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
910 }
911
912 static int ravb_poll(struct napi_struct *napi, int budget)
913 {
914 struct net_device *ndev = napi->dev;
915 struct ravb_private *priv = netdev_priv(ndev);
916 unsigned long flags;
917 int q = napi - priv->napi;
918 int mask = BIT(q);
919 int quota = budget;
920 u32 ris0, tis;
921
922 for (;;) {
923 tis = ravb_read(ndev, TIS);
924 ris0 = ravb_read(ndev, RIS0);
925 if (!((ris0 & mask) || (tis & mask)))
926 break;
927
928 /* Processing RX Descriptor Ring */
929 if (ris0 & mask) {
930 /* Clear RX interrupt */
931 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
932 if (ravb_rx(ndev, &quota, q))
933 goto out;
934 }
935 /* Processing TX Descriptor Ring */
936 if (tis & mask) {
937 spin_lock_irqsave(&priv->lock, flags);
938 /* Clear TX interrupt */
939 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
940 ravb_tx_free(ndev, q, true);
941 netif_wake_subqueue(ndev, q);
942 spin_unlock_irqrestore(&priv->lock, flags);
943 }
944 }
945
946 napi_complete(napi);
947
948 /* Re-enable RX/TX interrupts */
949 spin_lock_irqsave(&priv->lock, flags);
950 if (priv->chip_id == RCAR_GEN2) {
951 ravb_modify(ndev, RIC0, mask, mask);
952 ravb_modify(ndev, TIC, mask, mask);
953 } else {
954 ravb_write(ndev, mask, RIE0);
955 ravb_write(ndev, mask, TIE);
956 }
957 spin_unlock_irqrestore(&priv->lock, flags);
958
959 /* Receive error message handling */
960 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
961 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
962 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
963 ndev->stats.rx_over_errors = priv->rx_over_errors;
964 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
965 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
966 out:
967 return budget - quota;
968 }
969
970 /* PHY state control function */
971 static void ravb_adjust_link(struct net_device *ndev)
972 {
973 struct ravb_private *priv = netdev_priv(ndev);
974 struct phy_device *phydev = ndev->phydev;
975 bool new_state = false;
976 unsigned long flags;
977
978 spin_lock_irqsave(&priv->lock, flags);
979
980 /* Disable TX and RX right over here, if E-MAC change is ignored */
981 if (priv->no_avb_link)
982 ravb_rcv_snd_disable(ndev);
983
984 if (phydev->link) {
985 if (phydev->speed != priv->speed) {
986 new_state = true;
987 priv->speed = phydev->speed;
988 ravb_set_rate(ndev);
989 }
990 if (!priv->link) {
991 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
992 new_state = true;
993 priv->link = phydev->link;
994 }
995 } else if (priv->link) {
996 new_state = true;
997 priv->link = 0;
998 priv->speed = 0;
999 }
1000
1001 /* Enable TX and RX right over here, if E-MAC change is ignored */
1002 if (priv->no_avb_link && phydev->link)
1003 ravb_rcv_snd_enable(ndev);
1004
1005 spin_unlock_irqrestore(&priv->lock, flags);
1006
1007 if (new_state && netif_msg_link(priv))
1008 phy_print_status(phydev);
1009 }
1010
1011 static const struct soc_device_attribute r8a7795es10[] = {
1012 { .soc_id = "r8a7795", .revision = "ES1.0", },
1013 { /* sentinel */ }
1014 };
1015
1016 /* PHY init function */
1017 static int ravb_phy_init(struct net_device *ndev)
1018 {
1019 struct device_node *np = ndev->dev.parent->of_node;
1020 struct ravb_private *priv = netdev_priv(ndev);
1021 struct phy_device *phydev;
1022 struct device_node *pn;
1023 int err;
1024
1025 priv->link = 0;
1026 priv->speed = 0;
1027
1028 /* Try connecting to PHY */
1029 pn = of_parse_phandle(np, "phy-handle", 0);
1030 if (!pn) {
1031 /* In the case of a fixed PHY, the DT node associated
1032 * to the PHY is the Ethernet MAC DT node.
1033 */
1034 if (of_phy_is_fixed_link(np)) {
1035 err = of_phy_register_fixed_link(np);
1036 if (err)
1037 return err;
1038 }
1039 pn = of_node_get(np);
1040 }
1041 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1042 priv->phy_interface);
1043 of_node_put(pn);
1044 if (!phydev) {
1045 netdev_err(ndev, "failed to connect PHY\n");
1046 err = -ENOENT;
1047 goto err_deregister_fixed_link;
1048 }
1049
1050 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1051 * at this time.
1052 */
1053 if (soc_device_match(r8a7795es10)) {
1054 err = phy_set_max_speed(phydev, SPEED_100);
1055 if (err) {
1056 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1057 goto err_phy_disconnect;
1058 }
1059
1060 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1061 }
1062
1063 /* 10BASE, Pause and Asym Pause is not supported */
1064 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1065 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1066 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1067 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1068
1069 /* Half Duplex is not supported */
1070 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1071 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1072
1073 phy_attached_info(phydev);
1074
1075 return 0;
1076
1077 err_phy_disconnect:
1078 phy_disconnect(phydev);
1079 err_deregister_fixed_link:
1080 if (of_phy_is_fixed_link(np))
1081 of_phy_deregister_fixed_link(np);
1082
1083 return err;
1084 }
1085
1086 /* PHY control start function */
1087 static int ravb_phy_start(struct net_device *ndev)
1088 {
1089 int error;
1090
1091 error = ravb_phy_init(ndev);
1092 if (error)
1093 return error;
1094
1095 phy_start(ndev->phydev);
1096
1097 return 0;
1098 }
1099
1100 static u32 ravb_get_msglevel(struct net_device *ndev)
1101 {
1102 struct ravb_private *priv = netdev_priv(ndev);
1103
1104 return priv->msg_enable;
1105 }
1106
1107 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1108 {
1109 struct ravb_private *priv = netdev_priv(ndev);
1110
1111 priv->msg_enable = value;
1112 }
1113
1114 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1115 "rx_queue_0_current",
1116 "tx_queue_0_current",
1117 "rx_queue_0_dirty",
1118 "tx_queue_0_dirty",
1119 "rx_queue_0_packets",
1120 "tx_queue_0_packets",
1121 "rx_queue_0_bytes",
1122 "tx_queue_0_bytes",
1123 "rx_queue_0_mcast_packets",
1124 "rx_queue_0_errors",
1125 "rx_queue_0_crc_errors",
1126 "rx_queue_0_frame_errors",
1127 "rx_queue_0_length_errors",
1128 "rx_queue_0_missed_errors",
1129 "rx_queue_0_over_errors",
1130
1131 "rx_queue_1_current",
1132 "tx_queue_1_current",
1133 "rx_queue_1_dirty",
1134 "tx_queue_1_dirty",
1135 "rx_queue_1_packets",
1136 "tx_queue_1_packets",
1137 "rx_queue_1_bytes",
1138 "tx_queue_1_bytes",
1139 "rx_queue_1_mcast_packets",
1140 "rx_queue_1_errors",
1141 "rx_queue_1_crc_errors",
1142 "rx_queue_1_frame_errors",
1143 "rx_queue_1_length_errors",
1144 "rx_queue_1_missed_errors",
1145 "rx_queue_1_over_errors",
1146 };
1147
1148 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1149
1150 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1151 {
1152 switch (sset) {
1153 case ETH_SS_STATS:
1154 return RAVB_STATS_LEN;
1155 default:
1156 return -EOPNOTSUPP;
1157 }
1158 }
1159
1160 static void ravb_get_ethtool_stats(struct net_device *ndev,
1161 struct ethtool_stats *estats, u64 *data)
1162 {
1163 struct ravb_private *priv = netdev_priv(ndev);
1164 int i = 0;
1165 int q;
1166
1167 /* Device-specific stats */
1168 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1169 struct net_device_stats *stats = &priv->stats[q];
1170
1171 data[i++] = priv->cur_rx[q];
1172 data[i++] = priv->cur_tx[q];
1173 data[i++] = priv->dirty_rx[q];
1174 data[i++] = priv->dirty_tx[q];
1175 data[i++] = stats->rx_packets;
1176 data[i++] = stats->tx_packets;
1177 data[i++] = stats->rx_bytes;
1178 data[i++] = stats->tx_bytes;
1179 data[i++] = stats->multicast;
1180 data[i++] = stats->rx_errors;
1181 data[i++] = stats->rx_crc_errors;
1182 data[i++] = stats->rx_frame_errors;
1183 data[i++] = stats->rx_length_errors;
1184 data[i++] = stats->rx_missed_errors;
1185 data[i++] = stats->rx_over_errors;
1186 }
1187 }
1188
1189 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1190 {
1191 switch (stringset) {
1192 case ETH_SS_STATS:
1193 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1194 break;
1195 }
1196 }
1197
1198 static void ravb_get_ringparam(struct net_device *ndev,
1199 struct ethtool_ringparam *ring)
1200 {
1201 struct ravb_private *priv = netdev_priv(ndev);
1202
1203 ring->rx_max_pending = BE_RX_RING_MAX;
1204 ring->tx_max_pending = BE_TX_RING_MAX;
1205 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1206 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1207 }
1208
1209 static int ravb_set_ringparam(struct net_device *ndev,
1210 struct ethtool_ringparam *ring)
1211 {
1212 struct ravb_private *priv = netdev_priv(ndev);
1213 int error;
1214
1215 if (ring->tx_pending > BE_TX_RING_MAX ||
1216 ring->rx_pending > BE_RX_RING_MAX ||
1217 ring->tx_pending < BE_TX_RING_MIN ||
1218 ring->rx_pending < BE_RX_RING_MIN)
1219 return -EINVAL;
1220 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1221 return -EINVAL;
1222
1223 if (netif_running(ndev)) {
1224 netif_device_detach(ndev);
1225 /* Stop PTP Clock driver */
1226 if (priv->chip_id == RCAR_GEN2)
1227 ravb_ptp_stop(ndev);
1228 /* Wait for DMA stopping */
1229 error = ravb_stop_dma(ndev);
1230 if (error) {
1231 netdev_err(ndev,
1232 "cannot set ringparam! Any AVB processes are still running?\n");
1233 return error;
1234 }
1235 synchronize_irq(ndev->irq);
1236
1237 /* Free all the skb's in the RX queue and the DMA buffers. */
1238 ravb_ring_free(ndev, RAVB_BE);
1239 ravb_ring_free(ndev, RAVB_NC);
1240 }
1241
1242 /* Set new parameters */
1243 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1244 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1245
1246 if (netif_running(ndev)) {
1247 error = ravb_dmac_init(ndev);
1248 if (error) {
1249 netdev_err(ndev,
1250 "%s: ravb_dmac_init() failed, error %d\n",
1251 __func__, error);
1252 return error;
1253 }
1254
1255 ravb_emac_init(ndev);
1256
1257 /* Initialise PTP Clock driver */
1258 if (priv->chip_id == RCAR_GEN2)
1259 ravb_ptp_init(ndev, priv->pdev);
1260
1261 netif_device_attach(ndev);
1262 }
1263
1264 return 0;
1265 }
1266
1267 static int ravb_get_ts_info(struct net_device *ndev,
1268 struct ethtool_ts_info *info)
1269 {
1270 struct ravb_private *priv = netdev_priv(ndev);
1271
1272 info->so_timestamping =
1273 SOF_TIMESTAMPING_TX_SOFTWARE |
1274 SOF_TIMESTAMPING_RX_SOFTWARE |
1275 SOF_TIMESTAMPING_SOFTWARE |
1276 SOF_TIMESTAMPING_TX_HARDWARE |
1277 SOF_TIMESTAMPING_RX_HARDWARE |
1278 SOF_TIMESTAMPING_RAW_HARDWARE;
1279 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1280 info->rx_filters =
1281 (1 << HWTSTAMP_FILTER_NONE) |
1282 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1283 (1 << HWTSTAMP_FILTER_ALL);
1284 info->phc_index = ptp_clock_index(priv->ptp.clock);
1285
1286 return 0;
1287 }
1288
1289 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1290 {
1291 struct ravb_private *priv = netdev_priv(ndev);
1292
1293 wol->supported = WAKE_MAGIC;
1294 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1295 }
1296
1297 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1298 {
1299 struct ravb_private *priv = netdev_priv(ndev);
1300
1301 if (wol->wolopts & ~WAKE_MAGIC)
1302 return -EOPNOTSUPP;
1303
1304 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1305
1306 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1307
1308 return 0;
1309 }
1310
1311 static const struct ethtool_ops ravb_ethtool_ops = {
1312 .nway_reset = phy_ethtool_nway_reset,
1313 .get_msglevel = ravb_get_msglevel,
1314 .set_msglevel = ravb_set_msglevel,
1315 .get_link = ethtool_op_get_link,
1316 .get_strings = ravb_get_strings,
1317 .get_ethtool_stats = ravb_get_ethtool_stats,
1318 .get_sset_count = ravb_get_sset_count,
1319 .get_ringparam = ravb_get_ringparam,
1320 .set_ringparam = ravb_set_ringparam,
1321 .get_ts_info = ravb_get_ts_info,
1322 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1323 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1324 .get_wol = ravb_get_wol,
1325 .set_wol = ravb_set_wol,
1326 };
1327
1328 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1329 struct net_device *ndev, struct device *dev,
1330 const char *ch)
1331 {
1332 char *name;
1333 int error;
1334
1335 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1336 if (!name)
1337 return -ENOMEM;
1338 error = request_irq(irq, handler, 0, name, ndev);
1339 if (error)
1340 netdev_err(ndev, "cannot request IRQ %s\n", name);
1341
1342 return error;
1343 }
1344
1345 /* Network device open function for Ethernet AVB */
1346 static int ravb_open(struct net_device *ndev)
1347 {
1348 struct ravb_private *priv = netdev_priv(ndev);
1349 struct platform_device *pdev = priv->pdev;
1350 struct device *dev = &pdev->dev;
1351 int error;
1352
1353 napi_enable(&priv->napi[RAVB_BE]);
1354 napi_enable(&priv->napi[RAVB_NC]);
1355
1356 if (priv->chip_id == RCAR_GEN2) {
1357 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1358 ndev->name, ndev);
1359 if (error) {
1360 netdev_err(ndev, "cannot request IRQ\n");
1361 goto out_napi_off;
1362 }
1363 } else {
1364 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1365 dev, "ch22:multi");
1366 if (error)
1367 goto out_napi_off;
1368 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1369 dev, "ch24:emac");
1370 if (error)
1371 goto out_free_irq;
1372 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1373 ndev, dev, "ch0:rx_be");
1374 if (error)
1375 goto out_free_irq_emac;
1376 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1377 ndev, dev, "ch18:tx_be");
1378 if (error)
1379 goto out_free_irq_be_rx;
1380 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1381 ndev, dev, "ch1:rx_nc");
1382 if (error)
1383 goto out_free_irq_be_tx;
1384 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1385 ndev, dev, "ch19:tx_nc");
1386 if (error)
1387 goto out_free_irq_nc_rx;
1388 }
1389
1390 /* Device init */
1391 error = ravb_dmac_init(ndev);
1392 if (error)
1393 goto out_free_irq_nc_tx;
1394 ravb_emac_init(ndev);
1395
1396 /* Initialise PTP Clock driver */
1397 if (priv->chip_id == RCAR_GEN2)
1398 ravb_ptp_init(ndev, priv->pdev);
1399
1400 netif_tx_start_all_queues(ndev);
1401
1402 /* PHY control start */
1403 error = ravb_phy_start(ndev);
1404 if (error)
1405 goto out_ptp_stop;
1406
1407 return 0;
1408
1409 out_ptp_stop:
1410 /* Stop PTP Clock driver */
1411 if (priv->chip_id == RCAR_GEN2)
1412 ravb_ptp_stop(ndev);
1413 out_free_irq_nc_tx:
1414 if (priv->chip_id == RCAR_GEN2)
1415 goto out_free_irq;
1416 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1417 out_free_irq_nc_rx:
1418 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1419 out_free_irq_be_tx:
1420 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1421 out_free_irq_be_rx:
1422 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1423 out_free_irq_emac:
1424 free_irq(priv->emac_irq, ndev);
1425 out_free_irq:
1426 free_irq(ndev->irq, ndev);
1427 out_napi_off:
1428 napi_disable(&priv->napi[RAVB_NC]);
1429 napi_disable(&priv->napi[RAVB_BE]);
1430 return error;
1431 }
1432
1433 /* Timeout function for Ethernet AVB */
1434 static void ravb_tx_timeout(struct net_device *ndev)
1435 {
1436 struct ravb_private *priv = netdev_priv(ndev);
1437
1438 netif_err(priv, tx_err, ndev,
1439 "transmit timed out, status %08x, resetting...\n",
1440 ravb_read(ndev, ISS));
1441
1442 /* tx_errors count up */
1443 ndev->stats.tx_errors++;
1444
1445 schedule_work(&priv->work);
1446 }
1447
1448 static void ravb_tx_timeout_work(struct work_struct *work)
1449 {
1450 struct ravb_private *priv = container_of(work, struct ravb_private,
1451 work);
1452 struct net_device *ndev = priv->ndev;
1453
1454 netif_tx_stop_all_queues(ndev);
1455
1456 /* Stop PTP Clock driver */
1457 if (priv->chip_id == RCAR_GEN2)
1458 ravb_ptp_stop(ndev);
1459
1460 /* Wait for DMA stopping */
1461 ravb_stop_dma(ndev);
1462
1463 ravb_ring_free(ndev, RAVB_BE);
1464 ravb_ring_free(ndev, RAVB_NC);
1465
1466 /* Device init */
1467 ravb_dmac_init(ndev);
1468 ravb_emac_init(ndev);
1469
1470 /* Initialise PTP Clock driver */
1471 if (priv->chip_id == RCAR_GEN2)
1472 ravb_ptp_init(ndev, priv->pdev);
1473
1474 netif_tx_start_all_queues(ndev);
1475 }
1476
1477 /* Packet transmit function for Ethernet AVB */
1478 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1479 {
1480 struct ravb_private *priv = netdev_priv(ndev);
1481 int num_tx_desc = priv->num_tx_desc;
1482 u16 q = skb_get_queue_mapping(skb);
1483 struct ravb_tstamp_skb *ts_skb;
1484 struct ravb_tx_desc *desc;
1485 unsigned long flags;
1486 u32 dma_addr;
1487 void *buffer;
1488 u32 entry;
1489 u32 len;
1490
1491 spin_lock_irqsave(&priv->lock, flags);
1492 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1493 num_tx_desc) {
1494 netif_err(priv, tx_queued, ndev,
1495 "still transmitting with the full ring!\n");
1496 netif_stop_subqueue(ndev, q);
1497 spin_unlock_irqrestore(&priv->lock, flags);
1498 return NETDEV_TX_BUSY;
1499 }
1500
1501 if (skb_put_padto(skb, ETH_ZLEN))
1502 goto exit;
1503
1504 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1505 priv->tx_skb[q][entry / num_tx_desc] = skb;
1506
1507 if (num_tx_desc > 1) {
1508 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1509 entry / num_tx_desc * DPTR_ALIGN;
1510 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1511
1512 /* Zero length DMA descriptors are problematic as they seem
1513 * to terminate DMA transfers. Avoid them by simply using a
1514 * length of DPTR_ALIGN (4) when skb data is aligned to
1515 * DPTR_ALIGN.
1516 *
1517 * As skb is guaranteed to have at least ETH_ZLEN (60)
1518 * bytes of data by the call to skb_put_padto() above this
1519 * is safe with respect to both the length of the first DMA
1520 * descriptor (len) overflowing the available data and the
1521 * length of the second DMA descriptor (skb->len - len)
1522 * being negative.
1523 */
1524 if (len == 0)
1525 len = DPTR_ALIGN;
1526
1527 memcpy(buffer, skb->data, len);
1528 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1529 DMA_TO_DEVICE);
1530 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1531 goto drop;
1532
1533 desc = &priv->tx_ring[q][entry];
1534 desc->ds_tagl = cpu_to_le16(len);
1535 desc->dptr = cpu_to_le32(dma_addr);
1536
1537 buffer = skb->data + len;
1538 len = skb->len - len;
1539 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1540 DMA_TO_DEVICE);
1541 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1542 goto unmap;
1543
1544 desc++;
1545 } else {
1546 desc = &priv->tx_ring[q][entry];
1547 len = skb->len;
1548 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
1549 DMA_TO_DEVICE);
1550 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1551 goto drop;
1552 }
1553 desc->ds_tagl = cpu_to_le16(len);
1554 desc->dptr = cpu_to_le32(dma_addr);
1555
1556 /* TX timestamp required */
1557 if (q == RAVB_NC) {
1558 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1559 if (!ts_skb) {
1560 if (num_tx_desc > 1) {
1561 desc--;
1562 dma_unmap_single(ndev->dev.parent, dma_addr,
1563 len, DMA_TO_DEVICE);
1564 }
1565 goto unmap;
1566 }
1567 ts_skb->skb = skb;
1568 ts_skb->tag = priv->ts_skb_tag++;
1569 priv->ts_skb_tag &= 0x3ff;
1570 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1571
1572 /* TAG and timestamp required flag */
1573 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1574 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1575 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
1576 }
1577
1578 skb_tx_timestamp(skb);
1579 /* Descriptor type must be set after all the above writes */
1580 dma_wmb();
1581 if (num_tx_desc > 1) {
1582 desc->die_dt = DT_FEND;
1583 desc--;
1584 desc->die_dt = DT_FSTART;
1585 } else {
1586 desc->die_dt = DT_FSINGLE;
1587 }
1588 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1589
1590 priv->cur_tx[q] += num_tx_desc;
1591 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1592 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
1593 !ravb_tx_free(ndev, q, true))
1594 netif_stop_subqueue(ndev, q);
1595
1596 exit:
1597 spin_unlock_irqrestore(&priv->lock, flags);
1598 return NETDEV_TX_OK;
1599
1600 unmap:
1601 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1602 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1603 drop:
1604 dev_kfree_skb_any(skb);
1605 priv->tx_skb[q][entry / num_tx_desc] = NULL;
1606 goto exit;
1607 }
1608
1609 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1610 struct net_device *sb_dev)
1611 {
1612 /* If skb needs TX timestamp, it is handled in network control queue */
1613 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1614 RAVB_BE;
1615
1616 }
1617
1618 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1619 {
1620 struct ravb_private *priv = netdev_priv(ndev);
1621 struct net_device_stats *nstats, *stats0, *stats1;
1622
1623 nstats = &ndev->stats;
1624 stats0 = &priv->stats[RAVB_BE];
1625 stats1 = &priv->stats[RAVB_NC];
1626
1627 nstats->tx_dropped += ravb_read(ndev, TROCR);
1628 ravb_write(ndev, 0, TROCR); /* (write clear) */
1629 nstats->collisions += ravb_read(ndev, CDCR);
1630 ravb_write(ndev, 0, CDCR); /* (write clear) */
1631 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1632 ravb_write(ndev, 0, LCCR); /* (write clear) */
1633
1634 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1635 ravb_write(ndev, 0, CERCR); /* (write clear) */
1636 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1637 ravb_write(ndev, 0, CEECR); /* (write clear) */
1638
1639 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1640 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1641 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1642 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1643 nstats->multicast = stats0->multicast + stats1->multicast;
1644 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1645 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1646 nstats->rx_frame_errors =
1647 stats0->rx_frame_errors + stats1->rx_frame_errors;
1648 nstats->rx_length_errors =
1649 stats0->rx_length_errors + stats1->rx_length_errors;
1650 nstats->rx_missed_errors =
1651 stats0->rx_missed_errors + stats1->rx_missed_errors;
1652 nstats->rx_over_errors =
1653 stats0->rx_over_errors + stats1->rx_over_errors;
1654
1655 return nstats;
1656 }
1657
1658 /* Update promiscuous bit */
1659 static void ravb_set_rx_mode(struct net_device *ndev)
1660 {
1661 struct ravb_private *priv = netdev_priv(ndev);
1662 unsigned long flags;
1663
1664 spin_lock_irqsave(&priv->lock, flags);
1665 ravb_modify(ndev, ECMR, ECMR_PRM,
1666 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1667 spin_unlock_irqrestore(&priv->lock, flags);
1668 }
1669
1670 /* Device close function for Ethernet AVB */
1671 static int ravb_close(struct net_device *ndev)
1672 {
1673 struct device_node *np = ndev->dev.parent->of_node;
1674 struct ravb_private *priv = netdev_priv(ndev);
1675 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1676
1677 netif_tx_stop_all_queues(ndev);
1678
1679 /* Disable interrupts by clearing the interrupt masks. */
1680 ravb_write(ndev, 0, RIC0);
1681 ravb_write(ndev, 0, RIC2);
1682 ravb_write(ndev, 0, TIC);
1683
1684 /* Stop PTP Clock driver */
1685 if (priv->chip_id == RCAR_GEN2)
1686 ravb_ptp_stop(ndev);
1687
1688 /* Set the config mode to stop the AVB-DMAC's processes */
1689 if (ravb_stop_dma(ndev) < 0)
1690 netdev_err(ndev,
1691 "device will be stopped after h/w processes are done.\n");
1692
1693 /* Clear the timestamp list */
1694 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1695 list_del(&ts_skb->list);
1696 kfree(ts_skb);
1697 }
1698
1699 /* PHY disconnect */
1700 if (ndev->phydev) {
1701 phy_stop(ndev->phydev);
1702 phy_disconnect(ndev->phydev);
1703 if (of_phy_is_fixed_link(np))
1704 of_phy_deregister_fixed_link(np);
1705 }
1706
1707 if (priv->chip_id != RCAR_GEN2) {
1708 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1709 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1710 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1711 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1712 free_irq(priv->emac_irq, ndev);
1713 }
1714 free_irq(ndev->irq, ndev);
1715
1716 napi_disable(&priv->napi[RAVB_NC]);
1717 napi_disable(&priv->napi[RAVB_BE]);
1718
1719 /* Free all the skb's in the RX queue and the DMA buffers. */
1720 ravb_ring_free(ndev, RAVB_BE);
1721 ravb_ring_free(ndev, RAVB_NC);
1722
1723 return 0;
1724 }
1725
1726 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1727 {
1728 struct ravb_private *priv = netdev_priv(ndev);
1729 struct hwtstamp_config config;
1730
1731 config.flags = 0;
1732 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1733 HWTSTAMP_TX_OFF;
1734 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1735 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1736 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1737 config.rx_filter = HWTSTAMP_FILTER_ALL;
1738 else
1739 config.rx_filter = HWTSTAMP_FILTER_NONE;
1740
1741 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1742 -EFAULT : 0;
1743 }
1744
1745 /* Control hardware time stamping */
1746 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1747 {
1748 struct ravb_private *priv = netdev_priv(ndev);
1749 struct hwtstamp_config config;
1750 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1751 u32 tstamp_tx_ctrl;
1752
1753 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1754 return -EFAULT;
1755
1756 /* Reserved for future extensions */
1757 if (config.flags)
1758 return -EINVAL;
1759
1760 switch (config.tx_type) {
1761 case HWTSTAMP_TX_OFF:
1762 tstamp_tx_ctrl = 0;
1763 break;
1764 case HWTSTAMP_TX_ON:
1765 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1766 break;
1767 default:
1768 return -ERANGE;
1769 }
1770
1771 switch (config.rx_filter) {
1772 case HWTSTAMP_FILTER_NONE:
1773 tstamp_rx_ctrl = 0;
1774 break;
1775 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1776 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1777 break;
1778 default:
1779 config.rx_filter = HWTSTAMP_FILTER_ALL;
1780 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1781 }
1782
1783 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1784 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1785
1786 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1787 -EFAULT : 0;
1788 }
1789
1790 /* ioctl to device function */
1791 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1792 {
1793 struct phy_device *phydev = ndev->phydev;
1794
1795 if (!netif_running(ndev))
1796 return -EINVAL;
1797
1798 if (!phydev)
1799 return -ENODEV;
1800
1801 switch (cmd) {
1802 case SIOCGHWTSTAMP:
1803 return ravb_hwtstamp_get(ndev, req);
1804 case SIOCSHWTSTAMP:
1805 return ravb_hwtstamp_set(ndev, req);
1806 }
1807
1808 return phy_mii_ioctl(phydev, req, cmd);
1809 }
1810
1811 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
1812 {
1813 if (netif_running(ndev))
1814 return -EBUSY;
1815
1816 ndev->mtu = new_mtu;
1817 netdev_update_features(ndev);
1818
1819 return 0;
1820 }
1821
1822 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1823 {
1824 struct ravb_private *priv = netdev_priv(ndev);
1825 unsigned long flags;
1826
1827 spin_lock_irqsave(&priv->lock, flags);
1828
1829 /* Disable TX and RX */
1830 ravb_rcv_snd_disable(ndev);
1831
1832 /* Modify RX Checksum setting */
1833 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1834
1835 /* Enable TX and RX */
1836 ravb_rcv_snd_enable(ndev);
1837
1838 spin_unlock_irqrestore(&priv->lock, flags);
1839 }
1840
1841 static int ravb_set_features(struct net_device *ndev,
1842 netdev_features_t features)
1843 {
1844 netdev_features_t changed = ndev->features ^ features;
1845
1846 if (changed & NETIF_F_RXCSUM)
1847 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1848
1849 ndev->features = features;
1850
1851 return 0;
1852 }
1853
1854 static const struct net_device_ops ravb_netdev_ops = {
1855 .ndo_open = ravb_open,
1856 .ndo_stop = ravb_close,
1857 .ndo_start_xmit = ravb_start_xmit,
1858 .ndo_select_queue = ravb_select_queue,
1859 .ndo_get_stats = ravb_get_stats,
1860 .ndo_set_rx_mode = ravb_set_rx_mode,
1861 .ndo_tx_timeout = ravb_tx_timeout,
1862 .ndo_do_ioctl = ravb_do_ioctl,
1863 .ndo_change_mtu = ravb_change_mtu,
1864 .ndo_validate_addr = eth_validate_addr,
1865 .ndo_set_mac_address = eth_mac_addr,
1866 .ndo_set_features = ravb_set_features,
1867 };
1868
1869 /* MDIO bus init function */
1870 static int ravb_mdio_init(struct ravb_private *priv)
1871 {
1872 struct platform_device *pdev = priv->pdev;
1873 struct device *dev = &pdev->dev;
1874 int error;
1875
1876 /* Bitbang init */
1877 priv->mdiobb.ops = &bb_ops;
1878
1879 /* MII controller setting */
1880 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1881 if (!priv->mii_bus)
1882 return -ENOMEM;
1883
1884 /* Hook up MII support for ethtool */
1885 priv->mii_bus->name = "ravb_mii";
1886 priv->mii_bus->parent = dev;
1887 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1888 pdev->name, pdev->id);
1889
1890 /* Register MDIO bus */
1891 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1892 if (error)
1893 goto out_free_bus;
1894
1895 return 0;
1896
1897 out_free_bus:
1898 free_mdio_bitbang(priv->mii_bus);
1899 return error;
1900 }
1901
1902 /* MDIO bus release function */
1903 static int ravb_mdio_release(struct ravb_private *priv)
1904 {
1905 /* Unregister mdio bus */
1906 mdiobus_unregister(priv->mii_bus);
1907
1908 /* Free bitbang info */
1909 free_mdio_bitbang(priv->mii_bus);
1910
1911 return 0;
1912 }
1913
1914 static const struct of_device_id ravb_match_table[] = {
1915 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1916 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1917 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1918 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1919 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1920 { }
1921 };
1922 MODULE_DEVICE_TABLE(of, ravb_match_table);
1923
1924 static int ravb_set_gti(struct net_device *ndev)
1925 {
1926 struct ravb_private *priv = netdev_priv(ndev);
1927 struct device *dev = ndev->dev.parent;
1928 unsigned long rate;
1929 uint64_t inc;
1930
1931 rate = clk_get_rate(priv->clk);
1932 if (!rate)
1933 return -EINVAL;
1934
1935 inc = 1000000000ULL << 20;
1936 do_div(inc, rate);
1937
1938 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1939 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1940 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1941 return -EINVAL;
1942 }
1943
1944 ravb_write(ndev, inc, GTI);
1945
1946 return 0;
1947 }
1948
1949 static void ravb_set_config_mode(struct net_device *ndev)
1950 {
1951 struct ravb_private *priv = netdev_priv(ndev);
1952
1953 if (priv->chip_id == RCAR_GEN2) {
1954 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1955 /* Set CSEL value */
1956 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1957 } else {
1958 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1959 CCC_GAC | CCC_CSEL_HPB);
1960 }
1961 }
1962
1963 static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
1964 { .soc_id = "r8a774c0" },
1965 { .soc_id = "r8a77990" },
1966 { .soc_id = "r8a77995" },
1967 { /* sentinel */ }
1968 };
1969
1970 /* Set tx and rx clock internal delay modes */
1971 static void ravb_set_delay_mode(struct net_device *ndev)
1972 {
1973 struct ravb_private *priv = netdev_priv(ndev);
1974 int set = 0;
1975
1976 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1977 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
1978 set |= APSR_DM_RDM;
1979
1980 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1981 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
1982 if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
1983 "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
1984 phy_modes(priv->phy_interface)))
1985 set |= APSR_DM_TDM;
1986 }
1987
1988 ravb_modify(ndev, APSR, APSR_DM, set);
1989 }
1990
1991 static int ravb_probe(struct platform_device *pdev)
1992 {
1993 struct device_node *np = pdev->dev.of_node;
1994 struct ravb_private *priv;
1995 enum ravb_chip_id chip_id;
1996 struct net_device *ndev;
1997 int error, irq, q;
1998 struct resource *res;
1999 int i;
2000
2001 if (!np) {
2002 dev_err(&pdev->dev,
2003 "this driver is required to be instantiated from device tree\n");
2004 return -EINVAL;
2005 }
2006
2007 /* Get base address */
2008 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2009 if (!res) {
2010 dev_err(&pdev->dev, "invalid resource\n");
2011 return -EINVAL;
2012 }
2013
2014 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2015 NUM_TX_QUEUE, NUM_RX_QUEUE);
2016 if (!ndev)
2017 return -ENOMEM;
2018
2019 ndev->features = NETIF_F_RXCSUM;
2020 ndev->hw_features = NETIF_F_RXCSUM;
2021
2022 pm_runtime_enable(&pdev->dev);
2023 pm_runtime_get_sync(&pdev->dev);
2024
2025 /* The Ether-specific entries in the device structure. */
2026 ndev->base_addr = res->start;
2027
2028 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
2029
2030 if (chip_id == RCAR_GEN3)
2031 irq = platform_get_irq_byname(pdev, "ch22");
2032 else
2033 irq = platform_get_irq(pdev, 0);
2034 if (irq < 0) {
2035 error = irq;
2036 goto out_release;
2037 }
2038 ndev->irq = irq;
2039
2040 SET_NETDEV_DEV(ndev, &pdev->dev);
2041
2042 priv = netdev_priv(ndev);
2043 priv->ndev = ndev;
2044 priv->pdev = pdev;
2045 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2046 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2047 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2048 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2049 priv->addr = devm_ioremap_resource(&pdev->dev, res);
2050 if (IS_ERR(priv->addr)) {
2051 error = PTR_ERR(priv->addr);
2052 goto out_release;
2053 }
2054
2055 spin_lock_init(&priv->lock);
2056 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2057
2058 priv->phy_interface = of_get_phy_mode(np);
2059
2060 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2061 priv->avb_link_active_low =
2062 of_property_read_bool(np, "renesas,ether-link-active-low");
2063
2064 if (chip_id == RCAR_GEN3) {
2065 irq = platform_get_irq_byname(pdev, "ch24");
2066 if (irq < 0) {
2067 error = irq;
2068 goto out_release;
2069 }
2070 priv->emac_irq = irq;
2071 for (i = 0; i < NUM_RX_QUEUE; i++) {
2072 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2073 if (irq < 0) {
2074 error = irq;
2075 goto out_release;
2076 }
2077 priv->rx_irqs[i] = irq;
2078 }
2079 for (i = 0; i < NUM_TX_QUEUE; i++) {
2080 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2081 if (irq < 0) {
2082 error = irq;
2083 goto out_release;
2084 }
2085 priv->tx_irqs[i] = irq;
2086 }
2087 }
2088
2089 priv->chip_id = chip_id;
2090
2091 priv->clk = devm_clk_get(&pdev->dev, NULL);
2092 if (IS_ERR(priv->clk)) {
2093 error = PTR_ERR(priv->clk);
2094 goto out_release;
2095 }
2096
2097 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2098 ndev->min_mtu = ETH_MIN_MTU;
2099
2100 priv->num_tx_desc = chip_id == RCAR_GEN2 ?
2101 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3;
2102
2103 /* Set function */
2104 ndev->netdev_ops = &ravb_netdev_ops;
2105 ndev->ethtool_ops = &ravb_ethtool_ops;
2106
2107 /* Set AVB config mode */
2108 ravb_set_config_mode(ndev);
2109
2110 /* Set GTI value */
2111 error = ravb_set_gti(ndev);
2112 if (error)
2113 goto out_release;
2114
2115 /* Request GTI loading */
2116 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2117
2118 if (priv->chip_id != RCAR_GEN2)
2119 ravb_set_delay_mode(ndev);
2120
2121 /* Allocate descriptor base address table */
2122 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2123 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2124 &priv->desc_bat_dma, GFP_KERNEL);
2125 if (!priv->desc_bat) {
2126 dev_err(&pdev->dev,
2127 "Cannot allocate desc base address table (size %d bytes)\n",
2128 priv->desc_bat_size);
2129 error = -ENOMEM;
2130 goto out_release;
2131 }
2132 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2133 priv->desc_bat[q].die_dt = DT_EOS;
2134 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2135
2136 /* Initialise HW timestamp list */
2137 INIT_LIST_HEAD(&priv->ts_skb_list);
2138
2139 /* Initialise PTP Clock driver */
2140 if (chip_id != RCAR_GEN2)
2141 ravb_ptp_init(ndev, pdev);
2142
2143 /* Debug message level */
2144 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2145
2146 /* Read and set MAC address */
2147 ravb_read_mac_address(ndev, of_get_mac_address(np));
2148 if (!is_valid_ether_addr(ndev->dev_addr)) {
2149 dev_warn(&pdev->dev,
2150 "no valid MAC address supplied, using a random one\n");
2151 eth_hw_addr_random(ndev);
2152 }
2153
2154 /* MDIO bus init */
2155 error = ravb_mdio_init(priv);
2156 if (error) {
2157 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2158 goto out_dma_free;
2159 }
2160
2161 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2162 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2163
2164 /* Network device register */
2165 error = register_netdev(ndev);
2166 if (error)
2167 goto out_napi_del;
2168
2169 device_set_wakeup_capable(&pdev->dev, 1);
2170
2171 /* Print device information */
2172 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2173 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2174
2175 platform_set_drvdata(pdev, ndev);
2176
2177 return 0;
2178
2179 out_napi_del:
2180 netif_napi_del(&priv->napi[RAVB_NC]);
2181 netif_napi_del(&priv->napi[RAVB_BE]);
2182 ravb_mdio_release(priv);
2183 out_dma_free:
2184 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2185 priv->desc_bat_dma);
2186
2187 /* Stop PTP Clock driver */
2188 if (chip_id != RCAR_GEN2)
2189 ravb_ptp_stop(ndev);
2190 out_release:
2191 free_netdev(ndev);
2192
2193 pm_runtime_put(&pdev->dev);
2194 pm_runtime_disable(&pdev->dev);
2195 return error;
2196 }
2197
2198 static int ravb_remove(struct platform_device *pdev)
2199 {
2200 struct net_device *ndev = platform_get_drvdata(pdev);
2201 struct ravb_private *priv = netdev_priv(ndev);
2202
2203 /* Stop PTP Clock driver */
2204 if (priv->chip_id != RCAR_GEN2)
2205 ravb_ptp_stop(ndev);
2206
2207 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2208 priv->desc_bat_dma);
2209 /* Set reset mode */
2210 ravb_write(ndev, CCC_OPC_RESET, CCC);
2211 pm_runtime_put_sync(&pdev->dev);
2212 unregister_netdev(ndev);
2213 netif_napi_del(&priv->napi[RAVB_NC]);
2214 netif_napi_del(&priv->napi[RAVB_BE]);
2215 ravb_mdio_release(priv);
2216 pm_runtime_disable(&pdev->dev);
2217 free_netdev(ndev);
2218 platform_set_drvdata(pdev, NULL);
2219
2220 return 0;
2221 }
2222
2223 static int ravb_wol_setup(struct net_device *ndev)
2224 {
2225 struct ravb_private *priv = netdev_priv(ndev);
2226
2227 /* Disable interrupts by clearing the interrupt masks. */
2228 ravb_write(ndev, 0, RIC0);
2229 ravb_write(ndev, 0, RIC2);
2230 ravb_write(ndev, 0, TIC);
2231
2232 /* Only allow ECI interrupts */
2233 synchronize_irq(priv->emac_irq);
2234 napi_disable(&priv->napi[RAVB_NC]);
2235 napi_disable(&priv->napi[RAVB_BE]);
2236 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2237
2238 /* Enable MagicPacket */
2239 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2240
2241 return enable_irq_wake(priv->emac_irq);
2242 }
2243
2244 static int ravb_wol_restore(struct net_device *ndev)
2245 {
2246 struct ravb_private *priv = netdev_priv(ndev);
2247 int ret;
2248
2249 napi_enable(&priv->napi[RAVB_NC]);
2250 napi_enable(&priv->napi[RAVB_BE]);
2251
2252 /* Disable MagicPacket */
2253 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2254
2255 ret = ravb_close(ndev);
2256 if (ret < 0)
2257 return ret;
2258
2259 return disable_irq_wake(priv->emac_irq);
2260 }
2261
2262 static int __maybe_unused ravb_suspend(struct device *dev)
2263 {
2264 struct net_device *ndev = dev_get_drvdata(dev);
2265 struct ravb_private *priv = netdev_priv(ndev);
2266 int ret;
2267
2268 if (!netif_running(ndev))
2269 return 0;
2270
2271 netif_device_detach(ndev);
2272
2273 if (priv->wol_enabled)
2274 ret = ravb_wol_setup(ndev);
2275 else
2276 ret = ravb_close(ndev);
2277
2278 return ret;
2279 }
2280
2281 static int __maybe_unused ravb_resume(struct device *dev)
2282 {
2283 struct net_device *ndev = dev_get_drvdata(dev);
2284 struct ravb_private *priv = netdev_priv(ndev);
2285 int ret = 0;
2286
2287 /* If WoL is enabled set reset mode to rearm the WoL logic */
2288 if (priv->wol_enabled)
2289 ravb_write(ndev, CCC_OPC_RESET, CCC);
2290
2291 /* All register have been reset to default values.
2292 * Restore all registers which where setup at probe time and
2293 * reopen device if it was running before system suspended.
2294 */
2295
2296 /* Set AVB config mode */
2297 ravb_set_config_mode(ndev);
2298
2299 /* Set GTI value */
2300 ret = ravb_set_gti(ndev);
2301 if (ret)
2302 return ret;
2303
2304 /* Request GTI loading */
2305 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2306
2307 if (priv->chip_id != RCAR_GEN2)
2308 ravb_set_delay_mode(ndev);
2309
2310 /* Restore descriptor base address table */
2311 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2312
2313 if (netif_running(ndev)) {
2314 if (priv->wol_enabled) {
2315 ret = ravb_wol_restore(ndev);
2316 if (ret)
2317 return ret;
2318 }
2319 ret = ravb_open(ndev);
2320 if (ret < 0)
2321 return ret;
2322 netif_device_attach(ndev);
2323 }
2324
2325 return ret;
2326 }
2327
2328 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2329 {
2330 /* Runtime PM callback shared between ->runtime_suspend()
2331 * and ->runtime_resume(). Simply returns success.
2332 *
2333 * This driver re-initializes all registers after
2334 * pm_runtime_get_sync() anyway so there is no need
2335 * to save and restore registers here.
2336 */
2337 return 0;
2338 }
2339
2340 static const struct dev_pm_ops ravb_dev_pm_ops = {
2341 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2342 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2343 };
2344
2345 static struct platform_driver ravb_driver = {
2346 .probe = ravb_probe,
2347 .remove = ravb_remove,
2348 .driver = {
2349 .name = "ravb",
2350 .pm = &ravb_dev_pm_ops,
2351 .of_match_table = ravb_match_table,
2352 },
2353 };
2354
2355 module_platform_driver(ravb_driver);
2356
2357 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2358 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2359 MODULE_LICENSE("GPL v2");
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