1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
61 static int queue_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
62 u32 field1
, u32 field2
,
63 u32 field3
, u32 field4
, bool command_must_succeed
);
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
69 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
72 unsigned long segment_offset
;
74 if (!seg
|| !trb
|| trb
< seg
->trbs
)
77 segment_offset
= trb
- seg
->trbs
;
78 if (segment_offset
>= TRBS_PER_SEGMENT
)
80 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
83 static bool trb_is_noop(union xhci_trb
*trb
)
85 return TRB_TYPE_NOOP_LE32(trb
->generic
.field
[3]);
88 static bool trb_is_link(union xhci_trb
*trb
)
90 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
93 static bool last_trb_on_seg(struct xhci_segment
*seg
, union xhci_trb
*trb
)
95 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
- 1];
98 static bool last_trb_on_ring(struct xhci_ring
*ring
,
99 struct xhci_segment
*seg
, union xhci_trb
*trb
)
101 return last_trb_on_seg(seg
, trb
) && (seg
->next
== ring
->first_seg
);
104 static bool link_trb_toggles_cycle(union xhci_trb
*trb
)
106 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
109 static bool last_td_in_urb(struct xhci_td
*td
)
111 struct urb_priv
*urb_priv
= td
->urb
->hcpriv
;
113 return urb_priv
->num_tds_done
== urb_priv
->num_tds
;
116 static bool unhandled_event_trb(struct xhci_ring
*ring
)
118 return ((le32_to_cpu(ring
->dequeue
->event_cmd
.flags
) & TRB_CYCLE
) ==
122 static void inc_td_cnt(struct urb
*urb
)
124 struct urb_priv
*urb_priv
= urb
->hcpriv
;
126 urb_priv
->num_tds_done
++;
129 static void trb_to_noop(union xhci_trb
*trb
, u32 noop_type
)
131 if (trb_is_link(trb
)) {
132 /* unchain chained link TRBs */
133 trb
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
135 trb
->generic
.field
[0] = 0;
136 trb
->generic
.field
[1] = 0;
137 trb
->generic
.field
[2] = 0;
138 /* Preserve only the cycle bit of this TRB */
139 trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
140 trb
->generic
.field
[3] |= cpu_to_le32(TRB_TYPE(noop_type
));
144 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
145 * TRB is in a new segment. This does not skip over link TRBs, and it does not
146 * effect the ring dequeue or enqueue pointers.
148 static void next_trb(struct xhci_hcd
*xhci
,
149 struct xhci_ring
*ring
,
150 struct xhci_segment
**seg
,
151 union xhci_trb
**trb
)
153 if (trb_is_link(*trb
) || last_trb_on_seg(*seg
, *trb
)) {
155 *trb
= ((*seg
)->trbs
);
162 * See Cycle bit rules. SW is the consumer for the event ring only.
164 void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
166 unsigned int link_trb_count
= 0;
168 /* event ring doesn't have link trbs, check for last trb */
169 if (ring
->type
== TYPE_EVENT
) {
170 if (!last_trb_on_seg(ring
->deq_seg
, ring
->dequeue
)) {
174 if (last_trb_on_ring(ring
, ring
->deq_seg
, ring
->dequeue
))
175 ring
->cycle_state
^= 1;
176 ring
->deq_seg
= ring
->deq_seg
->next
;
177 ring
->dequeue
= ring
->deq_seg
->trbs
;
181 /* All other rings have link trbs */
182 if (!trb_is_link(ring
->dequeue
)) {
183 if (last_trb_on_seg(ring
->deq_seg
, ring
->dequeue
))
184 xhci_warn(xhci
, "Missing link TRB at end of segment\n");
189 while (trb_is_link(ring
->dequeue
)) {
190 ring
->deq_seg
= ring
->deq_seg
->next
;
191 ring
->dequeue
= ring
->deq_seg
->trbs
;
193 if (link_trb_count
++ > ring
->num_segs
) {
194 xhci_warn(xhci
, "Ring is an endless link TRB loop\n");
199 trace_xhci_inc_deq(ring
);
205 * See Cycle bit rules. SW is the consumer for the event ring only.
207 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
208 * chain bit is set), then set the chain bit in all the following link TRBs.
209 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
210 * have their chain bit cleared (so that each Link TRB is a separate TD).
212 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
213 * set, but other sections talk about dealing with the chain bit set. This was
214 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
215 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
217 * @more_trbs_coming: Will you enqueue more TRBs before calling
218 * prepare_transfer()?
220 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
221 bool more_trbs_coming
)
224 union xhci_trb
*next
;
225 unsigned int link_trb_count
= 0;
227 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
229 if (last_trb_on_seg(ring
->enq_seg
, ring
->enqueue
)) {
230 xhci_err(xhci
, "Tried to move enqueue past ring segment\n");
234 next
= ++(ring
->enqueue
);
236 /* Update the dequeue pointer further if that was a link TRB */
237 while (trb_is_link(next
)) {
240 * If the caller doesn't plan on enqueueing more TDs before
241 * ringing the doorbell, then we don't want to give the link TRB
242 * to the hardware just yet. We'll give the link TRB back in
243 * prepare_ring() just before we enqueue the TD at the top of
246 if (!chain
&& !more_trbs_coming
)
249 /* If we're not dealing with 0.95 hardware or isoc rings on
250 * AMD 0.96 host, carry over the chain bit of the previous TRB
251 * (which may mean the chain bit is cleared).
253 if (!(ring
->type
== TYPE_ISOC
&&
254 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)) &&
255 !xhci_link_trb_quirk(xhci
)) {
256 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
257 next
->link
.control
|= cpu_to_le32(chain
);
259 /* Give this link TRB to the hardware */
261 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
263 /* Toggle the cycle bit after the last ring segment. */
264 if (link_trb_toggles_cycle(next
))
265 ring
->cycle_state
^= 1;
267 ring
->enq_seg
= ring
->enq_seg
->next
;
268 ring
->enqueue
= ring
->enq_seg
->trbs
;
269 next
= ring
->enqueue
;
271 if (link_trb_count
++ > ring
->num_segs
) {
272 xhci_warn(xhci
, "%s: Ring link TRB loop\n", __func__
);
277 trace_xhci_inc_enq(ring
);
281 * Return number of free normal TRBs from enqueue to dequeue pointer on ring.
282 * Not counting an assumed link TRB at end of each TRBS_PER_SEGMENT sized segment.
283 * Only for transfer and command rings where driver is the producer, not for
286 static unsigned int xhci_num_trbs_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
288 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
289 union xhci_trb
*enq
= ring
->enqueue
;
290 union xhci_trb
*last_on_seg
;
291 unsigned int free
= 0;
294 /* Ring might be empty even if enq != deq if enq is left on a link trb */
295 if (trb_is_link(enq
)) {
296 enq_seg
= enq_seg
->next
;
300 /* Empty ring, common case, don't walk the segments */
301 if (enq
== ring
->dequeue
)
302 return ring
->num_segs
* (TRBS_PER_SEGMENT
- 1);
305 if (ring
->deq_seg
== enq_seg
&& ring
->dequeue
>= enq
)
306 return free
+ (ring
->dequeue
- enq
);
307 last_on_seg
= &enq_seg
->trbs
[TRBS_PER_SEGMENT
- 1];
308 free
+= last_on_seg
- enq
;
309 enq_seg
= enq_seg
->next
;
311 } while (i
++ <= ring
->num_segs
);
317 * Check to see if there's room to enqueue num_trbs on the ring and make sure
318 * enqueue pointer will not advance into dequeue segment. See rules above.
319 * return number of new segments needed to ensure this.
322 static unsigned int xhci_ring_expansion_needed(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
323 unsigned int num_trbs
)
325 struct xhci_segment
*seg
;
330 enq_used
= ring
->enqueue
- ring
->enq_seg
->trbs
;
332 /* how many trbs will be queued past the enqueue segment? */
333 trbs_past_seg
= enq_used
+ num_trbs
- (TRBS_PER_SEGMENT
- 1);
336 * Consider expanding the ring already if num_trbs fills the current
337 * segment (i.e. trbs_past_seg == 0), not only when num_trbs goes into
338 * the next segment. Avoids confusing full ring with special empty ring
341 if (trbs_past_seg
< 0)
344 /* Empty ring special case, enqueue stuck on link trb while dequeue advanced */
345 if (trb_is_link(ring
->enqueue
) && ring
->enq_seg
->next
->trbs
== ring
->dequeue
)
348 new_segs
= 1 + (trbs_past_seg
/ (TRBS_PER_SEGMENT
- 1));
351 while (new_segs
> 0) {
353 if (seg
== ring
->deq_seg
) {
354 xhci_dbg(xhci
, "Ring expansion by %d segments needed\n",
356 xhci_dbg(xhci
, "Adding %d trbs moves enq %d trbs into deq seg\n",
357 num_trbs
, trbs_past_seg
% TRBS_PER_SEGMENT
);
366 /* Ring the host controller doorbell after placing a command on the ring */
367 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
369 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
))
372 xhci_dbg(xhci
, "// Ding dong!\n");
374 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST
);
376 writel(DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
377 /* Flush PCI posted writes */
378 readl(&xhci
->dba
->doorbell
[0]);
381 static bool xhci_mod_cmd_timer(struct xhci_hcd
*xhci
)
383 return mod_delayed_work(system_wq
, &xhci
->cmd_timer
,
384 msecs_to_jiffies(xhci
->current_cmd
->timeout_ms
));
387 static struct xhci_command
*xhci_next_queued_cmd(struct xhci_hcd
*xhci
)
389 return list_first_entry_or_null(&xhci
->cmd_list
, struct xhci_command
,
394 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
395 * If there are other commands waiting then restart the ring and kick the timer.
396 * This must be called with command ring stopped and xhci->lock held.
398 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd
*xhci
,
399 struct xhci_command
*cur_cmd
)
401 struct xhci_command
*i_cmd
;
403 /* Turn all aborted commands in list to no-ops, then restart */
404 list_for_each_entry(i_cmd
, &xhci
->cmd_list
, cmd_list
) {
406 if (i_cmd
->status
!= COMP_COMMAND_ABORTED
)
409 i_cmd
->status
= COMP_COMMAND_RING_STOPPED
;
411 xhci_dbg(xhci
, "Turn aborted command %p to no-op\n",
414 trb_to_noop(i_cmd
->command_trb
, TRB_CMD_NOOP
);
417 * caller waiting for completion is called when command
418 * completion event is received for these no-op commands
422 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
424 /* ring command ring doorbell to restart the command ring */
425 if ((xhci
->cmd_ring
->dequeue
!= xhci
->cmd_ring
->enqueue
) &&
426 !(xhci
->xhc_state
& XHCI_STATE_DYING
)) {
427 xhci
->current_cmd
= cur_cmd
;
428 xhci_mod_cmd_timer(xhci
);
429 xhci_ring_cmd_db(xhci
);
433 /* Must be called with xhci->lock held, releases and aquires lock back */
434 static int xhci_abort_cmd_ring(struct xhci_hcd
*xhci
, unsigned long flags
)
436 struct xhci_segment
*new_seg
= xhci
->cmd_ring
->deq_seg
;
437 union xhci_trb
*new_deq
= xhci
->cmd_ring
->dequeue
;
441 xhci_dbg(xhci
, "Abort command ring\n");
443 reinit_completion(&xhci
->cmd_ring_stop_completion
);
446 * The control bits like command stop, abort are located in lower
447 * dword of the command ring control register.
448 * Some controllers require all 64 bits to be written to abort the ring.
449 * Make sure the upper dword is valid, pointing to the next command,
450 * avoiding corrupting the command ring pointer in case the command ring
451 * is stopped by the time the upper dword is written.
453 next_trb(xhci
, NULL
, &new_seg
, &new_deq
);
454 if (trb_is_link(new_deq
))
455 next_trb(xhci
, NULL
, &new_seg
, &new_deq
);
457 crcr
= xhci_trb_virt_to_dma(new_seg
, new_deq
);
458 xhci_write_64(xhci
, crcr
| CMD_RING_ABORT
, &xhci
->op_regs
->cmd_ring
);
460 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
461 * completion of the Command Abort operation. If CRR is not negated in 5
462 * seconds then driver handles it as if host died (-ENODEV).
463 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
464 * and try to recover a -ETIMEDOUT with a host controller reset.
466 ret
= xhci_handshake_check_state(xhci
, &xhci
->op_regs
->cmd_ring
,
467 CMD_RING_RUNNING
, 0, 5 * 1000 * 1000,
468 XHCI_STATE_REMOVING
);
470 xhci_err(xhci
, "Abort failed to stop command ring: %d\n", ret
);
476 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
477 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
478 * but the completion event in never sent. Wait 2 secs (arbitrary
479 * number) to handle those cases after negation of CMD_RING_RUNNING.
481 spin_unlock_irqrestore(&xhci
->lock
, flags
);
482 ret
= wait_for_completion_timeout(&xhci
->cmd_ring_stop_completion
,
483 msecs_to_jiffies(2000));
484 spin_lock_irqsave(&xhci
->lock
, flags
);
486 xhci_dbg(xhci
, "No stop event for abort, ring start fail?\n");
487 xhci_cleanup_command_queue(xhci
);
489 xhci_handle_stopped_cmd_ring(xhci
, xhci_next_queued_cmd(xhci
));
494 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
495 unsigned int slot_id
,
496 unsigned int ep_index
,
497 unsigned int stream_id
)
499 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
500 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
501 unsigned int ep_state
= ep
->ep_state
;
503 /* Don't ring the doorbell for this endpoint if there are pending
504 * cancellations because we don't want to interrupt processing.
505 * We don't want to restart any stream rings if there's a set dequeue
506 * pointer command pending because the device can choose to start any
507 * stream once the endpoint is on the HW schedule.
509 if ((ep_state
& EP_STOP_CMD_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
510 (ep_state
& EP_HALTED
) || (ep_state
& EP_CLEARING_TT
))
513 trace_xhci_ring_ep_doorbell(slot_id
, DB_VALUE(ep_index
, stream_id
));
515 writel(DB_VALUE(ep_index
, stream_id
), db_addr
);
516 /* flush the write */
520 /* Ring the doorbell for any rings with pending URBs */
521 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
522 unsigned int slot_id
,
523 unsigned int ep_index
)
525 unsigned int stream_id
;
526 struct xhci_virt_ep
*ep
;
528 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
530 /* A ring has pending URBs if its TD list is not empty */
531 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
532 if (ep
->ring
&& !(list_empty(&ep
->ring
->td_list
)))
533 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
537 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
539 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
540 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
541 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
546 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
547 unsigned int slot_id
,
548 unsigned int ep_index
)
550 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
553 static struct xhci_virt_ep
*xhci_get_virt_ep(struct xhci_hcd
*xhci
,
554 unsigned int slot_id
,
555 unsigned int ep_index
)
557 if (slot_id
== 0 || slot_id
>= MAX_HC_SLOTS
) {
558 xhci_warn(xhci
, "Invalid slot_id %u\n", slot_id
);
561 if (ep_index
>= EP_CTX_PER_DEV
) {
562 xhci_warn(xhci
, "Invalid endpoint index %u\n", ep_index
);
565 if (!xhci
->devs
[slot_id
]) {
566 xhci_warn(xhci
, "No xhci virt device for slot_id %u\n", slot_id
);
570 return &xhci
->devs
[slot_id
]->eps
[ep_index
];
573 static struct xhci_ring
*xhci_virt_ep_to_ring(struct xhci_hcd
*xhci
,
574 struct xhci_virt_ep
*ep
,
575 unsigned int stream_id
)
577 /* common case, no streams */
578 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
581 if (!ep
->stream_info
)
584 if (stream_id
== 0 || stream_id
>= ep
->stream_info
->num_streams
) {
585 xhci_warn(xhci
, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
586 stream_id
, ep
->vdev
->slot_id
, ep
->ep_index
);
590 return ep
->stream_info
->stream_rings
[stream_id
];
593 /* Get the right ring for the given slot_id, ep_index and stream_id.
594 * If the endpoint supports streams, boundary check the URB's stream ID.
595 * If the endpoint doesn't support streams, return the singular endpoint ring.
597 struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
598 unsigned int slot_id
, unsigned int ep_index
,
599 unsigned int stream_id
)
601 struct xhci_virt_ep
*ep
;
603 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
607 return xhci_virt_ep_to_ring(xhci
, ep
, stream_id
);
612 * Get the hw dequeue pointer xHC stopped on, either directly from the
613 * endpoint context, or if streams are in use from the stream context.
614 * The returned hw_dequeue contains the lowest four bits with cycle state
615 * and possbile stream context type.
617 static u64
xhci_get_hw_deq(struct xhci_hcd
*xhci
, struct xhci_virt_device
*vdev
,
618 unsigned int ep_index
, unsigned int stream_id
)
620 struct xhci_ep_ctx
*ep_ctx
;
621 struct xhci_stream_ctx
*st_ctx
;
622 struct xhci_virt_ep
*ep
;
624 ep
= &vdev
->eps
[ep_index
];
626 if (ep
->ep_state
& EP_HAS_STREAMS
) {
627 st_ctx
= &ep
->stream_info
->stream_ctx_array
[stream_id
];
628 return le64_to_cpu(st_ctx
->stream_ring
);
630 ep_ctx
= xhci_get_ep_ctx(xhci
, vdev
->out_ctx
, ep_index
);
631 return le64_to_cpu(ep_ctx
->deq
);
634 static int xhci_move_dequeue_past_td(struct xhci_hcd
*xhci
,
635 unsigned int slot_id
, unsigned int ep_index
,
636 unsigned int stream_id
, struct xhci_td
*td
)
638 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
639 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
640 struct xhci_ring
*ep_ring
;
641 struct xhci_command
*cmd
;
642 struct xhci_segment
*new_seg
;
643 union xhci_trb
*new_deq
;
647 bool cycle_found
= false;
648 bool td_last_trb_found
= false;
652 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
653 ep_index
, stream_id
);
655 xhci_warn(xhci
, "WARN can't find new dequeue, invalid stream ID %u\n",
660 * A cancelled TD can complete with a stall if HW cached the trb.
661 * In this case driver can't find td, but if the ring is empty we
662 * can move the dequeue pointer to the current enqueue position.
663 * We shouldn't hit this anymore as cached cancelled TRBs are given back
664 * after clearing the cache, but be on the safe side and keep it anyway
667 if (list_empty(&ep_ring
->td_list
)) {
668 new_seg
= ep_ring
->enq_seg
;
669 new_deq
= ep_ring
->enqueue
;
670 new_cycle
= ep_ring
->cycle_state
;
671 xhci_dbg(xhci
, "ep ring empty, Set new dequeue = enqueue");
674 xhci_warn(xhci
, "Can't find new dequeue state, missing td\n");
679 hw_dequeue
= xhci_get_hw_deq(xhci
, dev
, ep_index
, stream_id
);
680 new_seg
= ep_ring
->deq_seg
;
681 new_deq
= ep_ring
->dequeue
;
682 new_cycle
= hw_dequeue
& 0x1;
685 * We want to find the pointer, segment and cycle state of the new trb
686 * (the one after current TD's last_trb). We know the cycle state at
687 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
691 if (!cycle_found
&& xhci_trb_virt_to_dma(new_seg
, new_deq
)
692 == (dma_addr_t
)(hw_dequeue
& ~0xf)) {
694 if (td_last_trb_found
)
697 if (new_deq
== td
->last_trb
)
698 td_last_trb_found
= true;
700 if (cycle_found
&& trb_is_link(new_deq
) &&
701 link_trb_toggles_cycle(new_deq
))
704 next_trb(xhci
, ep_ring
, &new_seg
, &new_deq
);
706 /* Search wrapped around, bail out */
707 if (new_deq
== ep
->ring
->dequeue
) {
708 xhci_err(xhci
, "Error: Failed finding new dequeue state\n");
712 } while (!cycle_found
|| !td_last_trb_found
);
716 /* Don't update the ring cycle state for the producer (us). */
717 addr
= xhci_trb_virt_to_dma(new_seg
, new_deq
);
719 xhci_warn(xhci
, "Can't find dma of new dequeue ptr\n");
720 xhci_warn(xhci
, "deq seg = %p, deq ptr = %p\n", new_seg
, new_deq
);
724 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
725 xhci_warn(xhci
, "Set TR Deq already pending, don't submit for 0x%pad\n",
730 /* This function gets called from contexts where it cannot sleep */
731 cmd
= xhci_alloc_command(xhci
, false, GFP_ATOMIC
);
733 xhci_warn(xhci
, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr
);
738 trb_sct
= SCT_FOR_TRB(SCT_PRI_TR
);
739 ret
= queue_command(xhci
, cmd
,
740 lower_32_bits(addr
) | trb_sct
| new_cycle
,
742 STREAM_ID_FOR_TRB(stream_id
), SLOT_ID_FOR_TRB(slot_id
) |
743 EP_ID_FOR_TRB(ep_index
) | TRB_TYPE(TRB_SET_DEQ
), false);
745 xhci_free_command(xhci
, cmd
);
748 ep
->queued_deq_seg
= new_seg
;
749 ep
->queued_deq_ptr
= new_deq
;
751 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
752 "Set TR Deq ptr 0x%llx, cycle %u\n", addr
, new_cycle
);
754 /* Stop the TD queueing code from ringing the doorbell until
755 * this command completes. The HC won't set the dequeue pointer
756 * if the ring is running, and ringing the doorbell starts the
759 ep
->ep_state
|= SET_DEQ_PENDING
;
760 xhci_ring_cmd_db(xhci
);
764 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
765 * (The last TRB actually points to the ring enqueue pointer, which is not part
766 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
768 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
769 struct xhci_td
*td
, bool flip_cycle
)
771 struct xhci_segment
*seg
= td
->start_seg
;
772 union xhci_trb
*trb
= td
->first_trb
;
775 trb_to_noop(trb
, TRB_TR_NOOP
);
777 /* flip cycle if asked to */
778 if (flip_cycle
&& trb
!= td
->first_trb
&& trb
!= td
->last_trb
)
779 trb
->generic
.field
[3] ^= cpu_to_le32(TRB_CYCLE
);
781 if (trb
== td
->last_trb
)
784 next_trb(xhci
, ep_ring
, &seg
, &trb
);
789 * Must be called with xhci->lock held in interrupt context,
790 * releases and re-acquires xhci->lock
792 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
793 struct xhci_td
*cur_td
, int status
)
795 struct urb
*urb
= cur_td
->urb
;
796 struct urb_priv
*urb_priv
= urb
->hcpriv
;
797 struct usb_hcd
*hcd
= bus_to_hcd(urb
->dev
->bus
);
799 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
800 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
801 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
802 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
803 usb_amd_quirk_pll_enable();
806 xhci_urb_free_priv(urb_priv
);
807 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
808 trace_xhci_urb_giveback(urb
);
809 usb_hcd_giveback_urb(hcd
, urb
, status
);
812 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd
*xhci
,
813 struct xhci_ring
*ring
, struct xhci_td
*td
)
815 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
816 struct xhci_segment
*seg
= td
->bounce_seg
;
817 struct urb
*urb
= td
->urb
;
820 if (!ring
|| !seg
|| !urb
)
823 if (usb_urb_dir_out(urb
)) {
824 dma_unmap_single(dev
, seg
->bounce_dma
, ring
->bounce_buf_len
,
829 dma_unmap_single(dev
, seg
->bounce_dma
, ring
->bounce_buf_len
,
831 /* for in tranfers we need to copy the data from bounce to sg */
833 len
= sg_pcopy_from_buffer(urb
->sg
, urb
->num_sgs
, seg
->bounce_buf
,
834 seg
->bounce_len
, seg
->bounce_offs
);
835 if (len
!= seg
->bounce_len
)
836 xhci_warn(xhci
, "WARN Wrong bounce buffer read length: %zu != %d\n",
837 len
, seg
->bounce_len
);
839 memcpy(urb
->transfer_buffer
+ seg
->bounce_offs
, seg
->bounce_buf
,
843 seg
->bounce_offs
= 0;
846 static int xhci_td_cleanup(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
847 struct xhci_ring
*ep_ring
, int status
)
849 struct urb
*urb
= NULL
;
851 /* Clean up the endpoint's TD list */
854 /* if a bounce buffer was used to align this td then unmap it */
855 xhci_unmap_td_bounce_buffer(xhci
, ep_ring
, td
);
857 /* Do one last check of the actual transfer length.
858 * If the host controller said we transferred more data than the buffer
859 * length, urb->actual_length will be a very big number (since it's
860 * unsigned). Play it safe and say we didn't transfer anything.
862 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
863 xhci_warn(xhci
, "URB req %u and actual %u transfer length mismatch\n",
864 urb
->transfer_buffer_length
, urb
->actual_length
);
865 urb
->actual_length
= 0;
868 /* TD might be removed from td_list if we are giving back a cancelled URB */
869 if (!list_empty(&td
->td_list
))
870 list_del_init(&td
->td_list
);
871 /* Giving back a cancelled URB, or if a slated TD completed anyway */
872 if (!list_empty(&td
->cancelled_td_list
))
873 list_del_init(&td
->cancelled_td_list
);
876 /* Giveback the urb when all the tds are completed */
877 if (last_td_in_urb(td
)) {
878 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
879 (urb
->transfer_flags
& URB_SHORT_NOT_OK
)) ||
880 (status
!= 0 && !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
881 xhci_dbg(xhci
, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
882 urb
, urb
->actual_length
,
883 urb
->transfer_buffer_length
, status
);
885 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
886 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
888 xhci_giveback_urb_in_irq(xhci
, td
, status
);
895 /* Complete the cancelled URBs we unlinked from td_list. */
896 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep
*ep
)
898 struct xhci_ring
*ring
;
899 struct xhci_td
*td
, *tmp_td
;
901 list_for_each_entry_safe(td
, tmp_td
, &ep
->cancelled_td_list
,
904 ring
= xhci_urb_to_transfer_ring(ep
->xhci
, td
->urb
);
906 if (td
->cancel_status
== TD_CLEARED
) {
907 xhci_dbg(ep
->xhci
, "%s: Giveback cancelled URB %p TD\n",
909 xhci_td_cleanup(ep
->xhci
, td
, ring
, td
->status
);
911 xhci_dbg(ep
->xhci
, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
912 __func__
, td
->urb
, td
->cancel_status
);
914 if (ep
->xhci
->xhc_state
& XHCI_STATE_DYING
)
919 static int xhci_reset_halted_ep(struct xhci_hcd
*xhci
, unsigned int slot_id
,
920 unsigned int ep_index
, enum xhci_ep_reset_type reset_type
)
922 struct xhci_command
*command
;
925 command
= xhci_alloc_command(xhci
, false, GFP_ATOMIC
);
931 xhci_dbg(xhci
, "%s-reset ep %u, slot %u\n",
932 (reset_type
== EP_HARD_RESET
) ? "Hard" : "Soft",
935 ret
= xhci_queue_reset_ep(xhci
, command
, slot_id
, ep_index
, reset_type
);
938 xhci_err(xhci
, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
939 slot_id
, ep_index
, ret
);
943 static int xhci_handle_halted_endpoint(struct xhci_hcd
*xhci
,
944 struct xhci_virt_ep
*ep
,
946 enum xhci_ep_reset_type reset_type
)
948 unsigned int slot_id
= ep
->vdev
->slot_id
;
952 * Avoid resetting endpoint if link is inactive. Can cause host hang.
953 * Device will be reset soon to recover the link so don't do anything
955 if (ep
->vdev
->flags
& VDEV_PORT_ERROR
)
958 /* add td to cancelled list and let reset ep handler take care of it */
959 if (reset_type
== EP_HARD_RESET
) {
960 ep
->ep_state
|= EP_HARD_CLEAR_TOGGLE
;
961 if (td
&& list_empty(&td
->cancelled_td_list
)) {
962 list_add_tail(&td
->cancelled_td_list
, &ep
->cancelled_td_list
);
963 td
->cancel_status
= TD_HALTED
;
967 if (ep
->ep_state
& EP_HALTED
) {
968 xhci_dbg(xhci
, "Reset ep command for ep_index %d already pending\n",
973 err
= xhci_reset_halted_ep(xhci
, slot_id
, ep
->ep_index
, reset_type
);
977 ep
->ep_state
|= EP_HALTED
;
979 xhci_ring_cmd_db(xhci
);
985 * Fix up the ep ring first, so HW stops executing cancelled TDs.
986 * We have the xHCI lock, so nothing can modify this list until we drop it.
987 * We're also in the event handler, so we can't get re-interrupted if another
988 * Stop Endpoint command completes.
990 * only call this when ring is not in a running state
993 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep
*ep
)
995 struct xhci_hcd
*xhci
;
996 struct xhci_td
*td
= NULL
;
997 struct xhci_td
*tmp_td
= NULL
;
998 struct xhci_td
*cached_td
= NULL
;
999 struct xhci_ring
*ring
;
1001 unsigned int slot_id
= ep
->vdev
->slot_id
;
1006 list_for_each_entry_safe(td
, tmp_td
, &ep
->cancelled_td_list
, cancelled_td_list
) {
1007 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1008 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
1009 (unsigned long long)xhci_trb_virt_to_dma(
1010 td
->start_seg
, td
->first_trb
),
1011 td
->urb
->stream_id
, td
->urb
);
1012 list_del_init(&td
->td_list
);
1013 ring
= xhci_urb_to_transfer_ring(xhci
, td
->urb
);
1015 xhci_warn(xhci
, "WARN Cancelled URB %p has invalid stream ID %u.\n",
1016 td
->urb
, td
->urb
->stream_id
);
1020 * If a ring stopped on the TD we need to cancel then we have to
1021 * move the xHC endpoint ring dequeue pointer past this TD.
1022 * Rings halted due to STALL may show hw_deq is past the stalled
1023 * TD, but still require a set TR Deq command to flush xHC cache.
1025 hw_deq
= xhci_get_hw_deq(xhci
, ep
->vdev
, ep
->ep_index
,
1026 td
->urb
->stream_id
);
1029 if (td
->cancel_status
== TD_HALTED
||
1030 trb_in_td(xhci
, td
->start_seg
, td
->first_trb
, td
->last_trb
, hw_deq
, false)) {
1031 switch (td
->cancel_status
) {
1032 case TD_CLEARED
: /* TD is already no-op */
1033 case TD_CLEARING_CACHE
: /* set TR deq command already queued */
1035 case TD_DIRTY
: /* TD is cached, clear it */
1037 td
->cancel_status
= TD_CLEARING_CACHE
;
1039 /* FIXME stream case, several stopped rings */
1041 "Move dq past stream %u URB %p instead of stream %u URB %p\n",
1042 td
->urb
->stream_id
, td
->urb
,
1043 cached_td
->urb
->stream_id
, cached_td
->urb
);
1048 td_to_noop(xhci
, ring
, td
, false);
1049 td
->cancel_status
= TD_CLEARED
;
1053 /* If there's no need to move the dequeue pointer then we're done */
1057 err
= xhci_move_dequeue_past_td(xhci
, slot_id
, ep
->ep_index
,
1058 cached_td
->urb
->stream_id
,
1061 /* Failed to move past cached td, just set cached TDs to no-op */
1062 list_for_each_entry_safe(td
, tmp_td
, &ep
->cancelled_td_list
, cancelled_td_list
) {
1063 if (td
->cancel_status
!= TD_CLEARING_CACHE
)
1065 xhci_dbg(xhci
, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1067 td_to_noop(xhci
, ring
, td
, false);
1068 td
->cancel_status
= TD_CLEARED
;
1075 * Returns the TD the endpoint ring halted on.
1076 * Only call for non-running rings without streams.
1078 static struct xhci_td
*find_halted_td(struct xhci_virt_ep
*ep
)
1083 if (!list_empty(&ep
->ring
->td_list
)) { /* Not streams compatible */
1084 hw_deq
= xhci_get_hw_deq(ep
->xhci
, ep
->vdev
, ep
->ep_index
, 0);
1086 td
= list_first_entry(&ep
->ring
->td_list
, struct xhci_td
, td_list
);
1087 if (trb_in_td(ep
->xhci
, td
->start_seg
, td
->first_trb
,
1088 td
->last_trb
, hw_deq
, false))
1095 * When we get a command completion for a Stop Endpoint Command, we need to
1096 * unlink any cancelled TDs from the ring. There are two ways to do that:
1098 * 1. If the HW was in the middle of processing the TD that needs to be
1099 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1100 * in the TD with a Set Dequeue Pointer Command.
1101 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1102 * bit cleared) so that the HW will skip over them.
1104 static void xhci_handle_cmd_stop_ep(struct xhci_hcd
*xhci
, int slot_id
,
1105 union xhci_trb
*trb
, u32 comp_code
)
1107 unsigned int ep_index
;
1108 struct xhci_virt_ep
*ep
;
1109 struct xhci_ep_ctx
*ep_ctx
;
1110 struct xhci_td
*td
= NULL
;
1111 enum xhci_ep_reset_type reset_type
;
1112 struct xhci_command
*command
;
1115 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb
->generic
.field
[3])))) {
1116 if (!xhci
->devs
[slot_id
])
1117 xhci_warn(xhci
, "Stop endpoint command completion for disabled slot %u\n",
1122 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1123 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
1127 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep_index
);
1129 trace_xhci_handle_cmd_stop_ep(ep_ctx
);
1131 if (comp_code
== COMP_CONTEXT_STATE_ERROR
) {
1133 * If stop endpoint command raced with a halting endpoint we need to
1134 * reset the host side endpoint first.
1135 * If the TD we halted on isn't cancelled the TD should be given back
1136 * with a proper error code, and the ring dequeue moved past the TD.
1137 * If streams case we can't find hw_deq, or the TD we halted on so do a
1140 * Proper error code is unknown here, it would be -EPIPE if device side
1141 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1142 * We use -EPROTO, if device is stalled it should return a stall error on
1143 * next transfer, which then will return -EPIPE, and device side stall is
1144 * noted and cleared by class driver.
1146 switch (GET_EP_CTX_STATE(ep_ctx
)) {
1147 case EP_STATE_HALTED
:
1148 xhci_dbg(xhci
, "Stop ep completion raced with stall, reset ep\n");
1149 if (ep
->ep_state
& EP_HAS_STREAMS
) {
1150 reset_type
= EP_SOFT_RESET
;
1152 reset_type
= EP_HARD_RESET
;
1153 td
= find_halted_td(ep
);
1155 td
->status
= -EPROTO
;
1157 /* reset ep, reset handler cleans up cancelled tds */
1158 err
= xhci_handle_halted_endpoint(xhci
, ep
, td
, reset_type
);
1161 ep
->ep_state
&= ~EP_STOP_CMD_PENDING
;
1163 case EP_STATE_STOPPED
:
1165 * NEC uPD720200 sometimes sets this state and fails with
1166 * Context Error while continuing to process TRBs.
1167 * Be conservative and trust EP_CTX_STATE on other chips.
1169 if (!(xhci
->quirks
& XHCI_NEC_HOST
))
1172 case EP_STATE_RUNNING
:
1173 /* Race, HW handled stop ep cmd before ep was running */
1174 xhci_dbg(xhci
, "Stop ep completion ctx error, ep is running\n");
1176 command
= xhci_alloc_command(xhci
, false, GFP_ATOMIC
);
1178 ep
->ep_state
&= ~EP_STOP_CMD_PENDING
;
1181 xhci_queue_stop_endpoint(xhci
, command
, slot_id
, ep_index
, 0);
1182 xhci_ring_cmd_db(xhci
);
1190 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1191 xhci_invalidate_cancelled_tds(ep
);
1192 ep
->ep_state
&= ~EP_STOP_CMD_PENDING
;
1194 /* Otherwise ring the doorbell(s) to restart queued transfers */
1195 xhci_giveback_invalidated_tds(ep
);
1196 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1199 static void xhci_kill_ring_urbs(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
1201 struct xhci_td
*cur_td
;
1202 struct xhci_td
*tmp
;
1204 list_for_each_entry_safe(cur_td
, tmp
, &ring
->td_list
, td_list
) {
1205 list_del_init(&cur_td
->td_list
);
1207 if (!list_empty(&cur_td
->cancelled_td_list
))
1208 list_del_init(&cur_td
->cancelled_td_list
);
1210 xhci_unmap_td_bounce_buffer(xhci
, ring
, cur_td
);
1212 inc_td_cnt(cur_td
->urb
);
1213 if (last_td_in_urb(cur_td
))
1214 xhci_giveback_urb_in_irq(xhci
, cur_td
, -ESHUTDOWN
);
1218 static void xhci_kill_endpoint_urbs(struct xhci_hcd
*xhci
,
1219 int slot_id
, int ep_index
)
1221 struct xhci_td
*cur_td
;
1222 struct xhci_td
*tmp
;
1223 struct xhci_virt_ep
*ep
;
1224 struct xhci_ring
*ring
;
1226 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
1230 if ((ep
->ep_state
& EP_HAS_STREAMS
) ||
1231 (ep
->ep_state
& EP_GETTING_NO_STREAMS
)) {
1234 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
1236 ring
= ep
->stream_info
->stream_rings
[stream_id
];
1240 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1241 "Killing URBs for slot ID %u, ep index %u, stream %u",
1242 slot_id
, ep_index
, stream_id
);
1243 xhci_kill_ring_urbs(xhci
, ring
);
1249 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1250 "Killing URBs for slot ID %u, ep index %u",
1252 xhci_kill_ring_urbs(xhci
, ring
);
1255 list_for_each_entry_safe(cur_td
, tmp
, &ep
->cancelled_td_list
,
1256 cancelled_td_list
) {
1257 list_del_init(&cur_td
->cancelled_td_list
);
1258 inc_td_cnt(cur_td
->urb
);
1260 if (last_td_in_urb(cur_td
))
1261 xhci_giveback_urb_in_irq(xhci
, cur_td
, -ESHUTDOWN
);
1266 * host controller died, register read returns 0xffffffff
1267 * Complete pending commands, mark them ABORTED.
1268 * URBs need to be given back as usb core might be waiting with device locks
1269 * held for the URBs to finish during device disconnect, blocking host remove.
1271 * Call with xhci->lock held.
1272 * lock is relased and re-acquired while giving back urb.
1274 void xhci_hc_died(struct xhci_hcd
*xhci
)
1278 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1281 xhci_err(xhci
, "xHCI host controller not responding, assume dead\n");
1282 xhci
->xhc_state
|= XHCI_STATE_DYING
;
1284 xhci_cleanup_command_queue(xhci
);
1286 /* return any pending urbs, remove may be waiting for them */
1287 for (i
= 0; i
<= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
1290 for (j
= 0; j
< 31; j
++)
1291 xhci_kill_endpoint_urbs(xhci
, i
, j
);
1294 /* inform usb core hc died if PCI remove isn't already handling it */
1295 if (!(xhci
->xhc_state
& XHCI_STATE_REMOVING
))
1296 usb_hc_died(xhci_to_hcd(xhci
));
1299 static void update_ring_for_set_deq_completion(struct xhci_hcd
*xhci
,
1300 struct xhci_virt_device
*dev
,
1301 struct xhci_ring
*ep_ring
,
1302 unsigned int ep_index
)
1304 union xhci_trb
*dequeue_temp
;
1306 dequeue_temp
= ep_ring
->dequeue
;
1308 /* If we get two back-to-back stalls, and the first stalled transfer
1309 * ends just before a link TRB, the dequeue pointer will be left on
1310 * the link TRB by the code in the while loop. So we have to update
1311 * the dequeue pointer one segment further, or we'll jump off
1312 * the segment into la-la-land.
1314 if (trb_is_link(ep_ring
->dequeue
)) {
1315 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1316 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1319 while (ep_ring
->dequeue
!= dev
->eps
[ep_index
].queued_deq_ptr
) {
1320 /* We have more usable TRBs */
1322 if (trb_is_link(ep_ring
->dequeue
)) {
1323 if (ep_ring
->dequeue
==
1324 dev
->eps
[ep_index
].queued_deq_ptr
)
1326 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1327 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1329 if (ep_ring
->dequeue
== dequeue_temp
) {
1330 xhci_dbg(xhci
, "Unable to find new dequeue pointer\n");
1337 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1338 * we need to clear the set deq pending flag in the endpoint ring state, so that
1339 * the TD queueing code can ring the doorbell again. We also need to ring the
1340 * endpoint doorbell to restart the ring, but only if there aren't more
1341 * cancellations pending.
1343 static void xhci_handle_cmd_set_deq(struct xhci_hcd
*xhci
, int slot_id
,
1344 union xhci_trb
*trb
, u32 cmd_comp_code
)
1346 unsigned int ep_index
;
1347 unsigned int stream_id
;
1348 struct xhci_ring
*ep_ring
;
1349 struct xhci_virt_ep
*ep
;
1350 struct xhci_ep_ctx
*ep_ctx
;
1351 struct xhci_slot_ctx
*slot_ctx
;
1352 struct xhci_td
*td
, *tmp_td
;
1354 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1355 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
1356 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
1360 ep_ring
= xhci_virt_ep_to_ring(xhci
, ep
, stream_id
);
1362 xhci_warn(xhci
, "WARN Set TR deq ptr command for freed stream ID %u\n",
1364 /* XXX: Harmless??? */
1368 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep_index
);
1369 slot_ctx
= xhci_get_slot_ctx(xhci
, ep
->vdev
->out_ctx
);
1370 trace_xhci_handle_cmd_set_deq(slot_ctx
);
1371 trace_xhci_handle_cmd_set_deq_ep(ep_ctx
);
1373 if (cmd_comp_code
!= COMP_SUCCESS
) {
1374 unsigned int ep_state
;
1375 unsigned int slot_state
;
1377 switch (cmd_comp_code
) {
1378 case COMP_TRB_ERROR
:
1379 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1381 case COMP_CONTEXT_STATE_ERROR
:
1382 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1383 ep_state
= GET_EP_CTX_STATE(ep_ctx
);
1384 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
1385 slot_state
= GET_SLOT_STATE(slot_state
);
1386 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1387 "Slot state = %u, EP state = %u",
1388 slot_state
, ep_state
);
1390 case COMP_SLOT_NOT_ENABLED_ERROR
:
1391 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1395 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1399 /* OK what do we do now? The endpoint state is hosed, and we
1400 * should never get to this point if the synchronization between
1401 * queueing, and endpoint state are correct. This might happen
1402 * if the device gets disconnected after we've finished
1403 * cancelling URBs, which might not be an error...
1407 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1408 if (ep
->ep_state
& EP_HAS_STREAMS
) {
1409 struct xhci_stream_ctx
*ctx
=
1410 &ep
->stream_info
->stream_ctx_array
[stream_id
];
1411 deq
= le64_to_cpu(ctx
->stream_ring
) & SCTX_DEQ_MASK
;
1413 deq
= le64_to_cpu(ep_ctx
->deq
) & ~EP_CTX_CYCLE_MASK
;
1415 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1416 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq
);
1417 if (xhci_trb_virt_to_dma(ep
->queued_deq_seg
,
1418 ep
->queued_deq_ptr
) == deq
) {
1419 /* Update the ring's dequeue segment and dequeue pointer
1420 * to reflect the new position.
1422 update_ring_for_set_deq_completion(xhci
, ep
->vdev
,
1425 xhci_warn(xhci
, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1426 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
1427 ep
->queued_deq_seg
, ep
->queued_deq_ptr
);
1430 /* HW cached TDs cleared from cache, give them back */
1431 list_for_each_entry_safe(td
, tmp_td
, &ep
->cancelled_td_list
,
1432 cancelled_td_list
) {
1433 ep_ring
= xhci_urb_to_transfer_ring(ep
->xhci
, td
->urb
);
1434 if (td
->cancel_status
== TD_CLEARING_CACHE
) {
1435 td
->cancel_status
= TD_CLEARED
;
1436 xhci_dbg(ep
->xhci
, "%s: Giveback cancelled URB %p TD\n",
1438 xhci_td_cleanup(ep
->xhci
, td
, ep_ring
, td
->status
);
1440 xhci_dbg(ep
->xhci
, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1441 __func__
, td
->urb
, td
->cancel_status
);
1445 ep
->ep_state
&= ~SET_DEQ_PENDING
;
1446 ep
->queued_deq_seg
= NULL
;
1447 ep
->queued_deq_ptr
= NULL
;
1448 /* Restart any rings with pending URBs */
1449 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1452 static void xhci_handle_cmd_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
1453 union xhci_trb
*trb
, u32 cmd_comp_code
)
1455 struct xhci_virt_ep
*ep
;
1456 struct xhci_ep_ctx
*ep_ctx
;
1457 unsigned int ep_index
;
1459 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1460 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
1464 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep_index
);
1465 trace_xhci_handle_cmd_reset_ep(ep_ctx
);
1467 /* This command will only fail if the endpoint wasn't halted,
1468 * but we don't care.
1470 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
1471 "Ignoring reset ep completion code of %u", cmd_comp_code
);
1473 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1474 xhci_invalidate_cancelled_tds(ep
);
1476 /* Clear our internal halted state */
1477 ep
->ep_state
&= ~EP_HALTED
;
1479 xhci_giveback_invalidated_tds(ep
);
1481 /* if this was a soft reset, then restart */
1482 if ((le32_to_cpu(trb
->generic
.field
[3])) & TRB_TSP
)
1483 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1486 static void xhci_handle_cmd_enable_slot(struct xhci_hcd
*xhci
, int slot_id
,
1487 struct xhci_command
*command
, u32 cmd_comp_code
)
1489 if (cmd_comp_code
== COMP_SUCCESS
)
1490 command
->slot_id
= slot_id
;
1492 command
->slot_id
= 0;
1495 static void xhci_handle_cmd_disable_slot(struct xhci_hcd
*xhci
, int slot_id
)
1497 struct xhci_virt_device
*virt_dev
;
1498 struct xhci_slot_ctx
*slot_ctx
;
1500 virt_dev
= xhci
->devs
[slot_id
];
1504 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
1505 trace_xhci_handle_cmd_disable_slot(slot_ctx
);
1507 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1508 /* Delete default control endpoint resources */
1509 xhci_free_device_endpoint_resources(xhci
, virt_dev
, true);
1512 static void xhci_handle_cmd_config_ep(struct xhci_hcd
*xhci
, int slot_id
,
1515 struct xhci_virt_device
*virt_dev
;
1516 struct xhci_input_control_ctx
*ctrl_ctx
;
1517 struct xhci_ep_ctx
*ep_ctx
;
1518 unsigned int ep_index
;
1522 * Configure endpoint commands can come from the USB core configuration
1523 * or alt setting changes, or when streams were being configured.
1526 virt_dev
= xhci
->devs
[slot_id
];
1529 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
1531 xhci_warn(xhci
, "Could not get input context, bad type.\n");
1535 add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1537 /* Input ctx add_flags are the endpoint index plus one */
1538 ep_index
= xhci_last_valid_endpoint(add_flags
) - 1;
1540 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->out_ctx
, ep_index
);
1541 trace_xhci_handle_cmd_config_ep(ep_ctx
);
1546 static void xhci_handle_cmd_addr_dev(struct xhci_hcd
*xhci
, int slot_id
)
1548 struct xhci_virt_device
*vdev
;
1549 struct xhci_slot_ctx
*slot_ctx
;
1551 vdev
= xhci
->devs
[slot_id
];
1554 slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->out_ctx
);
1555 trace_xhci_handle_cmd_addr_dev(slot_ctx
);
1558 static void xhci_handle_cmd_reset_dev(struct xhci_hcd
*xhci
, int slot_id
)
1560 struct xhci_virt_device
*vdev
;
1561 struct xhci_slot_ctx
*slot_ctx
;
1563 vdev
= xhci
->devs
[slot_id
];
1565 xhci_warn(xhci
, "Reset device command completion for disabled slot %u\n",
1569 slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->out_ctx
);
1570 trace_xhci_handle_cmd_reset_dev(slot_ctx
);
1572 xhci_dbg(xhci
, "Completed reset device command.\n");
1575 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd
*xhci
,
1576 struct xhci_event_cmd
*event
)
1578 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1579 xhci_warn(xhci
, "WARN NEC_GET_FW command on non-NEC host\n");
1582 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1583 "NEC firmware version %2x.%02x",
1584 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1585 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1588 static void xhci_complete_del_and_free_cmd(struct xhci_command
*cmd
, u32 status
)
1590 list_del(&cmd
->cmd_list
);
1592 if (cmd
->completion
) {
1593 cmd
->status
= status
;
1594 complete(cmd
->completion
);
1600 void xhci_cleanup_command_queue(struct xhci_hcd
*xhci
)
1602 struct xhci_command
*cur_cmd
, *tmp_cmd
;
1603 xhci
->current_cmd
= NULL
;
1604 list_for_each_entry_safe(cur_cmd
, tmp_cmd
, &xhci
->cmd_list
, cmd_list
)
1605 xhci_complete_del_and_free_cmd(cur_cmd
, COMP_COMMAND_ABORTED
);
1608 void xhci_handle_command_timeout(struct work_struct
*work
)
1610 struct xhci_hcd
*xhci
;
1611 unsigned long flags
;
1612 char str
[XHCI_MSG_MAX
];
1617 xhci
= container_of(to_delayed_work(work
), struct xhci_hcd
, cmd_timer
);
1619 spin_lock_irqsave(&xhci
->lock
, flags
);
1622 * If timeout work is pending, or current_cmd is NULL, it means we
1623 * raced with command completion. Command is handled so just return.
1625 if (!xhci
->current_cmd
|| delayed_work_pending(&xhci
->cmd_timer
)) {
1626 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1630 cmd_field3
= le32_to_cpu(xhci
->current_cmd
->command_trb
->generic
.field
[3]);
1631 usbsts
= readl(&xhci
->op_regs
->status
);
1632 xhci_dbg(xhci
, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str
, usbsts
));
1634 /* Bail out and tear down xhci if a stop endpoint command failed */
1635 if (TRB_FIELD_TO_TYPE(cmd_field3
) == TRB_STOP_RING
) {
1636 struct xhci_virt_ep
*ep
;
1638 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command\n");
1640 ep
= xhci_get_virt_ep(xhci
, TRB_TO_SLOT_ID(cmd_field3
),
1641 TRB_TO_EP_INDEX(cmd_field3
));
1643 ep
->ep_state
&= ~EP_STOP_CMD_PENDING
;
1647 goto time_out_completed
;
1650 /* mark this command to be cancelled */
1651 xhci
->current_cmd
->status
= COMP_COMMAND_ABORTED
;
1653 /* Make sure command ring is running before aborting it */
1654 hw_ring_state
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
1655 if (hw_ring_state
== ~(u64
)0) {
1657 goto time_out_completed
;
1660 if ((xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
) &&
1661 (hw_ring_state
& CMD_RING_RUNNING
)) {
1662 /* Prevent new doorbell, and start command abort */
1663 xhci
->cmd_ring_state
= CMD_RING_STATE_ABORTED
;
1664 xhci_dbg(xhci
, "Command timeout\n");
1665 xhci_abort_cmd_ring(xhci
, flags
);
1666 goto time_out_completed
;
1669 /* host removed. Bail out */
1670 if (xhci
->xhc_state
& XHCI_STATE_REMOVING
) {
1671 xhci_dbg(xhci
, "host removed, ring start fail?\n");
1672 xhci_cleanup_command_queue(xhci
);
1674 goto time_out_completed
;
1677 /* command timeout on stopped ring, ring can't be aborted */
1678 xhci_dbg(xhci
, "Command timeout on stopped ring\n");
1679 xhci_handle_stopped_cmd_ring(xhci
, xhci
->current_cmd
);
1682 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1686 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1687 struct xhci_event_cmd
*event
)
1689 unsigned int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1691 dma_addr_t cmd_dequeue_dma
;
1693 union xhci_trb
*cmd_trb
;
1694 struct xhci_command
*cmd
;
1697 if (slot_id
>= MAX_HC_SLOTS
) {
1698 xhci_warn(xhci
, "Invalid slot_id %u\n", slot_id
);
1702 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1703 cmd_trb
= xhci
->cmd_ring
->dequeue
;
1705 trace_xhci_handle_command(xhci
->cmd_ring
, &cmd_trb
->generic
);
1707 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1710 * Check whether the completion event is for our internal kept
1713 if (!cmd_dequeue_dma
|| cmd_dma
!= (u64
)cmd_dequeue_dma
) {
1715 "ERROR mismatched command completion event\n");
1719 cmd
= list_first_entry(&xhci
->cmd_list
, struct xhci_command
, cmd_list
);
1721 cancel_delayed_work(&xhci
->cmd_timer
);
1723 cmd_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1725 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1726 if (cmd_comp_code
== COMP_COMMAND_RING_STOPPED
) {
1727 complete_all(&xhci
->cmd_ring_stop_completion
);
1731 if (cmd
->command_trb
!= xhci
->cmd_ring
->dequeue
) {
1733 "Command completion event does not match command\n");
1738 * Host aborted the command ring, check if the current command was
1739 * supposed to be aborted, otherwise continue normally.
1740 * The command ring is stopped now, but the xHC will issue a Command
1741 * Ring Stopped event which will cause us to restart it.
1743 if (cmd_comp_code
== COMP_COMMAND_ABORTED
) {
1744 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
1745 if (cmd
->status
== COMP_COMMAND_ABORTED
) {
1746 if (xhci
->current_cmd
== cmd
)
1747 xhci
->current_cmd
= NULL
;
1752 cmd_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb
->generic
.field
[3]));
1754 case TRB_ENABLE_SLOT
:
1755 xhci_handle_cmd_enable_slot(xhci
, slot_id
, cmd
, cmd_comp_code
);
1757 case TRB_DISABLE_SLOT
:
1758 xhci_handle_cmd_disable_slot(xhci
, slot_id
);
1761 if (!cmd
->completion
)
1762 xhci_handle_cmd_config_ep(xhci
, slot_id
, cmd_comp_code
);
1764 case TRB_EVAL_CONTEXT
:
1767 xhci_handle_cmd_addr_dev(xhci
, slot_id
);
1770 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1771 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1772 if (!cmd
->completion
)
1773 xhci_handle_cmd_stop_ep(xhci
, slot_id
, cmd_trb
,
1777 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1778 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1779 xhci_handle_cmd_set_deq(xhci
, slot_id
, cmd_trb
, cmd_comp_code
);
1782 /* Is this an aborted command turned to NO-OP? */
1783 if (cmd
->status
== COMP_COMMAND_RING_STOPPED
)
1784 cmd_comp_code
= COMP_COMMAND_RING_STOPPED
;
1787 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1788 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1789 xhci_handle_cmd_reset_ep(xhci
, slot_id
, cmd_trb
, cmd_comp_code
);
1792 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1793 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1795 slot_id
= TRB_TO_SLOT_ID(
1796 le32_to_cpu(cmd_trb
->generic
.field
[3]));
1797 xhci_handle_cmd_reset_dev(xhci
, slot_id
);
1799 case TRB_NEC_GET_FW
:
1800 xhci_handle_cmd_nec_get_fw(xhci
, event
);
1803 /* Skip over unknown commands on the event ring */
1804 xhci_info(xhci
, "INFO unknown command type %d\n", cmd_type
);
1808 /* restart timer if this wasn't the last command */
1809 if (!list_is_singular(&xhci
->cmd_list
)) {
1810 xhci
->current_cmd
= list_first_entry(&cmd
->cmd_list
,
1811 struct xhci_command
, cmd_list
);
1812 xhci_mod_cmd_timer(xhci
);
1813 } else if (xhci
->current_cmd
== cmd
) {
1814 xhci
->current_cmd
= NULL
;
1818 xhci_complete_del_and_free_cmd(cmd
, cmd_comp_code
);
1820 inc_deq(xhci
, xhci
->cmd_ring
);
1823 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1824 union xhci_trb
*event
, u32 trb_type
)
1826 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1827 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1828 handle_cmd_completion(xhci
, &event
->event_cmd
);
1831 static void handle_device_notification(struct xhci_hcd
*xhci
,
1832 union xhci_trb
*event
)
1835 struct usb_device
*udev
;
1837 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->generic
.field
[3]));
1838 if (!xhci
->devs
[slot_id
]) {
1839 xhci_warn(xhci
, "Device Notification event for "
1840 "unused slot %u\n", slot_id
);
1844 xhci_dbg(xhci
, "Device Wake Notification event for slot ID %u\n",
1846 udev
= xhci
->devs
[slot_id
]->udev
;
1847 if (udev
&& udev
->parent
)
1848 usb_wakeup_notification(udev
->parent
, udev
->portnum
);
1852 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1854 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1855 * If a connection to a USB 1 device is followed by another connection
1856 * to a USB 2 device.
1858 * Reset the PHY after the USB device is disconnected if device speed
1859 * is less than HCD_USB3.
1860 * Retry the reset sequence max of 4 times checking the PLL lock status.
1863 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd
*xhci
)
1865 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
1867 u32 retry_count
= 4;
1870 /* Assert PHY reset */
1871 writel(0x6F, hcd
->regs
+ 0x1048);
1873 /* De-assert the PHY reset */
1874 writel(0x7F, hcd
->regs
+ 0x1048);
1876 pll_lock_check
= readl(hcd
->regs
+ 0x1070);
1877 } while (!(pll_lock_check
& 0x1) && --retry_count
);
1880 static void handle_port_status(struct xhci_hcd
*xhci
,
1881 struct xhci_interrupter
*ir
,
1882 union xhci_trb
*event
)
1884 struct usb_hcd
*hcd
;
1886 u32 portsc
, cmd_reg
;
1888 unsigned int hcd_portnum
;
1889 struct xhci_bus_state
*bus_state
;
1890 bool bogus_port_status
= false;
1891 struct xhci_port
*port
;
1893 /* Port status change events always have a successful completion code */
1894 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
)
1896 "WARN: xHC returned failed port status event\n");
1898 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1899 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1901 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1902 xhci_warn(xhci
, "Port change event with invalid port ID %d\n",
1907 port
= &xhci
->hw_ports
[port_id
- 1];
1908 if (!port
|| !port
->rhub
|| port
->hcd_portnum
== DUPLICATE_ENTRY
) {
1909 xhci_warn(xhci
, "Port change event, no port for port ID %u\n",
1911 bogus_port_status
= true;
1915 /* We might get interrupts after shared_hcd is removed */
1916 if (port
->rhub
== &xhci
->usb3_rhub
&& xhci
->shared_hcd
== NULL
) {
1917 xhci_dbg(xhci
, "ignore port event for removed USB3 hcd\n");
1918 bogus_port_status
= true;
1922 hcd
= port
->rhub
->hcd
;
1923 bus_state
= &port
->rhub
->bus_state
;
1924 hcd_portnum
= port
->hcd_portnum
;
1925 portsc
= readl(port
->addr
);
1927 xhci_dbg(xhci
, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1928 hcd
->self
.busnum
, hcd_portnum
+ 1, port_id
, portsc
);
1930 trace_xhci_handle_port_status(port
, portsc
);
1932 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1933 xhci_dbg(xhci
, "resume root hub\n");
1934 usb_hcd_resume_root_hub(hcd
);
1937 if (hcd
->speed
>= HCD_USB3
&&
1938 (portsc
& PORT_PLS_MASK
) == XDEV_INACTIVE
) {
1939 if (port
->slot_id
&& xhci
->devs
[port
->slot_id
])
1940 xhci
->devs
[port
->slot_id
]->flags
|= VDEV_PORT_ERROR
;
1943 if ((portsc
& PORT_PLC
) && (portsc
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1944 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1946 cmd_reg
= readl(&xhci
->op_regs
->command
);
1947 if (!(cmd_reg
& CMD_RUN
)) {
1948 xhci_warn(xhci
, "xHC is not running.\n");
1952 if (DEV_SUPERSPEED_ANY(portsc
)) {
1953 xhci_dbg(xhci
, "remote wake SS port %d\n", port_id
);
1954 /* Set a flag to say the port signaled remote wakeup,
1955 * so we can tell the difference between the end of
1956 * device and host initiated resume.
1958 bus_state
->port_remote_wakeup
|= 1 << hcd_portnum
;
1959 xhci_test_and_clear_bit(xhci
, port
, PORT_PLC
);
1960 usb_hcd_start_port_resume(&hcd
->self
, hcd_portnum
);
1961 xhci_set_link_state(xhci
, port
, XDEV_U0
);
1962 /* Need to wait until the next link state change
1963 * indicates the device is actually in U0.
1965 bogus_port_status
= true;
1967 } else if (!test_bit(hcd_portnum
, &bus_state
->resuming_ports
)) {
1968 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1969 port
->resume_timestamp
= jiffies
+
1970 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
1971 set_bit(hcd_portnum
, &bus_state
->resuming_ports
);
1972 /* Do the rest in GetPortStatus after resume time delay.
1973 * Avoid polling roothub status before that so that a
1974 * usb device auto-resume latency around ~40ms.
1976 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1977 mod_timer(&hcd
->rh_timer
,
1978 port
->resume_timestamp
);
1979 usb_hcd_start_port_resume(&hcd
->self
, hcd_portnum
);
1980 bogus_port_status
= true;
1984 if ((portsc
& PORT_PLC
) &&
1985 DEV_SUPERSPEED_ANY(portsc
) &&
1986 ((portsc
& PORT_PLS_MASK
) == XDEV_U0
||
1987 (portsc
& PORT_PLS_MASK
) == XDEV_U1
||
1988 (portsc
& PORT_PLS_MASK
) == XDEV_U2
)) {
1989 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1990 complete(&port
->u3exit_done
);
1991 /* We've just brought the device into U0/1/2 through either the
1992 * Resume state after a device remote wakeup, or through the
1993 * U3Exit state after a host-initiated resume. If it's a device
1994 * initiated remote wake, don't pass up the link state change,
1995 * so the roothub behavior is consistent with external
1996 * USB 3.0 hub behavior.
1998 if (port
->slot_id
&& xhci
->devs
[port
->slot_id
])
1999 xhci_ring_device(xhci
, port
->slot_id
);
2000 if (bus_state
->port_remote_wakeup
& (1 << hcd_portnum
)) {
2001 xhci_test_and_clear_bit(xhci
, port
, PORT_PLC
);
2002 usb_wakeup_notification(hcd
->self
.root_hub
,
2004 bogus_port_status
= true;
2010 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
2011 * RExit to a disconnect state). If so, let the driver know it's
2012 * out of the RExit state.
2014 if (hcd
->speed
< HCD_USB3
&& port
->rexit_active
) {
2015 complete(&port
->rexit_done
);
2016 port
->rexit_active
= false;
2017 bogus_port_status
= true;
2021 if (hcd
->speed
< HCD_USB3
) {
2022 xhci_test_and_clear_bit(xhci
, port
, PORT_PLC
);
2023 if ((xhci
->quirks
& XHCI_RESET_PLL_ON_DISCONNECT
) &&
2024 (portsc
& PORT_CSC
) && !(portsc
& PORT_CONNECT
))
2025 xhci_cavium_reset_phy_quirk(xhci
);
2030 /* Don't make the USB core poll the roothub if we got a bad port status
2031 * change event. Besides, at that point we can't tell which roothub
2032 * (USB 2.0 or USB 3.0) to kick.
2034 if (bogus_port_status
)
2038 * xHCI port-status-change events occur when the "or" of all the
2039 * status-change bits in the portsc register changes from 0 to 1.
2040 * New status changes won't cause an event if any other change
2041 * bits are still set. When an event occurs, switch over to
2042 * polling to avoid losing status changes.
2044 xhci_dbg(xhci
, "%s: starting usb%d port polling.\n",
2045 __func__
, hcd
->self
.busnum
);
2046 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
2047 spin_unlock(&xhci
->lock
);
2048 /* Pass this up to the core */
2049 usb_hcd_poll_rh_status(hcd
);
2050 spin_lock(&xhci
->lock
);
2054 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2055 * at end_trb, which may be in another segment. If the suspect DMA address is a
2056 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2059 struct xhci_segment
*trb_in_td(struct xhci_hcd
*xhci
,
2060 struct xhci_segment
*start_seg
,
2061 union xhci_trb
*start_trb
,
2062 union xhci_trb
*end_trb
,
2063 dma_addr_t suspect_dma
,
2066 dma_addr_t start_dma
;
2067 dma_addr_t end_seg_dma
;
2068 dma_addr_t end_trb_dma
;
2069 struct xhci_segment
*cur_seg
;
2071 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
2072 cur_seg
= start_seg
;
2077 /* We may get an event for a Link TRB in the middle of a TD */
2078 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
2079 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
2080 /* If the end TRB isn't in this segment, this is set to 0 */
2081 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
2085 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2086 (unsigned long long)suspect_dma
,
2087 (unsigned long long)start_dma
,
2088 (unsigned long long)end_trb_dma
,
2089 (unsigned long long)cur_seg
->dma
,
2090 (unsigned long long)end_seg_dma
);
2092 if (end_trb_dma
> 0) {
2093 /* The end TRB is in this segment, so suspect should be here */
2094 if (start_dma
<= end_trb_dma
) {
2095 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
2098 /* Case for one segment with
2099 * a TD wrapped around to the top
2101 if ((suspect_dma
>= start_dma
&&
2102 suspect_dma
<= end_seg_dma
) ||
2103 (suspect_dma
>= cur_seg
->dma
&&
2104 suspect_dma
<= end_trb_dma
))
2109 /* Might still be somewhere in this segment */
2110 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
2113 cur_seg
= cur_seg
->next
;
2114 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
2115 } while (cur_seg
!= start_seg
);
2120 static void xhci_clear_hub_tt_buffer(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2121 struct xhci_virt_ep
*ep
)
2124 * As part of low/full-speed endpoint-halt processing
2125 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2127 if (td
->urb
->dev
->tt
&& !usb_pipeint(td
->urb
->pipe
) &&
2128 (td
->urb
->dev
->tt
->hub
!= xhci_to_hcd(xhci
)->self
.root_hub
) &&
2129 !(ep
->ep_state
& EP_CLEARING_TT
)) {
2130 ep
->ep_state
|= EP_CLEARING_TT
;
2131 td
->urb
->ep
->hcpriv
= td
->urb
->dev
;
2132 if (usb_hub_clear_tt_buffer(td
->urb
))
2133 ep
->ep_state
&= ~EP_CLEARING_TT
;
2137 /* Check if an error has halted the endpoint ring. The class driver will
2138 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2139 * However, a babble and other errors also halt the endpoint ring, and the class
2140 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2141 * Ring Dequeue Pointer command manually.
2143 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
2144 struct xhci_ep_ctx
*ep_ctx
,
2145 unsigned int trb_comp_code
)
2147 /* TRB completion codes that may require a manual halt cleanup */
2148 if (trb_comp_code
== COMP_USB_TRANSACTION_ERROR
||
2149 trb_comp_code
== COMP_BABBLE_DETECTED_ERROR
||
2150 trb_comp_code
== COMP_SPLIT_TRANSACTION_ERROR
)
2151 /* The 0.95 spec says a babbling control endpoint
2152 * is not halted. The 0.96 spec says it is. Some HW
2153 * claims to be 0.95 compliant, but it halts the control
2154 * endpoint anyway. Check if a babble halted the
2157 if (GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_HALTED
)
2163 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
2165 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
2166 /* Vendor defined "informational" completion code,
2167 * treat as not-an-error.
2169 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
2171 xhci_dbg(xhci
, "Treating code as success.\n");
2177 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_virt_ep
*ep
,
2178 struct xhci_ring
*ep_ring
, struct xhci_td
*td
,
2181 struct xhci_ep_ctx
*ep_ctx
;
2183 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep
->ep_index
);
2185 switch (trb_comp_code
) {
2186 case COMP_STOPPED_LENGTH_INVALID
:
2187 case COMP_STOPPED_SHORT_PACKET
:
2190 * The "Stop Endpoint" completion will take care of any
2191 * stopped TDs. A stopped TD may be restarted, so don't update
2192 * the ring dequeue pointer or take this TD off any lists yet.
2195 case COMP_USB_TRANSACTION_ERROR
:
2196 case COMP_BABBLE_DETECTED_ERROR
:
2197 case COMP_SPLIT_TRANSACTION_ERROR
:
2199 * If endpoint context state is not halted we might be
2200 * racing with a reset endpoint command issued by a unsuccessful
2201 * stop endpoint completion (context error). In that case the
2202 * td should be on the cancelled list, and EP_HALTED flag set.
2204 * Or then it's not halted due to the 0.95 spec stating that a
2205 * babbling control endpoint should not halt. The 0.96 spec
2206 * again says it should. Some HW claims to be 0.95 compliant,
2207 * but it halts the control endpoint anyway.
2209 if (GET_EP_CTX_STATE(ep_ctx
) != EP_STATE_HALTED
) {
2211 * If EP_HALTED is set and TD is on the cancelled list
2212 * the TD and dequeue pointer will be handled by reset
2213 * ep command completion
2215 if ((ep
->ep_state
& EP_HALTED
) &&
2216 !list_empty(&td
->cancelled_td_list
)) {
2217 xhci_dbg(xhci
, "Already resolving halted ep for 0x%llx\n",
2218 (unsigned long long)xhci_trb_virt_to_dma(
2219 td
->start_seg
, td
->first_trb
));
2222 /* endpoint not halted, don't reset it */
2225 /* Almost same procedure as for STALL_ERROR below */
2226 xhci_clear_hub_tt_buffer(xhci
, td
, ep
);
2227 xhci_handle_halted_endpoint(xhci
, ep
, td
, EP_HARD_RESET
);
2229 case COMP_STALL_ERROR
:
2231 * xhci internal endpoint state will go to a "halt" state for
2232 * any stall, including default control pipe protocol stall.
2233 * To clear the host side halt we need to issue a reset endpoint
2234 * command, followed by a set dequeue command to move past the
2236 * Class drivers clear the device side halt from a functional
2237 * stall later. Hub TT buffer should only be cleared for FS/LS
2238 * devices behind HS hubs for functional stalls.
2240 if (ep
->ep_index
!= 0)
2241 xhci_clear_hub_tt_buffer(xhci
, td
, ep
);
2243 xhci_handle_halted_endpoint(xhci
, ep
, td
, EP_HARD_RESET
);
2245 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2250 /* Update ring dequeue pointer */
2251 ep_ring
->dequeue
= td
->last_trb
;
2252 ep_ring
->deq_seg
= td
->last_trb_seg
;
2253 inc_deq(xhci
, ep_ring
);
2255 return xhci_td_cleanup(xhci
, td
, ep_ring
, td
->status
);
2258 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2259 static int sum_trb_lengths(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2260 union xhci_trb
*stop_trb
)
2263 union xhci_trb
*trb
= ring
->dequeue
;
2264 struct xhci_segment
*seg
= ring
->deq_seg
;
2266 for (sum
= 0; trb
!= stop_trb
; next_trb(xhci
, ring
, &seg
, &trb
)) {
2267 if (!trb_is_noop(trb
) && !trb_is_link(trb
))
2268 sum
+= TRB_LEN(le32_to_cpu(trb
->generic
.field
[2]));
2274 * Process control tds, update urb status and actual_length.
2276 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_virt_ep
*ep
,
2277 struct xhci_ring
*ep_ring
, struct xhci_td
*td
,
2278 union xhci_trb
*ep_trb
, struct xhci_transfer_event
*event
)
2280 struct xhci_ep_ctx
*ep_ctx
;
2282 u32 remaining
, requested
;
2285 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb
->generic
.field
[3]));
2286 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep
->ep_index
);
2287 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2288 requested
= td
->urb
->transfer_buffer_length
;
2289 remaining
= EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2291 switch (trb_comp_code
) {
2293 if (trb_type
!= TRB_STATUS
) {
2294 xhci_warn(xhci
, "WARN: Success on ctrl %s TRB without IOC set?\n",
2295 (trb_type
== TRB_DATA
) ? "data" : "setup");
2296 td
->status
= -ESHUTDOWN
;
2301 case COMP_SHORT_PACKET
:
2304 case COMP_STOPPED_SHORT_PACKET
:
2305 if (trb_type
== TRB_DATA
|| trb_type
== TRB_NORMAL
)
2306 td
->urb
->actual_length
= remaining
;
2308 xhci_warn(xhci
, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2313 td
->urb
->actual_length
= 0;
2317 td
->urb
->actual_length
= requested
- remaining
;
2320 td
->urb
->actual_length
= requested
;
2323 xhci_warn(xhci
, "WARN: unexpected TRB Type %d\n",
2327 case COMP_STOPPED_LENGTH_INVALID
:
2330 if (!xhci_requires_manual_halt_cleanup(xhci
,
2331 ep_ctx
, trb_comp_code
))
2333 xhci_dbg(xhci
, "TRB error %u, halted endpoint index = %u\n",
2334 trb_comp_code
, ep
->ep_index
);
2336 case COMP_STALL_ERROR
:
2337 /* Did we transfer part of the data (middle) phase? */
2338 if (trb_type
== TRB_DATA
|| trb_type
== TRB_NORMAL
)
2339 td
->urb
->actual_length
= requested
- remaining
;
2340 else if (!td
->urb_length_set
)
2341 td
->urb
->actual_length
= 0;
2345 /* stopped at setup stage, no data transferred */
2346 if (trb_type
== TRB_SETUP
)
2350 * if on data stage then update the actual_length of the URB and flag it
2351 * as set, so it won't be overwritten in the event for the last TRB.
2353 if (trb_type
== TRB_DATA
||
2354 trb_type
== TRB_NORMAL
) {
2355 td
->urb_length_set
= true;
2356 td
->urb
->actual_length
= requested
- remaining
;
2357 xhci_dbg(xhci
, "Waiting for status stage event\n");
2361 /* at status stage */
2362 if (!td
->urb_length_set
)
2363 td
->urb
->actual_length
= requested
;
2366 return finish_td(xhci
, ep
, ep_ring
, td
, trb_comp_code
);
2370 * Process isochronous tds, update urb packet status and actual_length.
2372 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_virt_ep
*ep
,
2373 struct xhci_ring
*ep_ring
, struct xhci_td
*td
,
2374 union xhci_trb
*ep_trb
, struct xhci_transfer_event
*event
)
2376 struct urb_priv
*urb_priv
;
2378 struct usb_iso_packet_descriptor
*frame
;
2380 bool sum_trbs_for_length
= false;
2381 u32 remaining
, requested
, ep_trb_len
;
2382 int short_framestatus
;
2384 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2385 urb_priv
= td
->urb
->hcpriv
;
2386 idx
= urb_priv
->num_tds_done
;
2387 frame
= &td
->urb
->iso_frame_desc
[idx
];
2388 requested
= frame
->length
;
2389 remaining
= EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2390 ep_trb_len
= TRB_LEN(le32_to_cpu(ep_trb
->generic
.field
[2]));
2391 short_framestatus
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
2394 /* handle completion code */
2395 switch (trb_comp_code
) {
2397 /* Don't overwrite status if TD had an error, see xHCI 4.9.1 */
2398 if (td
->error_mid_td
)
2401 frame
->status
= short_framestatus
;
2402 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
)
2403 sum_trbs_for_length
= true;
2408 case COMP_SHORT_PACKET
:
2409 frame
->status
= short_framestatus
;
2410 sum_trbs_for_length
= true;
2412 case COMP_BANDWIDTH_OVERRUN_ERROR
:
2413 frame
->status
= -ECOMM
;
2415 case COMP_BABBLE_DETECTED_ERROR
:
2416 sum_trbs_for_length
= true;
2418 case COMP_ISOCH_BUFFER_OVERRUN
:
2419 frame
->status
= -EOVERFLOW
;
2420 if (ep_trb
!= td
->last_trb
)
2421 td
->error_mid_td
= true;
2423 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
2424 case COMP_STALL_ERROR
:
2425 frame
->status
= -EPROTO
;
2427 case COMP_USB_TRANSACTION_ERROR
:
2428 frame
->status
= -EPROTO
;
2429 sum_trbs_for_length
= true;
2430 if (ep_trb
!= td
->last_trb
)
2431 td
->error_mid_td
= true;
2434 sum_trbs_for_length
= true;
2436 case COMP_STOPPED_SHORT_PACKET
:
2437 /* field normally containing residue now contains tranferred */
2438 frame
->status
= short_framestatus
;
2439 requested
= remaining
;
2441 case COMP_STOPPED_LENGTH_INVALID
:
2446 sum_trbs_for_length
= true;
2451 if (td
->urb_length_set
)
2454 if (sum_trbs_for_length
)
2455 frame
->actual_length
= sum_trb_lengths(xhci
, ep
->ring
, ep_trb
) +
2456 ep_trb_len
- remaining
;
2458 frame
->actual_length
= requested
;
2460 td
->urb
->actual_length
+= frame
->actual_length
;
2463 /* Don't give back TD yet if we encountered an error mid TD */
2464 if (td
->error_mid_td
&& ep_trb
!= td
->last_trb
) {
2465 xhci_dbg(xhci
, "Error mid isoc TD, wait for final completion event\n");
2466 td
->urb_length_set
= true;
2470 return finish_td(xhci
, ep
, ep_ring
, td
, trb_comp_code
);
2473 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2474 struct xhci_virt_ep
*ep
, int status
)
2476 struct urb_priv
*urb_priv
;
2477 struct usb_iso_packet_descriptor
*frame
;
2480 urb_priv
= td
->urb
->hcpriv
;
2481 idx
= urb_priv
->num_tds_done
;
2482 frame
= &td
->urb
->iso_frame_desc
[idx
];
2484 /* The transfer is partly done. */
2485 frame
->status
= -EXDEV
;
2487 /* calc actual length */
2488 frame
->actual_length
= 0;
2490 /* Update ring dequeue pointer */
2491 ep
->ring
->dequeue
= td
->last_trb
;
2492 ep
->ring
->deq_seg
= td
->last_trb_seg
;
2493 inc_deq(xhci
, ep
->ring
);
2495 return xhci_td_cleanup(xhci
, td
, ep
->ring
, status
);
2499 * Process bulk and interrupt tds, update urb status and actual_length.
2501 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_virt_ep
*ep
,
2502 struct xhci_ring
*ep_ring
, struct xhci_td
*td
,
2503 union xhci_trb
*ep_trb
, struct xhci_transfer_event
*event
)
2505 struct xhci_slot_ctx
*slot_ctx
;
2507 u32 remaining
, requested
, ep_trb_len
;
2509 slot_ctx
= xhci_get_slot_ctx(xhci
, ep
->vdev
->out_ctx
);
2510 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2511 remaining
= EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2512 ep_trb_len
= TRB_LEN(le32_to_cpu(ep_trb
->generic
.field
[2]));
2513 requested
= td
->urb
->transfer_buffer_length
;
2515 switch (trb_comp_code
) {
2518 /* handle success with untransferred data as short packet */
2519 if (ep_trb
!= td
->last_trb
|| remaining
) {
2520 xhci_warn(xhci
, "WARN Successful completion on short TX\n");
2521 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2522 td
->urb
->ep
->desc
.bEndpointAddress
,
2523 requested
, remaining
);
2527 case COMP_SHORT_PACKET
:
2528 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2529 td
->urb
->ep
->desc
.bEndpointAddress
,
2530 requested
, remaining
);
2533 case COMP_STOPPED_SHORT_PACKET
:
2534 td
->urb
->actual_length
= remaining
;
2536 case COMP_STOPPED_LENGTH_INVALID
:
2537 /* stopped on ep trb with invalid length, exclude it */
2541 case COMP_USB_TRANSACTION_ERROR
:
2542 if (xhci
->quirks
& XHCI_NO_SOFT_RETRY
||
2543 (ep
->err_count
++ > MAX_SOFT_RETRY
) ||
2544 le32_to_cpu(slot_ctx
->tt_info
) & TT_SLOT
)
2549 xhci_handle_halted_endpoint(xhci
, ep
, td
, EP_SOFT_RESET
);
2556 if (ep_trb
== td
->last_trb
)
2557 td
->urb
->actual_length
= requested
- remaining
;
2559 td
->urb
->actual_length
=
2560 sum_trb_lengths(xhci
, ep_ring
, ep_trb
) +
2561 ep_trb_len
- remaining
;
2563 if (remaining
> requested
) {
2564 xhci_warn(xhci
, "bad transfer trb length %d in event trb\n",
2566 td
->urb
->actual_length
= 0;
2569 return finish_td(xhci
, ep
, ep_ring
, td
, trb_comp_code
);
2573 * If this function returns an error condition, it means it got a Transfer
2574 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2575 * At this point, the host controller is probably hosed and should be reset.
2577 static int handle_tx_event(struct xhci_hcd
*xhci
,
2578 struct xhci_interrupter
*ir
,
2579 struct xhci_transfer_event
*event
)
2581 struct xhci_virt_ep
*ep
;
2582 struct xhci_ring
*ep_ring
;
2583 unsigned int slot_id
;
2585 struct xhci_td
*td
= NULL
;
2586 dma_addr_t ep_trb_dma
;
2587 struct xhci_segment
*ep_seg
;
2588 union xhci_trb
*ep_trb
;
2589 int status
= -EINPROGRESS
;
2590 struct xhci_ep_ctx
*ep_ctx
;
2593 bool handling_skipped_tds
= false;
2595 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2596 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2597 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2598 ep_trb_dma
= le64_to_cpu(event
->buffer
);
2600 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
2602 xhci_err(xhci
, "ERROR Invalid Transfer event\n");
2606 ep_ring
= xhci_dma_to_transfer_ring(ep
, ep_trb_dma
);
2607 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep_index
);
2609 if (GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_DISABLED
) {
2611 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2616 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2618 switch (trb_comp_code
) {
2619 case COMP_STALL_ERROR
:
2620 case COMP_USB_TRANSACTION_ERROR
:
2621 case COMP_INVALID_STREAM_TYPE_ERROR
:
2622 case COMP_INVALID_STREAM_ID_ERROR
:
2623 xhci_dbg(xhci
, "Stream transaction error ep %u no id\n",
2625 if (ep
->err_count
++ > MAX_SOFT_RETRY
)
2626 xhci_handle_halted_endpoint(xhci
, ep
, NULL
,
2629 xhci_handle_halted_endpoint(xhci
, ep
, NULL
,
2632 case COMP_RING_UNDERRUN
:
2633 case COMP_RING_OVERRUN
:
2634 case COMP_STOPPED_LENGTH_INVALID
:
2637 xhci_err(xhci
, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2643 /* Count current td numbers if ep->skip is set */
2645 td_num
+= list_count_nodes(&ep_ring
->td_list
);
2647 /* Look for common error cases */
2648 switch (trb_comp_code
) {
2649 /* Skip codes that require special handling depending on
2653 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0)
2655 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
||
2656 ep_ring
->last_td_was_short
)
2657 trb_comp_code
= COMP_SHORT_PACKET
;
2659 xhci_warn_ratelimited(xhci
,
2660 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2663 case COMP_SHORT_PACKET
:
2665 /* Completion codes for endpoint stopped state */
2667 xhci_dbg(xhci
, "Stopped on Transfer TRB for slot %u ep %u\n",
2670 case COMP_STOPPED_LENGTH_INVALID
:
2672 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2675 case COMP_STOPPED_SHORT_PACKET
:
2677 "Stopped with short packet transfer detected for slot %u ep %u\n",
2680 /* Completion codes for endpoint halted state */
2681 case COMP_STALL_ERROR
:
2682 xhci_dbg(xhci
, "Stalled endpoint for slot %u ep %u\n", slot_id
,
2686 case COMP_SPLIT_TRANSACTION_ERROR
:
2687 xhci_dbg(xhci
, "Split transaction error for slot %u ep %u\n",
2691 case COMP_USB_TRANSACTION_ERROR
:
2692 xhci_dbg(xhci
, "Transfer error for slot %u ep %u on endpoint\n",
2696 case COMP_BABBLE_DETECTED_ERROR
:
2697 xhci_dbg(xhci
, "Babble error for slot %u ep %u on endpoint\n",
2699 status
= -EOVERFLOW
;
2701 /* Completion codes for endpoint error state */
2702 case COMP_TRB_ERROR
:
2704 "WARN: TRB error for slot %u ep %u on endpoint\n",
2708 /* completion codes not indicating endpoint state change */
2709 case COMP_DATA_BUFFER_ERROR
:
2711 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2715 case COMP_BANDWIDTH_OVERRUN_ERROR
:
2717 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2720 case COMP_ISOCH_BUFFER_OVERRUN
:
2722 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2725 case COMP_RING_UNDERRUN
:
2727 * When the Isoch ring is empty, the xHC will generate
2728 * a Ring Overrun Event for IN Isoch endpoint or Ring
2729 * Underrun Event for OUT Isoch endpoint.
2731 xhci_dbg(xhci
, "underrun event on endpoint\n");
2732 if (!list_empty(&ep_ring
->td_list
))
2733 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2734 "still with TDs queued?\n",
2735 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2738 case COMP_RING_OVERRUN
:
2739 xhci_dbg(xhci
, "overrun event on endpoint\n");
2740 if (!list_empty(&ep_ring
->td_list
))
2741 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2742 "still with TDs queued?\n",
2743 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2746 case COMP_MISSED_SERVICE_ERROR
:
2748 * When encounter missed service error, one or more isoc tds
2749 * may be missed by xHC.
2750 * Set skip flag of the ep_ring; Complete the missed tds as
2751 * short transfer when process the ep_ring next time.
2755 "Miss service interval error for slot %u ep %u, set skip flag\n",
2758 case COMP_NO_PING_RESPONSE_ERROR
:
2761 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2765 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
2766 /* needs disable slot command to recover */
2768 "WARN: detect an incompatible device for slot %u ep %u",
2773 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2778 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2779 trb_comp_code
, slot_id
, ep_index
);
2784 /* This TRB should be in the TD at the head of this ring's
2787 if (list_empty(&ep_ring
->td_list
)) {
2789 * Don't print wanings if it's due to a stopped endpoint
2790 * generating an extra completion event if the device
2791 * was suspended. Or, a event for the last TRB of a
2792 * short TD we already got a short event for.
2793 * The short TD is already removed from the TD list.
2796 if (!(trb_comp_code
== COMP_STOPPED
||
2797 trb_comp_code
== COMP_STOPPED_LENGTH_INVALID
||
2798 ep_ring
->last_td_was_short
)) {
2799 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2800 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2805 xhci_dbg(xhci
, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2808 if (trb_comp_code
== COMP_STALL_ERROR
||
2809 xhci_requires_manual_halt_cleanup(xhci
, ep_ctx
,
2811 xhci_handle_halted_endpoint(xhci
, ep
, NULL
,
2817 /* We've skipped all the TDs on the ep ring when ep->skip set */
2818 if (ep
->skip
&& td_num
== 0) {
2820 xhci_dbg(xhci
, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2825 td
= list_first_entry(&ep_ring
->td_list
, struct xhci_td
,
2830 /* Is this a TRB in the currently executing TD? */
2831 ep_seg
= trb_in_td(xhci
, td
->start_seg
, td
->first_trb
,
2832 td
->last_trb
, ep_trb_dma
, false);
2835 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2836 * is not in the current TD pointed by ep_ring->dequeue because
2837 * that the hardware dequeue pointer still at the previous TRB
2838 * of the current TD. The previous TRB maybe a Link TD or the
2839 * last TRB of the previous TD. The command completion handle
2840 * will take care the rest.
2842 if (!ep_seg
&& (trb_comp_code
== COMP_STOPPED
||
2843 trb_comp_code
== COMP_STOPPED_LENGTH_INVALID
)) {
2849 if (ep
->skip
&& usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2850 skip_isoc_td(xhci
, td
, ep
, status
);
2855 * Some hosts give a spurious success event after a short
2856 * transfer. Ignore it.
2858 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2859 ep_ring
->last_td_was_short
) {
2860 ep_ring
->last_td_was_short
= false;
2865 * xhci 4.10.2 states isoc endpoints should continue
2866 * processing the next TD if there was an error mid TD.
2867 * So host like NEC don't generate an event for the last
2868 * isoc TRB even if the IOC flag is set.
2869 * xhci 4.9.1 states that if there are errors in mult-TRB
2870 * TDs xHC should generate an error for that TRB, and if xHC
2871 * proceeds to the next TD it should genete an event for
2872 * any TRB with IOC flag on the way. Other host follow this.
2873 * So this event might be for the next TD.
2875 if (td
->error_mid_td
&&
2876 !list_is_last(&td
->td_list
, &ep_ring
->td_list
)) {
2877 struct xhci_td
*td_next
= list_next_entry(td
, td_list
);
2879 ep_seg
= trb_in_td(xhci
, td_next
->start_seg
, td_next
->first_trb
,
2880 td_next
->last_trb
, ep_trb_dma
, false);
2882 /* give back previous TD, start handling new */
2883 xhci_dbg(xhci
, "Missing TD completion event after mid TD error\n");
2884 ep_ring
->dequeue
= td
->last_trb
;
2885 ep_ring
->deq_seg
= td
->last_trb_seg
;
2886 inc_deq(xhci
, ep_ring
);
2887 xhci_td_cleanup(xhci
, td
, ep_ring
, td
->status
);
2893 /* HC is busted, give up! */
2895 "ERROR Transfer event TRB DMA ptr not "
2896 "part of current TD ep_index %d "
2897 "comp_code %u\n", ep_index
,
2899 trb_in_td(xhci
, td
->start_seg
, td
->first_trb
,
2900 td
->last_trb
, ep_trb_dma
, true);
2904 if (trb_comp_code
== COMP_SHORT_PACKET
)
2905 ep_ring
->last_td_was_short
= true;
2907 ep_ring
->last_td_was_short
= false;
2911 "Found td. Clear skip flag for slot %u ep %u.\n",
2916 ep_trb
= &ep_seg
->trbs
[(ep_trb_dma
- ep_seg
->dma
) /
2919 trace_xhci_handle_transfer(ep_ring
,
2920 (struct xhci_generic_trb
*) ep_trb
);
2923 * No-op TRB could trigger interrupts in a case where
2924 * a URB was killed and a STALL_ERROR happens right
2925 * after the endpoint ring stopped. Reset the halted
2926 * endpoint. Otherwise, the endpoint remains stalled
2930 if (trb_is_noop(ep_trb
)) {
2931 if (trb_comp_code
== COMP_STALL_ERROR
||
2932 xhci_requires_manual_halt_cleanup(xhci
, ep_ctx
,
2934 xhci_handle_halted_endpoint(xhci
, ep
, td
,
2939 td
->status
= status
;
2941 /* update the urb's actual_length and give back to the core */
2942 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2943 process_ctrl_td(xhci
, ep
, ep_ring
, td
, ep_trb
, event
);
2944 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2945 process_isoc_td(xhci
, ep
, ep_ring
, td
, ep_trb
, event
);
2947 process_bulk_intr_td(xhci
, ep
, ep_ring
, td
, ep_trb
, event
);
2949 handling_skipped_tds
= ep
->skip
&&
2950 trb_comp_code
!= COMP_MISSED_SERVICE_ERROR
&&
2951 trb_comp_code
!= COMP_NO_PING_RESPONSE_ERROR
;
2954 * If ep->skip is set, it means there are missed tds on the
2955 * endpoint ring need to take care of.
2956 * Process them as short transfer until reach the td pointed by
2959 } while (handling_skipped_tds
);
2964 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2965 (unsigned long long) xhci_trb_virt_to_dma(
2966 ir
->event_ring
->deq_seg
,
2967 ir
->event_ring
->dequeue
),
2968 lower_32_bits(le64_to_cpu(event
->buffer
)),
2969 upper_32_bits(le64_to_cpu(event
->buffer
)),
2970 le32_to_cpu(event
->transfer_len
),
2971 le32_to_cpu(event
->flags
));
2976 * This function handles one OS-owned event on the event ring. It may drop
2977 * xhci->lock between event processing (e.g. to pass up port status changes).
2979 static int xhci_handle_event_trb(struct xhci_hcd
*xhci
, struct xhci_interrupter
*ir
,
2980 union xhci_trb
*event
)
2984 trace_xhci_handle_event(ir
->event_ring
, &event
->generic
);
2987 * Barrier between reading the TRB_CYCLE (valid) flag before, and any
2988 * speculative reads of the event's flags/data below.
2991 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->event_cmd
.flags
));
2992 /* FIXME: Handle more event types. */
2995 case TRB_COMPLETION
:
2996 handle_cmd_completion(xhci
, &event
->event_cmd
);
2998 case TRB_PORT_STATUS
:
2999 handle_port_status(xhci
, ir
, event
);
3002 handle_tx_event(xhci
, ir
, &event
->trans_event
);
3005 handle_device_notification(xhci
, event
);
3008 if (trb_type
>= TRB_VENDOR_DEFINED_LOW
)
3009 handle_vendor_event(xhci
, event
, trb_type
);
3011 xhci_warn(xhci
, "ERROR unknown event type %d\n", trb_type
);
3013 /* Any of the above functions may drop and re-acquire the lock, so check
3014 * to make sure a watchdog timer didn't mark the host as non-responsive.
3016 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
3017 xhci_dbg(xhci
, "xHCI host dying, returning from event handler.\n");
3025 * Update Event Ring Dequeue Pointer:
3026 * - When all events have finished
3027 * - To avoid "Event Ring Full Error" condition
3029 static void xhci_update_erst_dequeue(struct xhci_hcd
*xhci
,
3030 struct xhci_interrupter
*ir
,
3036 temp_64
= xhci_read_64(xhci
, &ir
->ir_set
->erst_dequeue
);
3037 deq
= xhci_trb_virt_to_dma(ir
->event_ring
->deq_seg
,
3038 ir
->event_ring
->dequeue
);
3040 xhci_warn(xhci
, "WARN something wrong with SW event ring dequeue ptr\n");
3042 * Per 4.9.4, Software writes to the ERDP register shall always advance
3043 * the Event Ring Dequeue Pointer value.
3045 if ((temp_64
& ERST_PTR_MASK
) == (deq
& ERST_PTR_MASK
) && !clear_ehb
)
3048 /* Update HC event ring dequeue pointer */
3049 temp_64
= ir
->event_ring
->deq_seg
->num
& ERST_DESI_MASK
;
3050 temp_64
|= deq
& ERST_PTR_MASK
;
3052 /* Clear the event handler busy flag (RW1C) */
3054 temp_64
|= ERST_EHB
;
3055 xhci_write_64(xhci
, temp_64
, &ir
->ir_set
->erst_dequeue
);
3058 /* Clear the interrupt pending bit for a specific interrupter. */
3059 static void xhci_clear_interrupt_pending(struct xhci_hcd
*xhci
,
3060 struct xhci_interrupter
*ir
)
3062 if (!ir
->ip_autoclear
) {
3065 irq_pending
= readl(&ir
->ir_set
->irq_pending
);
3066 irq_pending
|= IMAN_IP
;
3067 writel(irq_pending
, &ir
->ir_set
->irq_pending
);
3072 * Handle all OS-owned events on an interrupter event ring. It may drop
3073 * and reaquire xhci->lock between event processing.
3075 static int xhci_handle_events(struct xhci_hcd
*xhci
, struct xhci_interrupter
*ir
)
3081 xhci_clear_interrupt_pending(xhci
, ir
);
3083 /* Event ring hasn't been allocated yet. */
3084 if (!ir
->event_ring
|| !ir
->event_ring
->dequeue
) {
3085 xhci_err(xhci
, "ERROR interrupter event ring not ready\n");
3089 if (xhci
->xhc_state
& XHCI_STATE_DYING
||
3090 xhci
->xhc_state
& XHCI_STATE_HALTED
) {
3091 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. Shouldn't IRQs be disabled?\n");
3093 /* Clear the event handler busy flag (RW1C) */
3094 temp
= xhci_read_64(xhci
, &ir
->ir_set
->erst_dequeue
);
3095 xhci_write_64(xhci
, temp
| ERST_EHB
, &ir
->ir_set
->erst_dequeue
);
3099 /* Process all OS owned event TRBs on this event ring */
3100 while (unhandled_event_trb(ir
->event_ring
)) {
3101 err
= xhci_handle_event_trb(xhci
, ir
, ir
->event_ring
->dequeue
);
3104 * If half a segment of events have been handled in one go then
3105 * update ERDP, and force isoc trbs to interrupt more often
3107 if (event_loop
++ > TRBS_PER_SEGMENT
/ 2) {
3108 xhci_update_erst_dequeue(xhci
, ir
, false);
3110 if (ir
->isoc_bei_interval
> AVOID_BEI_INTERVAL_MIN
)
3111 ir
->isoc_bei_interval
= ir
->isoc_bei_interval
/ 2;
3116 /* Update SW event ring dequeue pointer */
3117 inc_deq(xhci
, ir
->event_ring
);
3123 xhci_update_erst_dequeue(xhci
, ir
, true);
3129 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3130 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3131 * indicators of an event TRB error, but we check the status *first* to be safe.
3133 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
3135 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3136 irqreturn_t ret
= IRQ_NONE
;
3139 spin_lock(&xhci
->lock
);
3140 /* Check if the xHC generated the interrupt, or the irq is shared */
3141 status
= readl(&xhci
->op_regs
->status
);
3142 if (status
== ~(u32
)0) {
3148 if (!(status
& STS_EINT
))
3151 if (status
& STS_HCE
) {
3152 xhci_warn(xhci
, "WARNING: Host Controller Error\n");
3156 if (status
& STS_FATAL
) {
3157 xhci_warn(xhci
, "WARNING: Host System Error\n");
3164 * Clear the op reg interrupt status first,
3165 * so we can receive interrupts from other MSI-X interrupters.
3166 * Write 1 to clear the interrupt status.
3169 writel(status
, &xhci
->op_regs
->status
);
3172 /* This is the handler of the primary interrupter */
3173 xhci_handle_events(xhci
, xhci
->interrupters
[0]);
3175 spin_unlock(&xhci
->lock
);
3180 irqreturn_t
xhci_msi_irq(int irq
, void *hcd
)
3182 return xhci_irq(hcd
);
3184 EXPORT_SYMBOL_GPL(xhci_msi_irq
);
3186 /**** Endpoint Ring Operations ****/
3189 * Generic function for queueing a TRB on a ring.
3190 * The caller must have checked to make sure there's room on the ring.
3192 * @more_trbs_coming: Will you enqueue more TRBs before calling
3193 * prepare_transfer()?
3195 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
3196 bool more_trbs_coming
,
3197 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3199 struct xhci_generic_trb
*trb
;
3201 trb
= &ring
->enqueue
->generic
;
3202 trb
->field
[0] = cpu_to_le32(field1
);
3203 trb
->field
[1] = cpu_to_le32(field2
);
3204 trb
->field
[2] = cpu_to_le32(field3
);
3205 /* make sure TRB is fully written before giving it to the controller */
3207 trb
->field
[3] = cpu_to_le32(field4
);
3209 trace_xhci_queue_trb(ring
, trb
);
3211 inc_enq(xhci
, ring
, more_trbs_coming
);
3215 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3216 * expand ring if it start to be full.
3218 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
3219 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
3221 unsigned int link_trb_count
= 0;
3222 unsigned int new_segs
= 0;
3224 /* Make sure the endpoint has been added to xHC schedule */
3226 case EP_STATE_DISABLED
:
3228 * USB core changed config/interfaces without notifying us,
3229 * or hardware is reporting the wrong state.
3231 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
3233 case EP_STATE_ERROR
:
3234 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
3235 /* FIXME event handling code for error needs to clear it */
3236 /* XXX not sure if this should be -ENOENT or not */
3238 case EP_STATE_HALTED
:
3239 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
3241 case EP_STATE_STOPPED
:
3242 case EP_STATE_RUNNING
:
3245 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
3247 * FIXME issue Configure Endpoint command to try to get the HC
3248 * back into a known state.
3253 if (ep_ring
!= xhci
->cmd_ring
) {
3254 new_segs
= xhci_ring_expansion_needed(xhci
, ep_ring
, num_trbs
);
3255 } else if (xhci_num_trbs_free(xhci
, ep_ring
) <= num_trbs
) {
3256 xhci_err(xhci
, "Do not support expand command ring\n");
3261 xhci_dbg_trace(xhci
, trace_xhci_dbg_ring_expansion
,
3262 "ERROR no room on ep ring, try ring expansion");
3263 if (xhci_ring_expansion(xhci
, ep_ring
, new_segs
, mem_flags
)) {
3264 xhci_err(xhci
, "Ring expansion failed\n");
3269 while (trb_is_link(ep_ring
->enqueue
)) {
3270 /* If we're not dealing with 0.95 hardware or isoc rings
3271 * on AMD 0.96 host, clear the chain bit.
3273 if (!xhci_link_trb_quirk(xhci
) &&
3274 !(ep_ring
->type
== TYPE_ISOC
&&
3275 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
3276 ep_ring
->enqueue
->link
.control
&=
3277 cpu_to_le32(~TRB_CHAIN
);
3279 ep_ring
->enqueue
->link
.control
|=
3280 cpu_to_le32(TRB_CHAIN
);
3283 ep_ring
->enqueue
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
3285 /* Toggle the cycle bit after the last ring segment. */
3286 if (link_trb_toggles_cycle(ep_ring
->enqueue
))
3287 ep_ring
->cycle_state
^= 1;
3289 ep_ring
->enq_seg
= ep_ring
->enq_seg
->next
;
3290 ep_ring
->enqueue
= ep_ring
->enq_seg
->trbs
;
3292 /* prevent infinite loop if all first trbs are link trbs */
3293 if (link_trb_count
++ > ep_ring
->num_segs
) {
3294 xhci_warn(xhci
, "Ring is an endless link TRB loop\n");
3299 if (last_trb_on_seg(ep_ring
->enq_seg
, ep_ring
->enqueue
)) {
3300 xhci_warn(xhci
, "Missing link TRB at end of ring segment\n");
3307 static int prepare_transfer(struct xhci_hcd
*xhci
,
3308 struct xhci_virt_device
*xdev
,
3309 unsigned int ep_index
,
3310 unsigned int stream_id
,
3311 unsigned int num_trbs
,
3313 unsigned int td_index
,
3317 struct urb_priv
*urb_priv
;
3319 struct xhci_ring
*ep_ring
;
3320 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3322 ep_ring
= xhci_triad_to_transfer_ring(xhci
, xdev
->slot_id
, ep_index
,
3325 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
3330 ret
= prepare_ring(xhci
, ep_ring
, GET_EP_CTX_STATE(ep_ctx
),
3331 num_trbs
, mem_flags
);
3335 urb_priv
= urb
->hcpriv
;
3336 td
= &urb_priv
->td
[td_index
];
3338 INIT_LIST_HEAD(&td
->td_list
);
3339 INIT_LIST_HEAD(&td
->cancelled_td_list
);
3341 if (td_index
== 0) {
3342 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3348 /* Add this TD to the tail of the endpoint ring's TD list */
3349 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
3350 td
->start_seg
= ep_ring
->enq_seg
;
3351 td
->first_trb
= ep_ring
->enqueue
;
3356 unsigned int count_trbs(u64 addr
, u64 len
)
3358 unsigned int num_trbs
;
3360 num_trbs
= DIV_ROUND_UP(len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
3368 static inline unsigned int count_trbs_needed(struct urb
*urb
)
3370 return count_trbs(urb
->transfer_dma
, urb
->transfer_buffer_length
);
3373 static unsigned int count_sg_trbs_needed(struct urb
*urb
)
3375 struct scatterlist
*sg
;
3376 unsigned int i
, len
, full_len
, num_trbs
= 0;
3378 full_len
= urb
->transfer_buffer_length
;
3380 for_each_sg(urb
->sg
, sg
, urb
->num_mapped_sgs
, i
) {
3381 len
= sg_dma_len(sg
);
3382 num_trbs
+= count_trbs(sg_dma_address(sg
), len
);
3383 len
= min_t(unsigned int, len
, full_len
);
3392 static unsigned int count_isoc_trbs_needed(struct urb
*urb
, int i
)
3396 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3397 len
= urb
->iso_frame_desc
[i
].length
;
3399 return count_trbs(addr
, len
);
3402 static void check_trb_math(struct urb
*urb
, int running_total
)
3404 if (unlikely(running_total
!= urb
->transfer_buffer_length
))
3405 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
3406 "queued %#x (%d), asked for %#x (%d)\n",
3408 urb
->ep
->desc
.bEndpointAddress
,
3409 running_total
, running_total
,
3410 urb
->transfer_buffer_length
,
3411 urb
->transfer_buffer_length
);
3414 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
3415 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
3416 struct xhci_generic_trb
*start_trb
)
3419 * Pass all the TRBs to the hardware at once and make sure this write
3424 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
3426 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
3427 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
3430 static void check_interval(struct xhci_hcd
*xhci
, struct urb
*urb
,
3431 struct xhci_ep_ctx
*ep_ctx
)
3436 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3437 ep_interval
= urb
->interval
;
3439 /* Convert to microframes */
3440 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3441 urb
->dev
->speed
== USB_SPEED_FULL
)
3444 /* FIXME change this to a warning and a suggestion to use the new API
3445 * to set the polling interval (once the API is added).
3447 if (xhci_interval
!= ep_interval
) {
3448 dev_dbg_ratelimited(&urb
->dev
->dev
,
3449 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3450 ep_interval
, ep_interval
== 1 ? "" : "s",
3451 xhci_interval
, xhci_interval
== 1 ? "" : "s");
3452 urb
->interval
= xhci_interval
;
3453 /* Convert back to frames for LS/FS devices */
3454 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3455 urb
->dev
->speed
== USB_SPEED_FULL
)
3461 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3462 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3463 * (comprised of sg list entries) can take several service intervals to
3466 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3467 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3469 struct xhci_ep_ctx
*ep_ctx
;
3471 ep_ctx
= xhci_get_ep_ctx(xhci
, xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
3472 check_interval(xhci
, urb
, ep_ctx
);
3474 return xhci_queue_bulk_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3478 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3479 * packets remaining in the TD (*not* including this TRB).
3481 * Total TD packet count = total_packet_count =
3482 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3484 * Packets transferred up to and including this TRB = packets_transferred =
3485 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3487 * TD size = total_packet_count - packets_transferred
3489 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3490 * including this TRB, right shifted by 10
3492 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3493 * This is taken care of in the TRB_TD_SIZE() macro
3495 * The last TRB in a TD must have the TD size set to zero.
3497 static u32
xhci_td_remainder(struct xhci_hcd
*xhci
, int transferred
,
3498 int trb_buff_len
, unsigned int td_total_len
,
3499 struct urb
*urb
, bool more_trbs_coming
)
3501 u32 maxp
, total_packet_count
;
3503 /* MTK xHCI 0.96 contains some features from 1.0 */
3504 if (xhci
->hci_version
< 0x100 && !(xhci
->quirks
& XHCI_MTK_HOST
))
3505 return ((td_total_len
- transferred
) >> 10);
3507 /* One TRB with a zero-length data packet. */
3508 if (!more_trbs_coming
|| (transferred
== 0 && trb_buff_len
== 0) ||
3509 trb_buff_len
== td_total_len
)
3512 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3513 if ((xhci
->quirks
& XHCI_MTK_HOST
) && (xhci
->hci_version
< 0x100))
3516 maxp
= usb_endpoint_maxp(&urb
->ep
->desc
);
3517 total_packet_count
= DIV_ROUND_UP(td_total_len
, maxp
);
3519 /* Queueing functions don't count the current TRB into transferred */
3520 return (total_packet_count
- ((transferred
+ trb_buff_len
) / maxp
));
3524 static int xhci_align_td(struct xhci_hcd
*xhci
, struct urb
*urb
, u32 enqd_len
,
3525 u32
*trb_buff_len
, struct xhci_segment
*seg
)
3527 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
3528 unsigned int unalign
;
3529 unsigned int max_pkt
;
3533 max_pkt
= usb_endpoint_maxp(&urb
->ep
->desc
);
3534 unalign
= (enqd_len
+ *trb_buff_len
) % max_pkt
;
3536 /* we got lucky, last normal TRB data on segment is packet aligned */
3540 xhci_dbg(xhci
, "Unaligned %d bytes, buff len %d\n",
3541 unalign
, *trb_buff_len
);
3543 /* is the last nornal TRB alignable by splitting it */
3544 if (*trb_buff_len
> unalign
) {
3545 *trb_buff_len
-= unalign
;
3546 xhci_dbg(xhci
, "split align, new buff len %d\n", *trb_buff_len
);
3551 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3552 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3553 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3555 new_buff_len
= max_pkt
- (enqd_len
% max_pkt
);
3557 if (new_buff_len
> (urb
->transfer_buffer_length
- enqd_len
))
3558 new_buff_len
= (urb
->transfer_buffer_length
- enqd_len
);
3560 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3561 if (usb_urb_dir_out(urb
)) {
3563 len
= sg_pcopy_to_buffer(urb
->sg
, urb
->num_sgs
,
3564 seg
->bounce_buf
, new_buff_len
, enqd_len
);
3565 if (len
!= new_buff_len
)
3566 xhci_warn(xhci
, "WARN Wrong bounce buffer write length: %zu != %d\n",
3569 memcpy(seg
->bounce_buf
, urb
->transfer_buffer
+ enqd_len
, new_buff_len
);
3572 seg
->bounce_dma
= dma_map_single(dev
, seg
->bounce_buf
,
3573 max_pkt
, DMA_TO_DEVICE
);
3575 seg
->bounce_dma
= dma_map_single(dev
, seg
->bounce_buf
,
3576 max_pkt
, DMA_FROM_DEVICE
);
3579 if (dma_mapping_error(dev
, seg
->bounce_dma
)) {
3580 /* try without aligning. Some host controllers survive */
3581 xhci_warn(xhci
, "Failed mapping bounce buffer, not aligning\n");
3584 *trb_buff_len
= new_buff_len
;
3585 seg
->bounce_len
= new_buff_len
;
3586 seg
->bounce_offs
= enqd_len
;
3588 xhci_dbg(xhci
, "Bounce align, new buff len %d\n", *trb_buff_len
);
3593 /* This is very similar to what ehci-q.c qtd_fill() does */
3594 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3595 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3597 struct xhci_ring
*ring
;
3598 struct urb_priv
*urb_priv
;
3600 struct xhci_generic_trb
*start_trb
;
3601 struct scatterlist
*sg
= NULL
;
3602 bool more_trbs_coming
= true;
3603 bool need_zero_pkt
= false;
3604 bool first_trb
= true;
3605 unsigned int num_trbs
;
3606 unsigned int start_cycle
, num_sgs
= 0;
3607 unsigned int enqd_len
, block_len
, trb_buff_len
, full_len
;
3609 u32 field
, length_field
, remainder
;
3610 u64 addr
, send_addr
;
3612 ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3616 full_len
= urb
->transfer_buffer_length
;
3617 /* If we have scatter/gather list, we use it. */
3618 if (urb
->num_sgs
&& !(urb
->transfer_flags
& URB_DMA_MAP_SINGLE
)) {
3619 num_sgs
= urb
->num_mapped_sgs
;
3621 addr
= (u64
) sg_dma_address(sg
);
3622 block_len
= sg_dma_len(sg
);
3623 num_trbs
= count_sg_trbs_needed(urb
);
3625 num_trbs
= count_trbs_needed(urb
);
3626 addr
= (u64
) urb
->transfer_dma
;
3627 block_len
= full_len
;
3629 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3630 ep_index
, urb
->stream_id
,
3631 num_trbs
, urb
, 0, mem_flags
);
3632 if (unlikely(ret
< 0))
3635 urb_priv
= urb
->hcpriv
;
3637 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3638 if (urb
->transfer_flags
& URB_ZERO_PACKET
&& urb_priv
->num_tds
> 1)
3639 need_zero_pkt
= true;
3641 td
= &urb_priv
->td
[0];
3644 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3645 * until we've finished creating all the other TRBs. The ring's cycle
3646 * state may change as we enqueue the other TRBs, so save it too.
3648 start_trb
= &ring
->enqueue
->generic
;
3649 start_cycle
= ring
->cycle_state
;
3652 /* Queue the TRBs, even if they are zero-length */
3653 for (enqd_len
= 0; first_trb
|| enqd_len
< full_len
;
3654 enqd_len
+= trb_buff_len
) {
3655 field
= TRB_TYPE(TRB_NORMAL
);
3657 /* TRB buffer should not cross 64KB boundaries */
3658 trb_buff_len
= TRB_BUFF_LEN_UP_TO_BOUNDARY(addr
);
3659 trb_buff_len
= min_t(unsigned int, trb_buff_len
, block_len
);
3661 if (enqd_len
+ trb_buff_len
> full_len
)
3662 trb_buff_len
= full_len
- enqd_len
;
3664 /* Don't change the cycle bit of the first TRB until later */
3667 if (start_cycle
== 0)
3670 field
|= ring
->cycle_state
;
3672 /* Chain all the TRBs together; clear the chain bit in the last
3673 * TRB to indicate it's the last TRB in the chain.
3675 if (enqd_len
+ trb_buff_len
< full_len
) {
3677 if (trb_is_link(ring
->enqueue
+ 1)) {
3678 if (xhci_align_td(xhci
, urb
, enqd_len
,
3681 send_addr
= ring
->enq_seg
->bounce_dma
;
3682 /* assuming TD won't span 2 segs */
3683 td
->bounce_seg
= ring
->enq_seg
;
3687 if (enqd_len
+ trb_buff_len
>= full_len
) {
3688 field
&= ~TRB_CHAIN
;
3690 more_trbs_coming
= false;
3691 td
->last_trb
= ring
->enqueue
;
3692 td
->last_trb_seg
= ring
->enq_seg
;
3693 if (xhci_urb_suitable_for_idt(urb
)) {
3694 memcpy(&send_addr
, urb
->transfer_buffer
,
3696 le64_to_cpus(&send_addr
);
3701 /* Only set interrupt on short packet for IN endpoints */
3702 if (usb_urb_dir_in(urb
))
3705 /* Set the TRB length, TD size, and interrupter fields. */
3706 remainder
= xhci_td_remainder(xhci
, enqd_len
, trb_buff_len
,
3707 full_len
, urb
, more_trbs_coming
);
3709 length_field
= TRB_LEN(trb_buff_len
) |
3710 TRB_TD_SIZE(remainder
) |
3713 queue_trb(xhci
, ring
, more_trbs_coming
| need_zero_pkt
,
3714 lower_32_bits(send_addr
),
3715 upper_32_bits(send_addr
),
3719 addr
+= trb_buff_len
;
3720 sent_len
= trb_buff_len
;
3722 while (sg
&& sent_len
>= block_len
) {
3725 sent_len
-= block_len
;
3727 if (num_sgs
!= 0 && sg
) {
3728 block_len
= sg_dma_len(sg
);
3729 addr
= (u64
) sg_dma_address(sg
);
3733 block_len
-= sent_len
;
3737 if (need_zero_pkt
) {
3738 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3739 ep_index
, urb
->stream_id
,
3740 1, urb
, 1, mem_flags
);
3741 urb_priv
->td
[1].last_trb
= ring
->enqueue
;
3742 urb_priv
->td
[1].last_trb_seg
= ring
->enq_seg
;
3743 field
= TRB_TYPE(TRB_NORMAL
) | ring
->cycle_state
| TRB_IOC
;
3744 queue_trb(xhci
, ring
, 0, 0, 0, TRB_INTR_TARGET(0), field
);
3745 urb_priv
->td
[1].num_trbs
++;
3748 check_trb_math(urb
, enqd_len
);
3749 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3750 start_cycle
, start_trb
);
3754 /* Caller must have locked xhci->lock */
3755 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3756 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3758 struct xhci_ring
*ep_ring
;
3761 struct usb_ctrlrequest
*setup
;
3762 struct xhci_generic_trb
*start_trb
;
3765 struct urb_priv
*urb_priv
;
3768 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3773 * Need to copy setup packet into setup TRB, so we can't use the setup
3776 if (!urb
->setup_packet
)
3779 /* 1 TRB for setup, 1 for status */
3782 * Don't need to check if we need additional event data and normal TRBs,
3783 * since data in control transfers will never get bigger than 16MB
3784 * XXX: can we get a buffer that crosses 64KB boundaries?
3786 if (urb
->transfer_buffer_length
> 0)
3788 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3789 ep_index
, urb
->stream_id
,
3790 num_trbs
, urb
, 0, mem_flags
);
3794 urb_priv
= urb
->hcpriv
;
3795 td
= &urb_priv
->td
[0];
3796 td
->num_trbs
= num_trbs
;
3799 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3800 * until we've finished creating all the other TRBs. The ring's cycle
3801 * state may change as we enqueue the other TRBs, so save it too.
3803 start_trb
= &ep_ring
->enqueue
->generic
;
3804 start_cycle
= ep_ring
->cycle_state
;
3806 /* Queue setup TRB - see section 6.4.1.2.1 */
3807 /* FIXME better way to translate setup_packet into two u32 fields? */
3808 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3810 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3811 if (start_cycle
== 0)
3814 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3815 if ((xhci
->hci_version
>= 0x100) || (xhci
->quirks
& XHCI_MTK_HOST
)) {
3816 if (urb
->transfer_buffer_length
> 0) {
3817 if (setup
->bRequestType
& USB_DIR_IN
)
3818 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3820 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3824 queue_trb(xhci
, ep_ring
, true,
3825 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3826 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3827 TRB_LEN(8) | TRB_INTR_TARGET(0),
3828 /* Immediate data in pointer */
3831 /* If there's data, queue data TRBs */
3832 /* Only set interrupt on short packet for IN endpoints */
3833 if (usb_urb_dir_in(urb
))
3834 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3836 field
= TRB_TYPE(TRB_DATA
);
3838 if (urb
->transfer_buffer_length
> 0) {
3839 u32 length_field
, remainder
;
3842 if (xhci_urb_suitable_for_idt(urb
)) {
3843 memcpy(&addr
, urb
->transfer_buffer
,
3844 urb
->transfer_buffer_length
);
3845 le64_to_cpus(&addr
);
3848 addr
= (u64
) urb
->transfer_dma
;
3851 remainder
= xhci_td_remainder(xhci
, 0,
3852 urb
->transfer_buffer_length
,
3853 urb
->transfer_buffer_length
,
3855 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3856 TRB_TD_SIZE(remainder
) |
3858 if (setup
->bRequestType
& USB_DIR_IN
)
3859 field
|= TRB_DIR_IN
;
3860 queue_trb(xhci
, ep_ring
, true,
3861 lower_32_bits(addr
),
3862 upper_32_bits(addr
),
3864 field
| ep_ring
->cycle_state
);
3867 /* Save the DMA address of the last TRB in the TD */
3868 td
->last_trb
= ep_ring
->enqueue
;
3869 td
->last_trb_seg
= ep_ring
->enq_seg
;
3871 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3872 /* If the device sent data, the status stage is an OUT transfer */
3873 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3877 queue_trb(xhci
, ep_ring
, false,
3881 /* Event on completion */
3882 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3884 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3885 start_cycle
, start_trb
);
3890 * The transfer burst count field of the isochronous TRB defines the number of
3891 * bursts that are required to move all packets in this TD. Only SuperSpeed
3892 * devices can burst up to bMaxBurst number of packets per service interval.
3893 * This field is zero based, meaning a value of zero in the field means one
3894 * burst. Basically, for everything but SuperSpeed devices, this field will be
3895 * zero. Only xHCI 1.0 host controllers support this field.
3897 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3898 struct urb
*urb
, unsigned int total_packet_count
)
3900 unsigned int max_burst
;
3902 if (xhci
->hci_version
< 0x100 || urb
->dev
->speed
< USB_SPEED_SUPER
)
3905 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3906 return DIV_ROUND_UP(total_packet_count
, max_burst
+ 1) - 1;
3910 * Returns the number of packets in the last "burst" of packets. This field is
3911 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3912 * the last burst packet count is equal to the total number of packets in the
3913 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3914 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3915 * contain 1 to (bMaxBurst + 1) packets.
3917 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3918 struct urb
*urb
, unsigned int total_packet_count
)
3920 unsigned int max_burst
;
3921 unsigned int residue
;
3923 if (xhci
->hci_version
< 0x100)
3926 if (urb
->dev
->speed
>= USB_SPEED_SUPER
) {
3927 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3928 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3929 residue
= total_packet_count
% (max_burst
+ 1);
3930 /* If residue is zero, the last burst contains (max_burst + 1)
3931 * number of packets, but the TLBPC field is zero-based.
3937 if (total_packet_count
== 0)
3939 return total_packet_count
- 1;
3943 * Calculates Frame ID field of the isochronous TRB identifies the
3944 * target frame that the Interval associated with this Isochronous
3945 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3947 * Returns actual frame id on success, negative value on error.
3949 static int xhci_get_isoc_frame_id(struct xhci_hcd
*xhci
,
3950 struct urb
*urb
, int index
)
3952 int start_frame
, ist
, ret
= 0;
3953 int start_frame_id
, end_frame_id
, current_frame_id
;
3955 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3956 urb
->dev
->speed
== USB_SPEED_FULL
)
3957 start_frame
= urb
->start_frame
+ index
* urb
->interval
;
3959 start_frame
= (urb
->start_frame
+ index
* urb
->interval
) >> 3;
3961 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3963 * If bit [3] of IST is cleared to '0', software can add a TRB no
3964 * later than IST[2:0] Microframes before that TRB is scheduled to
3966 * If bit [3] of IST is set to '1', software can add a TRB no later
3967 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3969 ist
= HCS_IST(xhci
->hcs_params2
) & 0x7;
3970 if (HCS_IST(xhci
->hcs_params2
) & (1 << 3))
3973 /* Software shall not schedule an Isoch TD with a Frame ID value that
3974 * is less than the Start Frame ID or greater than the End Frame ID,
3977 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3978 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3980 * Both the End Frame ID and Start Frame ID values are calculated
3981 * in microframes. When software determines the valid Frame ID value;
3982 * The End Frame ID value should be rounded down to the nearest Frame
3983 * boundary, and the Start Frame ID value should be rounded up to the
3984 * nearest Frame boundary.
3986 current_frame_id
= readl(&xhci
->run_regs
->microframe_index
);
3987 start_frame_id
= roundup(current_frame_id
+ ist
+ 1, 8);
3988 end_frame_id
= rounddown(current_frame_id
+ 895 * 8, 8);
3990 start_frame
&= 0x7ff;
3991 start_frame_id
= (start_frame_id
>> 3) & 0x7ff;
3992 end_frame_id
= (end_frame_id
>> 3) & 0x7ff;
3994 xhci_dbg(xhci
, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3995 __func__
, index
, readl(&xhci
->run_regs
->microframe_index
),
3996 start_frame_id
, end_frame_id
, start_frame
);
3998 if (start_frame_id
< end_frame_id
) {
3999 if (start_frame
> end_frame_id
||
4000 start_frame
< start_frame_id
)
4002 } else if (start_frame_id
> end_frame_id
) {
4003 if ((start_frame
> end_frame_id
&&
4004 start_frame
< start_frame_id
))
4011 if (ret
== -EINVAL
|| start_frame
== start_frame_id
) {
4012 start_frame
= start_frame_id
+ 1;
4013 if (urb
->dev
->speed
== USB_SPEED_LOW
||
4014 urb
->dev
->speed
== USB_SPEED_FULL
)
4015 urb
->start_frame
= start_frame
;
4017 urb
->start_frame
= start_frame
<< 3;
4023 xhci_warn(xhci
, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
4024 start_frame
, current_frame_id
, index
,
4025 start_frame_id
, end_frame_id
);
4026 xhci_warn(xhci
, "Ignore frame ID field, use SIA bit instead\n");
4033 /* Check if we should generate event interrupt for a TD in an isoc URB */
4034 static bool trb_block_event_intr(struct xhci_hcd
*xhci
, int num_tds
, int i
,
4035 struct xhci_interrupter
*ir
)
4037 if (xhci
->hci_version
< 0x100)
4039 /* always generate an event interrupt for the last TD */
4040 if (i
== num_tds
- 1)
4043 * If AVOID_BEI is set the host handles full event rings poorly,
4044 * generate an event at least every 8th TD to clear the event ring
4046 if (i
&& ir
->isoc_bei_interval
&& xhci
->quirks
& XHCI_AVOID_BEI
)
4047 return !!(i
% ir
->isoc_bei_interval
);
4052 /* This is for isoc transfer */
4053 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
4054 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
4056 struct xhci_interrupter
*ir
;
4057 struct xhci_ring
*ep_ring
;
4058 struct urb_priv
*urb_priv
;
4060 int num_tds
, trbs_per_td
;
4061 struct xhci_generic_trb
*start_trb
;
4064 u32 field
, length_field
;
4065 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
4066 u64 start_addr
, addr
;
4068 bool more_trbs_coming
;
4069 struct xhci_virt_ep
*xep
;
4072 xep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
4073 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
4074 ir
= xhci
->interrupters
[0];
4076 num_tds
= urb
->number_of_packets
;
4078 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
4081 start_addr
= (u64
) urb
->transfer_dma
;
4082 start_trb
= &ep_ring
->enqueue
->generic
;
4083 start_cycle
= ep_ring
->cycle_state
;
4085 urb_priv
= urb
->hcpriv
;
4086 /* Queue the TRBs for each TD, even if they are zero-length */
4087 for (i
= 0; i
< num_tds
; i
++) {
4088 unsigned int total_pkt_count
, max_pkt
;
4089 unsigned int burst_count
, last_burst_pkt_count
;
4094 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
4095 td_len
= urb
->iso_frame_desc
[i
].length
;
4096 td_remain_len
= td_len
;
4097 max_pkt
= usb_endpoint_maxp(&urb
->ep
->desc
);
4098 total_pkt_count
= DIV_ROUND_UP(td_len
, max_pkt
);
4100 /* A zero-length transfer still involves at least one packet. */
4101 if (total_pkt_count
== 0)
4103 burst_count
= xhci_get_burst_count(xhci
, urb
, total_pkt_count
);
4104 last_burst_pkt_count
= xhci_get_last_burst_packet_count(xhci
,
4105 urb
, total_pkt_count
);
4107 trbs_per_td
= count_isoc_trbs_needed(urb
, i
);
4109 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
4110 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
4116 td
= &urb_priv
->td
[i
];
4117 td
->num_trbs
= trbs_per_td
;
4118 /* use SIA as default, if frame id is used overwrite it */
4119 sia_frame_id
= TRB_SIA
;
4120 if (!(urb
->transfer_flags
& URB_ISO_ASAP
) &&
4121 HCC_CFC(xhci
->hcc_params
)) {
4122 frame_id
= xhci_get_isoc_frame_id(xhci
, urb
, i
);
4124 sia_frame_id
= TRB_FRAME_ID(frame_id
);
4127 * Set isoc specific data for the first TRB in a TD.
4128 * Prevent HW from getting the TRBs by keeping the cycle state
4129 * inverted in the first TDs isoc TRB.
4131 field
= TRB_TYPE(TRB_ISOC
) |
4132 TRB_TLBPC(last_burst_pkt_count
) |
4134 (i
? ep_ring
->cycle_state
: !start_cycle
);
4136 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4137 if (!xep
->use_extended_tbc
)
4138 field
|= TRB_TBC(burst_count
);
4140 /* fill the rest of the TRB fields, and remaining normal TRBs */
4141 for (j
= 0; j
< trbs_per_td
; j
++) {
4144 /* only first TRB is isoc, overwrite otherwise */
4146 field
= TRB_TYPE(TRB_NORMAL
) |
4147 ep_ring
->cycle_state
;
4149 /* Only set interrupt on short packet for IN EPs */
4150 if (usb_urb_dir_in(urb
))
4153 /* Set the chain bit for all except the last TRB */
4154 if (j
< trbs_per_td
- 1) {
4155 more_trbs_coming
= true;
4158 more_trbs_coming
= false;
4159 td
->last_trb
= ep_ring
->enqueue
;
4160 td
->last_trb_seg
= ep_ring
->enq_seg
;
4162 if (trb_block_event_intr(xhci
, num_tds
, i
, ir
))
4165 /* Calculate TRB length */
4166 trb_buff_len
= TRB_BUFF_LEN_UP_TO_BOUNDARY(addr
);
4167 if (trb_buff_len
> td_remain_len
)
4168 trb_buff_len
= td_remain_len
;
4170 /* Set the TRB length, TD size, & interrupter fields. */
4171 remainder
= xhci_td_remainder(xhci
, running_total
,
4172 trb_buff_len
, td_len
,
4173 urb
, more_trbs_coming
);
4175 length_field
= TRB_LEN(trb_buff_len
) |
4178 /* xhci 1.1 with ETE uses TD Size field for TBC */
4179 if (first_trb
&& xep
->use_extended_tbc
)
4180 length_field
|= TRB_TD_SIZE_TBC(burst_count
);
4182 length_field
|= TRB_TD_SIZE(remainder
);
4185 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
4186 lower_32_bits(addr
),
4187 upper_32_bits(addr
),
4190 running_total
+= trb_buff_len
;
4192 addr
+= trb_buff_len
;
4193 td_remain_len
-= trb_buff_len
;
4196 /* Check TD length */
4197 if (running_total
!= td_len
) {
4198 xhci_err(xhci
, "ISOC TD length unmatch\n");
4204 /* store the next frame id */
4205 if (HCC_CFC(xhci
->hcc_params
))
4206 xep
->next_frame_id
= urb
->start_frame
+ num_tds
* urb
->interval
;
4208 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
4209 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
4210 usb_amd_quirk_pll_disable();
4212 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
4214 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
4215 start_cycle
, start_trb
);
4218 /* Clean up a partially enqueued isoc transfer. */
4220 for (i
--; i
>= 0; i
--)
4221 list_del_init(&urb_priv
->td
[i
].td_list
);
4223 /* Use the first TD as a temporary variable to turn the TDs we've queued
4224 * into No-ops with a software-owned cycle bit. That way the hardware
4225 * won't accidentally start executing bogus TDs when we partially
4226 * overwrite them. td->first_trb and td->start_seg are already set.
4228 urb_priv
->td
[0].last_trb
= ep_ring
->enqueue
;
4229 /* Every TRB except the first & last will have its cycle bit flipped. */
4230 td_to_noop(xhci
, ep_ring
, &urb_priv
->td
[0], true);
4232 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4233 ep_ring
->enqueue
= urb_priv
->td
[0].first_trb
;
4234 ep_ring
->enq_seg
= urb_priv
->td
[0].start_seg
;
4235 ep_ring
->cycle_state
= start_cycle
;
4236 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
4241 * Check transfer ring to guarantee there is enough room for the urb.
4242 * Update ISO URB start_frame and interval.
4243 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4244 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4245 * Contiguous Frame ID is not supported by HC.
4247 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
4248 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
4250 struct xhci_virt_device
*xdev
;
4251 struct xhci_ring
*ep_ring
;
4252 struct xhci_ep_ctx
*ep_ctx
;
4254 int num_tds
, num_trbs
, i
;
4256 struct xhci_virt_ep
*xep
;
4259 xdev
= xhci
->devs
[slot_id
];
4260 xep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
4261 ep_ring
= xdev
->eps
[ep_index
].ring
;
4262 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
4265 num_tds
= urb
->number_of_packets
;
4266 for (i
= 0; i
< num_tds
; i
++)
4267 num_trbs
+= count_isoc_trbs_needed(urb
, i
);
4269 /* Check the ring to guarantee there is enough room for the whole urb.
4270 * Do not insert any td of the urb to the ring if the check failed.
4272 ret
= prepare_ring(xhci
, ep_ring
, GET_EP_CTX_STATE(ep_ctx
),
4273 num_trbs
, mem_flags
);
4278 * Check interval value. This should be done before we start to
4279 * calculate the start frame value.
4281 check_interval(xhci
, urb
, ep_ctx
);
4283 /* Calculate the start frame and put it in urb->start_frame. */
4284 if (HCC_CFC(xhci
->hcc_params
) && !list_empty(&ep_ring
->td_list
)) {
4285 if (GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_RUNNING
) {
4286 urb
->start_frame
= xep
->next_frame_id
;
4287 goto skip_start_over
;
4291 start_frame
= readl(&xhci
->run_regs
->microframe_index
);
4292 start_frame
&= 0x3fff;
4294 * Round up to the next frame and consider the time before trb really
4295 * gets scheduled by hardare.
4297 ist
= HCS_IST(xhci
->hcs_params2
) & 0x7;
4298 if (HCS_IST(xhci
->hcs_params2
) & (1 << 3))
4300 start_frame
+= ist
+ XHCI_CFC_DELAY
;
4301 start_frame
= roundup(start_frame
, 8);
4304 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4305 * is greate than 8 microframes.
4307 if (urb
->dev
->speed
== USB_SPEED_LOW
||
4308 urb
->dev
->speed
== USB_SPEED_FULL
) {
4309 start_frame
= roundup(start_frame
, urb
->interval
<< 3);
4310 urb
->start_frame
= start_frame
>> 3;
4312 start_frame
= roundup(start_frame
, urb
->interval
);
4313 urb
->start_frame
= start_frame
;
4318 return xhci_queue_isoc_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
4321 /**** Command Ring Operations ****/
4323 /* Generic function for queueing a command TRB on the command ring.
4324 * Check to make sure there's room on the command ring for one command TRB.
4325 * Also check that there's room reserved for commands that must not fail.
4326 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4327 * then only check for the number of reserved spots.
4328 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4329 * because the command event handler may want to resubmit a failed command.
4331 static int queue_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4332 u32 field1
, u32 field2
,
4333 u32 field3
, u32 field4
, bool command_must_succeed
)
4335 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
4338 if ((xhci
->xhc_state
& XHCI_STATE_DYING
) ||
4339 (xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
4340 xhci_dbg(xhci
, "xHCI dying or halted, can't queue_command\n");
4344 if (!command_must_succeed
)
4347 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
4348 reserved_trbs
, GFP_ATOMIC
);
4350 xhci_err(xhci
, "ERR: No room for command on command ring\n");
4351 if (command_must_succeed
)
4352 xhci_err(xhci
, "ERR: Reserved TRB counting for "
4353 "unfailable commands failed.\n");
4357 cmd
->command_trb
= xhci
->cmd_ring
->enqueue
;
4359 /* if there are no other commands queued we start the timeout timer */
4360 if (list_empty(&xhci
->cmd_list
)) {
4361 xhci
->current_cmd
= cmd
;
4362 xhci_mod_cmd_timer(xhci
);
4365 list_add_tail(&cmd
->cmd_list
, &xhci
->cmd_list
);
4367 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
4368 field4
| xhci
->cmd_ring
->cycle_state
);
4372 /* Queue a slot enable or disable request on the command ring */
4373 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4374 u32 trb_type
, u32 slot_id
)
4376 return queue_command(xhci
, cmd
, 0, 0, 0,
4377 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
4380 /* Queue an address device command TRB */
4381 int xhci_queue_address_device(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4382 dma_addr_t in_ctx_ptr
, u32 slot_id
, enum xhci_setup_dev setup
)
4384 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
4385 upper_32_bits(in_ctx_ptr
), 0,
4386 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
)
4387 | (setup
== SETUP_CONTEXT_ONLY
? TRB_BSR
: 0), false);
4390 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4391 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
4393 return queue_command(xhci
, cmd
, field1
, field2
, field3
, field4
, false);
4396 /* Queue a reset device command TRB */
4397 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4400 return queue_command(xhci
, cmd
, 0, 0, 0,
4401 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
4405 /* Queue a configure endpoint command TRB */
4406 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
,
4407 struct xhci_command
*cmd
, dma_addr_t in_ctx_ptr
,
4408 u32 slot_id
, bool command_must_succeed
)
4410 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
4411 upper_32_bits(in_ctx_ptr
), 0,
4412 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
4413 command_must_succeed
);
4416 /* Queue an evaluate context command TRB */
4417 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4418 dma_addr_t in_ctx_ptr
, u32 slot_id
, bool command_must_succeed
)
4420 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
4421 upper_32_bits(in_ctx_ptr
), 0,
4422 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
4423 command_must_succeed
);
4427 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4428 * activity on an endpoint that is about to be suspended.
4430 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4431 int slot_id
, unsigned int ep_index
, int suspend
)
4433 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4434 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4435 u32 type
= TRB_TYPE(TRB_STOP_RING
);
4436 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
4438 return queue_command(xhci
, cmd
, 0, 0, 0,
4439 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
4442 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4443 int slot_id
, unsigned int ep_index
,
4444 enum xhci_ep_reset_type reset_type
)
4446 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4447 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4448 u32 type
= TRB_TYPE(TRB_RESET_EP
);
4450 if (reset_type
== EP_SOFT_RESET
)
4453 return queue_command(xhci
, cmd
, 0, 0, 0,
4454 trb_slot_id
| trb_ep_index
| type
, false);