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Merge tag 'hyperv-fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git...
[thirdparty/linux.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
64 };
65
66 enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71 };
72
73 enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77 };
78
79 enum {
80 MLX5_SHARED_RESOURCE_UID = 0xffff,
81 };
82
83 enum {
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
85 };
86
87 enum {
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90 };
91
92 enum {
93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
94 MLX5_OBJ_TYPE_MKEY = 0xff01,
95 MLX5_OBJ_TYPE_QP = 0xff02,
96 MLX5_OBJ_TYPE_PSV = 0xff03,
97 MLX5_OBJ_TYPE_RMP = 0xff04,
98 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99 MLX5_OBJ_TYPE_RQ = 0xff06,
100 MLX5_OBJ_TYPE_SQ = 0xff07,
101 MLX5_OBJ_TYPE_TIR = 0xff08,
102 MLX5_OBJ_TYPE_TIS = 0xff09,
103 MLX5_OBJ_TYPE_DCT = 0xff0a,
104 MLX5_OBJ_TYPE_XRQ = 0xff0b,
105 MLX5_OBJ_TYPE_RQT = 0xff0e,
106 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107 MLX5_OBJ_TYPE_CQ = 0xff10,
108 };
109
110 enum {
111 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
112 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
113 MLX5_CMD_OP_INIT_HCA = 0x102,
114 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
115 MLX5_CMD_OP_ENABLE_HCA = 0x104,
116 MLX5_CMD_OP_DISABLE_HCA = 0x105,
117 MLX5_CMD_OP_QUERY_PAGES = 0x107,
118 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
119 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
120 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
121 MLX5_CMD_OP_SET_ISSI = 0x10b,
122 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
123 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
124 MLX5_CMD_OP_ALLOC_SF = 0x113,
125 MLX5_CMD_OP_DEALLOC_SF = 0x114,
126 MLX5_CMD_OP_CREATE_MKEY = 0x200,
127 MLX5_CMD_OP_QUERY_MKEY = 0x201,
128 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
129 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
130 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
131 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
132 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
133 MLX5_CMD_OP_CREATE_EQ = 0x301,
134 MLX5_CMD_OP_DESTROY_EQ = 0x302,
135 MLX5_CMD_OP_QUERY_EQ = 0x303,
136 MLX5_CMD_OP_GEN_EQE = 0x304,
137 MLX5_CMD_OP_CREATE_CQ = 0x400,
138 MLX5_CMD_OP_DESTROY_CQ = 0x401,
139 MLX5_CMD_OP_QUERY_CQ = 0x402,
140 MLX5_CMD_OP_MODIFY_CQ = 0x403,
141 MLX5_CMD_OP_CREATE_QP = 0x500,
142 MLX5_CMD_OP_DESTROY_QP = 0x501,
143 MLX5_CMD_OP_RST2INIT_QP = 0x502,
144 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
145 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
146 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
147 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
148 MLX5_CMD_OP_2ERR_QP = 0x507,
149 MLX5_CMD_OP_2RST_QP = 0x50a,
150 MLX5_CMD_OP_QUERY_QP = 0x50b,
151 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
152 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
153 MLX5_CMD_OP_CREATE_PSV = 0x600,
154 MLX5_CMD_OP_DESTROY_PSV = 0x601,
155 MLX5_CMD_OP_CREATE_SRQ = 0x700,
156 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
157 MLX5_CMD_OP_QUERY_SRQ = 0x702,
158 MLX5_CMD_OP_ARM_RQ = 0x703,
159 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
160 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
161 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
162 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
163 MLX5_CMD_OP_CREATE_DCT = 0x710,
164 MLX5_CMD_OP_DESTROY_DCT = 0x711,
165 MLX5_CMD_OP_DRAIN_DCT = 0x712,
166 MLX5_CMD_OP_QUERY_DCT = 0x713,
167 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
168 MLX5_CMD_OP_CREATE_XRQ = 0x717,
169 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
170 MLX5_CMD_OP_QUERY_XRQ = 0x719,
171 MLX5_CMD_OP_ARM_XRQ = 0x71a,
172 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
173 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
174 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
175 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
176 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
177 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
178 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
179 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
180 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
181 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
182 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
183 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
184 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
185 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
186 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
187 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
188 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
189 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
190 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
191 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
192 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
193 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
194 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
195 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
196 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
197 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
198 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
199 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
200 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
201 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
202 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
203 MLX5_CMD_OP_ALLOC_PD = 0x800,
204 MLX5_CMD_OP_DEALLOC_PD = 0x801,
205 MLX5_CMD_OP_ALLOC_UAR = 0x802,
206 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
207 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
208 MLX5_CMD_OP_ACCESS_REG = 0x805,
209 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
210 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
211 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
212 MLX5_CMD_OP_MAD_IFC = 0x50d,
213 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
214 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
215 MLX5_CMD_OP_NOP = 0x80d,
216 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
217 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
218 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
219 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
220 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
221 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
222 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
223 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
224 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
225 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
226 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
227 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
228 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
229 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
230 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
231 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
232 MLX5_CMD_OP_CREATE_LAG = 0x840,
233 MLX5_CMD_OP_MODIFY_LAG = 0x841,
234 MLX5_CMD_OP_QUERY_LAG = 0x842,
235 MLX5_CMD_OP_DESTROY_LAG = 0x843,
236 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
237 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
238 MLX5_CMD_OP_CREATE_TIR = 0x900,
239 MLX5_CMD_OP_MODIFY_TIR = 0x901,
240 MLX5_CMD_OP_DESTROY_TIR = 0x902,
241 MLX5_CMD_OP_QUERY_TIR = 0x903,
242 MLX5_CMD_OP_CREATE_SQ = 0x904,
243 MLX5_CMD_OP_MODIFY_SQ = 0x905,
244 MLX5_CMD_OP_DESTROY_SQ = 0x906,
245 MLX5_CMD_OP_QUERY_SQ = 0x907,
246 MLX5_CMD_OP_CREATE_RQ = 0x908,
247 MLX5_CMD_OP_MODIFY_RQ = 0x909,
248 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
249 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
250 MLX5_CMD_OP_QUERY_RQ = 0x90b,
251 MLX5_CMD_OP_CREATE_RMP = 0x90c,
252 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
253 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
254 MLX5_CMD_OP_QUERY_RMP = 0x90f,
255 MLX5_CMD_OP_CREATE_TIS = 0x912,
256 MLX5_CMD_OP_MODIFY_TIS = 0x913,
257 MLX5_CMD_OP_DESTROY_TIS = 0x914,
258 MLX5_CMD_OP_QUERY_TIS = 0x915,
259 MLX5_CMD_OP_CREATE_RQT = 0x916,
260 MLX5_CMD_OP_MODIFY_RQT = 0x917,
261 MLX5_CMD_OP_DESTROY_RQT = 0x918,
262 MLX5_CMD_OP_QUERY_RQT = 0x919,
263 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
264 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
265 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
266 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
267 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
268 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
269 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
270 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
271 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
272 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
273 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
274 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
275 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
276 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
277 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
278 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
279 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
280 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
281 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
282 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
283 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
284 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
285 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
286 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
287 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
288 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
289 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
290 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
291 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
292 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
293 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
294 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
295 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
296 MLX5_CMD_OP_MAX
297 };
298
299 /* Valid range for general commands that don't work over an object */
300 enum {
301 MLX5_CMD_OP_GENERAL_START = 0xb00,
302 MLX5_CMD_OP_GENERAL_END = 0xd00,
303 };
304
305 struct mlx5_ifc_flow_table_fields_supported_bits {
306 u8 outer_dmac[0x1];
307 u8 outer_smac[0x1];
308 u8 outer_ether_type[0x1];
309 u8 outer_ip_version[0x1];
310 u8 outer_first_prio[0x1];
311 u8 outer_first_cfi[0x1];
312 u8 outer_first_vid[0x1];
313 u8 outer_ipv4_ttl[0x1];
314 u8 outer_second_prio[0x1];
315 u8 outer_second_cfi[0x1];
316 u8 outer_second_vid[0x1];
317 u8 reserved_at_b[0x1];
318 u8 outer_sip[0x1];
319 u8 outer_dip[0x1];
320 u8 outer_frag[0x1];
321 u8 outer_ip_protocol[0x1];
322 u8 outer_ip_ecn[0x1];
323 u8 outer_ip_dscp[0x1];
324 u8 outer_udp_sport[0x1];
325 u8 outer_udp_dport[0x1];
326 u8 outer_tcp_sport[0x1];
327 u8 outer_tcp_dport[0x1];
328 u8 outer_tcp_flags[0x1];
329 u8 outer_gre_protocol[0x1];
330 u8 outer_gre_key[0x1];
331 u8 outer_vxlan_vni[0x1];
332 u8 outer_geneve_vni[0x1];
333 u8 outer_geneve_oam[0x1];
334 u8 outer_geneve_protocol_type[0x1];
335 u8 outer_geneve_opt_len[0x1];
336 u8 reserved_at_1e[0x1];
337 u8 source_eswitch_port[0x1];
338
339 u8 inner_dmac[0x1];
340 u8 inner_smac[0x1];
341 u8 inner_ether_type[0x1];
342 u8 inner_ip_version[0x1];
343 u8 inner_first_prio[0x1];
344 u8 inner_first_cfi[0x1];
345 u8 inner_first_vid[0x1];
346 u8 reserved_at_27[0x1];
347 u8 inner_second_prio[0x1];
348 u8 inner_second_cfi[0x1];
349 u8 inner_second_vid[0x1];
350 u8 reserved_at_2b[0x1];
351 u8 inner_sip[0x1];
352 u8 inner_dip[0x1];
353 u8 inner_frag[0x1];
354 u8 inner_ip_protocol[0x1];
355 u8 inner_ip_ecn[0x1];
356 u8 inner_ip_dscp[0x1];
357 u8 inner_udp_sport[0x1];
358 u8 inner_udp_dport[0x1];
359 u8 inner_tcp_sport[0x1];
360 u8 inner_tcp_dport[0x1];
361 u8 inner_tcp_flags[0x1];
362 u8 reserved_at_37[0x9];
363
364 u8 geneve_tlv_option_0_data[0x1];
365 u8 reserved_at_41[0x4];
366 u8 outer_first_mpls_over_udp[0x4];
367 u8 outer_first_mpls_over_gre[0x4];
368 u8 inner_first_mpls[0x4];
369 u8 outer_first_mpls[0x4];
370 u8 reserved_at_55[0x2];
371 u8 outer_esp_spi[0x1];
372 u8 reserved_at_58[0x2];
373 u8 bth_dst_qp[0x1];
374
375 u8 reserved_at_5b[0x25];
376 };
377
378 struct mlx5_ifc_flow_table_prop_layout_bits {
379 u8 ft_support[0x1];
380 u8 reserved_at_1[0x1];
381 u8 flow_counter[0x1];
382 u8 flow_modify_en[0x1];
383 u8 modify_root[0x1];
384 u8 identified_miss_table_mode[0x1];
385 u8 flow_table_modify[0x1];
386 u8 reformat[0x1];
387 u8 decap[0x1];
388 u8 reserved_at_9[0x1];
389 u8 pop_vlan[0x1];
390 u8 push_vlan[0x1];
391 u8 reserved_at_c[0x1];
392 u8 pop_vlan_2[0x1];
393 u8 push_vlan_2[0x1];
394 u8 reformat_and_vlan_action[0x1];
395 u8 reserved_at_10[0x1];
396 u8 sw_owner[0x1];
397 u8 reformat_l3_tunnel_to_l2[0x1];
398 u8 reformat_l2_to_l3_tunnel[0x1];
399 u8 reformat_and_modify_action[0x1];
400 u8 reserved_at_15[0x2];
401 u8 table_miss_action_domain[0x1];
402 u8 termination_table[0x1];
403 u8 reserved_at_19[0x7];
404 u8 reserved_at_20[0x2];
405 u8 log_max_ft_size[0x6];
406 u8 log_max_modify_header_context[0x8];
407 u8 max_modify_header_actions[0x8];
408 u8 max_ft_level[0x8];
409
410 u8 reserved_at_40[0x20];
411
412 u8 reserved_at_60[0x18];
413 u8 log_max_ft_num[0x8];
414
415 u8 reserved_at_80[0x18];
416 u8 log_max_destination[0x8];
417
418 u8 log_max_flow_counter[0x8];
419 u8 reserved_at_a8[0x10];
420 u8 log_max_flow[0x8];
421
422 u8 reserved_at_c0[0x40];
423
424 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
425
426 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
427 };
428
429 struct mlx5_ifc_odp_per_transport_service_cap_bits {
430 u8 send[0x1];
431 u8 receive[0x1];
432 u8 write[0x1];
433 u8 read[0x1];
434 u8 atomic[0x1];
435 u8 srq_receive[0x1];
436 u8 reserved_at_6[0x1a];
437 };
438
439 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
440 u8 smac_47_16[0x20];
441
442 u8 smac_15_0[0x10];
443 u8 ethertype[0x10];
444
445 u8 dmac_47_16[0x20];
446
447 u8 dmac_15_0[0x10];
448 u8 first_prio[0x3];
449 u8 first_cfi[0x1];
450 u8 first_vid[0xc];
451
452 u8 ip_protocol[0x8];
453 u8 ip_dscp[0x6];
454 u8 ip_ecn[0x2];
455 u8 cvlan_tag[0x1];
456 u8 svlan_tag[0x1];
457 u8 frag[0x1];
458 u8 ip_version[0x4];
459 u8 tcp_flags[0x9];
460
461 u8 tcp_sport[0x10];
462 u8 tcp_dport[0x10];
463
464 u8 reserved_at_c0[0x18];
465 u8 ttl_hoplimit[0x8];
466
467 u8 udp_sport[0x10];
468 u8 udp_dport[0x10];
469
470 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
471
472 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
473 };
474
475 struct mlx5_ifc_nvgre_key_bits {
476 u8 hi[0x18];
477 u8 lo[0x8];
478 };
479
480 union mlx5_ifc_gre_key_bits {
481 struct mlx5_ifc_nvgre_key_bits nvgre;
482 u8 key[0x20];
483 };
484
485 struct mlx5_ifc_fte_match_set_misc_bits {
486 u8 reserved_at_0[0x8];
487 u8 source_sqn[0x18];
488
489 u8 source_eswitch_owner_vhca_id[0x10];
490 u8 source_port[0x10];
491
492 u8 outer_second_prio[0x3];
493 u8 outer_second_cfi[0x1];
494 u8 outer_second_vid[0xc];
495 u8 inner_second_prio[0x3];
496 u8 inner_second_cfi[0x1];
497 u8 inner_second_vid[0xc];
498
499 u8 outer_second_cvlan_tag[0x1];
500 u8 inner_second_cvlan_tag[0x1];
501 u8 outer_second_svlan_tag[0x1];
502 u8 inner_second_svlan_tag[0x1];
503 u8 reserved_at_64[0xc];
504 u8 gre_protocol[0x10];
505
506 union mlx5_ifc_gre_key_bits gre_key;
507
508 u8 vxlan_vni[0x18];
509 u8 reserved_at_b8[0x8];
510
511 u8 geneve_vni[0x18];
512 u8 reserved_at_d8[0x7];
513 u8 geneve_oam[0x1];
514
515 u8 reserved_at_e0[0xc];
516 u8 outer_ipv6_flow_label[0x14];
517
518 u8 reserved_at_100[0xc];
519 u8 inner_ipv6_flow_label[0x14];
520
521 u8 reserved_at_120[0xa];
522 u8 geneve_opt_len[0x6];
523 u8 geneve_protocol_type[0x10];
524
525 u8 reserved_at_140[0x8];
526 u8 bth_dst_qp[0x18];
527 u8 reserved_at_160[0x20];
528 u8 outer_esp_spi[0x20];
529 u8 reserved_at_1a0[0x60];
530 };
531
532 struct mlx5_ifc_fte_match_mpls_bits {
533 u8 mpls_label[0x14];
534 u8 mpls_exp[0x3];
535 u8 mpls_s_bos[0x1];
536 u8 mpls_ttl[0x8];
537 };
538
539 struct mlx5_ifc_fte_match_set_misc2_bits {
540 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
541
542 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
543
544 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
545
546 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
547
548 u8 metadata_reg_c_7[0x20];
549
550 u8 metadata_reg_c_6[0x20];
551
552 u8 metadata_reg_c_5[0x20];
553
554 u8 metadata_reg_c_4[0x20];
555
556 u8 metadata_reg_c_3[0x20];
557
558 u8 metadata_reg_c_2[0x20];
559
560 u8 metadata_reg_c_1[0x20];
561
562 u8 metadata_reg_c_0[0x20];
563
564 u8 metadata_reg_a[0x20];
565
566 u8 reserved_at_1a0[0x60];
567 };
568
569 struct mlx5_ifc_fte_match_set_misc3_bits {
570 u8 reserved_at_0[0x120];
571 u8 geneve_tlv_option_0_data[0x20];
572 u8 reserved_at_140[0xc0];
573 };
574
575 struct mlx5_ifc_cmd_pas_bits {
576 u8 pa_h[0x20];
577
578 u8 pa_l[0x14];
579 u8 reserved_at_34[0xc];
580 };
581
582 struct mlx5_ifc_uint64_bits {
583 u8 hi[0x20];
584
585 u8 lo[0x20];
586 };
587
588 enum {
589 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
590 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
591 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
592 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
593 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
594 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
595 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
596 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
597 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
598 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
599 };
600
601 struct mlx5_ifc_ads_bits {
602 u8 fl[0x1];
603 u8 free_ar[0x1];
604 u8 reserved_at_2[0xe];
605 u8 pkey_index[0x10];
606
607 u8 reserved_at_20[0x8];
608 u8 grh[0x1];
609 u8 mlid[0x7];
610 u8 rlid[0x10];
611
612 u8 ack_timeout[0x5];
613 u8 reserved_at_45[0x3];
614 u8 src_addr_index[0x8];
615 u8 reserved_at_50[0x4];
616 u8 stat_rate[0x4];
617 u8 hop_limit[0x8];
618
619 u8 reserved_at_60[0x4];
620 u8 tclass[0x8];
621 u8 flow_label[0x14];
622
623 u8 rgid_rip[16][0x8];
624
625 u8 reserved_at_100[0x4];
626 u8 f_dscp[0x1];
627 u8 f_ecn[0x1];
628 u8 reserved_at_106[0x1];
629 u8 f_eth_prio[0x1];
630 u8 ecn[0x2];
631 u8 dscp[0x6];
632 u8 udp_sport[0x10];
633
634 u8 dei_cfi[0x1];
635 u8 eth_prio[0x3];
636 u8 sl[0x4];
637 u8 vhca_port_num[0x8];
638 u8 rmac_47_32[0x10];
639
640 u8 rmac_31_0[0x20];
641 };
642
643 struct mlx5_ifc_flow_table_nic_cap_bits {
644 u8 nic_rx_multi_path_tirs[0x1];
645 u8 nic_rx_multi_path_tirs_fts[0x1];
646 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
647 u8 reserved_at_3[0x1d];
648 u8 encap_general_header[0x1];
649 u8 reserved_at_21[0xa];
650 u8 log_max_packet_reformat_context[0x5];
651 u8 reserved_at_30[0x6];
652 u8 max_encap_header_size[0xa];
653 u8 reserved_at_40[0x1c0];
654
655 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
656
657 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
658
659 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
660
661 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
662
663 u8 reserved_at_a00[0x200];
664
665 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
666
667 u8 reserved_at_e00[0x7200];
668 };
669
670 enum {
671 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
672 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
673 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
674 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
675 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
676 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
677 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
678 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
679 };
680
681 struct mlx5_ifc_flow_table_eswitch_cap_bits {
682 u8 fdb_to_vport_reg_c_id[0x8];
683 u8 reserved_at_8[0xf];
684 u8 flow_source[0x1];
685 u8 reserved_at_18[0x2];
686 u8 multi_fdb_encap[0x1];
687 u8 reserved_at_1b[0x1];
688 u8 fdb_multi_path_to_table[0x1];
689 u8 reserved_at_1d[0x3];
690
691 u8 reserved_at_20[0x1e0];
692
693 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
694
695 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
696
697 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
698
699 u8 reserved_at_800[0x7800];
700 };
701
702 enum {
703 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
704 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
705 };
706
707 struct mlx5_ifc_e_switch_cap_bits {
708 u8 vport_svlan_strip[0x1];
709 u8 vport_cvlan_strip[0x1];
710 u8 vport_svlan_insert[0x1];
711 u8 vport_cvlan_insert_if_not_exist[0x1];
712 u8 vport_cvlan_insert_overwrite[0x1];
713 u8 reserved_at_5[0x3];
714 u8 esw_uplink_ingress_acl[0x1];
715 u8 reserved_at_9[0x10];
716 u8 esw_functions_changed[0x1];
717 u8 reserved_at_1a[0x1];
718 u8 ecpf_vport_exists[0x1];
719 u8 counter_eswitch_affinity[0x1];
720 u8 merged_eswitch[0x1];
721 u8 nic_vport_node_guid_modify[0x1];
722 u8 nic_vport_port_guid_modify[0x1];
723
724 u8 vxlan_encap_decap[0x1];
725 u8 nvgre_encap_decap[0x1];
726 u8 reserved_at_22[0x1];
727 u8 log_max_fdb_encap_uplink[0x5];
728 u8 reserved_at_21[0x3];
729 u8 log_max_packet_reformat_context[0x5];
730 u8 reserved_2b[0x6];
731 u8 max_encap_header_size[0xa];
732
733 u8 reserved_at_40[0xb];
734 u8 log_max_esw_sf[0x5];
735 u8 esw_sf_base_id[0x10];
736
737 u8 reserved_at_60[0x7a0];
738
739 };
740
741 struct mlx5_ifc_qos_cap_bits {
742 u8 packet_pacing[0x1];
743 u8 esw_scheduling[0x1];
744 u8 esw_bw_share[0x1];
745 u8 esw_rate_limit[0x1];
746 u8 reserved_at_4[0x1];
747 u8 packet_pacing_burst_bound[0x1];
748 u8 packet_pacing_typical_size[0x1];
749 u8 reserved_at_7[0x19];
750
751 u8 reserved_at_20[0x20];
752
753 u8 packet_pacing_max_rate[0x20];
754
755 u8 packet_pacing_min_rate[0x20];
756
757 u8 reserved_at_80[0x10];
758 u8 packet_pacing_rate_table_size[0x10];
759
760 u8 esw_element_type[0x10];
761 u8 esw_tsar_type[0x10];
762
763 u8 reserved_at_c0[0x10];
764 u8 max_qos_para_vport[0x10];
765
766 u8 max_tsar_bw_share[0x20];
767
768 u8 reserved_at_100[0x700];
769 };
770
771 struct mlx5_ifc_debug_cap_bits {
772 u8 core_dump_general[0x1];
773 u8 core_dump_qp[0x1];
774 u8 reserved_at_2[0x1e];
775
776 u8 reserved_at_20[0x2];
777 u8 stall_detect[0x1];
778 u8 reserved_at_23[0x1d];
779
780 u8 reserved_at_40[0x7c0];
781 };
782
783 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
784 u8 csum_cap[0x1];
785 u8 vlan_cap[0x1];
786 u8 lro_cap[0x1];
787 u8 lro_psh_flag[0x1];
788 u8 lro_time_stamp[0x1];
789 u8 reserved_at_5[0x2];
790 u8 wqe_vlan_insert[0x1];
791 u8 self_lb_en_modifiable[0x1];
792 u8 reserved_at_9[0x2];
793 u8 max_lso_cap[0x5];
794 u8 multi_pkt_send_wqe[0x2];
795 u8 wqe_inline_mode[0x2];
796 u8 rss_ind_tbl_cap[0x4];
797 u8 reg_umr_sq[0x1];
798 u8 scatter_fcs[0x1];
799 u8 enhanced_multi_pkt_send_wqe[0x1];
800 u8 tunnel_lso_const_out_ip_id[0x1];
801 u8 reserved_at_1c[0x2];
802 u8 tunnel_stateless_gre[0x1];
803 u8 tunnel_stateless_vxlan[0x1];
804
805 u8 swp[0x1];
806 u8 swp_csum[0x1];
807 u8 swp_lso[0x1];
808 u8 cqe_checksum_full[0x1];
809 u8 reserved_at_24[0xc];
810 u8 max_vxlan_udp_ports[0x8];
811 u8 reserved_at_38[0x6];
812 u8 max_geneve_opt_len[0x1];
813 u8 tunnel_stateless_geneve_rx[0x1];
814
815 u8 reserved_at_40[0x10];
816 u8 lro_min_mss_size[0x10];
817
818 u8 reserved_at_60[0x120];
819
820 u8 lro_timer_supported_periods[4][0x20];
821
822 u8 reserved_at_200[0x600];
823 };
824
825 struct mlx5_ifc_roce_cap_bits {
826 u8 roce_apm[0x1];
827 u8 reserved_at_1[0x1f];
828
829 u8 reserved_at_20[0x60];
830
831 u8 reserved_at_80[0xc];
832 u8 l3_type[0x4];
833 u8 reserved_at_90[0x8];
834 u8 roce_version[0x8];
835
836 u8 reserved_at_a0[0x10];
837 u8 r_roce_dest_udp_port[0x10];
838
839 u8 r_roce_max_src_udp_port[0x10];
840 u8 r_roce_min_src_udp_port[0x10];
841
842 u8 reserved_at_e0[0x10];
843 u8 roce_address_table_size[0x10];
844
845 u8 reserved_at_100[0x700];
846 };
847
848 struct mlx5_ifc_device_mem_cap_bits {
849 u8 memic[0x1];
850 u8 reserved_at_1[0x1f];
851
852 u8 reserved_at_20[0xb];
853 u8 log_min_memic_alloc_size[0x5];
854 u8 reserved_at_30[0x8];
855 u8 log_max_memic_addr_alignment[0x8];
856
857 u8 memic_bar_start_addr[0x40];
858
859 u8 memic_bar_size[0x20];
860
861 u8 max_memic_size[0x20];
862
863 u8 steering_sw_icm_start_address[0x40];
864
865 u8 reserved_at_100[0x8];
866 u8 log_header_modify_sw_icm_size[0x8];
867 u8 reserved_at_110[0x2];
868 u8 log_sw_icm_alloc_granularity[0x6];
869 u8 log_steering_sw_icm_size[0x8];
870
871 u8 reserved_at_120[0x20];
872
873 u8 header_modify_sw_icm_start_address[0x40];
874
875 u8 reserved_at_180[0x680];
876 };
877
878 struct mlx5_ifc_device_event_cap_bits {
879 u8 user_affiliated_events[4][0x40];
880
881 u8 user_unaffiliated_events[4][0x40];
882 };
883
884 enum {
885 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
886 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
887 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
888 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
889 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
890 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
891 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
892 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
893 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
894 };
895
896 enum {
897 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
898 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
899 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
900 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
901 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
902 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
903 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
904 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
905 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
906 };
907
908 struct mlx5_ifc_atomic_caps_bits {
909 u8 reserved_at_0[0x40];
910
911 u8 atomic_req_8B_endianness_mode[0x2];
912 u8 reserved_at_42[0x4];
913 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
914
915 u8 reserved_at_47[0x19];
916
917 u8 reserved_at_60[0x20];
918
919 u8 reserved_at_80[0x10];
920 u8 atomic_operations[0x10];
921
922 u8 reserved_at_a0[0x10];
923 u8 atomic_size_qp[0x10];
924
925 u8 reserved_at_c0[0x10];
926 u8 atomic_size_dc[0x10];
927
928 u8 reserved_at_e0[0x720];
929 };
930
931 struct mlx5_ifc_odp_cap_bits {
932 u8 reserved_at_0[0x40];
933
934 u8 sig[0x1];
935 u8 reserved_at_41[0x1f];
936
937 u8 reserved_at_60[0x20];
938
939 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
940
941 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
942
943 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
944
945 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
946
947 u8 reserved_at_100[0x700];
948 };
949
950 struct mlx5_ifc_calc_op {
951 u8 reserved_at_0[0x10];
952 u8 reserved_at_10[0x9];
953 u8 op_swap_endianness[0x1];
954 u8 op_min[0x1];
955 u8 op_xor[0x1];
956 u8 op_or[0x1];
957 u8 op_and[0x1];
958 u8 op_max[0x1];
959 u8 op_add[0x1];
960 };
961
962 struct mlx5_ifc_vector_calc_cap_bits {
963 u8 calc_matrix[0x1];
964 u8 reserved_at_1[0x1f];
965 u8 reserved_at_20[0x8];
966 u8 max_vec_count[0x8];
967 u8 reserved_at_30[0xd];
968 u8 max_chunk_size[0x3];
969 struct mlx5_ifc_calc_op calc0;
970 struct mlx5_ifc_calc_op calc1;
971 struct mlx5_ifc_calc_op calc2;
972 struct mlx5_ifc_calc_op calc3;
973
974 u8 reserved_at_c0[0x720];
975 };
976
977 struct mlx5_ifc_tls_cap_bits {
978 u8 tls_1_2_aes_gcm_128[0x1];
979 u8 tls_1_3_aes_gcm_128[0x1];
980 u8 tls_1_2_aes_gcm_256[0x1];
981 u8 tls_1_3_aes_gcm_256[0x1];
982 u8 reserved_at_4[0x1c];
983
984 u8 reserved_at_20[0x7e0];
985 };
986
987 enum {
988 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
989 MLX5_WQ_TYPE_CYCLIC = 0x1,
990 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
991 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
992 };
993
994 enum {
995 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
996 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
997 };
998
999 enum {
1000 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1001 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1002 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1003 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1004 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1005 };
1006
1007 enum {
1008 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1009 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1010 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1011 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1012 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1013 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1014 };
1015
1016 enum {
1017 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1018 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1019 };
1020
1021 enum {
1022 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1023 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1024 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1025 };
1026
1027 enum {
1028 MLX5_CAP_PORT_TYPE_IB = 0x0,
1029 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1030 };
1031
1032 enum {
1033 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1034 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1035 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1036 };
1037
1038 enum {
1039 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1040 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1041 };
1042
1043 struct mlx5_ifc_cmd_hca_cap_bits {
1044 u8 reserved_at_0[0x30];
1045 u8 vhca_id[0x10];
1046
1047 u8 reserved_at_40[0x40];
1048
1049 u8 log_max_srq_sz[0x8];
1050 u8 log_max_qp_sz[0x8];
1051 u8 event_cap[0x1];
1052 u8 reserved_at_91[0x7];
1053 u8 prio_tag_required[0x1];
1054 u8 reserved_at_99[0x2];
1055 u8 log_max_qp[0x5];
1056
1057 u8 reserved_at_a0[0xb];
1058 u8 log_max_srq[0x5];
1059 u8 reserved_at_b0[0x10];
1060
1061 u8 reserved_at_c0[0x8];
1062 u8 log_max_cq_sz[0x8];
1063 u8 reserved_at_d0[0xb];
1064 u8 log_max_cq[0x5];
1065
1066 u8 log_max_eq_sz[0x8];
1067 u8 reserved_at_e8[0x2];
1068 u8 log_max_mkey[0x6];
1069 u8 reserved_at_f0[0x8];
1070 u8 dump_fill_mkey[0x1];
1071 u8 reserved_at_f9[0x2];
1072 u8 fast_teardown[0x1];
1073 u8 log_max_eq[0x4];
1074
1075 u8 max_indirection[0x8];
1076 u8 fixed_buffer_size[0x1];
1077 u8 log_max_mrw_sz[0x7];
1078 u8 force_teardown[0x1];
1079 u8 reserved_at_111[0x1];
1080 u8 log_max_bsf_list_size[0x6];
1081 u8 umr_extended_translation_offset[0x1];
1082 u8 null_mkey[0x1];
1083 u8 log_max_klm_list_size[0x6];
1084
1085 u8 reserved_at_120[0xa];
1086 u8 log_max_ra_req_dc[0x6];
1087 u8 reserved_at_130[0xa];
1088 u8 log_max_ra_res_dc[0x6];
1089
1090 u8 reserved_at_140[0xa];
1091 u8 log_max_ra_req_qp[0x6];
1092 u8 reserved_at_150[0xa];
1093 u8 log_max_ra_res_qp[0x6];
1094
1095 u8 end_pad[0x1];
1096 u8 cc_query_allowed[0x1];
1097 u8 cc_modify_allowed[0x1];
1098 u8 start_pad[0x1];
1099 u8 cache_line_128byte[0x1];
1100 u8 reserved_at_165[0x4];
1101 u8 rts2rts_qp_counters_set_id[0x1];
1102 u8 reserved_at_16a[0x5];
1103 u8 qcam_reg[0x1];
1104 u8 gid_table_size[0x10];
1105
1106 u8 out_of_seq_cnt[0x1];
1107 u8 vport_counters[0x1];
1108 u8 retransmission_q_counters[0x1];
1109 u8 debug[0x1];
1110 u8 modify_rq_counter_set_id[0x1];
1111 u8 rq_delay_drop[0x1];
1112 u8 max_qp_cnt[0xa];
1113 u8 pkey_table_size[0x10];
1114
1115 u8 vport_group_manager[0x1];
1116 u8 vhca_group_manager[0x1];
1117 u8 ib_virt[0x1];
1118 u8 eth_virt[0x1];
1119 u8 vnic_env_queue_counters[0x1];
1120 u8 ets[0x1];
1121 u8 nic_flow_table[0x1];
1122 u8 eswitch_manager[0x1];
1123 u8 device_memory[0x1];
1124 u8 mcam_reg[0x1];
1125 u8 pcam_reg[0x1];
1126 u8 local_ca_ack_delay[0x5];
1127 u8 port_module_event[0x1];
1128 u8 enhanced_error_q_counters[0x1];
1129 u8 ports_check[0x1];
1130 u8 reserved_at_1b3[0x1];
1131 u8 disable_link_up[0x1];
1132 u8 beacon_led[0x1];
1133 u8 port_type[0x2];
1134 u8 num_ports[0x8];
1135
1136 u8 reserved_at_1c0[0x1];
1137 u8 pps[0x1];
1138 u8 pps_modify[0x1];
1139 u8 log_max_msg[0x5];
1140 u8 reserved_at_1c8[0x4];
1141 u8 max_tc[0x4];
1142 u8 temp_warn_event[0x1];
1143 u8 dcbx[0x1];
1144 u8 general_notification_event[0x1];
1145 u8 reserved_at_1d3[0x2];
1146 u8 fpga[0x1];
1147 u8 rol_s[0x1];
1148 u8 rol_g[0x1];
1149 u8 reserved_at_1d8[0x1];
1150 u8 wol_s[0x1];
1151 u8 wol_g[0x1];
1152 u8 wol_a[0x1];
1153 u8 wol_b[0x1];
1154 u8 wol_m[0x1];
1155 u8 wol_u[0x1];
1156 u8 wol_p[0x1];
1157
1158 u8 stat_rate_support[0x10];
1159 u8 reserved_at_1f0[0xc];
1160 u8 cqe_version[0x4];
1161
1162 u8 compact_address_vector[0x1];
1163 u8 striding_rq[0x1];
1164 u8 reserved_at_202[0x1];
1165 u8 ipoib_enhanced_offloads[0x1];
1166 u8 ipoib_basic_offloads[0x1];
1167 u8 reserved_at_205[0x1];
1168 u8 repeated_block_disabled[0x1];
1169 u8 umr_modify_entity_size_disabled[0x1];
1170 u8 umr_modify_atomic_disabled[0x1];
1171 u8 umr_indirect_mkey_disabled[0x1];
1172 u8 umr_fence[0x2];
1173 u8 dc_req_scat_data_cqe[0x1];
1174 u8 reserved_at_20d[0x2];
1175 u8 drain_sigerr[0x1];
1176 u8 cmdif_checksum[0x2];
1177 u8 sigerr_cqe[0x1];
1178 u8 reserved_at_213[0x1];
1179 u8 wq_signature[0x1];
1180 u8 sctr_data_cqe[0x1];
1181 u8 reserved_at_216[0x1];
1182 u8 sho[0x1];
1183 u8 tph[0x1];
1184 u8 rf[0x1];
1185 u8 dct[0x1];
1186 u8 qos[0x1];
1187 u8 eth_net_offloads[0x1];
1188 u8 roce[0x1];
1189 u8 atomic[0x1];
1190 u8 reserved_at_21f[0x1];
1191
1192 u8 cq_oi[0x1];
1193 u8 cq_resize[0x1];
1194 u8 cq_moderation[0x1];
1195 u8 reserved_at_223[0x3];
1196 u8 cq_eq_remap[0x1];
1197 u8 pg[0x1];
1198 u8 block_lb_mc[0x1];
1199 u8 reserved_at_229[0x1];
1200 u8 scqe_break_moderation[0x1];
1201 u8 cq_period_start_from_cqe[0x1];
1202 u8 cd[0x1];
1203 u8 reserved_at_22d[0x1];
1204 u8 apm[0x1];
1205 u8 vector_calc[0x1];
1206 u8 umr_ptr_rlky[0x1];
1207 u8 imaicl[0x1];
1208 u8 qp_packet_based[0x1];
1209 u8 reserved_at_233[0x3];
1210 u8 qkv[0x1];
1211 u8 pkv[0x1];
1212 u8 set_deth_sqpn[0x1];
1213 u8 reserved_at_239[0x3];
1214 u8 xrc[0x1];
1215 u8 ud[0x1];
1216 u8 uc[0x1];
1217 u8 rc[0x1];
1218
1219 u8 uar_4k[0x1];
1220 u8 reserved_at_241[0x9];
1221 u8 uar_sz[0x6];
1222 u8 reserved_at_250[0x8];
1223 u8 log_pg_sz[0x8];
1224
1225 u8 bf[0x1];
1226 u8 driver_version[0x1];
1227 u8 pad_tx_eth_packet[0x1];
1228 u8 reserved_at_263[0x8];
1229 u8 log_bf_reg_size[0x5];
1230
1231 u8 reserved_at_270[0xb];
1232 u8 lag_master[0x1];
1233 u8 num_lag_ports[0x4];
1234
1235 u8 reserved_at_280[0x10];
1236 u8 max_wqe_sz_sq[0x10];
1237
1238 u8 reserved_at_2a0[0x10];
1239 u8 max_wqe_sz_rq[0x10];
1240
1241 u8 max_flow_counter_31_16[0x10];
1242 u8 max_wqe_sz_sq_dc[0x10];
1243
1244 u8 reserved_at_2e0[0x7];
1245 u8 max_qp_mcg[0x19];
1246
1247 u8 reserved_at_300[0x18];
1248 u8 log_max_mcg[0x8];
1249
1250 u8 reserved_at_320[0x3];
1251 u8 log_max_transport_domain[0x5];
1252 u8 reserved_at_328[0x3];
1253 u8 log_max_pd[0x5];
1254 u8 reserved_at_330[0xb];
1255 u8 log_max_xrcd[0x5];
1256
1257 u8 nic_receive_steering_discard[0x1];
1258 u8 receive_discard_vport_down[0x1];
1259 u8 transmit_discard_vport_down[0x1];
1260 u8 reserved_at_343[0x5];
1261 u8 log_max_flow_counter_bulk[0x8];
1262 u8 max_flow_counter_15_0[0x10];
1263
1264
1265 u8 reserved_at_360[0x3];
1266 u8 log_max_rq[0x5];
1267 u8 reserved_at_368[0x3];
1268 u8 log_max_sq[0x5];
1269 u8 reserved_at_370[0x3];
1270 u8 log_max_tir[0x5];
1271 u8 reserved_at_378[0x3];
1272 u8 log_max_tis[0x5];
1273
1274 u8 basic_cyclic_rcv_wqe[0x1];
1275 u8 reserved_at_381[0x2];
1276 u8 log_max_rmp[0x5];
1277 u8 reserved_at_388[0x3];
1278 u8 log_max_rqt[0x5];
1279 u8 reserved_at_390[0x3];
1280 u8 log_max_rqt_size[0x5];
1281 u8 reserved_at_398[0x3];
1282 u8 log_max_tis_per_sq[0x5];
1283
1284 u8 ext_stride_num_range[0x1];
1285 u8 reserved_at_3a1[0x2];
1286 u8 log_max_stride_sz_rq[0x5];
1287 u8 reserved_at_3a8[0x3];
1288 u8 log_min_stride_sz_rq[0x5];
1289 u8 reserved_at_3b0[0x3];
1290 u8 log_max_stride_sz_sq[0x5];
1291 u8 reserved_at_3b8[0x3];
1292 u8 log_min_stride_sz_sq[0x5];
1293
1294 u8 hairpin[0x1];
1295 u8 reserved_at_3c1[0x2];
1296 u8 log_max_hairpin_queues[0x5];
1297 u8 reserved_at_3c8[0x3];
1298 u8 log_max_hairpin_wq_data_sz[0x5];
1299 u8 reserved_at_3d0[0x3];
1300 u8 log_max_hairpin_num_packets[0x5];
1301 u8 reserved_at_3d8[0x3];
1302 u8 log_max_wq_sz[0x5];
1303
1304 u8 nic_vport_change_event[0x1];
1305 u8 disable_local_lb_uc[0x1];
1306 u8 disable_local_lb_mc[0x1];
1307 u8 log_min_hairpin_wq_data_sz[0x5];
1308 u8 reserved_at_3e8[0x3];
1309 u8 log_max_vlan_list[0x5];
1310 u8 reserved_at_3f0[0x3];
1311 u8 log_max_current_mc_list[0x5];
1312 u8 reserved_at_3f8[0x3];
1313 u8 log_max_current_uc_list[0x5];
1314
1315 u8 general_obj_types[0x40];
1316
1317 u8 reserved_at_440[0x20];
1318
1319 u8 tls[0x1];
1320 u8 reserved_at_461[0x2];
1321 u8 log_max_uctx[0x5];
1322 u8 reserved_at_468[0x3];
1323 u8 log_max_umem[0x5];
1324 u8 max_num_eqs[0x10];
1325
1326 u8 reserved_at_480[0x3];
1327 u8 log_max_l2_table[0x5];
1328 u8 reserved_at_488[0x8];
1329 u8 log_uar_page_sz[0x10];
1330
1331 u8 reserved_at_4a0[0x20];
1332 u8 device_frequency_mhz[0x20];
1333 u8 device_frequency_khz[0x20];
1334
1335 u8 reserved_at_500[0x20];
1336 u8 num_of_uars_per_page[0x20];
1337
1338 u8 flex_parser_protocols[0x20];
1339
1340 u8 max_geneve_tlv_options[0x8];
1341 u8 reserved_at_568[0x3];
1342 u8 max_geneve_tlv_option_data_len[0x5];
1343 u8 reserved_at_570[0x10];
1344
1345 u8 reserved_at_580[0x33];
1346 u8 log_max_dek[0x5];
1347 u8 reserved_at_5b8[0x4];
1348 u8 mini_cqe_resp_stride_index[0x1];
1349 u8 cqe_128_always[0x1];
1350 u8 cqe_compression_128[0x1];
1351 u8 cqe_compression[0x1];
1352
1353 u8 cqe_compression_timeout[0x10];
1354 u8 cqe_compression_max_num[0x10];
1355
1356 u8 reserved_at_5e0[0x10];
1357 u8 tag_matching[0x1];
1358 u8 rndv_offload_rc[0x1];
1359 u8 rndv_offload_dc[0x1];
1360 u8 log_tag_matching_list_sz[0x5];
1361 u8 reserved_at_5f8[0x3];
1362 u8 log_max_xrq[0x5];
1363
1364 u8 affiliate_nic_vport_criteria[0x8];
1365 u8 native_port_num[0x8];
1366 u8 num_vhca_ports[0x8];
1367 u8 reserved_at_618[0x6];
1368 u8 sw_owner_id[0x1];
1369 u8 reserved_at_61f[0x1];
1370
1371 u8 max_num_of_monitor_counters[0x10];
1372 u8 num_ppcnt_monitor_counters[0x10];
1373
1374 u8 reserved_at_640[0x10];
1375 u8 num_q_monitor_counters[0x10];
1376
1377 u8 reserved_at_660[0x20];
1378
1379 u8 sf[0x1];
1380 u8 sf_set_partition[0x1];
1381 u8 reserved_at_682[0x1];
1382 u8 log_max_sf[0x5];
1383 u8 reserved_at_688[0x8];
1384 u8 log_min_sf_size[0x8];
1385 u8 max_num_sf_partitions[0x8];
1386
1387 u8 uctx_cap[0x20];
1388
1389 u8 reserved_at_6c0[0x4];
1390 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1391 u8 reserved_at_6c8[0x28];
1392 u8 sf_base_id[0x10];
1393
1394 u8 reserved_at_700[0x80];
1395 u8 vhca_tunnel_commands[0x40];
1396 u8 reserved_at_7c0[0x40];
1397 };
1398
1399 enum mlx5_flow_destination_type {
1400 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1401 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1402 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1403
1404 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1405 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1406 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1407 };
1408
1409 enum mlx5_flow_table_miss_action {
1410 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1411 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1412 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1413 };
1414
1415 struct mlx5_ifc_dest_format_struct_bits {
1416 u8 destination_type[0x8];
1417 u8 destination_id[0x18];
1418
1419 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1420 u8 packet_reformat[0x1];
1421 u8 reserved_at_22[0xe];
1422 u8 destination_eswitch_owner_vhca_id[0x10];
1423 };
1424
1425 struct mlx5_ifc_flow_counter_list_bits {
1426 u8 flow_counter_id[0x20];
1427
1428 u8 reserved_at_20[0x20];
1429 };
1430
1431 struct mlx5_ifc_extended_dest_format_bits {
1432 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1433
1434 u8 packet_reformat_id[0x20];
1435
1436 u8 reserved_at_60[0x20];
1437 };
1438
1439 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1440 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1441 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1442 u8 reserved_at_0[0x40];
1443 };
1444
1445 struct mlx5_ifc_fte_match_param_bits {
1446 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1447
1448 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1449
1450 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1451
1452 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1453
1454 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1455
1456 u8 reserved_at_a00[0x600];
1457 };
1458
1459 enum {
1460 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1461 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1462 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1463 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1464 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1465 };
1466
1467 struct mlx5_ifc_rx_hash_field_select_bits {
1468 u8 l3_prot_type[0x1];
1469 u8 l4_prot_type[0x1];
1470 u8 selected_fields[0x1e];
1471 };
1472
1473 enum {
1474 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1475 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1476 };
1477
1478 enum {
1479 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1480 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1481 };
1482
1483 struct mlx5_ifc_wq_bits {
1484 u8 wq_type[0x4];
1485 u8 wq_signature[0x1];
1486 u8 end_padding_mode[0x2];
1487 u8 cd_slave[0x1];
1488 u8 reserved_at_8[0x18];
1489
1490 u8 hds_skip_first_sge[0x1];
1491 u8 log2_hds_buf_size[0x3];
1492 u8 reserved_at_24[0x7];
1493 u8 page_offset[0x5];
1494 u8 lwm[0x10];
1495
1496 u8 reserved_at_40[0x8];
1497 u8 pd[0x18];
1498
1499 u8 reserved_at_60[0x8];
1500 u8 uar_page[0x18];
1501
1502 u8 dbr_addr[0x40];
1503
1504 u8 hw_counter[0x20];
1505
1506 u8 sw_counter[0x20];
1507
1508 u8 reserved_at_100[0xc];
1509 u8 log_wq_stride[0x4];
1510 u8 reserved_at_110[0x3];
1511 u8 log_wq_pg_sz[0x5];
1512 u8 reserved_at_118[0x3];
1513 u8 log_wq_sz[0x5];
1514
1515 u8 dbr_umem_valid[0x1];
1516 u8 wq_umem_valid[0x1];
1517 u8 reserved_at_122[0x1];
1518 u8 log_hairpin_num_packets[0x5];
1519 u8 reserved_at_128[0x3];
1520 u8 log_hairpin_data_sz[0x5];
1521
1522 u8 reserved_at_130[0x4];
1523 u8 log_wqe_num_of_strides[0x4];
1524 u8 two_byte_shift_en[0x1];
1525 u8 reserved_at_139[0x4];
1526 u8 log_wqe_stride_size[0x3];
1527
1528 u8 reserved_at_140[0x4c0];
1529
1530 struct mlx5_ifc_cmd_pas_bits pas[0];
1531 };
1532
1533 struct mlx5_ifc_rq_num_bits {
1534 u8 reserved_at_0[0x8];
1535 u8 rq_num[0x18];
1536 };
1537
1538 struct mlx5_ifc_mac_address_layout_bits {
1539 u8 reserved_at_0[0x10];
1540 u8 mac_addr_47_32[0x10];
1541
1542 u8 mac_addr_31_0[0x20];
1543 };
1544
1545 struct mlx5_ifc_vlan_layout_bits {
1546 u8 reserved_at_0[0x14];
1547 u8 vlan[0x0c];
1548
1549 u8 reserved_at_20[0x20];
1550 };
1551
1552 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1553 u8 reserved_at_0[0xa0];
1554
1555 u8 min_time_between_cnps[0x20];
1556
1557 u8 reserved_at_c0[0x12];
1558 u8 cnp_dscp[0x6];
1559 u8 reserved_at_d8[0x4];
1560 u8 cnp_prio_mode[0x1];
1561 u8 cnp_802p_prio[0x3];
1562
1563 u8 reserved_at_e0[0x720];
1564 };
1565
1566 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1567 u8 reserved_at_0[0x60];
1568
1569 u8 reserved_at_60[0x4];
1570 u8 clamp_tgt_rate[0x1];
1571 u8 reserved_at_65[0x3];
1572 u8 clamp_tgt_rate_after_time_inc[0x1];
1573 u8 reserved_at_69[0x17];
1574
1575 u8 reserved_at_80[0x20];
1576
1577 u8 rpg_time_reset[0x20];
1578
1579 u8 rpg_byte_reset[0x20];
1580
1581 u8 rpg_threshold[0x20];
1582
1583 u8 rpg_max_rate[0x20];
1584
1585 u8 rpg_ai_rate[0x20];
1586
1587 u8 rpg_hai_rate[0x20];
1588
1589 u8 rpg_gd[0x20];
1590
1591 u8 rpg_min_dec_fac[0x20];
1592
1593 u8 rpg_min_rate[0x20];
1594
1595 u8 reserved_at_1c0[0xe0];
1596
1597 u8 rate_to_set_on_first_cnp[0x20];
1598
1599 u8 dce_tcp_g[0x20];
1600
1601 u8 dce_tcp_rtt[0x20];
1602
1603 u8 rate_reduce_monitor_period[0x20];
1604
1605 u8 reserved_at_320[0x20];
1606
1607 u8 initial_alpha_value[0x20];
1608
1609 u8 reserved_at_360[0x4a0];
1610 };
1611
1612 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1613 u8 reserved_at_0[0x80];
1614
1615 u8 rppp_max_rps[0x20];
1616
1617 u8 rpg_time_reset[0x20];
1618
1619 u8 rpg_byte_reset[0x20];
1620
1621 u8 rpg_threshold[0x20];
1622
1623 u8 rpg_max_rate[0x20];
1624
1625 u8 rpg_ai_rate[0x20];
1626
1627 u8 rpg_hai_rate[0x20];
1628
1629 u8 rpg_gd[0x20];
1630
1631 u8 rpg_min_dec_fac[0x20];
1632
1633 u8 rpg_min_rate[0x20];
1634
1635 u8 reserved_at_1c0[0x640];
1636 };
1637
1638 enum {
1639 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1640 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1641 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1642 };
1643
1644 struct mlx5_ifc_resize_field_select_bits {
1645 u8 resize_field_select[0x20];
1646 };
1647
1648 enum {
1649 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1650 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1651 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1652 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1653 };
1654
1655 struct mlx5_ifc_modify_field_select_bits {
1656 u8 modify_field_select[0x20];
1657 };
1658
1659 struct mlx5_ifc_field_select_r_roce_np_bits {
1660 u8 field_select_r_roce_np[0x20];
1661 };
1662
1663 struct mlx5_ifc_field_select_r_roce_rp_bits {
1664 u8 field_select_r_roce_rp[0x20];
1665 };
1666
1667 enum {
1668 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1669 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1670 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1671 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1672 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1673 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1674 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1675 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1676 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1677 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1678 };
1679
1680 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1681 u8 field_select_8021qaurp[0x20];
1682 };
1683
1684 struct mlx5_ifc_phys_layer_cntrs_bits {
1685 u8 time_since_last_clear_high[0x20];
1686
1687 u8 time_since_last_clear_low[0x20];
1688
1689 u8 symbol_errors_high[0x20];
1690
1691 u8 symbol_errors_low[0x20];
1692
1693 u8 sync_headers_errors_high[0x20];
1694
1695 u8 sync_headers_errors_low[0x20];
1696
1697 u8 edpl_bip_errors_lane0_high[0x20];
1698
1699 u8 edpl_bip_errors_lane0_low[0x20];
1700
1701 u8 edpl_bip_errors_lane1_high[0x20];
1702
1703 u8 edpl_bip_errors_lane1_low[0x20];
1704
1705 u8 edpl_bip_errors_lane2_high[0x20];
1706
1707 u8 edpl_bip_errors_lane2_low[0x20];
1708
1709 u8 edpl_bip_errors_lane3_high[0x20];
1710
1711 u8 edpl_bip_errors_lane3_low[0x20];
1712
1713 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1714
1715 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1716
1717 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1718
1719 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1720
1721 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1722
1723 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1724
1725 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1726
1727 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1728
1729 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1730
1731 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1732
1733 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1734
1735 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1736
1737 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1738
1739 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1740
1741 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1742
1743 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1744
1745 u8 rs_fec_corrected_blocks_high[0x20];
1746
1747 u8 rs_fec_corrected_blocks_low[0x20];
1748
1749 u8 rs_fec_uncorrectable_blocks_high[0x20];
1750
1751 u8 rs_fec_uncorrectable_blocks_low[0x20];
1752
1753 u8 rs_fec_no_errors_blocks_high[0x20];
1754
1755 u8 rs_fec_no_errors_blocks_low[0x20];
1756
1757 u8 rs_fec_single_error_blocks_high[0x20];
1758
1759 u8 rs_fec_single_error_blocks_low[0x20];
1760
1761 u8 rs_fec_corrected_symbols_total_high[0x20];
1762
1763 u8 rs_fec_corrected_symbols_total_low[0x20];
1764
1765 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1766
1767 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1768
1769 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1770
1771 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1772
1773 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1774
1775 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1776
1777 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1778
1779 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1780
1781 u8 link_down_events[0x20];
1782
1783 u8 successful_recovery_events[0x20];
1784
1785 u8 reserved_at_640[0x180];
1786 };
1787
1788 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1789 u8 time_since_last_clear_high[0x20];
1790
1791 u8 time_since_last_clear_low[0x20];
1792
1793 u8 phy_received_bits_high[0x20];
1794
1795 u8 phy_received_bits_low[0x20];
1796
1797 u8 phy_symbol_errors_high[0x20];
1798
1799 u8 phy_symbol_errors_low[0x20];
1800
1801 u8 phy_corrected_bits_high[0x20];
1802
1803 u8 phy_corrected_bits_low[0x20];
1804
1805 u8 phy_corrected_bits_lane0_high[0x20];
1806
1807 u8 phy_corrected_bits_lane0_low[0x20];
1808
1809 u8 phy_corrected_bits_lane1_high[0x20];
1810
1811 u8 phy_corrected_bits_lane1_low[0x20];
1812
1813 u8 phy_corrected_bits_lane2_high[0x20];
1814
1815 u8 phy_corrected_bits_lane2_low[0x20];
1816
1817 u8 phy_corrected_bits_lane3_high[0x20];
1818
1819 u8 phy_corrected_bits_lane3_low[0x20];
1820
1821 u8 reserved_at_200[0x5c0];
1822 };
1823
1824 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1825 u8 symbol_error_counter[0x10];
1826
1827 u8 link_error_recovery_counter[0x8];
1828
1829 u8 link_downed_counter[0x8];
1830
1831 u8 port_rcv_errors[0x10];
1832
1833 u8 port_rcv_remote_physical_errors[0x10];
1834
1835 u8 port_rcv_switch_relay_errors[0x10];
1836
1837 u8 port_xmit_discards[0x10];
1838
1839 u8 port_xmit_constraint_errors[0x8];
1840
1841 u8 port_rcv_constraint_errors[0x8];
1842
1843 u8 reserved_at_70[0x8];
1844
1845 u8 link_overrun_errors[0x8];
1846
1847 u8 reserved_at_80[0x10];
1848
1849 u8 vl_15_dropped[0x10];
1850
1851 u8 reserved_at_a0[0x80];
1852
1853 u8 port_xmit_wait[0x20];
1854 };
1855
1856 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1857 u8 transmit_queue_high[0x20];
1858
1859 u8 transmit_queue_low[0x20];
1860
1861 u8 reserved_at_40[0x780];
1862 };
1863
1864 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1865 u8 rx_octets_high[0x20];
1866
1867 u8 rx_octets_low[0x20];
1868
1869 u8 reserved_at_40[0xc0];
1870
1871 u8 rx_frames_high[0x20];
1872
1873 u8 rx_frames_low[0x20];
1874
1875 u8 tx_octets_high[0x20];
1876
1877 u8 tx_octets_low[0x20];
1878
1879 u8 reserved_at_180[0xc0];
1880
1881 u8 tx_frames_high[0x20];
1882
1883 u8 tx_frames_low[0x20];
1884
1885 u8 rx_pause_high[0x20];
1886
1887 u8 rx_pause_low[0x20];
1888
1889 u8 rx_pause_duration_high[0x20];
1890
1891 u8 rx_pause_duration_low[0x20];
1892
1893 u8 tx_pause_high[0x20];
1894
1895 u8 tx_pause_low[0x20];
1896
1897 u8 tx_pause_duration_high[0x20];
1898
1899 u8 tx_pause_duration_low[0x20];
1900
1901 u8 rx_pause_transition_high[0x20];
1902
1903 u8 rx_pause_transition_low[0x20];
1904
1905 u8 reserved_at_3c0[0x40];
1906
1907 u8 device_stall_minor_watermark_cnt_high[0x20];
1908
1909 u8 device_stall_minor_watermark_cnt_low[0x20];
1910
1911 u8 device_stall_critical_watermark_cnt_high[0x20];
1912
1913 u8 device_stall_critical_watermark_cnt_low[0x20];
1914
1915 u8 reserved_at_480[0x340];
1916 };
1917
1918 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1919 u8 port_transmit_wait_high[0x20];
1920
1921 u8 port_transmit_wait_low[0x20];
1922
1923 u8 reserved_at_40[0x100];
1924
1925 u8 rx_buffer_almost_full_high[0x20];
1926
1927 u8 rx_buffer_almost_full_low[0x20];
1928
1929 u8 rx_buffer_full_high[0x20];
1930
1931 u8 rx_buffer_full_low[0x20];
1932
1933 u8 rx_icrc_encapsulated_high[0x20];
1934
1935 u8 rx_icrc_encapsulated_low[0x20];
1936
1937 u8 reserved_at_200[0x5c0];
1938 };
1939
1940 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1941 u8 dot3stats_alignment_errors_high[0x20];
1942
1943 u8 dot3stats_alignment_errors_low[0x20];
1944
1945 u8 dot3stats_fcs_errors_high[0x20];
1946
1947 u8 dot3stats_fcs_errors_low[0x20];
1948
1949 u8 dot3stats_single_collision_frames_high[0x20];
1950
1951 u8 dot3stats_single_collision_frames_low[0x20];
1952
1953 u8 dot3stats_multiple_collision_frames_high[0x20];
1954
1955 u8 dot3stats_multiple_collision_frames_low[0x20];
1956
1957 u8 dot3stats_sqe_test_errors_high[0x20];
1958
1959 u8 dot3stats_sqe_test_errors_low[0x20];
1960
1961 u8 dot3stats_deferred_transmissions_high[0x20];
1962
1963 u8 dot3stats_deferred_transmissions_low[0x20];
1964
1965 u8 dot3stats_late_collisions_high[0x20];
1966
1967 u8 dot3stats_late_collisions_low[0x20];
1968
1969 u8 dot3stats_excessive_collisions_high[0x20];
1970
1971 u8 dot3stats_excessive_collisions_low[0x20];
1972
1973 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1974
1975 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1976
1977 u8 dot3stats_carrier_sense_errors_high[0x20];
1978
1979 u8 dot3stats_carrier_sense_errors_low[0x20];
1980
1981 u8 dot3stats_frame_too_longs_high[0x20];
1982
1983 u8 dot3stats_frame_too_longs_low[0x20];
1984
1985 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1986
1987 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1988
1989 u8 dot3stats_symbol_errors_high[0x20];
1990
1991 u8 dot3stats_symbol_errors_low[0x20];
1992
1993 u8 dot3control_in_unknown_opcodes_high[0x20];
1994
1995 u8 dot3control_in_unknown_opcodes_low[0x20];
1996
1997 u8 dot3in_pause_frames_high[0x20];
1998
1999 u8 dot3in_pause_frames_low[0x20];
2000
2001 u8 dot3out_pause_frames_high[0x20];
2002
2003 u8 dot3out_pause_frames_low[0x20];
2004
2005 u8 reserved_at_400[0x3c0];
2006 };
2007
2008 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2009 u8 ether_stats_drop_events_high[0x20];
2010
2011 u8 ether_stats_drop_events_low[0x20];
2012
2013 u8 ether_stats_octets_high[0x20];
2014
2015 u8 ether_stats_octets_low[0x20];
2016
2017 u8 ether_stats_pkts_high[0x20];
2018
2019 u8 ether_stats_pkts_low[0x20];
2020
2021 u8 ether_stats_broadcast_pkts_high[0x20];
2022
2023 u8 ether_stats_broadcast_pkts_low[0x20];
2024
2025 u8 ether_stats_multicast_pkts_high[0x20];
2026
2027 u8 ether_stats_multicast_pkts_low[0x20];
2028
2029 u8 ether_stats_crc_align_errors_high[0x20];
2030
2031 u8 ether_stats_crc_align_errors_low[0x20];
2032
2033 u8 ether_stats_undersize_pkts_high[0x20];
2034
2035 u8 ether_stats_undersize_pkts_low[0x20];
2036
2037 u8 ether_stats_oversize_pkts_high[0x20];
2038
2039 u8 ether_stats_oversize_pkts_low[0x20];
2040
2041 u8 ether_stats_fragments_high[0x20];
2042
2043 u8 ether_stats_fragments_low[0x20];
2044
2045 u8 ether_stats_jabbers_high[0x20];
2046
2047 u8 ether_stats_jabbers_low[0x20];
2048
2049 u8 ether_stats_collisions_high[0x20];
2050
2051 u8 ether_stats_collisions_low[0x20];
2052
2053 u8 ether_stats_pkts64octets_high[0x20];
2054
2055 u8 ether_stats_pkts64octets_low[0x20];
2056
2057 u8 ether_stats_pkts65to127octets_high[0x20];
2058
2059 u8 ether_stats_pkts65to127octets_low[0x20];
2060
2061 u8 ether_stats_pkts128to255octets_high[0x20];
2062
2063 u8 ether_stats_pkts128to255octets_low[0x20];
2064
2065 u8 ether_stats_pkts256to511octets_high[0x20];
2066
2067 u8 ether_stats_pkts256to511octets_low[0x20];
2068
2069 u8 ether_stats_pkts512to1023octets_high[0x20];
2070
2071 u8 ether_stats_pkts512to1023octets_low[0x20];
2072
2073 u8 ether_stats_pkts1024to1518octets_high[0x20];
2074
2075 u8 ether_stats_pkts1024to1518octets_low[0x20];
2076
2077 u8 ether_stats_pkts1519to2047octets_high[0x20];
2078
2079 u8 ether_stats_pkts1519to2047octets_low[0x20];
2080
2081 u8 ether_stats_pkts2048to4095octets_high[0x20];
2082
2083 u8 ether_stats_pkts2048to4095octets_low[0x20];
2084
2085 u8 ether_stats_pkts4096to8191octets_high[0x20];
2086
2087 u8 ether_stats_pkts4096to8191octets_low[0x20];
2088
2089 u8 ether_stats_pkts8192to10239octets_high[0x20];
2090
2091 u8 ether_stats_pkts8192to10239octets_low[0x20];
2092
2093 u8 reserved_at_540[0x280];
2094 };
2095
2096 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2097 u8 if_in_octets_high[0x20];
2098
2099 u8 if_in_octets_low[0x20];
2100
2101 u8 if_in_ucast_pkts_high[0x20];
2102
2103 u8 if_in_ucast_pkts_low[0x20];
2104
2105 u8 if_in_discards_high[0x20];
2106
2107 u8 if_in_discards_low[0x20];
2108
2109 u8 if_in_errors_high[0x20];
2110
2111 u8 if_in_errors_low[0x20];
2112
2113 u8 if_in_unknown_protos_high[0x20];
2114
2115 u8 if_in_unknown_protos_low[0x20];
2116
2117 u8 if_out_octets_high[0x20];
2118
2119 u8 if_out_octets_low[0x20];
2120
2121 u8 if_out_ucast_pkts_high[0x20];
2122
2123 u8 if_out_ucast_pkts_low[0x20];
2124
2125 u8 if_out_discards_high[0x20];
2126
2127 u8 if_out_discards_low[0x20];
2128
2129 u8 if_out_errors_high[0x20];
2130
2131 u8 if_out_errors_low[0x20];
2132
2133 u8 if_in_multicast_pkts_high[0x20];
2134
2135 u8 if_in_multicast_pkts_low[0x20];
2136
2137 u8 if_in_broadcast_pkts_high[0x20];
2138
2139 u8 if_in_broadcast_pkts_low[0x20];
2140
2141 u8 if_out_multicast_pkts_high[0x20];
2142
2143 u8 if_out_multicast_pkts_low[0x20];
2144
2145 u8 if_out_broadcast_pkts_high[0x20];
2146
2147 u8 if_out_broadcast_pkts_low[0x20];
2148
2149 u8 reserved_at_340[0x480];
2150 };
2151
2152 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2153 u8 a_frames_transmitted_ok_high[0x20];
2154
2155 u8 a_frames_transmitted_ok_low[0x20];
2156
2157 u8 a_frames_received_ok_high[0x20];
2158
2159 u8 a_frames_received_ok_low[0x20];
2160
2161 u8 a_frame_check_sequence_errors_high[0x20];
2162
2163 u8 a_frame_check_sequence_errors_low[0x20];
2164
2165 u8 a_alignment_errors_high[0x20];
2166
2167 u8 a_alignment_errors_low[0x20];
2168
2169 u8 a_octets_transmitted_ok_high[0x20];
2170
2171 u8 a_octets_transmitted_ok_low[0x20];
2172
2173 u8 a_octets_received_ok_high[0x20];
2174
2175 u8 a_octets_received_ok_low[0x20];
2176
2177 u8 a_multicast_frames_xmitted_ok_high[0x20];
2178
2179 u8 a_multicast_frames_xmitted_ok_low[0x20];
2180
2181 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2182
2183 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2184
2185 u8 a_multicast_frames_received_ok_high[0x20];
2186
2187 u8 a_multicast_frames_received_ok_low[0x20];
2188
2189 u8 a_broadcast_frames_received_ok_high[0x20];
2190
2191 u8 a_broadcast_frames_received_ok_low[0x20];
2192
2193 u8 a_in_range_length_errors_high[0x20];
2194
2195 u8 a_in_range_length_errors_low[0x20];
2196
2197 u8 a_out_of_range_length_field_high[0x20];
2198
2199 u8 a_out_of_range_length_field_low[0x20];
2200
2201 u8 a_frame_too_long_errors_high[0x20];
2202
2203 u8 a_frame_too_long_errors_low[0x20];
2204
2205 u8 a_symbol_error_during_carrier_high[0x20];
2206
2207 u8 a_symbol_error_during_carrier_low[0x20];
2208
2209 u8 a_mac_control_frames_transmitted_high[0x20];
2210
2211 u8 a_mac_control_frames_transmitted_low[0x20];
2212
2213 u8 a_mac_control_frames_received_high[0x20];
2214
2215 u8 a_mac_control_frames_received_low[0x20];
2216
2217 u8 a_unsupported_opcodes_received_high[0x20];
2218
2219 u8 a_unsupported_opcodes_received_low[0x20];
2220
2221 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2222
2223 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2224
2225 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2226
2227 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2228
2229 u8 reserved_at_4c0[0x300];
2230 };
2231
2232 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2233 u8 life_time_counter_high[0x20];
2234
2235 u8 life_time_counter_low[0x20];
2236
2237 u8 rx_errors[0x20];
2238
2239 u8 tx_errors[0x20];
2240
2241 u8 l0_to_recovery_eieos[0x20];
2242
2243 u8 l0_to_recovery_ts[0x20];
2244
2245 u8 l0_to_recovery_framing[0x20];
2246
2247 u8 l0_to_recovery_retrain[0x20];
2248
2249 u8 crc_error_dllp[0x20];
2250
2251 u8 crc_error_tlp[0x20];
2252
2253 u8 tx_overflow_buffer_pkt_high[0x20];
2254
2255 u8 tx_overflow_buffer_pkt_low[0x20];
2256
2257 u8 outbound_stalled_reads[0x20];
2258
2259 u8 outbound_stalled_writes[0x20];
2260
2261 u8 outbound_stalled_reads_events[0x20];
2262
2263 u8 outbound_stalled_writes_events[0x20];
2264
2265 u8 reserved_at_200[0x5c0];
2266 };
2267
2268 struct mlx5_ifc_cmd_inter_comp_event_bits {
2269 u8 command_completion_vector[0x20];
2270
2271 u8 reserved_at_20[0xc0];
2272 };
2273
2274 struct mlx5_ifc_stall_vl_event_bits {
2275 u8 reserved_at_0[0x18];
2276 u8 port_num[0x1];
2277 u8 reserved_at_19[0x3];
2278 u8 vl[0x4];
2279
2280 u8 reserved_at_20[0xa0];
2281 };
2282
2283 struct mlx5_ifc_db_bf_congestion_event_bits {
2284 u8 event_subtype[0x8];
2285 u8 reserved_at_8[0x8];
2286 u8 congestion_level[0x8];
2287 u8 reserved_at_18[0x8];
2288
2289 u8 reserved_at_20[0xa0];
2290 };
2291
2292 struct mlx5_ifc_gpio_event_bits {
2293 u8 reserved_at_0[0x60];
2294
2295 u8 gpio_event_hi[0x20];
2296
2297 u8 gpio_event_lo[0x20];
2298
2299 u8 reserved_at_a0[0x40];
2300 };
2301
2302 struct mlx5_ifc_port_state_change_event_bits {
2303 u8 reserved_at_0[0x40];
2304
2305 u8 port_num[0x4];
2306 u8 reserved_at_44[0x1c];
2307
2308 u8 reserved_at_60[0x80];
2309 };
2310
2311 struct mlx5_ifc_dropped_packet_logged_bits {
2312 u8 reserved_at_0[0xe0];
2313 };
2314
2315 enum {
2316 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2317 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2318 };
2319
2320 struct mlx5_ifc_cq_error_bits {
2321 u8 reserved_at_0[0x8];
2322 u8 cqn[0x18];
2323
2324 u8 reserved_at_20[0x20];
2325
2326 u8 reserved_at_40[0x18];
2327 u8 syndrome[0x8];
2328
2329 u8 reserved_at_60[0x80];
2330 };
2331
2332 struct mlx5_ifc_rdma_page_fault_event_bits {
2333 u8 bytes_committed[0x20];
2334
2335 u8 r_key[0x20];
2336
2337 u8 reserved_at_40[0x10];
2338 u8 packet_len[0x10];
2339
2340 u8 rdma_op_len[0x20];
2341
2342 u8 rdma_va[0x40];
2343
2344 u8 reserved_at_c0[0x5];
2345 u8 rdma[0x1];
2346 u8 write[0x1];
2347 u8 requestor[0x1];
2348 u8 qp_number[0x18];
2349 };
2350
2351 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2352 u8 bytes_committed[0x20];
2353
2354 u8 reserved_at_20[0x10];
2355 u8 wqe_index[0x10];
2356
2357 u8 reserved_at_40[0x10];
2358 u8 len[0x10];
2359
2360 u8 reserved_at_60[0x60];
2361
2362 u8 reserved_at_c0[0x5];
2363 u8 rdma[0x1];
2364 u8 write_read[0x1];
2365 u8 requestor[0x1];
2366 u8 qpn[0x18];
2367 };
2368
2369 struct mlx5_ifc_qp_events_bits {
2370 u8 reserved_at_0[0xa0];
2371
2372 u8 type[0x8];
2373 u8 reserved_at_a8[0x18];
2374
2375 u8 reserved_at_c0[0x8];
2376 u8 qpn_rqn_sqn[0x18];
2377 };
2378
2379 struct mlx5_ifc_dct_events_bits {
2380 u8 reserved_at_0[0xc0];
2381
2382 u8 reserved_at_c0[0x8];
2383 u8 dct_number[0x18];
2384 };
2385
2386 struct mlx5_ifc_comp_event_bits {
2387 u8 reserved_at_0[0xc0];
2388
2389 u8 reserved_at_c0[0x8];
2390 u8 cq_number[0x18];
2391 };
2392
2393 enum {
2394 MLX5_QPC_STATE_RST = 0x0,
2395 MLX5_QPC_STATE_INIT = 0x1,
2396 MLX5_QPC_STATE_RTR = 0x2,
2397 MLX5_QPC_STATE_RTS = 0x3,
2398 MLX5_QPC_STATE_SQER = 0x4,
2399 MLX5_QPC_STATE_ERR = 0x6,
2400 MLX5_QPC_STATE_SQD = 0x7,
2401 MLX5_QPC_STATE_SUSPENDED = 0x9,
2402 };
2403
2404 enum {
2405 MLX5_QPC_ST_RC = 0x0,
2406 MLX5_QPC_ST_UC = 0x1,
2407 MLX5_QPC_ST_UD = 0x2,
2408 MLX5_QPC_ST_XRC = 0x3,
2409 MLX5_QPC_ST_DCI = 0x5,
2410 MLX5_QPC_ST_QP0 = 0x7,
2411 MLX5_QPC_ST_QP1 = 0x8,
2412 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2413 MLX5_QPC_ST_REG_UMR = 0xc,
2414 };
2415
2416 enum {
2417 MLX5_QPC_PM_STATE_ARMED = 0x0,
2418 MLX5_QPC_PM_STATE_REARM = 0x1,
2419 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2420 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2421 };
2422
2423 enum {
2424 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2425 };
2426
2427 enum {
2428 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2429 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2430 };
2431
2432 enum {
2433 MLX5_QPC_MTU_256_BYTES = 0x1,
2434 MLX5_QPC_MTU_512_BYTES = 0x2,
2435 MLX5_QPC_MTU_1K_BYTES = 0x3,
2436 MLX5_QPC_MTU_2K_BYTES = 0x4,
2437 MLX5_QPC_MTU_4K_BYTES = 0x5,
2438 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2439 };
2440
2441 enum {
2442 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2443 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2444 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2445 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2446 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2447 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2448 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2449 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2450 };
2451
2452 enum {
2453 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2454 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2455 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2456 };
2457
2458 enum {
2459 MLX5_QPC_CS_RES_DISABLE = 0x0,
2460 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2461 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2462 };
2463
2464 struct mlx5_ifc_qpc_bits {
2465 u8 state[0x4];
2466 u8 lag_tx_port_affinity[0x4];
2467 u8 st[0x8];
2468 u8 reserved_at_10[0x3];
2469 u8 pm_state[0x2];
2470 u8 reserved_at_15[0x1];
2471 u8 req_e2e_credit_mode[0x2];
2472 u8 offload_type[0x4];
2473 u8 end_padding_mode[0x2];
2474 u8 reserved_at_1e[0x2];
2475
2476 u8 wq_signature[0x1];
2477 u8 block_lb_mc[0x1];
2478 u8 atomic_like_write_en[0x1];
2479 u8 latency_sensitive[0x1];
2480 u8 reserved_at_24[0x1];
2481 u8 drain_sigerr[0x1];
2482 u8 reserved_at_26[0x2];
2483 u8 pd[0x18];
2484
2485 u8 mtu[0x3];
2486 u8 log_msg_max[0x5];
2487 u8 reserved_at_48[0x1];
2488 u8 log_rq_size[0x4];
2489 u8 log_rq_stride[0x3];
2490 u8 no_sq[0x1];
2491 u8 log_sq_size[0x4];
2492 u8 reserved_at_55[0x6];
2493 u8 rlky[0x1];
2494 u8 ulp_stateless_offload_mode[0x4];
2495
2496 u8 counter_set_id[0x8];
2497 u8 uar_page[0x18];
2498
2499 u8 reserved_at_80[0x8];
2500 u8 user_index[0x18];
2501
2502 u8 reserved_at_a0[0x3];
2503 u8 log_page_size[0x5];
2504 u8 remote_qpn[0x18];
2505
2506 struct mlx5_ifc_ads_bits primary_address_path;
2507
2508 struct mlx5_ifc_ads_bits secondary_address_path;
2509
2510 u8 log_ack_req_freq[0x4];
2511 u8 reserved_at_384[0x4];
2512 u8 log_sra_max[0x3];
2513 u8 reserved_at_38b[0x2];
2514 u8 retry_count[0x3];
2515 u8 rnr_retry[0x3];
2516 u8 reserved_at_393[0x1];
2517 u8 fre[0x1];
2518 u8 cur_rnr_retry[0x3];
2519 u8 cur_retry_count[0x3];
2520 u8 reserved_at_39b[0x5];
2521
2522 u8 reserved_at_3a0[0x20];
2523
2524 u8 reserved_at_3c0[0x8];
2525 u8 next_send_psn[0x18];
2526
2527 u8 reserved_at_3e0[0x8];
2528 u8 cqn_snd[0x18];
2529
2530 u8 reserved_at_400[0x8];
2531 u8 deth_sqpn[0x18];
2532
2533 u8 reserved_at_420[0x20];
2534
2535 u8 reserved_at_440[0x8];
2536 u8 last_acked_psn[0x18];
2537
2538 u8 reserved_at_460[0x8];
2539 u8 ssn[0x18];
2540
2541 u8 reserved_at_480[0x8];
2542 u8 log_rra_max[0x3];
2543 u8 reserved_at_48b[0x1];
2544 u8 atomic_mode[0x4];
2545 u8 rre[0x1];
2546 u8 rwe[0x1];
2547 u8 rae[0x1];
2548 u8 reserved_at_493[0x1];
2549 u8 page_offset[0x6];
2550 u8 reserved_at_49a[0x3];
2551 u8 cd_slave_receive[0x1];
2552 u8 cd_slave_send[0x1];
2553 u8 cd_master[0x1];
2554
2555 u8 reserved_at_4a0[0x3];
2556 u8 min_rnr_nak[0x5];
2557 u8 next_rcv_psn[0x18];
2558
2559 u8 reserved_at_4c0[0x8];
2560 u8 xrcd[0x18];
2561
2562 u8 reserved_at_4e0[0x8];
2563 u8 cqn_rcv[0x18];
2564
2565 u8 dbr_addr[0x40];
2566
2567 u8 q_key[0x20];
2568
2569 u8 reserved_at_560[0x5];
2570 u8 rq_type[0x3];
2571 u8 srqn_rmpn_xrqn[0x18];
2572
2573 u8 reserved_at_580[0x8];
2574 u8 rmsn[0x18];
2575
2576 u8 hw_sq_wqebb_counter[0x10];
2577 u8 sw_sq_wqebb_counter[0x10];
2578
2579 u8 hw_rq_counter[0x20];
2580
2581 u8 sw_rq_counter[0x20];
2582
2583 u8 reserved_at_600[0x20];
2584
2585 u8 reserved_at_620[0xf];
2586 u8 cgs[0x1];
2587 u8 cs_req[0x8];
2588 u8 cs_res[0x8];
2589
2590 u8 dc_access_key[0x40];
2591
2592 u8 reserved_at_680[0x3];
2593 u8 dbr_umem_valid[0x1];
2594
2595 u8 reserved_at_684[0xbc];
2596 };
2597
2598 struct mlx5_ifc_roce_addr_layout_bits {
2599 u8 source_l3_address[16][0x8];
2600
2601 u8 reserved_at_80[0x3];
2602 u8 vlan_valid[0x1];
2603 u8 vlan_id[0xc];
2604 u8 source_mac_47_32[0x10];
2605
2606 u8 source_mac_31_0[0x20];
2607
2608 u8 reserved_at_c0[0x14];
2609 u8 roce_l3_type[0x4];
2610 u8 roce_version[0x8];
2611
2612 u8 reserved_at_e0[0x20];
2613 };
2614
2615 union mlx5_ifc_hca_cap_union_bits {
2616 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2617 struct mlx5_ifc_odp_cap_bits odp_cap;
2618 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2619 struct mlx5_ifc_roce_cap_bits roce_cap;
2620 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2621 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2622 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2623 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2624 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2625 struct mlx5_ifc_qos_cap_bits qos_cap;
2626 struct mlx5_ifc_debug_cap_bits debug_cap;
2627 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2628 struct mlx5_ifc_tls_cap_bits tls_cap;
2629 u8 reserved_at_0[0x8000];
2630 };
2631
2632 enum {
2633 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2634 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2635 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2636 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2637 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2638 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2639 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2640 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2641 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2642 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2643 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2644 };
2645
2646 enum {
2647 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
2648 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
2649 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
2650 };
2651
2652 struct mlx5_ifc_vlan_bits {
2653 u8 ethtype[0x10];
2654 u8 prio[0x3];
2655 u8 cfi[0x1];
2656 u8 vid[0xc];
2657 };
2658
2659 struct mlx5_ifc_flow_context_bits {
2660 struct mlx5_ifc_vlan_bits push_vlan;
2661
2662 u8 group_id[0x20];
2663
2664 u8 reserved_at_40[0x8];
2665 u8 flow_tag[0x18];
2666
2667 u8 reserved_at_60[0x10];
2668 u8 action[0x10];
2669
2670 u8 extended_destination[0x1];
2671 u8 reserved_at_81[0x1];
2672 u8 flow_source[0x2];
2673 u8 reserved_at_84[0x4];
2674 u8 destination_list_size[0x18];
2675
2676 u8 reserved_at_a0[0x8];
2677 u8 flow_counter_list_size[0x18];
2678
2679 u8 packet_reformat_id[0x20];
2680
2681 u8 modify_header_id[0x20];
2682
2683 struct mlx5_ifc_vlan_bits push_vlan_2;
2684
2685 u8 reserved_at_120[0xe0];
2686
2687 struct mlx5_ifc_fte_match_param_bits match_value;
2688
2689 u8 reserved_at_1200[0x600];
2690
2691 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2692 };
2693
2694 enum {
2695 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2696 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2697 };
2698
2699 struct mlx5_ifc_xrc_srqc_bits {
2700 u8 state[0x4];
2701 u8 log_xrc_srq_size[0x4];
2702 u8 reserved_at_8[0x18];
2703
2704 u8 wq_signature[0x1];
2705 u8 cont_srq[0x1];
2706 u8 reserved_at_22[0x1];
2707 u8 rlky[0x1];
2708 u8 basic_cyclic_rcv_wqe[0x1];
2709 u8 log_rq_stride[0x3];
2710 u8 xrcd[0x18];
2711
2712 u8 page_offset[0x6];
2713 u8 reserved_at_46[0x1];
2714 u8 dbr_umem_valid[0x1];
2715 u8 cqn[0x18];
2716
2717 u8 reserved_at_60[0x20];
2718
2719 u8 user_index_equal_xrc_srqn[0x1];
2720 u8 reserved_at_81[0x1];
2721 u8 log_page_size[0x6];
2722 u8 user_index[0x18];
2723
2724 u8 reserved_at_a0[0x20];
2725
2726 u8 reserved_at_c0[0x8];
2727 u8 pd[0x18];
2728
2729 u8 lwm[0x10];
2730 u8 wqe_cnt[0x10];
2731
2732 u8 reserved_at_100[0x40];
2733
2734 u8 db_record_addr_h[0x20];
2735
2736 u8 db_record_addr_l[0x1e];
2737 u8 reserved_at_17e[0x2];
2738
2739 u8 reserved_at_180[0x80];
2740 };
2741
2742 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2743 u8 counter_error_queues[0x20];
2744
2745 u8 total_error_queues[0x20];
2746
2747 u8 send_queue_priority_update_flow[0x20];
2748
2749 u8 reserved_at_60[0x20];
2750
2751 u8 nic_receive_steering_discard[0x40];
2752
2753 u8 receive_discard_vport_down[0x40];
2754
2755 u8 transmit_discard_vport_down[0x40];
2756
2757 u8 reserved_at_140[0xec0];
2758 };
2759
2760 struct mlx5_ifc_traffic_counter_bits {
2761 u8 packets[0x40];
2762
2763 u8 octets[0x40];
2764 };
2765
2766 struct mlx5_ifc_tisc_bits {
2767 u8 strict_lag_tx_port_affinity[0x1];
2768 u8 tls_en[0x1];
2769 u8 reserved_at_1[0x2];
2770 u8 lag_tx_port_affinity[0x04];
2771
2772 u8 reserved_at_8[0x4];
2773 u8 prio[0x4];
2774 u8 reserved_at_10[0x10];
2775
2776 u8 reserved_at_20[0x100];
2777
2778 u8 reserved_at_120[0x8];
2779 u8 transport_domain[0x18];
2780
2781 u8 reserved_at_140[0x8];
2782 u8 underlay_qpn[0x18];
2783
2784 u8 reserved_at_160[0x8];
2785 u8 pd[0x18];
2786
2787 u8 reserved_at_180[0x380];
2788 };
2789
2790 enum {
2791 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2792 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2793 };
2794
2795 enum {
2796 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2797 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2798 };
2799
2800 enum {
2801 MLX5_RX_HASH_FN_NONE = 0x0,
2802 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2803 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2804 };
2805
2806 enum {
2807 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2808 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2809 };
2810
2811 struct mlx5_ifc_tirc_bits {
2812 u8 reserved_at_0[0x20];
2813
2814 u8 disp_type[0x4];
2815 u8 reserved_at_24[0x1c];
2816
2817 u8 reserved_at_40[0x40];
2818
2819 u8 reserved_at_80[0x4];
2820 u8 lro_timeout_period_usecs[0x10];
2821 u8 lro_enable_mask[0x4];
2822 u8 lro_max_ip_payload_size[0x8];
2823
2824 u8 reserved_at_a0[0x40];
2825
2826 u8 reserved_at_e0[0x8];
2827 u8 inline_rqn[0x18];
2828
2829 u8 rx_hash_symmetric[0x1];
2830 u8 reserved_at_101[0x1];
2831 u8 tunneled_offload_en[0x1];
2832 u8 reserved_at_103[0x5];
2833 u8 indirect_table[0x18];
2834
2835 u8 rx_hash_fn[0x4];
2836 u8 reserved_at_124[0x2];
2837 u8 self_lb_block[0x2];
2838 u8 transport_domain[0x18];
2839
2840 u8 rx_hash_toeplitz_key[10][0x20];
2841
2842 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2843
2844 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2845
2846 u8 reserved_at_2c0[0x4c0];
2847 };
2848
2849 enum {
2850 MLX5_SRQC_STATE_GOOD = 0x0,
2851 MLX5_SRQC_STATE_ERROR = 0x1,
2852 };
2853
2854 struct mlx5_ifc_srqc_bits {
2855 u8 state[0x4];
2856 u8 log_srq_size[0x4];
2857 u8 reserved_at_8[0x18];
2858
2859 u8 wq_signature[0x1];
2860 u8 cont_srq[0x1];
2861 u8 reserved_at_22[0x1];
2862 u8 rlky[0x1];
2863 u8 reserved_at_24[0x1];
2864 u8 log_rq_stride[0x3];
2865 u8 xrcd[0x18];
2866
2867 u8 page_offset[0x6];
2868 u8 reserved_at_46[0x2];
2869 u8 cqn[0x18];
2870
2871 u8 reserved_at_60[0x20];
2872
2873 u8 reserved_at_80[0x2];
2874 u8 log_page_size[0x6];
2875 u8 reserved_at_88[0x18];
2876
2877 u8 reserved_at_a0[0x20];
2878
2879 u8 reserved_at_c0[0x8];
2880 u8 pd[0x18];
2881
2882 u8 lwm[0x10];
2883 u8 wqe_cnt[0x10];
2884
2885 u8 reserved_at_100[0x40];
2886
2887 u8 dbr_addr[0x40];
2888
2889 u8 reserved_at_180[0x80];
2890 };
2891
2892 enum {
2893 MLX5_SQC_STATE_RST = 0x0,
2894 MLX5_SQC_STATE_RDY = 0x1,
2895 MLX5_SQC_STATE_ERR = 0x3,
2896 };
2897
2898 struct mlx5_ifc_sqc_bits {
2899 u8 rlky[0x1];
2900 u8 cd_master[0x1];
2901 u8 fre[0x1];
2902 u8 flush_in_error_en[0x1];
2903 u8 allow_multi_pkt_send_wqe[0x1];
2904 u8 min_wqe_inline_mode[0x3];
2905 u8 state[0x4];
2906 u8 reg_umr[0x1];
2907 u8 allow_swp[0x1];
2908 u8 hairpin[0x1];
2909 u8 reserved_at_f[0x11];
2910
2911 u8 reserved_at_20[0x8];
2912 u8 user_index[0x18];
2913
2914 u8 reserved_at_40[0x8];
2915 u8 cqn[0x18];
2916
2917 u8 reserved_at_60[0x8];
2918 u8 hairpin_peer_rq[0x18];
2919
2920 u8 reserved_at_80[0x10];
2921 u8 hairpin_peer_vhca[0x10];
2922
2923 u8 reserved_at_a0[0x50];
2924
2925 u8 packet_pacing_rate_limit_index[0x10];
2926 u8 tis_lst_sz[0x10];
2927 u8 reserved_at_110[0x10];
2928
2929 u8 reserved_at_120[0x40];
2930
2931 u8 reserved_at_160[0x8];
2932 u8 tis_num_0[0x18];
2933
2934 struct mlx5_ifc_wq_bits wq;
2935 };
2936
2937 enum {
2938 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2939 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2940 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2941 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2942 };
2943
2944 struct mlx5_ifc_scheduling_context_bits {
2945 u8 element_type[0x8];
2946 u8 reserved_at_8[0x18];
2947
2948 u8 element_attributes[0x20];
2949
2950 u8 parent_element_id[0x20];
2951
2952 u8 reserved_at_60[0x40];
2953
2954 u8 bw_share[0x20];
2955
2956 u8 max_average_bw[0x20];
2957
2958 u8 reserved_at_e0[0x120];
2959 };
2960
2961 struct mlx5_ifc_rqtc_bits {
2962 u8 reserved_at_0[0xa0];
2963
2964 u8 reserved_at_a0[0x10];
2965 u8 rqt_max_size[0x10];
2966
2967 u8 reserved_at_c0[0x10];
2968 u8 rqt_actual_size[0x10];
2969
2970 u8 reserved_at_e0[0x6a0];
2971
2972 struct mlx5_ifc_rq_num_bits rq_num[0];
2973 };
2974
2975 enum {
2976 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2977 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2978 };
2979
2980 enum {
2981 MLX5_RQC_STATE_RST = 0x0,
2982 MLX5_RQC_STATE_RDY = 0x1,
2983 MLX5_RQC_STATE_ERR = 0x3,
2984 };
2985
2986 struct mlx5_ifc_rqc_bits {
2987 u8 rlky[0x1];
2988 u8 delay_drop_en[0x1];
2989 u8 scatter_fcs[0x1];
2990 u8 vsd[0x1];
2991 u8 mem_rq_type[0x4];
2992 u8 state[0x4];
2993 u8 reserved_at_c[0x1];
2994 u8 flush_in_error_en[0x1];
2995 u8 hairpin[0x1];
2996 u8 reserved_at_f[0x11];
2997
2998 u8 reserved_at_20[0x8];
2999 u8 user_index[0x18];
3000
3001 u8 reserved_at_40[0x8];
3002 u8 cqn[0x18];
3003
3004 u8 counter_set_id[0x8];
3005 u8 reserved_at_68[0x18];
3006
3007 u8 reserved_at_80[0x8];
3008 u8 rmpn[0x18];
3009
3010 u8 reserved_at_a0[0x8];
3011 u8 hairpin_peer_sq[0x18];
3012
3013 u8 reserved_at_c0[0x10];
3014 u8 hairpin_peer_vhca[0x10];
3015
3016 u8 reserved_at_e0[0xa0];
3017
3018 struct mlx5_ifc_wq_bits wq;
3019 };
3020
3021 enum {
3022 MLX5_RMPC_STATE_RDY = 0x1,
3023 MLX5_RMPC_STATE_ERR = 0x3,
3024 };
3025
3026 struct mlx5_ifc_rmpc_bits {
3027 u8 reserved_at_0[0x8];
3028 u8 state[0x4];
3029 u8 reserved_at_c[0x14];
3030
3031 u8 basic_cyclic_rcv_wqe[0x1];
3032 u8 reserved_at_21[0x1f];
3033
3034 u8 reserved_at_40[0x140];
3035
3036 struct mlx5_ifc_wq_bits wq;
3037 };
3038
3039 struct mlx5_ifc_nic_vport_context_bits {
3040 u8 reserved_at_0[0x5];
3041 u8 min_wqe_inline_mode[0x3];
3042 u8 reserved_at_8[0x15];
3043 u8 disable_mc_local_lb[0x1];
3044 u8 disable_uc_local_lb[0x1];
3045 u8 roce_en[0x1];
3046
3047 u8 arm_change_event[0x1];
3048 u8 reserved_at_21[0x1a];
3049 u8 event_on_mtu[0x1];
3050 u8 event_on_promisc_change[0x1];
3051 u8 event_on_vlan_change[0x1];
3052 u8 event_on_mc_address_change[0x1];
3053 u8 event_on_uc_address_change[0x1];
3054
3055 u8 reserved_at_40[0xc];
3056
3057 u8 affiliation_criteria[0x4];
3058 u8 affiliated_vhca_id[0x10];
3059
3060 u8 reserved_at_60[0xd0];
3061
3062 u8 mtu[0x10];
3063
3064 u8 system_image_guid[0x40];
3065 u8 port_guid[0x40];
3066 u8 node_guid[0x40];
3067
3068 u8 reserved_at_200[0x140];
3069 u8 qkey_violation_counter[0x10];
3070 u8 reserved_at_350[0x430];
3071
3072 u8 promisc_uc[0x1];
3073 u8 promisc_mc[0x1];
3074 u8 promisc_all[0x1];
3075 u8 reserved_at_783[0x2];
3076 u8 allowed_list_type[0x3];
3077 u8 reserved_at_788[0xc];
3078 u8 allowed_list_size[0xc];
3079
3080 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3081
3082 u8 reserved_at_7e0[0x20];
3083
3084 u8 current_uc_mac_address[0][0x40];
3085 };
3086
3087 enum {
3088 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3089 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3090 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3091 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3092 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3093 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3094 };
3095
3096 struct mlx5_ifc_mkc_bits {
3097 u8 reserved_at_0[0x1];
3098 u8 free[0x1];
3099 u8 reserved_at_2[0x1];
3100 u8 access_mode_4_2[0x3];
3101 u8 reserved_at_6[0x7];
3102 u8 relaxed_ordering_write[0x1];
3103 u8 reserved_at_e[0x1];
3104 u8 small_fence_on_rdma_read_response[0x1];
3105 u8 umr_en[0x1];
3106 u8 a[0x1];
3107 u8 rw[0x1];
3108 u8 rr[0x1];
3109 u8 lw[0x1];
3110 u8 lr[0x1];
3111 u8 access_mode_1_0[0x2];
3112 u8 reserved_at_18[0x8];
3113
3114 u8 qpn[0x18];
3115 u8 mkey_7_0[0x8];
3116
3117 u8 reserved_at_40[0x20];
3118
3119 u8 length64[0x1];
3120 u8 bsf_en[0x1];
3121 u8 sync_umr[0x1];
3122 u8 reserved_at_63[0x2];
3123 u8 expected_sigerr_count[0x1];
3124 u8 reserved_at_66[0x1];
3125 u8 en_rinval[0x1];
3126 u8 pd[0x18];
3127
3128 u8 start_addr[0x40];
3129
3130 u8 len[0x40];
3131
3132 u8 bsf_octword_size[0x20];
3133
3134 u8 reserved_at_120[0x80];
3135
3136 u8 translations_octword_size[0x20];
3137
3138 u8 reserved_at_1c0[0x1b];
3139 u8 log_page_size[0x5];
3140
3141 u8 reserved_at_1e0[0x20];
3142 };
3143
3144 struct mlx5_ifc_pkey_bits {
3145 u8 reserved_at_0[0x10];
3146 u8 pkey[0x10];
3147 };
3148
3149 struct mlx5_ifc_array128_auto_bits {
3150 u8 array128_auto[16][0x8];
3151 };
3152
3153 struct mlx5_ifc_hca_vport_context_bits {
3154 u8 field_select[0x20];
3155
3156 u8 reserved_at_20[0xe0];
3157
3158 u8 sm_virt_aware[0x1];
3159 u8 has_smi[0x1];
3160 u8 has_raw[0x1];
3161 u8 grh_required[0x1];
3162 u8 reserved_at_104[0xc];
3163 u8 port_physical_state[0x4];
3164 u8 vport_state_policy[0x4];
3165 u8 port_state[0x4];
3166 u8 vport_state[0x4];
3167
3168 u8 reserved_at_120[0x20];
3169
3170 u8 system_image_guid[0x40];
3171
3172 u8 port_guid[0x40];
3173
3174 u8 node_guid[0x40];
3175
3176 u8 cap_mask1[0x20];
3177
3178 u8 cap_mask1_field_select[0x20];
3179
3180 u8 cap_mask2[0x20];
3181
3182 u8 cap_mask2_field_select[0x20];
3183
3184 u8 reserved_at_280[0x80];
3185
3186 u8 lid[0x10];
3187 u8 reserved_at_310[0x4];
3188 u8 init_type_reply[0x4];
3189 u8 lmc[0x3];
3190 u8 subnet_timeout[0x5];
3191
3192 u8 sm_lid[0x10];
3193 u8 sm_sl[0x4];
3194 u8 reserved_at_334[0xc];
3195
3196 u8 qkey_violation_counter[0x10];
3197 u8 pkey_violation_counter[0x10];
3198
3199 u8 reserved_at_360[0xca0];
3200 };
3201
3202 struct mlx5_ifc_esw_vport_context_bits {
3203 u8 fdb_to_vport_reg_c[0x1];
3204 u8 reserved_at_1[0x2];
3205 u8 vport_svlan_strip[0x1];
3206 u8 vport_cvlan_strip[0x1];
3207 u8 vport_svlan_insert[0x1];
3208 u8 vport_cvlan_insert[0x2];
3209 u8 fdb_to_vport_reg_c_id[0x8];
3210 u8 reserved_at_10[0x10];
3211
3212 u8 reserved_at_20[0x20];
3213
3214 u8 svlan_cfi[0x1];
3215 u8 svlan_pcp[0x3];
3216 u8 svlan_id[0xc];
3217 u8 cvlan_cfi[0x1];
3218 u8 cvlan_pcp[0x3];
3219 u8 cvlan_id[0xc];
3220
3221 u8 reserved_at_60[0x7a0];
3222 };
3223
3224 enum {
3225 MLX5_EQC_STATUS_OK = 0x0,
3226 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3227 };
3228
3229 enum {
3230 MLX5_EQC_ST_ARMED = 0x9,
3231 MLX5_EQC_ST_FIRED = 0xa,
3232 };
3233
3234 struct mlx5_ifc_eqc_bits {
3235 u8 status[0x4];
3236 u8 reserved_at_4[0x9];
3237 u8 ec[0x1];
3238 u8 oi[0x1];
3239 u8 reserved_at_f[0x5];
3240 u8 st[0x4];
3241 u8 reserved_at_18[0x8];
3242
3243 u8 reserved_at_20[0x20];
3244
3245 u8 reserved_at_40[0x14];
3246 u8 page_offset[0x6];
3247 u8 reserved_at_5a[0x6];
3248
3249 u8 reserved_at_60[0x3];
3250 u8 log_eq_size[0x5];
3251 u8 uar_page[0x18];
3252
3253 u8 reserved_at_80[0x20];
3254
3255 u8 reserved_at_a0[0x18];
3256 u8 intr[0x8];
3257
3258 u8 reserved_at_c0[0x3];
3259 u8 log_page_size[0x5];
3260 u8 reserved_at_c8[0x18];
3261
3262 u8 reserved_at_e0[0x60];
3263
3264 u8 reserved_at_140[0x8];
3265 u8 consumer_counter[0x18];
3266
3267 u8 reserved_at_160[0x8];
3268 u8 producer_counter[0x18];
3269
3270 u8 reserved_at_180[0x80];
3271 };
3272
3273 enum {
3274 MLX5_DCTC_STATE_ACTIVE = 0x0,
3275 MLX5_DCTC_STATE_DRAINING = 0x1,
3276 MLX5_DCTC_STATE_DRAINED = 0x2,
3277 };
3278
3279 enum {
3280 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3281 MLX5_DCTC_CS_RES_NA = 0x1,
3282 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3283 };
3284
3285 enum {
3286 MLX5_DCTC_MTU_256_BYTES = 0x1,
3287 MLX5_DCTC_MTU_512_BYTES = 0x2,
3288 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3289 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3290 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3291 };
3292
3293 struct mlx5_ifc_dctc_bits {
3294 u8 reserved_at_0[0x4];
3295 u8 state[0x4];
3296 u8 reserved_at_8[0x18];
3297
3298 u8 reserved_at_20[0x8];
3299 u8 user_index[0x18];
3300
3301 u8 reserved_at_40[0x8];
3302 u8 cqn[0x18];
3303
3304 u8 counter_set_id[0x8];
3305 u8 atomic_mode[0x4];
3306 u8 rre[0x1];
3307 u8 rwe[0x1];
3308 u8 rae[0x1];
3309 u8 atomic_like_write_en[0x1];
3310 u8 latency_sensitive[0x1];
3311 u8 rlky[0x1];
3312 u8 free_ar[0x1];
3313 u8 reserved_at_73[0xd];
3314
3315 u8 reserved_at_80[0x8];
3316 u8 cs_res[0x8];
3317 u8 reserved_at_90[0x3];
3318 u8 min_rnr_nak[0x5];
3319 u8 reserved_at_98[0x8];
3320
3321 u8 reserved_at_a0[0x8];
3322 u8 srqn_xrqn[0x18];
3323
3324 u8 reserved_at_c0[0x8];
3325 u8 pd[0x18];
3326
3327 u8 tclass[0x8];
3328 u8 reserved_at_e8[0x4];
3329 u8 flow_label[0x14];
3330
3331 u8 dc_access_key[0x40];
3332
3333 u8 reserved_at_140[0x5];
3334 u8 mtu[0x3];
3335 u8 port[0x8];
3336 u8 pkey_index[0x10];
3337
3338 u8 reserved_at_160[0x8];
3339 u8 my_addr_index[0x8];
3340 u8 reserved_at_170[0x8];
3341 u8 hop_limit[0x8];
3342
3343 u8 dc_access_key_violation_count[0x20];
3344
3345 u8 reserved_at_1a0[0x14];
3346 u8 dei_cfi[0x1];
3347 u8 eth_prio[0x3];
3348 u8 ecn[0x2];
3349 u8 dscp[0x6];
3350
3351 u8 reserved_at_1c0[0x40];
3352 };
3353
3354 enum {
3355 MLX5_CQC_STATUS_OK = 0x0,
3356 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3357 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3358 };
3359
3360 enum {
3361 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3362 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3363 };
3364
3365 enum {
3366 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3367 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3368 MLX5_CQC_ST_FIRED = 0xa,
3369 };
3370
3371 enum {
3372 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3373 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3374 MLX5_CQ_PERIOD_NUM_MODES
3375 };
3376
3377 struct mlx5_ifc_cqc_bits {
3378 u8 status[0x4];
3379 u8 reserved_at_4[0x2];
3380 u8 dbr_umem_valid[0x1];
3381 u8 reserved_at_7[0x1];
3382 u8 cqe_sz[0x3];
3383 u8 cc[0x1];
3384 u8 reserved_at_c[0x1];
3385 u8 scqe_break_moderation_en[0x1];
3386 u8 oi[0x1];
3387 u8 cq_period_mode[0x2];
3388 u8 cqe_comp_en[0x1];
3389 u8 mini_cqe_res_format[0x2];
3390 u8 st[0x4];
3391 u8 reserved_at_18[0x8];
3392
3393 u8 reserved_at_20[0x20];
3394
3395 u8 reserved_at_40[0x14];
3396 u8 page_offset[0x6];
3397 u8 reserved_at_5a[0x6];
3398
3399 u8 reserved_at_60[0x3];
3400 u8 log_cq_size[0x5];
3401 u8 uar_page[0x18];
3402
3403 u8 reserved_at_80[0x4];
3404 u8 cq_period[0xc];
3405 u8 cq_max_count[0x10];
3406
3407 u8 reserved_at_a0[0x18];
3408 u8 c_eqn[0x8];
3409
3410 u8 reserved_at_c0[0x3];
3411 u8 log_page_size[0x5];
3412 u8 reserved_at_c8[0x18];
3413
3414 u8 reserved_at_e0[0x20];
3415
3416 u8 reserved_at_100[0x8];
3417 u8 last_notified_index[0x18];
3418
3419 u8 reserved_at_120[0x8];
3420 u8 last_solicit_index[0x18];
3421
3422 u8 reserved_at_140[0x8];
3423 u8 consumer_counter[0x18];
3424
3425 u8 reserved_at_160[0x8];
3426 u8 producer_counter[0x18];
3427
3428 u8 reserved_at_180[0x40];
3429
3430 u8 dbr_addr[0x40];
3431 };
3432
3433 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3434 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3435 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3436 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3437 u8 reserved_at_0[0x800];
3438 };
3439
3440 struct mlx5_ifc_query_adapter_param_block_bits {
3441 u8 reserved_at_0[0xc0];
3442
3443 u8 reserved_at_c0[0x8];
3444 u8 ieee_vendor_id[0x18];
3445
3446 u8 reserved_at_e0[0x10];
3447 u8 vsd_vendor_id[0x10];
3448
3449 u8 vsd[208][0x8];
3450
3451 u8 vsd_contd_psid[16][0x8];
3452 };
3453
3454 enum {
3455 MLX5_XRQC_STATE_GOOD = 0x0,
3456 MLX5_XRQC_STATE_ERROR = 0x1,
3457 };
3458
3459 enum {
3460 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3461 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3462 };
3463
3464 enum {
3465 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3466 };
3467
3468 struct mlx5_ifc_tag_matching_topology_context_bits {
3469 u8 log_matching_list_sz[0x4];
3470 u8 reserved_at_4[0xc];
3471 u8 append_next_index[0x10];
3472
3473 u8 sw_phase_cnt[0x10];
3474 u8 hw_phase_cnt[0x10];
3475
3476 u8 reserved_at_40[0x40];
3477 };
3478
3479 struct mlx5_ifc_xrqc_bits {
3480 u8 state[0x4];
3481 u8 rlkey[0x1];
3482 u8 reserved_at_5[0xf];
3483 u8 topology[0x4];
3484 u8 reserved_at_18[0x4];
3485 u8 offload[0x4];
3486
3487 u8 reserved_at_20[0x8];
3488 u8 user_index[0x18];
3489
3490 u8 reserved_at_40[0x8];
3491 u8 cqn[0x18];
3492
3493 u8 reserved_at_60[0xa0];
3494
3495 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3496
3497 u8 reserved_at_180[0x280];
3498
3499 struct mlx5_ifc_wq_bits wq;
3500 };
3501
3502 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3503 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3504 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3505 u8 reserved_at_0[0x20];
3506 };
3507
3508 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3509 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3510 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3511 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3512 u8 reserved_at_0[0x20];
3513 };
3514
3515 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3516 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3517 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3518 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3519 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3520 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3521 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3522 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3523 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3524 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3525 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3526 u8 reserved_at_0[0x7c0];
3527 };
3528
3529 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3530 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3531 u8 reserved_at_0[0x7c0];
3532 };
3533
3534 union mlx5_ifc_event_auto_bits {
3535 struct mlx5_ifc_comp_event_bits comp_event;
3536 struct mlx5_ifc_dct_events_bits dct_events;
3537 struct mlx5_ifc_qp_events_bits qp_events;
3538 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3539 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3540 struct mlx5_ifc_cq_error_bits cq_error;
3541 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3542 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3543 struct mlx5_ifc_gpio_event_bits gpio_event;
3544 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3545 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3546 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3547 u8 reserved_at_0[0xe0];
3548 };
3549
3550 struct mlx5_ifc_health_buffer_bits {
3551 u8 reserved_at_0[0x100];
3552
3553 u8 assert_existptr[0x20];
3554
3555 u8 assert_callra[0x20];
3556
3557 u8 reserved_at_140[0x40];
3558
3559 u8 fw_version[0x20];
3560
3561 u8 hw_id[0x20];
3562
3563 u8 reserved_at_1c0[0x20];
3564
3565 u8 irisc_index[0x8];
3566 u8 synd[0x8];
3567 u8 ext_synd[0x10];
3568 };
3569
3570 struct mlx5_ifc_register_loopback_control_bits {
3571 u8 no_lb[0x1];
3572 u8 reserved_at_1[0x7];
3573 u8 port[0x8];
3574 u8 reserved_at_10[0x10];
3575
3576 u8 reserved_at_20[0x60];
3577 };
3578
3579 struct mlx5_ifc_vport_tc_element_bits {
3580 u8 traffic_class[0x4];
3581 u8 reserved_at_4[0xc];
3582 u8 vport_number[0x10];
3583 };
3584
3585 struct mlx5_ifc_vport_element_bits {
3586 u8 reserved_at_0[0x10];
3587 u8 vport_number[0x10];
3588 };
3589
3590 enum {
3591 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3592 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3593 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3594 };
3595
3596 struct mlx5_ifc_tsar_element_bits {
3597 u8 reserved_at_0[0x8];
3598 u8 tsar_type[0x8];
3599 u8 reserved_at_10[0x10];
3600 };
3601
3602 enum {
3603 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3604 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3605 };
3606
3607 struct mlx5_ifc_teardown_hca_out_bits {
3608 u8 status[0x8];
3609 u8 reserved_at_8[0x18];
3610
3611 u8 syndrome[0x20];
3612
3613 u8 reserved_at_40[0x3f];
3614
3615 u8 state[0x1];
3616 };
3617
3618 enum {
3619 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3620 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3621 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3622 };
3623
3624 struct mlx5_ifc_teardown_hca_in_bits {
3625 u8 opcode[0x10];
3626 u8 reserved_at_10[0x10];
3627
3628 u8 reserved_at_20[0x10];
3629 u8 op_mod[0x10];
3630
3631 u8 reserved_at_40[0x10];
3632 u8 profile[0x10];
3633
3634 u8 reserved_at_60[0x20];
3635 };
3636
3637 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3638 u8 status[0x8];
3639 u8 reserved_at_8[0x18];
3640
3641 u8 syndrome[0x20];
3642
3643 u8 reserved_at_40[0x40];
3644 };
3645
3646 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3647 u8 opcode[0x10];
3648 u8 uid[0x10];
3649
3650 u8 reserved_at_20[0x10];
3651 u8 op_mod[0x10];
3652
3653 u8 reserved_at_40[0x8];
3654 u8 qpn[0x18];
3655
3656 u8 reserved_at_60[0x20];
3657
3658 u8 opt_param_mask[0x20];
3659
3660 u8 reserved_at_a0[0x20];
3661
3662 struct mlx5_ifc_qpc_bits qpc;
3663
3664 u8 reserved_at_800[0x80];
3665 };
3666
3667 struct mlx5_ifc_sqd2rts_qp_out_bits {
3668 u8 status[0x8];
3669 u8 reserved_at_8[0x18];
3670
3671 u8 syndrome[0x20];
3672
3673 u8 reserved_at_40[0x40];
3674 };
3675
3676 struct mlx5_ifc_sqd2rts_qp_in_bits {
3677 u8 opcode[0x10];
3678 u8 uid[0x10];
3679
3680 u8 reserved_at_20[0x10];
3681 u8 op_mod[0x10];
3682
3683 u8 reserved_at_40[0x8];
3684 u8 qpn[0x18];
3685
3686 u8 reserved_at_60[0x20];
3687
3688 u8 opt_param_mask[0x20];
3689
3690 u8 reserved_at_a0[0x20];
3691
3692 struct mlx5_ifc_qpc_bits qpc;
3693
3694 u8 reserved_at_800[0x80];
3695 };
3696
3697 struct mlx5_ifc_set_roce_address_out_bits {
3698 u8 status[0x8];
3699 u8 reserved_at_8[0x18];
3700
3701 u8 syndrome[0x20];
3702
3703 u8 reserved_at_40[0x40];
3704 };
3705
3706 struct mlx5_ifc_set_roce_address_in_bits {
3707 u8 opcode[0x10];
3708 u8 reserved_at_10[0x10];
3709
3710 u8 reserved_at_20[0x10];
3711 u8 op_mod[0x10];
3712
3713 u8 roce_address_index[0x10];
3714 u8 reserved_at_50[0xc];
3715 u8 vhca_port_num[0x4];
3716
3717 u8 reserved_at_60[0x20];
3718
3719 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3720 };
3721
3722 struct mlx5_ifc_set_mad_demux_out_bits {
3723 u8 status[0x8];
3724 u8 reserved_at_8[0x18];
3725
3726 u8 syndrome[0x20];
3727
3728 u8 reserved_at_40[0x40];
3729 };
3730
3731 enum {
3732 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3733 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3734 };
3735
3736 struct mlx5_ifc_set_mad_demux_in_bits {
3737 u8 opcode[0x10];
3738 u8 reserved_at_10[0x10];
3739
3740 u8 reserved_at_20[0x10];
3741 u8 op_mod[0x10];
3742
3743 u8 reserved_at_40[0x20];
3744
3745 u8 reserved_at_60[0x6];
3746 u8 demux_mode[0x2];
3747 u8 reserved_at_68[0x18];
3748 };
3749
3750 struct mlx5_ifc_set_l2_table_entry_out_bits {
3751 u8 status[0x8];
3752 u8 reserved_at_8[0x18];
3753
3754 u8 syndrome[0x20];
3755
3756 u8 reserved_at_40[0x40];
3757 };
3758
3759 struct mlx5_ifc_set_l2_table_entry_in_bits {
3760 u8 opcode[0x10];
3761 u8 reserved_at_10[0x10];
3762
3763 u8 reserved_at_20[0x10];
3764 u8 op_mod[0x10];
3765
3766 u8 reserved_at_40[0x60];
3767
3768 u8 reserved_at_a0[0x8];
3769 u8 table_index[0x18];
3770
3771 u8 reserved_at_c0[0x20];
3772
3773 u8 reserved_at_e0[0x13];
3774 u8 vlan_valid[0x1];
3775 u8 vlan[0xc];
3776
3777 struct mlx5_ifc_mac_address_layout_bits mac_address;
3778
3779 u8 reserved_at_140[0xc0];
3780 };
3781
3782 struct mlx5_ifc_set_issi_out_bits {
3783 u8 status[0x8];
3784 u8 reserved_at_8[0x18];
3785
3786 u8 syndrome[0x20];
3787
3788 u8 reserved_at_40[0x40];
3789 };
3790
3791 struct mlx5_ifc_set_issi_in_bits {
3792 u8 opcode[0x10];
3793 u8 reserved_at_10[0x10];
3794
3795 u8 reserved_at_20[0x10];
3796 u8 op_mod[0x10];
3797
3798 u8 reserved_at_40[0x10];
3799 u8 current_issi[0x10];
3800
3801 u8 reserved_at_60[0x20];
3802 };
3803
3804 struct mlx5_ifc_set_hca_cap_out_bits {
3805 u8 status[0x8];
3806 u8 reserved_at_8[0x18];
3807
3808 u8 syndrome[0x20];
3809
3810 u8 reserved_at_40[0x40];
3811 };
3812
3813 struct mlx5_ifc_set_hca_cap_in_bits {
3814 u8 opcode[0x10];
3815 u8 reserved_at_10[0x10];
3816
3817 u8 reserved_at_20[0x10];
3818 u8 op_mod[0x10];
3819
3820 u8 reserved_at_40[0x40];
3821
3822 union mlx5_ifc_hca_cap_union_bits capability;
3823 };
3824
3825 enum {
3826 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3827 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3828 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3829 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3830 };
3831
3832 struct mlx5_ifc_set_fte_out_bits {
3833 u8 status[0x8];
3834 u8 reserved_at_8[0x18];
3835
3836 u8 syndrome[0x20];
3837
3838 u8 reserved_at_40[0x40];
3839 };
3840
3841 struct mlx5_ifc_set_fte_in_bits {
3842 u8 opcode[0x10];
3843 u8 reserved_at_10[0x10];
3844
3845 u8 reserved_at_20[0x10];
3846 u8 op_mod[0x10];
3847
3848 u8 other_vport[0x1];
3849 u8 reserved_at_41[0xf];
3850 u8 vport_number[0x10];
3851
3852 u8 reserved_at_60[0x20];
3853
3854 u8 table_type[0x8];
3855 u8 reserved_at_88[0x18];
3856
3857 u8 reserved_at_a0[0x8];
3858 u8 table_id[0x18];
3859
3860 u8 reserved_at_c0[0x18];
3861 u8 modify_enable_mask[0x8];
3862
3863 u8 reserved_at_e0[0x20];
3864
3865 u8 flow_index[0x20];
3866
3867 u8 reserved_at_120[0xe0];
3868
3869 struct mlx5_ifc_flow_context_bits flow_context;
3870 };
3871
3872 struct mlx5_ifc_rts2rts_qp_out_bits {
3873 u8 status[0x8];
3874 u8 reserved_at_8[0x18];
3875
3876 u8 syndrome[0x20];
3877
3878 u8 reserved_at_40[0x40];
3879 };
3880
3881 struct mlx5_ifc_rts2rts_qp_in_bits {
3882 u8 opcode[0x10];
3883 u8 uid[0x10];
3884
3885 u8 reserved_at_20[0x10];
3886 u8 op_mod[0x10];
3887
3888 u8 reserved_at_40[0x8];
3889 u8 qpn[0x18];
3890
3891 u8 reserved_at_60[0x20];
3892
3893 u8 opt_param_mask[0x20];
3894
3895 u8 reserved_at_a0[0x20];
3896
3897 struct mlx5_ifc_qpc_bits qpc;
3898
3899 u8 reserved_at_800[0x80];
3900 };
3901
3902 struct mlx5_ifc_rtr2rts_qp_out_bits {
3903 u8 status[0x8];
3904 u8 reserved_at_8[0x18];
3905
3906 u8 syndrome[0x20];
3907
3908 u8 reserved_at_40[0x40];
3909 };
3910
3911 struct mlx5_ifc_rtr2rts_qp_in_bits {
3912 u8 opcode[0x10];
3913 u8 uid[0x10];
3914
3915 u8 reserved_at_20[0x10];
3916 u8 op_mod[0x10];
3917
3918 u8 reserved_at_40[0x8];
3919 u8 qpn[0x18];
3920
3921 u8 reserved_at_60[0x20];
3922
3923 u8 opt_param_mask[0x20];
3924
3925 u8 reserved_at_a0[0x20];
3926
3927 struct mlx5_ifc_qpc_bits qpc;
3928
3929 u8 reserved_at_800[0x80];
3930 };
3931
3932 struct mlx5_ifc_rst2init_qp_out_bits {
3933 u8 status[0x8];
3934 u8 reserved_at_8[0x18];
3935
3936 u8 syndrome[0x20];
3937
3938 u8 reserved_at_40[0x40];
3939 };
3940
3941 struct mlx5_ifc_rst2init_qp_in_bits {
3942 u8 opcode[0x10];
3943 u8 uid[0x10];
3944
3945 u8 reserved_at_20[0x10];
3946 u8 op_mod[0x10];
3947
3948 u8 reserved_at_40[0x8];
3949 u8 qpn[0x18];
3950
3951 u8 reserved_at_60[0x20];
3952
3953 u8 opt_param_mask[0x20];
3954
3955 u8 reserved_at_a0[0x20];
3956
3957 struct mlx5_ifc_qpc_bits qpc;
3958
3959 u8 reserved_at_800[0x80];
3960 };
3961
3962 struct mlx5_ifc_query_xrq_out_bits {
3963 u8 status[0x8];
3964 u8 reserved_at_8[0x18];
3965
3966 u8 syndrome[0x20];
3967
3968 u8 reserved_at_40[0x40];
3969
3970 struct mlx5_ifc_xrqc_bits xrq_context;
3971 };
3972
3973 struct mlx5_ifc_query_xrq_in_bits {
3974 u8 opcode[0x10];
3975 u8 reserved_at_10[0x10];
3976
3977 u8 reserved_at_20[0x10];
3978 u8 op_mod[0x10];
3979
3980 u8 reserved_at_40[0x8];
3981 u8 xrqn[0x18];
3982
3983 u8 reserved_at_60[0x20];
3984 };
3985
3986 struct mlx5_ifc_query_xrc_srq_out_bits {
3987 u8 status[0x8];
3988 u8 reserved_at_8[0x18];
3989
3990 u8 syndrome[0x20];
3991
3992 u8 reserved_at_40[0x40];
3993
3994 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3995
3996 u8 reserved_at_280[0x600];
3997
3998 u8 pas[0][0x40];
3999 };
4000
4001 struct mlx5_ifc_query_xrc_srq_in_bits {
4002 u8 opcode[0x10];
4003 u8 reserved_at_10[0x10];
4004
4005 u8 reserved_at_20[0x10];
4006 u8 op_mod[0x10];
4007
4008 u8 reserved_at_40[0x8];
4009 u8 xrc_srqn[0x18];
4010
4011 u8 reserved_at_60[0x20];
4012 };
4013
4014 enum {
4015 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4016 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4017 };
4018
4019 struct mlx5_ifc_query_vport_state_out_bits {
4020 u8 status[0x8];
4021 u8 reserved_at_8[0x18];
4022
4023 u8 syndrome[0x20];
4024
4025 u8 reserved_at_40[0x20];
4026
4027 u8 reserved_at_60[0x18];
4028 u8 admin_state[0x4];
4029 u8 state[0x4];
4030 };
4031
4032 enum {
4033 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4034 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4035 };
4036
4037 struct mlx5_ifc_arm_monitor_counter_in_bits {
4038 u8 opcode[0x10];
4039 u8 uid[0x10];
4040
4041 u8 reserved_at_20[0x10];
4042 u8 op_mod[0x10];
4043
4044 u8 reserved_at_40[0x20];
4045
4046 u8 reserved_at_60[0x20];
4047 };
4048
4049 struct mlx5_ifc_arm_monitor_counter_out_bits {
4050 u8 status[0x8];
4051 u8 reserved_at_8[0x18];
4052
4053 u8 syndrome[0x20];
4054
4055 u8 reserved_at_40[0x40];
4056 };
4057
4058 enum {
4059 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4060 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4061 };
4062
4063 enum mlx5_monitor_counter_ppcnt {
4064 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4065 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4066 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4067 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4068 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4069 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4070 };
4071
4072 enum {
4073 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4074 };
4075
4076 struct mlx5_ifc_monitor_counter_output_bits {
4077 u8 reserved_at_0[0x4];
4078 u8 type[0x4];
4079 u8 reserved_at_8[0x8];
4080 u8 counter[0x10];
4081
4082 u8 counter_group_id[0x20];
4083 };
4084
4085 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4086 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4087 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4088 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4089
4090 struct mlx5_ifc_set_monitor_counter_in_bits {
4091 u8 opcode[0x10];
4092 u8 uid[0x10];
4093
4094 u8 reserved_at_20[0x10];
4095 u8 op_mod[0x10];
4096
4097 u8 reserved_at_40[0x10];
4098 u8 num_of_counters[0x10];
4099
4100 u8 reserved_at_60[0x20];
4101
4102 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4103 };
4104
4105 struct mlx5_ifc_set_monitor_counter_out_bits {
4106 u8 status[0x8];
4107 u8 reserved_at_8[0x18];
4108
4109 u8 syndrome[0x20];
4110
4111 u8 reserved_at_40[0x40];
4112 };
4113
4114 struct mlx5_ifc_query_vport_state_in_bits {
4115 u8 opcode[0x10];
4116 u8 reserved_at_10[0x10];
4117
4118 u8 reserved_at_20[0x10];
4119 u8 op_mod[0x10];
4120
4121 u8 other_vport[0x1];
4122 u8 reserved_at_41[0xf];
4123 u8 vport_number[0x10];
4124
4125 u8 reserved_at_60[0x20];
4126 };
4127
4128 struct mlx5_ifc_query_vnic_env_out_bits {
4129 u8 status[0x8];
4130 u8 reserved_at_8[0x18];
4131
4132 u8 syndrome[0x20];
4133
4134 u8 reserved_at_40[0x40];
4135
4136 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4137 };
4138
4139 enum {
4140 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4141 };
4142
4143 struct mlx5_ifc_query_vnic_env_in_bits {
4144 u8 opcode[0x10];
4145 u8 reserved_at_10[0x10];
4146
4147 u8 reserved_at_20[0x10];
4148 u8 op_mod[0x10];
4149
4150 u8 other_vport[0x1];
4151 u8 reserved_at_41[0xf];
4152 u8 vport_number[0x10];
4153
4154 u8 reserved_at_60[0x20];
4155 };
4156
4157 struct mlx5_ifc_query_vport_counter_out_bits {
4158 u8 status[0x8];
4159 u8 reserved_at_8[0x18];
4160
4161 u8 syndrome[0x20];
4162
4163 u8 reserved_at_40[0x40];
4164
4165 struct mlx5_ifc_traffic_counter_bits received_errors;
4166
4167 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4168
4169 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4170
4171 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4172
4173 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4174
4175 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4176
4177 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4178
4179 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4180
4181 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4182
4183 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4184
4185 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4186
4187 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4188
4189 u8 reserved_at_680[0xa00];
4190 };
4191
4192 enum {
4193 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4194 };
4195
4196 struct mlx5_ifc_query_vport_counter_in_bits {
4197 u8 opcode[0x10];
4198 u8 reserved_at_10[0x10];
4199
4200 u8 reserved_at_20[0x10];
4201 u8 op_mod[0x10];
4202
4203 u8 other_vport[0x1];
4204 u8 reserved_at_41[0xb];
4205 u8 port_num[0x4];
4206 u8 vport_number[0x10];
4207
4208 u8 reserved_at_60[0x60];
4209
4210 u8 clear[0x1];
4211 u8 reserved_at_c1[0x1f];
4212
4213 u8 reserved_at_e0[0x20];
4214 };
4215
4216 struct mlx5_ifc_query_tis_out_bits {
4217 u8 status[0x8];
4218 u8 reserved_at_8[0x18];
4219
4220 u8 syndrome[0x20];
4221
4222 u8 reserved_at_40[0x40];
4223
4224 struct mlx5_ifc_tisc_bits tis_context;
4225 };
4226
4227 struct mlx5_ifc_query_tis_in_bits {
4228 u8 opcode[0x10];
4229 u8 reserved_at_10[0x10];
4230
4231 u8 reserved_at_20[0x10];
4232 u8 op_mod[0x10];
4233
4234 u8 reserved_at_40[0x8];
4235 u8 tisn[0x18];
4236
4237 u8 reserved_at_60[0x20];
4238 };
4239
4240 struct mlx5_ifc_query_tir_out_bits {
4241 u8 status[0x8];
4242 u8 reserved_at_8[0x18];
4243
4244 u8 syndrome[0x20];
4245
4246 u8 reserved_at_40[0xc0];
4247
4248 struct mlx5_ifc_tirc_bits tir_context;
4249 };
4250
4251 struct mlx5_ifc_query_tir_in_bits {
4252 u8 opcode[0x10];
4253 u8 reserved_at_10[0x10];
4254
4255 u8 reserved_at_20[0x10];
4256 u8 op_mod[0x10];
4257
4258 u8 reserved_at_40[0x8];
4259 u8 tirn[0x18];
4260
4261 u8 reserved_at_60[0x20];
4262 };
4263
4264 struct mlx5_ifc_query_srq_out_bits {
4265 u8 status[0x8];
4266 u8 reserved_at_8[0x18];
4267
4268 u8 syndrome[0x20];
4269
4270 u8 reserved_at_40[0x40];
4271
4272 struct mlx5_ifc_srqc_bits srq_context_entry;
4273
4274 u8 reserved_at_280[0x600];
4275
4276 u8 pas[0][0x40];
4277 };
4278
4279 struct mlx5_ifc_query_srq_in_bits {
4280 u8 opcode[0x10];
4281 u8 reserved_at_10[0x10];
4282
4283 u8 reserved_at_20[0x10];
4284 u8 op_mod[0x10];
4285
4286 u8 reserved_at_40[0x8];
4287 u8 srqn[0x18];
4288
4289 u8 reserved_at_60[0x20];
4290 };
4291
4292 struct mlx5_ifc_query_sq_out_bits {
4293 u8 status[0x8];
4294 u8 reserved_at_8[0x18];
4295
4296 u8 syndrome[0x20];
4297
4298 u8 reserved_at_40[0xc0];
4299
4300 struct mlx5_ifc_sqc_bits sq_context;
4301 };
4302
4303 struct mlx5_ifc_query_sq_in_bits {
4304 u8 opcode[0x10];
4305 u8 reserved_at_10[0x10];
4306
4307 u8 reserved_at_20[0x10];
4308 u8 op_mod[0x10];
4309
4310 u8 reserved_at_40[0x8];
4311 u8 sqn[0x18];
4312
4313 u8 reserved_at_60[0x20];
4314 };
4315
4316 struct mlx5_ifc_query_special_contexts_out_bits {
4317 u8 status[0x8];
4318 u8 reserved_at_8[0x18];
4319
4320 u8 syndrome[0x20];
4321
4322 u8 dump_fill_mkey[0x20];
4323
4324 u8 resd_lkey[0x20];
4325
4326 u8 null_mkey[0x20];
4327
4328 u8 reserved_at_a0[0x60];
4329 };
4330
4331 struct mlx5_ifc_query_special_contexts_in_bits {
4332 u8 opcode[0x10];
4333 u8 reserved_at_10[0x10];
4334
4335 u8 reserved_at_20[0x10];
4336 u8 op_mod[0x10];
4337
4338 u8 reserved_at_40[0x40];
4339 };
4340
4341 struct mlx5_ifc_query_scheduling_element_out_bits {
4342 u8 opcode[0x10];
4343 u8 reserved_at_10[0x10];
4344
4345 u8 reserved_at_20[0x10];
4346 u8 op_mod[0x10];
4347
4348 u8 reserved_at_40[0xc0];
4349
4350 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4351
4352 u8 reserved_at_300[0x100];
4353 };
4354
4355 enum {
4356 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4357 };
4358
4359 struct mlx5_ifc_query_scheduling_element_in_bits {
4360 u8 opcode[0x10];
4361 u8 reserved_at_10[0x10];
4362
4363 u8 reserved_at_20[0x10];
4364 u8 op_mod[0x10];
4365
4366 u8 scheduling_hierarchy[0x8];
4367 u8 reserved_at_48[0x18];
4368
4369 u8 scheduling_element_id[0x20];
4370
4371 u8 reserved_at_80[0x180];
4372 };
4373
4374 struct mlx5_ifc_query_rqt_out_bits {
4375 u8 status[0x8];
4376 u8 reserved_at_8[0x18];
4377
4378 u8 syndrome[0x20];
4379
4380 u8 reserved_at_40[0xc0];
4381
4382 struct mlx5_ifc_rqtc_bits rqt_context;
4383 };
4384
4385 struct mlx5_ifc_query_rqt_in_bits {
4386 u8 opcode[0x10];
4387 u8 reserved_at_10[0x10];
4388
4389 u8 reserved_at_20[0x10];
4390 u8 op_mod[0x10];
4391
4392 u8 reserved_at_40[0x8];
4393 u8 rqtn[0x18];
4394
4395 u8 reserved_at_60[0x20];
4396 };
4397
4398 struct mlx5_ifc_query_rq_out_bits {
4399 u8 status[0x8];
4400 u8 reserved_at_8[0x18];
4401
4402 u8 syndrome[0x20];
4403
4404 u8 reserved_at_40[0xc0];
4405
4406 struct mlx5_ifc_rqc_bits rq_context;
4407 };
4408
4409 struct mlx5_ifc_query_rq_in_bits {
4410 u8 opcode[0x10];
4411 u8 reserved_at_10[0x10];
4412
4413 u8 reserved_at_20[0x10];
4414 u8 op_mod[0x10];
4415
4416 u8 reserved_at_40[0x8];
4417 u8 rqn[0x18];
4418
4419 u8 reserved_at_60[0x20];
4420 };
4421
4422 struct mlx5_ifc_query_roce_address_out_bits {
4423 u8 status[0x8];
4424 u8 reserved_at_8[0x18];
4425
4426 u8 syndrome[0x20];
4427
4428 u8 reserved_at_40[0x40];
4429
4430 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4431 };
4432
4433 struct mlx5_ifc_query_roce_address_in_bits {
4434 u8 opcode[0x10];
4435 u8 reserved_at_10[0x10];
4436
4437 u8 reserved_at_20[0x10];
4438 u8 op_mod[0x10];
4439
4440 u8 roce_address_index[0x10];
4441 u8 reserved_at_50[0xc];
4442 u8 vhca_port_num[0x4];
4443
4444 u8 reserved_at_60[0x20];
4445 };
4446
4447 struct mlx5_ifc_query_rmp_out_bits {
4448 u8 status[0x8];
4449 u8 reserved_at_8[0x18];
4450
4451 u8 syndrome[0x20];
4452
4453 u8 reserved_at_40[0xc0];
4454
4455 struct mlx5_ifc_rmpc_bits rmp_context;
4456 };
4457
4458 struct mlx5_ifc_query_rmp_in_bits {
4459 u8 opcode[0x10];
4460 u8 reserved_at_10[0x10];
4461
4462 u8 reserved_at_20[0x10];
4463 u8 op_mod[0x10];
4464
4465 u8 reserved_at_40[0x8];
4466 u8 rmpn[0x18];
4467
4468 u8 reserved_at_60[0x20];
4469 };
4470
4471 struct mlx5_ifc_query_qp_out_bits {
4472 u8 status[0x8];
4473 u8 reserved_at_8[0x18];
4474
4475 u8 syndrome[0x20];
4476
4477 u8 reserved_at_40[0x40];
4478
4479 u8 opt_param_mask[0x20];
4480
4481 u8 reserved_at_a0[0x20];
4482
4483 struct mlx5_ifc_qpc_bits qpc;
4484
4485 u8 reserved_at_800[0x80];
4486
4487 u8 pas[0][0x40];
4488 };
4489
4490 struct mlx5_ifc_query_qp_in_bits {
4491 u8 opcode[0x10];
4492 u8 reserved_at_10[0x10];
4493
4494 u8 reserved_at_20[0x10];
4495 u8 op_mod[0x10];
4496
4497 u8 reserved_at_40[0x8];
4498 u8 qpn[0x18];
4499
4500 u8 reserved_at_60[0x20];
4501 };
4502
4503 struct mlx5_ifc_query_q_counter_out_bits {
4504 u8 status[0x8];
4505 u8 reserved_at_8[0x18];
4506
4507 u8 syndrome[0x20];
4508
4509 u8 reserved_at_40[0x40];
4510
4511 u8 rx_write_requests[0x20];
4512
4513 u8 reserved_at_a0[0x20];
4514
4515 u8 rx_read_requests[0x20];
4516
4517 u8 reserved_at_e0[0x20];
4518
4519 u8 rx_atomic_requests[0x20];
4520
4521 u8 reserved_at_120[0x20];
4522
4523 u8 rx_dct_connect[0x20];
4524
4525 u8 reserved_at_160[0x20];
4526
4527 u8 out_of_buffer[0x20];
4528
4529 u8 reserved_at_1a0[0x20];
4530
4531 u8 out_of_sequence[0x20];
4532
4533 u8 reserved_at_1e0[0x20];
4534
4535 u8 duplicate_request[0x20];
4536
4537 u8 reserved_at_220[0x20];
4538
4539 u8 rnr_nak_retry_err[0x20];
4540
4541 u8 reserved_at_260[0x20];
4542
4543 u8 packet_seq_err[0x20];
4544
4545 u8 reserved_at_2a0[0x20];
4546
4547 u8 implied_nak_seq_err[0x20];
4548
4549 u8 reserved_at_2e0[0x20];
4550
4551 u8 local_ack_timeout_err[0x20];
4552
4553 u8 reserved_at_320[0xa0];
4554
4555 u8 resp_local_length_error[0x20];
4556
4557 u8 req_local_length_error[0x20];
4558
4559 u8 resp_local_qp_error[0x20];
4560
4561 u8 local_operation_error[0x20];
4562
4563 u8 resp_local_protection[0x20];
4564
4565 u8 req_local_protection[0x20];
4566
4567 u8 resp_cqe_error[0x20];
4568
4569 u8 req_cqe_error[0x20];
4570
4571 u8 req_mw_binding[0x20];
4572
4573 u8 req_bad_response[0x20];
4574
4575 u8 req_remote_invalid_request[0x20];
4576
4577 u8 resp_remote_invalid_request[0x20];
4578
4579 u8 req_remote_access_errors[0x20];
4580
4581 u8 resp_remote_access_errors[0x20];
4582
4583 u8 req_remote_operation_errors[0x20];
4584
4585 u8 req_transport_retries_exceeded[0x20];
4586
4587 u8 cq_overflow[0x20];
4588
4589 u8 resp_cqe_flush_error[0x20];
4590
4591 u8 req_cqe_flush_error[0x20];
4592
4593 u8 reserved_at_620[0x1e0];
4594 };
4595
4596 struct mlx5_ifc_query_q_counter_in_bits {
4597 u8 opcode[0x10];
4598 u8 reserved_at_10[0x10];
4599
4600 u8 reserved_at_20[0x10];
4601 u8 op_mod[0x10];
4602
4603 u8 reserved_at_40[0x80];
4604
4605 u8 clear[0x1];
4606 u8 reserved_at_c1[0x1f];
4607
4608 u8 reserved_at_e0[0x18];
4609 u8 counter_set_id[0x8];
4610 };
4611
4612 struct mlx5_ifc_query_pages_out_bits {
4613 u8 status[0x8];
4614 u8 reserved_at_8[0x18];
4615
4616 u8 syndrome[0x20];
4617
4618 u8 embedded_cpu_function[0x1];
4619 u8 reserved_at_41[0xf];
4620 u8 function_id[0x10];
4621
4622 u8 num_pages[0x20];
4623 };
4624
4625 enum {
4626 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4627 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4628 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4629 };
4630
4631 struct mlx5_ifc_query_pages_in_bits {
4632 u8 opcode[0x10];
4633 u8 reserved_at_10[0x10];
4634
4635 u8 reserved_at_20[0x10];
4636 u8 op_mod[0x10];
4637
4638 u8 embedded_cpu_function[0x1];
4639 u8 reserved_at_41[0xf];
4640 u8 function_id[0x10];
4641
4642 u8 reserved_at_60[0x20];
4643 };
4644
4645 struct mlx5_ifc_query_nic_vport_context_out_bits {
4646 u8 status[0x8];
4647 u8 reserved_at_8[0x18];
4648
4649 u8 syndrome[0x20];
4650
4651 u8 reserved_at_40[0x40];
4652
4653 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4654 };
4655
4656 struct mlx5_ifc_query_nic_vport_context_in_bits {
4657 u8 opcode[0x10];
4658 u8 reserved_at_10[0x10];
4659
4660 u8 reserved_at_20[0x10];
4661 u8 op_mod[0x10];
4662
4663 u8 other_vport[0x1];
4664 u8 reserved_at_41[0xf];
4665 u8 vport_number[0x10];
4666
4667 u8 reserved_at_60[0x5];
4668 u8 allowed_list_type[0x3];
4669 u8 reserved_at_68[0x18];
4670 };
4671
4672 struct mlx5_ifc_query_mkey_out_bits {
4673 u8 status[0x8];
4674 u8 reserved_at_8[0x18];
4675
4676 u8 syndrome[0x20];
4677
4678 u8 reserved_at_40[0x40];
4679
4680 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4681
4682 u8 reserved_at_280[0x600];
4683
4684 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4685
4686 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4687 };
4688
4689 struct mlx5_ifc_query_mkey_in_bits {
4690 u8 opcode[0x10];
4691 u8 reserved_at_10[0x10];
4692
4693 u8 reserved_at_20[0x10];
4694 u8 op_mod[0x10];
4695
4696 u8 reserved_at_40[0x8];
4697 u8 mkey_index[0x18];
4698
4699 u8 pg_access[0x1];
4700 u8 reserved_at_61[0x1f];
4701 };
4702
4703 struct mlx5_ifc_query_mad_demux_out_bits {
4704 u8 status[0x8];
4705 u8 reserved_at_8[0x18];
4706
4707 u8 syndrome[0x20];
4708
4709 u8 reserved_at_40[0x40];
4710
4711 u8 mad_dumux_parameters_block[0x20];
4712 };
4713
4714 struct mlx5_ifc_query_mad_demux_in_bits {
4715 u8 opcode[0x10];
4716 u8 reserved_at_10[0x10];
4717
4718 u8 reserved_at_20[0x10];
4719 u8 op_mod[0x10];
4720
4721 u8 reserved_at_40[0x40];
4722 };
4723
4724 struct mlx5_ifc_query_l2_table_entry_out_bits {
4725 u8 status[0x8];
4726 u8 reserved_at_8[0x18];
4727
4728 u8 syndrome[0x20];
4729
4730 u8 reserved_at_40[0xa0];
4731
4732 u8 reserved_at_e0[0x13];
4733 u8 vlan_valid[0x1];
4734 u8 vlan[0xc];
4735
4736 struct mlx5_ifc_mac_address_layout_bits mac_address;
4737
4738 u8 reserved_at_140[0xc0];
4739 };
4740
4741 struct mlx5_ifc_query_l2_table_entry_in_bits {
4742 u8 opcode[0x10];
4743 u8 reserved_at_10[0x10];
4744
4745 u8 reserved_at_20[0x10];
4746 u8 op_mod[0x10];
4747
4748 u8 reserved_at_40[0x60];
4749
4750 u8 reserved_at_a0[0x8];
4751 u8 table_index[0x18];
4752
4753 u8 reserved_at_c0[0x140];
4754 };
4755
4756 struct mlx5_ifc_query_issi_out_bits {
4757 u8 status[0x8];
4758 u8 reserved_at_8[0x18];
4759
4760 u8 syndrome[0x20];
4761
4762 u8 reserved_at_40[0x10];
4763 u8 current_issi[0x10];
4764
4765 u8 reserved_at_60[0xa0];
4766
4767 u8 reserved_at_100[76][0x8];
4768 u8 supported_issi_dw0[0x20];
4769 };
4770
4771 struct mlx5_ifc_query_issi_in_bits {
4772 u8 opcode[0x10];
4773 u8 reserved_at_10[0x10];
4774
4775 u8 reserved_at_20[0x10];
4776 u8 op_mod[0x10];
4777
4778 u8 reserved_at_40[0x40];
4779 };
4780
4781 struct mlx5_ifc_set_driver_version_out_bits {
4782 u8 status[0x8];
4783 u8 reserved_0[0x18];
4784
4785 u8 syndrome[0x20];
4786 u8 reserved_1[0x40];
4787 };
4788
4789 struct mlx5_ifc_set_driver_version_in_bits {
4790 u8 opcode[0x10];
4791 u8 reserved_0[0x10];
4792
4793 u8 reserved_1[0x10];
4794 u8 op_mod[0x10];
4795
4796 u8 reserved_2[0x40];
4797 u8 driver_version[64][0x8];
4798 };
4799
4800 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4801 u8 status[0x8];
4802 u8 reserved_at_8[0x18];
4803
4804 u8 syndrome[0x20];
4805
4806 u8 reserved_at_40[0x40];
4807
4808 struct mlx5_ifc_pkey_bits pkey[0];
4809 };
4810
4811 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4812 u8 opcode[0x10];
4813 u8 reserved_at_10[0x10];
4814
4815 u8 reserved_at_20[0x10];
4816 u8 op_mod[0x10];
4817
4818 u8 other_vport[0x1];
4819 u8 reserved_at_41[0xb];
4820 u8 port_num[0x4];
4821 u8 vport_number[0x10];
4822
4823 u8 reserved_at_60[0x10];
4824 u8 pkey_index[0x10];
4825 };
4826
4827 enum {
4828 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4829 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4830 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4831 };
4832
4833 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4834 u8 status[0x8];
4835 u8 reserved_at_8[0x18];
4836
4837 u8 syndrome[0x20];
4838
4839 u8 reserved_at_40[0x20];
4840
4841 u8 gids_num[0x10];
4842 u8 reserved_at_70[0x10];
4843
4844 struct mlx5_ifc_array128_auto_bits gid[0];
4845 };
4846
4847 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4848 u8 opcode[0x10];
4849 u8 reserved_at_10[0x10];
4850
4851 u8 reserved_at_20[0x10];
4852 u8 op_mod[0x10];
4853
4854 u8 other_vport[0x1];
4855 u8 reserved_at_41[0xb];
4856 u8 port_num[0x4];
4857 u8 vport_number[0x10];
4858
4859 u8 reserved_at_60[0x10];
4860 u8 gid_index[0x10];
4861 };
4862
4863 struct mlx5_ifc_query_hca_vport_context_out_bits {
4864 u8 status[0x8];
4865 u8 reserved_at_8[0x18];
4866
4867 u8 syndrome[0x20];
4868
4869 u8 reserved_at_40[0x40];
4870
4871 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4872 };
4873
4874 struct mlx5_ifc_query_hca_vport_context_in_bits {
4875 u8 opcode[0x10];
4876 u8 reserved_at_10[0x10];
4877
4878 u8 reserved_at_20[0x10];
4879 u8 op_mod[0x10];
4880
4881 u8 other_vport[0x1];
4882 u8 reserved_at_41[0xb];
4883 u8 port_num[0x4];
4884 u8 vport_number[0x10];
4885
4886 u8 reserved_at_60[0x20];
4887 };
4888
4889 struct mlx5_ifc_query_hca_cap_out_bits {
4890 u8 status[0x8];
4891 u8 reserved_at_8[0x18];
4892
4893 u8 syndrome[0x20];
4894
4895 u8 reserved_at_40[0x40];
4896
4897 union mlx5_ifc_hca_cap_union_bits capability;
4898 };
4899
4900 struct mlx5_ifc_query_hca_cap_in_bits {
4901 u8 opcode[0x10];
4902 u8 reserved_at_10[0x10];
4903
4904 u8 reserved_at_20[0x10];
4905 u8 op_mod[0x10];
4906
4907 u8 reserved_at_40[0x40];
4908 };
4909
4910 struct mlx5_ifc_query_flow_table_out_bits {
4911 u8 status[0x8];
4912 u8 reserved_at_8[0x18];
4913
4914 u8 syndrome[0x20];
4915
4916 u8 reserved_at_40[0x80];
4917
4918 u8 reserved_at_c0[0x8];
4919 u8 level[0x8];
4920 u8 reserved_at_d0[0x8];
4921 u8 log_size[0x8];
4922
4923 u8 reserved_at_e0[0x120];
4924 };
4925
4926 struct mlx5_ifc_query_flow_table_in_bits {
4927 u8 opcode[0x10];
4928 u8 reserved_at_10[0x10];
4929
4930 u8 reserved_at_20[0x10];
4931 u8 op_mod[0x10];
4932
4933 u8 reserved_at_40[0x40];
4934
4935 u8 table_type[0x8];
4936 u8 reserved_at_88[0x18];
4937
4938 u8 reserved_at_a0[0x8];
4939 u8 table_id[0x18];
4940
4941 u8 reserved_at_c0[0x140];
4942 };
4943
4944 struct mlx5_ifc_query_fte_out_bits {
4945 u8 status[0x8];
4946 u8 reserved_at_8[0x18];
4947
4948 u8 syndrome[0x20];
4949
4950 u8 reserved_at_40[0x1c0];
4951
4952 struct mlx5_ifc_flow_context_bits flow_context;
4953 };
4954
4955 struct mlx5_ifc_query_fte_in_bits {
4956 u8 opcode[0x10];
4957 u8 reserved_at_10[0x10];
4958
4959 u8 reserved_at_20[0x10];
4960 u8 op_mod[0x10];
4961
4962 u8 reserved_at_40[0x40];
4963
4964 u8 table_type[0x8];
4965 u8 reserved_at_88[0x18];
4966
4967 u8 reserved_at_a0[0x8];
4968 u8 table_id[0x18];
4969
4970 u8 reserved_at_c0[0x40];
4971
4972 u8 flow_index[0x20];
4973
4974 u8 reserved_at_120[0xe0];
4975 };
4976
4977 enum {
4978 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4979 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4980 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4981 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
4982 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
4983 };
4984
4985 struct mlx5_ifc_query_flow_group_out_bits {
4986 u8 status[0x8];
4987 u8 reserved_at_8[0x18];
4988
4989 u8 syndrome[0x20];
4990
4991 u8 reserved_at_40[0xa0];
4992
4993 u8 start_flow_index[0x20];
4994
4995 u8 reserved_at_100[0x20];
4996
4997 u8 end_flow_index[0x20];
4998
4999 u8 reserved_at_140[0xa0];
5000
5001 u8 reserved_at_1e0[0x18];
5002 u8 match_criteria_enable[0x8];
5003
5004 struct mlx5_ifc_fte_match_param_bits match_criteria;
5005
5006 u8 reserved_at_1200[0xe00];
5007 };
5008
5009 struct mlx5_ifc_query_flow_group_in_bits {
5010 u8 opcode[0x10];
5011 u8 reserved_at_10[0x10];
5012
5013 u8 reserved_at_20[0x10];
5014 u8 op_mod[0x10];
5015
5016 u8 reserved_at_40[0x40];
5017
5018 u8 table_type[0x8];
5019 u8 reserved_at_88[0x18];
5020
5021 u8 reserved_at_a0[0x8];
5022 u8 table_id[0x18];
5023
5024 u8 group_id[0x20];
5025
5026 u8 reserved_at_e0[0x120];
5027 };
5028
5029 struct mlx5_ifc_query_flow_counter_out_bits {
5030 u8 status[0x8];
5031 u8 reserved_at_8[0x18];
5032
5033 u8 syndrome[0x20];
5034
5035 u8 reserved_at_40[0x40];
5036
5037 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5038 };
5039
5040 struct mlx5_ifc_query_flow_counter_in_bits {
5041 u8 opcode[0x10];
5042 u8 reserved_at_10[0x10];
5043
5044 u8 reserved_at_20[0x10];
5045 u8 op_mod[0x10];
5046
5047 u8 reserved_at_40[0x80];
5048
5049 u8 clear[0x1];
5050 u8 reserved_at_c1[0xf];
5051 u8 num_of_counters[0x10];
5052
5053 u8 flow_counter_id[0x20];
5054 };
5055
5056 struct mlx5_ifc_query_esw_vport_context_out_bits {
5057 u8 status[0x8];
5058 u8 reserved_at_8[0x18];
5059
5060 u8 syndrome[0x20];
5061
5062 u8 reserved_at_40[0x40];
5063
5064 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5065 };
5066
5067 struct mlx5_ifc_query_esw_vport_context_in_bits {
5068 u8 opcode[0x10];
5069 u8 reserved_at_10[0x10];
5070
5071 u8 reserved_at_20[0x10];
5072 u8 op_mod[0x10];
5073
5074 u8 other_vport[0x1];
5075 u8 reserved_at_41[0xf];
5076 u8 vport_number[0x10];
5077
5078 u8 reserved_at_60[0x20];
5079 };
5080
5081 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5082 u8 status[0x8];
5083 u8 reserved_at_8[0x18];
5084
5085 u8 syndrome[0x20];
5086
5087 u8 reserved_at_40[0x40];
5088 };
5089
5090 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5091 u8 reserved_at_0[0x1b];
5092 u8 fdb_to_vport_reg_c_id[0x1];
5093 u8 vport_cvlan_insert[0x1];
5094 u8 vport_svlan_insert[0x1];
5095 u8 vport_cvlan_strip[0x1];
5096 u8 vport_svlan_strip[0x1];
5097 };
5098
5099 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5100 u8 opcode[0x10];
5101 u8 reserved_at_10[0x10];
5102
5103 u8 reserved_at_20[0x10];
5104 u8 op_mod[0x10];
5105
5106 u8 other_vport[0x1];
5107 u8 reserved_at_41[0xf];
5108 u8 vport_number[0x10];
5109
5110 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5111
5112 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5113 };
5114
5115 struct mlx5_ifc_query_eq_out_bits {
5116 u8 status[0x8];
5117 u8 reserved_at_8[0x18];
5118
5119 u8 syndrome[0x20];
5120
5121 u8 reserved_at_40[0x40];
5122
5123 struct mlx5_ifc_eqc_bits eq_context_entry;
5124
5125 u8 reserved_at_280[0x40];
5126
5127 u8 event_bitmask[0x40];
5128
5129 u8 reserved_at_300[0x580];
5130
5131 u8 pas[0][0x40];
5132 };
5133
5134 struct mlx5_ifc_query_eq_in_bits {
5135 u8 opcode[0x10];
5136 u8 reserved_at_10[0x10];
5137
5138 u8 reserved_at_20[0x10];
5139 u8 op_mod[0x10];
5140
5141 u8 reserved_at_40[0x18];
5142 u8 eq_number[0x8];
5143
5144 u8 reserved_at_60[0x20];
5145 };
5146
5147 struct mlx5_ifc_packet_reformat_context_in_bits {
5148 u8 reserved_at_0[0x5];
5149 u8 reformat_type[0x3];
5150 u8 reserved_at_8[0xe];
5151 u8 reformat_data_size[0xa];
5152
5153 u8 reserved_at_20[0x10];
5154 u8 reformat_data[2][0x8];
5155
5156 u8 more_reformat_data[0][0x8];
5157 };
5158
5159 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5160 u8 status[0x8];
5161 u8 reserved_at_8[0x18];
5162
5163 u8 syndrome[0x20];
5164
5165 u8 reserved_at_40[0xa0];
5166
5167 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5168 };
5169
5170 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5171 u8 opcode[0x10];
5172 u8 reserved_at_10[0x10];
5173
5174 u8 reserved_at_20[0x10];
5175 u8 op_mod[0x10];
5176
5177 u8 packet_reformat_id[0x20];
5178
5179 u8 reserved_at_60[0xa0];
5180 };
5181
5182 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5183 u8 status[0x8];
5184 u8 reserved_at_8[0x18];
5185
5186 u8 syndrome[0x20];
5187
5188 u8 packet_reformat_id[0x20];
5189
5190 u8 reserved_at_60[0x20];
5191 };
5192
5193 enum {
5194 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5195 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5196 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5197 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5198 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5199 };
5200
5201 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5202 u8 opcode[0x10];
5203 u8 reserved_at_10[0x10];
5204
5205 u8 reserved_at_20[0x10];
5206 u8 op_mod[0x10];
5207
5208 u8 reserved_at_40[0xa0];
5209
5210 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5211 };
5212
5213 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5214 u8 status[0x8];
5215 u8 reserved_at_8[0x18];
5216
5217 u8 syndrome[0x20];
5218
5219 u8 reserved_at_40[0x40];
5220 };
5221
5222 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5223 u8 opcode[0x10];
5224 u8 reserved_at_10[0x10];
5225
5226 u8 reserved_20[0x10];
5227 u8 op_mod[0x10];
5228
5229 u8 packet_reformat_id[0x20];
5230
5231 u8 reserved_60[0x20];
5232 };
5233
5234 struct mlx5_ifc_set_action_in_bits {
5235 u8 action_type[0x4];
5236 u8 field[0xc];
5237 u8 reserved_at_10[0x3];
5238 u8 offset[0x5];
5239 u8 reserved_at_18[0x3];
5240 u8 length[0x5];
5241
5242 u8 data[0x20];
5243 };
5244
5245 struct mlx5_ifc_add_action_in_bits {
5246 u8 action_type[0x4];
5247 u8 field[0xc];
5248 u8 reserved_at_10[0x10];
5249
5250 u8 data[0x20];
5251 };
5252
5253 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5254 struct mlx5_ifc_set_action_in_bits set_action_in;
5255 struct mlx5_ifc_add_action_in_bits add_action_in;
5256 u8 reserved_at_0[0x40];
5257 };
5258
5259 enum {
5260 MLX5_ACTION_TYPE_SET = 0x1,
5261 MLX5_ACTION_TYPE_ADD = 0x2,
5262 };
5263
5264 enum {
5265 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5266 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5267 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5268 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5269 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5270 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5271 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5272 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5273 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5274 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5275 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5276 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5277 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5278 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5279 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5280 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5281 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5282 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5283 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5284 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5285 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5286 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5287 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5288 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5289 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5290 };
5291
5292 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5293 u8 status[0x8];
5294 u8 reserved_at_8[0x18];
5295
5296 u8 syndrome[0x20];
5297
5298 u8 modify_header_id[0x20];
5299
5300 u8 reserved_at_60[0x20];
5301 };
5302
5303 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5304 u8 opcode[0x10];
5305 u8 reserved_at_10[0x10];
5306
5307 u8 reserved_at_20[0x10];
5308 u8 op_mod[0x10];
5309
5310 u8 reserved_at_40[0x20];
5311
5312 u8 table_type[0x8];
5313 u8 reserved_at_68[0x10];
5314 u8 num_of_actions[0x8];
5315
5316 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5317 };
5318
5319 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5320 u8 status[0x8];
5321 u8 reserved_at_8[0x18];
5322
5323 u8 syndrome[0x20];
5324
5325 u8 reserved_at_40[0x40];
5326 };
5327
5328 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5329 u8 opcode[0x10];
5330 u8 reserved_at_10[0x10];
5331
5332 u8 reserved_at_20[0x10];
5333 u8 op_mod[0x10];
5334
5335 u8 modify_header_id[0x20];
5336
5337 u8 reserved_at_60[0x20];
5338 };
5339
5340 struct mlx5_ifc_query_dct_out_bits {
5341 u8 status[0x8];
5342 u8 reserved_at_8[0x18];
5343
5344 u8 syndrome[0x20];
5345
5346 u8 reserved_at_40[0x40];
5347
5348 struct mlx5_ifc_dctc_bits dct_context_entry;
5349
5350 u8 reserved_at_280[0x180];
5351 };
5352
5353 struct mlx5_ifc_query_dct_in_bits {
5354 u8 opcode[0x10];
5355 u8 reserved_at_10[0x10];
5356
5357 u8 reserved_at_20[0x10];
5358 u8 op_mod[0x10];
5359
5360 u8 reserved_at_40[0x8];
5361 u8 dctn[0x18];
5362
5363 u8 reserved_at_60[0x20];
5364 };
5365
5366 struct mlx5_ifc_query_cq_out_bits {
5367 u8 status[0x8];
5368 u8 reserved_at_8[0x18];
5369
5370 u8 syndrome[0x20];
5371
5372 u8 reserved_at_40[0x40];
5373
5374 struct mlx5_ifc_cqc_bits cq_context;
5375
5376 u8 reserved_at_280[0x600];
5377
5378 u8 pas[0][0x40];
5379 };
5380
5381 struct mlx5_ifc_query_cq_in_bits {
5382 u8 opcode[0x10];
5383 u8 reserved_at_10[0x10];
5384
5385 u8 reserved_at_20[0x10];
5386 u8 op_mod[0x10];
5387
5388 u8 reserved_at_40[0x8];
5389 u8 cqn[0x18];
5390
5391 u8 reserved_at_60[0x20];
5392 };
5393
5394 struct mlx5_ifc_query_cong_status_out_bits {
5395 u8 status[0x8];
5396 u8 reserved_at_8[0x18];
5397
5398 u8 syndrome[0x20];
5399
5400 u8 reserved_at_40[0x20];
5401
5402 u8 enable[0x1];
5403 u8 tag_enable[0x1];
5404 u8 reserved_at_62[0x1e];
5405 };
5406
5407 struct mlx5_ifc_query_cong_status_in_bits {
5408 u8 opcode[0x10];
5409 u8 reserved_at_10[0x10];
5410
5411 u8 reserved_at_20[0x10];
5412 u8 op_mod[0x10];
5413
5414 u8 reserved_at_40[0x18];
5415 u8 priority[0x4];
5416 u8 cong_protocol[0x4];
5417
5418 u8 reserved_at_60[0x20];
5419 };
5420
5421 struct mlx5_ifc_query_cong_statistics_out_bits {
5422 u8 status[0x8];
5423 u8 reserved_at_8[0x18];
5424
5425 u8 syndrome[0x20];
5426
5427 u8 reserved_at_40[0x40];
5428
5429 u8 rp_cur_flows[0x20];
5430
5431 u8 sum_flows[0x20];
5432
5433 u8 rp_cnp_ignored_high[0x20];
5434
5435 u8 rp_cnp_ignored_low[0x20];
5436
5437 u8 rp_cnp_handled_high[0x20];
5438
5439 u8 rp_cnp_handled_low[0x20];
5440
5441 u8 reserved_at_140[0x100];
5442
5443 u8 time_stamp_high[0x20];
5444
5445 u8 time_stamp_low[0x20];
5446
5447 u8 accumulators_period[0x20];
5448
5449 u8 np_ecn_marked_roce_packets_high[0x20];
5450
5451 u8 np_ecn_marked_roce_packets_low[0x20];
5452
5453 u8 np_cnp_sent_high[0x20];
5454
5455 u8 np_cnp_sent_low[0x20];
5456
5457 u8 reserved_at_320[0x560];
5458 };
5459
5460 struct mlx5_ifc_query_cong_statistics_in_bits {
5461 u8 opcode[0x10];
5462 u8 reserved_at_10[0x10];
5463
5464 u8 reserved_at_20[0x10];
5465 u8 op_mod[0x10];
5466
5467 u8 clear[0x1];
5468 u8 reserved_at_41[0x1f];
5469
5470 u8 reserved_at_60[0x20];
5471 };
5472
5473 struct mlx5_ifc_query_cong_params_out_bits {
5474 u8 status[0x8];
5475 u8 reserved_at_8[0x18];
5476
5477 u8 syndrome[0x20];
5478
5479 u8 reserved_at_40[0x40];
5480
5481 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5482 };
5483
5484 struct mlx5_ifc_query_cong_params_in_bits {
5485 u8 opcode[0x10];
5486 u8 reserved_at_10[0x10];
5487
5488 u8 reserved_at_20[0x10];
5489 u8 op_mod[0x10];
5490
5491 u8 reserved_at_40[0x1c];
5492 u8 cong_protocol[0x4];
5493
5494 u8 reserved_at_60[0x20];
5495 };
5496
5497 struct mlx5_ifc_query_adapter_out_bits {
5498 u8 status[0x8];
5499 u8 reserved_at_8[0x18];
5500
5501 u8 syndrome[0x20];
5502
5503 u8 reserved_at_40[0x40];
5504
5505 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5506 };
5507
5508 struct mlx5_ifc_query_adapter_in_bits {
5509 u8 opcode[0x10];
5510 u8 reserved_at_10[0x10];
5511
5512 u8 reserved_at_20[0x10];
5513 u8 op_mod[0x10];
5514
5515 u8 reserved_at_40[0x40];
5516 };
5517
5518 struct mlx5_ifc_qp_2rst_out_bits {
5519 u8 status[0x8];
5520 u8 reserved_at_8[0x18];
5521
5522 u8 syndrome[0x20];
5523
5524 u8 reserved_at_40[0x40];
5525 };
5526
5527 struct mlx5_ifc_qp_2rst_in_bits {
5528 u8 opcode[0x10];
5529 u8 uid[0x10];
5530
5531 u8 reserved_at_20[0x10];
5532 u8 op_mod[0x10];
5533
5534 u8 reserved_at_40[0x8];
5535 u8 qpn[0x18];
5536
5537 u8 reserved_at_60[0x20];
5538 };
5539
5540 struct mlx5_ifc_qp_2err_out_bits {
5541 u8 status[0x8];
5542 u8 reserved_at_8[0x18];
5543
5544 u8 syndrome[0x20];
5545
5546 u8 reserved_at_40[0x40];
5547 };
5548
5549 struct mlx5_ifc_qp_2err_in_bits {
5550 u8 opcode[0x10];
5551 u8 uid[0x10];
5552
5553 u8 reserved_at_20[0x10];
5554 u8 op_mod[0x10];
5555
5556 u8 reserved_at_40[0x8];
5557 u8 qpn[0x18];
5558
5559 u8 reserved_at_60[0x20];
5560 };
5561
5562 struct mlx5_ifc_page_fault_resume_out_bits {
5563 u8 status[0x8];
5564 u8 reserved_at_8[0x18];
5565
5566 u8 syndrome[0x20];
5567
5568 u8 reserved_at_40[0x40];
5569 };
5570
5571 struct mlx5_ifc_page_fault_resume_in_bits {
5572 u8 opcode[0x10];
5573 u8 reserved_at_10[0x10];
5574
5575 u8 reserved_at_20[0x10];
5576 u8 op_mod[0x10];
5577
5578 u8 error[0x1];
5579 u8 reserved_at_41[0x4];
5580 u8 page_fault_type[0x3];
5581 u8 wq_number[0x18];
5582
5583 u8 reserved_at_60[0x8];
5584 u8 token[0x18];
5585 };
5586
5587 struct mlx5_ifc_nop_out_bits {
5588 u8 status[0x8];
5589 u8 reserved_at_8[0x18];
5590
5591 u8 syndrome[0x20];
5592
5593 u8 reserved_at_40[0x40];
5594 };
5595
5596 struct mlx5_ifc_nop_in_bits {
5597 u8 opcode[0x10];
5598 u8 reserved_at_10[0x10];
5599
5600 u8 reserved_at_20[0x10];
5601 u8 op_mod[0x10];
5602
5603 u8 reserved_at_40[0x40];
5604 };
5605
5606 struct mlx5_ifc_modify_vport_state_out_bits {
5607 u8 status[0x8];
5608 u8 reserved_at_8[0x18];
5609
5610 u8 syndrome[0x20];
5611
5612 u8 reserved_at_40[0x40];
5613 };
5614
5615 struct mlx5_ifc_modify_vport_state_in_bits {
5616 u8 opcode[0x10];
5617 u8 reserved_at_10[0x10];
5618
5619 u8 reserved_at_20[0x10];
5620 u8 op_mod[0x10];
5621
5622 u8 other_vport[0x1];
5623 u8 reserved_at_41[0xf];
5624 u8 vport_number[0x10];
5625
5626 u8 reserved_at_60[0x18];
5627 u8 admin_state[0x4];
5628 u8 reserved_at_7c[0x4];
5629 };
5630
5631 struct mlx5_ifc_modify_tis_out_bits {
5632 u8 status[0x8];
5633 u8 reserved_at_8[0x18];
5634
5635 u8 syndrome[0x20];
5636
5637 u8 reserved_at_40[0x40];
5638 };
5639
5640 struct mlx5_ifc_modify_tis_bitmask_bits {
5641 u8 reserved_at_0[0x20];
5642
5643 u8 reserved_at_20[0x1d];
5644 u8 lag_tx_port_affinity[0x1];
5645 u8 strict_lag_tx_port_affinity[0x1];
5646 u8 prio[0x1];
5647 };
5648
5649 struct mlx5_ifc_modify_tis_in_bits {
5650 u8 opcode[0x10];
5651 u8 uid[0x10];
5652
5653 u8 reserved_at_20[0x10];
5654 u8 op_mod[0x10];
5655
5656 u8 reserved_at_40[0x8];
5657 u8 tisn[0x18];
5658
5659 u8 reserved_at_60[0x20];
5660
5661 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5662
5663 u8 reserved_at_c0[0x40];
5664
5665 struct mlx5_ifc_tisc_bits ctx;
5666 };
5667
5668 struct mlx5_ifc_modify_tir_bitmask_bits {
5669 u8 reserved_at_0[0x20];
5670
5671 u8 reserved_at_20[0x1b];
5672 u8 self_lb_en[0x1];
5673 u8 reserved_at_3c[0x1];
5674 u8 hash[0x1];
5675 u8 reserved_at_3e[0x1];
5676 u8 lro[0x1];
5677 };
5678
5679 struct mlx5_ifc_modify_tir_out_bits {
5680 u8 status[0x8];
5681 u8 reserved_at_8[0x18];
5682
5683 u8 syndrome[0x20];
5684
5685 u8 reserved_at_40[0x40];
5686 };
5687
5688 struct mlx5_ifc_modify_tir_in_bits {
5689 u8 opcode[0x10];
5690 u8 uid[0x10];
5691
5692 u8 reserved_at_20[0x10];
5693 u8 op_mod[0x10];
5694
5695 u8 reserved_at_40[0x8];
5696 u8 tirn[0x18];
5697
5698 u8 reserved_at_60[0x20];
5699
5700 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5701
5702 u8 reserved_at_c0[0x40];
5703
5704 struct mlx5_ifc_tirc_bits ctx;
5705 };
5706
5707 struct mlx5_ifc_modify_sq_out_bits {
5708 u8 status[0x8];
5709 u8 reserved_at_8[0x18];
5710
5711 u8 syndrome[0x20];
5712
5713 u8 reserved_at_40[0x40];
5714 };
5715
5716 struct mlx5_ifc_modify_sq_in_bits {
5717 u8 opcode[0x10];
5718 u8 uid[0x10];
5719
5720 u8 reserved_at_20[0x10];
5721 u8 op_mod[0x10];
5722
5723 u8 sq_state[0x4];
5724 u8 reserved_at_44[0x4];
5725 u8 sqn[0x18];
5726
5727 u8 reserved_at_60[0x20];
5728
5729 u8 modify_bitmask[0x40];
5730
5731 u8 reserved_at_c0[0x40];
5732
5733 struct mlx5_ifc_sqc_bits ctx;
5734 };
5735
5736 struct mlx5_ifc_modify_scheduling_element_out_bits {
5737 u8 status[0x8];
5738 u8 reserved_at_8[0x18];
5739
5740 u8 syndrome[0x20];
5741
5742 u8 reserved_at_40[0x1c0];
5743 };
5744
5745 enum {
5746 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5747 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5748 };
5749
5750 struct mlx5_ifc_modify_scheduling_element_in_bits {
5751 u8 opcode[0x10];
5752 u8 reserved_at_10[0x10];
5753
5754 u8 reserved_at_20[0x10];
5755 u8 op_mod[0x10];
5756
5757 u8 scheduling_hierarchy[0x8];
5758 u8 reserved_at_48[0x18];
5759
5760 u8 scheduling_element_id[0x20];
5761
5762 u8 reserved_at_80[0x20];
5763
5764 u8 modify_bitmask[0x20];
5765
5766 u8 reserved_at_c0[0x40];
5767
5768 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5769
5770 u8 reserved_at_300[0x100];
5771 };
5772
5773 struct mlx5_ifc_modify_rqt_out_bits {
5774 u8 status[0x8];
5775 u8 reserved_at_8[0x18];
5776
5777 u8 syndrome[0x20];
5778
5779 u8 reserved_at_40[0x40];
5780 };
5781
5782 struct mlx5_ifc_rqt_bitmask_bits {
5783 u8 reserved_at_0[0x20];
5784
5785 u8 reserved_at_20[0x1f];
5786 u8 rqn_list[0x1];
5787 };
5788
5789 struct mlx5_ifc_modify_rqt_in_bits {
5790 u8 opcode[0x10];
5791 u8 uid[0x10];
5792
5793 u8 reserved_at_20[0x10];
5794 u8 op_mod[0x10];
5795
5796 u8 reserved_at_40[0x8];
5797 u8 rqtn[0x18];
5798
5799 u8 reserved_at_60[0x20];
5800
5801 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5802
5803 u8 reserved_at_c0[0x40];
5804
5805 struct mlx5_ifc_rqtc_bits ctx;
5806 };
5807
5808 struct mlx5_ifc_modify_rq_out_bits {
5809 u8 status[0x8];
5810 u8 reserved_at_8[0x18];
5811
5812 u8 syndrome[0x20];
5813
5814 u8 reserved_at_40[0x40];
5815 };
5816
5817 enum {
5818 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5819 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5820 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5821 };
5822
5823 struct mlx5_ifc_modify_rq_in_bits {
5824 u8 opcode[0x10];
5825 u8 uid[0x10];
5826
5827 u8 reserved_at_20[0x10];
5828 u8 op_mod[0x10];
5829
5830 u8 rq_state[0x4];
5831 u8 reserved_at_44[0x4];
5832 u8 rqn[0x18];
5833
5834 u8 reserved_at_60[0x20];
5835
5836 u8 modify_bitmask[0x40];
5837
5838 u8 reserved_at_c0[0x40];
5839
5840 struct mlx5_ifc_rqc_bits ctx;
5841 };
5842
5843 struct mlx5_ifc_modify_rmp_out_bits {
5844 u8 status[0x8];
5845 u8 reserved_at_8[0x18];
5846
5847 u8 syndrome[0x20];
5848
5849 u8 reserved_at_40[0x40];
5850 };
5851
5852 struct mlx5_ifc_rmp_bitmask_bits {
5853 u8 reserved_at_0[0x20];
5854
5855 u8 reserved_at_20[0x1f];
5856 u8 lwm[0x1];
5857 };
5858
5859 struct mlx5_ifc_modify_rmp_in_bits {
5860 u8 opcode[0x10];
5861 u8 uid[0x10];
5862
5863 u8 reserved_at_20[0x10];
5864 u8 op_mod[0x10];
5865
5866 u8 rmp_state[0x4];
5867 u8 reserved_at_44[0x4];
5868 u8 rmpn[0x18];
5869
5870 u8 reserved_at_60[0x20];
5871
5872 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5873
5874 u8 reserved_at_c0[0x40];
5875
5876 struct mlx5_ifc_rmpc_bits ctx;
5877 };
5878
5879 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5880 u8 status[0x8];
5881 u8 reserved_at_8[0x18];
5882
5883 u8 syndrome[0x20];
5884
5885 u8 reserved_at_40[0x40];
5886 };
5887
5888 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5889 u8 reserved_at_0[0x12];
5890 u8 affiliation[0x1];
5891 u8 reserved_at_13[0x1];
5892 u8 disable_uc_local_lb[0x1];
5893 u8 disable_mc_local_lb[0x1];
5894 u8 node_guid[0x1];
5895 u8 port_guid[0x1];
5896 u8 min_inline[0x1];
5897 u8 mtu[0x1];
5898 u8 change_event[0x1];
5899 u8 promisc[0x1];
5900 u8 permanent_address[0x1];
5901 u8 addresses_list[0x1];
5902 u8 roce_en[0x1];
5903 u8 reserved_at_1f[0x1];
5904 };
5905
5906 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5907 u8 opcode[0x10];
5908 u8 reserved_at_10[0x10];
5909
5910 u8 reserved_at_20[0x10];
5911 u8 op_mod[0x10];
5912
5913 u8 other_vport[0x1];
5914 u8 reserved_at_41[0xf];
5915 u8 vport_number[0x10];
5916
5917 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5918
5919 u8 reserved_at_80[0x780];
5920
5921 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5922 };
5923
5924 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5925 u8 status[0x8];
5926 u8 reserved_at_8[0x18];
5927
5928 u8 syndrome[0x20];
5929
5930 u8 reserved_at_40[0x40];
5931 };
5932
5933 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5934 u8 opcode[0x10];
5935 u8 reserved_at_10[0x10];
5936
5937 u8 reserved_at_20[0x10];
5938 u8 op_mod[0x10];
5939
5940 u8 other_vport[0x1];
5941 u8 reserved_at_41[0xb];
5942 u8 port_num[0x4];
5943 u8 vport_number[0x10];
5944
5945 u8 reserved_at_60[0x20];
5946
5947 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5948 };
5949
5950 struct mlx5_ifc_modify_cq_out_bits {
5951 u8 status[0x8];
5952 u8 reserved_at_8[0x18];
5953
5954 u8 syndrome[0x20];
5955
5956 u8 reserved_at_40[0x40];
5957 };
5958
5959 enum {
5960 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5961 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5962 };
5963
5964 struct mlx5_ifc_modify_cq_in_bits {
5965 u8 opcode[0x10];
5966 u8 uid[0x10];
5967
5968 u8 reserved_at_20[0x10];
5969 u8 op_mod[0x10];
5970
5971 u8 reserved_at_40[0x8];
5972 u8 cqn[0x18];
5973
5974 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5975
5976 struct mlx5_ifc_cqc_bits cq_context;
5977
5978 u8 reserved_at_280[0x60];
5979
5980 u8 cq_umem_valid[0x1];
5981 u8 reserved_at_2e1[0x1f];
5982
5983 u8 reserved_at_300[0x580];
5984
5985 u8 pas[0][0x40];
5986 };
5987
5988 struct mlx5_ifc_modify_cong_status_out_bits {
5989 u8 status[0x8];
5990 u8 reserved_at_8[0x18];
5991
5992 u8 syndrome[0x20];
5993
5994 u8 reserved_at_40[0x40];
5995 };
5996
5997 struct mlx5_ifc_modify_cong_status_in_bits {
5998 u8 opcode[0x10];
5999 u8 reserved_at_10[0x10];
6000
6001 u8 reserved_at_20[0x10];
6002 u8 op_mod[0x10];
6003
6004 u8 reserved_at_40[0x18];
6005 u8 priority[0x4];
6006 u8 cong_protocol[0x4];
6007
6008 u8 enable[0x1];
6009 u8 tag_enable[0x1];
6010 u8 reserved_at_62[0x1e];
6011 };
6012
6013 struct mlx5_ifc_modify_cong_params_out_bits {
6014 u8 status[0x8];
6015 u8 reserved_at_8[0x18];
6016
6017 u8 syndrome[0x20];
6018
6019 u8 reserved_at_40[0x40];
6020 };
6021
6022 struct mlx5_ifc_modify_cong_params_in_bits {
6023 u8 opcode[0x10];
6024 u8 reserved_at_10[0x10];
6025
6026 u8 reserved_at_20[0x10];
6027 u8 op_mod[0x10];
6028
6029 u8 reserved_at_40[0x1c];
6030 u8 cong_protocol[0x4];
6031
6032 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6033
6034 u8 reserved_at_80[0x80];
6035
6036 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6037 };
6038
6039 struct mlx5_ifc_manage_pages_out_bits {
6040 u8 status[0x8];
6041 u8 reserved_at_8[0x18];
6042
6043 u8 syndrome[0x20];
6044
6045 u8 output_num_entries[0x20];
6046
6047 u8 reserved_at_60[0x20];
6048
6049 u8 pas[0][0x40];
6050 };
6051
6052 enum {
6053 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6054 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6055 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6056 };
6057
6058 struct mlx5_ifc_manage_pages_in_bits {
6059 u8 opcode[0x10];
6060 u8 reserved_at_10[0x10];
6061
6062 u8 reserved_at_20[0x10];
6063 u8 op_mod[0x10];
6064
6065 u8 embedded_cpu_function[0x1];
6066 u8 reserved_at_41[0xf];
6067 u8 function_id[0x10];
6068
6069 u8 input_num_entries[0x20];
6070
6071 u8 pas[0][0x40];
6072 };
6073
6074 struct mlx5_ifc_mad_ifc_out_bits {
6075 u8 status[0x8];
6076 u8 reserved_at_8[0x18];
6077
6078 u8 syndrome[0x20];
6079
6080 u8 reserved_at_40[0x40];
6081
6082 u8 response_mad_packet[256][0x8];
6083 };
6084
6085 struct mlx5_ifc_mad_ifc_in_bits {
6086 u8 opcode[0x10];
6087 u8 reserved_at_10[0x10];
6088
6089 u8 reserved_at_20[0x10];
6090 u8 op_mod[0x10];
6091
6092 u8 remote_lid[0x10];
6093 u8 reserved_at_50[0x8];
6094 u8 port[0x8];
6095
6096 u8 reserved_at_60[0x20];
6097
6098 u8 mad[256][0x8];
6099 };
6100
6101 struct mlx5_ifc_init_hca_out_bits {
6102 u8 status[0x8];
6103 u8 reserved_at_8[0x18];
6104
6105 u8 syndrome[0x20];
6106
6107 u8 reserved_at_40[0x40];
6108 };
6109
6110 struct mlx5_ifc_init_hca_in_bits {
6111 u8 opcode[0x10];
6112 u8 reserved_at_10[0x10];
6113
6114 u8 reserved_at_20[0x10];
6115 u8 op_mod[0x10];
6116
6117 u8 reserved_at_40[0x40];
6118 u8 sw_owner_id[4][0x20];
6119 };
6120
6121 struct mlx5_ifc_init2rtr_qp_out_bits {
6122 u8 status[0x8];
6123 u8 reserved_at_8[0x18];
6124
6125 u8 syndrome[0x20];
6126
6127 u8 reserved_at_40[0x40];
6128 };
6129
6130 struct mlx5_ifc_init2rtr_qp_in_bits {
6131 u8 opcode[0x10];
6132 u8 uid[0x10];
6133
6134 u8 reserved_at_20[0x10];
6135 u8 op_mod[0x10];
6136
6137 u8 reserved_at_40[0x8];
6138 u8 qpn[0x18];
6139
6140 u8 reserved_at_60[0x20];
6141
6142 u8 opt_param_mask[0x20];
6143
6144 u8 reserved_at_a0[0x20];
6145
6146 struct mlx5_ifc_qpc_bits qpc;
6147
6148 u8 reserved_at_800[0x80];
6149 };
6150
6151 struct mlx5_ifc_init2init_qp_out_bits {
6152 u8 status[0x8];
6153 u8 reserved_at_8[0x18];
6154
6155 u8 syndrome[0x20];
6156
6157 u8 reserved_at_40[0x40];
6158 };
6159
6160 struct mlx5_ifc_init2init_qp_in_bits {
6161 u8 opcode[0x10];
6162 u8 uid[0x10];
6163
6164 u8 reserved_at_20[0x10];
6165 u8 op_mod[0x10];
6166
6167 u8 reserved_at_40[0x8];
6168 u8 qpn[0x18];
6169
6170 u8 reserved_at_60[0x20];
6171
6172 u8 opt_param_mask[0x20];
6173
6174 u8 reserved_at_a0[0x20];
6175
6176 struct mlx5_ifc_qpc_bits qpc;
6177
6178 u8 reserved_at_800[0x80];
6179 };
6180
6181 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6182 u8 status[0x8];
6183 u8 reserved_at_8[0x18];
6184
6185 u8 syndrome[0x20];
6186
6187 u8 reserved_at_40[0x40];
6188
6189 u8 packet_headers_log[128][0x8];
6190
6191 u8 packet_syndrome[64][0x8];
6192 };
6193
6194 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6195 u8 opcode[0x10];
6196 u8 reserved_at_10[0x10];
6197
6198 u8 reserved_at_20[0x10];
6199 u8 op_mod[0x10];
6200
6201 u8 reserved_at_40[0x40];
6202 };
6203
6204 struct mlx5_ifc_gen_eqe_in_bits {
6205 u8 opcode[0x10];
6206 u8 reserved_at_10[0x10];
6207
6208 u8 reserved_at_20[0x10];
6209 u8 op_mod[0x10];
6210
6211 u8 reserved_at_40[0x18];
6212 u8 eq_number[0x8];
6213
6214 u8 reserved_at_60[0x20];
6215
6216 u8 eqe[64][0x8];
6217 };
6218
6219 struct mlx5_ifc_gen_eq_out_bits {
6220 u8 status[0x8];
6221 u8 reserved_at_8[0x18];
6222
6223 u8 syndrome[0x20];
6224
6225 u8 reserved_at_40[0x40];
6226 };
6227
6228 struct mlx5_ifc_enable_hca_out_bits {
6229 u8 status[0x8];
6230 u8 reserved_at_8[0x18];
6231
6232 u8 syndrome[0x20];
6233
6234 u8 reserved_at_40[0x20];
6235 };
6236
6237 struct mlx5_ifc_enable_hca_in_bits {
6238 u8 opcode[0x10];
6239 u8 reserved_at_10[0x10];
6240
6241 u8 reserved_at_20[0x10];
6242 u8 op_mod[0x10];
6243
6244 u8 embedded_cpu_function[0x1];
6245 u8 reserved_at_41[0xf];
6246 u8 function_id[0x10];
6247
6248 u8 reserved_at_60[0x20];
6249 };
6250
6251 struct mlx5_ifc_drain_dct_out_bits {
6252 u8 status[0x8];
6253 u8 reserved_at_8[0x18];
6254
6255 u8 syndrome[0x20];
6256
6257 u8 reserved_at_40[0x40];
6258 };
6259
6260 struct mlx5_ifc_drain_dct_in_bits {
6261 u8 opcode[0x10];
6262 u8 uid[0x10];
6263
6264 u8 reserved_at_20[0x10];
6265 u8 op_mod[0x10];
6266
6267 u8 reserved_at_40[0x8];
6268 u8 dctn[0x18];
6269
6270 u8 reserved_at_60[0x20];
6271 };
6272
6273 struct mlx5_ifc_disable_hca_out_bits {
6274 u8 status[0x8];
6275 u8 reserved_at_8[0x18];
6276
6277 u8 syndrome[0x20];
6278
6279 u8 reserved_at_40[0x20];
6280 };
6281
6282 struct mlx5_ifc_disable_hca_in_bits {
6283 u8 opcode[0x10];
6284 u8 reserved_at_10[0x10];
6285
6286 u8 reserved_at_20[0x10];
6287 u8 op_mod[0x10];
6288
6289 u8 embedded_cpu_function[0x1];
6290 u8 reserved_at_41[0xf];
6291 u8 function_id[0x10];
6292
6293 u8 reserved_at_60[0x20];
6294 };
6295
6296 struct mlx5_ifc_detach_from_mcg_out_bits {
6297 u8 status[0x8];
6298 u8 reserved_at_8[0x18];
6299
6300 u8 syndrome[0x20];
6301
6302 u8 reserved_at_40[0x40];
6303 };
6304
6305 struct mlx5_ifc_detach_from_mcg_in_bits {
6306 u8 opcode[0x10];
6307 u8 uid[0x10];
6308
6309 u8 reserved_at_20[0x10];
6310 u8 op_mod[0x10];
6311
6312 u8 reserved_at_40[0x8];
6313 u8 qpn[0x18];
6314
6315 u8 reserved_at_60[0x20];
6316
6317 u8 multicast_gid[16][0x8];
6318 };
6319
6320 struct mlx5_ifc_destroy_xrq_out_bits {
6321 u8 status[0x8];
6322 u8 reserved_at_8[0x18];
6323
6324 u8 syndrome[0x20];
6325
6326 u8 reserved_at_40[0x40];
6327 };
6328
6329 struct mlx5_ifc_destroy_xrq_in_bits {
6330 u8 opcode[0x10];
6331 u8 uid[0x10];
6332
6333 u8 reserved_at_20[0x10];
6334 u8 op_mod[0x10];
6335
6336 u8 reserved_at_40[0x8];
6337 u8 xrqn[0x18];
6338
6339 u8 reserved_at_60[0x20];
6340 };
6341
6342 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6343 u8 status[0x8];
6344 u8 reserved_at_8[0x18];
6345
6346 u8 syndrome[0x20];
6347
6348 u8 reserved_at_40[0x40];
6349 };
6350
6351 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6352 u8 opcode[0x10];
6353 u8 uid[0x10];
6354
6355 u8 reserved_at_20[0x10];
6356 u8 op_mod[0x10];
6357
6358 u8 reserved_at_40[0x8];
6359 u8 xrc_srqn[0x18];
6360
6361 u8 reserved_at_60[0x20];
6362 };
6363
6364 struct mlx5_ifc_destroy_tis_out_bits {
6365 u8 status[0x8];
6366 u8 reserved_at_8[0x18];
6367
6368 u8 syndrome[0x20];
6369
6370 u8 reserved_at_40[0x40];
6371 };
6372
6373 struct mlx5_ifc_destroy_tis_in_bits {
6374 u8 opcode[0x10];
6375 u8 uid[0x10];
6376
6377 u8 reserved_at_20[0x10];
6378 u8 op_mod[0x10];
6379
6380 u8 reserved_at_40[0x8];
6381 u8 tisn[0x18];
6382
6383 u8 reserved_at_60[0x20];
6384 };
6385
6386 struct mlx5_ifc_destroy_tir_out_bits {
6387 u8 status[0x8];
6388 u8 reserved_at_8[0x18];
6389
6390 u8 syndrome[0x20];
6391
6392 u8 reserved_at_40[0x40];
6393 };
6394
6395 struct mlx5_ifc_destroy_tir_in_bits {
6396 u8 opcode[0x10];
6397 u8 uid[0x10];
6398
6399 u8 reserved_at_20[0x10];
6400 u8 op_mod[0x10];
6401
6402 u8 reserved_at_40[0x8];
6403 u8 tirn[0x18];
6404
6405 u8 reserved_at_60[0x20];
6406 };
6407
6408 struct mlx5_ifc_destroy_srq_out_bits {
6409 u8 status[0x8];
6410 u8 reserved_at_8[0x18];
6411
6412 u8 syndrome[0x20];
6413
6414 u8 reserved_at_40[0x40];
6415 };
6416
6417 struct mlx5_ifc_destroy_srq_in_bits {
6418 u8 opcode[0x10];
6419 u8 uid[0x10];
6420
6421 u8 reserved_at_20[0x10];
6422 u8 op_mod[0x10];
6423
6424 u8 reserved_at_40[0x8];
6425 u8 srqn[0x18];
6426
6427 u8 reserved_at_60[0x20];
6428 };
6429
6430 struct mlx5_ifc_destroy_sq_out_bits {
6431 u8 status[0x8];
6432 u8 reserved_at_8[0x18];
6433
6434 u8 syndrome[0x20];
6435
6436 u8 reserved_at_40[0x40];
6437 };
6438
6439 struct mlx5_ifc_destroy_sq_in_bits {
6440 u8 opcode[0x10];
6441 u8 uid[0x10];
6442
6443 u8 reserved_at_20[0x10];
6444 u8 op_mod[0x10];
6445
6446 u8 reserved_at_40[0x8];
6447 u8 sqn[0x18];
6448
6449 u8 reserved_at_60[0x20];
6450 };
6451
6452 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6453 u8 status[0x8];
6454 u8 reserved_at_8[0x18];
6455
6456 u8 syndrome[0x20];
6457
6458 u8 reserved_at_40[0x1c0];
6459 };
6460
6461 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6462 u8 opcode[0x10];
6463 u8 reserved_at_10[0x10];
6464
6465 u8 reserved_at_20[0x10];
6466 u8 op_mod[0x10];
6467
6468 u8 scheduling_hierarchy[0x8];
6469 u8 reserved_at_48[0x18];
6470
6471 u8 scheduling_element_id[0x20];
6472
6473 u8 reserved_at_80[0x180];
6474 };
6475
6476 struct mlx5_ifc_destroy_rqt_out_bits {
6477 u8 status[0x8];
6478 u8 reserved_at_8[0x18];
6479
6480 u8 syndrome[0x20];
6481
6482 u8 reserved_at_40[0x40];
6483 };
6484
6485 struct mlx5_ifc_destroy_rqt_in_bits {
6486 u8 opcode[0x10];
6487 u8 uid[0x10];
6488
6489 u8 reserved_at_20[0x10];
6490 u8 op_mod[0x10];
6491
6492 u8 reserved_at_40[0x8];
6493 u8 rqtn[0x18];
6494
6495 u8 reserved_at_60[0x20];
6496 };
6497
6498 struct mlx5_ifc_destroy_rq_out_bits {
6499 u8 status[0x8];
6500 u8 reserved_at_8[0x18];
6501
6502 u8 syndrome[0x20];
6503
6504 u8 reserved_at_40[0x40];
6505 };
6506
6507 struct mlx5_ifc_destroy_rq_in_bits {
6508 u8 opcode[0x10];
6509 u8 uid[0x10];
6510
6511 u8 reserved_at_20[0x10];
6512 u8 op_mod[0x10];
6513
6514 u8 reserved_at_40[0x8];
6515 u8 rqn[0x18];
6516
6517 u8 reserved_at_60[0x20];
6518 };
6519
6520 struct mlx5_ifc_set_delay_drop_params_in_bits {
6521 u8 opcode[0x10];
6522 u8 reserved_at_10[0x10];
6523
6524 u8 reserved_at_20[0x10];
6525 u8 op_mod[0x10];
6526
6527 u8 reserved_at_40[0x20];
6528
6529 u8 reserved_at_60[0x10];
6530 u8 delay_drop_timeout[0x10];
6531 };
6532
6533 struct mlx5_ifc_set_delay_drop_params_out_bits {
6534 u8 status[0x8];
6535 u8 reserved_at_8[0x18];
6536
6537 u8 syndrome[0x20];
6538
6539 u8 reserved_at_40[0x40];
6540 };
6541
6542 struct mlx5_ifc_destroy_rmp_out_bits {
6543 u8 status[0x8];
6544 u8 reserved_at_8[0x18];
6545
6546 u8 syndrome[0x20];
6547
6548 u8 reserved_at_40[0x40];
6549 };
6550
6551 struct mlx5_ifc_destroy_rmp_in_bits {
6552 u8 opcode[0x10];
6553 u8 uid[0x10];
6554
6555 u8 reserved_at_20[0x10];
6556 u8 op_mod[0x10];
6557
6558 u8 reserved_at_40[0x8];
6559 u8 rmpn[0x18];
6560
6561 u8 reserved_at_60[0x20];
6562 };
6563
6564 struct mlx5_ifc_destroy_qp_out_bits {
6565 u8 status[0x8];
6566 u8 reserved_at_8[0x18];
6567
6568 u8 syndrome[0x20];
6569
6570 u8 reserved_at_40[0x40];
6571 };
6572
6573 struct mlx5_ifc_destroy_qp_in_bits {
6574 u8 opcode[0x10];
6575 u8 uid[0x10];
6576
6577 u8 reserved_at_20[0x10];
6578 u8 op_mod[0x10];
6579
6580 u8 reserved_at_40[0x8];
6581 u8 qpn[0x18];
6582
6583 u8 reserved_at_60[0x20];
6584 };
6585
6586 struct mlx5_ifc_destroy_psv_out_bits {
6587 u8 status[0x8];
6588 u8 reserved_at_8[0x18];
6589
6590 u8 syndrome[0x20];
6591
6592 u8 reserved_at_40[0x40];
6593 };
6594
6595 struct mlx5_ifc_destroy_psv_in_bits {
6596 u8 opcode[0x10];
6597 u8 reserved_at_10[0x10];
6598
6599 u8 reserved_at_20[0x10];
6600 u8 op_mod[0x10];
6601
6602 u8 reserved_at_40[0x8];
6603 u8 psvn[0x18];
6604
6605 u8 reserved_at_60[0x20];
6606 };
6607
6608 struct mlx5_ifc_destroy_mkey_out_bits {
6609 u8 status[0x8];
6610 u8 reserved_at_8[0x18];
6611
6612 u8 syndrome[0x20];
6613
6614 u8 reserved_at_40[0x40];
6615 };
6616
6617 struct mlx5_ifc_destroy_mkey_in_bits {
6618 u8 opcode[0x10];
6619 u8 reserved_at_10[0x10];
6620
6621 u8 reserved_at_20[0x10];
6622 u8 op_mod[0x10];
6623
6624 u8 reserved_at_40[0x8];
6625 u8 mkey_index[0x18];
6626
6627 u8 reserved_at_60[0x20];
6628 };
6629
6630 struct mlx5_ifc_destroy_flow_table_out_bits {
6631 u8 status[0x8];
6632 u8 reserved_at_8[0x18];
6633
6634 u8 syndrome[0x20];
6635
6636 u8 reserved_at_40[0x40];
6637 };
6638
6639 struct mlx5_ifc_destroy_flow_table_in_bits {
6640 u8 opcode[0x10];
6641 u8 reserved_at_10[0x10];
6642
6643 u8 reserved_at_20[0x10];
6644 u8 op_mod[0x10];
6645
6646 u8 other_vport[0x1];
6647 u8 reserved_at_41[0xf];
6648 u8 vport_number[0x10];
6649
6650 u8 reserved_at_60[0x20];
6651
6652 u8 table_type[0x8];
6653 u8 reserved_at_88[0x18];
6654
6655 u8 reserved_at_a0[0x8];
6656 u8 table_id[0x18];
6657
6658 u8 reserved_at_c0[0x140];
6659 };
6660
6661 struct mlx5_ifc_destroy_flow_group_out_bits {
6662 u8 status[0x8];
6663 u8 reserved_at_8[0x18];
6664
6665 u8 syndrome[0x20];
6666
6667 u8 reserved_at_40[0x40];
6668 };
6669
6670 struct mlx5_ifc_destroy_flow_group_in_bits {
6671 u8 opcode[0x10];
6672 u8 reserved_at_10[0x10];
6673
6674 u8 reserved_at_20[0x10];
6675 u8 op_mod[0x10];
6676
6677 u8 other_vport[0x1];
6678 u8 reserved_at_41[0xf];
6679 u8 vport_number[0x10];
6680
6681 u8 reserved_at_60[0x20];
6682
6683 u8 table_type[0x8];
6684 u8 reserved_at_88[0x18];
6685
6686 u8 reserved_at_a0[0x8];
6687 u8 table_id[0x18];
6688
6689 u8 group_id[0x20];
6690
6691 u8 reserved_at_e0[0x120];
6692 };
6693
6694 struct mlx5_ifc_destroy_eq_out_bits {
6695 u8 status[0x8];
6696 u8 reserved_at_8[0x18];
6697
6698 u8 syndrome[0x20];
6699
6700 u8 reserved_at_40[0x40];
6701 };
6702
6703 struct mlx5_ifc_destroy_eq_in_bits {
6704 u8 opcode[0x10];
6705 u8 reserved_at_10[0x10];
6706
6707 u8 reserved_at_20[0x10];
6708 u8 op_mod[0x10];
6709
6710 u8 reserved_at_40[0x18];
6711 u8 eq_number[0x8];
6712
6713 u8 reserved_at_60[0x20];
6714 };
6715
6716 struct mlx5_ifc_destroy_dct_out_bits {
6717 u8 status[0x8];
6718 u8 reserved_at_8[0x18];
6719
6720 u8 syndrome[0x20];
6721
6722 u8 reserved_at_40[0x40];
6723 };
6724
6725 struct mlx5_ifc_destroy_dct_in_bits {
6726 u8 opcode[0x10];
6727 u8 uid[0x10];
6728
6729 u8 reserved_at_20[0x10];
6730 u8 op_mod[0x10];
6731
6732 u8 reserved_at_40[0x8];
6733 u8 dctn[0x18];
6734
6735 u8 reserved_at_60[0x20];
6736 };
6737
6738 struct mlx5_ifc_destroy_cq_out_bits {
6739 u8 status[0x8];
6740 u8 reserved_at_8[0x18];
6741
6742 u8 syndrome[0x20];
6743
6744 u8 reserved_at_40[0x40];
6745 };
6746
6747 struct mlx5_ifc_destroy_cq_in_bits {
6748 u8 opcode[0x10];
6749 u8 uid[0x10];
6750
6751 u8 reserved_at_20[0x10];
6752 u8 op_mod[0x10];
6753
6754 u8 reserved_at_40[0x8];
6755 u8 cqn[0x18];
6756
6757 u8 reserved_at_60[0x20];
6758 };
6759
6760 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6761 u8 status[0x8];
6762 u8 reserved_at_8[0x18];
6763
6764 u8 syndrome[0x20];
6765
6766 u8 reserved_at_40[0x40];
6767 };
6768
6769 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6770 u8 opcode[0x10];
6771 u8 reserved_at_10[0x10];
6772
6773 u8 reserved_at_20[0x10];
6774 u8 op_mod[0x10];
6775
6776 u8 reserved_at_40[0x20];
6777
6778 u8 reserved_at_60[0x10];
6779 u8 vxlan_udp_port[0x10];
6780 };
6781
6782 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6783 u8 status[0x8];
6784 u8 reserved_at_8[0x18];
6785
6786 u8 syndrome[0x20];
6787
6788 u8 reserved_at_40[0x40];
6789 };
6790
6791 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6792 u8 opcode[0x10];
6793 u8 reserved_at_10[0x10];
6794
6795 u8 reserved_at_20[0x10];
6796 u8 op_mod[0x10];
6797
6798 u8 reserved_at_40[0x60];
6799
6800 u8 reserved_at_a0[0x8];
6801 u8 table_index[0x18];
6802
6803 u8 reserved_at_c0[0x140];
6804 };
6805
6806 struct mlx5_ifc_delete_fte_out_bits {
6807 u8 status[0x8];
6808 u8 reserved_at_8[0x18];
6809
6810 u8 syndrome[0x20];
6811
6812 u8 reserved_at_40[0x40];
6813 };
6814
6815 struct mlx5_ifc_delete_fte_in_bits {
6816 u8 opcode[0x10];
6817 u8 reserved_at_10[0x10];
6818
6819 u8 reserved_at_20[0x10];
6820 u8 op_mod[0x10];
6821
6822 u8 other_vport[0x1];
6823 u8 reserved_at_41[0xf];
6824 u8 vport_number[0x10];
6825
6826 u8 reserved_at_60[0x20];
6827
6828 u8 table_type[0x8];
6829 u8 reserved_at_88[0x18];
6830
6831 u8 reserved_at_a0[0x8];
6832 u8 table_id[0x18];
6833
6834 u8 reserved_at_c0[0x40];
6835
6836 u8 flow_index[0x20];
6837
6838 u8 reserved_at_120[0xe0];
6839 };
6840
6841 struct mlx5_ifc_dealloc_xrcd_out_bits {
6842 u8 status[0x8];
6843 u8 reserved_at_8[0x18];
6844
6845 u8 syndrome[0x20];
6846
6847 u8 reserved_at_40[0x40];
6848 };
6849
6850 struct mlx5_ifc_dealloc_xrcd_in_bits {
6851 u8 opcode[0x10];
6852 u8 uid[0x10];
6853
6854 u8 reserved_at_20[0x10];
6855 u8 op_mod[0x10];
6856
6857 u8 reserved_at_40[0x8];
6858 u8 xrcd[0x18];
6859
6860 u8 reserved_at_60[0x20];
6861 };
6862
6863 struct mlx5_ifc_dealloc_uar_out_bits {
6864 u8 status[0x8];
6865 u8 reserved_at_8[0x18];
6866
6867 u8 syndrome[0x20];
6868
6869 u8 reserved_at_40[0x40];
6870 };
6871
6872 struct mlx5_ifc_dealloc_uar_in_bits {
6873 u8 opcode[0x10];
6874 u8 reserved_at_10[0x10];
6875
6876 u8 reserved_at_20[0x10];
6877 u8 op_mod[0x10];
6878
6879 u8 reserved_at_40[0x8];
6880 u8 uar[0x18];
6881
6882 u8 reserved_at_60[0x20];
6883 };
6884
6885 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6886 u8 status[0x8];
6887 u8 reserved_at_8[0x18];
6888
6889 u8 syndrome[0x20];
6890
6891 u8 reserved_at_40[0x40];
6892 };
6893
6894 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6895 u8 opcode[0x10];
6896 u8 uid[0x10];
6897
6898 u8 reserved_at_20[0x10];
6899 u8 op_mod[0x10];
6900
6901 u8 reserved_at_40[0x8];
6902 u8 transport_domain[0x18];
6903
6904 u8 reserved_at_60[0x20];
6905 };
6906
6907 struct mlx5_ifc_dealloc_q_counter_out_bits {
6908 u8 status[0x8];
6909 u8 reserved_at_8[0x18];
6910
6911 u8 syndrome[0x20];
6912
6913 u8 reserved_at_40[0x40];
6914 };
6915
6916 struct mlx5_ifc_dealloc_q_counter_in_bits {
6917 u8 opcode[0x10];
6918 u8 reserved_at_10[0x10];
6919
6920 u8 reserved_at_20[0x10];
6921 u8 op_mod[0x10];
6922
6923 u8 reserved_at_40[0x18];
6924 u8 counter_set_id[0x8];
6925
6926 u8 reserved_at_60[0x20];
6927 };
6928
6929 struct mlx5_ifc_dealloc_pd_out_bits {
6930 u8 status[0x8];
6931 u8 reserved_at_8[0x18];
6932
6933 u8 syndrome[0x20];
6934
6935 u8 reserved_at_40[0x40];
6936 };
6937
6938 struct mlx5_ifc_dealloc_pd_in_bits {
6939 u8 opcode[0x10];
6940 u8 uid[0x10];
6941
6942 u8 reserved_at_20[0x10];
6943 u8 op_mod[0x10];
6944
6945 u8 reserved_at_40[0x8];
6946 u8 pd[0x18];
6947
6948 u8 reserved_at_60[0x20];
6949 };
6950
6951 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6952 u8 status[0x8];
6953 u8 reserved_at_8[0x18];
6954
6955 u8 syndrome[0x20];
6956
6957 u8 reserved_at_40[0x40];
6958 };
6959
6960 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6961 u8 opcode[0x10];
6962 u8 reserved_at_10[0x10];
6963
6964 u8 reserved_at_20[0x10];
6965 u8 op_mod[0x10];
6966
6967 u8 flow_counter_id[0x20];
6968
6969 u8 reserved_at_60[0x20];
6970 };
6971
6972 struct mlx5_ifc_create_xrq_out_bits {
6973 u8 status[0x8];
6974 u8 reserved_at_8[0x18];
6975
6976 u8 syndrome[0x20];
6977
6978 u8 reserved_at_40[0x8];
6979 u8 xrqn[0x18];
6980
6981 u8 reserved_at_60[0x20];
6982 };
6983
6984 struct mlx5_ifc_create_xrq_in_bits {
6985 u8 opcode[0x10];
6986 u8 uid[0x10];
6987
6988 u8 reserved_at_20[0x10];
6989 u8 op_mod[0x10];
6990
6991 u8 reserved_at_40[0x40];
6992
6993 struct mlx5_ifc_xrqc_bits xrq_context;
6994 };
6995
6996 struct mlx5_ifc_create_xrc_srq_out_bits {
6997 u8 status[0x8];
6998 u8 reserved_at_8[0x18];
6999
7000 u8 syndrome[0x20];
7001
7002 u8 reserved_at_40[0x8];
7003 u8 xrc_srqn[0x18];
7004
7005 u8 reserved_at_60[0x20];
7006 };
7007
7008 struct mlx5_ifc_create_xrc_srq_in_bits {
7009 u8 opcode[0x10];
7010 u8 uid[0x10];
7011
7012 u8 reserved_at_20[0x10];
7013 u8 op_mod[0x10];
7014
7015 u8 reserved_at_40[0x40];
7016
7017 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7018
7019 u8 reserved_at_280[0x60];
7020
7021 u8 xrc_srq_umem_valid[0x1];
7022 u8 reserved_at_2e1[0x1f];
7023
7024 u8 reserved_at_300[0x580];
7025
7026 u8 pas[0][0x40];
7027 };
7028
7029 struct mlx5_ifc_create_tis_out_bits {
7030 u8 status[0x8];
7031 u8 reserved_at_8[0x18];
7032
7033 u8 syndrome[0x20];
7034
7035 u8 reserved_at_40[0x8];
7036 u8 tisn[0x18];
7037
7038 u8 reserved_at_60[0x20];
7039 };
7040
7041 struct mlx5_ifc_create_tis_in_bits {
7042 u8 opcode[0x10];
7043 u8 uid[0x10];
7044
7045 u8 reserved_at_20[0x10];
7046 u8 op_mod[0x10];
7047
7048 u8 reserved_at_40[0xc0];
7049
7050 struct mlx5_ifc_tisc_bits ctx;
7051 };
7052
7053 struct mlx5_ifc_create_tir_out_bits {
7054 u8 status[0x8];
7055 u8 icm_address_63_40[0x18];
7056
7057 u8 syndrome[0x20];
7058
7059 u8 icm_address_39_32[0x8];
7060 u8 tirn[0x18];
7061
7062 u8 icm_address_31_0[0x20];
7063 };
7064
7065 struct mlx5_ifc_create_tir_in_bits {
7066 u8 opcode[0x10];
7067 u8 uid[0x10];
7068
7069 u8 reserved_at_20[0x10];
7070 u8 op_mod[0x10];
7071
7072 u8 reserved_at_40[0xc0];
7073
7074 struct mlx5_ifc_tirc_bits ctx;
7075 };
7076
7077 struct mlx5_ifc_create_srq_out_bits {
7078 u8 status[0x8];
7079 u8 reserved_at_8[0x18];
7080
7081 u8 syndrome[0x20];
7082
7083 u8 reserved_at_40[0x8];
7084 u8 srqn[0x18];
7085
7086 u8 reserved_at_60[0x20];
7087 };
7088
7089 struct mlx5_ifc_create_srq_in_bits {
7090 u8 opcode[0x10];
7091 u8 uid[0x10];
7092
7093 u8 reserved_at_20[0x10];
7094 u8 op_mod[0x10];
7095
7096 u8 reserved_at_40[0x40];
7097
7098 struct mlx5_ifc_srqc_bits srq_context_entry;
7099
7100 u8 reserved_at_280[0x600];
7101
7102 u8 pas[0][0x40];
7103 };
7104
7105 struct mlx5_ifc_create_sq_out_bits {
7106 u8 status[0x8];
7107 u8 reserved_at_8[0x18];
7108
7109 u8 syndrome[0x20];
7110
7111 u8 reserved_at_40[0x8];
7112 u8 sqn[0x18];
7113
7114 u8 reserved_at_60[0x20];
7115 };
7116
7117 struct mlx5_ifc_create_sq_in_bits {
7118 u8 opcode[0x10];
7119 u8 uid[0x10];
7120
7121 u8 reserved_at_20[0x10];
7122 u8 op_mod[0x10];
7123
7124 u8 reserved_at_40[0xc0];
7125
7126 struct mlx5_ifc_sqc_bits ctx;
7127 };
7128
7129 struct mlx5_ifc_create_scheduling_element_out_bits {
7130 u8 status[0x8];
7131 u8 reserved_at_8[0x18];
7132
7133 u8 syndrome[0x20];
7134
7135 u8 reserved_at_40[0x40];
7136
7137 u8 scheduling_element_id[0x20];
7138
7139 u8 reserved_at_a0[0x160];
7140 };
7141
7142 struct mlx5_ifc_create_scheduling_element_in_bits {
7143 u8 opcode[0x10];
7144 u8 reserved_at_10[0x10];
7145
7146 u8 reserved_at_20[0x10];
7147 u8 op_mod[0x10];
7148
7149 u8 scheduling_hierarchy[0x8];
7150 u8 reserved_at_48[0x18];
7151
7152 u8 reserved_at_60[0xa0];
7153
7154 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7155
7156 u8 reserved_at_300[0x100];
7157 };
7158
7159 struct mlx5_ifc_create_rqt_out_bits {
7160 u8 status[0x8];
7161 u8 reserved_at_8[0x18];
7162
7163 u8 syndrome[0x20];
7164
7165 u8 reserved_at_40[0x8];
7166 u8 rqtn[0x18];
7167
7168 u8 reserved_at_60[0x20];
7169 };
7170
7171 struct mlx5_ifc_create_rqt_in_bits {
7172 u8 opcode[0x10];
7173 u8 uid[0x10];
7174
7175 u8 reserved_at_20[0x10];
7176 u8 op_mod[0x10];
7177
7178 u8 reserved_at_40[0xc0];
7179
7180 struct mlx5_ifc_rqtc_bits rqt_context;
7181 };
7182
7183 struct mlx5_ifc_create_rq_out_bits {
7184 u8 status[0x8];
7185 u8 reserved_at_8[0x18];
7186
7187 u8 syndrome[0x20];
7188
7189 u8 reserved_at_40[0x8];
7190 u8 rqn[0x18];
7191
7192 u8 reserved_at_60[0x20];
7193 };
7194
7195 struct mlx5_ifc_create_rq_in_bits {
7196 u8 opcode[0x10];
7197 u8 uid[0x10];
7198
7199 u8 reserved_at_20[0x10];
7200 u8 op_mod[0x10];
7201
7202 u8 reserved_at_40[0xc0];
7203
7204 struct mlx5_ifc_rqc_bits ctx;
7205 };
7206
7207 struct mlx5_ifc_create_rmp_out_bits {
7208 u8 status[0x8];
7209 u8 reserved_at_8[0x18];
7210
7211 u8 syndrome[0x20];
7212
7213 u8 reserved_at_40[0x8];
7214 u8 rmpn[0x18];
7215
7216 u8 reserved_at_60[0x20];
7217 };
7218
7219 struct mlx5_ifc_create_rmp_in_bits {
7220 u8 opcode[0x10];
7221 u8 uid[0x10];
7222
7223 u8 reserved_at_20[0x10];
7224 u8 op_mod[0x10];
7225
7226 u8 reserved_at_40[0xc0];
7227
7228 struct mlx5_ifc_rmpc_bits ctx;
7229 };
7230
7231 struct mlx5_ifc_create_qp_out_bits {
7232 u8 status[0x8];
7233 u8 reserved_at_8[0x18];
7234
7235 u8 syndrome[0x20];
7236
7237 u8 reserved_at_40[0x8];
7238 u8 qpn[0x18];
7239
7240 u8 reserved_at_60[0x20];
7241 };
7242
7243 struct mlx5_ifc_create_qp_in_bits {
7244 u8 opcode[0x10];
7245 u8 uid[0x10];
7246
7247 u8 reserved_at_20[0x10];
7248 u8 op_mod[0x10];
7249
7250 u8 reserved_at_40[0x40];
7251
7252 u8 opt_param_mask[0x20];
7253
7254 u8 reserved_at_a0[0x20];
7255
7256 struct mlx5_ifc_qpc_bits qpc;
7257
7258 u8 reserved_at_800[0x60];
7259
7260 u8 wq_umem_valid[0x1];
7261 u8 reserved_at_861[0x1f];
7262
7263 u8 pas[0][0x40];
7264 };
7265
7266 struct mlx5_ifc_create_psv_out_bits {
7267 u8 status[0x8];
7268 u8 reserved_at_8[0x18];
7269
7270 u8 syndrome[0x20];
7271
7272 u8 reserved_at_40[0x40];
7273
7274 u8 reserved_at_80[0x8];
7275 u8 psv0_index[0x18];
7276
7277 u8 reserved_at_a0[0x8];
7278 u8 psv1_index[0x18];
7279
7280 u8 reserved_at_c0[0x8];
7281 u8 psv2_index[0x18];
7282
7283 u8 reserved_at_e0[0x8];
7284 u8 psv3_index[0x18];
7285 };
7286
7287 struct mlx5_ifc_create_psv_in_bits {
7288 u8 opcode[0x10];
7289 u8 reserved_at_10[0x10];
7290
7291 u8 reserved_at_20[0x10];
7292 u8 op_mod[0x10];
7293
7294 u8 num_psv[0x4];
7295 u8 reserved_at_44[0x4];
7296 u8 pd[0x18];
7297
7298 u8 reserved_at_60[0x20];
7299 };
7300
7301 struct mlx5_ifc_create_mkey_out_bits {
7302 u8 status[0x8];
7303 u8 reserved_at_8[0x18];
7304
7305 u8 syndrome[0x20];
7306
7307 u8 reserved_at_40[0x8];
7308 u8 mkey_index[0x18];
7309
7310 u8 reserved_at_60[0x20];
7311 };
7312
7313 struct mlx5_ifc_create_mkey_in_bits {
7314 u8 opcode[0x10];
7315 u8 reserved_at_10[0x10];
7316
7317 u8 reserved_at_20[0x10];
7318 u8 op_mod[0x10];
7319
7320 u8 reserved_at_40[0x20];
7321
7322 u8 pg_access[0x1];
7323 u8 mkey_umem_valid[0x1];
7324 u8 reserved_at_62[0x1e];
7325
7326 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7327
7328 u8 reserved_at_280[0x80];
7329
7330 u8 translations_octword_actual_size[0x20];
7331
7332 u8 reserved_at_320[0x560];
7333
7334 u8 klm_pas_mtt[0][0x20];
7335 };
7336
7337 struct mlx5_ifc_create_flow_table_out_bits {
7338 u8 status[0x8];
7339 u8 reserved_at_8[0x18];
7340
7341 u8 syndrome[0x20];
7342
7343 u8 reserved_at_40[0x8];
7344 u8 table_id[0x18];
7345
7346 u8 reserved_at_60[0x20];
7347 };
7348
7349 struct mlx5_ifc_flow_table_context_bits {
7350 u8 reformat_en[0x1];
7351 u8 decap_en[0x1];
7352 u8 reserved_at_2[0x1];
7353 u8 termination_table[0x1];
7354 u8 table_miss_action[0x4];
7355 u8 level[0x8];
7356 u8 reserved_at_10[0x8];
7357 u8 log_size[0x8];
7358
7359 u8 reserved_at_20[0x8];
7360 u8 table_miss_id[0x18];
7361
7362 u8 reserved_at_40[0x8];
7363 u8 lag_master_next_table_id[0x18];
7364
7365 u8 reserved_at_60[0xe0];
7366 };
7367
7368 struct mlx5_ifc_create_flow_table_in_bits {
7369 u8 opcode[0x10];
7370 u8 reserved_at_10[0x10];
7371
7372 u8 reserved_at_20[0x10];
7373 u8 op_mod[0x10];
7374
7375 u8 other_vport[0x1];
7376 u8 reserved_at_41[0xf];
7377 u8 vport_number[0x10];
7378
7379 u8 reserved_at_60[0x20];
7380
7381 u8 table_type[0x8];
7382 u8 reserved_at_88[0x18];
7383
7384 u8 reserved_at_a0[0x20];
7385
7386 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7387 };
7388
7389 struct mlx5_ifc_create_flow_group_out_bits {
7390 u8 status[0x8];
7391 u8 reserved_at_8[0x18];
7392
7393 u8 syndrome[0x20];
7394
7395 u8 reserved_at_40[0x8];
7396 u8 group_id[0x18];
7397
7398 u8 reserved_at_60[0x20];
7399 };
7400
7401 enum {
7402 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7403 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7404 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7405 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7406 };
7407
7408 struct mlx5_ifc_create_flow_group_in_bits {
7409 u8 opcode[0x10];
7410 u8 reserved_at_10[0x10];
7411
7412 u8 reserved_at_20[0x10];
7413 u8 op_mod[0x10];
7414
7415 u8 other_vport[0x1];
7416 u8 reserved_at_41[0xf];
7417 u8 vport_number[0x10];
7418
7419 u8 reserved_at_60[0x20];
7420
7421 u8 table_type[0x8];
7422 u8 reserved_at_88[0x18];
7423
7424 u8 reserved_at_a0[0x8];
7425 u8 table_id[0x18];
7426
7427 u8 source_eswitch_owner_vhca_id_valid[0x1];
7428
7429 u8 reserved_at_c1[0x1f];
7430
7431 u8 start_flow_index[0x20];
7432
7433 u8 reserved_at_100[0x20];
7434
7435 u8 end_flow_index[0x20];
7436
7437 u8 reserved_at_140[0xa0];
7438
7439 u8 reserved_at_1e0[0x18];
7440 u8 match_criteria_enable[0x8];
7441
7442 struct mlx5_ifc_fte_match_param_bits match_criteria;
7443
7444 u8 reserved_at_1200[0xe00];
7445 };
7446
7447 struct mlx5_ifc_create_eq_out_bits {
7448 u8 status[0x8];
7449 u8 reserved_at_8[0x18];
7450
7451 u8 syndrome[0x20];
7452
7453 u8 reserved_at_40[0x18];
7454 u8 eq_number[0x8];
7455
7456 u8 reserved_at_60[0x20];
7457 };
7458
7459 struct mlx5_ifc_create_eq_in_bits {
7460 u8 opcode[0x10];
7461 u8 uid[0x10];
7462
7463 u8 reserved_at_20[0x10];
7464 u8 op_mod[0x10];
7465
7466 u8 reserved_at_40[0x40];
7467
7468 struct mlx5_ifc_eqc_bits eq_context_entry;
7469
7470 u8 reserved_at_280[0x40];
7471
7472 u8 event_bitmask[4][0x40];
7473
7474 u8 reserved_at_3c0[0x4c0];
7475
7476 u8 pas[0][0x40];
7477 };
7478
7479 struct mlx5_ifc_create_dct_out_bits {
7480 u8 status[0x8];
7481 u8 reserved_at_8[0x18];
7482
7483 u8 syndrome[0x20];
7484
7485 u8 reserved_at_40[0x8];
7486 u8 dctn[0x18];
7487
7488 u8 reserved_at_60[0x20];
7489 };
7490
7491 struct mlx5_ifc_create_dct_in_bits {
7492 u8 opcode[0x10];
7493 u8 uid[0x10];
7494
7495 u8 reserved_at_20[0x10];
7496 u8 op_mod[0x10];
7497
7498 u8 reserved_at_40[0x40];
7499
7500 struct mlx5_ifc_dctc_bits dct_context_entry;
7501
7502 u8 reserved_at_280[0x180];
7503 };
7504
7505 struct mlx5_ifc_create_cq_out_bits {
7506 u8 status[0x8];
7507 u8 reserved_at_8[0x18];
7508
7509 u8 syndrome[0x20];
7510
7511 u8 reserved_at_40[0x8];
7512 u8 cqn[0x18];
7513
7514 u8 reserved_at_60[0x20];
7515 };
7516
7517 struct mlx5_ifc_create_cq_in_bits {
7518 u8 opcode[0x10];
7519 u8 uid[0x10];
7520
7521 u8 reserved_at_20[0x10];
7522 u8 op_mod[0x10];
7523
7524 u8 reserved_at_40[0x40];
7525
7526 struct mlx5_ifc_cqc_bits cq_context;
7527
7528 u8 reserved_at_280[0x60];
7529
7530 u8 cq_umem_valid[0x1];
7531 u8 reserved_at_2e1[0x59f];
7532
7533 u8 pas[0][0x40];
7534 };
7535
7536 struct mlx5_ifc_config_int_moderation_out_bits {
7537 u8 status[0x8];
7538 u8 reserved_at_8[0x18];
7539
7540 u8 syndrome[0x20];
7541
7542 u8 reserved_at_40[0x4];
7543 u8 min_delay[0xc];
7544 u8 int_vector[0x10];
7545
7546 u8 reserved_at_60[0x20];
7547 };
7548
7549 enum {
7550 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7551 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7552 };
7553
7554 struct mlx5_ifc_config_int_moderation_in_bits {
7555 u8 opcode[0x10];
7556 u8 reserved_at_10[0x10];
7557
7558 u8 reserved_at_20[0x10];
7559 u8 op_mod[0x10];
7560
7561 u8 reserved_at_40[0x4];
7562 u8 min_delay[0xc];
7563 u8 int_vector[0x10];
7564
7565 u8 reserved_at_60[0x20];
7566 };
7567
7568 struct mlx5_ifc_attach_to_mcg_out_bits {
7569 u8 status[0x8];
7570 u8 reserved_at_8[0x18];
7571
7572 u8 syndrome[0x20];
7573
7574 u8 reserved_at_40[0x40];
7575 };
7576
7577 struct mlx5_ifc_attach_to_mcg_in_bits {
7578 u8 opcode[0x10];
7579 u8 uid[0x10];
7580
7581 u8 reserved_at_20[0x10];
7582 u8 op_mod[0x10];
7583
7584 u8 reserved_at_40[0x8];
7585 u8 qpn[0x18];
7586
7587 u8 reserved_at_60[0x20];
7588
7589 u8 multicast_gid[16][0x8];
7590 };
7591
7592 struct mlx5_ifc_arm_xrq_out_bits {
7593 u8 status[0x8];
7594 u8 reserved_at_8[0x18];
7595
7596 u8 syndrome[0x20];
7597
7598 u8 reserved_at_40[0x40];
7599 };
7600
7601 struct mlx5_ifc_arm_xrq_in_bits {
7602 u8 opcode[0x10];
7603 u8 reserved_at_10[0x10];
7604
7605 u8 reserved_at_20[0x10];
7606 u8 op_mod[0x10];
7607
7608 u8 reserved_at_40[0x8];
7609 u8 xrqn[0x18];
7610
7611 u8 reserved_at_60[0x10];
7612 u8 lwm[0x10];
7613 };
7614
7615 struct mlx5_ifc_arm_xrc_srq_out_bits {
7616 u8 status[0x8];
7617 u8 reserved_at_8[0x18];
7618
7619 u8 syndrome[0x20];
7620
7621 u8 reserved_at_40[0x40];
7622 };
7623
7624 enum {
7625 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7626 };
7627
7628 struct mlx5_ifc_arm_xrc_srq_in_bits {
7629 u8 opcode[0x10];
7630 u8 uid[0x10];
7631
7632 u8 reserved_at_20[0x10];
7633 u8 op_mod[0x10];
7634
7635 u8 reserved_at_40[0x8];
7636 u8 xrc_srqn[0x18];
7637
7638 u8 reserved_at_60[0x10];
7639 u8 lwm[0x10];
7640 };
7641
7642 struct mlx5_ifc_arm_rq_out_bits {
7643 u8 status[0x8];
7644 u8 reserved_at_8[0x18];
7645
7646 u8 syndrome[0x20];
7647
7648 u8 reserved_at_40[0x40];
7649 };
7650
7651 enum {
7652 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7653 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7654 };
7655
7656 struct mlx5_ifc_arm_rq_in_bits {
7657 u8 opcode[0x10];
7658 u8 uid[0x10];
7659
7660 u8 reserved_at_20[0x10];
7661 u8 op_mod[0x10];
7662
7663 u8 reserved_at_40[0x8];
7664 u8 srq_number[0x18];
7665
7666 u8 reserved_at_60[0x10];
7667 u8 lwm[0x10];
7668 };
7669
7670 struct mlx5_ifc_arm_dct_out_bits {
7671 u8 status[0x8];
7672 u8 reserved_at_8[0x18];
7673
7674 u8 syndrome[0x20];
7675
7676 u8 reserved_at_40[0x40];
7677 };
7678
7679 struct mlx5_ifc_arm_dct_in_bits {
7680 u8 opcode[0x10];
7681 u8 reserved_at_10[0x10];
7682
7683 u8 reserved_at_20[0x10];
7684 u8 op_mod[0x10];
7685
7686 u8 reserved_at_40[0x8];
7687 u8 dct_number[0x18];
7688
7689 u8 reserved_at_60[0x20];
7690 };
7691
7692 struct mlx5_ifc_alloc_xrcd_out_bits {
7693 u8 status[0x8];
7694 u8 reserved_at_8[0x18];
7695
7696 u8 syndrome[0x20];
7697
7698 u8 reserved_at_40[0x8];
7699 u8 xrcd[0x18];
7700
7701 u8 reserved_at_60[0x20];
7702 };
7703
7704 struct mlx5_ifc_alloc_xrcd_in_bits {
7705 u8 opcode[0x10];
7706 u8 uid[0x10];
7707
7708 u8 reserved_at_20[0x10];
7709 u8 op_mod[0x10];
7710
7711 u8 reserved_at_40[0x40];
7712 };
7713
7714 struct mlx5_ifc_alloc_uar_out_bits {
7715 u8 status[0x8];
7716 u8 reserved_at_8[0x18];
7717
7718 u8 syndrome[0x20];
7719
7720 u8 reserved_at_40[0x8];
7721 u8 uar[0x18];
7722
7723 u8 reserved_at_60[0x20];
7724 };
7725
7726 struct mlx5_ifc_alloc_uar_in_bits {
7727 u8 opcode[0x10];
7728 u8 reserved_at_10[0x10];
7729
7730 u8 reserved_at_20[0x10];
7731 u8 op_mod[0x10];
7732
7733 u8 reserved_at_40[0x40];
7734 };
7735
7736 struct mlx5_ifc_alloc_transport_domain_out_bits {
7737 u8 status[0x8];
7738 u8 reserved_at_8[0x18];
7739
7740 u8 syndrome[0x20];
7741
7742 u8 reserved_at_40[0x8];
7743 u8 transport_domain[0x18];
7744
7745 u8 reserved_at_60[0x20];
7746 };
7747
7748 struct mlx5_ifc_alloc_transport_domain_in_bits {
7749 u8 opcode[0x10];
7750 u8 uid[0x10];
7751
7752 u8 reserved_at_20[0x10];
7753 u8 op_mod[0x10];
7754
7755 u8 reserved_at_40[0x40];
7756 };
7757
7758 struct mlx5_ifc_alloc_q_counter_out_bits {
7759 u8 status[0x8];
7760 u8 reserved_at_8[0x18];
7761
7762 u8 syndrome[0x20];
7763
7764 u8 reserved_at_40[0x18];
7765 u8 counter_set_id[0x8];
7766
7767 u8 reserved_at_60[0x20];
7768 };
7769
7770 struct mlx5_ifc_alloc_q_counter_in_bits {
7771 u8 opcode[0x10];
7772 u8 uid[0x10];
7773
7774 u8 reserved_at_20[0x10];
7775 u8 op_mod[0x10];
7776
7777 u8 reserved_at_40[0x40];
7778 };
7779
7780 struct mlx5_ifc_alloc_pd_out_bits {
7781 u8 status[0x8];
7782 u8 reserved_at_8[0x18];
7783
7784 u8 syndrome[0x20];
7785
7786 u8 reserved_at_40[0x8];
7787 u8 pd[0x18];
7788
7789 u8 reserved_at_60[0x20];
7790 };
7791
7792 struct mlx5_ifc_alloc_pd_in_bits {
7793 u8 opcode[0x10];
7794 u8 uid[0x10];
7795
7796 u8 reserved_at_20[0x10];
7797 u8 op_mod[0x10];
7798
7799 u8 reserved_at_40[0x40];
7800 };
7801
7802 struct mlx5_ifc_alloc_flow_counter_out_bits {
7803 u8 status[0x8];
7804 u8 reserved_at_8[0x18];
7805
7806 u8 syndrome[0x20];
7807
7808 u8 flow_counter_id[0x20];
7809
7810 u8 reserved_at_60[0x20];
7811 };
7812
7813 struct mlx5_ifc_alloc_flow_counter_in_bits {
7814 u8 opcode[0x10];
7815 u8 reserved_at_10[0x10];
7816
7817 u8 reserved_at_20[0x10];
7818 u8 op_mod[0x10];
7819
7820 u8 reserved_at_40[0x40];
7821 };
7822
7823 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7824 u8 status[0x8];
7825 u8 reserved_at_8[0x18];
7826
7827 u8 syndrome[0x20];
7828
7829 u8 reserved_at_40[0x40];
7830 };
7831
7832 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7833 u8 opcode[0x10];
7834 u8 reserved_at_10[0x10];
7835
7836 u8 reserved_at_20[0x10];
7837 u8 op_mod[0x10];
7838
7839 u8 reserved_at_40[0x20];
7840
7841 u8 reserved_at_60[0x10];
7842 u8 vxlan_udp_port[0x10];
7843 };
7844
7845 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7846 u8 status[0x8];
7847 u8 reserved_at_8[0x18];
7848
7849 u8 syndrome[0x20];
7850
7851 u8 reserved_at_40[0x40];
7852 };
7853
7854 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7855 u8 opcode[0x10];
7856 u8 reserved_at_10[0x10];
7857
7858 u8 reserved_at_20[0x10];
7859 u8 op_mod[0x10];
7860
7861 u8 reserved_at_40[0x10];
7862 u8 rate_limit_index[0x10];
7863
7864 u8 reserved_at_60[0x20];
7865
7866 u8 rate_limit[0x20];
7867
7868 u8 burst_upper_bound[0x20];
7869
7870 u8 reserved_at_c0[0x10];
7871 u8 typical_packet_size[0x10];
7872
7873 u8 reserved_at_e0[0x120];
7874 };
7875
7876 struct mlx5_ifc_access_register_out_bits {
7877 u8 status[0x8];
7878 u8 reserved_at_8[0x18];
7879
7880 u8 syndrome[0x20];
7881
7882 u8 reserved_at_40[0x40];
7883
7884 u8 register_data[0][0x20];
7885 };
7886
7887 enum {
7888 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7889 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7890 };
7891
7892 struct mlx5_ifc_access_register_in_bits {
7893 u8 opcode[0x10];
7894 u8 reserved_at_10[0x10];
7895
7896 u8 reserved_at_20[0x10];
7897 u8 op_mod[0x10];
7898
7899 u8 reserved_at_40[0x10];
7900 u8 register_id[0x10];
7901
7902 u8 argument[0x20];
7903
7904 u8 register_data[0][0x20];
7905 };
7906
7907 struct mlx5_ifc_sltp_reg_bits {
7908 u8 status[0x4];
7909 u8 version[0x4];
7910 u8 local_port[0x8];
7911 u8 pnat[0x2];
7912 u8 reserved_at_12[0x2];
7913 u8 lane[0x4];
7914 u8 reserved_at_18[0x8];
7915
7916 u8 reserved_at_20[0x20];
7917
7918 u8 reserved_at_40[0x7];
7919 u8 polarity[0x1];
7920 u8 ob_tap0[0x8];
7921 u8 ob_tap1[0x8];
7922 u8 ob_tap2[0x8];
7923
7924 u8 reserved_at_60[0xc];
7925 u8 ob_preemp_mode[0x4];
7926 u8 ob_reg[0x8];
7927 u8 ob_bias[0x8];
7928
7929 u8 reserved_at_80[0x20];
7930 };
7931
7932 struct mlx5_ifc_slrg_reg_bits {
7933 u8 status[0x4];
7934 u8 version[0x4];
7935 u8 local_port[0x8];
7936 u8 pnat[0x2];
7937 u8 reserved_at_12[0x2];
7938 u8 lane[0x4];
7939 u8 reserved_at_18[0x8];
7940
7941 u8 time_to_link_up[0x10];
7942 u8 reserved_at_30[0xc];
7943 u8 grade_lane_speed[0x4];
7944
7945 u8 grade_version[0x8];
7946 u8 grade[0x18];
7947
7948 u8 reserved_at_60[0x4];
7949 u8 height_grade_type[0x4];
7950 u8 height_grade[0x18];
7951
7952 u8 height_dz[0x10];
7953 u8 height_dv[0x10];
7954
7955 u8 reserved_at_a0[0x10];
7956 u8 height_sigma[0x10];
7957
7958 u8 reserved_at_c0[0x20];
7959
7960 u8 reserved_at_e0[0x4];
7961 u8 phase_grade_type[0x4];
7962 u8 phase_grade[0x18];
7963
7964 u8 reserved_at_100[0x8];
7965 u8 phase_eo_pos[0x8];
7966 u8 reserved_at_110[0x8];
7967 u8 phase_eo_neg[0x8];
7968
7969 u8 ffe_set_tested[0x10];
7970 u8 test_errors_per_lane[0x10];
7971 };
7972
7973 struct mlx5_ifc_pvlc_reg_bits {
7974 u8 reserved_at_0[0x8];
7975 u8 local_port[0x8];
7976 u8 reserved_at_10[0x10];
7977
7978 u8 reserved_at_20[0x1c];
7979 u8 vl_hw_cap[0x4];
7980
7981 u8 reserved_at_40[0x1c];
7982 u8 vl_admin[0x4];
7983
7984 u8 reserved_at_60[0x1c];
7985 u8 vl_operational[0x4];
7986 };
7987
7988 struct mlx5_ifc_pude_reg_bits {
7989 u8 swid[0x8];
7990 u8 local_port[0x8];
7991 u8 reserved_at_10[0x4];
7992 u8 admin_status[0x4];
7993 u8 reserved_at_18[0x4];
7994 u8 oper_status[0x4];
7995
7996 u8 reserved_at_20[0x60];
7997 };
7998
7999 struct mlx5_ifc_ptys_reg_bits {
8000 u8 reserved_at_0[0x1];
8001 u8 an_disable_admin[0x1];
8002 u8 an_disable_cap[0x1];
8003 u8 reserved_at_3[0x5];
8004 u8 local_port[0x8];
8005 u8 reserved_at_10[0xd];
8006 u8 proto_mask[0x3];
8007
8008 u8 an_status[0x4];
8009 u8 reserved_at_24[0x1c];
8010
8011 u8 ext_eth_proto_capability[0x20];
8012
8013 u8 eth_proto_capability[0x20];
8014
8015 u8 ib_link_width_capability[0x10];
8016 u8 ib_proto_capability[0x10];
8017
8018 u8 ext_eth_proto_admin[0x20];
8019
8020 u8 eth_proto_admin[0x20];
8021
8022 u8 ib_link_width_admin[0x10];
8023 u8 ib_proto_admin[0x10];
8024
8025 u8 ext_eth_proto_oper[0x20];
8026
8027 u8 eth_proto_oper[0x20];
8028
8029 u8 ib_link_width_oper[0x10];
8030 u8 ib_proto_oper[0x10];
8031
8032 u8 reserved_at_160[0x1c];
8033 u8 connector_type[0x4];
8034
8035 u8 eth_proto_lp_advertise[0x20];
8036
8037 u8 reserved_at_1a0[0x60];
8038 };
8039
8040 struct mlx5_ifc_mlcr_reg_bits {
8041 u8 reserved_at_0[0x8];
8042 u8 local_port[0x8];
8043 u8 reserved_at_10[0x20];
8044
8045 u8 beacon_duration[0x10];
8046 u8 reserved_at_40[0x10];
8047
8048 u8 beacon_remain[0x10];
8049 };
8050
8051 struct mlx5_ifc_ptas_reg_bits {
8052 u8 reserved_at_0[0x20];
8053
8054 u8 algorithm_options[0x10];
8055 u8 reserved_at_30[0x4];
8056 u8 repetitions_mode[0x4];
8057 u8 num_of_repetitions[0x8];
8058
8059 u8 grade_version[0x8];
8060 u8 height_grade_type[0x4];
8061 u8 phase_grade_type[0x4];
8062 u8 height_grade_weight[0x8];
8063 u8 phase_grade_weight[0x8];
8064
8065 u8 gisim_measure_bits[0x10];
8066 u8 adaptive_tap_measure_bits[0x10];
8067
8068 u8 ber_bath_high_error_threshold[0x10];
8069 u8 ber_bath_mid_error_threshold[0x10];
8070
8071 u8 ber_bath_low_error_threshold[0x10];
8072 u8 one_ratio_high_threshold[0x10];
8073
8074 u8 one_ratio_high_mid_threshold[0x10];
8075 u8 one_ratio_low_mid_threshold[0x10];
8076
8077 u8 one_ratio_low_threshold[0x10];
8078 u8 ndeo_error_threshold[0x10];
8079
8080 u8 mixer_offset_step_size[0x10];
8081 u8 reserved_at_110[0x8];
8082 u8 mix90_phase_for_voltage_bath[0x8];
8083
8084 u8 mixer_offset_start[0x10];
8085 u8 mixer_offset_end[0x10];
8086
8087 u8 reserved_at_140[0x15];
8088 u8 ber_test_time[0xb];
8089 };
8090
8091 struct mlx5_ifc_pspa_reg_bits {
8092 u8 swid[0x8];
8093 u8 local_port[0x8];
8094 u8 sub_port[0x8];
8095 u8 reserved_at_18[0x8];
8096
8097 u8 reserved_at_20[0x20];
8098 };
8099
8100 struct mlx5_ifc_pqdr_reg_bits {
8101 u8 reserved_at_0[0x8];
8102 u8 local_port[0x8];
8103 u8 reserved_at_10[0x5];
8104 u8 prio[0x3];
8105 u8 reserved_at_18[0x6];
8106 u8 mode[0x2];
8107
8108 u8 reserved_at_20[0x20];
8109
8110 u8 reserved_at_40[0x10];
8111 u8 min_threshold[0x10];
8112
8113 u8 reserved_at_60[0x10];
8114 u8 max_threshold[0x10];
8115
8116 u8 reserved_at_80[0x10];
8117 u8 mark_probability_denominator[0x10];
8118
8119 u8 reserved_at_a0[0x60];
8120 };
8121
8122 struct mlx5_ifc_ppsc_reg_bits {
8123 u8 reserved_at_0[0x8];
8124 u8 local_port[0x8];
8125 u8 reserved_at_10[0x10];
8126
8127 u8 reserved_at_20[0x60];
8128
8129 u8 reserved_at_80[0x1c];
8130 u8 wrps_admin[0x4];
8131
8132 u8 reserved_at_a0[0x1c];
8133 u8 wrps_status[0x4];
8134
8135 u8 reserved_at_c0[0x8];
8136 u8 up_threshold[0x8];
8137 u8 reserved_at_d0[0x8];
8138 u8 down_threshold[0x8];
8139
8140 u8 reserved_at_e0[0x20];
8141
8142 u8 reserved_at_100[0x1c];
8143 u8 srps_admin[0x4];
8144
8145 u8 reserved_at_120[0x1c];
8146 u8 srps_status[0x4];
8147
8148 u8 reserved_at_140[0x40];
8149 };
8150
8151 struct mlx5_ifc_pplr_reg_bits {
8152 u8 reserved_at_0[0x8];
8153 u8 local_port[0x8];
8154 u8 reserved_at_10[0x10];
8155
8156 u8 reserved_at_20[0x8];
8157 u8 lb_cap[0x8];
8158 u8 reserved_at_30[0x8];
8159 u8 lb_en[0x8];
8160 };
8161
8162 struct mlx5_ifc_pplm_reg_bits {
8163 u8 reserved_at_0[0x8];
8164 u8 local_port[0x8];
8165 u8 reserved_at_10[0x10];
8166
8167 u8 reserved_at_20[0x20];
8168
8169 u8 port_profile_mode[0x8];
8170 u8 static_port_profile[0x8];
8171 u8 active_port_profile[0x8];
8172 u8 reserved_at_58[0x8];
8173
8174 u8 retransmission_active[0x8];
8175 u8 fec_mode_active[0x18];
8176
8177 u8 rs_fec_correction_bypass_cap[0x4];
8178 u8 reserved_at_84[0x8];
8179 u8 fec_override_cap_56g[0x4];
8180 u8 fec_override_cap_100g[0x4];
8181 u8 fec_override_cap_50g[0x4];
8182 u8 fec_override_cap_25g[0x4];
8183 u8 fec_override_cap_10g_40g[0x4];
8184
8185 u8 rs_fec_correction_bypass_admin[0x4];
8186 u8 reserved_at_a4[0x8];
8187 u8 fec_override_admin_56g[0x4];
8188 u8 fec_override_admin_100g[0x4];
8189 u8 fec_override_admin_50g[0x4];
8190 u8 fec_override_admin_25g[0x4];
8191 u8 fec_override_admin_10g_40g[0x4];
8192 };
8193
8194 struct mlx5_ifc_ppcnt_reg_bits {
8195 u8 swid[0x8];
8196 u8 local_port[0x8];
8197 u8 pnat[0x2];
8198 u8 reserved_at_12[0x8];
8199 u8 grp[0x6];
8200
8201 u8 clr[0x1];
8202 u8 reserved_at_21[0x1c];
8203 u8 prio_tc[0x3];
8204
8205 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8206 };
8207
8208 struct mlx5_ifc_mpein_reg_bits {
8209 u8 reserved_at_0[0x2];
8210 u8 depth[0x6];
8211 u8 pcie_index[0x8];
8212 u8 node[0x8];
8213 u8 reserved_at_18[0x8];
8214
8215 u8 capability_mask[0x20];
8216
8217 u8 reserved_at_40[0x8];
8218 u8 link_width_enabled[0x8];
8219 u8 link_speed_enabled[0x10];
8220
8221 u8 lane0_physical_position[0x8];
8222 u8 link_width_active[0x8];
8223 u8 link_speed_active[0x10];
8224
8225 u8 num_of_pfs[0x10];
8226 u8 num_of_vfs[0x10];
8227
8228 u8 bdf0[0x10];
8229 u8 reserved_at_b0[0x10];
8230
8231 u8 max_read_request_size[0x4];
8232 u8 max_payload_size[0x4];
8233 u8 reserved_at_c8[0x5];
8234 u8 pwr_status[0x3];
8235 u8 port_type[0x4];
8236 u8 reserved_at_d4[0xb];
8237 u8 lane_reversal[0x1];
8238
8239 u8 reserved_at_e0[0x14];
8240 u8 pci_power[0xc];
8241
8242 u8 reserved_at_100[0x20];
8243
8244 u8 device_status[0x10];
8245 u8 port_state[0x8];
8246 u8 reserved_at_138[0x8];
8247
8248 u8 reserved_at_140[0x10];
8249 u8 receiver_detect_result[0x10];
8250
8251 u8 reserved_at_160[0x20];
8252 };
8253
8254 struct mlx5_ifc_mpcnt_reg_bits {
8255 u8 reserved_at_0[0x8];
8256 u8 pcie_index[0x8];
8257 u8 reserved_at_10[0xa];
8258 u8 grp[0x6];
8259
8260 u8 clr[0x1];
8261 u8 reserved_at_21[0x1f];
8262
8263 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8264 };
8265
8266 struct mlx5_ifc_ppad_reg_bits {
8267 u8 reserved_at_0[0x3];
8268 u8 single_mac[0x1];
8269 u8 reserved_at_4[0x4];
8270 u8 local_port[0x8];
8271 u8 mac_47_32[0x10];
8272
8273 u8 mac_31_0[0x20];
8274
8275 u8 reserved_at_40[0x40];
8276 };
8277
8278 struct mlx5_ifc_pmtu_reg_bits {
8279 u8 reserved_at_0[0x8];
8280 u8 local_port[0x8];
8281 u8 reserved_at_10[0x10];
8282
8283 u8 max_mtu[0x10];
8284 u8 reserved_at_30[0x10];
8285
8286 u8 admin_mtu[0x10];
8287 u8 reserved_at_50[0x10];
8288
8289 u8 oper_mtu[0x10];
8290 u8 reserved_at_70[0x10];
8291 };
8292
8293 struct mlx5_ifc_pmpr_reg_bits {
8294 u8 reserved_at_0[0x8];
8295 u8 module[0x8];
8296 u8 reserved_at_10[0x10];
8297
8298 u8 reserved_at_20[0x18];
8299 u8 attenuation_5g[0x8];
8300
8301 u8 reserved_at_40[0x18];
8302 u8 attenuation_7g[0x8];
8303
8304 u8 reserved_at_60[0x18];
8305 u8 attenuation_12g[0x8];
8306 };
8307
8308 struct mlx5_ifc_pmpe_reg_bits {
8309 u8 reserved_at_0[0x8];
8310 u8 module[0x8];
8311 u8 reserved_at_10[0xc];
8312 u8 module_status[0x4];
8313
8314 u8 reserved_at_20[0x60];
8315 };
8316
8317 struct mlx5_ifc_pmpc_reg_bits {
8318 u8 module_state_updated[32][0x8];
8319 };
8320
8321 struct mlx5_ifc_pmlpn_reg_bits {
8322 u8 reserved_at_0[0x4];
8323 u8 mlpn_status[0x4];
8324 u8 local_port[0x8];
8325 u8 reserved_at_10[0x10];
8326
8327 u8 e[0x1];
8328 u8 reserved_at_21[0x1f];
8329 };
8330
8331 struct mlx5_ifc_pmlp_reg_bits {
8332 u8 rxtx[0x1];
8333 u8 reserved_at_1[0x7];
8334 u8 local_port[0x8];
8335 u8 reserved_at_10[0x8];
8336 u8 width[0x8];
8337
8338 u8 lane0_module_mapping[0x20];
8339
8340 u8 lane1_module_mapping[0x20];
8341
8342 u8 lane2_module_mapping[0x20];
8343
8344 u8 lane3_module_mapping[0x20];
8345
8346 u8 reserved_at_a0[0x160];
8347 };
8348
8349 struct mlx5_ifc_pmaos_reg_bits {
8350 u8 reserved_at_0[0x8];
8351 u8 module[0x8];
8352 u8 reserved_at_10[0x4];
8353 u8 admin_status[0x4];
8354 u8 reserved_at_18[0x4];
8355 u8 oper_status[0x4];
8356
8357 u8 ase[0x1];
8358 u8 ee[0x1];
8359 u8 reserved_at_22[0x1c];
8360 u8 e[0x2];
8361
8362 u8 reserved_at_40[0x40];
8363 };
8364
8365 struct mlx5_ifc_plpc_reg_bits {
8366 u8 reserved_at_0[0x4];
8367 u8 profile_id[0xc];
8368 u8 reserved_at_10[0x4];
8369 u8 proto_mask[0x4];
8370 u8 reserved_at_18[0x8];
8371
8372 u8 reserved_at_20[0x10];
8373 u8 lane_speed[0x10];
8374
8375 u8 reserved_at_40[0x17];
8376 u8 lpbf[0x1];
8377 u8 fec_mode_policy[0x8];
8378
8379 u8 retransmission_capability[0x8];
8380 u8 fec_mode_capability[0x18];
8381
8382 u8 retransmission_support_admin[0x8];
8383 u8 fec_mode_support_admin[0x18];
8384
8385 u8 retransmission_request_admin[0x8];
8386 u8 fec_mode_request_admin[0x18];
8387
8388 u8 reserved_at_c0[0x80];
8389 };
8390
8391 struct mlx5_ifc_plib_reg_bits {
8392 u8 reserved_at_0[0x8];
8393 u8 local_port[0x8];
8394 u8 reserved_at_10[0x8];
8395 u8 ib_port[0x8];
8396
8397 u8 reserved_at_20[0x60];
8398 };
8399
8400 struct mlx5_ifc_plbf_reg_bits {
8401 u8 reserved_at_0[0x8];
8402 u8 local_port[0x8];
8403 u8 reserved_at_10[0xd];
8404 u8 lbf_mode[0x3];
8405
8406 u8 reserved_at_20[0x20];
8407 };
8408
8409 struct mlx5_ifc_pipg_reg_bits {
8410 u8 reserved_at_0[0x8];
8411 u8 local_port[0x8];
8412 u8 reserved_at_10[0x10];
8413
8414 u8 dic[0x1];
8415 u8 reserved_at_21[0x19];
8416 u8 ipg[0x4];
8417 u8 reserved_at_3e[0x2];
8418 };
8419
8420 struct mlx5_ifc_pifr_reg_bits {
8421 u8 reserved_at_0[0x8];
8422 u8 local_port[0x8];
8423 u8 reserved_at_10[0x10];
8424
8425 u8 reserved_at_20[0xe0];
8426
8427 u8 port_filter[8][0x20];
8428
8429 u8 port_filter_update_en[8][0x20];
8430 };
8431
8432 struct mlx5_ifc_pfcc_reg_bits {
8433 u8 reserved_at_0[0x8];
8434 u8 local_port[0x8];
8435 u8 reserved_at_10[0xb];
8436 u8 ppan_mask_n[0x1];
8437 u8 minor_stall_mask[0x1];
8438 u8 critical_stall_mask[0x1];
8439 u8 reserved_at_1e[0x2];
8440
8441 u8 ppan[0x4];
8442 u8 reserved_at_24[0x4];
8443 u8 prio_mask_tx[0x8];
8444 u8 reserved_at_30[0x8];
8445 u8 prio_mask_rx[0x8];
8446
8447 u8 pptx[0x1];
8448 u8 aptx[0x1];
8449 u8 pptx_mask_n[0x1];
8450 u8 reserved_at_43[0x5];
8451 u8 pfctx[0x8];
8452 u8 reserved_at_50[0x10];
8453
8454 u8 pprx[0x1];
8455 u8 aprx[0x1];
8456 u8 pprx_mask_n[0x1];
8457 u8 reserved_at_63[0x5];
8458 u8 pfcrx[0x8];
8459 u8 reserved_at_70[0x10];
8460
8461 u8 device_stall_minor_watermark[0x10];
8462 u8 device_stall_critical_watermark[0x10];
8463
8464 u8 reserved_at_a0[0x60];
8465 };
8466
8467 struct mlx5_ifc_pelc_reg_bits {
8468 u8 op[0x4];
8469 u8 reserved_at_4[0x4];
8470 u8 local_port[0x8];
8471 u8 reserved_at_10[0x10];
8472
8473 u8 op_admin[0x8];
8474 u8 op_capability[0x8];
8475 u8 op_request[0x8];
8476 u8 op_active[0x8];
8477
8478 u8 admin[0x40];
8479
8480 u8 capability[0x40];
8481
8482 u8 request[0x40];
8483
8484 u8 active[0x40];
8485
8486 u8 reserved_at_140[0x80];
8487 };
8488
8489 struct mlx5_ifc_peir_reg_bits {
8490 u8 reserved_at_0[0x8];
8491 u8 local_port[0x8];
8492 u8 reserved_at_10[0x10];
8493
8494 u8 reserved_at_20[0xc];
8495 u8 error_count[0x4];
8496 u8 reserved_at_30[0x10];
8497
8498 u8 reserved_at_40[0xc];
8499 u8 lane[0x4];
8500 u8 reserved_at_50[0x8];
8501 u8 error_type[0x8];
8502 };
8503
8504 struct mlx5_ifc_mpegc_reg_bits {
8505 u8 reserved_at_0[0x30];
8506 u8 field_select[0x10];
8507
8508 u8 tx_overflow_sense[0x1];
8509 u8 mark_cqe[0x1];
8510 u8 mark_cnp[0x1];
8511 u8 reserved_at_43[0x1b];
8512 u8 tx_lossy_overflow_oper[0x2];
8513
8514 u8 reserved_at_60[0x100];
8515 };
8516
8517 struct mlx5_ifc_pcam_enhanced_features_bits {
8518 u8 reserved_at_0[0x6d];
8519 u8 rx_icrc_encapsulated_counter[0x1];
8520 u8 reserved_at_6e[0x4];
8521 u8 ptys_extended_ethernet[0x1];
8522 u8 reserved_at_73[0x3];
8523 u8 pfcc_mask[0x1];
8524 u8 reserved_at_77[0x3];
8525 u8 per_lane_error_counters[0x1];
8526 u8 rx_buffer_fullness_counters[0x1];
8527 u8 ptys_connector_type[0x1];
8528 u8 reserved_at_7d[0x1];
8529 u8 ppcnt_discard_group[0x1];
8530 u8 ppcnt_statistical_group[0x1];
8531 };
8532
8533 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8534 u8 port_access_reg_cap_mask_127_to_96[0x20];
8535 u8 port_access_reg_cap_mask_95_to_64[0x20];
8536
8537 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8538 u8 pplm[0x1];
8539 u8 port_access_reg_cap_mask_34_to_32[0x3];
8540
8541 u8 port_access_reg_cap_mask_31_to_13[0x13];
8542 u8 pbmc[0x1];
8543 u8 pptb[0x1];
8544 u8 port_access_reg_cap_mask_10_to_09[0x2];
8545 u8 ppcnt[0x1];
8546 u8 port_access_reg_cap_mask_07_to_00[0x8];
8547 };
8548
8549 struct mlx5_ifc_pcam_reg_bits {
8550 u8 reserved_at_0[0x8];
8551 u8 feature_group[0x8];
8552 u8 reserved_at_10[0x8];
8553 u8 access_reg_group[0x8];
8554
8555 u8 reserved_at_20[0x20];
8556
8557 union {
8558 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8559 u8 reserved_at_0[0x80];
8560 } port_access_reg_cap_mask;
8561
8562 u8 reserved_at_c0[0x80];
8563
8564 union {
8565 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8566 u8 reserved_at_0[0x80];
8567 } feature_cap_mask;
8568
8569 u8 reserved_at_1c0[0xc0];
8570 };
8571
8572 struct mlx5_ifc_mcam_enhanced_features_bits {
8573 u8 reserved_at_0[0x6e];
8574 u8 pci_status_and_power[0x1];
8575 u8 reserved_at_6f[0x5];
8576 u8 mark_tx_action_cnp[0x1];
8577 u8 mark_tx_action_cqe[0x1];
8578 u8 dynamic_tx_overflow[0x1];
8579 u8 reserved_at_77[0x4];
8580 u8 pcie_outbound_stalled[0x1];
8581 u8 tx_overflow_buffer_pkt[0x1];
8582 u8 mtpps_enh_out_per_adj[0x1];
8583 u8 mtpps_fs[0x1];
8584 u8 pcie_performance_group[0x1];
8585 };
8586
8587 struct mlx5_ifc_mcam_access_reg_bits {
8588 u8 reserved_at_0[0x1c];
8589 u8 mcda[0x1];
8590 u8 mcc[0x1];
8591 u8 mcqi[0x1];
8592 u8 mcqs[0x1];
8593
8594 u8 regs_95_to_87[0x9];
8595 u8 mpegc[0x1];
8596 u8 regs_85_to_68[0x12];
8597 u8 tracer_registers[0x4];
8598
8599 u8 regs_63_to_32[0x20];
8600 u8 regs_31_to_0[0x20];
8601 };
8602
8603 struct mlx5_ifc_mcam_reg_bits {
8604 u8 reserved_at_0[0x8];
8605 u8 feature_group[0x8];
8606 u8 reserved_at_10[0x8];
8607 u8 access_reg_group[0x8];
8608
8609 u8 reserved_at_20[0x20];
8610
8611 union {
8612 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8613 u8 reserved_at_0[0x80];
8614 } mng_access_reg_cap_mask;
8615
8616 u8 reserved_at_c0[0x80];
8617
8618 union {
8619 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8620 u8 reserved_at_0[0x80];
8621 } mng_feature_cap_mask;
8622
8623 u8 reserved_at_1c0[0x80];
8624 };
8625
8626 struct mlx5_ifc_qcam_access_reg_cap_mask {
8627 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8628 u8 qpdpm[0x1];
8629 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8630 u8 qdpm[0x1];
8631 u8 qpts[0x1];
8632 u8 qcap[0x1];
8633 u8 qcam_access_reg_cap_mask_0[0x1];
8634 };
8635
8636 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8637 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8638 u8 qpts_trust_both[0x1];
8639 };
8640
8641 struct mlx5_ifc_qcam_reg_bits {
8642 u8 reserved_at_0[0x8];
8643 u8 feature_group[0x8];
8644 u8 reserved_at_10[0x8];
8645 u8 access_reg_group[0x8];
8646 u8 reserved_at_20[0x20];
8647
8648 union {
8649 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8650 u8 reserved_at_0[0x80];
8651 } qos_access_reg_cap_mask;
8652
8653 u8 reserved_at_c0[0x80];
8654
8655 union {
8656 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8657 u8 reserved_at_0[0x80];
8658 } qos_feature_cap_mask;
8659
8660 u8 reserved_at_1c0[0x80];
8661 };
8662
8663 struct mlx5_ifc_core_dump_reg_bits {
8664 u8 reserved_at_0[0x18];
8665 u8 core_dump_type[0x8];
8666
8667 u8 reserved_at_20[0x30];
8668 u8 vhca_id[0x10];
8669
8670 u8 reserved_at_60[0x8];
8671 u8 qpn[0x18];
8672 u8 reserved_at_80[0x180];
8673 };
8674
8675 struct mlx5_ifc_pcap_reg_bits {
8676 u8 reserved_at_0[0x8];
8677 u8 local_port[0x8];
8678 u8 reserved_at_10[0x10];
8679
8680 u8 port_capability_mask[4][0x20];
8681 };
8682
8683 struct mlx5_ifc_paos_reg_bits {
8684 u8 swid[0x8];
8685 u8 local_port[0x8];
8686 u8 reserved_at_10[0x4];
8687 u8 admin_status[0x4];
8688 u8 reserved_at_18[0x4];
8689 u8 oper_status[0x4];
8690
8691 u8 ase[0x1];
8692 u8 ee[0x1];
8693 u8 reserved_at_22[0x1c];
8694 u8 e[0x2];
8695
8696 u8 reserved_at_40[0x40];
8697 };
8698
8699 struct mlx5_ifc_pamp_reg_bits {
8700 u8 reserved_at_0[0x8];
8701 u8 opamp_group[0x8];
8702 u8 reserved_at_10[0xc];
8703 u8 opamp_group_type[0x4];
8704
8705 u8 start_index[0x10];
8706 u8 reserved_at_30[0x4];
8707 u8 num_of_indices[0xc];
8708
8709 u8 index_data[18][0x10];
8710 };
8711
8712 struct mlx5_ifc_pcmr_reg_bits {
8713 u8 reserved_at_0[0x8];
8714 u8 local_port[0x8];
8715 u8 reserved_at_10[0x10];
8716 u8 entropy_force_cap[0x1];
8717 u8 entropy_calc_cap[0x1];
8718 u8 entropy_gre_calc_cap[0x1];
8719 u8 reserved_at_23[0x1b];
8720 u8 fcs_cap[0x1];
8721 u8 reserved_at_3f[0x1];
8722 u8 entropy_force[0x1];
8723 u8 entropy_calc[0x1];
8724 u8 entropy_gre_calc[0x1];
8725 u8 reserved_at_43[0x1b];
8726 u8 fcs_chk[0x1];
8727 u8 reserved_at_5f[0x1];
8728 };
8729
8730 struct mlx5_ifc_lane_2_module_mapping_bits {
8731 u8 reserved_at_0[0x6];
8732 u8 rx_lane[0x2];
8733 u8 reserved_at_8[0x6];
8734 u8 tx_lane[0x2];
8735 u8 reserved_at_10[0x8];
8736 u8 module[0x8];
8737 };
8738
8739 struct mlx5_ifc_bufferx_reg_bits {
8740 u8 reserved_at_0[0x6];
8741 u8 lossy[0x1];
8742 u8 epsb[0x1];
8743 u8 reserved_at_8[0xc];
8744 u8 size[0xc];
8745
8746 u8 xoff_threshold[0x10];
8747 u8 xon_threshold[0x10];
8748 };
8749
8750 struct mlx5_ifc_set_node_in_bits {
8751 u8 node_description[64][0x8];
8752 };
8753
8754 struct mlx5_ifc_register_power_settings_bits {
8755 u8 reserved_at_0[0x18];
8756 u8 power_settings_level[0x8];
8757
8758 u8 reserved_at_20[0x60];
8759 };
8760
8761 struct mlx5_ifc_register_host_endianness_bits {
8762 u8 he[0x1];
8763 u8 reserved_at_1[0x1f];
8764
8765 u8 reserved_at_20[0x60];
8766 };
8767
8768 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8769 u8 reserved_at_0[0x20];
8770
8771 u8 mkey[0x20];
8772
8773 u8 addressh_63_32[0x20];
8774
8775 u8 addressl_31_0[0x20];
8776 };
8777
8778 struct mlx5_ifc_ud_adrs_vector_bits {
8779 u8 dc_key[0x40];
8780
8781 u8 ext[0x1];
8782 u8 reserved_at_41[0x7];
8783 u8 destination_qp_dct[0x18];
8784
8785 u8 static_rate[0x4];
8786 u8 sl_eth_prio[0x4];
8787 u8 fl[0x1];
8788 u8 mlid[0x7];
8789 u8 rlid_udp_sport[0x10];
8790
8791 u8 reserved_at_80[0x20];
8792
8793 u8 rmac_47_16[0x20];
8794
8795 u8 rmac_15_0[0x10];
8796 u8 tclass[0x8];
8797 u8 hop_limit[0x8];
8798
8799 u8 reserved_at_e0[0x1];
8800 u8 grh[0x1];
8801 u8 reserved_at_e2[0x2];
8802 u8 src_addr_index[0x8];
8803 u8 flow_label[0x14];
8804
8805 u8 rgid_rip[16][0x8];
8806 };
8807
8808 struct mlx5_ifc_pages_req_event_bits {
8809 u8 reserved_at_0[0x10];
8810 u8 function_id[0x10];
8811
8812 u8 num_pages[0x20];
8813
8814 u8 reserved_at_40[0xa0];
8815 };
8816
8817 struct mlx5_ifc_eqe_bits {
8818 u8 reserved_at_0[0x8];
8819 u8 event_type[0x8];
8820 u8 reserved_at_10[0x8];
8821 u8 event_sub_type[0x8];
8822
8823 u8 reserved_at_20[0xe0];
8824
8825 union mlx5_ifc_event_auto_bits event_data;
8826
8827 u8 reserved_at_1e0[0x10];
8828 u8 signature[0x8];
8829 u8 reserved_at_1f8[0x7];
8830 u8 owner[0x1];
8831 };
8832
8833 enum {
8834 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8835 };
8836
8837 struct mlx5_ifc_cmd_queue_entry_bits {
8838 u8 type[0x8];
8839 u8 reserved_at_8[0x18];
8840
8841 u8 input_length[0x20];
8842
8843 u8 input_mailbox_pointer_63_32[0x20];
8844
8845 u8 input_mailbox_pointer_31_9[0x17];
8846 u8 reserved_at_77[0x9];
8847
8848 u8 command_input_inline_data[16][0x8];
8849
8850 u8 command_output_inline_data[16][0x8];
8851
8852 u8 output_mailbox_pointer_63_32[0x20];
8853
8854 u8 output_mailbox_pointer_31_9[0x17];
8855 u8 reserved_at_1b7[0x9];
8856
8857 u8 output_length[0x20];
8858
8859 u8 token[0x8];
8860 u8 signature[0x8];
8861 u8 reserved_at_1f0[0x8];
8862 u8 status[0x7];
8863 u8 ownership[0x1];
8864 };
8865
8866 struct mlx5_ifc_cmd_out_bits {
8867 u8 status[0x8];
8868 u8 reserved_at_8[0x18];
8869
8870 u8 syndrome[0x20];
8871
8872 u8 command_output[0x20];
8873 };
8874
8875 struct mlx5_ifc_cmd_in_bits {
8876 u8 opcode[0x10];
8877 u8 reserved_at_10[0x10];
8878
8879 u8 reserved_at_20[0x10];
8880 u8 op_mod[0x10];
8881
8882 u8 command[0][0x20];
8883 };
8884
8885 struct mlx5_ifc_cmd_if_box_bits {
8886 u8 mailbox_data[512][0x8];
8887
8888 u8 reserved_at_1000[0x180];
8889
8890 u8 next_pointer_63_32[0x20];
8891
8892 u8 next_pointer_31_10[0x16];
8893 u8 reserved_at_11b6[0xa];
8894
8895 u8 block_number[0x20];
8896
8897 u8 reserved_at_11e0[0x8];
8898 u8 token[0x8];
8899 u8 ctrl_signature[0x8];
8900 u8 signature[0x8];
8901 };
8902
8903 struct mlx5_ifc_mtt_bits {
8904 u8 ptag_63_32[0x20];
8905
8906 u8 ptag_31_8[0x18];
8907 u8 reserved_at_38[0x6];
8908 u8 wr_en[0x1];
8909 u8 rd_en[0x1];
8910 };
8911
8912 struct mlx5_ifc_query_wol_rol_out_bits {
8913 u8 status[0x8];
8914 u8 reserved_at_8[0x18];
8915
8916 u8 syndrome[0x20];
8917
8918 u8 reserved_at_40[0x10];
8919 u8 rol_mode[0x8];
8920 u8 wol_mode[0x8];
8921
8922 u8 reserved_at_60[0x20];
8923 };
8924
8925 struct mlx5_ifc_query_wol_rol_in_bits {
8926 u8 opcode[0x10];
8927 u8 reserved_at_10[0x10];
8928
8929 u8 reserved_at_20[0x10];
8930 u8 op_mod[0x10];
8931
8932 u8 reserved_at_40[0x40];
8933 };
8934
8935 struct mlx5_ifc_set_wol_rol_out_bits {
8936 u8 status[0x8];
8937 u8 reserved_at_8[0x18];
8938
8939 u8 syndrome[0x20];
8940
8941 u8 reserved_at_40[0x40];
8942 };
8943
8944 struct mlx5_ifc_set_wol_rol_in_bits {
8945 u8 opcode[0x10];
8946 u8 reserved_at_10[0x10];
8947
8948 u8 reserved_at_20[0x10];
8949 u8 op_mod[0x10];
8950
8951 u8 rol_mode_valid[0x1];
8952 u8 wol_mode_valid[0x1];
8953 u8 reserved_at_42[0xe];
8954 u8 rol_mode[0x8];
8955 u8 wol_mode[0x8];
8956
8957 u8 reserved_at_60[0x20];
8958 };
8959
8960 enum {
8961 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8962 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8963 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8964 };
8965
8966 enum {
8967 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8968 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8969 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8970 };
8971
8972 enum {
8973 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8974 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8975 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8976 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8977 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8978 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8979 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8980 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8981 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8982 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8983 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8984 };
8985
8986 struct mlx5_ifc_initial_seg_bits {
8987 u8 fw_rev_minor[0x10];
8988 u8 fw_rev_major[0x10];
8989
8990 u8 cmd_interface_rev[0x10];
8991 u8 fw_rev_subminor[0x10];
8992
8993 u8 reserved_at_40[0x40];
8994
8995 u8 cmdq_phy_addr_63_32[0x20];
8996
8997 u8 cmdq_phy_addr_31_12[0x14];
8998 u8 reserved_at_b4[0x2];
8999 u8 nic_interface[0x2];
9000 u8 log_cmdq_size[0x4];
9001 u8 log_cmdq_stride[0x4];
9002
9003 u8 command_doorbell_vector[0x20];
9004
9005 u8 reserved_at_e0[0xf00];
9006
9007 u8 initializing[0x1];
9008 u8 reserved_at_fe1[0x4];
9009 u8 nic_interface_supported[0x3];
9010 u8 embedded_cpu[0x1];
9011 u8 reserved_at_fe9[0x17];
9012
9013 struct mlx5_ifc_health_buffer_bits health_buffer;
9014
9015 u8 no_dram_nic_offset[0x20];
9016
9017 u8 reserved_at_1220[0x6e40];
9018
9019 u8 reserved_at_8060[0x1f];
9020 u8 clear_int[0x1];
9021
9022 u8 health_syndrome[0x8];
9023 u8 health_counter[0x18];
9024
9025 u8 reserved_at_80a0[0x17fc0];
9026 };
9027
9028 struct mlx5_ifc_mtpps_reg_bits {
9029 u8 reserved_at_0[0xc];
9030 u8 cap_number_of_pps_pins[0x4];
9031 u8 reserved_at_10[0x4];
9032 u8 cap_max_num_of_pps_in_pins[0x4];
9033 u8 reserved_at_18[0x4];
9034 u8 cap_max_num_of_pps_out_pins[0x4];
9035
9036 u8 reserved_at_20[0x24];
9037 u8 cap_pin_3_mode[0x4];
9038 u8 reserved_at_48[0x4];
9039 u8 cap_pin_2_mode[0x4];
9040 u8 reserved_at_50[0x4];
9041 u8 cap_pin_1_mode[0x4];
9042 u8 reserved_at_58[0x4];
9043 u8 cap_pin_0_mode[0x4];
9044
9045 u8 reserved_at_60[0x4];
9046 u8 cap_pin_7_mode[0x4];
9047 u8 reserved_at_68[0x4];
9048 u8 cap_pin_6_mode[0x4];
9049 u8 reserved_at_70[0x4];
9050 u8 cap_pin_5_mode[0x4];
9051 u8 reserved_at_78[0x4];
9052 u8 cap_pin_4_mode[0x4];
9053
9054 u8 field_select[0x20];
9055 u8 reserved_at_a0[0x60];
9056
9057 u8 enable[0x1];
9058 u8 reserved_at_101[0xb];
9059 u8 pattern[0x4];
9060 u8 reserved_at_110[0x4];
9061 u8 pin_mode[0x4];
9062 u8 pin[0x8];
9063
9064 u8 reserved_at_120[0x20];
9065
9066 u8 time_stamp[0x40];
9067
9068 u8 out_pulse_duration[0x10];
9069 u8 out_periodic_adjustment[0x10];
9070 u8 enhanced_out_periodic_adjustment[0x20];
9071
9072 u8 reserved_at_1c0[0x20];
9073 };
9074
9075 struct mlx5_ifc_mtppse_reg_bits {
9076 u8 reserved_at_0[0x18];
9077 u8 pin[0x8];
9078 u8 event_arm[0x1];
9079 u8 reserved_at_21[0x1b];
9080 u8 event_generation_mode[0x4];
9081 u8 reserved_at_40[0x40];
9082 };
9083
9084 struct mlx5_ifc_mcqs_reg_bits {
9085 u8 last_index_flag[0x1];
9086 u8 reserved_at_1[0x7];
9087 u8 fw_device[0x8];
9088 u8 component_index[0x10];
9089
9090 u8 reserved_at_20[0x10];
9091 u8 identifier[0x10];
9092
9093 u8 reserved_at_40[0x17];
9094 u8 component_status[0x5];
9095 u8 component_update_state[0x4];
9096
9097 u8 last_update_state_changer_type[0x4];
9098 u8 last_update_state_changer_host_id[0x4];
9099 u8 reserved_at_68[0x18];
9100 };
9101
9102 struct mlx5_ifc_mcqi_cap_bits {
9103 u8 supported_info_bitmask[0x20];
9104
9105 u8 component_size[0x20];
9106
9107 u8 max_component_size[0x20];
9108
9109 u8 log_mcda_word_size[0x4];
9110 u8 reserved_at_64[0xc];
9111 u8 mcda_max_write_size[0x10];
9112
9113 u8 rd_en[0x1];
9114 u8 reserved_at_81[0x1];
9115 u8 match_chip_id[0x1];
9116 u8 match_psid[0x1];
9117 u8 check_user_timestamp[0x1];
9118 u8 match_base_guid_mac[0x1];
9119 u8 reserved_at_86[0x1a];
9120 };
9121
9122 struct mlx5_ifc_mcqi_version_bits {
9123 u8 reserved_at_0[0x2];
9124 u8 build_time_valid[0x1];
9125 u8 user_defined_time_valid[0x1];
9126 u8 reserved_at_4[0x14];
9127 u8 version_string_length[0x8];
9128
9129 u8 version[0x20];
9130
9131 u8 build_time[0x40];
9132
9133 u8 user_defined_time[0x40];
9134
9135 u8 build_tool_version[0x20];
9136
9137 u8 reserved_at_e0[0x20];
9138
9139 u8 version_string[92][0x8];
9140 };
9141
9142 struct mlx5_ifc_mcqi_activation_method_bits {
9143 u8 pending_server_ac_power_cycle[0x1];
9144 u8 pending_server_dc_power_cycle[0x1];
9145 u8 pending_server_reboot[0x1];
9146 u8 pending_fw_reset[0x1];
9147 u8 auto_activate[0x1];
9148 u8 all_hosts_sync[0x1];
9149 u8 device_hw_reset[0x1];
9150 u8 reserved_at_7[0x19];
9151 };
9152
9153 union mlx5_ifc_mcqi_reg_data_bits {
9154 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9155 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9156 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9157 };
9158
9159 struct mlx5_ifc_mcqi_reg_bits {
9160 u8 read_pending_component[0x1];
9161 u8 reserved_at_1[0xf];
9162 u8 component_index[0x10];
9163
9164 u8 reserved_at_20[0x20];
9165
9166 u8 reserved_at_40[0x1b];
9167 u8 info_type[0x5];
9168
9169 u8 info_size[0x20];
9170
9171 u8 offset[0x20];
9172
9173 u8 reserved_at_a0[0x10];
9174 u8 data_size[0x10];
9175
9176 union mlx5_ifc_mcqi_reg_data_bits data[0];
9177 };
9178
9179 struct mlx5_ifc_mcc_reg_bits {
9180 u8 reserved_at_0[0x4];
9181 u8 time_elapsed_since_last_cmd[0xc];
9182 u8 reserved_at_10[0x8];
9183 u8 instruction[0x8];
9184
9185 u8 reserved_at_20[0x10];
9186 u8 component_index[0x10];
9187
9188 u8 reserved_at_40[0x8];
9189 u8 update_handle[0x18];
9190
9191 u8 handle_owner_type[0x4];
9192 u8 handle_owner_host_id[0x4];
9193 u8 reserved_at_68[0x1];
9194 u8 control_progress[0x7];
9195 u8 error_code[0x8];
9196 u8 reserved_at_78[0x4];
9197 u8 control_state[0x4];
9198
9199 u8 component_size[0x20];
9200
9201 u8 reserved_at_a0[0x60];
9202 };
9203
9204 struct mlx5_ifc_mcda_reg_bits {
9205 u8 reserved_at_0[0x8];
9206 u8 update_handle[0x18];
9207
9208 u8 offset[0x20];
9209
9210 u8 reserved_at_40[0x10];
9211 u8 size[0x10];
9212
9213 u8 reserved_at_60[0x20];
9214
9215 u8 data[0][0x20];
9216 };
9217
9218 union mlx5_ifc_ports_control_registers_document_bits {
9219 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9220 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9221 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9222 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9223 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9224 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9225 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9226 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9227 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9228 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9229 struct mlx5_ifc_paos_reg_bits paos_reg;
9230 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9231 struct mlx5_ifc_peir_reg_bits peir_reg;
9232 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9233 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9234 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9235 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9236 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9237 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9238 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9239 struct mlx5_ifc_plib_reg_bits plib_reg;
9240 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9241 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9242 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9243 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9244 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9245 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9246 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9247 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9248 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9249 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9250 struct mlx5_ifc_mpein_reg_bits mpein_reg;
9251 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9252 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9253 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9254 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9255 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9256 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9257 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9258 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9259 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9260 struct mlx5_ifc_pude_reg_bits pude_reg;
9261 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9262 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9263 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9264 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9265 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9266 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9267 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9268 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9269 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9270 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9271 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9272 u8 reserved_at_0[0x60e0];
9273 };
9274
9275 union mlx5_ifc_debug_enhancements_document_bits {
9276 struct mlx5_ifc_health_buffer_bits health_buffer;
9277 u8 reserved_at_0[0x200];
9278 };
9279
9280 union mlx5_ifc_uplink_pci_interface_document_bits {
9281 struct mlx5_ifc_initial_seg_bits initial_seg;
9282 u8 reserved_at_0[0x20060];
9283 };
9284
9285 struct mlx5_ifc_set_flow_table_root_out_bits {
9286 u8 status[0x8];
9287 u8 reserved_at_8[0x18];
9288
9289 u8 syndrome[0x20];
9290
9291 u8 reserved_at_40[0x40];
9292 };
9293
9294 struct mlx5_ifc_set_flow_table_root_in_bits {
9295 u8 opcode[0x10];
9296 u8 reserved_at_10[0x10];
9297
9298 u8 reserved_at_20[0x10];
9299 u8 op_mod[0x10];
9300
9301 u8 other_vport[0x1];
9302 u8 reserved_at_41[0xf];
9303 u8 vport_number[0x10];
9304
9305 u8 reserved_at_60[0x20];
9306
9307 u8 table_type[0x8];
9308 u8 reserved_at_88[0x18];
9309
9310 u8 reserved_at_a0[0x8];
9311 u8 table_id[0x18];
9312
9313 u8 reserved_at_c0[0x8];
9314 u8 underlay_qpn[0x18];
9315 u8 reserved_at_e0[0x120];
9316 };
9317
9318 enum {
9319 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9320 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9321 };
9322
9323 struct mlx5_ifc_modify_flow_table_out_bits {
9324 u8 status[0x8];
9325 u8 reserved_at_8[0x18];
9326
9327 u8 syndrome[0x20];
9328
9329 u8 reserved_at_40[0x40];
9330 };
9331
9332 struct mlx5_ifc_modify_flow_table_in_bits {
9333 u8 opcode[0x10];
9334 u8 reserved_at_10[0x10];
9335
9336 u8 reserved_at_20[0x10];
9337 u8 op_mod[0x10];
9338
9339 u8 other_vport[0x1];
9340 u8 reserved_at_41[0xf];
9341 u8 vport_number[0x10];
9342
9343 u8 reserved_at_60[0x10];
9344 u8 modify_field_select[0x10];
9345
9346 u8 table_type[0x8];
9347 u8 reserved_at_88[0x18];
9348
9349 u8 reserved_at_a0[0x8];
9350 u8 table_id[0x18];
9351
9352 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9353 };
9354
9355 struct mlx5_ifc_ets_tcn_config_reg_bits {
9356 u8 g[0x1];
9357 u8 b[0x1];
9358 u8 r[0x1];
9359 u8 reserved_at_3[0x9];
9360 u8 group[0x4];
9361 u8 reserved_at_10[0x9];
9362 u8 bw_allocation[0x7];
9363
9364 u8 reserved_at_20[0xc];
9365 u8 max_bw_units[0x4];
9366 u8 reserved_at_30[0x8];
9367 u8 max_bw_value[0x8];
9368 };
9369
9370 struct mlx5_ifc_ets_global_config_reg_bits {
9371 u8 reserved_at_0[0x2];
9372 u8 r[0x1];
9373 u8 reserved_at_3[0x1d];
9374
9375 u8 reserved_at_20[0xc];
9376 u8 max_bw_units[0x4];
9377 u8 reserved_at_30[0x8];
9378 u8 max_bw_value[0x8];
9379 };
9380
9381 struct mlx5_ifc_qetc_reg_bits {
9382 u8 reserved_at_0[0x8];
9383 u8 port_number[0x8];
9384 u8 reserved_at_10[0x30];
9385
9386 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9387 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9388 };
9389
9390 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9391 u8 e[0x1];
9392 u8 reserved_at_01[0x0b];
9393 u8 prio[0x04];
9394 };
9395
9396 struct mlx5_ifc_qpdpm_reg_bits {
9397 u8 reserved_at_0[0x8];
9398 u8 local_port[0x8];
9399 u8 reserved_at_10[0x10];
9400 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9401 };
9402
9403 struct mlx5_ifc_qpts_reg_bits {
9404 u8 reserved_at_0[0x8];
9405 u8 local_port[0x8];
9406 u8 reserved_at_10[0x2d];
9407 u8 trust_state[0x3];
9408 };
9409
9410 struct mlx5_ifc_pptb_reg_bits {
9411 u8 reserved_at_0[0x2];
9412 u8 mm[0x2];
9413 u8 reserved_at_4[0x4];
9414 u8 local_port[0x8];
9415 u8 reserved_at_10[0x6];
9416 u8 cm[0x1];
9417 u8 um[0x1];
9418 u8 pm[0x8];
9419
9420 u8 prio_x_buff[0x20];
9421
9422 u8 pm_msb[0x8];
9423 u8 reserved_at_48[0x10];
9424 u8 ctrl_buff[0x4];
9425 u8 untagged_buff[0x4];
9426 };
9427
9428 struct mlx5_ifc_pbmc_reg_bits {
9429 u8 reserved_at_0[0x8];
9430 u8 local_port[0x8];
9431 u8 reserved_at_10[0x10];
9432
9433 u8 xoff_timer_value[0x10];
9434 u8 xoff_refresh[0x10];
9435
9436 u8 reserved_at_40[0x9];
9437 u8 fullness_threshold[0x7];
9438 u8 port_buffer_size[0x10];
9439
9440 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9441
9442 u8 reserved_at_2e0[0x40];
9443 };
9444
9445 struct mlx5_ifc_qtct_reg_bits {
9446 u8 reserved_at_0[0x8];
9447 u8 port_number[0x8];
9448 u8 reserved_at_10[0xd];
9449 u8 prio[0x3];
9450
9451 u8 reserved_at_20[0x1d];
9452 u8 tclass[0x3];
9453 };
9454
9455 struct mlx5_ifc_mcia_reg_bits {
9456 u8 l[0x1];
9457 u8 reserved_at_1[0x7];
9458 u8 module[0x8];
9459 u8 reserved_at_10[0x8];
9460 u8 status[0x8];
9461
9462 u8 i2c_device_address[0x8];
9463 u8 page_number[0x8];
9464 u8 device_address[0x10];
9465
9466 u8 reserved_at_40[0x10];
9467 u8 size[0x10];
9468
9469 u8 reserved_at_60[0x20];
9470
9471 u8 dword_0[0x20];
9472 u8 dword_1[0x20];
9473 u8 dword_2[0x20];
9474 u8 dword_3[0x20];
9475 u8 dword_4[0x20];
9476 u8 dword_5[0x20];
9477 u8 dword_6[0x20];
9478 u8 dword_7[0x20];
9479 u8 dword_8[0x20];
9480 u8 dword_9[0x20];
9481 u8 dword_10[0x20];
9482 u8 dword_11[0x20];
9483 };
9484
9485 struct mlx5_ifc_dcbx_param_bits {
9486 u8 dcbx_cee_cap[0x1];
9487 u8 dcbx_ieee_cap[0x1];
9488 u8 dcbx_standby_cap[0x1];
9489 u8 reserved_at_3[0x5];
9490 u8 port_number[0x8];
9491 u8 reserved_at_10[0xa];
9492 u8 max_application_table_size[6];
9493 u8 reserved_at_20[0x15];
9494 u8 version_oper[0x3];
9495 u8 reserved_at_38[5];
9496 u8 version_admin[0x3];
9497 u8 willing_admin[0x1];
9498 u8 reserved_at_41[0x3];
9499 u8 pfc_cap_oper[0x4];
9500 u8 reserved_at_48[0x4];
9501 u8 pfc_cap_admin[0x4];
9502 u8 reserved_at_50[0x4];
9503 u8 num_of_tc_oper[0x4];
9504 u8 reserved_at_58[0x4];
9505 u8 num_of_tc_admin[0x4];
9506 u8 remote_willing[0x1];
9507 u8 reserved_at_61[3];
9508 u8 remote_pfc_cap[4];
9509 u8 reserved_at_68[0x14];
9510 u8 remote_num_of_tc[0x4];
9511 u8 reserved_at_80[0x18];
9512 u8 error[0x8];
9513 u8 reserved_at_a0[0x160];
9514 };
9515
9516 struct mlx5_ifc_lagc_bits {
9517 u8 reserved_at_0[0x1d];
9518 u8 lag_state[0x3];
9519
9520 u8 reserved_at_20[0x14];
9521 u8 tx_remap_affinity_2[0x4];
9522 u8 reserved_at_38[0x4];
9523 u8 tx_remap_affinity_1[0x4];
9524 };
9525
9526 struct mlx5_ifc_create_lag_out_bits {
9527 u8 status[0x8];
9528 u8 reserved_at_8[0x18];
9529
9530 u8 syndrome[0x20];
9531
9532 u8 reserved_at_40[0x40];
9533 };
9534
9535 struct mlx5_ifc_create_lag_in_bits {
9536 u8 opcode[0x10];
9537 u8 reserved_at_10[0x10];
9538
9539 u8 reserved_at_20[0x10];
9540 u8 op_mod[0x10];
9541
9542 struct mlx5_ifc_lagc_bits ctx;
9543 };
9544
9545 struct mlx5_ifc_modify_lag_out_bits {
9546 u8 status[0x8];
9547 u8 reserved_at_8[0x18];
9548
9549 u8 syndrome[0x20];
9550
9551 u8 reserved_at_40[0x40];
9552 };
9553
9554 struct mlx5_ifc_modify_lag_in_bits {
9555 u8 opcode[0x10];
9556 u8 reserved_at_10[0x10];
9557
9558 u8 reserved_at_20[0x10];
9559 u8 op_mod[0x10];
9560
9561 u8 reserved_at_40[0x20];
9562 u8 field_select[0x20];
9563
9564 struct mlx5_ifc_lagc_bits ctx;
9565 };
9566
9567 struct mlx5_ifc_query_lag_out_bits {
9568 u8 status[0x8];
9569 u8 reserved_at_8[0x18];
9570
9571 u8 syndrome[0x20];
9572
9573 u8 reserved_at_40[0x40];
9574
9575 struct mlx5_ifc_lagc_bits ctx;
9576 };
9577
9578 struct mlx5_ifc_query_lag_in_bits {
9579 u8 opcode[0x10];
9580 u8 reserved_at_10[0x10];
9581
9582 u8 reserved_at_20[0x10];
9583 u8 op_mod[0x10];
9584
9585 u8 reserved_at_40[0x40];
9586 };
9587
9588 struct mlx5_ifc_destroy_lag_out_bits {
9589 u8 status[0x8];
9590 u8 reserved_at_8[0x18];
9591
9592 u8 syndrome[0x20];
9593
9594 u8 reserved_at_40[0x40];
9595 };
9596
9597 struct mlx5_ifc_destroy_lag_in_bits {
9598 u8 opcode[0x10];
9599 u8 reserved_at_10[0x10];
9600
9601 u8 reserved_at_20[0x10];
9602 u8 op_mod[0x10];
9603
9604 u8 reserved_at_40[0x40];
9605 };
9606
9607 struct mlx5_ifc_create_vport_lag_out_bits {
9608 u8 status[0x8];
9609 u8 reserved_at_8[0x18];
9610
9611 u8 syndrome[0x20];
9612
9613 u8 reserved_at_40[0x40];
9614 };
9615
9616 struct mlx5_ifc_create_vport_lag_in_bits {
9617 u8 opcode[0x10];
9618 u8 reserved_at_10[0x10];
9619
9620 u8 reserved_at_20[0x10];
9621 u8 op_mod[0x10];
9622
9623 u8 reserved_at_40[0x40];
9624 };
9625
9626 struct mlx5_ifc_destroy_vport_lag_out_bits {
9627 u8 status[0x8];
9628 u8 reserved_at_8[0x18];
9629
9630 u8 syndrome[0x20];
9631
9632 u8 reserved_at_40[0x40];
9633 };
9634
9635 struct mlx5_ifc_destroy_vport_lag_in_bits {
9636 u8 opcode[0x10];
9637 u8 reserved_at_10[0x10];
9638
9639 u8 reserved_at_20[0x10];
9640 u8 op_mod[0x10];
9641
9642 u8 reserved_at_40[0x40];
9643 };
9644
9645 struct mlx5_ifc_alloc_memic_in_bits {
9646 u8 opcode[0x10];
9647 u8 reserved_at_10[0x10];
9648
9649 u8 reserved_at_20[0x10];
9650 u8 op_mod[0x10];
9651
9652 u8 reserved_at_30[0x20];
9653
9654 u8 reserved_at_40[0x18];
9655 u8 log_memic_addr_alignment[0x8];
9656
9657 u8 range_start_addr[0x40];
9658
9659 u8 range_size[0x20];
9660
9661 u8 memic_size[0x20];
9662 };
9663
9664 struct mlx5_ifc_alloc_memic_out_bits {
9665 u8 status[0x8];
9666 u8 reserved_at_8[0x18];
9667
9668 u8 syndrome[0x20];
9669
9670 u8 memic_start_addr[0x40];
9671 };
9672
9673 struct mlx5_ifc_dealloc_memic_in_bits {
9674 u8 opcode[0x10];
9675 u8 reserved_at_10[0x10];
9676
9677 u8 reserved_at_20[0x10];
9678 u8 op_mod[0x10];
9679
9680 u8 reserved_at_40[0x40];
9681
9682 u8 memic_start_addr[0x40];
9683
9684 u8 memic_size[0x20];
9685
9686 u8 reserved_at_e0[0x20];
9687 };
9688
9689 struct mlx5_ifc_dealloc_memic_out_bits {
9690 u8 status[0x8];
9691 u8 reserved_at_8[0x18];
9692
9693 u8 syndrome[0x20];
9694
9695 u8 reserved_at_40[0x40];
9696 };
9697
9698 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9699 u8 opcode[0x10];
9700 u8 uid[0x10];
9701
9702 u8 vhca_tunnel_id[0x10];
9703 u8 obj_type[0x10];
9704
9705 u8 obj_id[0x20];
9706
9707 u8 reserved_at_60[0x20];
9708 };
9709
9710 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9711 u8 status[0x8];
9712 u8 reserved_at_8[0x18];
9713
9714 u8 syndrome[0x20];
9715
9716 u8 obj_id[0x20];
9717
9718 u8 reserved_at_60[0x20];
9719 };
9720
9721 struct mlx5_ifc_umem_bits {
9722 u8 reserved_at_0[0x80];
9723
9724 u8 reserved_at_80[0x1b];
9725 u8 log_page_size[0x5];
9726
9727 u8 page_offset[0x20];
9728
9729 u8 num_of_mtt[0x40];
9730
9731 struct mlx5_ifc_mtt_bits mtt[0];
9732 };
9733
9734 struct mlx5_ifc_uctx_bits {
9735 u8 cap[0x20];
9736
9737 u8 reserved_at_20[0x160];
9738 };
9739
9740 struct mlx5_ifc_sw_icm_bits {
9741 u8 modify_field_select[0x40];
9742
9743 u8 reserved_at_40[0x18];
9744 u8 log_sw_icm_size[0x8];
9745
9746 u8 reserved_at_60[0x20];
9747
9748 u8 sw_icm_start_addr[0x40];
9749
9750 u8 reserved_at_c0[0x140];
9751 };
9752
9753 struct mlx5_ifc_geneve_tlv_option_bits {
9754 u8 modify_field_select[0x40];
9755
9756 u8 reserved_at_40[0x18];
9757 u8 geneve_option_fte_index[0x8];
9758
9759 u8 option_class[0x10];
9760 u8 option_type[0x8];
9761 u8 reserved_at_78[0x3];
9762 u8 option_data_length[0x5];
9763
9764 u8 reserved_at_80[0x180];
9765 };
9766
9767 struct mlx5_ifc_create_umem_in_bits {
9768 u8 opcode[0x10];
9769 u8 uid[0x10];
9770
9771 u8 reserved_at_20[0x10];
9772 u8 op_mod[0x10];
9773
9774 u8 reserved_at_40[0x40];
9775
9776 struct mlx5_ifc_umem_bits umem;
9777 };
9778
9779 struct mlx5_ifc_create_uctx_in_bits {
9780 u8 opcode[0x10];
9781 u8 reserved_at_10[0x10];
9782
9783 u8 reserved_at_20[0x10];
9784 u8 op_mod[0x10];
9785
9786 u8 reserved_at_40[0x40];
9787
9788 struct mlx5_ifc_uctx_bits uctx;
9789 };
9790
9791 struct mlx5_ifc_destroy_uctx_in_bits {
9792 u8 opcode[0x10];
9793 u8 reserved_at_10[0x10];
9794
9795 u8 reserved_at_20[0x10];
9796 u8 op_mod[0x10];
9797
9798 u8 reserved_at_40[0x10];
9799 u8 uid[0x10];
9800
9801 u8 reserved_at_60[0x20];
9802 };
9803
9804 struct mlx5_ifc_create_sw_icm_in_bits {
9805 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9806 struct mlx5_ifc_sw_icm_bits sw_icm;
9807 };
9808
9809 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
9810 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9811 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
9812 };
9813
9814 struct mlx5_ifc_mtrc_string_db_param_bits {
9815 u8 string_db_base_address[0x20];
9816
9817 u8 reserved_at_20[0x8];
9818 u8 string_db_size[0x18];
9819 };
9820
9821 struct mlx5_ifc_mtrc_cap_bits {
9822 u8 trace_owner[0x1];
9823 u8 trace_to_memory[0x1];
9824 u8 reserved_at_2[0x4];
9825 u8 trc_ver[0x2];
9826 u8 reserved_at_8[0x14];
9827 u8 num_string_db[0x4];
9828
9829 u8 first_string_trace[0x8];
9830 u8 num_string_trace[0x8];
9831 u8 reserved_at_30[0x28];
9832
9833 u8 log_max_trace_buffer_size[0x8];
9834
9835 u8 reserved_at_60[0x20];
9836
9837 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9838
9839 u8 reserved_at_280[0x180];
9840 };
9841
9842 struct mlx5_ifc_mtrc_conf_bits {
9843 u8 reserved_at_0[0x1c];
9844 u8 trace_mode[0x4];
9845 u8 reserved_at_20[0x18];
9846 u8 log_trace_buffer_size[0x8];
9847 u8 trace_mkey[0x20];
9848 u8 reserved_at_60[0x3a0];
9849 };
9850
9851 struct mlx5_ifc_mtrc_stdb_bits {
9852 u8 string_db_index[0x4];
9853 u8 reserved_at_4[0x4];
9854 u8 read_size[0x18];
9855 u8 start_offset[0x20];
9856 u8 string_db_data[0];
9857 };
9858
9859 struct mlx5_ifc_mtrc_ctrl_bits {
9860 u8 trace_status[0x2];
9861 u8 reserved_at_2[0x2];
9862 u8 arm_event[0x1];
9863 u8 reserved_at_5[0xb];
9864 u8 modify_field_select[0x10];
9865 u8 reserved_at_20[0x2b];
9866 u8 current_timestamp52_32[0x15];
9867 u8 current_timestamp31_0[0x20];
9868 u8 reserved_at_80[0x180];
9869 };
9870
9871 struct mlx5_ifc_host_params_context_bits {
9872 u8 host_number[0x8];
9873 u8 reserved_at_8[0x7];
9874 u8 host_pf_disabled[0x1];
9875 u8 host_num_of_vfs[0x10];
9876
9877 u8 host_total_vfs[0x10];
9878 u8 host_pci_bus[0x10];
9879
9880 u8 reserved_at_40[0x10];
9881 u8 host_pci_device[0x10];
9882
9883 u8 reserved_at_60[0x10];
9884 u8 host_pci_function[0x10];
9885
9886 u8 reserved_at_80[0x180];
9887 };
9888
9889 struct mlx5_ifc_query_esw_functions_in_bits {
9890 u8 opcode[0x10];
9891 u8 reserved_at_10[0x10];
9892
9893 u8 reserved_at_20[0x10];
9894 u8 op_mod[0x10];
9895
9896 u8 reserved_at_40[0x40];
9897 };
9898
9899 struct mlx5_ifc_query_esw_functions_out_bits {
9900 u8 status[0x8];
9901 u8 reserved_at_8[0x18];
9902
9903 u8 syndrome[0x20];
9904
9905 u8 reserved_at_40[0x40];
9906
9907 struct mlx5_ifc_host_params_context_bits host_params_context;
9908
9909 u8 reserved_at_280[0x180];
9910 u8 host_sf_enable[0][0x40];
9911 };
9912
9913 struct mlx5_ifc_sf_partition_bits {
9914 u8 reserved_at_0[0x10];
9915 u8 log_num_sf[0x8];
9916 u8 log_sf_bar_size[0x8];
9917 };
9918
9919 struct mlx5_ifc_query_sf_partitions_out_bits {
9920 u8 status[0x8];
9921 u8 reserved_at_8[0x18];
9922
9923 u8 syndrome[0x20];
9924
9925 u8 reserved_at_40[0x18];
9926 u8 num_sf_partitions[0x8];
9927
9928 u8 reserved_at_60[0x20];
9929
9930 struct mlx5_ifc_sf_partition_bits sf_partition[0];
9931 };
9932
9933 struct mlx5_ifc_query_sf_partitions_in_bits {
9934 u8 opcode[0x10];
9935 u8 reserved_at_10[0x10];
9936
9937 u8 reserved_at_20[0x10];
9938 u8 op_mod[0x10];
9939
9940 u8 reserved_at_40[0x40];
9941 };
9942
9943 struct mlx5_ifc_dealloc_sf_out_bits {
9944 u8 status[0x8];
9945 u8 reserved_at_8[0x18];
9946
9947 u8 syndrome[0x20];
9948
9949 u8 reserved_at_40[0x40];
9950 };
9951
9952 struct mlx5_ifc_dealloc_sf_in_bits {
9953 u8 opcode[0x10];
9954 u8 reserved_at_10[0x10];
9955
9956 u8 reserved_at_20[0x10];
9957 u8 op_mod[0x10];
9958
9959 u8 reserved_at_40[0x10];
9960 u8 function_id[0x10];
9961
9962 u8 reserved_at_60[0x20];
9963 };
9964
9965 struct mlx5_ifc_alloc_sf_out_bits {
9966 u8 status[0x8];
9967 u8 reserved_at_8[0x18];
9968
9969 u8 syndrome[0x20];
9970
9971 u8 reserved_at_40[0x40];
9972 };
9973
9974 struct mlx5_ifc_alloc_sf_in_bits {
9975 u8 opcode[0x10];
9976 u8 reserved_at_10[0x10];
9977
9978 u8 reserved_at_20[0x10];
9979 u8 op_mod[0x10];
9980
9981 u8 reserved_at_40[0x10];
9982 u8 function_id[0x10];
9983
9984 u8 reserved_at_60[0x20];
9985 };
9986
9987 struct mlx5_ifc_affiliated_event_header_bits {
9988 u8 reserved_at_0[0x10];
9989 u8 obj_type[0x10];
9990
9991 u8 obj_id[0x20];
9992 };
9993
9994 enum {
9995 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
9996 };
9997
9998 enum {
9999 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10000 };
10001
10002 struct mlx5_ifc_encryption_key_obj_bits {
10003 u8 modify_field_select[0x40];
10004
10005 u8 reserved_at_40[0x14];
10006 u8 key_size[0x4];
10007 u8 reserved_at_58[0x4];
10008 u8 key_type[0x4];
10009
10010 u8 reserved_at_60[0x8];
10011 u8 pd[0x18];
10012
10013 u8 reserved_at_80[0x180];
10014 u8 key[8][0x20];
10015
10016 u8 reserved_at_300[0x500];
10017 };
10018
10019 struct mlx5_ifc_create_encryption_key_in_bits {
10020 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10021 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10022 };
10023
10024 enum {
10025 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10026 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10027 };
10028
10029 enum {
10030 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10031 };
10032
10033 struct mlx5_ifc_tls_static_params_bits {
10034 u8 const_2[0x2];
10035 u8 tls_version[0x4];
10036 u8 const_1[0x2];
10037 u8 reserved_at_8[0x14];
10038 u8 encryption_standard[0x4];
10039
10040 u8 reserved_at_20[0x20];
10041
10042 u8 initial_record_number[0x40];
10043
10044 u8 resync_tcp_sn[0x20];
10045
10046 u8 gcm_iv[0x20];
10047
10048 u8 implicit_iv[0x40];
10049
10050 u8 reserved_at_100[0x8];
10051 u8 dek_index[0x18];
10052
10053 u8 reserved_at_120[0xe0];
10054 };
10055
10056 struct mlx5_ifc_tls_progress_params_bits {
10057 u8 valid[0x1];
10058 u8 reserved_at_1[0x7];
10059 u8 pd[0x18];
10060
10061 u8 next_record_tcp_sn[0x20];
10062
10063 u8 hw_resync_tcp_sn[0x20];
10064
10065 u8 record_tracker_state[0x2];
10066 u8 auth_state[0x2];
10067 u8 reserved_at_64[0x4];
10068 u8 hw_offset_record_number[0x18];
10069 };
10070
10071 #endif /* MLX5_IFC_H */
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