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ls-ecaps: Correct the link state reporting
[thirdparty/pciutils.git] / ls-caps.c
CommitLineData
c7a34993
MM		 1/*
2 * The PCI Utilities -- Show Capabilities
3 *
b47b5bd4 4 * Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
c7a34993 5 *
61829219
MM		 6 * Can be freely distributed and used under the terms of the GNU GPL v2+.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
c7a34993
MM		 9 */
10
11#include <stdio.h>
12#include <string.h>
13
14#include "lspci.h"
15
16static void
17cap_pm(struct device *d, int where, int cap)
18{
19 int t, b;
20 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
21
22 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
23 if (verbose < 2)
24 return;
25 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
26 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
27 FLAG(cap, PCI_PM_CAP_DSI),
28 FLAG(cap, PCI_PM_CAP_D1),
29 FLAG(cap, PCI_PM_CAP_D2),
02d761b4 30 pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
c7a34993
MM		 31 FLAG(cap, PCI_PM_CAP_PME_D0),
32 FLAG(cap, PCI_PM_CAP_PME_D1),
33 FLAG(cap, PCI_PM_CAP_PME_D2),
34 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
35 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
36 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
37 return;
38 t = get_conf_word(d, where + PCI_PM_CTRL);
1c702fac 39 printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
c7a34993 40 t & PCI_PM_CTRL_STATE_MASK,
1c702fac 41 FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
c7a34993
MM		 42 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
43 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
44 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
45 FLAG(t, PCI_PM_CTRL_PME_STATUS));
46 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
47 if (b)
48 printf("\t\tBridge: PM%c B3%c\n",
6da04fbb
MB		 49 FLAG(b, PCI_PM_BPCC_ENABLE),
50 FLAG(~b, PCI_PM_PPB_B2_B3));
c7a34993
MM		 51}
52
53static void
54format_agp_rate(int rate, char *buf, int agp3)
55{
56 char *c = buf;
57 int i;
58
59 for (i=0; i<=2; i++)
60 if (rate & (1 << i))
61 {
62 if (c != buf)
63 *c++ = ',';
64 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
65 }
66 if (c != buf)
67 *c = 0;
68 else
69 strcpy(buf, "<none>");
70}
71
72static void
73cap_agp(struct device *d, int where, int cap)
74{
75 u32 t;
76 char rate[16];
77 int ver, rev;
78 int agp3 = 0;
79
80 ver = (cap >> 4) & 0x0f;
81 rev = cap & 0x0f;
82 printf("AGP version %x.%x\n", ver, rev);
83 if (verbose < 2)
84 return;
85 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
86 return;
87 t = get_conf_long(d, where + PCI_AGP_STATUS);
88 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
89 agp3 = 1;
90 format_agp_rate(t & 7, rate, agp3);
91 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
92 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
93 FLAG(t, PCI_AGP_STATUS_ISOCH),
94 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
95 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
96 FLAG(t, PCI_AGP_STATUS_SBA),
97 FLAG(t, PCI_AGP_STATUS_ITA_COH),
98 FLAG(t, PCI_AGP_STATUS_GART64),
99 FLAG(t, PCI_AGP_STATUS_HTRANS),
100 FLAG(t, PCI_AGP_STATUS_64BIT),
101 FLAG(t, PCI_AGP_STATUS_FW),
102 FLAG(t, PCI_AGP_STATUS_AGP3),
103 rate);
104 t = get_conf_long(d, where + PCI_AGP_COMMAND);
105 format_agp_rate(t & 7, rate, agp3);
106 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
107 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
108 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
109 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
110 FLAG(t, PCI_AGP_COMMAND_SBA),
111 FLAG(t, PCI_AGP_COMMAND_AGP),
112 FLAG(t, PCI_AGP_COMMAND_GART64),
113 FLAG(t, PCI_AGP_COMMAND_64BIT),
114 FLAG(t, PCI_AGP_COMMAND_FW),
115 rate);
116}
117
118static void
119cap_pcix_nobridge(struct device *d, int where)
120{
121 u16 command;
122 u32 status;
123 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
124
125 printf("PCI-X non-bridge device\n");
126
127 if (verbose < 2)
128 return;
129
130 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
131 return;
132
133 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
134 status = get_conf_long(d, where + PCI_PCIX_STATUS);
135 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
136 FLAG(command, PCI_PCIX_COMMAND_DPERE),
137 FLAG(command, PCI_PCIX_COMMAND_ERO),
138 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
139 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
140 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
02d761b4
BH		 141 (status & PCI_PCIX_STATUS_BUS) >> 8,
142 (status & PCI_PCIX_STATUS_DEVICE) >> 3,
c7a34993
MM		 143 (status & PCI_PCIX_STATUS_FUNCTION),
144 FLAG(status, PCI_PCIX_STATUS_64BIT),
145 FLAG(status, PCI_PCIX_STATUS_133MHZ),
146 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
147 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
148 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
02d761b4
BH		 149 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
150 max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
151 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
c7a34993
MM		 152 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
153 FLAG(status, PCI_PCIX_STATUS_266MHZ),
154 FLAG(status, PCI_PCIX_STATUS_533MHZ));
155}
156
157static void
158cap_pcix_bridge(struct device *d, int where)
159{
160 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
161 u16 secstatus;
162 u32 status, upstcr, downstcr;
163
164 printf("PCI-X bridge device\n");
165
166 if (verbose < 2)
167 return;
168
169 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
170 return;
171
172 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
173 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
174 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
175 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
176 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
177 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
178 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
179 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
02d761b4 180 sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
c7a34993
MM		 181 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
182 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
02d761b4
BH		 183 (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
184 (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
c7a34993
MM		 185 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
186 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
187 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
188 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
189 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
190 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
191 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
192 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
193 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
194 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
195 (upstcr >> 16) & 0xffff);
196 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
197 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
198 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
199 (downstcr >> 16) & 0xffff);
200}
201
202static void
203cap_pcix(struct device *d, int where)
204{
205 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
206 {
207 case PCI_HEADER_TYPE_NORMAL:
208 cap_pcix_nobridge(d, where);
209 break;
210 case PCI_HEADER_TYPE_BRIDGE:
211 cap_pcix_bridge(d, where);
212 break;
213 }
214}
215
216static inline char *
217ht_link_width(unsigned width)
218{
219 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
220 return widths[width];
221}
222
223static inline char *
224ht_link_freq(unsigned freq)
225{
226 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
227 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
228 return freqs[freq];
229}
230
231static void
232cap_ht_pri(struct device *d, int where, int cmd)
233{
234 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
235 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
c7a34993
MM		 236
237 printf("HyperTransport: Slave or Primary Interface\n");
238 if (verbose < 2)
239 return;
240
241 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
242 return;
243 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
244 if (rid < 0x22 && rid > 0x11)
245 printf("\t\t!!! Possibly incomplete decoding\n");
246
0089d489 247 printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c",
c7a34993
MM		 248 (cmd & PCI_HT_PRI_CMD_BUID),
249 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
250 FLAG(cmd, PCI_HT_PRI_CMD_MH),
0089d489 251 FLAG(cmd, PCI_HT_PRI_CMD_DD));
c7a34993 252 if (rid >= 0x22)
0089d489
MM		 253 printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL));
254 printf("\n");
255
256 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
257 printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
c7a34993
MM		 258 FLAG(lctr0, PCI_HT_LCTR_CFLE),
259 FLAG(lctr0, PCI_HT_LCTR_CST),
260 FLAG(lctr0, PCI_HT_LCTR_CFE),
261 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
262 FLAG(lctr0, PCI_HT_LCTR_INIT),
263 FLAG(lctr0, PCI_HT_LCTR_EOC),
264 FLAG(lctr0, PCI_HT_LCTR_TXO),
0089d489 265 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8);
c7a34993 266 if (rid >= 0x22)
0089d489
MM		 267 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
268 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
269 FLAG(lctr0, PCI_HT_LCTR_LSEN),
270 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
271 FLAG(lctr0, PCI_HT_LCTR_64B));
272 printf("\n");
273
274 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
275 if (rid < 0x22)
276 printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
277 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
278 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
279 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
280 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12));
c7a34993 281 else
0089d489
MM		 282 printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
283 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
284 FLAG(lcnf0, PCI_HT_LCNF_DFI),
285 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
286 FLAG(lcnf0, PCI_HT_LCNF_DFO),
287 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
288 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
289 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
290 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
291
c7a34993 292 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
0089d489 293 printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
c7a34993
MM		 294 FLAG(lctr1, PCI_HT_LCTR_CFLE),
295 FLAG(lctr1, PCI_HT_LCTR_CST),
296 FLAG(lctr1, PCI_HT_LCTR_CFE),
297 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
298 FLAG(lctr1, PCI_HT_LCTR_INIT),
299 FLAG(lctr1, PCI_HT_LCTR_EOC),
300 FLAG(lctr1, PCI_HT_LCTR_TXO),
0089d489
MM		 301 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8);
302 if (rid >= 0x22)
303 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
c7a34993
MM		 304 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
305 FLAG(lctr1, PCI_HT_LCTR_LSEN),
306 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
307 FLAG(lctr1, PCI_HT_LCTR_64B));
0089d489
MM		 308 printf("\n");
309
c7a34993 310 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
0089d489
MM		 311 if (rid < 0x22)
312 printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
313 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
314 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
315 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
316 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12));
c7a34993 317 else
0089d489
MM		 318 printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
319 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
320 FLAG(lcnf1, PCI_HT_LCNF_DFI),
321 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
322 FLAG(lcnf1, PCI_HT_LCNF_DFO),
323 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
324 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
325 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
326 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
327
c7a34993
MM		 328 printf("\t\tRevision ID: %u.%02u\n",
329 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
330 if (rid < 0x22)
331 return;
0089d489 332
c7a34993
MM		 333 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
334 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
335 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
336 FLAG(lfrer0, PCI_HT_LFRER_PROT),
337 FLAG(lfrer0, PCI_HT_LFRER_OV),
338 FLAG(lfrer0, PCI_HT_LFRER_EOC),
339 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
0089d489 340
c7a34993
MM		 341 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
342 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
343 FLAG(lfcap0, PCI_HT_LFCAP_200),
344 FLAG(lfcap0, PCI_HT_LFCAP_300),
345 FLAG(lfcap0, PCI_HT_LFCAP_400),
346 FLAG(lfcap0, PCI_HT_LFCAP_500),
347 FLAG(lfcap0, PCI_HT_LFCAP_600),
348 FLAG(lfcap0, PCI_HT_LFCAP_800),
349 FLAG(lfcap0, PCI_HT_LFCAP_1000),
350 FLAG(lfcap0, PCI_HT_LFCAP_1200),
351 FLAG(lfcap0, PCI_HT_LFCAP_1400),
352 FLAG(lfcap0, PCI_HT_LFCAP_1600),
353 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
0089d489 354
c7a34993
MM		 355 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
356 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
357 FLAG(ftr, PCI_HT_FTR_ISOCFC),
358 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
359 FLAG(ftr, PCI_HT_FTR_CRCTM),
360 FLAG(ftr, PCI_HT_FTR_ECTLT),
361 FLAG(ftr, PCI_HT_FTR_64BA),
362 FLAG(ftr, PCI_HT_FTR_UIDRD));
0089d489 363
c7a34993
MM		 364 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
365 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
366 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
367 FLAG(lfrer1, PCI_HT_LFRER_PROT),
368 FLAG(lfrer1, PCI_HT_LFRER_OV),
369 FLAG(lfrer1, PCI_HT_LFRER_EOC),
370 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
0089d489 371
c7a34993
MM		 372 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
373 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
374 FLAG(lfcap1, PCI_HT_LFCAP_200),
375 FLAG(lfcap1, PCI_HT_LFCAP_300),
376 FLAG(lfcap1, PCI_HT_LFCAP_400),
377 FLAG(lfcap1, PCI_HT_LFCAP_500),
378 FLAG(lfcap1, PCI_HT_LFCAP_600),
379 FLAG(lfcap1, PCI_HT_LFCAP_800),
380 FLAG(lfcap1, PCI_HT_LFCAP_1000),
381 FLAG(lfcap1, PCI_HT_LFCAP_1200),
382 FLAG(lfcap1, PCI_HT_LFCAP_1400),
383 FLAG(lfcap1, PCI_HT_LFCAP_1600),
384 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
0089d489 385
c7a34993
MM		 386 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
387 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
388 FLAG(eh, PCI_HT_EH_PFLE),
389 FLAG(eh, PCI_HT_EH_OFLE),
390 FLAG(eh, PCI_HT_EH_PFE),
391 FLAG(eh, PCI_HT_EH_OFE),
392 FLAG(eh, PCI_HT_EH_EOCFE),
393 FLAG(eh, PCI_HT_EH_RFE),
394 FLAG(eh, PCI_HT_EH_CRCFE),
395 FLAG(eh, PCI_HT_EH_SERRFE),
396 FLAG(eh, PCI_HT_EH_CF),
397 FLAG(eh, PCI_HT_EH_RE),
398 FLAG(eh, PCI_HT_EH_PNFE),
399 FLAG(eh, PCI_HT_EH_ONFE),
400 FLAG(eh, PCI_HT_EH_EOCNFE),
401 FLAG(eh, PCI_HT_EH_RNFE),
402 FLAG(eh, PCI_HT_EH_CRCNFE),
403 FLAG(eh, PCI_HT_EH_SERRNFE));
0089d489 404
c7a34993
MM		 405 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
406 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
407 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
0089d489 408
c7a34993
MM		 409 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
410 printf("\t\tBus Number: %02x\n", bn);
411}
412
413static void
414cap_ht_sec(struct device *d, int where, int cmd)
415{
416 u16 lctr, lcnf, ftr, eh;
417 u8 rid, lfrer, lfcap, mbu, mlu;
418 char *fmt;
419
420 printf("HyperTransport: Host or Secondary Interface\n");
421 if (verbose < 2)
422 return;
423
424 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
425 return;
426 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
427 if (rid < 0x22 && rid > 0x11)
428 printf("\t\t!!! Possibly incomplete decoding\n");
429
430 if (rid >= 0x22)
431 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
432 else
433 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
434 printf(fmt,
435 FLAG(cmd, PCI_HT_SEC_CMD_WR),
436 FLAG(cmd, PCI_HT_SEC_CMD_DE),
437 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
438 FLAG(cmd, PCI_HT_SEC_CMD_CS),
439 FLAG(cmd, PCI_HT_SEC_CMD_HH),
440 FLAG(cmd, PCI_HT_SEC_CMD_AS),
441 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
442 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
443 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
444 if (rid >= 0x22)
445 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
446 else
447 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
448 printf(fmt,
449 FLAG(lctr, PCI_HT_LCTR_CFLE),
450 FLAG(lctr, PCI_HT_LCTR_CST),
451 FLAG(lctr, PCI_HT_LCTR_CFE),
452 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
453 FLAG(lctr, PCI_HT_LCTR_INIT),
454 FLAG(lctr, PCI_HT_LCTR_EOC),
455 FLAG(lctr, PCI_HT_LCTR_TXO),
456 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
457 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
458 FLAG(lctr, PCI_HT_LCTR_LSEN),
459 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
460 FLAG(lctr, PCI_HT_LCTR_64B));
461 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
462 if (rid >= 0x22)
463 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
464 else
465 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
466 printf(fmt,
467 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
468 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
469 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
470 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
471 FLAG(lcnf, PCI_HT_LCNF_DFI),
472 FLAG(lcnf, PCI_HT_LCNF_DFO),
473 FLAG(lcnf, PCI_HT_LCNF_DFIE),
474 FLAG(lcnf, PCI_HT_LCNF_DFOE));
475 printf("\t\tRevision ID: %u.%02u\n",
476 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
477 if (rid < 0x22)
478 return;
479 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
480 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
481 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
482 FLAG(lfrer, PCI_HT_LFRER_PROT),
483 FLAG(lfrer, PCI_HT_LFRER_OV),
484 FLAG(lfrer, PCI_HT_LFRER_EOC),
485 FLAG(lfrer, PCI_HT_LFRER_CTLT));
486 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
487 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
488 FLAG(lfcap, PCI_HT_LFCAP_200),
489 FLAG(lfcap, PCI_HT_LFCAP_300),
490 FLAG(lfcap, PCI_HT_LFCAP_400),
491 FLAG(lfcap, PCI_HT_LFCAP_500),
492 FLAG(lfcap, PCI_HT_LFCAP_600),
493 FLAG(lfcap, PCI_HT_LFCAP_800),
494 FLAG(lfcap, PCI_HT_LFCAP_1000),
495 FLAG(lfcap, PCI_HT_LFCAP_1200),
496 FLAG(lfcap, PCI_HT_LFCAP_1400),
497 FLAG(lfcap, PCI_HT_LFCAP_1600),
498 FLAG(lfcap, PCI_HT_LFCAP_VEND));
499 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
500 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
501 FLAG(ftr, PCI_HT_FTR_ISOCFC),
502 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
503 FLAG(ftr, PCI_HT_FTR_CRCTM),
504 FLAG(ftr, PCI_HT_FTR_ECTLT),
505 FLAG(ftr, PCI_HT_FTR_64BA),
506 FLAG(ftr, PCI_HT_FTR_UIDRD),
507 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
508 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
509 if (ftr & PCI_HT_SEC_FTR_EXTRS)
510 {
511 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
512 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
513 FLAG(eh, PCI_HT_EH_PFLE),
514 FLAG(eh, PCI_HT_EH_OFLE),
515 FLAG(eh, PCI_HT_EH_PFE),
516 FLAG(eh, PCI_HT_EH_OFE),
517 FLAG(eh, PCI_HT_EH_EOCFE),
518 FLAG(eh, PCI_HT_EH_RFE),
519 FLAG(eh, PCI_HT_EH_CRCFE),
520 FLAG(eh, PCI_HT_EH_SERRFE),
521 FLAG(eh, PCI_HT_EH_CF),
522 FLAG(eh, PCI_HT_EH_RE),
523 FLAG(eh, PCI_HT_EH_PNFE),
524 FLAG(eh, PCI_HT_EH_ONFE),
525 FLAG(eh, PCI_HT_EH_EOCNFE),
526 FLAG(eh, PCI_HT_EH_RNFE),
527 FLAG(eh, PCI_HT_EH_CRCNFE),
528 FLAG(eh, PCI_HT_EH_SERRNFE));
529 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
530 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
531 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
532 }
533}
534
535static void
536cap_ht(struct device *d, int where, int cmd)
537{
538 int type;
539
540 switch (cmd & PCI_HT_CMD_TYP_HI)
541 {
542 case PCI_HT_CMD_TYP_HI_PRI:
543 cap_ht_pri(d, where, cmd);
544 return;
545 case PCI_HT_CMD_TYP_HI_SEC:
546 cap_ht_sec(d, where, cmd);
547 return;
548 }
549
550 type = cmd & PCI_HT_CMD_TYP;
551 switch (type)
552 {
553 case PCI_HT_CMD_TYP_SW:
554 printf("HyperTransport: Switch\n");
555 break;
556 case PCI_HT_CMD_TYP_IDC:
557 printf("HyperTransport: Interrupt Discovery and Configuration\n");
558 break;
559 case PCI_HT_CMD_TYP_RID:
560 printf("HyperTransport: Revision ID: %u.%02u\n",
561 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
562 break;
563 case PCI_HT_CMD_TYP_UIDC:
564 printf("HyperTransport: UnitID Clumping\n");
565 break;
566 case PCI_HT_CMD_TYP_ECSA:
567 printf("HyperTransport: Extended Configuration Space Access\n");
568 break;
569 case PCI_HT_CMD_TYP_AM:
570 printf("HyperTransport: Address Mapping\n");
571 break;
572 case PCI_HT_CMD_TYP_MSIM:
573 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
574 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
575 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
576 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
577 {
578 u32 offl, offh;
579 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
580 break;
581 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
582 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
6811edb8 583 printf("\t\tMapping Address Base: %016" PCI_U64_FMT_X "\n", ((u64)offh << 32) | (offl & ~0xfffff));
c7a34993
MM		 584 }
585 break;
586 case PCI_HT_CMD_TYP_DR:
587 printf("HyperTransport: DirectRoute\n");
588 break;
589 case PCI_HT_CMD_TYP_VCS:
590 printf("HyperTransport: VCSet\n");
591 break;
592 case PCI_HT_CMD_TYP_RM:
593 printf("HyperTransport: Retry Mode\n");
594 break;
595 case PCI_HT_CMD_TYP_X86:
596 printf("HyperTransport: X86 (reserved)\n");
597 break;
598 default:
599 printf("HyperTransport: #%02x\n", type >> 11);
600 }
601}
602
603static void
604cap_msi(struct device *d, int where, int cap)
605{
606 int is64;
607 u32 t;
608 u16 w;
609
04885ef7
MW		 610 printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
611 FLAG(cap, PCI_MSI_FLAGS_ENABLE),
c7a34993
MM		 612 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
613 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
04885ef7
MW		 614 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
615 FLAG(cap, PCI_MSI_FLAGS_64BIT));
c7a34993
MM		 616 if (verbose < 2)
617 return;
618 is64 = cap & PCI_MSI_FLAGS_64BIT;
619 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
620 return;
621 printf("\t\tAddress: ");
622 if (is64)
623 {
624 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
625 w = get_conf_word(d, where + PCI_MSI_DATA_64);
626 printf("%08x", t);
627 }
628 else
629 w = get_conf_word(d, where + PCI_MSI_DATA_32);
630 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
631 printf("%08x Data: %04x\n", t, w);
632 if (cap & PCI_MSI_FLAGS_MASK_BIT)
633 {
634 u32 mask, pending;
635
636 if (is64)
637 {
638 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
639 return;
640 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
641 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
642 }
643 else
644 {
645 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
646 return;
647 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
648 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
649 }
650 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
651 }
652}
653
623ed0e1
BH		 654static int exp_downstream_port(int type)
655{
656 return type == PCI_EXP_TYPE_ROOT_PORT ||
657 type == PCI_EXP_TYPE_DOWNSTREAM ||
658 type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */
659}
660
41e49114 661static void show_power_limit(int value, int scale)
c7a34993
MM		 662{
663 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
41e49114 664
cac545f6 665 if (scale == 0 && value == 0xFF)
41e49114 666 {
cac545f6
PR		 667 printf(">600W");
668 return;
41e49114 669 }
cac545f6
PR		 670
671 if (scale == 0 && value >= 0xF0 && value <= 0xFE)
672 value = 250 + 25 * (value - 0xF0);
673
41e49114 674 printf("%gW", value * scales[scale]);
c7a34993
MM		 675}
676
677static const char *latency_l0s(int value)
678{
679 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
680 return latencies[value];
681}
682
683static const char *latency_l1(int value)
684{
685 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
686 return latencies[value];
687}
688
689static void cap_express_dev(struct device *d, int where, int type)
690{
691 u32 t;
692 u16 w;
693
694 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
0dc85d67 695 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
c7a34993 696 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
0dc85d67
BH		 697 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
698 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
699 printf(", Latency L0s %s, L1 %s",
c7a34993
MM		 700 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
701 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
0dc85d67 702 printf("\n");
c7a34993
MM		 703 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
704 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
705 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
706 printf(" AttnBtn%c AttnInd%c PwrInd%c",
707 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
708 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
5d602ff4
BH		 709 printf(" RBE%c",
710 FLAG(t, PCI_EXP_DEVCAP_RBE));
10168b84 711 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP))
5d602ff4 712 printf(" FLReset%c",
c7a34993 713 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
acf56dd2
BH		 714 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
715 (type == PCI_EXP_TYPE_PCI_BRIDGE))
41e49114
PR		 716 {
717 printf(" SlotPowerLimit ");
718 show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26);
719 }
651a352a 720 printf(" TEE-IO%c", FLAG(t, PCI_EXP_DEVCAP_TEE_IO));
c7a34993
MM		 721 printf("\n");
722
723 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
aca48104 724 printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
c7a34993
MM		 725 FLAG(w, PCI_EXP_DEVCTL_CERE),
726 FLAG(w, PCI_EXP_DEVCTL_NFERE),
727 FLAG(w, PCI_EXP_DEVCTL_FERE),
728 FLAG(w, PCI_EXP_DEVCTL_URRE));
729 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
730 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
731 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
732 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
733 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
734 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
77120d53 735 if (type == PCI_EXP_TYPE_PCI_BRIDGE)
c7a34993 736 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
10168b84 737 if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) &&
5d602ff4 738 (t & PCI_EXP_DEVCAP_FLRESET))
c7a34993
MM		 739 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
740 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
741 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
742 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
743
744 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
aca48104 745 printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
c7a34993
MM		 746 FLAG(w, PCI_EXP_DEVSTA_CED),
747 FLAG(w, PCI_EXP_DEVSTA_NFED),
748 FLAG(w, PCI_EXP_DEVSTA_FED),
749 FLAG(w, PCI_EXP_DEVSTA_URD),
750 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
751 FLAG(w, PCI_EXP_DEVSTA_TRPND));
752}
753
754static char *link_speed(int speed)
755{
756 switch (speed)
757 {
758 case 1:
759 return "2.5GT/s";
760 case 2:
761 return "5GT/s";
4dc4ff43
MM		 762 case 3:
763 return "8GT/s";
9628600b
GS		 764 case 4:
765 return "16GT/s";
caca31a0
GP		 766 case 5:
767 return "32GT/s";
5bdf63b6
GP		 768 case 6:
769 return "64GT/s";
c7a34993
MM		 770 default:
771 return "unknown";
772 }
773}
774
9f768120 775static char *link_compare(int type, int sta, int cap)
b47b5bd4 776{
b47b5bd4 777 if (sta > cap)
9f768120
MM		 778 return " (overdriven)";
779 if (sta == cap)
780 return "";
781 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) ||
782 (type == PCI_EXP_TYPE_PCIE_BRIDGE))
783 return "";
784 return " (downgraded)";
b47b5bd4
MM		 785}
786
c7a34993
MM		 787static char *aspm_support(int code)
788{
789 switch (code)
790 {
87bc7e64
BH		 791 case 0:
792 return "not supported";
c7a34993
MM		 793 case 1:
794 return "L0s";
4dc4ff43
MM		 795 case 2:
796 return "L1";
c7a34993
MM		 797 case 3:
798 return "L0s L1";
799 default:
800 return "unknown";
801 }
802}
803
804static const char *aspm_enabled(int code)
805{
806 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
807 return desc[code];
808}
809
810static void cap_express_link(struct device *d, int where, int type)
811{
b47b5bd4 812 u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
c7a34993
MM		 813 u16 w;
814
815 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
78996f1c 816 aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
b47b5bd4
MM		 817 cap_speed = t & PCI_EXP_LNKCAP_SPEED;
818 cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
78996f1c 819 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
c7a34993 820 t >> 24,
b47b5bd4 821 link_speed(cap_speed), cap_width,
78996f1c
BH		 822 aspm_support(aspm));
823 if (aspm)
824 {
825 printf(", Exit Latency ");
826 if (aspm & 1)
827 printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
828 if (aspm & 2)
829 printf("%sL1 %s", (aspm & 1) ? ", " : "",
830 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
831 }
832 printf("\n");
b7a807b4 833 printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
c7a34993
MM		 834 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
835 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
836 FLAG(t, PCI_EXP_LNKCAP_DLLA),
b7a807b4
MM		 837 FLAG(t, PCI_EXP_LNKCAP_LBNC),
838 FLAG(t, PCI_EXP_LNKCAP_AOC));
c7a34993
MM		 839
840 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
841 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
842 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
a1f57a29 843 (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
018f413c 844 printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
011ca4bb 845 printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
c7a34993 846 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
c7a34993
MM		 847 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
848 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
849 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
850 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
851 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
852 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
853
854 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
b47b5bd4
MM		 855 sta_speed = w & PCI_EXP_LNKSTA_SPEED;
856 sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
9f768120 857 printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n",
b47b5bd4 858 link_speed(sta_speed),
9f768120 859 link_compare(type, sta_speed, cap_speed),
b47b5bd4 860 sta_width,
9f768120 861 link_compare(type, sta_width, cap_width));
b47b5bd4 862 printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
c7a34993
MM		 863 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
864 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
865 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
866 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
867 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
868 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
869}
870
871static const char *indicator(int code)
872{
873 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
874 return names[code];
875}
876
877static void cap_express_slot(struct device *d, int where)
878{
879 u32 t;
880 u16 w;
881
882 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
5f6aca18 883 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
c7a34993
MM		 884 FLAG(t, PCI_EXP_SLTCAP_ATNB),
885 FLAG(t, PCI_EXP_SLTCAP_PWRC),
886 FLAG(t, PCI_EXP_SLTCAP_MRL),
887 FLAG(t, PCI_EXP_SLTCAP_ATNI),
888 FLAG(t, PCI_EXP_SLTCAP_PWRI),
889 FLAG(t, PCI_EXP_SLTCAP_HPC),
890 FLAG(t, PCI_EXP_SLTCAP_HPS));
41e49114
PR		 891 printf("\t\t\tSlot #%d, PowerLimit ",
892 (t & PCI_EXP_SLTCAP_PSN) >> 19);
893 show_power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15);
894 printf("; Interlock%c NoCompl%c\n",
c7a34993
MM		 895 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
896 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
897
898 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
899 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
900 FLAG(w, PCI_EXP_SLTCTL_ATNB),
901 FLAG(w, PCI_EXP_SLTCTL_PWRF),
902 FLAG(w, PCI_EXP_SLTCTL_MRLS),
903 FLAG(w, PCI_EXP_SLTCTL_PRSD),
904 FLAG(w, PCI_EXP_SLTCTL_CMDC),
905 FLAG(w, PCI_EXP_SLTCTL_HPIE),
906 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
907 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
908 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
909 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
910 FLAG(w, PCI_EXP_SLTCTL_PWRC),
911 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
912
913 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
914 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
915 FLAG(w, PCI_EXP_SLTSTA_ATNB),
916 FLAG(w, PCI_EXP_SLTSTA_PWRF),
917 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
918 FLAG(w, PCI_EXP_SLTSTA_CMDC),
919 FLAG(w, PCI_EXP_SLTSTA_PRES),
920 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
921 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
922 FLAG(w, PCI_EXP_SLTSTA_MRLS),
923 FLAG(w, PCI_EXP_SLTSTA_PRSD),
924 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
925}
926
927static void cap_express_root(struct device *d, int where)
928{
e6a11bb4
BH		 929 u32 w;
930
931 w = get_conf_word(d, where + PCI_EXP_RTCAP);
932 printf("\t\tRootCap: CRSVisible%c\n",
933 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
934
935 w = get_conf_word(d, where + PCI_EXP_RTCTL);
c7a34993
MM		 936 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
937 FLAG(w, PCI_EXP_RTCTL_SECEE),
938 FLAG(w, PCI_EXP_RTCTL_SENFEE),
939 FLAG(w, PCI_EXP_RTCTL_SEFEE),
940 FLAG(w, PCI_EXP_RTCTL_PMEIE),
941 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
942
23c27798 943 w = get_conf_long(d, where + PCI_EXP_RTSTA);
c7a34993
MM		 944 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
945 w & PCI_EXP_RTSTA_PME_REQID,
946 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
947 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
948}
949
950static const char *cap_express_dev2_timeout_range(int type)
951{
952 /* Decode Completion Timeout Ranges. */
953 switch (type)
954 {
955 case 0:
956 return "Not Supported";
957 case 1:
958 return "Range A";
959 case 2:
960 return "Range B";
961 case 3:
962 return "Range AB";
963 case 6:
964 return "Range BC";
965 case 7:
966 return "Range ABC";
967 case 14:
968 return "Range BCD";
969 case 15:
970 return "Range ABCD";
971 default:
972 return "Unknown";
973 }
974}
975
976static const char *cap_express_dev2_timeout_value(int type)
977{
978 /* Decode Completion Timeout Value. */
979 switch (type)
980 {
981 case 0:
982 return "50us to 50ms";
983 case 1:
984 return "50us to 100us";
985 case 2:
986 return "1ms to 10ms";
987 case 5:
988 return "16ms to 55ms";
989 case 6:
990 return "65ms to 210ms";
991 case 9:
992 return "260ms to 900ms";
993 case 10:
994 return "1s to 3.5s";
995 case 13:
996 return "4s to 13s";
997 case 14:
998 return "17s to 64s";
999 default:
1000 return "Unknown";
1001 }
1002}
1003
d4c91e40
MW		 1004static const char *cap_express_devcap2_obff(int obff)
1005{
1006 switch (obff)
1007 {
1008 case 1:
1009 return "Via message";
1010 case 2:
1011 return "Via WAKE#";
1012 case 3:
1013 return "Via message/WAKE#";
1014 default:
1015 return "Not Supported";
1016 }
1017}
1018
33226851
FL		 1019static const char *cap_express_devcap2_epr(int epr)
1020{
1021 switch (epr)
1022 {
1023 case 1:
1024 return "Dev Specific";
1025 case 2:
1026 return "Form Factor Dev Specific";
1027 case 3:
1028 return "Reserved";
1029 default:
1030 return "Not Supported";
1031 }
1032}
1033
1034static const char *cap_express_devcap2_lncls(int lncls)
1035{
1036 switch (lncls)
1037 {
1038 case 1:
1039 return "64byte cachelines";
1040 case 2:
1041 return "128byte cachelines";
1042 case 3:
1043 return "Reserved";
1044 default:
1045 return "Not Supported";
1046 }
1047}
1048
1049static const char *cap_express_devcap2_tphcomp(int tph)
1050{
1051 switch (tph)
1052 {
1053 case 1:
018f413c 1054 return "TPHComp+ ExtTPHComp-";
33226851
FL		 1055 case 2:
1056 /* Reserved; intentionally left blank */
1057 return "";
1058 case 3:
018f413c 1059 return "TPHComp+ ExtTPHComp+";
33226851 1060 default:
018f413c 1061 return "TPHComp- ExtTPHComp-";
33226851
FL		 1062 }
1063}
1064
d4c91e40
MW		 1065static const char *cap_express_devctl2_obff(int obff)
1066{
1067 switch (obff)
1068 {
1069 case 0:
1070 return "Disabled";
1071 case 1:
1072 return "Via message A";
1073 case 2:
1074 return "Via message B";
1075 case 3:
1076 return "Via WAKE#";
1077 default:
1078 return "Unknown";
1079 }
1080}
1081
ad431573
SB		 1082static int
1083device_has_memory_space_bar(struct device *d)
1084{
1085 struct pci_dev *p = d->dev;
1086 int i, found = 0;
1087
1088 for (i=0; i<6; i++)
dcd6913e 1089 if (p->base_addr[i] || p->size[i])
ad431573
SB		 1090 {
1091 if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
1092 {
1093 found = 1;
1094 break;
1095 }
1096 }
1097 return found;
1098}
1099
c7a34993
MM		 1100static void cap_express_dev2(struct device *d, int where, int type)
1101{
1102 u32 l;
1103 u16 w;
5371aab4 1104 int has_mem_bar = device_has_memory_space_bar(d);
c7a34993
MM		 1105
1106 l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
018f413c 1107 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
e79a4207
DL		 1108 cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)),
1109 FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS),
33226851
FL		 1110 FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
1111 FLAG(l, PCI_EXP_DEVCAP2_LTR));
018f413c 1112 printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
33226851
FL		 1113 FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP),
1114 FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ),
1115 cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)),
1116 FLAG(l, PCI_EXP_DEVCAP2_EXTFMT),
1117 FLAG(l, PCI_EXP_DEVCAP2_EE_TLP));
1118
1119 if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP))
1120 {
1121 printf(", MaxEETLPPrefixes %d",
1122 PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4);
1123 }
1124
1125 printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c",
1126 cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)),
1127 FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT));
1128 printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS));
1129
1130 if (type == PCI_EXP_TYPE_ROOT_PORT)
018f413c 1131 printf(" LN System CLS %s,",
33226851
FL		 1132 cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l)));
1133
1134 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT)
018f413c 1135 printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
33226851 1136
c7a34993 1137 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
e79a4207 1138 printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI));
c7a34993
MM		 1139 else
1140 printf("\n");
ad431573
SB		 1141 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1142 type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1143 {
c4cf2d1c 1144 printf("\t\t\t AtomicOpsCap:");
ad431573
SB		 1145 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1146 type == PCI_EXP_TYPE_DOWNSTREAM)
1147 printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1148 if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1149 printf(" 32bit%c 64bit%c 128bitCAS%c",
1150 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1151 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1152 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1153 printf("\n");
1154 }
c7a34993
MM		 1155
1156 w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
ba06b2f5 1157 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
e79a4207 1158 cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
ba06b2f5 1159 FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS));
c7a34993 1160 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
e79a4207 1161 printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
c7a34993
MM		 1162 else
1163 printf("\n");
ad431573
SB		 1164 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1165 type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1166 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1167 {
c4cf2d1c 1168 printf("\t\t\t AtomicOpsCtl:");
ad431573
SB		 1169 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1170 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
e79a4207 1171 printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN));
ad431573
SB		 1172 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1173 type == PCI_EXP_TYPE_DOWNSTREAM)
e79a4207 1174 printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
ad431573
SB		 1175 printf("\n");
1176 }
a99d27a3 1177 printf("\t\t\t IDOReq%c IDOCompl%c LTR%c EmergencyPowerReductionReq%c\n",
3746111d
BH		 1178 FLAG(w, PCI_EXP_DEVCTL2_IDO_REQ_EN),
1179 FLAG(w, PCI_EXP_DEVCTL2_IDO_CMP_EN),
ba06b2f5 1180 FLAG(w, PCI_EXP_DEVCTL2_LTR),
a99d27a3 1181 FLAG(w, PCI_EXP_DEVCTL2_EPR_REQ));
7d2b2d69 1182 printf("\t\t\t 10BitTagReq%c OBFF %s, EETLPPrefixBlk%c\n",
ba06b2f5 1183 FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
7d2b2d69
BH		 1184 cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)),
1185 FLAG(w, PCI_EXP_DEVCTL2_EE_TLP_BLK));
c7a34993
MM		 1186}
1187
623ed0e1
BH		 1188static const char *cap_express_link2_speed_cap(int vector)
1189{
1190 /*
1191 * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not
1192 * permitted to skip support for any data rates between 2.5GT/s and the
1193 * highest supported rate.
1194 */
90d270fa 1195 if (vector & 0x40)
623ed0e1 1196 return "RsvdP";
90d270fa
IJ		 1197 if (vector & 0x20)
1198 return "2.5-64GT/s";
623ed0e1
BH		 1199 if (vector & 0x10)
1200 return "2.5-32GT/s";
1201 if (vector & 0x08)
1202 return "2.5-16GT/s";
1203 if (vector & 0x04)
1204 return "2.5-8GT/s";
1205 if (vector & 0x02)
1206 return "2.5-5GT/s";
1207 if (vector & 0x01)
1208 return "2.5GT/s";
1209
1210 return "Unknown";
1211}
1212
c7a34993
MM		 1213static const char *cap_express_link2_speed(int type)
1214{
1215 switch (type)
1216 {
1217 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1218 case 1:
1219 return "2.5GT/s";
1220 case 2:
1221 return "5GT/s";
4dc4ff43
MM		 1222 case 3:
1223 return "8GT/s";
9628600b
GS		 1224 case 4:
1225 return "16GT/s";
caca31a0
GP		 1226 case 5:
1227 return "32GT/s";
5bdf63b6
GP		 1228 case 6:
1229 return "64GT/s";
c7a34993
MM		 1230 default:
1231 return "Unknown";
1232 }
1233}
1234
1235static const char *cap_express_link2_deemphasis(int type)
1236{
1237 switch (type)
1238 {
1239 case 0:
1240 return "-6dB";
1241 case 1:
1242 return "-3.5dB";
1243 default:
1244 return "Unknown";
1245 }
1246}
1247
ad140168
LB		 1248static const char *cap_express_link2_compliance_preset(int type)
1249{
1250 switch (type)
1251 {
1252 case 0:
1253 return "-6dB de-emphasis, 0dB preshoot";
1254 case 1:
1255 return "-3.5dB de-emphasis, 0dB preshoot";
1256 case 2:
1257 return "-4.4dB de-emphasis, 0dB preshoot";
1258 case 3:
1259 return "-2.5dB de-emphasis, 0dB preshoot";
1260 case 4:
1261 return "0dB de-emphasis, 0dB preshoot";
1262 case 5:
1263 return "0dB de-emphasis, 1.9dB preshoot";
1264 case 6:
1265 return "0dB de-emphasis, 2.5dB preshoot";
1266 case 7:
1267 return "-6.0dB de-emphasis, 3.5dB preshoot";
1268 case 8:
1269 return "-3.5dB de-emphasis, 3.5dB preshoot";
1270 case 9:
1271 return "0dB de-emphasis, 3.5dB preshoot";
1272 default:
1273 return "Unknown";
1274 }
1275}
1276
c7a34993
MM		 1277static const char *cap_express_link2_transmargin(int type)
1278{
1279 switch (type)
1280 {
1281 case 0:
1282 return "Normal Operating Range";
1283 case 1:
1284 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1285 case 2:
1286 case 3:
1287 case 4:
1288 case 5:
1289 return "200-400mV(full-swing)/100-200mV(half-swing)";
1290 default:
1291 return "Unknown";
1292 }
1293}
1294
623ed0e1
BH		 1295static const char *cap_express_link2_crosslink_res(int crosslink)
1296{
1297 switch (crosslink)
1298 {
1299 case 0:
1300 return "unsupported";
1301 case 1:
1302 return "Upstream Port";
1303 case 2:
1304 return "Downstream Port";
1305 default:
1306 return "incomplete";
1307 }
1308}
1309
1310static const char *cap_express_link2_component(int presence)
1311{
1312 switch (presence)
1313 {
1314 case 0:
1315 return "Link Down - Not Determined";
1316 case 1:
1317 return "Link Down - Not Present";
1318 case 2:
1319 return "Link Down - Present";
1320 case 4:
1321 return "Link Up - Present";
1322 case 5:
1323 return "Link Up - Present and DRS Received";
1324 default:
1325 return "Reserved";
1326 }
1327}
1328
37f8039d 1329static void cap_express_link2(struct device *d, int where, int type)
c7a34993 1330{
623ed0e1 1331 u32 l = 0;
c7a34993
MM		 1332 u16 w;
1333
37f8039d
BH		 1334 if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1335 (d->dev->dev != 0 || d->dev->func != 0))) {
623ed0e1
BH		 1336 /* Link Capabilities 2 was reserved before PCIe r3.0 */
1337 l = get_conf_long(d, where + PCI_EXP_LNKCAP2);
1338 if (l) {
1339 printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c "
1340 "Retimer%c 2Retimers%c DRS%c\n",
1341 cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)),
1342 FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK),
1343 FLAG(l, PCI_EXP_LNKCAP2_RETIMER),
1344 FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS),
1345 FLAG(l, PCI_EXP_LNKCAP2_DRS));
1346 }
1347
37f8039d
BH		 1348 w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1349 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
c7a34993
MM		 1350 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1351 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
37f8039d
BH		 1352 FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1353 if (type == PCI_EXP_TYPE_DOWNSTREAM)
1354 printf(", Selectable De-emphasis: %s",
1355 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1356 printf("\n"
1357 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
ad140168 1358 "\t\t\t Compliance Preset/De-emphasis: %s\n",
c7a34993
MM		 1359 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1360 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1361 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
ad140168 1362 cap_express_link2_compliance_preset(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
37f8039d 1363 }
c7a34993
MM		 1364
1365 w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
018f413c
BH		 1366 printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n"
1367 "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n"
623ed0e1 1368 "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s",
4dc4ff43
MM		 1369 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1370 FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1371 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1372 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1373 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
623ed0e1
BH		 1374 FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ),
1375 FLAG(w, PCI_EXP_LINKSTA2_RETIMER),
1376 FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS),
1377 cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)));
1378
1379 if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) {
1380 printf(", DRS%c\n"
1381 "\t\t\t DownstreamComp: %s\n",
1382 FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD),
1383 cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w)));
1384 } else
1385 printf("\n");
c7a34993
MM		 1386}
1387
1388static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1389{
1390 /* No capabilities that require this field in PCIe rev2.0 spec. */
1391}
1392
a1492b88 1393static int
c7a34993
MM		 1394cap_express(struct device *d, int where, int cap)
1395{
1396 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1397 int size;
1398 int slot = 0;
17ebd1d1 1399 int link = 1;
c7a34993
MM		 1400
1401 printf("Express ");
1402 if (verbose >= 2)
1403 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1404 switch (type)
1405 {
1406 case PCI_EXP_TYPE_ENDPOINT:
1407 printf("Endpoint");
1408 break;
1409 case PCI_EXP_TYPE_LEG_END:
1410 printf("Legacy Endpoint");
1411 break;
1412 case PCI_EXP_TYPE_ROOT_PORT:
1413 slot = cap & PCI_EXP_FLAGS_SLOT;
1414 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1415 break;
1416 case PCI_EXP_TYPE_UPSTREAM:
1417 printf("Upstream Port");
1418 break;
1419 case PCI_EXP_TYPE_DOWNSTREAM:
1420 slot = cap & PCI_EXP_FLAGS_SLOT;
1421 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1422 break;
1423 case PCI_EXP_TYPE_PCI_BRIDGE:
77120d53 1424 printf("PCI-Express to PCI/PCI-X Bridge");
c7a34993
MM		 1425 break;
1426 case PCI_EXP_TYPE_PCIE_BRIDGE:
f41bb847
BH		 1427 slot = cap & PCI_EXP_FLAGS_SLOT;
1428 printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1429 FLAG(cap, PCI_EXP_FLAGS_SLOT));
c7a34993
MM		 1430 break;
1431 case PCI_EXP_TYPE_ROOT_INT_EP:
17ebd1d1 1432 link = 0;
c7a34993
MM		 1433 printf("Root Complex Integrated Endpoint");
1434 break;
1435 case PCI_EXP_TYPE_ROOT_EC:
17ebd1d1 1436 link = 0;
c7a34993
MM		 1437 printf("Root Complex Event Collector");
1438 break;
1439 default:
1440 printf("Unknown type %d", type);
1441 }
aeb74fe2 1442 printf(", IntMsgNum %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
c7a34993 1443 if (verbose < 2)
a1492b88 1444 return type;
c7a34993
MM		 1445
1446 size = 16;
1447 if (slot)
1448 size = 24;
7155d510 1449 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
c7a34993
MM		 1450 size = 32;
1451 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
a1492b88 1452 return type;
c7a34993
MM		 1453
1454 cap_express_dev(d, where, type);
17ebd1d1
BH		 1455 if (link)
1456 cap_express_link(d, where, type);
c7a34993
MM		 1457 if (slot)
1458 cap_express_slot(d, where);
7155d510 1459 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
c7a34993
MM		 1460 cap_express_root(d, where);
1461
1462 if ((cap & PCI_EXP_FLAGS_VERS) < 2)
a1492b88 1463 return type;
c7a34993
MM		 1464
1465 size = 16;
1466 if (slot)
1467 size = 24;
1468 if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
a1492b88 1469 return type;
c7a34993
MM		 1470
1471 cap_express_dev2(d, where, type);
17ebd1d1
BH		 1472 if (link)
1473 cap_express_link2(d, where, type);
c7a34993
MM		 1474 if (slot)
1475 cap_express_slot2(d, where);
a1492b88 1476 return type;
c7a34993
MM		 1477}
1478
1479static void
1480cap_msix(struct device *d, int where, int cap)
1481{
1482 u32 off;
1483
04885ef7 1484 printf("MSI-X: Enable%c Count=%d Masked%c\n",
c7a34993 1485 FLAG(cap, PCI_MSIX_ENABLE),
04885ef7
MW		 1486 (cap & PCI_MSIX_TABSIZE) + 1,
1487 FLAG(cap, PCI_MSIX_MASK));
c7a34993
MM		 1488 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1489 return;
1490
1491 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1492 printf("\t\tVector table: BAR=%d offset=%08x\n",
1493 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1494 off = get_conf_long(d, where + PCI_MSIX_PBA);
1495 printf("\t\tPBA: BAR=%d offset=%08x\n",
1496 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1497}
1498
1499static void
1500cap_slotid(int cap)
1501{
1502 int esr = cap & 0xff;
1503 int chs = cap >> 8;
1504
1505 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1506 esr & PCI_SID_ESR_NSLOTS,
1507 FLAG(esr, PCI_SID_ESR_FIC),
1508 chs);
1509}
1510
1511static void
1512cap_ssvid(struct device *d, int where)
1513{
1514 u16 subsys_v, subsys_d;
1515 char ssnamebuf[256];
1516
1517 if (!config_fetch(d, where, 8))
1518 return;
1519 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1520 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1521 printf("Subsystem: %s\n",
1522 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1523 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1524 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1525}
1526
1527static void
1528cap_debug_port(int cap)
1529{
1530 int bar = cap >> 13;
1531 int pos = cap & 0x1fff;
1532 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1533}
1534
99eb76e5
YZ		 1535static void
1536cap_af(struct device *d, int where)
1537{
1538 u8 reg;
1539
1540 printf("PCI Advanced Features\n");
1541 if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1542 return;
1543
1544 reg = get_conf_byte(d, where + PCI_AF_CAP);
1545 printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1546 FLAG(reg, PCI_AF_CAP_FLR));
1547 reg = get_conf_byte(d, where + PCI_AF_CTRL);
1548 printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1549 reg = get_conf_byte(d, where + PCI_AF_STATUS);
1550 printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1551}
1552
be9c1b75
MM		 1553static void
1554cap_sata_hba(struct device *d, int where, int cap)
1555{
1556 u32 bars;
1557 int bar;
1558
1559 printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1560 if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1561 {
1562 printf("\n");
1563 return;
1564 }
1565
1566 bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1567 bar = BITS(bars, 0, 4);
1568 if (bar >= 4 && bar <= 9)
1569 printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1570 else if (bar == 15)
1571 printf(" InCfgSpace\n");
1572 else
1573 printf(" BAR??%d\n", bar);
1574}
1575
4cd841df
DD		 1576static const char *cap_ea_property(int p, int is_secondary)
1577{
1578 switch (p) {
1579 case 0x00:
1580 return "memory space, non-prefetchable";
1581 case 0x01:
1582 return "memory space, prefetchable";
1583 case 0x02:
1584 return "I/O space";
1585 case 0x03:
1586 return "VF memory space, prefetchable";
1587 case 0x04:
1588 return "VF memory space, non-prefetchable";
1589 case 0x05:
1590 return "allocation behind bridge, non-prefetchable memory";
1591 case 0x06:
1592 return "allocation behind bridge, prefetchable memory";
1593 case 0x07:
1594 return "allocation behind bridge, I/O space";
1595 case 0xfd:
1596 return "memory space resource unavailable for use";
1597 case 0xfe:
1598 return "I/O space resource unavailable for use";
1599 case 0xff:
1600 if (is_secondary)
1601 return "entry unavailable for use, PrimaryProperties should be used";
1602 else
1603 return "entry unavailable for use";
1604 default:
1605 return NULL;
1606 }
1607}
1608
1609static void cap_ea(struct device *d, int where, int cap)
1610{
1611 int entry;
1612 int entry_base = where + 4;
1613 int num_entries = BITS(cap, 0, 6);
1614 u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1615
1616 printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1617 if (htype == PCI_HEADER_TYPE_BRIDGE) {
1618 byte fixed_sub, fixed_sec;
1619
1620 entry_base += 4;
1621 if (!config_fetch(d, where + 4, 2)) {
1622 printf("\n");
1623 return;
1624 }
1625 fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1626 fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1627 printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1628 }
1629 printf("\n");
1630 if (verbose < 2)
1631 return;
1632
1633 for (entry = 0; entry < num_entries; entry++) {
1634 int max_offset_high_pos, has_base_high, has_max_offset_high;
1635 u32 entry_header;
1636 u32 base, max_offset;
1637 int es, bei, pp, sp;
1638 const char *prop_text;
1639
1640 if (!config_fetch(d, entry_base, 4))
1641 return;
1642 entry_header = get_conf_long(d, entry_base);
1643 es = BITS(entry_header, 0, 3);
1644 bei = BITS(entry_header, 4, 4);
1645 pp = BITS(entry_header, 8, 8);
1646 sp = BITS(entry_header, 16, 8);
1647 if (!config_fetch(d, entry_base + 4, es * 4))
1648 return;
1649 printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1650 FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1651 FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1652 printf("\t\t\t BAR Equivalent Indicator: ");
1653 switch (bei) {
1654 case 0:
1655 case 1:
1656 case 2:
1657 case 3:
1658 case 4:
1659 case 5:
1660 printf("BAR %u", bei);
1661 break;
1662 case 6:
1663 printf("resource behind function");
1664 break;
1665 case 7:
1666 printf("not indicated");
1667 break;
1668 case 8:
1669 printf("expansion ROM");
1670 break;
1671 case 9:
1672 case 10:
1673 case 11:
1674 case 12:
1675 case 13:
1676 case 14:
1677 printf("VF-BAR %u", bei - 9);
1678 break;
1679 default:
1680 printf("reserved");
1681 break;
1682 }
1683 printf("\n");
1684
1685 prop_text = cap_ea_property(pp, 0);
1686 printf("\t\t\t PrimaryProperties: ");
1687 if (prop_text)
1688 printf("%s\n", prop_text);
1689 else
1690 printf("[%02x]\n", pp);
1691
1692 prop_text = cap_ea_property(sp, 1);
1693 printf("\t\t\t SecondaryProperties: ");
1694 if (prop_text)
1695 printf("%s\n", prop_text);
1696 else
1697 printf("[%02x]\n", sp);
1698
1699 base = get_conf_long(d, entry_base + 4);
1700 has_base_high = ((base & 2) != 0);
1701 base &= ~3;
1702
1703 max_offset = get_conf_long(d, entry_base + 8);
1704 has_max_offset_high = ((max_offset & 2) != 0);
1705 max_offset |= 3;
1706 max_offset_high_pos = entry_base + 12;
1707
1708 printf("\t\t\t Base: ");
1709 if (has_base_high) {
1710 u32 base_high = get_conf_long(d, entry_base + 12);
1711
1712 printf("%x", base_high);
1713 max_offset_high_pos += 4;
1714 }
1715 printf("%08x\n", base);
1716
1717 printf("\t\t\t MaxOffset: ");
1718 if (has_max_offset_high) {
1719 u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1720
1721 printf("%x", max_offset_high);
1722 }
1723 printf("%08x\n", max_offset);
1724
1725 entry_base += 4 + 4 * es;
1726 }
1727}
1728
c7a34993 1729void
21510591 1730show_caps(struct device *d, int where)
c7a34993
MM		 1731{
1732 int can_have_ext_caps = 0;
a1492b88 1733 int type = -1;
c7a34993
MM		 1734
1735 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1736 {
c7a34993 1737 byte been_there[256];
01de4db1 1738 where = get_conf_byte(d, where) & ~3;
c7a34993
MM		 1739 memset(been_there, 0, 256);
1740 while (where)
1741 {
1742 int id, next, cap;
1743 printf("\tCapabilities: ");
1744 if (!config_fetch(d, where, 4))
1745 {
1746 puts("<access denied>");
1747 break;
1748 }
1749 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1750 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1751 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1752 printf("[%02x] ", where);
1753 if (been_there[where]++)
1754 {
1755 printf("<chain looped>\n");
1756 break;
1757 }
1758 if (id == 0xff)
1759 {
1760 printf("<chain broken>\n");
1761 break;
1762 }
1763 switch (id)
1764 {
c508d1c9
BH		 1765 case PCI_CAP_ID_NULL:
1766 printf("Null\n");
1767 break;
c7a34993
MM		 1768 case PCI_CAP_ID_PM:
1769 cap_pm(d, where, cap);
1770 break;
1771 case PCI_CAP_ID_AGP:
1772 cap_agp(d, where, cap);
1773 break;
1774 case PCI_CAP_ID_VPD:
1775 cap_vpd(d);
1776 break;
1777 case PCI_CAP_ID_SLOTID:
1778 cap_slotid(cap);
1779 break;
1780 case PCI_CAP_ID_MSI:
1781 cap_msi(d, where, cap);
1782 break;
1783 case PCI_CAP_ID_CHSWP:
1784 printf("CompactPCI hot-swap <?>\n");
1785 break;
1786 case PCI_CAP_ID_PCIX:
1787 cap_pcix(d, where);
1788 can_have_ext_caps = 1;
1789 break;
1790 case PCI_CAP_ID_HT:
1791 cap_ht(d, where, cap);
1792 break;
1793 case PCI_CAP_ID_VNDR:
7ff8a323 1794 show_vendor_caps(d, where, cap);
c7a34993
MM		 1795 break;
1796 case PCI_CAP_ID_DBG:
1797 cap_debug_port(cap);
1798 break;
1799 case PCI_CAP_ID_CCRC:
1800 printf("CompactPCI central resource control <?>\n");
1801 break;
1802 case PCI_CAP_ID_HOTPLUG:
1803 printf("Hot-plug capable\n");
1804 break;
1805 case PCI_CAP_ID_SSVID:
1806 cap_ssvid(d, where);
1807 break;
1808 case PCI_CAP_ID_AGP3:
1809 printf("AGP3 <?>\n");
1810 break;
1811 case PCI_CAP_ID_SECURE:
1812 printf("Secure device <?>\n");
1813 break;
1814 case PCI_CAP_ID_EXP:
a1492b88 1815 type = cap_express(d, where, cap);
c7a34993
MM		 1816 can_have_ext_caps = 1;
1817 break;
1818 case PCI_CAP_ID_MSIX:
1819 cap_msix(d, where, cap);
1820 break;
1821 case PCI_CAP_ID_SATA:
be9c1b75 1822 cap_sata_hba(d, where, cap);
c7a34993
MM		 1823 break;
1824 case PCI_CAP_ID_AF:
99eb76e5 1825 cap_af(d, where);
c7a34993 1826 break;
4cd841df
DD		 1827 case PCI_CAP_ID_EA:
1828 cap_ea(d, where, cap);
1829 break;
c7a34993 1830 default:
60a45a7e 1831 printf("Capability ID %#02x [%04x]\n", id, cap);
c7a34993
MM		 1832 }
1833 where = next;
1834 }
1835 }
1836 if (can_have_ext_caps)
a1492b88 1837 show_ext_caps(d, type);
c7a34993 1838}
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