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[thirdparty/pciutils.git] / ls-ecaps.c
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c7a34993
MM		 1/*
2 * The PCI Utilities -- Show Extended Capabilities
3 *
8f39f69e 4 * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
c7a34993
MM		 5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9#include <stdio.h>
10#include <string.h>
11
12#include "lspci.h"
13
67da1792
MM		 14static void
15cap_tph(struct device *d, int where)
16{
17 u32 tph_cap;
18 printf("Transaction Processing Hints\n");
19 if (verbose < 2)
20 return;
21
22 if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
23 return;
24
25 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
26
27 if (tph_cap & PCI_TPH_INTVEC_SUP)
28 printf("\t\tInterrupt vector mode supported\n");
29 if (tph_cap & PCI_TPH_DEV_SUP)
30 printf("\t\tDevice specific mode supported\n");
31 if (tph_cap & PCI_TPH_EXT_REQ_SUP)
32 printf("\t\tExtended requester support\n");
33
34 switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
35 case PCI_TPH_ST_NONE:
36 printf("\t\tNo steering table available\n");
37 break;
38 case PCI_TPH_ST_CAP:
39 printf("\t\tSteering table in TPH capability structure\n");
40 break;
41 case PCI_TPH_ST_MSIX:
42 printf("\t\tSteering table in MSI-X table\n");
43 break;
44 default:
45 printf("\t\tReserved steering table location\n");
46 break;
47 }
48}
49
50static u32
51cap_ltr_scale(u8 scale)
52{
53 return 1 << (scale * 5);
54}
55
56static void
57cap_ltr(struct device *d, int where)
58{
59 u32 scale;
60 u16 snoop, nosnoop;
61 printf("Latency Tolerance Reporting\n");
62 if (verbose < 2)
63 return;
64
65 if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
66 return;
67
68 snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
69 scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
70 printf("\t\tMax snoop latency: %lldns\n",
71 ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale);
72
73 nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
74 scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
75 printf("\t\tMax no snoop latency: %lldns\n",
76 ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale);
77}
78
c7a34993
MM		 79static void
80cap_dsn(struct device *d, int where)
81{
82 u32 t1, t2;
83 if (!config_fetch(d, where + 4, 8))
84 return;
85 t1 = get_conf_long(d, where + 4);
86 t2 = get_conf_long(d, where + 8);
87 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
6f9f8fd7
MW		 88 t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
89 t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
c7a34993
MM		 90}
91
92static void
a1492b88 93cap_aer(struct device *d, int where, int type)
c7a34993 94{
a6625432 95 u32 l, l0, l1, l2, l3;
a1492b88 96 u16 w;
c7a34993
MM		 97
98 printf("Advanced Error Reporting\n");
9a2e4b35
YZ		 99 if (verbose < 2)
100 return;
101
a6625432 102 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
c7a34993
MM		 103 return;
104
105 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
106 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
107 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
108 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
109 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
110 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
111 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
112 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
113 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
114 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
115 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
116 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
117 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
118 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
119 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
120 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
121 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
122 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
123 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
124 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
125 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
126 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
aca48104 127 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
c7a34993
MM		 128 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
129 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
130 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
aca48104 131 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
c7a34993
MM		 132 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
133 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
134 l = get_conf_long(d, where + PCI_ERR_CAP);
9a54979e 135 printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
b33a4a2b 136 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
c7a34993 137 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
b33a4a2b
BH		 138 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
139 FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
140 FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
a6625432
BH		 141
142 l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
143 l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
144 l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
145 l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
146 printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
a1492b88
BH		 147
148 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
149 {
150 if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12))
151 return;
152
153 l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND);
154 printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
155 FLAG(l, PCI_ERR_ROOT_CMD_COR_EN),
156 FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN),
157 FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN));
158
159 l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
160 printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
161 "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
162 FLAG(l, PCI_ERR_ROOT_COR_RCV),
163 FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
164 FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
165 FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV),
166 FLAG(l, PCI_ERR_ROOT_FIRST_FATAL),
167 FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV),
168 FLAG(l, PCI_ERR_ROOT_FATAL_RCV),
169 PCI_ERR_MSG_NUM(l));
170
171 w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC);
172 printf("\t\tErrorSrc: ERR_COR: %04x ", w);
173
174 w = get_conf_word(d, where + PCI_ERR_ROOT_SRC);
175 printf("ERR_FATAL/NONFATAL: %04x\n", w);
176 }
c7a34993
MM		 177}
178
de91b6f2
KB		 179static void cap_dpc(struct device *d, int where)
180{
181 u16 l;
182
183 printf("Downstream Port Containment\n");
184 if (verbose < 2)
185 return;
186
187 if (!config_fetch(d, where + PCI_DPC_CAP, 8))
188 return;
189
190 l = get_conf_word(d, where + PCI_DPC_CAP);
191 printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
192 PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
193 FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
194
195 l = get_conf_word(d, where + PCI_DPC_CTL);
196 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
197 PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
198 FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
199 FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
200
201 l = get_conf_word(d, where + PCI_DPC_STATUS);
202 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
203 FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
204 FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
205
206 l = get_conf_word(d, where + PCI_DPC_SOURCE);
207 printf("\t\tSource:\t%04x\n", l);
208}
209
c7a34993
MM		 210static void
211cap_acs(struct device *d, int where)
212{
213 u16 w;
214
215 printf("Access Control Services\n");
9a2e4b35
YZ		 216 if (verbose < 2)
217 return;
218
c7a34993
MM		 219 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
220 return;
221
222 w = get_conf_word(d, where + PCI_ACS_CAP);
223 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
224 "DirectTrans%c\n",
225 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
226 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
227 FLAG(w, PCI_ACS_CAP_TRANS));
228 w = get_conf_word(d, where + PCI_ACS_CTRL);
229 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
230 "DirectTrans%c\n",
231 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
232 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
233 FLAG(w, PCI_ACS_CTRL_TRANS));
234}
235
236static void
237cap_ari(struct device *d, int where)
238{
239 u16 w;
240
241 printf("Alternative Routing-ID Interpretation (ARI)\n");
9a2e4b35
YZ		 242 if (verbose < 2)
243 return;
244
c7a34993
MM		 245 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
246 return;
247
248 w = get_conf_word(d, where + PCI_ARI_CAP);
249 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
250 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
251 PCI_ARI_CAP_NFN(w));
252 w = get_conf_word(d, where + PCI_ARI_CTRL);
253 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
254 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
255 PCI_ARI_CTRL_FG(w));
256}
257
258static void
259cap_ats(struct device *d, int where)
260{
261 u16 w;
262
263 printf("Address Translation Service (ATS)\n");
9a2e4b35
YZ		 264 if (verbose < 2)
265 return;
266
c7a34993
MM		 267 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
268 return;
269
270 w = get_conf_word(d, where + PCI_ATS_CAP);
271 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
272 w = get_conf_word(d, where + PCI_ATS_CTRL);
273 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
274 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
275}
276
a858df0d
DW		 277static void
278cap_pri(struct device *d, int where)
279{
280 u16 w;
281 u32 l;
282
283 printf("Page Request Interface (PRI)\n");
284 if (verbose < 2)
285 return;
286
287 if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
288 return;
289
290 w = get_conf_word(d, where + PCI_PRI_CTRL);
bfd8658f 291 printf("\t\tPRICtl: Enable%c Reset%c\n",
a858df0d
DW		 292 FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
293 w = get_conf_word(d, where + PCI_PRI_STATUS);
bfd8658f 294 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
a858df0d
DW		 295 FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
296 FLAG(w, PCI_PRI_STATUS_STOPPED));
297 l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
298 printf("\t\tPage Request Capacity: %08x, ", l);
299 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
300 printf("Page Request Allocation: %08x\n", l);
301}
302
303static void
304cap_pasid(struct device *d, int where)
305{
306 u16 w;
307
308 printf("Process Address Space ID (PASID)\n");
309 if (verbose < 2)
310 return;
311
312 if (!config_fetch(d, where + PCI_PASID_CAP, 4))
313 return;
314
315 w = get_conf_word(d, where + PCI_PASID_CAP);
bfd8658f 316 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
a858df0d
DW		 317 FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
318 PCI_PASID_CAP_WIDTH(w));
319 w = get_conf_word(d, where + PCI_PASID_CTRL);
bfd8658f 320 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
a858df0d
DW		 321 FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
322 FLAG(w, PCI_PASID_CTRL_PRIV));
323}
324
c7a34993
MM		 325static void
326cap_sriov(struct device *d, int where)
327{
328 u16 b;
329 u16 w;
330 u32 l;
67e78b32 331 int i;
c7a34993
MM		 332
333 printf("Single Root I/O Virtualization (SR-IOV)\n");
9a2e4b35
YZ		 334 if (verbose < 2)
335 return;
336
c7a34993
MM		 337 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
338 return;
339
340 l = get_conf_long(d, where + PCI_IOV_CAP);
341 printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
342 FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
343 w = get_conf_word(d, where + PCI_IOV_CTRL);
344 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
345 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
346 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
347 FLAG(w, PCI_IOV_CTRL_ARI));
348 w = get_conf_word(d, where + PCI_IOV_STATUS);
349 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
350 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
351 printf("\t\tInitial VFs: %d, ", w);
352 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
353 printf("Total VFs: %d, ", w);
354 w = get_conf_word(d, where + PCI_IOV_NUMVF);
355 printf("Number of VFs: %d, ", w);
356 b = get_conf_byte(d, where + PCI_IOV_FDL);
357 printf("Function Dependency Link: %02x\n", b);
358 w = get_conf_word(d, where + PCI_IOV_OFFSET);
359 printf("\t\tVF offset: %d, ", w);
360 w = get_conf_word(d, where + PCI_IOV_STRIDE);
361 printf("stride: %d, ", w);
362 w = get_conf_word(d, where + PCI_IOV_DID);
363 printf("Device ID: %04x\n", w);
364 l = get_conf_long(d, where + PCI_IOV_SUPPS);
365 printf("\t\tSupported Page Size: %08x, ", l);
366 l = get_conf_long(d, where + PCI_IOV_SYSPS);
367 printf("System Page Size: %08x\n", l);
b9e11c65
MM		 368
369 for (i=0; i < PCI_IOV_NUM_BAR; i++)
370 {
187bf2f5 371 u32 addr;
b9e11c65
MM		 372 int type;
373 u32 h;
374 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
375 if (l == 0xffffffff)
376 l = 0;
377 if (!l)
378 continue;
379 printf("\t\tRegion %d: Memory at ", i);
380 addr = l & PCI_ADDR_MEM_MASK;
381 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
382 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
383 {
384 i++;
385 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
187bf2f5 386 printf("%08x", h);
b9e11c65 387 }
187bf2f5
MM		 388 printf("%08x (%s-bit, %sprefetchable)\n",
389 addr,
b9e11c65
MM		 390 (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
391 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
67e78b32 392 }
b9e11c65 393
edca3520 394 l = get_conf_long(d, where + PCI_IOV_MSAO);
c7a34993
MM		 395 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
396 PCI_IOV_MSA_BIR(l));
397}
398
33088c24
MM		 399static void
400cap_vc(struct device *d, int where)
401{
402 u32 cr1, cr2;
403 u16 ctrl, status;
404 int evc_cnt;
405 int arb_table_pos;
406 int i, j;
3d8b5258 407 static const char ref_clocks[][6] = { "100ns" };
3edae14a
MM		 408 static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
409 static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
3d8b5258 410 char buf[8];
33088c24
MM		 411
412 printf("Virtual Channel\n");
413 if (verbose < 2)
414 return;
415
416 if (!config_fetch(d, where + 4, 0x1c - 4))
417 return;
418
419 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
420 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
421 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
422 status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
423
3d8b5258 424 evc_cnt = BITS(cr1, 0, 3);
d676f20d 425 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
3d8b5258
MM		 426 BITS(cr1, 4, 3),
427 TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
d676f20d 428 1 << BITS(cr1, 10, 2));
33088c24 429
d676f20d 430 printf("\t\tArb:");
33088c24
MM		 431 for (i=0; i<8; i++)
432 if (arb_selects[i][0] != '?' || cr2 & (1 << i))
d676f20d 433 printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
3d8b5258 434 arb_table_pos = BITS(cr2, 24, 8);
33088c24 435
d676f20d 436 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
33088c24
MM		 437 printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
438
439 if (arb_table_pos)
d676f20d
MM		 440 {
441 arb_table_pos = where + 16*arb_table_pos;
442 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
443 }
33088c24
MM		 444
445 for (i=0; i<=evc_cnt; i++)
446 {
447 int pos = where + PCI_VC_RES_CAP + 12*i;
448 u32 rcap, rctrl;
449 u16 rstatus;
450 int pat_pos;
451
5a9a932c 452 printf("\t\tVC%d:\t", i);
33088c24
MM		 453 if (!config_fetch(d, pos, 12))
454 {
5a9a932c 455 printf("<unreadable>\n");
33088c24
MM		 456 continue;
457 }
458 rcap = get_conf_long(d, pos);
459 rctrl = get_conf_long(d, pos+4);
7970509b 460 rstatus = get_conf_word(d, pos+10);
33088c24 461
3d8b5258 462 pat_pos = BITS(rcap, 24, 8);
5a9a932c 463 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
33088c24 464 pat_pos,
3d8b5258 465 BITS(rcap, 16, 6) + 1,
33088c24
MM		 466 FLAG(rcap, 1 << 15));
467
468 printf("\t\t\tArb:");
469 for (j=0; j<8; j++)
470 if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
471 printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
472
473 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
474 FLAG(rctrl, 1 << 31),
3d8b5258
MM		 475 BITS(rctrl, 24, 3),
476 TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
477 BITS(rctrl, 0, 8));
33088c24
MM		 478
479 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
480 FLAG(rstatus, 2),
481 FLAG(rstatus, 1));
482
483 if (pat_pos)
484 printf("\t\t\tPort Arbitration Table <?>\n");
485 }
486}
487
5a9a932c
MM		 488static void
489cap_rclink(struct device *d, int where)
490{
491 u32 esd;
492 int num_links;
493 int i;
494 static const char elt_types[][9] = { "Config", "Egress", "Internal" };
495 char buf[8];
496
497 printf("Root Complex Link\n");
498 if (verbose < 2)
499 return;
500
501 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
502 return;
503
504 esd = get_conf_long(d, where + PCI_RCLINK_ESD);
505 num_links = BITS(esd, 8, 8);
506 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
507 BITS(esd, 24, 8),
508 BITS(esd, 16, 8),
509 TABLE(elt_types, BITS(esd, 0, 8), buf));
510
511 for (i=0; i<num_links; i++)
512 {
513 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
514 u32 desc;
515 u32 addr_lo, addr_hi;
516
517 printf("\t\tLink%d:\t", i);
518 if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
519 {
520 printf("<unreadable>\n");
521 return;
522 }
523 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
524 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
525 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
526
527 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
528 BITS(desc, 24, 8),
529 BITS(desc, 16, 8),
530 FLAG(desc, 4),
531 ((desc & 2) ? "Config" : "MemMapped"),
532 FLAG(desc, 1));
533
534 if (desc & 2)
535 {
536 int n = addr_lo & 7;
537 if (!n)
538 n = 8;
539 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
540 BITS(addr_lo, 20, n),
541 BITS(addr_lo, 15, 5),
542 BITS(addr_lo, 12, 3),
543 addr_hi, addr_lo);
544 }
545 else
546 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
547 }
548}
549
78ca9582
MM		 550static void
551cap_evendor(struct device *d, int where)
552{
553 u32 hdr;
554
555 printf("Vendor Specific Information: ");
556 if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
557 {
558 printf("<unreadable>\n");
559 return;
560 }
561
562 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
563 printf("ID=%04x Rev=%d Len=%03x <?>\n",
564 BITS(hdr, 0, 16),
565 BITS(hdr, 16, 4),
566 BITS(hdr, 20, 12));
567}
568
fb17077d 569static int l1pm_calc_pwron(int scale, int value)
8efbe075
RJ		 570{
571 switch (scale)
572 {
573 case 0:
574 return 2 * value;
575 case 1:
576 return 10 * value;
577 case 2:
578 return 100 * value;
579 }
580 return -1;
581}
582
214c9a95
DB		 583static void
584cap_l1pm(struct device *d, int where)
585{
8efbe075
RJ		 586 u32 l1_cap, val, scale;
587 int time;
214c9a95
DB		 588
589 printf("L1 PM Substates\n");
590
591 if (verbose < 2)
592 return;
593
8efbe075 594 if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
214c9a95
DB		 595 {
596 printf("\t\t<unreadable>\n");
597 return;
598 }
599
8efbe075 600 l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
214c9a95 601 printf("\t\tL1SubCap: ");
e495466c 602 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
8efbe075
RJ		 603 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
604 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
605 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
606 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
607 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
608
fb17077d 609 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
214c9a95 610 {
fb17077d 611 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
8efbe075
RJ		 612 time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
613 if (time != -1)
614 printf("PortTPowerOnTime=%dus\n", time);
615 else
616 printf("PortTPowerOnTime=<error>\n");
617 }
214c9a95 618
8efbe075 619 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
fb17077d 620 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
8efbe075
RJ		 621 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
622 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
623 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
624 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
625
fb17077d
MM		 626 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
627 printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8));
8efbe075
RJ		 628
629 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
630 {
631 scale = BITS(val, 29, 3);
632 if (scale > 5)
fb17077d 633 printf(" LTR1.2_Threshold=<error>");
8efbe075 634 else
fb17077d 635 printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale));
8efbe075 636 }
fb17077d 637 printf("\n");
8efbe075
RJ		 638
639 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
fb17077d
MM		 640 printf("\t\tL1SubCtl2:");
641 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
8efbe075
RJ		 642 {
643 time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
644 if (time != -1)
fb17077d 645 printf(" T_PwrOn=%dus", time);
8efbe075 646 else
fb17077d 647 printf(" T_PwrOn=<error>");
214c9a95 648 }
fb17077d 649 printf("\n");
214c9a95
DB		 650}
651
415a9c18
YJ		 652static void
653cap_ptm(struct device *d, int where)
654{
655 u32 buff;
656 u16 clock;
657
658 printf("Precision Time Measurement\n");
659
660 if (verbose < 2)
661 return;
662
663 if (!config_fetch(d, where + 4, 8))
664 {
665 printf("\t\t<unreadable>\n");
666 return;
667 }
668
669 buff = get_conf_long(d, where + 4);
670 printf("\t\tPTMCap: ");
671 printf("Requester:%c Responder:%c Root:%c\n",
672 FLAG(buff, 0x1),
673 FLAG(buff, 0x2),
674 FLAG(buff, 0x4));
675
676 clock = BITS(buff, 8, 8);
677 printf("\t\tPTMClockGranularity: ");
678 switch (clock)
679 {
680 case 0x00:
681 printf("Unimplemented\n");
682 break;
683 case 0xff:
684 printf("Greater than 254ns\n");
685 break;
686 default:
687 printf("%huns\n", clock);
688 }
689
690 buff = get_conf_long(d, where + 8);
691 printf("\t\tPTMControl: ");
692 printf("Enabled:%c RootSelected:%c\n",
693 FLAG(buff, 0x1),
694 FLAG(buff, 0x2));
695
696 clock = BITS(buff, 8, 8);
697 printf("\t\tPTMEffectiveGranularity: ");
698 switch (clock)
699 {
700 case 0x00:
701 printf("Unknown\n");
702 break;
703 case 0xff:
704 printf("Greater than 254ns\n");
705 break;
706 default:
707 printf("%huns\n", clock);
708 }
709}
710
c7a34993 711void
a1492b88 712show_ext_caps(struct device *d, int type)
c7a34993
MM		 713{
714 int where = 0x100;
715 char been_there[0x1000];
716 memset(been_there, 0, 0x1000);
717 do
718 {
719 u32 header;
33088c24 720 int id, version;
c7a34993
MM		 721
722 if (!config_fetch(d, where, 4))
723 break;
724 header = get_conf_long(d, where);
725 if (!header)
726 break;
727 id = header & 0xffff;
33088c24
MM		 728 version = (header >> 16) & 0xf;
729 printf("\tCapabilities: [%03x", where);
730 if (verbose > 1)
731 printf(" v%d", version);
732 printf("] ");
c7a34993
MM		 733 if (been_there[where]++)
734 {
735 printf("<chain looped>\n");
736 break;
737 }
738 switch (id)
739 {
740 case PCI_EXT_CAP_ID_AER:
a1492b88 741 cap_aer(d, where, type);
c7a34993 742 break;
de91b6f2
KB		 743 case PCI_EXT_CAP_ID_DPC:
744 cap_dpc(d, where);
745 break;
c7a34993 746 case PCI_EXT_CAP_ID_VC:
33088c24
MM		 747 case PCI_EXT_CAP_ID_VC2:
748 cap_vc(d, where);
c7a34993
MM		 749 break;
750 case PCI_EXT_CAP_ID_DSN:
751 cap_dsn(d, where);
752 break;
753 case PCI_EXT_CAP_ID_PB:
754 printf("Power Budgeting <?>\n");
755 break;
756 case PCI_EXT_CAP_ID_RCLINK:
5a9a932c 757 cap_rclink(d, where);
c7a34993
MM		 758 break;
759 case PCI_EXT_CAP_ID_RCILINK:
760 printf("Root Complex Internal Link <?>\n");
761 break;
762 case PCI_EXT_CAP_ID_RCECOLL:
763 printf("Root Complex Event Collector <?>\n");
764 break;
765 case PCI_EXT_CAP_ID_MFVC:
766 printf("Multi-Function Virtual Channel <?>\n");
767 break;
768 case PCI_EXT_CAP_ID_RBCB:
769 printf("Root Bridge Control Block <?>\n");
770 break;
771 case PCI_EXT_CAP_ID_VNDR:
78ca9582 772 cap_evendor(d, where);
c7a34993
MM		 773 break;
774 case PCI_EXT_CAP_ID_ACS:
775 cap_acs(d, where);
776 break;
777 case PCI_EXT_CAP_ID_ARI:
778 cap_ari(d, where);
779 break;
780 case PCI_EXT_CAP_ID_ATS:
781 cap_ats(d, where);
782 break;
783 case PCI_EXT_CAP_ID_SRIOV:
784 cap_sriov(d, where);
785 break;
a858df0d
DW		 786 case PCI_EXT_CAP_ID_PRI:
787 cap_pri(d, where);
788 break;
67da1792
MM		 789 case PCI_EXT_CAP_ID_TPH:
790 cap_tph(d, where);
791 break;
792 case PCI_EXT_CAP_ID_LTR:
793 cap_ltr(d, where);
794 break;
a858df0d
DW		 795 case PCI_EXT_CAP_ID_PASID:
796 cap_pasid(d, where);
797 break;
214c9a95
DB		 798 case PCI_EXT_CAP_ID_L1PM:
799 cap_l1pm(d, where);
800 break;
415a9c18
YJ		 801 case PCI_EXT_CAP_ID_PTM:
802 cap_ptm(d, where);
803 break;
c7a34993
MM		 804 default:
805 printf("#%02x\n", id);
806 break;
807 }
d61c4772 808 where = (header >> 20) & ~3;
c7a34993
MM		 809 } while (where);
810}
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