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Commit | Line | Data |
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c7a34993 MM |
1 | /* |
2 | * The PCI Utilities -- Show Extended Capabilities | |
3 | * | |
8f39f69e | 4 | * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz> |
c7a34993 MM |
5 | * |
6 | * Can be freely distributed and used under the terms of the GNU GPL. | |
7 | */ | |
8 | ||
9 | #include <stdio.h> | |
10 | #include <string.h> | |
11 | ||
12 | #include "lspci.h" | |
13 | ||
67da1792 MM |
14 | static void |
15 | cap_tph(struct device *d, int where) | |
16 | { | |
17 | u32 tph_cap; | |
18 | printf("Transaction Processing Hints\n"); | |
19 | if (verbose < 2) | |
20 | return; | |
21 | ||
22 | if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4)) | |
23 | return; | |
24 | ||
25 | tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES); | |
26 | ||
27 | if (tph_cap & PCI_TPH_INTVEC_SUP) | |
28 | printf("\t\tInterrupt vector mode supported\n"); | |
29 | if (tph_cap & PCI_TPH_DEV_SUP) | |
30 | printf("\t\tDevice specific mode supported\n"); | |
31 | if (tph_cap & PCI_TPH_EXT_REQ_SUP) | |
32 | printf("\t\tExtended requester support\n"); | |
33 | ||
34 | switch (tph_cap & PCI_TPH_ST_LOC_MASK) { | |
35 | case PCI_TPH_ST_NONE: | |
36 | printf("\t\tNo steering table available\n"); | |
37 | break; | |
38 | case PCI_TPH_ST_CAP: | |
39 | printf("\t\tSteering table in TPH capability structure\n"); | |
40 | break; | |
41 | case PCI_TPH_ST_MSIX: | |
42 | printf("\t\tSteering table in MSI-X table\n"); | |
43 | break; | |
44 | default: | |
45 | printf("\t\tReserved steering table location\n"); | |
46 | break; | |
47 | } | |
48 | } | |
49 | ||
50 | static u32 | |
51 | cap_ltr_scale(u8 scale) | |
52 | { | |
53 | return 1 << (scale * 5); | |
54 | } | |
55 | ||
56 | static void | |
57 | cap_ltr(struct device *d, int where) | |
58 | { | |
59 | u32 scale; | |
60 | u16 snoop, nosnoop; | |
61 | printf("Latency Tolerance Reporting\n"); | |
62 | if (verbose < 2) | |
63 | return; | |
64 | ||
65 | if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4)) | |
66 | return; | |
67 | ||
68 | snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP); | |
69 | scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); | |
70 | printf("\t\tMax snoop latency: %lldns\n", | |
71 | ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale); | |
72 | ||
73 | nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP); | |
74 | scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); | |
75 | printf("\t\tMax no snoop latency: %lldns\n", | |
76 | ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale); | |
77 | } | |
78 | ||
c7a34993 MM |
79 | static void |
80 | cap_dsn(struct device *d, int where) | |
81 | { | |
82 | u32 t1, t2; | |
83 | if (!config_fetch(d, where + 4, 8)) | |
84 | return; | |
85 | t1 = get_conf_long(d, where + 4); | |
86 | t2 = get_conf_long(d, where + 8); | |
87 | printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", | |
6f9f8fd7 MW |
88 | t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff, |
89 | t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff); | |
c7a34993 MM |
90 | } |
91 | ||
92 | static void | |
93 | cap_aer(struct device *d, int where) | |
94 | { | |
95 | u32 l; | |
96 | ||
97 | printf("Advanced Error Reporting\n"); | |
9a2e4b35 YZ |
98 | if (verbose < 2) |
99 | return; | |
100 | ||
c7a34993 MM |
101 | if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24)) |
102 | return; | |
103 | ||
104 | l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS); | |
105 | printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c " | |
106 | "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n", | |
107 | FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), | |
108 | FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), | |
109 | FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), | |
110 | FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); | |
111 | l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK); | |
112 | printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c " | |
113 | "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n", | |
114 | FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), | |
115 | FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), | |
116 | FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), | |
117 | FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); | |
118 | l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER); | |
119 | printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c " | |
120 | "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n", | |
121 | FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), | |
122 | FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), | |
123 | FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), | |
124 | FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); | |
125 | l = get_conf_long(d, where + PCI_ERR_COR_STATUS); | |
126 | printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n", | |
127 | FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), | |
128 | FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); | |
129 | l = get_conf_long(d, where + PCI_ERR_COR_MASK); | |
130 | printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n", | |
131 | FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), | |
132 | FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); | |
133 | l = get_conf_long(d, where + PCI_ERR_CAP); | |
134 | printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n", | |
135 | PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE), | |
136 | FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE)); | |
137 | ||
138 | } | |
139 | ||
de91b6f2 KB |
140 | static void cap_dpc(struct device *d, int where) |
141 | { | |
142 | u16 l; | |
143 | ||
144 | printf("Downstream Port Containment\n"); | |
145 | if (verbose < 2) | |
146 | return; | |
147 | ||
148 | if (!config_fetch(d, where + PCI_DPC_CAP, 8)) | |
149 | return; | |
150 | ||
151 | l = get_conf_word(d, where + PCI_DPC_CAP); | |
152 | printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", | |
153 | PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK), | |
154 | FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR)); | |
155 | ||
156 | l = get_conf_word(d, where + PCI_DPC_CTL); | |
157 | printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n", | |
158 | PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT), | |
159 | FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER), | |
160 | FLAG(l, PCI_DPC_CTL_DL_ACTIVE)); | |
161 | ||
162 | l = get_conf_word(d, where + PCI_DPC_STATUS); | |
163 | printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n", | |
164 | FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT), | |
165 | FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l)); | |
166 | ||
167 | l = get_conf_word(d, where + PCI_DPC_SOURCE); | |
168 | printf("\t\tSource:\t%04x\n", l); | |
169 | } | |
170 | ||
c7a34993 MM |
171 | static void |
172 | cap_acs(struct device *d, int where) | |
173 | { | |
174 | u16 w; | |
175 | ||
176 | printf("Access Control Services\n"); | |
9a2e4b35 YZ |
177 | if (verbose < 2) |
178 | return; | |
179 | ||
c7a34993 MM |
180 | if (!config_fetch(d, where + PCI_ACS_CAP, 4)) |
181 | return; | |
182 | ||
183 | w = get_conf_word(d, where + PCI_ACS_CAP); | |
184 | printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c " | |
185 | "DirectTrans%c\n", | |
186 | FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED), | |
187 | FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS), | |
188 | FLAG(w, PCI_ACS_CAP_TRANS)); | |
189 | w = get_conf_word(d, where + PCI_ACS_CTRL); | |
190 | printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c " | |
191 | "DirectTrans%c\n", | |
192 | FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED), | |
193 | FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS), | |
194 | FLAG(w, PCI_ACS_CTRL_TRANS)); | |
195 | } | |
196 | ||
197 | static void | |
198 | cap_ari(struct device *d, int where) | |
199 | { | |
200 | u16 w; | |
201 | ||
202 | printf("Alternative Routing-ID Interpretation (ARI)\n"); | |
9a2e4b35 YZ |
203 | if (verbose < 2) |
204 | return; | |
205 | ||
c7a34993 MM |
206 | if (!config_fetch(d, where + PCI_ARI_CAP, 4)) |
207 | return; | |
208 | ||
209 | w = get_conf_word(d, where + PCI_ARI_CAP); | |
210 | printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n", | |
211 | FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS), | |
212 | PCI_ARI_CAP_NFN(w)); | |
213 | w = get_conf_word(d, where + PCI_ARI_CTRL); | |
214 | printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n", | |
215 | FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS), | |
216 | PCI_ARI_CTRL_FG(w)); | |
217 | } | |
218 | ||
219 | static void | |
220 | cap_ats(struct device *d, int where) | |
221 | { | |
222 | u16 w; | |
223 | ||
224 | printf("Address Translation Service (ATS)\n"); | |
9a2e4b35 YZ |
225 | if (verbose < 2) |
226 | return; | |
227 | ||
c7a34993 MM |
228 | if (!config_fetch(d, where + PCI_ATS_CAP, 4)) |
229 | return; | |
230 | ||
231 | w = get_conf_word(d, where + PCI_ATS_CAP); | |
232 | printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w)); | |
233 | w = get_conf_word(d, where + PCI_ATS_CTRL); | |
234 | printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n", | |
235 | FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w)); | |
236 | } | |
237 | ||
a858df0d DW |
238 | static void |
239 | cap_pri(struct device *d, int where) | |
240 | { | |
241 | u16 w; | |
242 | u32 l; | |
243 | ||
244 | printf("Page Request Interface (PRI)\n"); | |
245 | if (verbose < 2) | |
246 | return; | |
247 | ||
248 | if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc)) | |
249 | return; | |
250 | ||
251 | w = get_conf_word(d, where + PCI_PRI_CTRL); | |
bfd8658f | 252 | printf("\t\tPRICtl: Enable%c Reset%c\n", |
a858df0d DW |
253 | FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET)); |
254 | w = get_conf_word(d, where + PCI_PRI_STATUS); | |
bfd8658f | 255 | printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n", |
a858df0d DW |
256 | FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI), |
257 | FLAG(w, PCI_PRI_STATUS_STOPPED)); | |
258 | l = get_conf_long(d, where + PCI_PRI_MAX_REQ); | |
259 | printf("\t\tPage Request Capacity: %08x, ", l); | |
260 | l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ); | |
261 | printf("Page Request Allocation: %08x\n", l); | |
262 | } | |
263 | ||
264 | static void | |
265 | cap_pasid(struct device *d, int where) | |
266 | { | |
267 | u16 w; | |
268 | ||
269 | printf("Process Address Space ID (PASID)\n"); | |
270 | if (verbose < 2) | |
271 | return; | |
272 | ||
273 | if (!config_fetch(d, where + PCI_PASID_CAP, 4)) | |
274 | return; | |
275 | ||
276 | w = get_conf_word(d, where + PCI_PASID_CAP); | |
bfd8658f | 277 | printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n", |
a858df0d DW |
278 | FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV), |
279 | PCI_PASID_CAP_WIDTH(w)); | |
280 | w = get_conf_word(d, where + PCI_PASID_CTRL); | |
bfd8658f | 281 | printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n", |
a858df0d DW |
282 | FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC), |
283 | FLAG(w, PCI_PASID_CTRL_PRIV)); | |
284 | } | |
285 | ||
c7a34993 MM |
286 | static void |
287 | cap_sriov(struct device *d, int where) | |
288 | { | |
289 | u16 b; | |
290 | u16 w; | |
291 | u32 l; | |
67e78b32 | 292 | int i; |
c7a34993 MM |
293 | |
294 | printf("Single Root I/O Virtualization (SR-IOV)\n"); | |
9a2e4b35 YZ |
295 | if (verbose < 2) |
296 | return; | |
297 | ||
c7a34993 MM |
298 | if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c)) |
299 | return; | |
300 | ||
301 | l = get_conf_long(d, where + PCI_IOV_CAP); | |
302 | printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n", | |
303 | FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l)); | |
304 | w = get_conf_word(d, where + PCI_IOV_CTRL); | |
305 | printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n", | |
306 | FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME), | |
307 | FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE), | |
308 | FLAG(w, PCI_IOV_CTRL_ARI)); | |
309 | w = get_conf_word(d, where + PCI_IOV_STATUS); | |
310 | printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS)); | |
311 | w = get_conf_word(d, where + PCI_IOV_INITIALVF); | |
312 | printf("\t\tInitial VFs: %d, ", w); | |
313 | w = get_conf_word(d, where + PCI_IOV_TOTALVF); | |
314 | printf("Total VFs: %d, ", w); | |
315 | w = get_conf_word(d, where + PCI_IOV_NUMVF); | |
316 | printf("Number of VFs: %d, ", w); | |
317 | b = get_conf_byte(d, where + PCI_IOV_FDL); | |
318 | printf("Function Dependency Link: %02x\n", b); | |
319 | w = get_conf_word(d, where + PCI_IOV_OFFSET); | |
320 | printf("\t\tVF offset: %d, ", w); | |
321 | w = get_conf_word(d, where + PCI_IOV_STRIDE); | |
322 | printf("stride: %d, ", w); | |
323 | w = get_conf_word(d, where + PCI_IOV_DID); | |
324 | printf("Device ID: %04x\n", w); | |
325 | l = get_conf_long(d, where + PCI_IOV_SUPPS); | |
326 | printf("\t\tSupported Page Size: %08x, ", l); | |
327 | l = get_conf_long(d, where + PCI_IOV_SYSPS); | |
328 | printf("System Page Size: %08x\n", l); | |
b9e11c65 MM |
329 | |
330 | for (i=0; i < PCI_IOV_NUM_BAR; i++) | |
331 | { | |
187bf2f5 | 332 | u32 addr; |
b9e11c65 MM |
333 | int type; |
334 | u32 h; | |
335 | l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i); | |
336 | if (l == 0xffffffff) | |
337 | l = 0; | |
338 | if (!l) | |
339 | continue; | |
340 | printf("\t\tRegion %d: Memory at ", i); | |
341 | addr = l & PCI_ADDR_MEM_MASK; | |
342 | type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK; | |
343 | if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) | |
344 | { | |
345 | i++; | |
346 | h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4)); | |
187bf2f5 | 347 | printf("%08x", h); |
b9e11c65 | 348 | } |
187bf2f5 MM |
349 | printf("%08x (%s-bit, %sprefetchable)\n", |
350 | addr, | |
b9e11c65 MM |
351 | (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64", |
352 | (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-"); | |
67e78b32 | 353 | } |
b9e11c65 | 354 | |
edca3520 | 355 | l = get_conf_long(d, where + PCI_IOV_MSAO); |
c7a34993 MM |
356 | printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l), |
357 | PCI_IOV_MSA_BIR(l)); | |
358 | } | |
359 | ||
33088c24 MM |
360 | static void |
361 | cap_vc(struct device *d, int where) | |
362 | { | |
363 | u32 cr1, cr2; | |
364 | u16 ctrl, status; | |
365 | int evc_cnt; | |
366 | int arb_table_pos; | |
367 | int i, j; | |
3d8b5258 | 368 | static const char ref_clocks[][6] = { "100ns" }; |
3edae14a MM |
369 | static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" }; |
370 | static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" }; | |
3d8b5258 | 371 | char buf[8]; |
33088c24 MM |
372 | |
373 | printf("Virtual Channel\n"); | |
374 | if (verbose < 2) | |
375 | return; | |
376 | ||
377 | if (!config_fetch(d, where + 4, 0x1c - 4)) | |
378 | return; | |
379 | ||
380 | cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1); | |
381 | cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2); | |
382 | ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL); | |
383 | status = get_conf_word(d, where + PCI_VC_PORT_STATUS); | |
384 | ||
3d8b5258 | 385 | evc_cnt = BITS(cr1, 0, 3); |
d676f20d | 386 | printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n", |
3d8b5258 MM |
387 | BITS(cr1, 4, 3), |
388 | TABLE(ref_clocks, BITS(cr1, 8, 2), buf), | |
d676f20d | 389 | 1 << BITS(cr1, 10, 2)); |
33088c24 | 390 | |
d676f20d | 391 | printf("\t\tArb:"); |
33088c24 MM |
392 | for (i=0; i<8; i++) |
393 | if (arb_selects[i][0] != '?' || cr2 & (1 << i)) | |
d676f20d | 394 | printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i)); |
3d8b5258 | 395 | arb_table_pos = BITS(cr2, 24, 8); |
33088c24 | 396 | |
d676f20d | 397 | printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf)); |
33088c24 MM |
398 | printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1)); |
399 | ||
400 | if (arb_table_pos) | |
d676f20d MM |
401 | { |
402 | arb_table_pos = where + 16*arb_table_pos; | |
403 | printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos); | |
404 | } | |
33088c24 MM |
405 | |
406 | for (i=0; i<=evc_cnt; i++) | |
407 | { | |
408 | int pos = where + PCI_VC_RES_CAP + 12*i; | |
409 | u32 rcap, rctrl; | |
410 | u16 rstatus; | |
411 | int pat_pos; | |
412 | ||
5a9a932c | 413 | printf("\t\tVC%d:\t", i); |
33088c24 MM |
414 | if (!config_fetch(d, pos, 12)) |
415 | { | |
5a9a932c | 416 | printf("<unreadable>\n"); |
33088c24 MM |
417 | continue; |
418 | } | |
419 | rcap = get_conf_long(d, pos); | |
420 | rctrl = get_conf_long(d, pos+4); | |
7970509b | 421 | rstatus = get_conf_word(d, pos+10); |
33088c24 | 422 | |
3d8b5258 | 423 | pat_pos = BITS(rcap, 24, 8); |
5a9a932c | 424 | printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n", |
33088c24 | 425 | pat_pos, |
3d8b5258 | 426 | BITS(rcap, 16, 6) + 1, |
33088c24 MM |
427 | FLAG(rcap, 1 << 15)); |
428 | ||
429 | printf("\t\t\tArb:"); | |
430 | for (j=0; j<8; j++) | |
431 | if (vc_arb_selects[j][0] != '?' || rcap & (1 << j)) | |
432 | printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j)); | |
433 | ||
434 | printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n", | |
435 | FLAG(rctrl, 1 << 31), | |
3d8b5258 MM |
436 | BITS(rctrl, 24, 3), |
437 | TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf), | |
438 | BITS(rctrl, 0, 8)); | |
33088c24 MM |
439 | |
440 | printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n", | |
441 | FLAG(rstatus, 2), | |
442 | FLAG(rstatus, 1)); | |
443 | ||
444 | if (pat_pos) | |
445 | printf("\t\t\tPort Arbitration Table <?>\n"); | |
446 | } | |
447 | } | |
448 | ||
5a9a932c MM |
449 | static void |
450 | cap_rclink(struct device *d, int where) | |
451 | { | |
452 | u32 esd; | |
453 | int num_links; | |
454 | int i; | |
455 | static const char elt_types[][9] = { "Config", "Egress", "Internal" }; | |
456 | char buf[8]; | |
457 | ||
458 | printf("Root Complex Link\n"); | |
459 | if (verbose < 2) | |
460 | return; | |
461 | ||
462 | if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4)) | |
463 | return; | |
464 | ||
465 | esd = get_conf_long(d, where + PCI_RCLINK_ESD); | |
466 | num_links = BITS(esd, 8, 8); | |
467 | printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n", | |
468 | BITS(esd, 24, 8), | |
469 | BITS(esd, 16, 8), | |
470 | TABLE(elt_types, BITS(esd, 0, 8), buf)); | |
471 | ||
472 | for (i=0; i<num_links; i++) | |
473 | { | |
474 | int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE; | |
475 | u32 desc; | |
476 | u32 addr_lo, addr_hi; | |
477 | ||
478 | printf("\t\tLink%d:\t", i); | |
479 | if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE)) | |
480 | { | |
481 | printf("<unreadable>\n"); | |
482 | return; | |
483 | } | |
484 | desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC); | |
485 | addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR); | |
486 | addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4); | |
487 | ||
488 | printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n", | |
489 | BITS(desc, 24, 8), | |
490 | BITS(desc, 16, 8), | |
491 | FLAG(desc, 4), | |
492 | ((desc & 2) ? "Config" : "MemMapped"), | |
493 | FLAG(desc, 1)); | |
494 | ||
495 | if (desc & 2) | |
496 | { | |
497 | int n = addr_lo & 7; | |
498 | if (!n) | |
499 | n = 8; | |
500 | printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n", | |
501 | BITS(addr_lo, 20, n), | |
502 | BITS(addr_lo, 15, 5), | |
503 | BITS(addr_lo, 12, 3), | |
504 | addr_hi, addr_lo); | |
505 | } | |
506 | else | |
507 | printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo); | |
508 | } | |
509 | } | |
510 | ||
78ca9582 MM |
511 | static void |
512 | cap_evendor(struct device *d, int where) | |
513 | { | |
514 | u32 hdr; | |
515 | ||
516 | printf("Vendor Specific Information: "); | |
517 | if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4)) | |
518 | { | |
519 | printf("<unreadable>\n"); | |
520 | return; | |
521 | } | |
522 | ||
523 | hdr = get_conf_long(d, where + PCI_EVNDR_HEADER); | |
524 | printf("ID=%04x Rev=%d Len=%03x <?>\n", | |
525 | BITS(hdr, 0, 16), | |
526 | BITS(hdr, 16, 4), | |
527 | BITS(hdr, 20, 12)); | |
528 | } | |
529 | ||
fb17077d | 530 | static int l1pm_calc_pwron(int scale, int value) |
8efbe075 RJ |
531 | { |
532 | switch (scale) | |
533 | { | |
534 | case 0: | |
535 | return 2 * value; | |
536 | case 1: | |
537 | return 10 * value; | |
538 | case 2: | |
539 | return 100 * value; | |
540 | } | |
541 | return -1; | |
542 | } | |
543 | ||
214c9a95 DB |
544 | static void |
545 | cap_l1pm(struct device *d, int where) | |
546 | { | |
8efbe075 RJ |
547 | u32 l1_cap, val, scale; |
548 | int time; | |
214c9a95 DB |
549 | |
550 | printf("L1 PM Substates\n"); | |
551 | ||
552 | if (verbose < 2) | |
553 | return; | |
554 | ||
8efbe075 | 555 | if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12)) |
214c9a95 DB |
556 | { |
557 | printf("\t\t<unreadable>\n"); | |
558 | return; | |
559 | } | |
560 | ||
8efbe075 | 561 | l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP); |
214c9a95 | 562 | printf("\t\tL1SubCap: "); |
e495466c | 563 | printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n", |
8efbe075 RJ |
564 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12), |
565 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11), | |
566 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12), | |
567 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11), | |
568 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP)); | |
569 | ||
fb17077d | 570 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) |
214c9a95 | 571 | { |
fb17077d | 572 | printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8)); |
8efbe075 RJ |
573 | time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5)); |
574 | if (time != -1) | |
575 | printf("PortTPowerOnTime=%dus\n", time); | |
576 | else | |
577 | printf("PortTPowerOnTime=<error>\n"); | |
578 | } | |
214c9a95 | 579 | |
8efbe075 | 580 | val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1); |
fb17077d | 581 | printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n", |
8efbe075 RJ |
582 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12), |
583 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11), | |
584 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12), | |
585 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11)); | |
586 | ||
fb17077d MM |
587 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) |
588 | printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8)); | |
8efbe075 RJ |
589 | |
590 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) | |
591 | { | |
592 | scale = BITS(val, 29, 3); | |
593 | if (scale > 5) | |
fb17077d | 594 | printf(" LTR1.2_Threshold=<error>"); |
8efbe075 | 595 | else |
fb17077d | 596 | printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale)); |
8efbe075 | 597 | } |
fb17077d | 598 | printf("\n"); |
8efbe075 RJ |
599 | |
600 | val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2); | |
fb17077d MM |
601 | printf("\t\tL1SubCtl2:"); |
602 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) | |
8efbe075 RJ |
603 | { |
604 | time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5)); | |
605 | if (time != -1) | |
fb17077d | 606 | printf(" T_PwrOn=%dus", time); |
8efbe075 | 607 | else |
fb17077d | 608 | printf(" T_PwrOn=<error>"); |
214c9a95 | 609 | } |
fb17077d | 610 | printf("\n"); |
214c9a95 DB |
611 | } |
612 | ||
415a9c18 YJ |
613 | static void |
614 | cap_ptm(struct device *d, int where) | |
615 | { | |
616 | u32 buff; | |
617 | u16 clock; | |
618 | ||
619 | printf("Precision Time Measurement\n"); | |
620 | ||
621 | if (verbose < 2) | |
622 | return; | |
623 | ||
624 | if (!config_fetch(d, where + 4, 8)) | |
625 | { | |
626 | printf("\t\t<unreadable>\n"); | |
627 | return; | |
628 | } | |
629 | ||
630 | buff = get_conf_long(d, where + 4); | |
631 | printf("\t\tPTMCap: "); | |
632 | printf("Requester:%c Responder:%c Root:%c\n", | |
633 | FLAG(buff, 0x1), | |
634 | FLAG(buff, 0x2), | |
635 | FLAG(buff, 0x4)); | |
636 | ||
637 | clock = BITS(buff, 8, 8); | |
638 | printf("\t\tPTMClockGranularity: "); | |
639 | switch (clock) | |
640 | { | |
641 | case 0x00: | |
642 | printf("Unimplemented\n"); | |
643 | break; | |
644 | case 0xff: | |
645 | printf("Greater than 254ns\n"); | |
646 | break; | |
647 | default: | |
648 | printf("%huns\n", clock); | |
649 | } | |
650 | ||
651 | buff = get_conf_long(d, where + 8); | |
652 | printf("\t\tPTMControl: "); | |
653 | printf("Enabled:%c RootSelected:%c\n", | |
654 | FLAG(buff, 0x1), | |
655 | FLAG(buff, 0x2)); | |
656 | ||
657 | clock = BITS(buff, 8, 8); | |
658 | printf("\t\tPTMEffectiveGranularity: "); | |
659 | switch (clock) | |
660 | { | |
661 | case 0x00: | |
662 | printf("Unknown\n"); | |
663 | break; | |
664 | case 0xff: | |
665 | printf("Greater than 254ns\n"); | |
666 | break; | |
667 | default: | |
668 | printf("%huns\n", clock); | |
669 | } | |
670 | } | |
671 | ||
c7a34993 MM |
672 | void |
673 | show_ext_caps(struct device *d) | |
674 | { | |
675 | int where = 0x100; | |
676 | char been_there[0x1000]; | |
677 | memset(been_there, 0, 0x1000); | |
678 | do | |
679 | { | |
680 | u32 header; | |
33088c24 | 681 | int id, version; |
c7a34993 MM |
682 | |
683 | if (!config_fetch(d, where, 4)) | |
684 | break; | |
685 | header = get_conf_long(d, where); | |
686 | if (!header) | |
687 | break; | |
688 | id = header & 0xffff; | |
33088c24 MM |
689 | version = (header >> 16) & 0xf; |
690 | printf("\tCapabilities: [%03x", where); | |
691 | if (verbose > 1) | |
692 | printf(" v%d", version); | |
693 | printf("] "); | |
c7a34993 MM |
694 | if (been_there[where]++) |
695 | { | |
696 | printf("<chain looped>\n"); | |
697 | break; | |
698 | } | |
699 | switch (id) | |
700 | { | |
701 | case PCI_EXT_CAP_ID_AER: | |
702 | cap_aer(d, where); | |
703 | break; | |
de91b6f2 KB |
704 | case PCI_EXT_CAP_ID_DPC: |
705 | cap_dpc(d, where); | |
706 | break; | |
c7a34993 | 707 | case PCI_EXT_CAP_ID_VC: |
33088c24 MM |
708 | case PCI_EXT_CAP_ID_VC2: |
709 | cap_vc(d, where); | |
c7a34993 MM |
710 | break; |
711 | case PCI_EXT_CAP_ID_DSN: | |
712 | cap_dsn(d, where); | |
713 | break; | |
714 | case PCI_EXT_CAP_ID_PB: | |
715 | printf("Power Budgeting <?>\n"); | |
716 | break; | |
717 | case PCI_EXT_CAP_ID_RCLINK: | |
5a9a932c | 718 | cap_rclink(d, where); |
c7a34993 MM |
719 | break; |
720 | case PCI_EXT_CAP_ID_RCILINK: | |
721 | printf("Root Complex Internal Link <?>\n"); | |
722 | break; | |
723 | case PCI_EXT_CAP_ID_RCECOLL: | |
724 | printf("Root Complex Event Collector <?>\n"); | |
725 | break; | |
726 | case PCI_EXT_CAP_ID_MFVC: | |
727 | printf("Multi-Function Virtual Channel <?>\n"); | |
728 | break; | |
729 | case PCI_EXT_CAP_ID_RBCB: | |
730 | printf("Root Bridge Control Block <?>\n"); | |
731 | break; | |
732 | case PCI_EXT_CAP_ID_VNDR: | |
78ca9582 | 733 | cap_evendor(d, where); |
c7a34993 MM |
734 | break; |
735 | case PCI_EXT_CAP_ID_ACS: | |
736 | cap_acs(d, where); | |
737 | break; | |
738 | case PCI_EXT_CAP_ID_ARI: | |
739 | cap_ari(d, where); | |
740 | break; | |
741 | case PCI_EXT_CAP_ID_ATS: | |
742 | cap_ats(d, where); | |
743 | break; | |
744 | case PCI_EXT_CAP_ID_SRIOV: | |
745 | cap_sriov(d, where); | |
746 | break; | |
a858df0d DW |
747 | case PCI_EXT_CAP_ID_PRI: |
748 | cap_pri(d, where); | |
749 | break; | |
67da1792 MM |
750 | case PCI_EXT_CAP_ID_TPH: |
751 | cap_tph(d, where); | |
752 | break; | |
753 | case PCI_EXT_CAP_ID_LTR: | |
754 | cap_ltr(d, where); | |
755 | break; | |
a858df0d DW |
756 | case PCI_EXT_CAP_ID_PASID: |
757 | cap_pasid(d, where); | |
758 | break; | |
214c9a95 DB |
759 | case PCI_EXT_CAP_ID_L1PM: |
760 | cap_l1pm(d, where); | |
761 | break; | |
415a9c18 YJ |
762 | case PCI_EXT_CAP_ID_PTM: |
763 | cap_ptm(d, where); | |
764 | break; | |
c7a34993 MM |
765 | default: |
766 | printf("#%02x\n", id); | |
767 | break; | |
768 | } | |
d61c4772 | 769 | where = (header >> 20) & ~3; |
c7a34993 MM |
770 | } while (where); |
771 | } |